2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #ifndef __JME_H_INCLUDED__
25 #define __JME_H_INCLUDEE__
27 #define DRV_NAME "jme"
28 #define DRV_VERSION "1.0.3"
29 #define PFX DRV_NAME ": "
31 #define PCI_DEVICE_ID_JMICRON_JMC250 0x0250
32 #define PCI_DEVICE_ID_JMICRON_JMC260 0x0260
35 * Message related definitions
37 #define JME_DEF_MSG_ENABLE \
44 #define jeprintk(pdev, fmt, args...) \
45 printk(KERN_ERR PFX fmt, ## args)
48 #define tx_dbg(priv, fmt, args...) \
49 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ## args)
51 #define tx_dbg(priv, fmt, args...)
54 #define jme_msg(msglvl, type, priv, fmt, args...) \
55 if (netif_msg_##type(priv)) \
56 printk(msglvl "%s: " fmt, (priv)->dev->name, ## args)
58 #define msg_probe(priv, fmt, args...) \
59 jme_msg(KERN_INFO, probe, priv, fmt, ## args)
61 #define msg_link(priv, fmt, args...) \
62 jme_msg(KERN_INFO, link, priv, fmt, ## args)
64 #define msg_intr(priv, fmt, args...) \
65 jme_msg(KERN_INFO, intr, priv, fmt, ## args)
67 #define msg_rx_err(priv, fmt, args...) \
68 jme_msg(KERN_ERR, rx_err, priv, fmt, ## args)
70 #define msg_rx_status(priv, fmt, args...) \
71 jme_msg(KERN_INFO, rx_status, priv, fmt, ## args)
73 #define msg_tx_err(priv, fmt, args...) \
74 jme_msg(KERN_ERR, tx_err, priv, fmt, ## args)
76 #define msg_tx_done(priv, fmt, args...) \
77 jme_msg(KERN_INFO, tx_done, priv, fmt, ## args)
79 #define msg_tx_queued(priv, fmt, args...) \
80 jme_msg(KERN_INFO, tx_queued, priv, fmt, ## args)
82 #define msg_hw(priv, fmt, args...) \
83 jme_msg(KERN_ERR, hw, priv, fmt, ## args)
86 * Extra PCI Configuration space interface
88 #define PCI_DCSR_MRRS 0x59
89 #define PCI_DCSR_MRRS_MASK 0x70
91 enum pci_dcsr_mrrs_vals
{
113 __u8 wn
; /* Number of write actions */
114 __u8 rn
; /* Number of read actions */
115 __u8 bitn
; /* Number of bits per action */
116 __u8 spd
; /* The maxim acceptable speed of controller, in MHz.*/
117 __u8 mode
; /* CPOL, CPHA, and Duplex mode of SPI */
119 /* Internal use only */
123 u16 halfclk
; /* Half of clock cycle calculated from spd, in ns */
126 enum jme_spi_op_bits
{
127 SPI_MODE_CPHA
= 0x01,
128 SPI_MODE_CPOL
= 0x02,
132 #define HALF_US 500 /* 500 ns */
133 #define JMESPIIOCTL SIOCDEVPRIVATE
136 * Dynamic(adaptive)/Static PCC values
138 enum dynamic_pcc_values
{
155 unsigned long last_bytes
;
156 unsigned long last_pkts
;
157 unsigned long intr_cnt
;
159 unsigned char attempt
;
162 #define PCC_INTERVAL_US 100000
163 #define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
164 #define PCC_P3_THRESHOLD (2 * 1024 * 1024)
165 #define PCC_P2_THRESHOLD 800
166 #define PCC_INTR_THRESHOLD 800
167 #define PCC_TX_TO 1000
173 * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
175 #define RING_DESC_ALIGN 16 /* Descriptor alignment */
176 #define TX_DESC_SIZE 16
178 #define TX_RING_ALLOC_SIZE(s) ((s * TX_DESC_SIZE) + RING_DESC_ALIGN)
238 enum jme_txdesc_flags_bits
{
249 #define TXDESC_MSS_SHIFT 2
250 enum jme_rxdescwb_flags_bits
{
253 TXWBFLAG_TMOUT
= 0x20,
254 TXWBFLAG_TRYOUT
= 0x10,
257 TXWBFLAG_ALLERR
= TXWBFLAG_TMOUT
|
262 #define RX_DESC_SIZE 16
264 #define RX_RING_ALLOC_SIZE(s) ((s * RX_DESC_SIZE) + RING_DESC_ALIGN)
265 #define RX_BUF_DMA_ALIGN 8
266 #define RX_PREPAD_SIZE 10
267 #define ETH_CRC_LEN 2
268 #define RX_VLANHDR_LEN 2
269 #define RX_EXTRA_LEN (RX_PREPAD_SIZE + \
316 enum jme_rxdesc_flags_bits
{
322 enum jme_rxwbdesc_flags_bits
{
323 RXWBFLAG_OWN
= 0x8000,
324 RXWBFLAG_INT
= 0x4000,
325 RXWBFLAG_MF
= 0x2000,
326 RXWBFLAG_64BIT
= 0x2000,
327 RXWBFLAG_TCPON
= 0x1000,
328 RXWBFLAG_UDPON
= 0x0800,
329 RXWBFLAG_IPCS
= 0x0400,
330 RXWBFLAG_TCPCS
= 0x0200,
331 RXWBFLAG_UDPCS
= 0x0100,
332 RXWBFLAG_TAGON
= 0x0080,
333 RXWBFLAG_IPV4
= 0x0040,
334 RXWBFLAG_IPV6
= 0x0020,
335 RXWBFLAG_PAUSE
= 0x0010,
336 RXWBFLAG_MAGIC
= 0x0008,
337 RXWBFLAG_WAKEUP
= 0x0004,
338 RXWBFLAG_DEST
= 0x0003,
339 RXWBFLAG_DEST_UNI
= 0x0001,
340 RXWBFLAG_DEST_MUL
= 0x0002,
341 RXWBFLAG_DEST_BRO
= 0x0003,
344 enum jme_rxwbdesc_desccnt_mask
{
345 RXWBDCNT_WBCPL
= 0x80,
346 RXWBDCNT_DCNT
= 0x7F,
349 enum jme_rxwbdesc_errstat_bits
{
350 RXWBERR_LIMIT
= 0x80,
351 RXWBERR_MIIER
= 0x40,
352 RXWBERR_NIBON
= 0x20,
353 RXWBERR_COLON
= 0x10,
354 RXWBERR_ABORT
= 0x08,
355 RXWBERR_SHORT
= 0x04,
356 RXWBERR_OVERUN
= 0x02,
357 RXWBERR_CRCERR
= 0x01,
358 RXWBERR_ALLERR
= 0xFF,
362 * Buffer information corresponding to ring descriptors.
364 struct jme_buffer_info
{
369 unsigned long start_xmit
;
373 * The structure holding buffer information and ring descriptors all together.
375 #define MAX_RING_DESC_NR 1024
377 void *alloc
; /* pointer to allocated memory */
378 void *desc
; /* pointer to ring memory */
379 dma_addr_t dmaalloc
; /* phys address of ring alloc */
380 dma_addr_t dma
; /* phys address for ring dma */
382 /* Buffer information corresponding to each descriptor */
383 struct jme_buffer_info bufinf
[MAX_RING_DESC_NR
];
386 atomic_t next_to_clean
;
390 #define NET_STAT(priv) (priv->dev->stats)
391 #define NETDEV_GET_STATS(netdev, fun_ptr)
392 #define DECLARE_NET_DEVICE_STATS
394 #define DECLARE_NAPI_STRUCT struct napi_struct napi;
395 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
396 netif_napi_add(dev, napis, pollfn, q);
397 #define JME_NAPI_HOLDER(holder) struct napi_struct *holder
398 #define JME_NAPI_WEIGHT(w) int w
399 #define JME_NAPI_WEIGHT_VAL(w) w
400 #define JME_NAPI_WEIGHT_SET(w, r)
401 #define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev, napis)
402 #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
403 #define JME_NAPI_DISABLE(priv) \
404 if (!napi_disable_pending(&priv->napi)) \
405 napi_disable(&priv->napi);
406 #define JME_RX_SCHEDULE_PREP(priv) \
407 netif_rx_schedule_prep(priv->dev, &priv->napi)
408 #define JME_RX_SCHEDULE(priv) \
409 __netif_rx_schedule(priv->dev, &priv->napi);
412 * Jmac Adapter Private data
414 #define SHADOW_REG_NR 8
416 struct pci_dev
*pdev
;
417 struct net_device
*dev
;
419 dma_addr_t shadow_dma
;
421 struct mii_if_info mii_if
;
422 struct jme_ring rxring
[RX_RING_NR
];
423 struct jme_ring txring
[TX_RING_NR
];
425 spinlock_t macaddr_lock
;
426 spinlock_t rxmcs_lock
;
427 struct tasklet_struct rxempty_task
;
428 struct tasklet_struct rxclean_task
;
429 struct tasklet_struct txclean_task
;
430 struct tasklet_struct linkch_task
;
431 struct tasklet_struct pcc_task
;
442 u32 tx_wake_threshold
;
446 unsigned int fpgaver
;
447 unsigned int chiprev
;
450 struct ethtool_cmd old_ecmd
;
451 unsigned int old_mtu
;
452 struct vlan_group
*vlgrp
;
453 struct dynpcc_info dpi
;
455 atomic_t link_changing
;
456 atomic_t tx_cleaning
;
457 atomic_t rx_cleaning
;
459 int (*jme_rx
)(struct sk_buff
*skb
);
460 int (*jme_vlan_rx
)(struct sk_buff
*skb
,
461 struct vlan_group
*grp
,
462 unsigned short vlan_tag
);
464 DECLARE_NET_DEVICE_STATS
467 enum shadow_reg_val
{
471 enum jme_flags_bits
{
477 JME_FLAG_SHUTDOWN
= 6,
480 #define TX_TIMEOUT (5 * HZ)
481 #define JME_REG_LEN 0x500
482 #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
484 static inline struct jme_adapter
*
485 jme_napi_priv(struct napi_struct
*napi
)
487 struct jme_adapter
*jme
;
488 jme
= container_of(napi
, struct jme_adapter
, napi
);
495 enum jme_iomap_offsets
{
502 enum jme_iomap_lens
{
509 enum jme_iomap_regs
{
510 JME_TXCS
= JME_MAC
| 0x00, /* Transmit Control and Status */
511 JME_TXDBA_LO
= JME_MAC
| 0x04, /* Transmit Queue Desc Base Addr */
512 JME_TXDBA_HI
= JME_MAC
| 0x08, /* Transmit Queue Desc Base Addr */
513 JME_TXQDC
= JME_MAC
| 0x0C, /* Transmit Queue Desc Count */
514 JME_TXNDA
= JME_MAC
| 0x10, /* Transmit Queue Next Desc Addr */
515 JME_TXMCS
= JME_MAC
| 0x14, /* Transmit MAC Control Status */
516 JME_TXPFC
= JME_MAC
| 0x18, /* Transmit Pause Frame Control */
517 JME_TXTRHD
= JME_MAC
| 0x1C, /* Transmit Timer/Retry@Half-Dup */
519 JME_RXCS
= JME_MAC
| 0x20, /* Receive Control and Status */
520 JME_RXDBA_LO
= JME_MAC
| 0x24, /* Receive Queue Desc Base Addr */
521 JME_RXDBA_HI
= JME_MAC
| 0x28, /* Receive Queue Desc Base Addr */
522 JME_RXQDC
= JME_MAC
| 0x2C, /* Receive Queue Desc Count */
523 JME_RXNDA
= JME_MAC
| 0x30, /* Receive Queue Next Desc Addr */
524 JME_RXMCS
= JME_MAC
| 0x34, /* Receive MAC Control Status */
525 JME_RXUMA_LO
= JME_MAC
| 0x38, /* Receive Unicast MAC Address */
526 JME_RXUMA_HI
= JME_MAC
| 0x3C, /* Receive Unicast MAC Address */
527 JME_RXMCHT_LO
= JME_MAC
| 0x40, /* Recv Multicast Addr HashTable */
528 JME_RXMCHT_HI
= JME_MAC
| 0x44, /* Recv Multicast Addr HashTable */
529 JME_WFODP
= JME_MAC
| 0x48, /* Wakeup Frame Output Data Port */
530 JME_WFOI
= JME_MAC
| 0x4C, /* Wakeup Frame Output Interface */
532 JME_SMI
= JME_MAC
| 0x50, /* Station Management Interface */
533 JME_GHC
= JME_MAC
| 0x54, /* Global Host Control */
534 JME_PMCS
= JME_MAC
| 0x60, /* Power Management Control/Stat */
537 JME_PHY_CS
= JME_PHY
| 0x28, /* PHY Ctrl and Status Register */
538 JME_PHY_LINK
= JME_PHY
| 0x30, /* PHY Link Status Register */
539 JME_SMBCSR
= JME_PHY
| 0x40, /* SMB Control and Status */
540 JME_SMBINTF
= JME_PHY
| 0x44, /* SMB Interface */
543 JME_TMCSR
= JME_MISC
| 0x00, /* Timer Control/Status Register */
544 JME_GPREG0
= JME_MISC
| 0x08, /* General purpose REG-0 */
545 JME_GPREG1
= JME_MISC
| 0x0C, /* General purpose REG-1 */
546 JME_IEVE
= JME_MISC
| 0x20, /* Interrupt Event Status */
547 JME_IREQ
= JME_MISC
| 0x24, /* Intr Req Status(For Debug) */
548 JME_IENS
= JME_MISC
| 0x28, /* Intr Enable - Setting Port */
549 JME_IENC
= JME_MISC
| 0x2C, /* Interrupt Enable - Clear Port */
550 JME_PCCRX0
= JME_MISC
| 0x30, /* PCC Control for RX Queue 0 */
551 JME_PCCTX
= JME_MISC
| 0x40, /* PCC Control for TX Queues */
552 JME_CHIPMODE
= JME_MISC
| 0x44, /* Identify FPGA Version */
553 JME_SHBA_HI
= JME_MISC
| 0x48, /* Shadow Register Base HI */
554 JME_SHBA_LO
= JME_MISC
| 0x4C, /* Shadow Register Base LO */
555 JME_TIMER1
= JME_MISC
| 0x70, /* Timer1 */
556 JME_TIMER2
= JME_MISC
| 0x74, /* Timer2 */
557 JME_APMC
= JME_MISC
| 0x7C, /* Aggressive Power Mode Control */
558 JME_PCCSRX0
= JME_MISC
| 0x80, /* PCC Status of RX0 */
562 * TX Control/Status Bits
565 TXCS_QUEUE7S
= 0x00008000,
566 TXCS_QUEUE6S
= 0x00004000,
567 TXCS_QUEUE5S
= 0x00002000,
568 TXCS_QUEUE4S
= 0x00001000,
569 TXCS_QUEUE3S
= 0x00000800,
570 TXCS_QUEUE2S
= 0x00000400,
571 TXCS_QUEUE1S
= 0x00000200,
572 TXCS_QUEUE0S
= 0x00000100,
573 TXCS_FIFOTH
= 0x000000C0,
574 TXCS_DMASIZE
= 0x00000030,
575 TXCS_BURST
= 0x00000004,
576 TXCS_ENABLE
= 0x00000001,
579 enum jme_txcs_value
{
580 TXCS_FIFOTH_16QW
= 0x000000C0,
581 TXCS_FIFOTH_12QW
= 0x00000080,
582 TXCS_FIFOTH_8QW
= 0x00000040,
583 TXCS_FIFOTH_4QW
= 0x00000000,
585 TXCS_DMASIZE_64B
= 0x00000000,
586 TXCS_DMASIZE_128B
= 0x00000010,
587 TXCS_DMASIZE_256B
= 0x00000020,
588 TXCS_DMASIZE_512B
= 0x00000030,
590 TXCS_SELECT_QUEUE0
= 0x00000000,
591 TXCS_SELECT_QUEUE1
= 0x00010000,
592 TXCS_SELECT_QUEUE2
= 0x00020000,
593 TXCS_SELECT_QUEUE3
= 0x00030000,
594 TXCS_SELECT_QUEUE4
= 0x00040000,
595 TXCS_SELECT_QUEUE5
= 0x00050000,
596 TXCS_SELECT_QUEUE6
= 0x00060000,
597 TXCS_SELECT_QUEUE7
= 0x00070000,
599 TXCS_DEFAULT
= TXCS_FIFOTH_4QW
|
603 #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
606 * TX MAC Control/Status Bits
608 enum jme_txmcs_bit_masks
{
609 TXMCS_IFG2
= 0xC0000000,
610 TXMCS_IFG1
= 0x30000000,
611 TXMCS_TTHOLD
= 0x00000300,
612 TXMCS_FBURST
= 0x00000080,
613 TXMCS_CARRIEREXT
= 0x00000040,
614 TXMCS_DEFER
= 0x00000020,
615 TXMCS_BACKOFF
= 0x00000010,
616 TXMCS_CARRIERSENSE
= 0x00000008,
617 TXMCS_COLLISION
= 0x00000004,
618 TXMCS_CRC
= 0x00000002,
619 TXMCS_PADDING
= 0x00000001,
622 enum jme_txmcs_values
{
623 TXMCS_IFG2_6_4
= 0x00000000,
624 TXMCS_IFG2_8_5
= 0x40000000,
625 TXMCS_IFG2_10_6
= 0x80000000,
626 TXMCS_IFG2_12_7
= 0xC0000000,
628 TXMCS_IFG1_8_4
= 0x00000000,
629 TXMCS_IFG1_12_6
= 0x10000000,
630 TXMCS_IFG1_16_8
= 0x20000000,
631 TXMCS_IFG1_20_10
= 0x30000000,
633 TXMCS_TTHOLD_1_8
= 0x00000000,
634 TXMCS_TTHOLD_1_4
= 0x00000100,
635 TXMCS_TTHOLD_1_2
= 0x00000200,
636 TXMCS_TTHOLD_FULL
= 0x00000300,
638 TXMCS_DEFAULT
= TXMCS_IFG2_8_5
|
646 enum jme_txpfc_bits_masks
{
647 TXPFC_VLAN_TAG
= 0xFFFF0000,
648 TXPFC_VLAN_EN
= 0x00008000,
649 TXPFC_PF_EN
= 0x00000001,
652 enum jme_txtrhd_bits_masks
{
653 TXTRHD_TXPEN
= 0x80000000,
654 TXTRHD_TXP
= 0x7FFFFF00,
655 TXTRHD_TXREN
= 0x00000080,
656 TXTRHD_TXRL
= 0x0000007F,
659 enum jme_txtrhd_shifts
{
660 TXTRHD_TXP_SHIFT
= 8,
661 TXTRHD_TXRL_SHIFT
= 0,
665 * RX Control/Status Bits
667 enum jme_rxcs_bit_masks
{
668 /* FIFO full threshold for transmitting Tx Pause Packet */
669 RXCS_FIFOTHTP
= 0x30000000,
670 /* FIFO threshold for processing next packet */
671 RXCS_FIFOTHNP
= 0x0C000000,
672 RXCS_DMAREQSZ
= 0x03000000, /* DMA Request Size */
673 RXCS_QUEUESEL
= 0x00030000, /* Queue selection */
674 RXCS_RETRYGAP
= 0x0000F000, /* RX Desc full retry gap */
675 RXCS_RETRYCNT
= 0x00000F00, /* RX Desc full retry counter */
676 RXCS_WAKEUP
= 0x00000040, /* Enable receive wakeup packet */
677 RXCS_MAGIC
= 0x00000020, /* Enable receive magic packet */
678 RXCS_SHORT
= 0x00000010, /* Enable receive short packet */
679 RXCS_ABORT
= 0x00000008, /* Enable receive errorr packet */
680 RXCS_QST
= 0x00000004, /* Receive queue start */
681 RXCS_SUSPEND
= 0x00000002,
682 RXCS_ENABLE
= 0x00000001,
685 enum jme_rxcs_values
{
686 RXCS_FIFOTHTP_16T
= 0x00000000,
687 RXCS_FIFOTHTP_32T
= 0x10000000,
688 RXCS_FIFOTHTP_64T
= 0x20000000,
689 RXCS_FIFOTHTP_128T
= 0x30000000,
691 RXCS_FIFOTHNP_16QW
= 0x00000000,
692 RXCS_FIFOTHNP_32QW
= 0x04000000,
693 RXCS_FIFOTHNP_64QW
= 0x08000000,
694 RXCS_FIFOTHNP_128QW
= 0x0C000000,
696 RXCS_DMAREQSZ_16B
= 0x00000000,
697 RXCS_DMAREQSZ_32B
= 0x01000000,
698 RXCS_DMAREQSZ_64B
= 0x02000000,
699 RXCS_DMAREQSZ_128B
= 0x03000000,
701 RXCS_QUEUESEL_Q0
= 0x00000000,
702 RXCS_QUEUESEL_Q1
= 0x00010000,
703 RXCS_QUEUESEL_Q2
= 0x00020000,
704 RXCS_QUEUESEL_Q3
= 0x00030000,
706 RXCS_RETRYGAP_256ns
= 0x00000000,
707 RXCS_RETRYGAP_512ns
= 0x00001000,
708 RXCS_RETRYGAP_1024ns
= 0x00002000,
709 RXCS_RETRYGAP_2048ns
= 0x00003000,
710 RXCS_RETRYGAP_4096ns
= 0x00004000,
711 RXCS_RETRYGAP_8192ns
= 0x00005000,
712 RXCS_RETRYGAP_16384ns
= 0x00006000,
713 RXCS_RETRYGAP_32768ns
= 0x00007000,
715 RXCS_RETRYCNT_0
= 0x00000000,
716 RXCS_RETRYCNT_4
= 0x00000100,
717 RXCS_RETRYCNT_8
= 0x00000200,
718 RXCS_RETRYCNT_12
= 0x00000300,
719 RXCS_RETRYCNT_16
= 0x00000400,
720 RXCS_RETRYCNT_20
= 0x00000500,
721 RXCS_RETRYCNT_24
= 0x00000600,
722 RXCS_RETRYCNT_28
= 0x00000700,
723 RXCS_RETRYCNT_32
= 0x00000800,
724 RXCS_RETRYCNT_36
= 0x00000900,
725 RXCS_RETRYCNT_40
= 0x00000A00,
726 RXCS_RETRYCNT_44
= 0x00000B00,
727 RXCS_RETRYCNT_48
= 0x00000C00,
728 RXCS_RETRYCNT_52
= 0x00000D00,
729 RXCS_RETRYCNT_56
= 0x00000E00,
730 RXCS_RETRYCNT_60
= 0x00000F00,
732 RXCS_DEFAULT
= RXCS_FIFOTHTP_128T
|
733 RXCS_FIFOTHNP_128QW
|
735 RXCS_RETRYGAP_256ns
|
739 #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
742 * RX MAC Control/Status Bits
744 enum jme_rxmcs_bits
{
745 RXMCS_ALLFRAME
= 0x00000800,
746 RXMCS_BRDFRAME
= 0x00000400,
747 RXMCS_MULFRAME
= 0x00000200,
748 RXMCS_UNIFRAME
= 0x00000100,
749 RXMCS_ALLMULFRAME
= 0x00000080,
750 RXMCS_MULFILTERED
= 0x00000040,
751 RXMCS_RXCOLLDEC
= 0x00000020,
752 RXMCS_FLOWCTRL
= 0x00000008,
753 RXMCS_VTAGRM
= 0x00000004,
754 RXMCS_PREPAD
= 0x00000002,
755 RXMCS_CHECKSUM
= 0x00000001,
757 RXMCS_DEFAULT
= RXMCS_VTAGRM
|
764 * Wakeup Frame setup interface registers
766 #define WAKEUP_FRAME_NR 8
767 #define WAKEUP_FRAME_MASK_DWNR 4
769 enum jme_wfoi_bit_masks
{
770 WFOI_MASK_SEL
= 0x00000070,
771 WFOI_CRC_SEL
= 0x00000008,
772 WFOI_FRAME_SEL
= 0x00000007,
775 enum jme_wfoi_shifts
{
780 * SMI Related definitions
782 enum jme_smi_bit_mask
{
783 SMI_DATA_MASK
= 0xFFFF0000,
784 SMI_REG_ADDR_MASK
= 0x0000F800,
785 SMI_PHY_ADDR_MASK
= 0x000007C0,
786 SMI_OP_WRITE
= 0x00000020,
787 /* Set to 1, after req done it'll be cleared to 0 */
788 SMI_OP_REQ
= 0x00000010,
789 SMI_OP_MDIO
= 0x00000008, /* Software assess In/Out */
790 SMI_OP_MDOE
= 0x00000004, /* Software Output Enable */
791 SMI_OP_MDC
= 0x00000002, /* Software CLK Control */
792 SMI_OP_MDEN
= 0x00000001, /* Software access Enable */
795 enum jme_smi_bit_shift
{
797 SMI_REG_ADDR_SHIFT
= 11,
798 SMI_PHY_ADDR_SHIFT
= 6,
801 static inline u32
smi_reg_addr(int x
)
803 return (x
<< SMI_REG_ADDR_SHIFT
) & SMI_REG_ADDR_MASK
;
806 static inline u32
smi_phy_addr(int x
)
808 return (x
<< SMI_PHY_ADDR_SHIFT
) & SMI_PHY_ADDR_MASK
;
811 #define JME_PHY_TIMEOUT 100 /* 100 msec */
812 #define JME_PHY_REG_NR 32
815 * Global Host Control
817 enum jme_ghc_bit_mask
{
818 GHC_SWRST
= 0x40000000,
819 GHC_DPX
= 0x00000040,
820 GHC_SPEED
= 0x00000030,
821 GHC_LINK_POLL
= 0x00000001,
824 enum jme_ghc_speed_val
{
825 GHC_SPEED_10M
= 0x00000010,
826 GHC_SPEED_100M
= 0x00000020,
827 GHC_SPEED_1000M
= 0x00000030,
830 enum jme_ghc_to_clk
{
831 GHC_TO_CLK_OFF
= 0x00000000,
832 GHC_TO_CLK_GPHY
= 0x00400000,
833 GHC_TO_CLK_PCIE
= 0x00800000,
834 GHC_TO_CLK_INVALID
= 0x00C00000,
837 enum jme_ghc_txmac_clk
{
838 GHC_TXMAC_CLK_OFF
= 0x00000000,
839 GHC_TXMAC_CLK_GPHY
= 0x00100000,
840 GHC_TXMAC_CLK_PCIE
= 0x00200000,
841 GHC_TXMAC_CLK_INVALID
= 0x00300000,
845 * Power management control and status register
847 enum jme_pmcs_bit_masks
{
848 PMCS_WF7DET
= 0x80000000,
849 PMCS_WF6DET
= 0x40000000,
850 PMCS_WF5DET
= 0x20000000,
851 PMCS_WF4DET
= 0x10000000,
852 PMCS_WF3DET
= 0x08000000,
853 PMCS_WF2DET
= 0x04000000,
854 PMCS_WF1DET
= 0x02000000,
855 PMCS_WF0DET
= 0x01000000,
856 PMCS_LFDET
= 0x00040000,
857 PMCS_LRDET
= 0x00020000,
858 PMCS_MFDET
= 0x00010000,
859 PMCS_WF7EN
= 0x00008000,
860 PMCS_WF6EN
= 0x00004000,
861 PMCS_WF5EN
= 0x00002000,
862 PMCS_WF4EN
= 0x00001000,
863 PMCS_WF3EN
= 0x00000800,
864 PMCS_WF2EN
= 0x00000400,
865 PMCS_WF1EN
= 0x00000200,
866 PMCS_WF0EN
= 0x00000100,
867 PMCS_LFEN
= 0x00000004,
868 PMCS_LREN
= 0x00000002,
869 PMCS_MFEN
= 0x00000001,
873 * Giga PHY Status Registers
875 enum jme_phy_link_bit_mask
{
876 PHY_LINK_SPEED_MASK
= 0x0000C000,
877 PHY_LINK_DUPLEX
= 0x00002000,
878 PHY_LINK_SPEEDDPU_RESOLVED
= 0x00000800,
879 PHY_LINK_UP
= 0x00000400,
880 PHY_LINK_AUTONEG_COMPLETE
= 0x00000200,
881 PHY_LINK_MDI_STAT
= 0x00000040,
884 enum jme_phy_link_speed_val
{
885 PHY_LINK_SPEED_10M
= 0x00000000,
886 PHY_LINK_SPEED_100M
= 0x00004000,
887 PHY_LINK_SPEED_1000M
= 0x00008000,
890 #define JME_SPDRSV_TIMEOUT 500 /* 500 us */
893 * SMB Control and Status
895 enum jme_smbcsr_bit_mask
{
896 SMBCSR_CNACK
= 0x00020000,
897 SMBCSR_RELOAD
= 0x00010000,
898 SMBCSR_EEPROMD
= 0x00000020,
899 SMBCSR_INITDONE
= 0x00000010,
900 SMBCSR_BUSY
= 0x0000000F,
903 enum jme_smbintf_bit_mask
{
904 SMBINTF_HWDATR
= 0xFF000000,
905 SMBINTF_HWDATW
= 0x00FF0000,
906 SMBINTF_HWADDR
= 0x0000FF00,
907 SMBINTF_HWRWN
= 0x00000020,
908 SMBINTF_HWCMD
= 0x00000010,
909 SMBINTF_FASTM
= 0x00000008,
910 SMBINTF_GPIOSCL
= 0x00000004,
911 SMBINTF_GPIOSDA
= 0x00000002,
912 SMBINTF_GPIOEN
= 0x00000001,
915 enum jme_smbintf_vals
{
916 SMBINTF_HWRWN_READ
= 0x00000020,
917 SMBINTF_HWRWN_WRITE
= 0x00000000,
920 enum jme_smbintf_shifts
{
921 SMBINTF_HWDATR_SHIFT
= 24,
922 SMBINTF_HWDATW_SHIFT
= 16,
923 SMBINTF_HWADDR_SHIFT
= 8,
926 #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
927 #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
928 #define JME_SMB_LEN 256
929 #define JME_EEPROM_MAGIC 0x250
932 * Timer Control/Status Register
934 enum jme_tmcsr_bit_masks
{
935 TMCSR_SWIT
= 0x80000000,
936 TMCSR_EN
= 0x01000000,
937 TMCSR_CNT
= 0x00FFFFFF,
941 * General Purpose REG-0
943 enum jme_gpreg0_masks
{
944 GPREG0_DISSH
= 0xFF000000,
945 GPREG0_PCIRLMT
= 0x00300000,
946 GPREG0_PCCNOMUTCLR
= 0x00040000,
947 GPREG0_LNKINTPOLL
= 0x00001000,
948 GPREG0_PCCTMR
= 0x00000300,
949 GPREG0_PHYADDR
= 0x0000001F,
952 enum jme_gpreg0_vals
{
953 GPREG0_DISSH_DW7
= 0x80000000,
954 GPREG0_DISSH_DW6
= 0x40000000,
955 GPREG0_DISSH_DW5
= 0x20000000,
956 GPREG0_DISSH_DW4
= 0x10000000,
957 GPREG0_DISSH_DW3
= 0x08000000,
958 GPREG0_DISSH_DW2
= 0x04000000,
959 GPREG0_DISSH_DW1
= 0x02000000,
960 GPREG0_DISSH_DW0
= 0x01000000,
961 GPREG0_DISSH_ALL
= 0xFF000000,
963 GPREG0_PCIRLMT_8
= 0x00000000,
964 GPREG0_PCIRLMT_6
= 0x00100000,
965 GPREG0_PCIRLMT_5
= 0x00200000,
966 GPREG0_PCIRLMT_4
= 0x00300000,
968 GPREG0_PCCTMR_16ns
= 0x00000000,
969 GPREG0_PCCTMR_256ns
= 0x00000100,
970 GPREG0_PCCTMR_1us
= 0x00000200,
971 GPREG0_PCCTMR_1ms
= 0x00000300,
973 GPREG0_PHYADDR_1
= 0x00000001,
975 GPREG0_DEFAULT
= GPREG0_PCIRLMT_4
|
981 * General Purpose REG-1
982 * Note: All theses bits defined here are for
983 * Chip mode revision 0x11 only
985 enum jme_gpreg1_masks
{
986 GPREG1_INTRDELAYUNIT
= 0x00000018,
987 GPREG1_INTRDELAYENABLE
= 0x00000007,
990 enum jme_gpreg1_vals
{
991 GPREG1_RSSPATCH
= 0x00000040,
992 GPREG1_HALFMODEPATCH
= 0x00000020,
994 GPREG1_INTDLYUNIT_16NS
= 0x00000000,
995 GPREG1_INTDLYUNIT_256NS
= 0x00000008,
996 GPREG1_INTDLYUNIT_1US
= 0x00000010,
997 GPREG1_INTDLYUNIT_16US
= 0x00000018,
999 GPREG1_INTDLYEN_1U
= 0x00000001,
1000 GPREG1_INTDLYEN_2U
= 0x00000002,
1001 GPREG1_INTDLYEN_3U
= 0x00000003,
1002 GPREG1_INTDLYEN_4U
= 0x00000004,
1003 GPREG1_INTDLYEN_5U
= 0x00000005,
1004 GPREG1_INTDLYEN_6U
= 0x00000006,
1005 GPREG1_INTDLYEN_7U
= 0x00000007,
1007 GPREG1_DEFAULT
= 0x00000000,
1011 * Interrupt Status Bits
1013 enum jme_interrupt_bits
{
1014 INTR_SWINTR
= 0x80000000,
1015 INTR_TMINTR
= 0x40000000,
1016 INTR_LINKCH
= 0x20000000,
1017 INTR_PAUSERCV
= 0x10000000,
1018 INTR_MAGICRCV
= 0x08000000,
1019 INTR_WAKERCV
= 0x04000000,
1020 INTR_PCCRX0TO
= 0x02000000,
1021 INTR_PCCRX1TO
= 0x01000000,
1022 INTR_PCCRX2TO
= 0x00800000,
1023 INTR_PCCRX3TO
= 0x00400000,
1024 INTR_PCCTXTO
= 0x00200000,
1025 INTR_PCCRX0
= 0x00100000,
1026 INTR_PCCRX1
= 0x00080000,
1027 INTR_PCCRX2
= 0x00040000,
1028 INTR_PCCRX3
= 0x00020000,
1029 INTR_PCCTX
= 0x00010000,
1030 INTR_RX3EMP
= 0x00008000,
1031 INTR_RX2EMP
= 0x00004000,
1032 INTR_RX1EMP
= 0x00002000,
1033 INTR_RX0EMP
= 0x00001000,
1034 INTR_RX3
= 0x00000800,
1035 INTR_RX2
= 0x00000400,
1036 INTR_RX1
= 0x00000200,
1037 INTR_RX0
= 0x00000100,
1038 INTR_TX7
= 0x00000080,
1039 INTR_TX6
= 0x00000040,
1040 INTR_TX5
= 0x00000020,
1041 INTR_TX4
= 0x00000010,
1042 INTR_TX3
= 0x00000008,
1043 INTR_TX2
= 0x00000004,
1044 INTR_TX1
= 0x00000002,
1045 INTR_TX0
= 0x00000001,
1048 static const u32 INTR_ENABLE
= INTR_SWINTR
|
1058 * PCC Control Registers
1060 enum jme_pccrx_masks
{
1061 PCCRXTO_MASK
= 0xFFFF0000,
1062 PCCRX_MASK
= 0x0000FF00,
1065 enum jme_pcctx_masks
{
1066 PCCTXTO_MASK
= 0xFFFF0000,
1067 PCCTX_MASK
= 0x0000FF00,
1068 PCCTX_QS_MASK
= 0x000000FF,
1071 enum jme_pccrx_shifts
{
1076 enum jme_pcctx_shifts
{
1081 enum jme_pcctx_bits
{
1082 PCCTXQ0_EN
= 0x00000001,
1083 PCCTXQ1_EN
= 0x00000002,
1084 PCCTXQ2_EN
= 0x00000004,
1085 PCCTXQ3_EN
= 0x00000008,
1086 PCCTXQ4_EN
= 0x00000010,
1087 PCCTXQ5_EN
= 0x00000020,
1088 PCCTXQ6_EN
= 0x00000040,
1089 PCCTXQ7_EN
= 0x00000080,
1093 * Chip Mode Register
1095 enum jme_chipmode_bit_masks
{
1096 CM_FPGAVER_MASK
= 0xFFFF0000,
1097 CM_CHIPREV_MASK
= 0x0000FF00,
1098 CM_CHIPMODE_MASK
= 0x0000000F,
1101 enum jme_chipmode_shifts
{
1102 CM_FPGAVER_SHIFT
= 16,
1103 CM_CHIPREV_SHIFT
= 8,
1107 * Shadow base address register bits
1109 enum jme_shadow_base_address_bits
{
1114 * Aggressive Power Mode Control
1116 enum jme_apmc_bits
{
1117 JME_APMC_PCIE_SD_EN
= 0x40000000,
1118 JME_APMC_PSEUDO_HP_EN
= 0x20000000,
1119 JME_APMC_EPIEN
= 0x04000000,
1120 JME_APMC_EPIEN_CTRL
= 0x03000000,
1123 enum jme_apmc_values
{
1124 JME_APMC_EPIEN_CTRL_EN
= 0x02000000,
1125 JME_APMC_EPIEN_CTRL_DIS
= 0x01000000,
1128 #define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000)
1131 static char *MAC_REG_NAME
[] = {
1132 "JME_TXCS", "JME_TXDBA_LO", "JME_TXDBA_HI", "JME_TXQDC",
1133 "JME_TXNDA", "JME_TXMCS", "JME_TXPFC", "JME_TXTRHD",
1134 "JME_RXCS", "JME_RXDBA_LO", "JME_RXDBA_HI", "JME_RXQDC",
1135 "JME_RXNDA", "JME_RXMCS", "JME_RXUMA_LO", "JME_RXUMA_HI",
1136 "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP", "JME_WFOI",
1137 "JME_SMI", "JME_GHC", "UNKNOWN", "UNKNOWN",
1140 static char *PE_REG_NAME
[] = {
1141 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1142 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1143 "UNKNOWN", "UNKNOWN", "JME_PHY_CS", "UNKNOWN",
1144 "JME_PHY_LINK", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1145 "JME_SMBCSR", "JME_SMBINTF"};
1147 static char *MISC_REG_NAME
[] = {
1148 "JME_TMCSR", "JME_GPIO", "JME_GPREG0", "JME_GPREG1",
1149 "JME_IEVE", "JME_IREQ", "JME_IENS", "JME_IENC",
1150 "JME_PCCRX0", "JME_PCCRX1", "JME_PCCRX2", "JME_PCCRX3",
1151 "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO",
1152 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1153 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1154 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1155 "JME_TIMER1", "JME_TIMER2", "UNKNOWN", "JME_APMC",
1158 static inline void reg_dbg(const struct jme_adapter
*jme
,
1159 const char *msg
, u32 val
, u32 reg
)
1161 const char *regname
;
1162 switch (reg
& 0xF00) {
1164 regname
= MAC_REG_NAME
[(reg
& 0xFF) >> 2];
1167 regname
= PE_REG_NAME
[(reg
& 0xFF) >> 2];
1170 regname
= MISC_REG_NAME
[(reg
& 0xFF) >> 2];
1173 regname
= PE_REG_NAME
[0];
1175 printk(KERN_DEBUG
"%s: %-20s %08x@%s\n", jme
->dev
->name
,
1179 static inline void reg_dbg(const struct jme_adapter
*jme
,
1180 const char *msg
, u32 val
, u32 reg
) {}
1184 * Read/Write MMaped I/O Registers
1186 static inline u32
jread32(struct jme_adapter
*jme
, u32 reg
)
1188 return readl(jme
->regs
+ reg
);
1191 static inline void jwrite32(struct jme_adapter
*jme
, u32 reg
, u32 val
)
1193 reg_dbg(jme
, "REG WRITE", val
, reg
);
1194 writel(val
, jme
->regs
+ reg
);
1195 reg_dbg(jme
, "VAL AFTER WRITE", readl(jme
->regs
+ reg
), reg
);
1198 static inline void jwrite32f(struct jme_adapter
*jme
, u32 reg
, u32 val
)
1201 * Read after write should cause flush
1203 reg_dbg(jme
, "REG WRITE FLUSH", val
, reg
);
1204 writel(val
, jme
->regs
+ reg
);
1205 readl(jme
->regs
+ reg
);
1206 reg_dbg(jme
, "VAL AFTER WRITE", readl(jme
->regs
+ reg
), reg
);
1212 enum jme_phy_reg17_bit_masks
{
1213 PREG17_SPEED
= 0xC000,
1214 PREG17_DUPLEX
= 0x2000,
1215 PREG17_SPDRSV
= 0x0800,
1216 PREG17_LNKUP
= 0x0400,
1217 PREG17_MDI
= 0x0040,
1220 enum jme_phy_reg17_vals
{
1221 PREG17_SPEED_10M
= 0x0000,
1222 PREG17_SPEED_100M
= 0x4000,
1223 PREG17_SPEED_1000M
= 0x8000,
1226 #define BMSR_ANCOMP 0x0020
1231 static inline int is_buggy250(unsigned short device
, unsigned int chiprev
)
1233 return device
== PCI_DEVICE_ID_JMICRON_JMC250
&& chiprev
== 0x11;
1237 * Function prototypes
1239 static int jme_set_settings(struct net_device
*netdev
,
1240 struct ethtool_cmd
*ecmd
);
1241 static void jme_set_multi(struct net_device
*netdev
);