2 * Network device driver for the MACE ethernet controller on
3 * Apple Powermacs. Assumes it's under a DBDMA controller.
5 * Copyright (C) 1996 Paul Mackerras.
8 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/netdevice.h>
11 #include <linux/etherdevice.h>
12 #include <linux/delay.h>
13 #include <linux/string.h>
14 #include <linux/timer.h>
15 #include <linux/init.h>
16 #include <linux/crc32.h>
17 #include <linux/spinlock.h>
18 #include <linux/bitrev.h>
20 #include <asm/dbdma.h>
22 #include <asm/pgtable.h>
23 #include <asm/macio.h>
27 static int port_aaui
= -1;
31 #define MAX_TX_ACTIVE 1
32 #define NCMDS_TX 1 /* dma commands per element in tx ring */
33 #define RX_BUFLEN (ETH_FRAME_LEN + 8)
34 #define TX_TIMEOUT HZ /* 1 second */
36 /* Chip rev needs workaround on HW & multicast addr change */
37 #define BROKEN_ADDRCHG_REV 0x0941
39 /* Bits in transmit DMA status */
40 #define TX_DMA_ERR 0x80
43 volatile struct mace __iomem
*mace
;
44 volatile struct dbdma_regs __iomem
*tx_dma
;
46 volatile struct dbdma_regs __iomem
*rx_dma
;
48 volatile struct dbdma_cmd
*tx_cmds
; /* xmit dma command list */
49 volatile struct dbdma_cmd
*rx_cmds
; /* recv dma command list */
50 struct sk_buff
*rx_bufs
[N_RX_RING
];
53 struct sk_buff
*tx_bufs
[N_TX_RING
];
57 unsigned char tx_fullup
;
58 unsigned char tx_active
;
59 unsigned char tx_bad_runt
;
60 struct timer_list tx_timeout
;
64 struct macio_dev
*mdev
;
69 * Number of bytes of private data per MACE: allow enough for
70 * the rx and tx dma commands plus a branch dma command each,
71 * and another 16 bytes to allow us to align the dma command
72 * buffers on a 16 byte boundary.
74 #define PRIV_BYTES (sizeof(struct mace_data) \
75 + (N_RX_RING + NCMDS_TX * N_TX_RING + 3) * sizeof(struct dbdma_cmd))
77 static int mace_open(struct net_device
*dev
);
78 static int mace_close(struct net_device
*dev
);
79 static int mace_xmit_start(struct sk_buff
*skb
, struct net_device
*dev
);
80 static void mace_set_multicast(struct net_device
*dev
);
81 static void mace_reset(struct net_device
*dev
);
82 static int mace_set_address(struct net_device
*dev
, void *addr
);
83 static irqreturn_t
mace_interrupt(int irq
, void *dev_id
);
84 static irqreturn_t
mace_txdma_intr(int irq
, void *dev_id
);
85 static irqreturn_t
mace_rxdma_intr(int irq
, void *dev_id
);
86 static void mace_set_timeout(struct net_device
*dev
);
87 static void mace_tx_timeout(unsigned long data
);
88 static inline void dbdma_reset(volatile struct dbdma_regs __iomem
*dma
);
89 static inline void mace_clean_rings(struct mace_data
*mp
);
90 static void __mace_set_address(struct net_device
*dev
, void *addr
);
93 * If we can't get a skbuff when we need it, we use this area for DMA.
95 static unsigned char *dummy_buf
;
97 static int __devinit
mace_probe(struct macio_dev
*mdev
, const struct of_device_id
*match
)
99 struct device_node
*mace
= macio_get_of_node(mdev
);
100 struct net_device
*dev
;
101 struct mace_data
*mp
;
102 const unsigned char *addr
;
103 int j
, rev
, rc
= -EBUSY
;
105 if (macio_resource_count(mdev
) != 3 || macio_irq_count(mdev
) != 3) {
106 printk(KERN_ERR
"can't use MACE %s: need 3 addrs and 3 irqs\n",
111 addr
= of_get_property(mace
, "mac-address", NULL
);
113 addr
= of_get_property(mace
, "local-mac-address", NULL
);
115 printk(KERN_ERR
"Can't get mac-address for MACE %s\n",
122 * lazy allocate the driver-wide dummy buffer. (Note that we
123 * never have more than one MACE in the system anyway)
125 if (dummy_buf
== NULL
) {
126 dummy_buf
= kmalloc(RX_BUFLEN
+2, GFP_KERNEL
);
127 if (dummy_buf
== NULL
) {
128 printk(KERN_ERR
"MACE: couldn't allocate dummy buffer\n");
133 if (macio_request_resources(mdev
, "mace")) {
134 printk(KERN_ERR
"MACE: can't request IO resources !\n");
138 dev
= alloc_etherdev(PRIV_BYTES
);
140 printk(KERN_ERR
"MACE: can't allocate ethernet device !\n");
144 SET_NETDEV_DEV(dev
, &mdev
->ofdev
.dev
);
146 mp
= netdev_priv(dev
);
148 macio_set_drvdata(mdev
, dev
);
150 dev
->base_addr
= macio_resource_start(mdev
, 0);
151 mp
->mace
= ioremap(dev
->base_addr
, 0x1000);
152 if (mp
->mace
== NULL
) {
153 printk(KERN_ERR
"MACE: can't map IO resources !\n");
157 dev
->irq
= macio_irq(mdev
, 0);
159 rev
= addr
[0] == 0 && addr
[1] == 0xA0;
160 for (j
= 0; j
< 6; ++j
) {
161 dev
->dev_addr
[j
] = rev
? bitrev8(addr
[j
]): addr
[j
];
163 mp
->chipid
= (in_8(&mp
->mace
->chipid_hi
) << 8) |
164 in_8(&mp
->mace
->chipid_lo
);
167 mp
= netdev_priv(dev
);
168 mp
->maccc
= ENXMT
| ENRCV
;
170 mp
->tx_dma
= ioremap(macio_resource_start(mdev
, 1), 0x1000);
171 if (mp
->tx_dma
== NULL
) {
172 printk(KERN_ERR
"MACE: can't map TX DMA resources !\n");
176 mp
->tx_dma_intr
= macio_irq(mdev
, 1);
178 mp
->rx_dma
= ioremap(macio_resource_start(mdev
, 2), 0x1000);
179 if (mp
->rx_dma
== NULL
) {
180 printk(KERN_ERR
"MACE: can't map RX DMA resources !\n");
182 goto err_unmap_tx_dma
;
184 mp
->rx_dma_intr
= macio_irq(mdev
, 2);
186 mp
->tx_cmds
= (volatile struct dbdma_cmd
*) DBDMA_ALIGN(mp
+ 1);
187 mp
->rx_cmds
= mp
->tx_cmds
+ NCMDS_TX
* N_TX_RING
+ 1;
189 memset((char *) mp
->tx_cmds
, 0,
190 (NCMDS_TX
*N_TX_RING
+ N_RX_RING
+ 2) * sizeof(struct dbdma_cmd
));
191 init_timer(&mp
->tx_timeout
);
192 spin_lock_init(&mp
->lock
);
193 mp
->timeout_active
= 0;
196 mp
->port_aaui
= port_aaui
;
198 /* Apple Network Server uses the AAUI port */
199 if (machine_is_compatible("AAPL,ShinerESB"))
202 #ifdef CONFIG_MACE_AAUI_PORT
210 dev
->open
= mace_open
;
211 dev
->stop
= mace_close
;
212 dev
->hard_start_xmit
= mace_xmit_start
;
213 dev
->set_multicast_list
= mace_set_multicast
;
214 dev
->set_mac_address
= mace_set_address
;
217 * Most of what is below could be moved to mace_open()
221 rc
= request_irq(dev
->irq
, mace_interrupt
, 0, "MACE", dev
);
223 printk(KERN_ERR
"MACE: can't get irq %d\n", dev
->irq
);
224 goto err_unmap_rx_dma
;
226 rc
= request_irq(mp
->tx_dma_intr
, mace_txdma_intr
, 0, "MACE-txdma", dev
);
228 printk(KERN_ERR
"MACE: can't get irq %d\n", mp
->tx_dma_intr
);
231 rc
= request_irq(mp
->rx_dma_intr
, mace_rxdma_intr
, 0, "MACE-rxdma", dev
);
233 printk(KERN_ERR
"MACE: can't get irq %d\n", mp
->rx_dma_intr
);
234 goto err_free_tx_irq
;
237 rc
= register_netdev(dev
);
239 printk(KERN_ERR
"MACE: Cannot register net device, aborting.\n");
240 goto err_free_rx_irq
;
243 printk(KERN_INFO
"%s: MACE at %pM, chip revision %d.%d\n",
244 dev
->name
, dev
->dev_addr
,
245 mp
->chipid
>> 8, mp
->chipid
& 0xff);
250 free_irq(macio_irq(mdev
, 2), dev
);
252 free_irq(macio_irq(mdev
, 1), dev
);
254 free_irq(macio_irq(mdev
, 0), dev
);
264 macio_release_resources(mdev
);
269 static int __devexit
mace_remove(struct macio_dev
*mdev
)
271 struct net_device
*dev
= macio_get_drvdata(mdev
);
272 struct mace_data
*mp
;
276 macio_set_drvdata(mdev
, NULL
);
278 mp
= netdev_priv(dev
);
280 unregister_netdev(dev
);
282 free_irq(dev
->irq
, dev
);
283 free_irq(mp
->tx_dma_intr
, dev
);
284 free_irq(mp
->rx_dma_intr
, dev
);
292 macio_release_resources(mdev
);
297 static void dbdma_reset(volatile struct dbdma_regs __iomem
*dma
)
301 out_le32(&dma
->control
, (WAKE
|FLUSH
|PAUSE
|RUN
) << 16);
304 * Yes this looks peculiar, but apparently it needs to be this
305 * way on some machines.
307 for (i
= 200; i
> 0; --i
)
308 if (ld_le32(&dma
->control
) & RUN
)
312 static void mace_reset(struct net_device
*dev
)
314 struct mace_data
*mp
= netdev_priv(dev
);
315 volatile struct mace __iomem
*mb
= mp
->mace
;
318 /* soft-reset the chip */
321 out_8(&mb
->biucc
, SWRST
);
322 if (in_8(&mb
->biucc
) & SWRST
) {
329 printk(KERN_ERR
"mace: cannot reset chip!\n");
333 out_8(&mb
->imr
, 0xff); /* disable all intrs for now */
335 out_8(&mb
->maccc
, 0); /* turn off tx, rx */
337 out_8(&mb
->biucc
, XMTSP_64
);
338 out_8(&mb
->utr
, RTRD
);
339 out_8(&mb
->fifocc
, RCVFW_32
| XMTFW_16
| XMTFWU
| RCVFWU
| XMTBRST
);
340 out_8(&mb
->xmtfc
, AUTO_PAD_XMIT
); /* auto-pad short frames */
341 out_8(&mb
->rcvfc
, 0);
343 /* load up the hardware address */
344 __mace_set_address(dev
, dev
->dev_addr
);
346 /* clear the multicast filter */
347 if (mp
->chipid
== BROKEN_ADDRCHG_REV
)
348 out_8(&mb
->iac
, LOGADDR
);
350 out_8(&mb
->iac
, ADDRCHG
| LOGADDR
);
351 while ((in_8(&mb
->iac
) & ADDRCHG
) != 0)
354 for (i
= 0; i
< 8; ++i
)
355 out_8(&mb
->ladrf
, 0);
357 /* done changing address */
358 if (mp
->chipid
!= BROKEN_ADDRCHG_REV
)
362 out_8(&mb
->plscc
, PORTSEL_AUI
+ ENPLSIO
);
364 out_8(&mb
->plscc
, PORTSEL_GPSI
+ ENPLSIO
);
367 static void __mace_set_address(struct net_device
*dev
, void *addr
)
369 struct mace_data
*mp
= netdev_priv(dev
);
370 volatile struct mace __iomem
*mb
= mp
->mace
;
371 unsigned char *p
= addr
;
374 /* load up the hardware address */
375 if (mp
->chipid
== BROKEN_ADDRCHG_REV
)
376 out_8(&mb
->iac
, PHYADDR
);
378 out_8(&mb
->iac
, ADDRCHG
| PHYADDR
);
379 while ((in_8(&mb
->iac
) & ADDRCHG
) != 0)
382 for (i
= 0; i
< 6; ++i
)
383 out_8(&mb
->padr
, dev
->dev_addr
[i
] = p
[i
]);
384 if (mp
->chipid
!= BROKEN_ADDRCHG_REV
)
388 static int mace_set_address(struct net_device
*dev
, void *addr
)
390 struct mace_data
*mp
= netdev_priv(dev
);
391 volatile struct mace __iomem
*mb
= mp
->mace
;
394 spin_lock_irqsave(&mp
->lock
, flags
);
396 __mace_set_address(dev
, addr
);
398 /* note: setting ADDRCHG clears ENRCV */
399 out_8(&mb
->maccc
, mp
->maccc
);
401 spin_unlock_irqrestore(&mp
->lock
, flags
);
405 static inline void mace_clean_rings(struct mace_data
*mp
)
409 /* free some skb's */
410 for (i
= 0; i
< N_RX_RING
; ++i
) {
411 if (mp
->rx_bufs
[i
] != NULL
) {
412 dev_kfree_skb(mp
->rx_bufs
[i
]);
413 mp
->rx_bufs
[i
] = NULL
;
416 for (i
= mp
->tx_empty
; i
!= mp
->tx_fill
; ) {
417 dev_kfree_skb(mp
->tx_bufs
[i
]);
418 if (++i
>= N_TX_RING
)
423 static int mace_open(struct net_device
*dev
)
425 struct mace_data
*mp
= netdev_priv(dev
);
426 volatile struct mace __iomem
*mb
= mp
->mace
;
427 volatile struct dbdma_regs __iomem
*rd
= mp
->rx_dma
;
428 volatile struct dbdma_regs __iomem
*td
= mp
->tx_dma
;
429 volatile struct dbdma_cmd
*cp
;
437 /* initialize list of sk_buffs for receiving and set up recv dma */
438 mace_clean_rings(mp
);
439 memset((char *)mp
->rx_cmds
, 0, N_RX_RING
* sizeof(struct dbdma_cmd
));
441 for (i
= 0; i
< N_RX_RING
- 1; ++i
) {
442 skb
= dev_alloc_skb(RX_BUFLEN
+ 2);
446 skb_reserve(skb
, 2); /* so IP header lands on 4-byte bdry */
449 mp
->rx_bufs
[i
] = skb
;
450 st_le16(&cp
->req_count
, RX_BUFLEN
);
451 st_le16(&cp
->command
, INPUT_LAST
+ INTR_ALWAYS
);
452 st_le32(&cp
->phy_addr
, virt_to_bus(data
));
456 mp
->rx_bufs
[i
] = NULL
;
457 st_le16(&cp
->command
, DBDMA_STOP
);
461 /* Put a branch back to the beginning of the receive command list */
463 st_le16(&cp
->command
, DBDMA_NOP
+ BR_ALWAYS
);
464 st_le32(&cp
->cmd_dep
, virt_to_bus(mp
->rx_cmds
));
467 out_le32(&rd
->control
, (RUN
|PAUSE
|FLUSH
|WAKE
) << 16); /* clear run bit */
468 out_le32(&rd
->cmdptr
, virt_to_bus(mp
->rx_cmds
));
469 out_le32(&rd
->control
, (RUN
<< 16) | RUN
);
471 /* put a branch at the end of the tx command list */
472 cp
= mp
->tx_cmds
+ NCMDS_TX
* N_TX_RING
;
473 st_le16(&cp
->command
, DBDMA_NOP
+ BR_ALWAYS
);
474 st_le32(&cp
->cmd_dep
, virt_to_bus(mp
->tx_cmds
));
477 out_le32(&td
->control
, (RUN
|PAUSE
|FLUSH
|WAKE
) << 16);
478 out_le32(&td
->cmdptr
, virt_to_bus(mp
->tx_cmds
));
486 out_8(&mb
->maccc
, mp
->maccc
);
487 /* enable all interrupts except receive interrupts */
488 out_8(&mb
->imr
, RCVINT
);
493 static int mace_close(struct net_device
*dev
)
495 struct mace_data
*mp
= netdev_priv(dev
);
496 volatile struct mace __iomem
*mb
= mp
->mace
;
497 volatile struct dbdma_regs __iomem
*rd
= mp
->rx_dma
;
498 volatile struct dbdma_regs __iomem
*td
= mp
->tx_dma
;
500 /* disable rx and tx */
501 out_8(&mb
->maccc
, 0);
502 out_8(&mb
->imr
, 0xff); /* disable all intrs */
504 /* disable rx and tx dma */
505 st_le32(&rd
->control
, (RUN
|PAUSE
|FLUSH
|WAKE
) << 16); /* clear run bit */
506 st_le32(&td
->control
, (RUN
|PAUSE
|FLUSH
|WAKE
) << 16); /* clear run bit */
508 mace_clean_rings(mp
);
513 static inline void mace_set_timeout(struct net_device
*dev
)
515 struct mace_data
*mp
= netdev_priv(dev
);
517 if (mp
->timeout_active
)
518 del_timer(&mp
->tx_timeout
);
519 mp
->tx_timeout
.expires
= jiffies
+ TX_TIMEOUT
;
520 mp
->tx_timeout
.function
= mace_tx_timeout
;
521 mp
->tx_timeout
.data
= (unsigned long) dev
;
522 add_timer(&mp
->tx_timeout
);
523 mp
->timeout_active
= 1;
526 static int mace_xmit_start(struct sk_buff
*skb
, struct net_device
*dev
)
528 struct mace_data
*mp
= netdev_priv(dev
);
529 volatile struct dbdma_regs __iomem
*td
= mp
->tx_dma
;
530 volatile struct dbdma_cmd
*cp
, *np
;
534 /* see if there's a free slot in the tx ring */
535 spin_lock_irqsave(&mp
->lock
, flags
);
538 if (next
>= N_TX_RING
)
540 if (next
== mp
->tx_empty
) {
541 netif_stop_queue(dev
);
543 spin_unlock_irqrestore(&mp
->lock
, flags
);
544 return 1; /* can't take it at the moment */
546 spin_unlock_irqrestore(&mp
->lock
, flags
);
548 /* partially fill in the dma command block */
550 if (len
> ETH_FRAME_LEN
) {
551 printk(KERN_DEBUG
"mace: xmit frame too long (%d)\n", len
);
554 mp
->tx_bufs
[fill
] = skb
;
555 cp
= mp
->tx_cmds
+ NCMDS_TX
* fill
;
556 st_le16(&cp
->req_count
, len
);
557 st_le32(&cp
->phy_addr
, virt_to_bus(skb
->data
));
559 np
= mp
->tx_cmds
+ NCMDS_TX
* next
;
560 out_le16(&np
->command
, DBDMA_STOP
);
562 /* poke the tx dma channel */
563 spin_lock_irqsave(&mp
->lock
, flags
);
565 if (!mp
->tx_bad_runt
&& mp
->tx_active
< MAX_TX_ACTIVE
) {
566 out_le16(&cp
->xfer_status
, 0);
567 out_le16(&cp
->command
, OUTPUT_LAST
);
568 out_le32(&td
->control
, ((RUN
|WAKE
) << 16) + (RUN
|WAKE
));
570 mace_set_timeout(dev
);
572 if (++next
>= N_TX_RING
)
574 if (next
== mp
->tx_empty
)
575 netif_stop_queue(dev
);
576 spin_unlock_irqrestore(&mp
->lock
, flags
);
581 static void mace_set_multicast(struct net_device
*dev
)
583 struct mace_data
*mp
= netdev_priv(dev
);
584 volatile struct mace __iomem
*mb
= mp
->mace
;
589 spin_lock_irqsave(&mp
->lock
, flags
);
591 if (dev
->flags
& IFF_PROMISC
) {
594 unsigned char multicast_filter
[8];
595 struct dev_mc_list
*dmi
= dev
->mc_list
;
597 if (dev
->flags
& IFF_ALLMULTI
) {
598 for (i
= 0; i
< 8; i
++)
599 multicast_filter
[i
] = 0xff;
601 for (i
= 0; i
< 8; i
++)
602 multicast_filter
[i
] = 0;
603 for (i
= 0; i
< dev
->mc_count
; i
++) {
604 crc
= ether_crc_le(6, dmi
->dmi_addr
);
605 j
= crc
>> 26; /* bit number in multicast_filter */
606 multicast_filter
[j
>> 3] |= 1 << (j
& 7);
611 printk("Multicast filter :");
612 for (i
= 0; i
< 8; i
++)
613 printk("%02x ", multicast_filter
[i
]);
617 if (mp
->chipid
== BROKEN_ADDRCHG_REV
)
618 out_8(&mb
->iac
, LOGADDR
);
620 out_8(&mb
->iac
, ADDRCHG
| LOGADDR
);
621 while ((in_8(&mb
->iac
) & ADDRCHG
) != 0)
624 for (i
= 0; i
< 8; ++i
)
625 out_8(&mb
->ladrf
, multicast_filter
[i
]);
626 if (mp
->chipid
!= BROKEN_ADDRCHG_REV
)
630 out_8(&mb
->maccc
, mp
->maccc
);
631 spin_unlock_irqrestore(&mp
->lock
, flags
);
634 static void mace_handle_misc_intrs(struct mace_data
*mp
, int intr
, struct net_device
*dev
)
636 volatile struct mace __iomem
*mb
= mp
->mace
;
637 static int mace_babbles
, mace_jabbers
;
640 dev
->stats
.rx_missed_errors
+= 256;
641 dev
->stats
.rx_missed_errors
+= in_8(&mb
->mpc
); /* reading clears it */
643 dev
->stats
.rx_length_errors
+= 256;
644 dev
->stats
.rx_length_errors
+= in_8(&mb
->rntpc
); /* reading clears it */
646 ++dev
->stats
.tx_heartbeat_errors
;
648 if (mace_babbles
++ < 4)
649 printk(KERN_DEBUG
"mace: babbling transmitter\n");
651 if (mace_jabbers
++ < 4)
652 printk(KERN_DEBUG
"mace: jabbering transceiver\n");
655 static irqreturn_t
mace_interrupt(int irq
, void *dev_id
)
657 struct net_device
*dev
= (struct net_device
*) dev_id
;
658 struct mace_data
*mp
= netdev_priv(dev
);
659 volatile struct mace __iomem
*mb
= mp
->mace
;
660 volatile struct dbdma_regs __iomem
*td
= mp
->tx_dma
;
661 volatile struct dbdma_cmd
*cp
;
662 int intr
, fs
, i
, stat
, x
;
665 /* static int mace_last_fs, mace_last_xcount; */
667 spin_lock_irqsave(&mp
->lock
, flags
);
668 intr
= in_8(&mb
->ir
); /* read interrupt register */
669 in_8(&mb
->xmtrc
); /* get retries */
670 mace_handle_misc_intrs(mp
, intr
, dev
);
673 while (in_8(&mb
->pr
) & XMTSV
) {
674 del_timer(&mp
->tx_timeout
);
675 mp
->timeout_active
= 0;
677 * Clear any interrupt indication associated with this status
678 * word. This appears to unlatch any error indication from
679 * the DMA controller.
681 intr
= in_8(&mb
->ir
);
683 mace_handle_misc_intrs(mp
, intr
, dev
);
684 if (mp
->tx_bad_runt
) {
685 fs
= in_8(&mb
->xmtfs
);
687 out_8(&mb
->xmtfc
, AUTO_PAD_XMIT
);
690 dstat
= ld_le32(&td
->status
);
691 /* stop DMA controller */
692 out_le32(&td
->control
, RUN
<< 16);
694 * xcount is the number of complete frames which have been
695 * written to the fifo but for which status has not been read.
697 xcount
= (in_8(&mb
->fifofc
) >> XMTFC_SH
) & XMTFC_MASK
;
698 if (xcount
== 0 || (dstat
& DEAD
)) {
700 * If a packet was aborted before the DMA controller has
701 * finished transferring it, it seems that there are 2 bytes
702 * which are stuck in some buffer somewhere. These will get
703 * transmitted as soon as we read the frame status (which
704 * reenables the transmit data transfer request). Turning
705 * off the DMA controller and/or resetting the MACE doesn't
706 * help. So we disable auto-padding and FCS transmission
707 * so the two bytes will only be a runt packet which should
708 * be ignored by other stations.
710 out_8(&mb
->xmtfc
, DXMTFCS
);
712 fs
= in_8(&mb
->xmtfs
);
713 if ((fs
& XMTSV
) == 0) {
714 printk(KERN_ERR
"mace: xmtfs not valid! (fs=%x xc=%d ds=%x)\n",
718 * XXX mace likes to hang the machine after a xmtfs error.
719 * This is hard to reproduce, reseting *may* help
722 cp
= mp
->tx_cmds
+ NCMDS_TX
* i
;
723 stat
= ld_le16(&cp
->xfer_status
);
724 if ((fs
& (UFLO
|LCOL
|LCAR
|RTRY
)) || (dstat
& DEAD
) || xcount
== 0) {
726 * Check whether there were in fact 2 bytes written to
730 x
= (in_8(&mb
->fifofc
) >> XMTFC_SH
) & XMTFC_MASK
;
732 /* there were two bytes with an end-of-packet indication */
734 mace_set_timeout(dev
);
737 * Either there weren't the two bytes buffered up, or they
738 * didn't have an end-of-packet indication.
739 * We flush the transmit FIFO just in case (by setting the
740 * XMTFWU bit with the transmitter disabled).
742 out_8(&mb
->maccc
, in_8(&mb
->maccc
) & ~ENXMT
);
743 out_8(&mb
->fifocc
, in_8(&mb
->fifocc
) | XMTFWU
);
745 out_8(&mb
->maccc
, in_8(&mb
->maccc
) | ENXMT
);
746 out_8(&mb
->xmtfc
, AUTO_PAD_XMIT
);
749 /* dma should have finished */
750 if (i
== mp
->tx_fill
) {
751 printk(KERN_DEBUG
"mace: tx ring ran out? (fs=%x xc=%d ds=%x)\n",
756 if (fs
& (UFLO
|LCOL
|LCAR
|RTRY
)) {
757 ++dev
->stats
.tx_errors
;
759 ++dev
->stats
.tx_carrier_errors
;
760 if (fs
& (UFLO
|LCOL
|RTRY
))
761 ++dev
->stats
.tx_aborted_errors
;
763 dev
->stats
.tx_bytes
+= mp
->tx_bufs
[i
]->len
;
764 ++dev
->stats
.tx_packets
;
766 dev_kfree_skb_irq(mp
->tx_bufs
[i
]);
768 if (++i
>= N_TX_RING
)
772 mace_last_xcount
= xcount
;
776 if (i
!= mp
->tx_empty
) {
778 netif_wake_queue(dev
);
784 if (!mp
->tx_bad_runt
&& i
!= mp
->tx_fill
&& mp
->tx_active
< MAX_TX_ACTIVE
) {
786 /* set up the next one */
787 cp
= mp
->tx_cmds
+ NCMDS_TX
* i
;
788 out_le16(&cp
->xfer_status
, 0);
789 out_le16(&cp
->command
, OUTPUT_LAST
);
791 if (++i
>= N_TX_RING
)
793 } while (i
!= mp
->tx_fill
&& mp
->tx_active
< MAX_TX_ACTIVE
);
794 out_le32(&td
->control
, ((RUN
|WAKE
) << 16) + (RUN
|WAKE
));
795 mace_set_timeout(dev
);
797 spin_unlock_irqrestore(&mp
->lock
, flags
);
801 static void mace_tx_timeout(unsigned long data
)
803 struct net_device
*dev
= (struct net_device
*) data
;
804 struct mace_data
*mp
= netdev_priv(dev
);
805 volatile struct mace __iomem
*mb
= mp
->mace
;
806 volatile struct dbdma_regs __iomem
*td
= mp
->tx_dma
;
807 volatile struct dbdma_regs __iomem
*rd
= mp
->rx_dma
;
808 volatile struct dbdma_cmd
*cp
;
812 spin_lock_irqsave(&mp
->lock
, flags
);
813 mp
->timeout_active
= 0;
814 if (mp
->tx_active
== 0 && !mp
->tx_bad_runt
)
817 /* update various counters */
818 mace_handle_misc_intrs(mp
, in_8(&mb
->ir
), dev
);
820 cp
= mp
->tx_cmds
+ NCMDS_TX
* mp
->tx_empty
;
822 /* turn off both tx and rx and reset the chip */
823 out_8(&mb
->maccc
, 0);
824 printk(KERN_ERR
"mace: transmit timeout - resetting\n");
829 cp
= bus_to_virt(ld_le32(&rd
->cmdptr
));
831 out_le16(&cp
->xfer_status
, 0);
832 out_le32(&rd
->cmdptr
, virt_to_bus(cp
));
833 out_le32(&rd
->control
, (RUN
<< 16) | RUN
);
835 /* fix up the transmit side */
838 ++dev
->stats
.tx_errors
;
839 if (mp
->tx_bad_runt
) {
841 } else if (i
!= mp
->tx_fill
) {
842 dev_kfree_skb(mp
->tx_bufs
[i
]);
843 if (++i
>= N_TX_RING
)
848 netif_wake_queue(dev
);
849 if (i
!= mp
->tx_fill
) {
850 cp
= mp
->tx_cmds
+ NCMDS_TX
* i
;
851 out_le16(&cp
->xfer_status
, 0);
852 out_le16(&cp
->command
, OUTPUT_LAST
);
853 out_le32(&td
->cmdptr
, virt_to_bus(cp
));
854 out_le32(&td
->control
, (RUN
<< 16) | RUN
);
856 mace_set_timeout(dev
);
859 /* turn it back on */
860 out_8(&mb
->imr
, RCVINT
);
861 out_8(&mb
->maccc
, mp
->maccc
);
864 spin_unlock_irqrestore(&mp
->lock
, flags
);
867 static irqreturn_t
mace_txdma_intr(int irq
, void *dev_id
)
872 static irqreturn_t
mace_rxdma_intr(int irq
, void *dev_id
)
874 struct net_device
*dev
= (struct net_device
*) dev_id
;
875 struct mace_data
*mp
= netdev_priv(dev
);
876 volatile struct dbdma_regs __iomem
*rd
= mp
->rx_dma
;
877 volatile struct dbdma_cmd
*cp
, *np
;
878 int i
, nb
, stat
, next
;
880 unsigned frame_status
;
881 static int mace_lost_status
;
885 spin_lock_irqsave(&mp
->lock
, flags
);
886 for (i
= mp
->rx_empty
; i
!= mp
->rx_fill
; ) {
887 cp
= mp
->rx_cmds
+ i
;
888 stat
= ld_le16(&cp
->xfer_status
);
889 if ((stat
& ACTIVE
) == 0) {
891 if (next
>= N_RX_RING
)
893 np
= mp
->rx_cmds
+ next
;
894 if (next
!= mp
->rx_fill
895 && (ld_le16(&np
->xfer_status
) & ACTIVE
) != 0) {
896 printk(KERN_DEBUG
"mace: lost a status word\n");
901 nb
= ld_le16(&cp
->req_count
) - ld_le16(&cp
->res_count
);
902 out_le16(&cp
->command
, DBDMA_STOP
);
903 /* got a packet, have a look at it */
904 skb
= mp
->rx_bufs
[i
];
906 ++dev
->stats
.rx_dropped
;
909 frame_status
= (data
[nb
-3] << 8) + data
[nb
-4];
910 if (frame_status
& (RS_OFLO
|RS_CLSN
|RS_FRAMERR
|RS_FCSERR
)) {
911 ++dev
->stats
.rx_errors
;
912 if (frame_status
& RS_OFLO
)
913 ++dev
->stats
.rx_over_errors
;
914 if (frame_status
& RS_FRAMERR
)
915 ++dev
->stats
.rx_frame_errors
;
916 if (frame_status
& RS_FCSERR
)
917 ++dev
->stats
.rx_crc_errors
;
919 /* Mace feature AUTO_STRIP_RCV is on by default, dropping the
920 * FCS on frames with 802.3 headers. This means that Ethernet
921 * frames have 8 extra octets at the end, while 802.3 frames
922 * have only 4. We need to correctly account for this. */
923 if (*(unsigned short *)(data
+12) < 1536) /* 802.3 header */
925 else /* Ethernet header; mace includes FCS */
928 skb
->protocol
= eth_type_trans(skb
, dev
);
929 dev
->stats
.rx_bytes
+= skb
->len
;
931 mp
->rx_bufs
[i
] = NULL
;
932 ++dev
->stats
.rx_packets
;
935 ++dev
->stats
.rx_errors
;
936 ++dev
->stats
.rx_length_errors
;
939 /* advance to next */
940 if (++i
>= N_RX_RING
)
948 if (next
>= N_RX_RING
)
950 if (next
== mp
->rx_empty
)
952 cp
= mp
->rx_cmds
+ i
;
953 skb
= mp
->rx_bufs
[i
];
955 skb
= dev_alloc_skb(RX_BUFLEN
+ 2);
958 mp
->rx_bufs
[i
] = skb
;
961 st_le16(&cp
->req_count
, RX_BUFLEN
);
962 data
= skb
? skb
->data
: dummy_buf
;
963 st_le32(&cp
->phy_addr
, virt_to_bus(data
));
964 out_le16(&cp
->xfer_status
, 0);
965 out_le16(&cp
->command
, INPUT_LAST
+ INTR_ALWAYS
);
967 if ((ld_le32(&rd
->status
) & ACTIVE
) != 0) {
968 out_le32(&rd
->control
, (PAUSE
<< 16) | PAUSE
);
969 while ((in_le32(&rd
->status
) & ACTIVE
) != 0)
975 if (i
!= mp
->rx_fill
) {
976 out_le32(&rd
->control
, ((RUN
|WAKE
) << 16) | (RUN
|WAKE
));
979 spin_unlock_irqrestore(&mp
->lock
, flags
);
983 static struct of_device_id mace_match
[] =
990 MODULE_DEVICE_TABLE (of
, mace_match
);
992 static struct macio_driver mace_driver
=
995 .match_table
= mace_match
,
997 .remove
= mace_remove
,
1001 static int __init
mace_init(void)
1003 return macio_register_driver(&mace_driver
);
1006 static void __exit
mace_cleanup(void)
1008 macio_unregister_driver(&mace_driver
);
1014 MODULE_AUTHOR("Paul Mackerras");
1015 MODULE_DESCRIPTION("PowerMac MACE driver.");
1016 module_param(port_aaui
, int, 0);
1017 MODULE_PARM_DESC(port_aaui
, "MACE uses AAUI port (0-1)");
1018 MODULE_LICENSE("GPL");
1020 module_init(mace_init
);
1021 module_exit(mace_cleanup
);
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