drivers/net/mlx4/mlx4_en.h

   1 /*
   2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33
  34 #ifndef _MLX4_EN_H_
  35 #define _MLX4_EN_H_
  36
  37 #include <linux/compiler.h>
  38 #include <linux/list.h>
  39 #include <linux/mutex.h>
  40 #include <linux/netdevice.h>
  41 #include <linux/inet_lro.h>
  42
  43 #include <linux/mlx4/device.h>
  44 #include <linux/mlx4/qp.h>
  45 #include <linux/mlx4/cq.h>
  46 #include <linux/mlx4/srq.h>
  47 #include <linux/mlx4/doorbell.h>
  48
  49 #include "en_port.h"
  50
  51 #define DRV_NAME        "mlx4_en"
  52 #define DRV_VERSION     "1.4.1.1"
  53 #define DRV_RELDATE     "June 2009"
  54
  55
  56 #define MLX4_EN_MSG_LEVEL       (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
  57
  58 #define en_print(level, priv, format, arg...)                   \
  59         {                                                       \
  60         if ((priv)->registered)                                 \
  61                 printk(level "%s: %s: " format, DRV_NAME,       \
  62                         (priv->dev)->name, ## arg);             \
  63         else                                                    \
  64                 printk(level "%s: %s: Port %d: " format,        \
  65                         DRV_NAME, dev_name(&priv->mdev->pdev->dev), \
  66                         (priv)->port, ## arg);                  \
  67         }
  68
  69 #define en_dbg(mlevel, priv, format, arg...)                    \
  70         {                                                       \
  71         if (NETIF_MSG_##mlevel & priv->msg_enable)              \
  72                 en_print(KERN_DEBUG, priv, format, ## arg)      \
  73         }
  74 #define en_warn(priv, format, arg...)                           \
  75         en_print(KERN_WARNING, priv, format, ## arg)
  76 #define en_err(priv, format, arg...)                            \
  77         en_print(KERN_ERR, priv, format, ## arg)
  78
  79 #define mlx4_err(mdev, format, arg...) \
  80         printk(KERN_ERR "%s %s: " format , DRV_NAME ,\
  81                 dev_name(&mdev->pdev->dev) , ## arg)
  82 #define mlx4_info(mdev, format, arg...) \
  83         printk(KERN_INFO "%s %s: " format , DRV_NAME ,\
  84                 dev_name(&mdev->pdev->dev) , ## arg)
  85 #define mlx4_warn(mdev, format, arg...) \
  86         printk(KERN_WARNING "%s %s: " format , DRV_NAME ,\
  87                 dev_name(&mdev->pdev->dev) , ## arg)
  88
  89 /*
  90  * Device constants
  91  */
  92
  93
  94 #define MLX4_EN_PAGE_SHIFT      12
  95 #define MLX4_EN_PAGE_SIZE       (1 << MLX4_EN_PAGE_SHIFT)
  96 #define MAX_TX_RINGS            16
  97 #define MAX_RX_RINGS            16
  98 #define TXBB_SIZE               64
  99 #define HEADROOM                (2048 / TXBB_SIZE + 1)
 100 #define STAMP_STRIDE            64
 101 #define STAMP_DWORDS            (STAMP_STRIDE / 4)
 102 #define STAMP_SHIFT             31
 103 #define STAMP_VAL               0x7fffffff
 104 #define STATS_DELAY             (HZ / 4)
 105
 106 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */
 107 #define MAX_DESC_SIZE           512
 108 #define MAX_DESC_TXBBS          (MAX_DESC_SIZE / TXBB_SIZE)
 109
 110 /*
 111  * OS related constants and tunables
 112  */
 113
 114 #define MLX4_EN_WATCHDOG_TIMEOUT        (15 * HZ)
 115
 116 #define MLX4_EN_ALLOC_ORDER     2
 117 #define MLX4_EN_ALLOC_SIZE      (PAGE_SIZE << MLX4_EN_ALLOC_ORDER)
 118
 119 #define MLX4_EN_MAX_LRO_DESCRIPTORS     32
 120
 121 /* Receive fragment sizes; we use at most 4 fragments (for 9600 byte MTU
 122  * and 4K allocations) */
 123 enum {
 124         FRAG_SZ0 = 512 - NET_IP_ALIGN,
 125         FRAG_SZ1 = 1024,
 126         FRAG_SZ2 = 4096,
 127         FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
 128 };
 129 #define MLX4_EN_MAX_RX_FRAGS    4
 130
 131 /* Maximum ring sizes */
 132 #define MLX4_EN_MAX_TX_SIZE     8192
 133 #define MLX4_EN_MAX_RX_SIZE     8192
 134
 135 /* Minimum ring size for our page-allocation sceme to work */
 136 #define MLX4_EN_MIN_RX_SIZE     (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
 137 #define MLX4_EN_MIN_TX_SIZE     (4096 / TXBB_SIZE)
 138
 139 #define MLX4_EN_SMALL_PKT_SIZE          64
 140 #define MLX4_EN_NUM_TX_RINGS            8
 141 #define MLX4_EN_NUM_PPP_RINGS           8
 142 #define MLX4_EN_DEF_TX_RING_SIZE        512
 143 #define MLX4_EN_DEF_RX_RING_SIZE        1024
 144
 145 /* Target number of packets to coalesce with interrupt moderation */
 146 #define MLX4_EN_RX_COAL_TARGET  44
 147 #define MLX4_EN_RX_COAL_TIME    0x10
 148
 149 #define MLX4_EN_TX_COAL_PKTS    5
 150 #define MLX4_EN_TX_COAL_TIME    0x80
 151
 152 #define MLX4_EN_RX_RATE_LOW             400000
 153 #define MLX4_EN_RX_COAL_TIME_LOW        0
 154 #define MLX4_EN_RX_RATE_HIGH            450000
 155 #define MLX4_EN_RX_COAL_TIME_HIGH       128
 156 #define MLX4_EN_RX_SIZE_THRESH          1024
 157 #define MLX4_EN_RX_RATE_THRESH          (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
 158 #define MLX4_EN_SAMPLE_INTERVAL         0
 159
 160 #define MLX4_EN_AUTO_CONF       0xffff
 161
 162 #define MLX4_EN_DEF_RX_PAUSE    1
 163 #define MLX4_EN_DEF_TX_PAUSE    1
 164
 165 /* Interval between sucessive polls in the Tx routine when polling is used
 166    instead of interrupts (in per-core Tx rings) - should be power of 2 */
 167 #define MLX4_EN_TX_POLL_MODER   16
 168 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
 169
 170 #define ETH_LLC_SNAP_SIZE       8
 171
 172 #define SMALL_PACKET_SIZE      (256 - NET_IP_ALIGN)
 173 #define HEADER_COPY_SIZE       (128 - NET_IP_ALIGN)
 174
 175 #define MLX4_EN_MIN_MTU         46
 176 #define ETH_BCAST               0xffffffffffffULL
 177
 178 #ifdef MLX4_EN_PERF_STAT
 179 /* Number of samples to 'average' */
 180 #define AVG_SIZE                        128
 181 #define AVG_FACTOR                      1024
 182 #define NUM_PERF_STATS                  NUM_PERF_COUNTERS
 183
 184 #define INC_PERF_COUNTER(cnt)           (++(cnt))
 185 #define ADD_PERF_COUNTER(cnt, add)      ((cnt) += (add))
 186 #define AVG_PERF_COUNTER(cnt, sample) \
 187         ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
 188 #define GET_PERF_COUNTER(cnt)           (cnt)
 189 #define GET_AVG_PERF_COUNTER(cnt)       ((cnt) / AVG_FACTOR)
 190
 191 #else
 192
 193 #define NUM_PERF_STATS                  0
 194 #define INC_PERF_COUNTER(cnt)           do {} while (0)
 195 #define ADD_PERF_COUNTER(cnt, add)      do {} while (0)
 196 #define AVG_PERF_COUNTER(cnt, sample)   do {} while (0)
 197 #define GET_PERF_COUNTER(cnt)           (0)
 198 #define GET_AVG_PERF_COUNTER(cnt)       (0)
 199 #endif /* MLX4_EN_PERF_STAT */
 200
 201 /*
 202  * Configurables
 203  */
 204
 205 enum cq_type {
 206         RX = 0,
 207         TX = 1,
 208 };
 209
 210
 211 /*
 212  * Useful macros
 213  */
 214 #define ROUNDUP_LOG2(x)         ilog2(roundup_pow_of_two(x))
 215 #define XNOR(x, y)              (!(x) == !(y))
 216 #define ILLEGAL_MAC(addr)       (addr == 0xffffffffffffULL || addr == 0x0)
 217
 218
 219 struct mlx4_en_tx_info {
 220         struct sk_buff *skb;
 221         u32 nr_txbb;
 222         u8 linear;
 223         u8 data_offset;
 224         u8 inl;
 225 };
 226
 227
 228 #define MLX4_EN_BIT_DESC_OWN    0x80000000
 229 #define CTRL_SIZE       sizeof(struct mlx4_wqe_ctrl_seg)
 230 #define MLX4_EN_MEMTYPE_PAD     0x100
 231 #define DS_SIZE         sizeof(struct mlx4_wqe_data_seg)
 232
 233
 234 struct mlx4_en_tx_desc {
 235         struct mlx4_wqe_ctrl_seg ctrl;
 236         union {
 237                 struct mlx4_wqe_data_seg data; /* at least one data segment */
 238                 struct mlx4_wqe_lso_seg lso;
 239                 struct mlx4_wqe_inline_seg inl;
 240         };
 241 };
 242
 243 #define MLX4_EN_USE_SRQ         0x01000000
 244
 245 struct mlx4_en_rx_alloc {
 246         struct page *page;
 247         u16 offset;
 248 };
 249
 250 struct mlx4_en_tx_ring {
 251         struct mlx4_hwq_resources wqres;
 252         u32 size ; /* number of TXBBs */
 253         u32 size_mask;
 254         u16 stride;
 255         u16 cqn;        /* index of port CQ associated with this ring */
 256         u32 prod;
 257         u32 cons;
 258         u32 buf_size;
 259         u32 doorbell_qpn;
 260         void *buf;
 261         u16 poll_cnt;
 262         int blocked;
 263         struct mlx4_en_tx_info *tx_info;
 264         u8 *bounce_buf;
 265         u32 last_nr_txbb;
 266         struct mlx4_qp qp;
 267         struct mlx4_qp_context context;
 268         int qpn;
 269         enum mlx4_qp_state qp_state;
 270         struct mlx4_srq dummy;
 271         unsigned long bytes;
 272         unsigned long packets;
 273         spinlock_t comp_lock;
 274 };
 275
 276 struct mlx4_en_rx_desc {
 277         /* actual number of entries depends on rx ring stride */
 278         struct mlx4_wqe_data_seg data[0];
 279 };
 280
 281 struct mlx4_en_rx_ring {
 282         struct mlx4_hwq_resources wqres;
 283         struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
 284         struct net_lro_mgr lro;
 285         u32 size ;      /* number of Rx descs*/
 286         u32 actual_size;
 287         u32 size_mask;
 288         u16 stride;
 289         u16 log_stride;
 290         u16 cqn;        /* index of port CQ associated with this ring */
 291         u32 prod;
 292         u32 cons;
 293         u32 buf_size;
 294         void *buf;
 295         void *rx_info;
 296         unsigned long bytes;
 297         unsigned long packets;
 298 };
 299
 300
 301 static inline int mlx4_en_can_lro(__be16 status)
 302 {
 303         return (status & cpu_to_be16(MLX4_CQE_STATUS_IPV4       |
 304                                      MLX4_CQE_STATUS_IPV4F      |
 305                                      MLX4_CQE_STATUS_IPV6       |
 306                                      MLX4_CQE_STATUS_IPV4OPT    |
 307                                      MLX4_CQE_STATUS_TCP        |
 308                                      MLX4_CQE_STATUS_UDP        |
 309                                      MLX4_CQE_STATUS_IPOK)) ==
 310                 cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
 311                             MLX4_CQE_STATUS_IPOK |
 312                             MLX4_CQE_STATUS_TCP);
 313 }
 314
 315 struct mlx4_en_cq {
 316         struct mlx4_cq          mcq;
 317         struct mlx4_hwq_resources wqres;
 318         int                     ring;
 319         spinlock_t              lock;
 320         struct net_device      *dev;
 321         struct napi_struct      napi;
 322         /* Per-core Tx cq processing support */
 323         struct timer_list timer;
 324         int size;
 325         int buf_size;
 326         unsigned vector;
 327         enum cq_type is_tx;
 328         u16 moder_time;
 329         u16 moder_cnt;
 330         struct mlx4_cqe *buf;
 331 #define MLX4_EN_OPCODE_ERROR    0x1e
 332 };
 333
 334 struct mlx4_en_port_profile {
 335         u32 flags;
 336         u32 tx_ring_num;
 337         u32 rx_ring_num;
 338         u32 tx_ring_size;
 339         u32 rx_ring_size;
 340         u8 rx_pause;
 341         u8 rx_ppp;
 342         u8 tx_pause;
 343         u8 tx_ppp;
 344 };
 345
 346 struct mlx4_en_profile {
 347         int rss_xor;
 348         int num_lro;
 349         u8 rss_mask;
 350         u32 active_ports;
 351         u32 small_pkt_int;
 352         u8 no_reset;
 353         struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
 354 };
 355
 356 struct mlx4_en_dev {
 357         struct mlx4_dev         *dev;
 358         struct pci_dev          *pdev;
 359         struct mutex            state_lock;
 360         struct net_device       *pndev[MLX4_MAX_PORTS + 1];
 361         u32                     port_cnt;
 362         bool                    device_up;
 363         struct mlx4_en_profile  profile;
 364         u32                     LSO_support;
 365         struct workqueue_struct *workqueue;
 366         struct device           *dma_device;
 367         void __iomem            *uar_map;
 368         struct mlx4_uar         priv_uar;
 369         struct mlx4_mr          mr;
 370         u32                     priv_pdn;
 371         spinlock_t              uar_lock;
 372 };
 373
 374
 375 struct mlx4_en_rss_map {
 376         int base_qpn;
 377         struct mlx4_qp qps[MAX_RX_RINGS];
 378         enum mlx4_qp_state state[MAX_RX_RINGS];
 379         struct mlx4_qp indir_qp;
 380         enum mlx4_qp_state indir_state;
 381 };
 382
 383 struct mlx4_en_rss_context {
 384         __be32 base_qpn;
 385         __be32 default_qpn;
 386         u16 reserved;
 387         u8 hash_fn;
 388         u8 flags;
 389         __be32 rss_key[10];
 390 };
 391
 392 struct mlx4_en_pkt_stats {
 393         unsigned long broadcast;
 394         unsigned long rx_prio[8];
 395         unsigned long tx_prio[8];
 396 #define NUM_PKT_STATS           17
 397 };
 398
 399 struct mlx4_en_port_stats {
 400         unsigned long lro_aggregated;
 401         unsigned long lro_flushed;
 402         unsigned long lro_no_desc;
 403         unsigned long tso_packets;
 404         unsigned long queue_stopped;
 405         unsigned long wake_queue;
 406         unsigned long tx_timeout;
 407         unsigned long rx_alloc_failed;
 408         unsigned long rx_chksum_good;
 409         unsigned long rx_chksum_none;
 410         unsigned long tx_chksum_offload;
 411 #define NUM_PORT_STATS          11
 412 };
 413
 414 struct mlx4_en_perf_stats {
 415         u32 tx_poll;
 416         u64 tx_pktsz_avg;
 417         u32 inflight_avg;
 418         u16 tx_coal_avg;
 419         u16 rx_coal_avg;
 420         u32 napi_quota;
 421 #define NUM_PERF_COUNTERS               6
 422 };
 423
 424 struct mlx4_en_frag_info {
 425         u16 frag_size;
 426         u16 frag_prefix_size;
 427         u16 frag_stride;
 428         u16 frag_align;
 429         u16 last_offset;
 430
 431 };
 432
 433 struct mlx4_en_priv {
 434         struct mlx4_en_dev *mdev;
 435         struct mlx4_en_port_profile *prof;
 436         struct net_device *dev;
 437         struct vlan_group *vlgrp;
 438         struct net_device_stats stats;
 439         struct net_device_stats ret_stats;
 440         spinlock_t stats_lock;
 441
 442         unsigned long last_moder_packets;
 443         unsigned long last_moder_tx_packets;
 444         unsigned long last_moder_bytes;
 445         unsigned long last_moder_jiffies;
 446         int last_moder_time;
 447         u16 rx_usecs;
 448         u16 rx_frames;
 449         u16 tx_usecs;
 450         u16 tx_frames;
 451         u32 pkt_rate_low;
 452         u16 rx_usecs_low;
 453         u32 pkt_rate_high;
 454         u16 rx_usecs_high;
 455         u16 sample_interval;
 456         u16 adaptive_rx_coal;
 457         u32 msg_enable;
 458
 459         struct mlx4_hwq_resources res;
 460         int link_state;
 461         int last_link_state;
 462         bool port_up;
 463         int port;
 464         int registered;
 465         int allocated;
 466         int stride;
 467         int rx_csum;
 468         u64 mac;
 469         int mac_index;
 470         unsigned max_mtu;
 471         int base_qpn;
 472
 473         struct mlx4_en_rss_map rss_map;
 474         u32 flags;
 475 #define MLX4_EN_FLAG_PROMISC    0x1
 476         u32 tx_ring_num;
 477         u32 rx_ring_num;
 478         u32 rx_skb_size;
 479         struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
 480         u16 num_frags;
 481         u16 log_rx_info;
 482
 483         struct mlx4_en_tx_ring tx_ring[MAX_TX_RINGS];
 484         struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS];
 485         struct mlx4_en_cq tx_cq[MAX_TX_RINGS];
 486         struct mlx4_en_cq rx_cq[MAX_RX_RINGS];
 487         struct work_struct mcast_task;
 488         struct work_struct mac_task;
 489         struct work_struct watchdog_task;
 490         struct work_struct linkstate_task;
 491         struct delayed_work stats_task;
 492         struct mlx4_en_perf_stats pstats;
 493         struct mlx4_en_pkt_stats pkstats;
 494         struct mlx4_en_port_stats port_stats;
 495         struct dev_mc_list *mc_list;
 496         struct mlx4_en_stat_out_mbox hw_stats;
 497 };
 498
 499
 500 void mlx4_en_destroy_netdev(struct net_device *dev);
 501 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
 502                         struct mlx4_en_port_profile *prof);
 503
 504 int mlx4_en_start_port(struct net_device *dev);
 505 void mlx4_en_stop_port(struct net_device *dev);
 506
 507 void mlx4_en_free_resources(struct mlx4_en_priv *priv);
 508 int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
 509
 510 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
 511                       int entries, int ring, enum cq_type mode);
 512 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 513 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 514 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 515 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 516 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 517
 518 void mlx4_en_poll_tx_cq(unsigned long data);
 519 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
 520 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb);
 521 int mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
 522
 523 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring,
 524                            u32 size, u16 stride);
 525 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring);
 526 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
 527                              struct mlx4_en_tx_ring *ring,
 528                              int cq);
 529 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
 530                                 struct mlx4_en_tx_ring *ring);
 531
 532 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
 533                            struct mlx4_en_rx_ring *ring,
 534                            u32 size, u16 stride);
 535 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
 536                              struct mlx4_en_rx_ring *ring);
 537 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
 538 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
 539                                 struct mlx4_en_rx_ring *ring);
 540 int mlx4_en_process_rx_cq(struct net_device *dev,
 541                           struct mlx4_en_cq *cq,
 542                           int budget);
 543 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
 544 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
 545                              int is_tx, int rss, int qpn, int cqn,
 546                              struct mlx4_qp_context *context);
 547 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
 548 int mlx4_en_map_buffer(struct mlx4_buf *buf);
 549 void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
 550
 551 void mlx4_en_calc_rx_buf(struct net_device *dev);
 552 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
 553 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
 554 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
 555 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
 556
 557 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
 558 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, u8 port, struct vlan_group *grp);
 559 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
 560                           u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
 561 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
 562                            u8 promisc);
 563
 564 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
 565
 566 /*
 567  * Globals
 568  */
 569 extern const struct ethtool_ops mlx4_en_ethtool_ops;
 570 #endif