2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/etherdevice.h>
44 #include <linux/delay.h>
45 #include <linux/ethtool.h>
46 #include <linux/platform_device.h>
47 #include <linux/module.h>
48 #include <linux/kernel.h>
49 #include <linux/spinlock.h>
50 #include <linux/workqueue.h>
51 #include <linux/mii.h>
52 #include <linux/mv643xx_eth.h>
54 #include <asm/types.h>
55 #include <asm/system.h>
57 static char mv643xx_eth_driver_name
[] = "mv643xx_eth";
58 static char mv643xx_eth_driver_version
[] = "1.2";
60 #define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
61 #define MV643XX_ETH_NAPI
62 #define MV643XX_ETH_TX_FAST_REFILL
64 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
65 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
67 #define MAX_DESCS_PER_SKB 1
71 * Registers shared between all ports.
73 #define PHY_ADDR 0x0000
74 #define SMI_REG 0x0004
75 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
76 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
77 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
78 #define WINDOW_BAR_ENABLE 0x0290
79 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
84 #define PORT_CONFIG(p) (0x0400 + ((p) << 10))
85 #define UNICAST_PROMISCUOUS_MODE 0x00000001
86 #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
87 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
88 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
89 #define SDMA_CONFIG(p) (0x041c + ((p) << 10))
90 #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
91 #define PORT_STATUS(p) (0x0444 + ((p) << 10))
92 #define TX_FIFO_EMPTY 0x00000400
93 #define TX_IN_PROGRESS 0x00000080
94 #define PORT_SPEED_MASK 0x00000030
95 #define PORT_SPEED_1000 0x00000010
96 #define PORT_SPEED_100 0x00000020
97 #define PORT_SPEED_10 0x00000000
98 #define FLOW_CONTROL_ENABLED 0x00000008
99 #define FULL_DUPLEX 0x00000004
100 #define LINK_UP 0x00000002
101 #define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
102 #define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
103 #define TX_BW_RATE(p) (0x0450 + ((p) << 10))
104 #define TX_BW_MTU(p) (0x0458 + ((p) << 10))
105 #define TX_BW_BURST(p) (0x045c + ((p) << 10))
106 #define INT_CAUSE(p) (0x0460 + ((p) << 10))
107 #define INT_TX_END_0 0x00080000
108 #define INT_TX_END 0x07f80000
109 #define INT_RX 0x0007fbfc
110 #define INT_EXT 0x00000002
111 #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
112 #define INT_EXT_LINK 0x00100000
113 #define INT_EXT_PHY 0x00010000
114 #define INT_EXT_TX_ERROR_0 0x00000100
115 #define INT_EXT_TX_0 0x00000001
116 #define INT_EXT_TX 0x0000ffff
117 #define INT_MASK(p) (0x0468 + ((p) << 10))
118 #define INT_MASK_EXT(p) (0x046c + ((p) << 10))
119 #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
120 #define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
121 #define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
122 #define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
123 #define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
124 #define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
125 #define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
126 #define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
127 #define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
128 #define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
129 #define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
130 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
131 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
132 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
133 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
137 * SDMA configuration register.
139 #define RX_BURST_SIZE_16_64BIT (4 << 1)
140 #define BLM_RX_NO_SWAP (1 << 4)
141 #define BLM_TX_NO_SWAP (1 << 5)
142 #define TX_BURST_SIZE_16_64BIT (4 << 22)
144 #if defined(__BIG_ENDIAN)
145 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
146 RX_BURST_SIZE_16_64BIT | \
147 TX_BURST_SIZE_16_64BIT
148 #elif defined(__LITTLE_ENDIAN)
149 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
150 RX_BURST_SIZE_16_64BIT | \
153 TX_BURST_SIZE_16_64BIT
155 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
160 * Port serial control register.
162 #define SET_MII_SPEED_TO_100 (1 << 24)
163 #define SET_GMII_SPEED_TO_1000 (1 << 23)
164 #define SET_FULL_DUPLEX_MODE (1 << 21)
165 #define MAX_RX_PACKET_9700BYTE (5 << 17)
166 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
167 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
168 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
169 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
170 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
171 #define FORCE_LINK_PASS (1 << 1)
172 #define SERIAL_PORT_ENABLE (1 << 0)
174 #define DEFAULT_RX_QUEUE_SIZE 400
175 #define DEFAULT_TX_QUEUE_SIZE 800
181 #if defined(__BIG_ENDIAN)
183 u16 byte_cnt
; /* Descriptor buffer byte count */
184 u16 buf_size
; /* Buffer size */
185 u32 cmd_sts
; /* Descriptor command status */
186 u32 next_desc_ptr
; /* Next descriptor pointer */
187 u32 buf_ptr
; /* Descriptor buffer pointer */
191 u16 byte_cnt
; /* buffer byte count */
192 u16 l4i_chk
; /* CPU provided TCP checksum */
193 u32 cmd_sts
; /* Command/status field */
194 u32 next_desc_ptr
; /* Pointer to next descriptor */
195 u32 buf_ptr
; /* pointer to buffer for this descriptor*/
197 #elif defined(__LITTLE_ENDIAN)
199 u32 cmd_sts
; /* Descriptor command status */
200 u16 buf_size
; /* Buffer size */
201 u16 byte_cnt
; /* Descriptor buffer byte count */
202 u32 buf_ptr
; /* Descriptor buffer pointer */
203 u32 next_desc_ptr
; /* Next descriptor pointer */
207 u32 cmd_sts
; /* Command/status field */
208 u16 l4i_chk
; /* CPU provided TCP checksum */
209 u16 byte_cnt
; /* buffer byte count */
210 u32 buf_ptr
; /* pointer to buffer for this descriptor*/
211 u32 next_desc_ptr
; /* Pointer to next descriptor */
214 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
217 /* RX & TX descriptor command */
218 #define BUFFER_OWNED_BY_DMA 0x80000000
220 /* RX & TX descriptor status */
221 #define ERROR_SUMMARY 0x00000001
223 /* RX descriptor status */
224 #define LAYER_4_CHECKSUM_OK 0x40000000
225 #define RX_ENABLE_INTERRUPT 0x20000000
226 #define RX_FIRST_DESC 0x08000000
227 #define RX_LAST_DESC 0x04000000
229 /* TX descriptor command */
230 #define TX_ENABLE_INTERRUPT 0x00800000
231 #define GEN_CRC 0x00400000
232 #define TX_FIRST_DESC 0x00200000
233 #define TX_LAST_DESC 0x00100000
234 #define ZERO_PADDING 0x00080000
235 #define GEN_IP_V4_CHECKSUM 0x00040000
236 #define GEN_TCP_UDP_CHECKSUM 0x00020000
237 #define UDP_FRAME 0x00010000
238 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
239 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
241 #define TX_IHL_SHIFT 11
244 /* global *******************************************************************/
245 struct mv643xx_eth_shared_private
{
247 * Ethernet controller base address.
252 * Protects access to SMI_REG, which is shared between ports.
257 * Per-port MBUS window access register value.
262 * Hardware-specific parameters.
265 int extended_rx_coal_limit
;
266 int tx_bw_control_moved
;
270 /* per-port *****************************************************************/
271 struct mib_counters
{
272 u64 good_octets_received
;
273 u32 bad_octets_received
;
274 u32 internal_mac_transmit_err
;
275 u32 good_frames_received
;
276 u32 bad_frames_received
;
277 u32 broadcast_frames_received
;
278 u32 multicast_frames_received
;
279 u32 frames_64_octets
;
280 u32 frames_65_to_127_octets
;
281 u32 frames_128_to_255_octets
;
282 u32 frames_256_to_511_octets
;
283 u32 frames_512_to_1023_octets
;
284 u32 frames_1024_to_max_octets
;
285 u64 good_octets_sent
;
286 u32 good_frames_sent
;
287 u32 excessive_collision
;
288 u32 multicast_frames_sent
;
289 u32 broadcast_frames_sent
;
290 u32 unrec_mac_control_received
;
292 u32 good_fc_received
;
294 u32 undersize_received
;
295 u32 fragments_received
;
296 u32 oversize_received
;
298 u32 mac_receive_error
;
313 struct rx_desc
*rx_desc_area
;
314 dma_addr_t rx_desc_dma
;
315 int rx_desc_area_size
;
316 struct sk_buff
**rx_skb
;
318 struct timer_list rx_oom
;
330 struct tx_desc
*tx_desc_area
;
331 dma_addr_t tx_desc_dma
;
332 int tx_desc_area_size
;
333 struct sk_buff
**tx_skb
;
336 struct mv643xx_eth_private
{
337 struct mv643xx_eth_shared_private
*shared
;
340 struct net_device
*dev
;
342 struct mv643xx_eth_shared_private
*shared_smi
;
347 struct mib_counters mib_counters
;
348 struct work_struct tx_timeout_task
;
349 struct mii_if_info mii
;
354 int default_rx_ring_size
;
355 unsigned long rx_desc_sram_addr
;
356 int rx_desc_sram_size
;
359 struct napi_struct napi
;
360 struct rx_queue rxq
[8];
365 int default_tx_ring_size
;
366 unsigned long tx_desc_sram_addr
;
367 int tx_desc_sram_size
;
370 struct tx_queue txq
[8];
371 #ifdef MV643XX_ETH_TX_FAST_REFILL
372 int tx_clean_threshold
;
377 /* port register accessors **************************************************/
378 static inline u32
rdl(struct mv643xx_eth_private
*mp
, int offset
)
380 return readl(mp
->shared
->base
+ offset
);
383 static inline void wrl(struct mv643xx_eth_private
*mp
, int offset
, u32 data
)
385 writel(data
, mp
->shared
->base
+ offset
);
389 /* rxq/txq helper functions *************************************************/
390 static struct mv643xx_eth_private
*rxq_to_mp(struct rx_queue
*rxq
)
392 return container_of(rxq
, struct mv643xx_eth_private
, rxq
[rxq
->index
]);
395 static struct mv643xx_eth_private
*txq_to_mp(struct tx_queue
*txq
)
397 return container_of(txq
, struct mv643xx_eth_private
, txq
[txq
->index
]);
400 static void rxq_enable(struct rx_queue
*rxq
)
402 struct mv643xx_eth_private
*mp
= rxq_to_mp(rxq
);
403 wrl(mp
, RXQ_COMMAND(mp
->port_num
), 1 << rxq
->index
);
406 static void rxq_disable(struct rx_queue
*rxq
)
408 struct mv643xx_eth_private
*mp
= rxq_to_mp(rxq
);
409 u8 mask
= 1 << rxq
->index
;
411 wrl(mp
, RXQ_COMMAND(mp
->port_num
), mask
<< 8);
412 while (rdl(mp
, RXQ_COMMAND(mp
->port_num
)) & mask
)
416 static void txq_reset_hw_ptr(struct tx_queue
*txq
)
418 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
419 int off
= TXQ_CURRENT_DESC_PTR(mp
->port_num
, txq
->index
);
422 addr
= (u32
)txq
->tx_desc_dma
;
423 addr
+= txq
->tx_curr_desc
* sizeof(struct tx_desc
);
427 static void txq_enable(struct tx_queue
*txq
)
429 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
430 wrl(mp
, TXQ_COMMAND(mp
->port_num
), 1 << txq
->index
);
433 static void txq_disable(struct tx_queue
*txq
)
435 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
436 u8 mask
= 1 << txq
->index
;
438 wrl(mp
, TXQ_COMMAND(mp
->port_num
), mask
<< 8);
439 while (rdl(mp
, TXQ_COMMAND(mp
->port_num
)) & mask
)
443 static void __txq_maybe_wake(struct tx_queue
*txq
)
445 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
448 * netif_{stop,wake}_queue() flow control only applies to
451 BUG_ON(txq
->index
!= mp
->txq_primary
);
453 if (txq
->tx_ring_size
- txq
->tx_desc_count
>= MAX_DESCS_PER_SKB
)
454 netif_wake_queue(mp
->dev
);
458 /* rx ***********************************************************************/
459 static void txq_reclaim(struct tx_queue
*txq
, int force
);
461 static void rxq_refill(struct rx_queue
*rxq
)
463 struct mv643xx_eth_private
*mp
= rxq_to_mp(rxq
);
466 spin_lock_irqsave(&mp
->lock
, flags
);
468 while (rxq
->rx_desc_count
< rxq
->rx_ring_size
) {
475 * Reserve 2+14 bytes for an ethernet header (the
476 * hardware automatically prepends 2 bytes of dummy
477 * data to each received packet), 4 bytes for a VLAN
478 * header, and 4 bytes for the trailing FCS -- 24
481 skb_size
= mp
->dev
->mtu
+ 24;
483 skb
= dev_alloc_skb(skb_size
+ dma_get_cache_alignment() - 1);
487 unaligned
= (u32
)skb
->data
& (dma_get_cache_alignment() - 1);
489 skb_reserve(skb
, dma_get_cache_alignment() - unaligned
);
491 rxq
->rx_desc_count
++;
492 rx
= rxq
->rx_used_desc
;
493 rxq
->rx_used_desc
= (rx
+ 1) % rxq
->rx_ring_size
;
495 rxq
->rx_desc_area
[rx
].buf_ptr
= dma_map_single(NULL
, skb
->data
,
496 skb_size
, DMA_FROM_DEVICE
);
497 rxq
->rx_desc_area
[rx
].buf_size
= skb_size
;
498 rxq
->rx_skb
[rx
] = skb
;
500 rxq
->rx_desc_area
[rx
].cmd_sts
= BUFFER_OWNED_BY_DMA
|
505 * The hardware automatically prepends 2 bytes of
506 * dummy data to each received packet, so that the
507 * IP header ends up 16-byte aligned.
512 if (rxq
->rx_desc_count
!= rxq
->rx_ring_size
) {
513 rxq
->rx_oom
.expires
= jiffies
+ (HZ
/ 10);
514 add_timer(&rxq
->rx_oom
);
517 spin_unlock_irqrestore(&mp
->lock
, flags
);
520 static inline void rxq_refill_timer_wrapper(unsigned long data
)
522 rxq_refill((struct rx_queue
*)data
);
525 static int rxq_process(struct rx_queue
*rxq
, int budget
)
527 struct mv643xx_eth_private
*mp
= rxq_to_mp(rxq
);
528 struct net_device_stats
*stats
= &mp
->dev
->stats
;
532 while (rx
< budget
) {
533 struct rx_desc
*rx_desc
;
534 unsigned int cmd_sts
;
538 spin_lock_irqsave(&mp
->lock
, flags
);
540 rx_desc
= &rxq
->rx_desc_area
[rxq
->rx_curr_desc
];
542 cmd_sts
= rx_desc
->cmd_sts
;
543 if (cmd_sts
& BUFFER_OWNED_BY_DMA
) {
544 spin_unlock_irqrestore(&mp
->lock
, flags
);
549 skb
= rxq
->rx_skb
[rxq
->rx_curr_desc
];
550 rxq
->rx_skb
[rxq
->rx_curr_desc
] = NULL
;
552 rxq
->rx_curr_desc
= (rxq
->rx_curr_desc
+ 1) % rxq
->rx_ring_size
;
554 spin_unlock_irqrestore(&mp
->lock
, flags
);
556 dma_unmap_single(NULL
, rx_desc
->buf_ptr
+ 2,
557 mp
->dev
->mtu
+ 24, DMA_FROM_DEVICE
);
558 rxq
->rx_desc_count
--;
564 * Note that the descriptor byte count includes 2 dummy
565 * bytes automatically inserted by the hardware at the
566 * start of the packet (which we don't count), and a 4
567 * byte CRC at the end of the packet (which we do count).
570 stats
->rx_bytes
+= rx_desc
->byte_cnt
- 2;
573 * In case we received a packet without first / last bits
574 * on, or the error summary bit is set, the packet needs
577 if (((cmd_sts
& (RX_FIRST_DESC
| RX_LAST_DESC
)) !=
578 (RX_FIRST_DESC
| RX_LAST_DESC
))
579 || (cmd_sts
& ERROR_SUMMARY
)) {
582 if ((cmd_sts
& (RX_FIRST_DESC
| RX_LAST_DESC
)) !=
583 (RX_FIRST_DESC
| RX_LAST_DESC
)) {
585 dev_printk(KERN_ERR
, &mp
->dev
->dev
,
586 "received packet spanning "
587 "multiple descriptors\n");
590 if (cmd_sts
& ERROR_SUMMARY
)
593 dev_kfree_skb_irq(skb
);
596 * The -4 is for the CRC in the trailer of the
599 skb_put(skb
, rx_desc
->byte_cnt
- 2 - 4);
601 if (cmd_sts
& LAYER_4_CHECKSUM_OK
) {
602 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
604 (cmd_sts
& 0x0007fff8) >> 3);
606 skb
->protocol
= eth_type_trans(skb
, mp
->dev
);
607 #ifdef MV643XX_ETH_NAPI
608 netif_receive_skb(skb
);
614 mp
->dev
->last_rx
= jiffies
;
622 #ifdef MV643XX_ETH_NAPI
623 static int mv643xx_eth_poll(struct napi_struct
*napi
, int budget
)
625 struct mv643xx_eth_private
*mp
;
629 mp
= container_of(napi
, struct mv643xx_eth_private
, napi
);
631 #ifdef MV643XX_ETH_TX_FAST_REFILL
632 if (++mp
->tx_clean_threshold
> 5) {
633 mp
->tx_clean_threshold
= 0;
634 for (i
= 0; i
< 8; i
++)
635 if (mp
->txq_mask
& (1 << i
))
636 txq_reclaim(mp
->txq
+ i
, 0);
638 if (netif_carrier_ok(mp
->dev
)) {
639 spin_lock(&mp
->lock
);
640 __txq_maybe_wake(mp
->txq
+ mp
->txq_primary
);
641 spin_unlock(&mp
->lock
);
647 for (i
= 7; rx
< budget
&& i
>= 0; i
--)
648 if (mp
->rxq_mask
& (1 << i
))
649 rx
+= rxq_process(mp
->rxq
+ i
, budget
- rx
);
652 netif_rx_complete(mp
->dev
, napi
);
653 wrl(mp
, INT_CAUSE(mp
->port_num
), 0);
654 wrl(mp
, INT_CAUSE_EXT(mp
->port_num
), 0);
655 wrl(mp
, INT_MASK(mp
->port_num
), INT_TX_END
| INT_RX
| INT_EXT
);
663 /* tx ***********************************************************************/
664 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff
*skb
)
668 for (frag
= 0; frag
< skb_shinfo(skb
)->nr_frags
; frag
++) {
669 skb_frag_t
*fragp
= &skb_shinfo(skb
)->frags
[frag
];
670 if (fragp
->size
<= 8 && fragp
->page_offset
& 7)
677 static int txq_alloc_desc_index(struct tx_queue
*txq
)
681 BUG_ON(txq
->tx_desc_count
>= txq
->tx_ring_size
);
683 tx_desc_curr
= txq
->tx_curr_desc
;
684 txq
->tx_curr_desc
= (tx_desc_curr
+ 1) % txq
->tx_ring_size
;
686 BUG_ON(txq
->tx_curr_desc
== txq
->tx_used_desc
);
691 static void txq_submit_frag_skb(struct tx_queue
*txq
, struct sk_buff
*skb
)
693 int nr_frags
= skb_shinfo(skb
)->nr_frags
;
696 for (frag
= 0; frag
< nr_frags
; frag
++) {
697 skb_frag_t
*this_frag
;
699 struct tx_desc
*desc
;
701 this_frag
= &skb_shinfo(skb
)->frags
[frag
];
702 tx_index
= txq_alloc_desc_index(txq
);
703 desc
= &txq
->tx_desc_area
[tx_index
];
706 * The last fragment will generate an interrupt
707 * which will free the skb on TX completion.
709 if (frag
== nr_frags
- 1) {
710 desc
->cmd_sts
= BUFFER_OWNED_BY_DMA
|
711 ZERO_PADDING
| TX_LAST_DESC
|
713 txq
->tx_skb
[tx_index
] = skb
;
715 desc
->cmd_sts
= BUFFER_OWNED_BY_DMA
;
716 txq
->tx_skb
[tx_index
] = NULL
;
720 desc
->byte_cnt
= this_frag
->size
;
721 desc
->buf_ptr
= dma_map_page(NULL
, this_frag
->page
,
722 this_frag
->page_offset
,
728 static inline __be16
sum16_as_be(__sum16 sum
)
730 return (__force __be16
)sum
;
733 static void txq_submit_skb(struct tx_queue
*txq
, struct sk_buff
*skb
)
735 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
736 int nr_frags
= skb_shinfo(skb
)->nr_frags
;
738 struct tx_desc
*desc
;
742 cmd_sts
= TX_FIRST_DESC
| GEN_CRC
| BUFFER_OWNED_BY_DMA
;
744 tx_index
= txq_alloc_desc_index(txq
);
745 desc
= &txq
->tx_desc_area
[tx_index
];
748 txq_submit_frag_skb(txq
, skb
);
750 length
= skb_headlen(skb
);
751 txq
->tx_skb
[tx_index
] = NULL
;
753 cmd_sts
|= ZERO_PADDING
| TX_LAST_DESC
| TX_ENABLE_INTERRUPT
;
755 txq
->tx_skb
[tx_index
] = skb
;
758 desc
->byte_cnt
= length
;
759 desc
->buf_ptr
= dma_map_single(NULL
, skb
->data
, length
, DMA_TO_DEVICE
);
761 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
764 BUG_ON(skb
->protocol
!= htons(ETH_P_IP
) &&
765 skb
->protocol
!= htons(ETH_P_8021Q
));
767 cmd_sts
|= GEN_TCP_UDP_CHECKSUM
|
769 ip_hdr(skb
)->ihl
<< TX_IHL_SHIFT
;
771 mac_hdr_len
= (void *)ip_hdr(skb
) - (void *)skb
->data
;
772 switch (mac_hdr_len
- ETH_HLEN
) {
776 cmd_sts
|= MAC_HDR_EXTRA_4_BYTES
;
779 cmd_sts
|= MAC_HDR_EXTRA_8_BYTES
;
782 cmd_sts
|= MAC_HDR_EXTRA_4_BYTES
;
783 cmd_sts
|= MAC_HDR_EXTRA_8_BYTES
;
787 dev_printk(KERN_ERR
, &txq_to_mp(txq
)->dev
->dev
,
788 "mac header length is %d?!\n", mac_hdr_len
);
792 switch (ip_hdr(skb
)->protocol
) {
794 cmd_sts
|= UDP_FRAME
;
795 desc
->l4i_chk
= ntohs(sum16_as_be(udp_hdr(skb
)->check
));
798 desc
->l4i_chk
= ntohs(sum16_as_be(tcp_hdr(skb
)->check
));
804 /* Errata BTS #50, IHL must be 5 if no HW checksum */
805 cmd_sts
|= 5 << TX_IHL_SHIFT
;
809 /* ensure all other descriptors are written before first cmd_sts */
811 desc
->cmd_sts
= cmd_sts
;
813 /* clear TX_END interrupt status */
814 wrl(mp
, INT_CAUSE(mp
->port_num
), ~(INT_TX_END_0
<< txq
->index
));
815 rdl(mp
, INT_CAUSE(mp
->port_num
));
817 /* ensure all descriptors are written before poking hardware */
821 txq
->tx_desc_count
+= nr_frags
+ 1;
824 static int mv643xx_eth_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
826 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
827 struct net_device_stats
*stats
= &dev
->stats
;
828 struct tx_queue
*txq
;
831 if (has_tiny_unaligned_frags(skb
) && __skb_linearize(skb
)) {
833 dev_printk(KERN_DEBUG
, &dev
->dev
,
834 "failed to linearize skb with tiny "
835 "unaligned fragment\n");
836 return NETDEV_TX_BUSY
;
839 spin_lock_irqsave(&mp
->lock
, flags
);
841 txq
= mp
->txq
+ mp
->txq_primary
;
843 if (txq
->tx_ring_size
- txq
->tx_desc_count
< MAX_DESCS_PER_SKB
) {
844 spin_unlock_irqrestore(&mp
->lock
, flags
);
845 if (txq
->index
== mp
->txq_primary
&& net_ratelimit())
846 dev_printk(KERN_ERR
, &dev
->dev
,
847 "primary tx queue full?!\n");
852 txq_submit_skb(txq
, skb
);
853 stats
->tx_bytes
+= skb
->len
;
855 dev
->trans_start
= jiffies
;
857 if (txq
->index
== mp
->txq_primary
) {
860 entries_left
= txq
->tx_ring_size
- txq
->tx_desc_count
;
861 if (entries_left
< MAX_DESCS_PER_SKB
)
862 netif_stop_queue(dev
);
865 spin_unlock_irqrestore(&mp
->lock
, flags
);
871 /* tx rate control **********************************************************/
873 * Set total maximum TX rate (shared by all TX queues for this port)
874 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
876 static void tx_set_rate(struct mv643xx_eth_private
*mp
, int rate
, int burst
)
882 token_rate
= ((rate
/ 1000) * 64) / (mp
->shared
->t_clk
/ 1000);
883 if (token_rate
> 1023)
886 mtu
= (mp
->dev
->mtu
+ 255) >> 8;
890 bucket_size
= (burst
+ 255) >> 8;
891 if (bucket_size
> 65535)
894 if (mp
->shared
->tx_bw_control_moved
) {
895 wrl(mp
, TX_BW_RATE_MOVED(mp
->port_num
), token_rate
);
896 wrl(mp
, TX_BW_MTU_MOVED(mp
->port_num
), mtu
);
897 wrl(mp
, TX_BW_BURST_MOVED(mp
->port_num
), bucket_size
);
899 wrl(mp
, TX_BW_RATE(mp
->port_num
), token_rate
);
900 wrl(mp
, TX_BW_MTU(mp
->port_num
), mtu
);
901 wrl(mp
, TX_BW_BURST(mp
->port_num
), bucket_size
);
905 static void txq_set_rate(struct tx_queue
*txq
, int rate
, int burst
)
907 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
911 token_rate
= ((rate
/ 1000) * 64) / (mp
->shared
->t_clk
/ 1000);
912 if (token_rate
> 1023)
915 bucket_size
= (burst
+ 255) >> 8;
916 if (bucket_size
> 65535)
919 wrl(mp
, TXQ_BW_TOKENS(mp
->port_num
, txq
->index
), token_rate
<< 14);
920 wrl(mp
, TXQ_BW_CONF(mp
->port_num
, txq
->index
),
921 (bucket_size
<< 10) | token_rate
);
924 static void txq_set_fixed_prio_mode(struct tx_queue
*txq
)
926 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
931 * Turn on fixed priority mode.
933 if (mp
->shared
->tx_bw_control_moved
)
934 off
= TXQ_FIX_PRIO_CONF_MOVED(mp
->port_num
);
936 off
= TXQ_FIX_PRIO_CONF(mp
->port_num
);
939 val
|= 1 << txq
->index
;
943 static void txq_set_wrr(struct tx_queue
*txq
, int weight
)
945 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
950 * Turn off fixed priority mode.
952 if (mp
->shared
->tx_bw_control_moved
)
953 off
= TXQ_FIX_PRIO_CONF_MOVED(mp
->port_num
);
955 off
= TXQ_FIX_PRIO_CONF(mp
->port_num
);
958 val
&= ~(1 << txq
->index
);
962 * Configure WRR weight for this queue.
964 off
= TXQ_BW_WRR_CONF(mp
->port_num
, txq
->index
);
967 val
= (val
& ~0xff) | (weight
& 0xff);
972 /* mii management interface *************************************************/
973 #define SMI_BUSY 0x10000000
974 #define SMI_READ_VALID 0x08000000
975 #define SMI_OPCODE_READ 0x04000000
976 #define SMI_OPCODE_WRITE 0x00000000
978 static void smi_reg_read(struct mv643xx_eth_private
*mp
, unsigned int addr
,
979 unsigned int reg
, unsigned int *value
)
981 void __iomem
*smi_reg
= mp
->shared_smi
->base
+ SMI_REG
;
985 /* the SMI register is a shared resource */
986 spin_lock_irqsave(&mp
->shared_smi
->phy_lock
, flags
);
988 /* wait for the SMI register to become available */
989 for (i
= 0; readl(smi_reg
) & SMI_BUSY
; i
++) {
991 printk("%s: PHY busy timeout\n", mp
->dev
->name
);
997 writel(SMI_OPCODE_READ
| (reg
<< 21) | (addr
<< 16), smi_reg
);
999 /* now wait for the data to be valid */
1000 for (i
= 0; !(readl(smi_reg
) & SMI_READ_VALID
); i
++) {
1002 printk("%s: PHY read timeout\n", mp
->dev
->name
);
1008 *value
= readl(smi_reg
) & 0xffff;
1010 spin_unlock_irqrestore(&mp
->shared_smi
->phy_lock
, flags
);
1013 static void smi_reg_write(struct mv643xx_eth_private
*mp
,
1015 unsigned int reg
, unsigned int value
)
1017 void __iomem
*smi_reg
= mp
->shared_smi
->base
+ SMI_REG
;
1018 unsigned long flags
;
1021 /* the SMI register is a shared resource */
1022 spin_lock_irqsave(&mp
->shared_smi
->phy_lock
, flags
);
1024 /* wait for the SMI register to become available */
1025 for (i
= 0; readl(smi_reg
) & SMI_BUSY
; i
++) {
1027 printk("%s: PHY busy timeout\n", mp
->dev
->name
);
1033 writel(SMI_OPCODE_WRITE
| (reg
<< 21) |
1034 (addr
<< 16) | (value
& 0xffff), smi_reg
);
1036 spin_unlock_irqrestore(&mp
->shared_smi
->phy_lock
, flags
);
1040 /* mib counters *************************************************************/
1041 static inline u32
mib_read(struct mv643xx_eth_private
*mp
, int offset
)
1043 return rdl(mp
, MIB_COUNTERS(mp
->port_num
) + offset
);
1046 static void mib_counters_clear(struct mv643xx_eth_private
*mp
)
1050 for (i
= 0; i
< 0x80; i
+= 4)
1054 static void mib_counters_update(struct mv643xx_eth_private
*mp
)
1056 struct mib_counters
*p
= &mp
->mib_counters
;
1058 p
->good_octets_received
+= mib_read(mp
, 0x00);
1059 p
->good_octets_received
+= (u64
)mib_read(mp
, 0x04) << 32;
1060 p
->bad_octets_received
+= mib_read(mp
, 0x08);
1061 p
->internal_mac_transmit_err
+= mib_read(mp
, 0x0c);
1062 p
->good_frames_received
+= mib_read(mp
, 0x10);
1063 p
->bad_frames_received
+= mib_read(mp
, 0x14);
1064 p
->broadcast_frames_received
+= mib_read(mp
, 0x18);
1065 p
->multicast_frames_received
+= mib_read(mp
, 0x1c);
1066 p
->frames_64_octets
+= mib_read(mp
, 0x20);
1067 p
->frames_65_to_127_octets
+= mib_read(mp
, 0x24);
1068 p
->frames_128_to_255_octets
+= mib_read(mp
, 0x28);
1069 p
->frames_256_to_511_octets
+= mib_read(mp
, 0x2c);
1070 p
->frames_512_to_1023_octets
+= mib_read(mp
, 0x30);
1071 p
->frames_1024_to_max_octets
+= mib_read(mp
, 0x34);
1072 p
->good_octets_sent
+= mib_read(mp
, 0x38);
1073 p
->good_octets_sent
+= (u64
)mib_read(mp
, 0x3c) << 32;
1074 p
->good_frames_sent
+= mib_read(mp
, 0x40);
1075 p
->excessive_collision
+= mib_read(mp
, 0x44);
1076 p
->multicast_frames_sent
+= mib_read(mp
, 0x48);
1077 p
->broadcast_frames_sent
+= mib_read(mp
, 0x4c);
1078 p
->unrec_mac_control_received
+= mib_read(mp
, 0x50);
1079 p
->fc_sent
+= mib_read(mp
, 0x54);
1080 p
->good_fc_received
+= mib_read(mp
, 0x58);
1081 p
->bad_fc_received
+= mib_read(mp
, 0x5c);
1082 p
->undersize_received
+= mib_read(mp
, 0x60);
1083 p
->fragments_received
+= mib_read(mp
, 0x64);
1084 p
->oversize_received
+= mib_read(mp
, 0x68);
1085 p
->jabber_received
+= mib_read(mp
, 0x6c);
1086 p
->mac_receive_error
+= mib_read(mp
, 0x70);
1087 p
->bad_crc_event
+= mib_read(mp
, 0x74);
1088 p
->collision
+= mib_read(mp
, 0x78);
1089 p
->late_collision
+= mib_read(mp
, 0x7c);
1093 /* ethtool ******************************************************************/
1094 struct mv643xx_eth_stats
{
1095 char stat_string
[ETH_GSTRING_LEN
];
1102 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1103 offsetof(struct net_device, stats.m), -1 }
1105 #define MIBSTAT(m) \
1106 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1107 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1109 static const struct mv643xx_eth_stats mv643xx_eth_stats
[] = {
1118 MIBSTAT(good_octets_received
),
1119 MIBSTAT(bad_octets_received
),
1120 MIBSTAT(internal_mac_transmit_err
),
1121 MIBSTAT(good_frames_received
),
1122 MIBSTAT(bad_frames_received
),
1123 MIBSTAT(broadcast_frames_received
),
1124 MIBSTAT(multicast_frames_received
),
1125 MIBSTAT(frames_64_octets
),
1126 MIBSTAT(frames_65_to_127_octets
),
1127 MIBSTAT(frames_128_to_255_octets
),
1128 MIBSTAT(frames_256_to_511_octets
),
1129 MIBSTAT(frames_512_to_1023_octets
),
1130 MIBSTAT(frames_1024_to_max_octets
),
1131 MIBSTAT(good_octets_sent
),
1132 MIBSTAT(good_frames_sent
),
1133 MIBSTAT(excessive_collision
),
1134 MIBSTAT(multicast_frames_sent
),
1135 MIBSTAT(broadcast_frames_sent
),
1136 MIBSTAT(unrec_mac_control_received
),
1138 MIBSTAT(good_fc_received
),
1139 MIBSTAT(bad_fc_received
),
1140 MIBSTAT(undersize_received
),
1141 MIBSTAT(fragments_received
),
1142 MIBSTAT(oversize_received
),
1143 MIBSTAT(jabber_received
),
1144 MIBSTAT(mac_receive_error
),
1145 MIBSTAT(bad_crc_event
),
1147 MIBSTAT(late_collision
),
1150 static int mv643xx_eth_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1152 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1155 spin_lock_irq(&mp
->lock
);
1156 err
= mii_ethtool_gset(&mp
->mii
, cmd
);
1157 spin_unlock_irq(&mp
->lock
);
1160 * The MAC does not support 1000baseT_Half.
1162 cmd
->supported
&= ~SUPPORTED_1000baseT_Half
;
1163 cmd
->advertising
&= ~ADVERTISED_1000baseT_Half
;
1168 static int mv643xx_eth_get_settings_phyless(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1170 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1173 port_status
= rdl(mp
, PORT_STATUS(mp
->port_num
));
1175 cmd
->supported
= SUPPORTED_MII
;
1176 cmd
->advertising
= ADVERTISED_MII
;
1177 switch (port_status
& PORT_SPEED_MASK
) {
1179 cmd
->speed
= SPEED_10
;
1181 case PORT_SPEED_100
:
1182 cmd
->speed
= SPEED_100
;
1184 case PORT_SPEED_1000
:
1185 cmd
->speed
= SPEED_1000
;
1191 cmd
->duplex
= (port_status
& FULL_DUPLEX
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1192 cmd
->port
= PORT_MII
;
1193 cmd
->phy_address
= 0;
1194 cmd
->transceiver
= XCVR_INTERNAL
;
1195 cmd
->autoneg
= AUTONEG_DISABLE
;
1202 static int mv643xx_eth_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1204 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1208 * The MAC does not support 1000baseT_Half.
1210 cmd
->advertising
&= ~ADVERTISED_1000baseT_Half
;
1212 spin_lock_irq(&mp
->lock
);
1213 err
= mii_ethtool_sset(&mp
->mii
, cmd
);
1214 spin_unlock_irq(&mp
->lock
);
1219 static int mv643xx_eth_set_settings_phyless(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1224 static void mv643xx_eth_get_drvinfo(struct net_device
*dev
,
1225 struct ethtool_drvinfo
*drvinfo
)
1227 strncpy(drvinfo
->driver
, mv643xx_eth_driver_name
, 32);
1228 strncpy(drvinfo
->version
, mv643xx_eth_driver_version
, 32);
1229 strncpy(drvinfo
->fw_version
, "N/A", 32);
1230 strncpy(drvinfo
->bus_info
, "platform", 32);
1231 drvinfo
->n_stats
= ARRAY_SIZE(mv643xx_eth_stats
);
1234 static int mv643xx_eth_nway_reset(struct net_device
*dev
)
1236 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1238 return mii_nway_restart(&mp
->mii
);
1241 static int mv643xx_eth_nway_reset_phyless(struct net_device
*dev
)
1246 static u32
mv643xx_eth_get_link(struct net_device
*dev
)
1248 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1250 return mii_link_ok(&mp
->mii
);
1253 static u32
mv643xx_eth_get_link_phyless(struct net_device
*dev
)
1258 static void mv643xx_eth_get_strings(struct net_device
*dev
,
1259 uint32_t stringset
, uint8_t *data
)
1263 if (stringset
== ETH_SS_STATS
) {
1264 for (i
= 0; i
< ARRAY_SIZE(mv643xx_eth_stats
); i
++) {
1265 memcpy(data
+ i
* ETH_GSTRING_LEN
,
1266 mv643xx_eth_stats
[i
].stat_string
,
1272 static void mv643xx_eth_get_ethtool_stats(struct net_device
*dev
,
1273 struct ethtool_stats
*stats
,
1276 struct mv643xx_eth_private
*mp
= dev
->priv
;
1279 mib_counters_update(mp
);
1281 for (i
= 0; i
< ARRAY_SIZE(mv643xx_eth_stats
); i
++) {
1282 const struct mv643xx_eth_stats
*stat
;
1285 stat
= mv643xx_eth_stats
+ i
;
1287 if (stat
->netdev_off
>= 0)
1288 p
= ((void *)mp
->dev
) + stat
->netdev_off
;
1290 p
= ((void *)mp
) + stat
->mp_off
;
1292 data
[i
] = (stat
->sizeof_stat
== 8) ?
1293 *(uint64_t *)p
: *(uint32_t *)p
;
1297 static int mv643xx_eth_get_sset_count(struct net_device
*dev
, int sset
)
1299 if (sset
== ETH_SS_STATS
)
1300 return ARRAY_SIZE(mv643xx_eth_stats
);
1305 static const struct ethtool_ops mv643xx_eth_ethtool_ops
= {
1306 .get_settings
= mv643xx_eth_get_settings
,
1307 .set_settings
= mv643xx_eth_set_settings
,
1308 .get_drvinfo
= mv643xx_eth_get_drvinfo
,
1309 .nway_reset
= mv643xx_eth_nway_reset
,
1310 .get_link
= mv643xx_eth_get_link
,
1311 .set_sg
= ethtool_op_set_sg
,
1312 .get_strings
= mv643xx_eth_get_strings
,
1313 .get_ethtool_stats
= mv643xx_eth_get_ethtool_stats
,
1314 .get_sset_count
= mv643xx_eth_get_sset_count
,
1317 static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless
= {
1318 .get_settings
= mv643xx_eth_get_settings_phyless
,
1319 .set_settings
= mv643xx_eth_set_settings_phyless
,
1320 .get_drvinfo
= mv643xx_eth_get_drvinfo
,
1321 .nway_reset
= mv643xx_eth_nway_reset_phyless
,
1322 .get_link
= mv643xx_eth_get_link_phyless
,
1323 .set_sg
= ethtool_op_set_sg
,
1324 .get_strings
= mv643xx_eth_get_strings
,
1325 .get_ethtool_stats
= mv643xx_eth_get_ethtool_stats
,
1326 .get_sset_count
= mv643xx_eth_get_sset_count
,
1330 /* address handling *********************************************************/
1331 static void uc_addr_get(struct mv643xx_eth_private
*mp
, unsigned char *addr
)
1336 mac_h
= rdl(mp
, MAC_ADDR_HIGH(mp
->port_num
));
1337 mac_l
= rdl(mp
, MAC_ADDR_LOW(mp
->port_num
));
1339 addr
[0] = (mac_h
>> 24) & 0xff;
1340 addr
[1] = (mac_h
>> 16) & 0xff;
1341 addr
[2] = (mac_h
>> 8) & 0xff;
1342 addr
[3] = mac_h
& 0xff;
1343 addr
[4] = (mac_l
>> 8) & 0xff;
1344 addr
[5] = mac_l
& 0xff;
1347 static void init_mac_tables(struct mv643xx_eth_private
*mp
)
1351 for (i
= 0; i
< 0x100; i
+= 4) {
1352 wrl(mp
, SPECIAL_MCAST_TABLE(mp
->port_num
) + i
, 0);
1353 wrl(mp
, OTHER_MCAST_TABLE(mp
->port_num
) + i
, 0);
1356 for (i
= 0; i
< 0x10; i
+= 4)
1357 wrl(mp
, UNICAST_TABLE(mp
->port_num
) + i
, 0);
1360 static void set_filter_table_entry(struct mv643xx_eth_private
*mp
,
1361 int table
, unsigned char entry
)
1363 unsigned int table_reg
;
1365 /* Set "accepts frame bit" at specified table entry */
1366 table_reg
= rdl(mp
, table
+ (entry
& 0xfc));
1367 table_reg
|= 0x01 << (8 * (entry
& 3));
1368 wrl(mp
, table
+ (entry
& 0xfc), table_reg
);
1371 static void uc_addr_set(struct mv643xx_eth_private
*mp
, unsigned char *addr
)
1377 mac_l
= (addr
[4] << 8) | addr
[5];
1378 mac_h
= (addr
[0] << 24) | (addr
[1] << 16) | (addr
[2] << 8) | addr
[3];
1380 wrl(mp
, MAC_ADDR_LOW(mp
->port_num
), mac_l
);
1381 wrl(mp
, MAC_ADDR_HIGH(mp
->port_num
), mac_h
);
1383 table
= UNICAST_TABLE(mp
->port_num
);
1384 set_filter_table_entry(mp
, table
, addr
[5] & 0x0f);
1387 static int mv643xx_eth_set_mac_address(struct net_device
*dev
, void *addr
)
1389 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1391 /* +2 is for the offset of the HW addr type */
1392 memcpy(dev
->dev_addr
, addr
+ 2, 6);
1394 init_mac_tables(mp
);
1395 uc_addr_set(mp
, dev
->dev_addr
);
1400 static int addr_crc(unsigned char *addr
)
1405 for (i
= 0; i
< 6; i
++) {
1408 crc
= (crc
^ addr
[i
]) << 8;
1409 for (j
= 7; j
>= 0; j
--) {
1410 if (crc
& (0x100 << j
))
1418 static void mv643xx_eth_set_rx_mode(struct net_device
*dev
)
1420 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1422 struct dev_addr_list
*addr
;
1425 port_config
= rdl(mp
, PORT_CONFIG(mp
->port_num
));
1426 if (dev
->flags
& IFF_PROMISC
)
1427 port_config
|= UNICAST_PROMISCUOUS_MODE
;
1429 port_config
&= ~UNICAST_PROMISCUOUS_MODE
;
1430 wrl(mp
, PORT_CONFIG(mp
->port_num
), port_config
);
1432 if (dev
->flags
& (IFF_PROMISC
| IFF_ALLMULTI
)) {
1433 int port_num
= mp
->port_num
;
1434 u32 accept
= 0x01010101;
1436 for (i
= 0; i
< 0x100; i
+= 4) {
1437 wrl(mp
, SPECIAL_MCAST_TABLE(port_num
) + i
, accept
);
1438 wrl(mp
, OTHER_MCAST_TABLE(port_num
) + i
, accept
);
1443 for (i
= 0; i
< 0x100; i
+= 4) {
1444 wrl(mp
, SPECIAL_MCAST_TABLE(mp
->port_num
) + i
, 0);
1445 wrl(mp
, OTHER_MCAST_TABLE(mp
->port_num
) + i
, 0);
1448 for (addr
= dev
->mc_list
; addr
!= NULL
; addr
= addr
->next
) {
1449 u8
*a
= addr
->da_addr
;
1452 if (addr
->da_addrlen
!= 6)
1455 if (memcmp(a
, "\x01\x00\x5e\x00\x00", 5) == 0) {
1456 table
= SPECIAL_MCAST_TABLE(mp
->port_num
);
1457 set_filter_table_entry(mp
, table
, a
[5]);
1459 int crc
= addr_crc(a
);
1461 table
= OTHER_MCAST_TABLE(mp
->port_num
);
1462 set_filter_table_entry(mp
, table
, crc
);
1468 /* rx/tx queue initialisation ***********************************************/
1469 static int rxq_init(struct mv643xx_eth_private
*mp
, int index
)
1471 struct rx_queue
*rxq
= mp
->rxq
+ index
;
1472 struct rx_desc
*rx_desc
;
1478 rxq
->rx_ring_size
= mp
->default_rx_ring_size
;
1480 rxq
->rx_desc_count
= 0;
1481 rxq
->rx_curr_desc
= 0;
1482 rxq
->rx_used_desc
= 0;
1484 size
= rxq
->rx_ring_size
* sizeof(struct rx_desc
);
1486 if (index
== mp
->rxq_primary
&& size
<= mp
->rx_desc_sram_size
) {
1487 rxq
->rx_desc_area
= ioremap(mp
->rx_desc_sram_addr
,
1488 mp
->rx_desc_sram_size
);
1489 rxq
->rx_desc_dma
= mp
->rx_desc_sram_addr
;
1491 rxq
->rx_desc_area
= dma_alloc_coherent(NULL
, size
,
1496 if (rxq
->rx_desc_area
== NULL
) {
1497 dev_printk(KERN_ERR
, &mp
->dev
->dev
,
1498 "can't allocate rx ring (%d bytes)\n", size
);
1501 memset(rxq
->rx_desc_area
, 0, size
);
1503 rxq
->rx_desc_area_size
= size
;
1504 rxq
->rx_skb
= kmalloc(rxq
->rx_ring_size
* sizeof(*rxq
->rx_skb
),
1506 if (rxq
->rx_skb
== NULL
) {
1507 dev_printk(KERN_ERR
, &mp
->dev
->dev
,
1508 "can't allocate rx skb ring\n");
1512 rx_desc
= (struct rx_desc
*)rxq
->rx_desc_area
;
1513 for (i
= 0; i
< rxq
->rx_ring_size
; i
++) {
1514 int nexti
= (i
+ 1) % rxq
->rx_ring_size
;
1515 rx_desc
[i
].next_desc_ptr
= rxq
->rx_desc_dma
+
1516 nexti
* sizeof(struct rx_desc
);
1519 init_timer(&rxq
->rx_oom
);
1520 rxq
->rx_oom
.data
= (unsigned long)rxq
;
1521 rxq
->rx_oom
.function
= rxq_refill_timer_wrapper
;
1527 if (index
== mp
->rxq_primary
&& size
<= mp
->rx_desc_sram_size
)
1528 iounmap(rxq
->rx_desc_area
);
1530 dma_free_coherent(NULL
, size
,
1538 static void rxq_deinit(struct rx_queue
*rxq
)
1540 struct mv643xx_eth_private
*mp
= rxq_to_mp(rxq
);
1545 del_timer_sync(&rxq
->rx_oom
);
1547 for (i
= 0; i
< rxq
->rx_ring_size
; i
++) {
1548 if (rxq
->rx_skb
[i
]) {
1549 dev_kfree_skb(rxq
->rx_skb
[i
]);
1550 rxq
->rx_desc_count
--;
1554 if (rxq
->rx_desc_count
) {
1555 dev_printk(KERN_ERR
, &mp
->dev
->dev
,
1556 "error freeing rx ring -- %d skbs stuck\n",
1557 rxq
->rx_desc_count
);
1560 if (rxq
->index
== mp
->rxq_primary
&&
1561 rxq
->rx_desc_area_size
<= mp
->rx_desc_sram_size
)
1562 iounmap(rxq
->rx_desc_area
);
1564 dma_free_coherent(NULL
, rxq
->rx_desc_area_size
,
1565 rxq
->rx_desc_area
, rxq
->rx_desc_dma
);
1570 static int txq_init(struct mv643xx_eth_private
*mp
, int index
)
1572 struct tx_queue
*txq
= mp
->txq
+ index
;
1573 struct tx_desc
*tx_desc
;
1579 txq
->tx_ring_size
= mp
->default_tx_ring_size
;
1581 txq
->tx_desc_count
= 0;
1582 txq
->tx_curr_desc
= 0;
1583 txq
->tx_used_desc
= 0;
1585 size
= txq
->tx_ring_size
* sizeof(struct tx_desc
);
1587 if (index
== mp
->txq_primary
&& size
<= mp
->tx_desc_sram_size
) {
1588 txq
->tx_desc_area
= ioremap(mp
->tx_desc_sram_addr
,
1589 mp
->tx_desc_sram_size
);
1590 txq
->tx_desc_dma
= mp
->tx_desc_sram_addr
;
1592 txq
->tx_desc_area
= dma_alloc_coherent(NULL
, size
,
1597 if (txq
->tx_desc_area
== NULL
) {
1598 dev_printk(KERN_ERR
, &mp
->dev
->dev
,
1599 "can't allocate tx ring (%d bytes)\n", size
);
1602 memset(txq
->tx_desc_area
, 0, size
);
1604 txq
->tx_desc_area_size
= size
;
1605 txq
->tx_skb
= kmalloc(txq
->tx_ring_size
* sizeof(*txq
->tx_skb
),
1607 if (txq
->tx_skb
== NULL
) {
1608 dev_printk(KERN_ERR
, &mp
->dev
->dev
,
1609 "can't allocate tx skb ring\n");
1613 tx_desc
= (struct tx_desc
*)txq
->tx_desc_area
;
1614 for (i
= 0; i
< txq
->tx_ring_size
; i
++) {
1615 struct tx_desc
*txd
= tx_desc
+ i
;
1616 int nexti
= (i
+ 1) % txq
->tx_ring_size
;
1619 txd
->next_desc_ptr
= txq
->tx_desc_dma
+
1620 nexti
* sizeof(struct tx_desc
);
1627 if (index
== mp
->txq_primary
&& size
<= mp
->tx_desc_sram_size
)
1628 iounmap(txq
->tx_desc_area
);
1630 dma_free_coherent(NULL
, size
,
1638 static void txq_reclaim(struct tx_queue
*txq
, int force
)
1640 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
1641 unsigned long flags
;
1643 spin_lock_irqsave(&mp
->lock
, flags
);
1644 while (txq
->tx_desc_count
> 0) {
1646 struct tx_desc
*desc
;
1648 struct sk_buff
*skb
;
1652 tx_index
= txq
->tx_used_desc
;
1653 desc
= &txq
->tx_desc_area
[tx_index
];
1654 cmd_sts
= desc
->cmd_sts
;
1656 if (cmd_sts
& BUFFER_OWNED_BY_DMA
) {
1659 desc
->cmd_sts
= cmd_sts
& ~BUFFER_OWNED_BY_DMA
;
1662 txq
->tx_used_desc
= (tx_index
+ 1) % txq
->tx_ring_size
;
1663 txq
->tx_desc_count
--;
1665 addr
= desc
->buf_ptr
;
1666 count
= desc
->byte_cnt
;
1667 skb
= txq
->tx_skb
[tx_index
];
1668 txq
->tx_skb
[tx_index
] = NULL
;
1670 if (cmd_sts
& ERROR_SUMMARY
) {
1671 dev_printk(KERN_INFO
, &mp
->dev
->dev
, "tx error\n");
1672 mp
->dev
->stats
.tx_errors
++;
1676 * Drop mp->lock while we free the skb.
1678 spin_unlock_irqrestore(&mp
->lock
, flags
);
1680 if (cmd_sts
& TX_FIRST_DESC
)
1681 dma_unmap_single(NULL
, addr
, count
, DMA_TO_DEVICE
);
1683 dma_unmap_page(NULL
, addr
, count
, DMA_TO_DEVICE
);
1686 dev_kfree_skb_irq(skb
);
1688 spin_lock_irqsave(&mp
->lock
, flags
);
1690 spin_unlock_irqrestore(&mp
->lock
, flags
);
1693 static void txq_deinit(struct tx_queue
*txq
)
1695 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
1698 txq_reclaim(txq
, 1);
1700 BUG_ON(txq
->tx_used_desc
!= txq
->tx_curr_desc
);
1702 if (txq
->index
== mp
->txq_primary
&&
1703 txq
->tx_desc_area_size
<= mp
->tx_desc_sram_size
)
1704 iounmap(txq
->tx_desc_area
);
1706 dma_free_coherent(NULL
, txq
->tx_desc_area_size
,
1707 txq
->tx_desc_area
, txq
->tx_desc_dma
);
1713 /* netdev ops and related ***************************************************/
1714 static void handle_link_event(struct mv643xx_eth_private
*mp
)
1716 struct net_device
*dev
= mp
->dev
;
1722 port_status
= rdl(mp
, PORT_STATUS(mp
->port_num
));
1723 if (!(port_status
& LINK_UP
)) {
1724 if (netif_carrier_ok(dev
)) {
1727 printk(KERN_INFO
"%s: link down\n", dev
->name
);
1729 netif_carrier_off(dev
);
1730 netif_stop_queue(dev
);
1732 for (i
= 0; i
< 8; i
++) {
1733 struct tx_queue
*txq
= mp
->txq
+ i
;
1735 if (mp
->txq_mask
& (1 << i
)) {
1736 txq_reclaim(txq
, 1);
1737 txq_reset_hw_ptr(txq
);
1744 switch (port_status
& PORT_SPEED_MASK
) {
1748 case PORT_SPEED_100
:
1751 case PORT_SPEED_1000
:
1758 duplex
= (port_status
& FULL_DUPLEX
) ? 1 : 0;
1759 fc
= (port_status
& FLOW_CONTROL_ENABLED
) ? 1 : 0;
1761 printk(KERN_INFO
"%s: link up, %d Mb/s, %s duplex, "
1762 "flow control %sabled\n", dev
->name
,
1763 speed
, duplex
? "full" : "half",
1766 if (!netif_carrier_ok(dev
)) {
1767 netif_carrier_on(dev
);
1768 netif_wake_queue(dev
);
1772 static irqreturn_t
mv643xx_eth_irq(int irq
, void *dev_id
)
1774 struct net_device
*dev
= (struct net_device
*)dev_id
;
1775 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1779 int_cause
= rdl(mp
, INT_CAUSE(mp
->port_num
)) &
1780 (INT_TX_END
| INT_RX
| INT_EXT
);
1785 if (int_cause
& INT_EXT
) {
1786 int_cause_ext
= rdl(mp
, INT_CAUSE_EXT(mp
->port_num
))
1787 & (INT_EXT_LINK
| INT_EXT_PHY
| INT_EXT_TX
);
1788 wrl(mp
, INT_CAUSE_EXT(mp
->port_num
), ~int_cause_ext
);
1791 if (int_cause_ext
& (INT_EXT_PHY
| INT_EXT_LINK
))
1792 handle_link_event(mp
);
1795 * RxBuffer or RxError set for any of the 8 queues?
1797 #ifdef MV643XX_ETH_NAPI
1798 if (int_cause
& INT_RX
) {
1799 wrl(mp
, INT_MASK(mp
->port_num
), 0x00000000);
1800 rdl(mp
, INT_MASK(mp
->port_num
));
1802 netif_rx_schedule(dev
, &mp
->napi
);
1805 if (int_cause
& INT_RX
) {
1808 for (i
= 7; i
>= 0; i
--)
1809 if (mp
->rxq_mask
& (1 << i
))
1810 rxq_process(mp
->rxq
+ i
, INT_MAX
);
1815 * TxBuffer or TxError set for any of the 8 queues?
1817 if (int_cause_ext
& INT_EXT_TX
) {
1820 for (i
= 0; i
< 8; i
++)
1821 if (mp
->txq_mask
& (1 << i
))
1822 txq_reclaim(mp
->txq
+ i
, 0);
1825 * Enough space again in the primary TX queue for a
1828 if (netif_carrier_ok(dev
)) {
1829 spin_lock(&mp
->lock
);
1830 __txq_maybe_wake(mp
->txq
+ mp
->txq_primary
);
1831 spin_unlock(&mp
->lock
);
1836 * Any TxEnd interrupts?
1838 if (int_cause
& INT_TX_END
) {
1841 wrl(mp
, INT_CAUSE(mp
->port_num
), ~(int_cause
& INT_TX_END
));
1843 spin_lock(&mp
->lock
);
1844 for (i
= 0; i
< 8; i
++) {
1845 struct tx_queue
*txq
= mp
->txq
+ i
;
1849 if ((int_cause
& (INT_TX_END_0
<< i
)) == 0)
1853 rdl(mp
, TXQ_CURRENT_DESC_PTR(mp
->port_num
, i
));
1854 expected_ptr
= (u32
)txq
->tx_desc_dma
+
1855 txq
->tx_curr_desc
* sizeof(struct tx_desc
);
1857 if (hw_desc_ptr
!= expected_ptr
)
1860 spin_unlock(&mp
->lock
);
1866 static void phy_reset(struct mv643xx_eth_private
*mp
)
1870 smi_reg_read(mp
, mp
->phy_addr
, MII_BMCR
, &data
);
1872 smi_reg_write(mp
, mp
->phy_addr
, MII_BMCR
, data
);
1876 smi_reg_read(mp
, mp
->phy_addr
, MII_BMCR
, &data
);
1877 } while (data
& BMCR_RESET
);
1880 static void port_start(struct mv643xx_eth_private
*mp
)
1886 * Perform PHY reset, if there is a PHY.
1888 if (mp
->phy_addr
!= -1) {
1889 struct ethtool_cmd cmd
;
1891 mv643xx_eth_get_settings(mp
->dev
, &cmd
);
1893 mv643xx_eth_set_settings(mp
->dev
, &cmd
);
1897 * Configure basic link parameters.
1899 pscr
= rdl(mp
, PORT_SERIAL_CONTROL(mp
->port_num
));
1901 pscr
|= SERIAL_PORT_ENABLE
;
1902 wrl(mp
, PORT_SERIAL_CONTROL(mp
->port_num
), pscr
);
1904 pscr
|= DO_NOT_FORCE_LINK_FAIL
;
1905 if (mp
->phy_addr
== -1)
1906 pscr
|= FORCE_LINK_PASS
;
1907 wrl(mp
, PORT_SERIAL_CONTROL(mp
->port_num
), pscr
);
1909 wrl(mp
, SDMA_CONFIG(mp
->port_num
), PORT_SDMA_CONFIG_DEFAULT_VALUE
);
1912 * Configure TX path and queues.
1914 tx_set_rate(mp
, 1000000000, 16777216);
1915 for (i
= 0; i
< 8; i
++) {
1916 struct tx_queue
*txq
= mp
->txq
+ i
;
1918 if ((mp
->txq_mask
& (1 << i
)) == 0)
1921 txq_reset_hw_ptr(txq
);
1922 txq_set_rate(txq
, 1000000000, 16777216);
1923 txq_set_fixed_prio_mode(txq
);
1927 * Add configured unicast address to address filter table.
1929 uc_addr_set(mp
, mp
->dev
->dev_addr
);
1932 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1933 * frames to RX queue #0.
1935 wrl(mp
, PORT_CONFIG(mp
->port_num
), 0x00000000);
1938 * Treat BPDUs as normal multicasts, and disable partition mode.
1940 wrl(mp
, PORT_CONFIG_EXT(mp
->port_num
), 0x00000000);
1943 * Enable the receive queues.
1945 for (i
= 0; i
< 8; i
++) {
1946 struct rx_queue
*rxq
= mp
->rxq
+ i
;
1947 int off
= RXQ_CURRENT_DESC_PTR(mp
->port_num
, i
);
1950 if ((mp
->rxq_mask
& (1 << i
)) == 0)
1953 addr
= (u32
)rxq
->rx_desc_dma
;
1954 addr
+= rxq
->rx_curr_desc
* sizeof(struct rx_desc
);
1961 static void set_rx_coal(struct mv643xx_eth_private
*mp
, unsigned int delay
)
1963 unsigned int coal
= ((mp
->shared
->t_clk
/ 1000000) * delay
) / 64;
1966 val
= rdl(mp
, SDMA_CONFIG(mp
->port_num
));
1967 if (mp
->shared
->extended_rx_coal_limit
) {
1971 val
|= (coal
& 0x8000) << 10;
1972 val
|= (coal
& 0x7fff) << 7;
1977 val
|= (coal
& 0x3fff) << 8;
1979 wrl(mp
, SDMA_CONFIG(mp
->port_num
), val
);
1982 static void set_tx_coal(struct mv643xx_eth_private
*mp
, unsigned int delay
)
1984 unsigned int coal
= ((mp
->shared
->t_clk
/ 1000000) * delay
) / 64;
1988 wrl(mp
, TX_FIFO_URGENT_THRESHOLD(mp
->port_num
), (coal
& 0x3fff) << 4);
1991 static int mv643xx_eth_open(struct net_device
*dev
)
1993 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1997 wrl(mp
, INT_CAUSE(mp
->port_num
), 0);
1998 wrl(mp
, INT_CAUSE_EXT(mp
->port_num
), 0);
1999 rdl(mp
, INT_CAUSE_EXT(mp
->port_num
));
2001 err
= request_irq(dev
->irq
, mv643xx_eth_irq
,
2002 IRQF_SHARED
| IRQF_SAMPLE_RANDOM
,
2005 dev_printk(KERN_ERR
, &dev
->dev
, "can't assign irq\n");
2009 init_mac_tables(mp
);
2011 for (i
= 0; i
< 8; i
++) {
2012 if ((mp
->rxq_mask
& (1 << i
)) == 0)
2015 err
= rxq_init(mp
, i
);
2018 if (mp
->rxq_mask
& (1 << i
))
2019 rxq_deinit(mp
->rxq
+ i
);
2023 rxq_refill(mp
->rxq
+ i
);
2026 for (i
= 0; i
< 8; i
++) {
2027 if ((mp
->txq_mask
& (1 << i
)) == 0)
2030 err
= txq_init(mp
, i
);
2033 if (mp
->txq_mask
& (1 << i
))
2034 txq_deinit(mp
->txq
+ i
);
2039 #ifdef MV643XX_ETH_NAPI
2040 napi_enable(&mp
->napi
);
2043 netif_carrier_off(dev
);
2044 netif_stop_queue(dev
);
2051 wrl(mp
, INT_MASK_EXT(mp
->port_num
),
2052 INT_EXT_LINK
| INT_EXT_PHY
| INT_EXT_TX
);
2054 wrl(mp
, INT_MASK(mp
->port_num
), INT_TX_END
| INT_RX
| INT_EXT
);
2060 for (i
= 0; i
< 8; i
++)
2061 if (mp
->rxq_mask
& (1 << i
))
2062 rxq_deinit(mp
->rxq
+ i
);
2064 free_irq(dev
->irq
, dev
);
2069 static void port_reset(struct mv643xx_eth_private
*mp
)
2074 for (i
= 0; i
< 8; i
++) {
2075 if (mp
->rxq_mask
& (1 << i
))
2076 rxq_disable(mp
->rxq
+ i
);
2077 if (mp
->txq_mask
& (1 << i
))
2078 txq_disable(mp
->txq
+ i
);
2082 u32 ps
= rdl(mp
, PORT_STATUS(mp
->port_num
));
2084 if ((ps
& (TX_IN_PROGRESS
| TX_FIFO_EMPTY
)) == TX_FIFO_EMPTY
)
2089 /* Reset the Enable bit in the Configuration Register */
2090 data
= rdl(mp
, PORT_SERIAL_CONTROL(mp
->port_num
));
2091 data
&= ~(SERIAL_PORT_ENABLE
|
2092 DO_NOT_FORCE_LINK_FAIL
|
2094 wrl(mp
, PORT_SERIAL_CONTROL(mp
->port_num
), data
);
2097 static int mv643xx_eth_stop(struct net_device
*dev
)
2099 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
2102 wrl(mp
, INT_MASK(mp
->port_num
), 0x00000000);
2103 rdl(mp
, INT_MASK(mp
->port_num
));
2105 #ifdef MV643XX_ETH_NAPI
2106 napi_disable(&mp
->napi
);
2108 netif_carrier_off(dev
);
2109 netif_stop_queue(dev
);
2111 free_irq(dev
->irq
, dev
);
2114 mib_counters_update(mp
);
2116 for (i
= 0; i
< 8; i
++) {
2117 if (mp
->rxq_mask
& (1 << i
))
2118 rxq_deinit(mp
->rxq
+ i
);
2119 if (mp
->txq_mask
& (1 << i
))
2120 txq_deinit(mp
->txq
+ i
);
2126 static int mv643xx_eth_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
2128 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
2130 if (mp
->phy_addr
!= -1)
2131 return generic_mii_ioctl(&mp
->mii
, if_mii(ifr
), cmd
, NULL
);
2136 static int mv643xx_eth_change_mtu(struct net_device
*dev
, int new_mtu
)
2138 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
2140 if (new_mtu
< 64 || new_mtu
> 9500)
2144 tx_set_rate(mp
, 1000000000, 16777216);
2146 if (!netif_running(dev
))
2150 * Stop and then re-open the interface. This will allocate RX
2151 * skbs of the new MTU.
2152 * There is a possible danger that the open will not succeed,
2153 * due to memory being full.
2155 mv643xx_eth_stop(dev
);
2156 if (mv643xx_eth_open(dev
)) {
2157 dev_printk(KERN_ERR
, &dev
->dev
,
2158 "fatal error on re-opening device after "
2165 static void tx_timeout_task(struct work_struct
*ugly
)
2167 struct mv643xx_eth_private
*mp
;
2169 mp
= container_of(ugly
, struct mv643xx_eth_private
, tx_timeout_task
);
2170 if (netif_running(mp
->dev
)) {
2171 netif_stop_queue(mp
->dev
);
2176 __txq_maybe_wake(mp
->txq
+ mp
->txq_primary
);
2180 static void mv643xx_eth_tx_timeout(struct net_device
*dev
)
2182 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
2184 dev_printk(KERN_INFO
, &dev
->dev
, "tx timeout\n");
2186 schedule_work(&mp
->tx_timeout_task
);
2189 #ifdef CONFIG_NET_POLL_CONTROLLER
2190 static void mv643xx_eth_netpoll(struct net_device
*dev
)
2192 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
2194 wrl(mp
, INT_MASK(mp
->port_num
), 0x00000000);
2195 rdl(mp
, INT_MASK(mp
->port_num
));
2197 mv643xx_eth_irq(dev
->irq
, dev
);
2199 wrl(mp
, INT_MASK(mp
->port_num
), INT_TX_END
| INT_RX
| INT_EXT
);
2203 static int mv643xx_eth_mdio_read(struct net_device
*dev
, int addr
, int reg
)
2205 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
2208 smi_reg_read(mp
, addr
, reg
, &val
);
2213 static void mv643xx_eth_mdio_write(struct net_device
*dev
, int addr
, int reg
, int val
)
2215 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
2216 smi_reg_write(mp
, addr
, reg
, val
);
2220 /* platform glue ************************************************************/
2222 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private
*msp
,
2223 struct mbus_dram_target_info
*dram
)
2225 void __iomem
*base
= msp
->base
;
2230 for (i
= 0; i
< 6; i
++) {
2231 writel(0, base
+ WINDOW_BASE(i
));
2232 writel(0, base
+ WINDOW_SIZE(i
));
2234 writel(0, base
+ WINDOW_REMAP_HIGH(i
));
2240 for (i
= 0; i
< dram
->num_cs
; i
++) {
2241 struct mbus_dram_window
*cs
= dram
->cs
+ i
;
2243 writel((cs
->base
& 0xffff0000) |
2244 (cs
->mbus_attr
<< 8) |
2245 dram
->mbus_dram_target_id
, base
+ WINDOW_BASE(i
));
2246 writel((cs
->size
- 1) & 0xffff0000, base
+ WINDOW_SIZE(i
));
2248 win_enable
&= ~(1 << i
);
2249 win_protect
|= 3 << (2 * i
);
2252 writel(win_enable
, base
+ WINDOW_BAR_ENABLE
);
2253 msp
->win_protect
= win_protect
;
2256 static void infer_hw_params(struct mv643xx_eth_shared_private
*msp
)
2259 * Check whether we have a 14-bit coal limit field in bits
2260 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2261 * SDMA config register.
2263 writel(0x02000000, msp
->base
+ SDMA_CONFIG(0));
2264 if (readl(msp
->base
+ SDMA_CONFIG(0)) & 0x02000000)
2265 msp
->extended_rx_coal_limit
= 1;
2267 msp
->extended_rx_coal_limit
= 0;
2270 * Check whether the TX rate control registers are in the
2271 * old or the new place.
2273 writel(1, msp
->base
+ TX_BW_MTU_MOVED(0));
2274 if (readl(msp
->base
+ TX_BW_MTU_MOVED(0)) & 1)
2275 msp
->tx_bw_control_moved
= 1;
2277 msp
->tx_bw_control_moved
= 0;
2280 static int mv643xx_eth_shared_probe(struct platform_device
*pdev
)
2282 static int mv643xx_eth_version_printed
= 0;
2283 struct mv643xx_eth_shared_platform_data
*pd
= pdev
->dev
.platform_data
;
2284 struct mv643xx_eth_shared_private
*msp
;
2285 struct resource
*res
;
2288 if (!mv643xx_eth_version_printed
++)
2289 printk(KERN_NOTICE
"MV-643xx 10/100/1000 ethernet "
2290 "driver version %s\n", mv643xx_eth_driver_version
);
2293 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2298 msp
= kmalloc(sizeof(*msp
), GFP_KERNEL
);
2301 memset(msp
, 0, sizeof(*msp
));
2303 msp
->base
= ioremap(res
->start
, res
->end
- res
->start
+ 1);
2304 if (msp
->base
== NULL
)
2307 spin_lock_init(&msp
->phy_lock
);
2310 * (Re-)program MBUS remapping windows if we are asked to.
2312 if (pd
!= NULL
&& pd
->dram
!= NULL
)
2313 mv643xx_eth_conf_mbus_windows(msp
, pd
->dram
);
2316 * Detect hardware parameters.
2318 msp
->t_clk
= (pd
!= NULL
&& pd
->t_clk
!= 0) ? pd
->t_clk
: 133000000;
2319 infer_hw_params(msp
);
2321 platform_set_drvdata(pdev
, msp
);
2331 static int mv643xx_eth_shared_remove(struct platform_device
*pdev
)
2333 struct mv643xx_eth_shared_private
*msp
= platform_get_drvdata(pdev
);
2341 static struct platform_driver mv643xx_eth_shared_driver
= {
2342 .probe
= mv643xx_eth_shared_probe
,
2343 .remove
= mv643xx_eth_shared_remove
,
2345 .name
= MV643XX_ETH_SHARED_NAME
,
2346 .owner
= THIS_MODULE
,
2350 static void phy_addr_set(struct mv643xx_eth_private
*mp
, int phy_addr
)
2352 int addr_shift
= 5 * mp
->port_num
;
2355 data
= rdl(mp
, PHY_ADDR
);
2356 data
&= ~(0x1f << addr_shift
);
2357 data
|= (phy_addr
& 0x1f) << addr_shift
;
2358 wrl(mp
, PHY_ADDR
, data
);
2361 static int phy_addr_get(struct mv643xx_eth_private
*mp
)
2365 data
= rdl(mp
, PHY_ADDR
);
2367 return (data
>> (5 * mp
->port_num
)) & 0x1f;
2370 static void set_params(struct mv643xx_eth_private
*mp
,
2371 struct mv643xx_eth_platform_data
*pd
)
2373 struct net_device
*dev
= mp
->dev
;
2375 if (is_valid_ether_addr(pd
->mac_addr
))
2376 memcpy(dev
->dev_addr
, pd
->mac_addr
, 6);
2378 uc_addr_get(mp
, dev
->dev_addr
);
2380 if (pd
->phy_addr
== -1) {
2381 mp
->shared_smi
= NULL
;
2384 mp
->shared_smi
= mp
->shared
;
2385 if (pd
->shared_smi
!= NULL
)
2386 mp
->shared_smi
= platform_get_drvdata(pd
->shared_smi
);
2388 if (pd
->force_phy_addr
|| pd
->phy_addr
) {
2389 mp
->phy_addr
= pd
->phy_addr
& 0x3f;
2390 phy_addr_set(mp
, mp
->phy_addr
);
2392 mp
->phy_addr
= phy_addr_get(mp
);
2396 mp
->default_rx_ring_size
= DEFAULT_RX_QUEUE_SIZE
;
2397 if (pd
->rx_queue_size
)
2398 mp
->default_rx_ring_size
= pd
->rx_queue_size
;
2399 mp
->rx_desc_sram_addr
= pd
->rx_sram_addr
;
2400 mp
->rx_desc_sram_size
= pd
->rx_sram_size
;
2402 if (pd
->rx_queue_mask
)
2403 mp
->rxq_mask
= pd
->rx_queue_mask
;
2405 mp
->rxq_mask
= 0x01;
2406 mp
->rxq_primary
= fls(mp
->rxq_mask
) - 1;
2408 mp
->default_tx_ring_size
= DEFAULT_TX_QUEUE_SIZE
;
2409 if (pd
->tx_queue_size
)
2410 mp
->default_tx_ring_size
= pd
->tx_queue_size
;
2411 mp
->tx_desc_sram_addr
= pd
->tx_sram_addr
;
2412 mp
->tx_desc_sram_size
= pd
->tx_sram_size
;
2414 if (pd
->tx_queue_mask
)
2415 mp
->txq_mask
= pd
->tx_queue_mask
;
2417 mp
->txq_mask
= 0x01;
2418 mp
->txq_primary
= fls(mp
->txq_mask
) - 1;
2421 static int phy_detect(struct mv643xx_eth_private
*mp
)
2426 smi_reg_read(mp
, mp
->phy_addr
, MII_BMCR
, &data
);
2427 smi_reg_write(mp
, mp
->phy_addr
, MII_BMCR
, data
^ BMCR_ANENABLE
);
2429 smi_reg_read(mp
, mp
->phy_addr
, MII_BMCR
, &data2
);
2430 if (((data
^ data2
) & BMCR_ANENABLE
) == 0)
2433 smi_reg_write(mp
, mp
->phy_addr
, MII_BMCR
, data
);
2438 static int phy_init(struct mv643xx_eth_private
*mp
,
2439 struct mv643xx_eth_platform_data
*pd
)
2441 struct ethtool_cmd cmd
;
2444 err
= phy_detect(mp
);
2446 dev_printk(KERN_INFO
, &mp
->dev
->dev
,
2447 "no PHY detected at addr %d\n", mp
->phy_addr
);
2452 mp
->mii
.phy_id
= mp
->phy_addr
;
2453 mp
->mii
.phy_id_mask
= 0x3f;
2454 mp
->mii
.reg_num_mask
= 0x1f;
2455 mp
->mii
.dev
= mp
->dev
;
2456 mp
->mii
.mdio_read
= mv643xx_eth_mdio_read
;
2457 mp
->mii
.mdio_write
= mv643xx_eth_mdio_write
;
2459 mp
->mii
.supports_gmii
= mii_check_gmii_support(&mp
->mii
);
2461 memset(&cmd
, 0, sizeof(cmd
));
2463 cmd
.port
= PORT_MII
;
2464 cmd
.transceiver
= XCVR_INTERNAL
;
2465 cmd
.phy_address
= mp
->phy_addr
;
2466 if (pd
->speed
== 0) {
2467 cmd
.autoneg
= AUTONEG_ENABLE
;
2468 cmd
.speed
= SPEED_100
;
2469 cmd
.advertising
= ADVERTISED_10baseT_Half
|
2470 ADVERTISED_10baseT_Full
|
2471 ADVERTISED_100baseT_Half
|
2472 ADVERTISED_100baseT_Full
;
2473 if (mp
->mii
.supports_gmii
)
2474 cmd
.advertising
|= ADVERTISED_1000baseT_Full
;
2476 cmd
.autoneg
= AUTONEG_DISABLE
;
2477 cmd
.speed
= pd
->speed
;
2478 cmd
.duplex
= pd
->duplex
;
2481 mv643xx_eth_set_settings(mp
->dev
, &cmd
);
2486 static void init_pscr(struct mv643xx_eth_private
*mp
, int speed
, int duplex
)
2490 pscr
= rdl(mp
, PORT_SERIAL_CONTROL(mp
->port_num
));
2491 if (pscr
& SERIAL_PORT_ENABLE
) {
2492 pscr
&= ~SERIAL_PORT_ENABLE
;
2493 wrl(mp
, PORT_SERIAL_CONTROL(mp
->port_num
), pscr
);
2496 pscr
= MAX_RX_PACKET_9700BYTE
| SERIAL_PORT_CONTROL_RESERVED
;
2497 if (mp
->phy_addr
== -1) {
2498 pscr
|= DISABLE_AUTO_NEG_SPEED_GMII
;
2499 if (speed
== SPEED_1000
)
2500 pscr
|= SET_GMII_SPEED_TO_1000
;
2501 else if (speed
== SPEED_100
)
2502 pscr
|= SET_MII_SPEED_TO_100
;
2504 pscr
|= DISABLE_AUTO_NEG_FOR_FLOW_CTRL
;
2506 pscr
|= DISABLE_AUTO_NEG_FOR_DUPLEX
;
2507 if (duplex
== DUPLEX_FULL
)
2508 pscr
|= SET_FULL_DUPLEX_MODE
;
2511 wrl(mp
, PORT_SERIAL_CONTROL(mp
->port_num
), pscr
);
2514 static int mv643xx_eth_probe(struct platform_device
*pdev
)
2516 struct mv643xx_eth_platform_data
*pd
;
2517 struct mv643xx_eth_private
*mp
;
2518 struct net_device
*dev
;
2519 struct resource
*res
;
2520 DECLARE_MAC_BUF(mac
);
2523 pd
= pdev
->dev
.platform_data
;
2525 dev_printk(KERN_ERR
, &pdev
->dev
,
2526 "no mv643xx_eth_platform_data\n");
2530 if (pd
->shared
== NULL
) {
2531 dev_printk(KERN_ERR
, &pdev
->dev
,
2532 "no mv643xx_eth_platform_data->shared\n");
2536 dev
= alloc_etherdev(sizeof(struct mv643xx_eth_private
));
2540 mp
= netdev_priv(dev
);
2541 platform_set_drvdata(pdev
, mp
);
2543 mp
->shared
= platform_get_drvdata(pd
->shared
);
2544 mp
->port_num
= pd
->port_number
;
2547 #ifdef MV643XX_ETH_NAPI
2548 netif_napi_add(dev
, &mp
->napi
, mv643xx_eth_poll
, 64);
2553 spin_lock_init(&mp
->lock
);
2555 mib_counters_clear(mp
);
2556 INIT_WORK(&mp
->tx_timeout_task
, tx_timeout_task
);
2558 if (mp
->phy_addr
!= -1) {
2559 err
= phy_init(mp
, pd
);
2563 SET_ETHTOOL_OPS(dev
, &mv643xx_eth_ethtool_ops
);
2565 SET_ETHTOOL_OPS(dev
, &mv643xx_eth_ethtool_ops_phyless
);
2567 init_pscr(mp
, pd
->speed
, pd
->duplex
);
2570 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
2572 dev
->irq
= res
->start
;
2574 dev
->hard_start_xmit
= mv643xx_eth_xmit
;
2575 dev
->open
= mv643xx_eth_open
;
2576 dev
->stop
= mv643xx_eth_stop
;
2577 dev
->set_multicast_list
= mv643xx_eth_set_rx_mode
;
2578 dev
->set_mac_address
= mv643xx_eth_set_mac_address
;
2579 dev
->do_ioctl
= mv643xx_eth_ioctl
;
2580 dev
->change_mtu
= mv643xx_eth_change_mtu
;
2581 dev
->tx_timeout
= mv643xx_eth_tx_timeout
;
2582 #ifdef CONFIG_NET_POLL_CONTROLLER
2583 dev
->poll_controller
= mv643xx_eth_netpoll
;
2585 dev
->watchdog_timeo
= 2 * HZ
;
2588 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
2590 * Zero copy can only work if we use Discovery II memory. Else, we will
2591 * have to map the buffers to ISA memory which is only 16 MB
2593 dev
->features
= NETIF_F_SG
| NETIF_F_IP_CSUM
;
2594 dev
->vlan_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
;
2597 SET_NETDEV_DEV(dev
, &pdev
->dev
);
2599 if (mp
->shared
->win_protect
)
2600 wrl(mp
, WINDOW_PROTECT(mp
->port_num
), mp
->shared
->win_protect
);
2602 err
= register_netdev(dev
);
2606 dev_printk(KERN_NOTICE
, &dev
->dev
, "port %d with MAC address %s\n",
2607 mp
->port_num
, print_mac(mac
, dev
->dev_addr
));
2609 if (dev
->features
& NETIF_F_SG
)
2610 dev_printk(KERN_NOTICE
, &dev
->dev
, "scatter/gather enabled\n");
2612 if (dev
->features
& NETIF_F_IP_CSUM
)
2613 dev_printk(KERN_NOTICE
, &dev
->dev
, "tx checksum offload\n");
2615 #ifdef MV643XX_ETH_NAPI
2616 dev_printk(KERN_NOTICE
, &dev
->dev
, "napi enabled\n");
2619 if (mp
->tx_desc_sram_size
> 0)
2620 dev_printk(KERN_NOTICE
, &dev
->dev
, "configured with sram\n");
2630 static int mv643xx_eth_remove(struct platform_device
*pdev
)
2632 struct mv643xx_eth_private
*mp
= platform_get_drvdata(pdev
);
2634 unregister_netdev(mp
->dev
);
2635 flush_scheduled_work();
2636 free_netdev(mp
->dev
);
2638 platform_set_drvdata(pdev
, NULL
);
2643 static void mv643xx_eth_shutdown(struct platform_device
*pdev
)
2645 struct mv643xx_eth_private
*mp
= platform_get_drvdata(pdev
);
2647 /* Mask all interrupts on ethernet port */
2648 wrl(mp
, INT_MASK(mp
->port_num
), 0);
2649 rdl(mp
, INT_MASK(mp
->port_num
));
2651 if (netif_running(mp
->dev
))
2655 static struct platform_driver mv643xx_eth_driver
= {
2656 .probe
= mv643xx_eth_probe
,
2657 .remove
= mv643xx_eth_remove
,
2658 .shutdown
= mv643xx_eth_shutdown
,
2660 .name
= MV643XX_ETH_NAME
,
2661 .owner
= THIS_MODULE
,
2665 static int __init
mv643xx_eth_init_module(void)
2669 rc
= platform_driver_register(&mv643xx_eth_shared_driver
);
2671 rc
= platform_driver_register(&mv643xx_eth_driver
);
2673 platform_driver_unregister(&mv643xx_eth_shared_driver
);
2678 module_init(mv643xx_eth_init_module
);
2680 static void __exit
mv643xx_eth_cleanup_module(void)
2682 platform_driver_unregister(&mv643xx_eth_driver
);
2683 platform_driver_unregister(&mv643xx_eth_shared_driver
);
2685 module_exit(mv643xx_eth_cleanup_module
);
2687 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2688 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
2689 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2690 MODULE_LICENSE("GPL");
2691 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME
);
2692 MODULE_ALIAS("platform:" MV643XX_ETH_NAME
);