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netxen: update driver version
[deliverable/linux.git] / drivers / net / netxen / netxen_nic.h
1 /*
2 * Copyright (C) 2003 - 2006 NetXen, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
22 *
23 * Contact Information:
24 * info@netxen.com
25 * NetXen,
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
28 */
29
30 #ifndef _NETXEN_NIC_H_
31 #define _NETXEN_NIC_H_
32
33 #include <linux/module.h>
34 #include <linux/kernel.h>
35 #include <linux/types.h>
36 #include <linux/compiler.h>
37 #include <linux/slab.h>
38 #include <linux/delay.h>
39 #include <linux/init.h>
40 #include <linux/ioport.h>
41 #include <linux/pci.h>
42 #include <linux/netdevice.h>
43 #include <linux/etherdevice.h>
44 #include <linux/ip.h>
45 #include <linux/in.h>
46 #include <linux/tcp.h>
47 #include <linux/skbuff.h>
48 #include <linux/version.h>
49
50 #include <linux/ethtool.h>
51 #include <linux/mii.h>
52 #include <linux/interrupt.h>
53 #include <linux/timer.h>
54
55 #include <linux/mm.h>
56 #include <linux/mman.h>
57 #include <linux/vmalloc.h>
58
59 #include <asm/system.h>
60 #include <asm/io.h>
61 #include <asm/byteorder.h>
62 #include <asm/uaccess.h>
63 #include <asm/pgtable.h>
64
65 #include "netxen_nic_hw.h"
66
67 #define _NETXEN_NIC_LINUX_MAJOR 4
68 #define _NETXEN_NIC_LINUX_MINOR 0
69 #define _NETXEN_NIC_LINUX_SUBVERSION 11
70 #define NETXEN_NIC_LINUX_VERSIONID "4.0.11"
71
72 #define NETXEN_VERSION_CODE(a, b, c) (((a) << 16) + ((b) << 8) + (c))
73
74 #define NETXEN_NUM_FLASH_SECTORS (64)
75 #define NETXEN_FLASH_SECTOR_SIZE (64 * 1024)
76 #define NETXEN_FLASH_TOTAL_SIZE (NETXEN_NUM_FLASH_SECTORS \
77 * NETXEN_FLASH_SECTOR_SIZE)
78
79 #define PHAN_VENDOR_ID 0x4040
80
81 #define RCV_DESC_RINGSIZE \
82 (sizeof(struct rcv_desc) * adapter->max_rx_desc_count)
83 #define STATUS_DESC_RINGSIZE \
84 (sizeof(struct status_desc)* adapter->max_rx_desc_count)
85 #define LRO_DESC_RINGSIZE \
86 (sizeof(rcvDesc_t) * adapter->max_lro_rx_desc_count)
87 #define TX_RINGSIZE \
88 (sizeof(struct netxen_cmd_buffer) * adapter->max_tx_desc_count)
89 #define RCV_BUFFSIZE \
90 (sizeof(struct netxen_rx_buffer) * rds_ring->max_rx_desc_count)
91 #define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a)))
92
93 #define NETXEN_NETDEV_STATUS 0x1
94 #define NETXEN_RCV_PRODUCER_OFFSET 0
95 #define NETXEN_RCV_PEG_DB_ID 2
96 #define NETXEN_HOST_DUMMY_DMA_SIZE 1024
97 #define FLASH_SUCCESS 0
98
99 #define ADDR_IN_WINDOW1(off) \
100 ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0
101
102 /*
103 * normalize a 64MB crb address to 32MB PCI window
104 * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1
105 */
106 #define NETXEN_CRB_NORMAL(reg) \
107 ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST)
108
109 #define NETXEN_CRB_NORMALIZE(adapter, reg) \
110 pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg))
111
112 #define DB_NORMALIZE(adapter, off) \
113 (adapter->ahw.db_base + (off))
114
115 #define NX_P2_C0 0x24
116 #define NX_P2_C1 0x25
117 #define NX_P3_A0 0x30
118 #define NX_P3_A2 0x30
119 #define NX_P3_B0 0x40
120 #define NX_P3_B1 0x41
121
122 #define NX_IS_REVISION_P2(REVISION) (REVISION <= NX_P2_C1)
123 #define NX_IS_REVISION_P3(REVISION) (REVISION >= NX_P3_A0)
124
125 #define FIRST_PAGE_GROUP_START 0
126 #define FIRST_PAGE_GROUP_END 0x100000
127
128 #define SECOND_PAGE_GROUP_START 0x6000000
129 #define SECOND_PAGE_GROUP_END 0x68BC000
130
131 #define THIRD_PAGE_GROUP_START 0x70E4000
132 #define THIRD_PAGE_GROUP_END 0x8000000
133
134 #define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START
135 #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START
136 #define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START
137
138 #define P2_MAX_MTU (8000)
139 #define P3_MAX_MTU (9600)
140 #define NX_ETHERMTU 1500
141 #define NX_MAX_ETHERHDR 32 /* This contains some padding */
142
143 #define NX_RX_NORMAL_BUF_MAX_LEN (NX_MAX_ETHERHDR + NX_ETHERMTU)
144 #define NX_P2_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P2_MAX_MTU)
145 #define NX_P3_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P3_MAX_MTU)
146 #define NX_CT_DEFAULT_RX_BUF_LEN 2048
147
148 #define MAX_RX_BUFFER_LENGTH 1760
149 #define MAX_RX_JUMBO_BUFFER_LENGTH 8062
150 #define MAX_RX_LRO_BUFFER_LENGTH ((48*1024)-512)
151 #define RX_DMA_MAP_LEN (MAX_RX_BUFFER_LENGTH - 2)
152 #define RX_JUMBO_DMA_MAP_LEN \
153 (MAX_RX_JUMBO_BUFFER_LENGTH - 2)
154 #define RX_LRO_DMA_MAP_LEN (MAX_RX_LRO_BUFFER_LENGTH - 2)
155
156 /*
157 * Maximum number of ring contexts
158 */
159 #define MAX_RING_CTX 1
160
161 /* Opcodes to be used with the commands */
162 #define TX_ETHER_PKT 0x01
163 #define TX_TCP_PKT 0x02
164 #define TX_UDP_PKT 0x03
165 #define TX_IP_PKT 0x04
166 #define TX_TCP_LSO 0x05
167 #define TX_TCP_LSO6 0x06
168 #define TX_IPSEC 0x07
169 #define TX_IPSEC_CMD 0x0a
170 #define TX_TCPV6_PKT 0x0b
171 #define TX_UDPV6_PKT 0x0c
172
173 /* The following opcodes are for internal consumption. */
174 #define NETXEN_CONTROL_OP 0x10
175 #define PEGNET_REQUEST 0x11
176
177 #define MAX_NUM_CARDS 4
178
179 #define MAX_BUFFERS_PER_CMD 32
180
181 /*
182 * Following are the states of the Phantom. Phantom will set them and
183 * Host will read to check if the fields are correct.
184 */
185 #define PHAN_INITIALIZE_START 0xff00
186 #define PHAN_INITIALIZE_FAILED 0xffff
187 #define PHAN_INITIALIZE_COMPLETE 0xff01
188
189 /* Host writes the following to notify that it has done the init-handshake */
190 #define PHAN_INITIALIZE_ACK 0xf00f
191
192 #define NUM_RCV_DESC_RINGS 3 /* No of Rcv Descriptor contexts */
193
194 /* descriptor types */
195 #define RCV_DESC_NORMAL 0x01
196 #define RCV_DESC_JUMBO 0x02
197 #define RCV_DESC_LRO 0x04
198 #define RCV_DESC_NORMAL_CTXID 0
199 #define RCV_DESC_JUMBO_CTXID 1
200 #define RCV_DESC_LRO_CTXID 2
201
202 #define RCV_DESC_TYPE(ID) \
203 ((ID == RCV_DESC_JUMBO_CTXID) \
204 ? RCV_DESC_JUMBO \
205 : ((ID == RCV_DESC_LRO_CTXID) \
206 ? RCV_DESC_LRO : \
207 (RCV_DESC_NORMAL)))
208
209 #define MAX_CMD_DESCRIPTORS 4096
210 #define MAX_RCV_DESCRIPTORS 16384
211 #define MAX_CMD_DESCRIPTORS_HOST (MAX_CMD_DESCRIPTORS / 4)
212 #define MAX_RCV_DESCRIPTORS_1G (MAX_RCV_DESCRIPTORS / 4)
213 #define MAX_RCV_DESCRIPTORS_10G 8192
214 #define MAX_JUMBO_RCV_DESCRIPTORS 1024
215 #define MAX_LRO_RCV_DESCRIPTORS 64
216 #define MAX_RCVSTATUS_DESCRIPTORS MAX_RCV_DESCRIPTORS
217 #define MAX_JUMBO_RCV_DESC MAX_JUMBO_RCV_DESCRIPTORS
218 #define MAX_RCV_DESC MAX_RCV_DESCRIPTORS
219 #define MAX_RCVSTATUS_DESC MAX_RCV_DESCRIPTORS
220 #define MAX_EPG_DESCRIPTORS (MAX_CMD_DESCRIPTORS * 8)
221 #define NUM_RCV_DESC (MAX_RCV_DESC + MAX_JUMBO_RCV_DESCRIPTORS + \
222 MAX_LRO_RCV_DESCRIPTORS)
223 #define MIN_TX_COUNT 4096
224 #define MIN_RX_COUNT 4096
225 #define NETXEN_CTX_SIGNATURE 0xdee0
226 #define NETXEN_RCV_PRODUCER(ringid) (ringid)
227 #define MAX_FRAME_SIZE 0x10000 /* 64K MAX size for LSO */
228
229 #define PHAN_PEG_RCV_INITIALIZED 0xff01
230 #define PHAN_PEG_RCV_START_INITIALIZE 0xff00
231
232 #define get_next_index(index, length) \
233 (((index) + 1) & ((length) - 1))
234
235 #define get_index_range(index,length,count) \
236 (((index) + (count)) & ((length) - 1))
237
238 #define MPORT_SINGLE_FUNCTION_MODE 0x1111
239 #define MPORT_MULTI_FUNCTION_MODE 0x2222
240
241 #include "netxen_nic_phan_reg.h"
242
243 /*
244 * NetXen host-peg signal message structure
245 *
246 * Bit 0-1 : peg_id => 0x2 for tx and 01 for rx
247 * Bit 2 : priv_id => must be 1
248 * Bit 3-17 : count => for doorbell
249 * Bit 18-27 : ctx_id => Context id
250 * Bit 28-31 : opcode
251 */
252
253 typedef u32 netxen_ctx_msg;
254
255 #define netxen_set_msg_peg_id(config_word, val) \
256 ((config_word) &= ~3, (config_word) |= val & 3)
257 #define netxen_set_msg_privid(config_word) \
258 ((config_word) |= 1 << 2)
259 #define netxen_set_msg_count(config_word, val) \
260 ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3)
261 #define netxen_set_msg_ctxid(config_word, val) \
262 ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18)
263 #define netxen_set_msg_opcode(config_word, val) \
264 ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28)
265
266 struct netxen_rcv_context {
267 __le64 rcv_ring_addr;
268 __le32 rcv_ring_size;
269 __le32 rsrvd;
270 };
271
272 struct netxen_ring_ctx {
273
274 /* one command ring */
275 __le64 cmd_consumer_offset;
276 __le64 cmd_ring_addr;
277 __le32 cmd_ring_size;
278 __le32 rsrvd;
279
280 /* three receive rings */
281 struct netxen_rcv_context rcv_ctx[3];
282
283 /* one status ring */
284 __le64 sts_ring_addr;
285 __le32 sts_ring_size;
286
287 __le32 ctx_id;
288 } __attribute__ ((aligned(64)));
289
290 /*
291 * Following data structures describe the descriptors that will be used.
292 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
293 * we are doing LSO (above the 1500 size packet) only.
294 */
295
296 /*
297 * The size of reference handle been changed to 16 bits to pass the MSS fields
298 * for the LSO packet
299 */
300
301 #define FLAGS_CHECKSUM_ENABLED 0x01
302 #define FLAGS_LSO_ENABLED 0x02
303 #define FLAGS_IPSEC_SA_ADD 0x04
304 #define FLAGS_IPSEC_SA_DELETE 0x08
305 #define FLAGS_VLAN_TAGGED 0x10
306
307 #define netxen_set_cmd_desc_port(cmd_desc, var) \
308 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
309 #define netxen_set_cmd_desc_ctxid(cmd_desc, var) \
310 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
311
312 #define netxen_set_cmd_desc_flags(cmd_desc, val) \
313 (cmd_desc)->flags_opcode = ((cmd_desc)->flags_opcode & \
314 ~cpu_to_le16(0x7f)) | cpu_to_le16((val) & 0x7f)
315 #define netxen_set_cmd_desc_opcode(cmd_desc, val) \
316 (cmd_desc)->flags_opcode = ((cmd_desc)->flags_opcode & \
317 ~cpu_to_le16((u16)0x3f << 7)) | cpu_to_le16(((val) & 0x3f) << 7)
318
319 #define netxen_set_cmd_desc_num_of_buff(cmd_desc, val) \
320 (cmd_desc)->num_of_buffers_total_length = \
321 ((cmd_desc)->num_of_buffers_total_length & \
322 ~cpu_to_le32(0xff)) | cpu_to_le32((val) & 0xff)
323 #define netxen_set_cmd_desc_totallength(cmd_desc, val) \
324 (cmd_desc)->num_of_buffers_total_length = \
325 ((cmd_desc)->num_of_buffers_total_length & \
326 ~cpu_to_le32((u32)0xffffff << 8)) | \
327 cpu_to_le32(((val) & 0xffffff) << 8)
328
329 #define netxen_get_cmd_desc_opcode(cmd_desc) \
330 ((le16_to_cpu((cmd_desc)->flags_opcode) >> 7) & 0x003f)
331 #define netxen_get_cmd_desc_totallength(cmd_desc) \
332 ((le32_to_cpu((cmd_desc)->num_of_buffers_total_length) >> 8) & 0xffffff)
333
334 struct cmd_desc_type0 {
335 u8 tcp_hdr_offset; /* For LSO only */
336 u8 ip_hdr_offset; /* For LSO only */
337 /* Bit pattern: 0-6 flags, 7-12 opcode, 13-15 unused */
338 __le16 flags_opcode;
339 /* Bit pattern: 0-7 total number of segments,
340 8-31 Total size of the packet */
341 __le32 num_of_buffers_total_length;
342 union {
343 struct {
344 __le32 addr_low_part2;
345 __le32 addr_high_part2;
346 };
347 __le64 addr_buffer2;
348 };
349
350 __le16 reference_handle; /* changed to u16 to add mss */
351 __le16 mss; /* passed by NDIS_PACKET for LSO */
352 /* Bit pattern 0-3 port, 0-3 ctx id */
353 u8 port_ctxid;
354 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
355 __le16 conn_id; /* IPSec offoad only */
356
357 union {
358 struct {
359 __le32 addr_low_part3;
360 __le32 addr_high_part3;
361 };
362 __le64 addr_buffer3;
363 };
364 union {
365 struct {
366 __le32 addr_low_part1;
367 __le32 addr_high_part1;
368 };
369 __le64 addr_buffer1;
370 };
371
372 __le16 buffer1_length;
373 __le16 buffer2_length;
374 __le16 buffer3_length;
375 __le16 buffer4_length;
376
377 union {
378 struct {
379 __le32 addr_low_part4;
380 __le32 addr_high_part4;
381 };
382 __le64 addr_buffer4;
383 };
384
385 __le64 unused;
386
387 } __attribute__ ((aligned(64)));
388
389 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
390 struct rcv_desc {
391 __le16 reference_handle;
392 __le16 reserved;
393 __le32 buffer_length; /* allocated buffer length (usually 2K) */
394 __le64 addr_buffer;
395 };
396
397 /* opcode field in status_desc */
398 #define NETXEN_NIC_RXPKT_DESC 0x04
399 #define NETXEN_OLD_RXPKT_DESC 0x3f
400
401 /* for status field in status_desc */
402 #define STATUS_NEED_CKSUM (1)
403 #define STATUS_CKSUM_OK (2)
404
405 /* owner bits of status_desc */
406 #define STATUS_OWNER_HOST (0x1)
407 #define STATUS_OWNER_PHANTOM (0x2)
408
409 #define NETXEN_PROT_IP (1)
410 #define NETXEN_PROT_UNKNOWN (0)
411
412 /* Note: sizeof(status_desc) should always be a mutliple of 2 */
413
414 #define netxen_get_sts_desc_lro_cnt(status_desc) \
415 ((status_desc)->lro & 0x7F)
416 #define netxen_get_sts_desc_lro_last_frag(status_desc) \
417 (((status_desc)->lro & 0x80) >> 7)
418
419 #define netxen_get_sts_port(sts_data) \
420 ((sts_data) & 0x0F)
421 #define netxen_get_sts_status(sts_data) \
422 (((sts_data) >> 4) & 0x0F)
423 #define netxen_get_sts_type(sts_data) \
424 (((sts_data) >> 8) & 0x0F)
425 #define netxen_get_sts_totallength(sts_data) \
426 (((sts_data) >> 12) & 0xFFFF)
427 #define netxen_get_sts_refhandle(sts_data) \
428 (((sts_data) >> 28) & 0xFFFF)
429 #define netxen_get_sts_prot(sts_data) \
430 (((sts_data) >> 44) & 0x0F)
431 #define netxen_get_sts_pkt_offset(sts_data) \
432 (((sts_data) >> 48) & 0x1F)
433 #define netxen_get_sts_opcode(sts_data) \
434 (((sts_data) >> 58) & 0x03F)
435
436 #define netxen_get_sts_owner(status_desc) \
437 ((le64_to_cpu((status_desc)->status_desc_data) >> 56) & 0x03)
438 #define netxen_set_sts_owner(status_desc, val) { \
439 (status_desc)->status_desc_data = \
440 ((status_desc)->status_desc_data & \
441 ~cpu_to_le64(0x3ULL << 56)) | \
442 cpu_to_le64((u64)((val) & 0x3) << 56); \
443 }
444
445 struct status_desc {
446 /* Bit pattern: 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
447 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
448 53-55 desc_cnt, 56-57 owner, 58-63 opcode
449 */
450 __le64 status_desc_data;
451 union {
452 struct {
453 __le32 hash_value;
454 u8 hash_type;
455 u8 msg_type;
456 u8 unused;
457 union {
458 /* Bit pattern: 0-6 lro_count indicates frag
459 * sequence, 7 last_frag indicates last frag
460 */
461 u8 lro;
462
463 /* chained buffers */
464 u8 nr_frags;
465 };
466 };
467 struct {
468 __le16 frag_handles[4];
469 };
470 };
471 } __attribute__ ((aligned(16)));
472
473 enum {
474 NETXEN_RCV_PEG_0 = 0,
475 NETXEN_RCV_PEG_1
476 };
477 /* The version of the main data structure */
478 #define NETXEN_BDINFO_VERSION 1
479
480 /* Magic number to let user know flash is programmed */
481 #define NETXEN_BDINFO_MAGIC 0x12345678
482
483 /* Max number of Gig ports on a Phantom board */
484 #define NETXEN_MAX_PORTS 4
485
486 typedef enum {
487 NETXEN_BRDTYPE_P1_BD = 0x0000,
488 NETXEN_BRDTYPE_P1_SB = 0x0001,
489 NETXEN_BRDTYPE_P1_SMAX = 0x0002,
490 NETXEN_BRDTYPE_P1_SOCK = 0x0003,
491
492 NETXEN_BRDTYPE_P2_SOCK_31 = 0x0008,
493 NETXEN_BRDTYPE_P2_SOCK_35 = 0x0009,
494 NETXEN_BRDTYPE_P2_SB35_4G = 0x000a,
495 NETXEN_BRDTYPE_P2_SB31_10G = 0x000b,
496 NETXEN_BRDTYPE_P2_SB31_2G = 0x000c,
497
498 NETXEN_BRDTYPE_P2_SB31_10G_IMEZ = 0x000d,
499 NETXEN_BRDTYPE_P2_SB31_10G_HMEZ = 0x000e,
500 NETXEN_BRDTYPE_P2_SB31_10G_CX4 = 0x000f,
501
502 NETXEN_BRDTYPE_P3_REF_QG = 0x0021,
503 NETXEN_BRDTYPE_P3_HMEZ = 0x0022,
504 NETXEN_BRDTYPE_P3_10G_CX4_LP = 0x0023,
505 NETXEN_BRDTYPE_P3_4_GB = 0x0024,
506 NETXEN_BRDTYPE_P3_IMEZ = 0x0025,
507 NETXEN_BRDTYPE_P3_10G_SFP_PLUS = 0x0026,
508 NETXEN_BRDTYPE_P3_10000_BASE_T = 0x0027,
509 NETXEN_BRDTYPE_P3_XG_LOM = 0x0028,
510 NETXEN_BRDTYPE_P3_4_GB_MM = 0x0029,
511 NETXEN_BRDTYPE_P3_10G_SFP_CT = 0x002a,
512 NETXEN_BRDTYPE_P3_10G_SFP_QT = 0x002b,
513 NETXEN_BRDTYPE_P3_10G_CX4 = 0x0031,
514 NETXEN_BRDTYPE_P3_10G_XFP = 0x0032
515
516 } netxen_brdtype_t;
517
518 typedef enum {
519 NETXEN_BRDMFG_INVENTEC = 1
520 } netxen_brdmfg;
521
522 typedef enum {
523 MEM_ORG_128Mbx4 = 0x0, /* DDR1 only */
524 MEM_ORG_128Mbx8 = 0x1, /* DDR1 only */
525 MEM_ORG_128Mbx16 = 0x2, /* DDR1 only */
526 MEM_ORG_256Mbx4 = 0x3,
527 MEM_ORG_256Mbx8 = 0x4,
528 MEM_ORG_256Mbx16 = 0x5,
529 MEM_ORG_512Mbx4 = 0x6,
530 MEM_ORG_512Mbx8 = 0x7,
531 MEM_ORG_512Mbx16 = 0x8,
532 MEM_ORG_1Gbx4 = 0x9,
533 MEM_ORG_1Gbx8 = 0xa,
534 MEM_ORG_1Gbx16 = 0xb,
535 MEM_ORG_2Gbx4 = 0xc,
536 MEM_ORG_2Gbx8 = 0xd,
537 MEM_ORG_2Gbx16 = 0xe,
538 MEM_ORG_128Mbx32 = 0x10002, /* GDDR only */
539 MEM_ORG_256Mbx32 = 0x10005 /* GDDR only */
540 } netxen_mn_mem_org_t;
541
542 typedef enum {
543 MEM_ORG_512Kx36 = 0x0,
544 MEM_ORG_1Mx36 = 0x1,
545 MEM_ORG_2Mx36 = 0x2
546 } netxen_sn_mem_org_t;
547
548 typedef enum {
549 MEM_DEPTH_4MB = 0x1,
550 MEM_DEPTH_8MB = 0x2,
551 MEM_DEPTH_16MB = 0x3,
552 MEM_DEPTH_32MB = 0x4,
553 MEM_DEPTH_64MB = 0x5,
554 MEM_DEPTH_128MB = 0x6,
555 MEM_DEPTH_256MB = 0x7,
556 MEM_DEPTH_512MB = 0x8,
557 MEM_DEPTH_1GB = 0x9,
558 MEM_DEPTH_2GB = 0xa,
559 MEM_DEPTH_4GB = 0xb,
560 MEM_DEPTH_8GB = 0xc,
561 MEM_DEPTH_16GB = 0xd,
562 MEM_DEPTH_32GB = 0xe
563 } netxen_mem_depth_t;
564
565 struct netxen_board_info {
566 u32 header_version;
567
568 u32 board_mfg;
569 u32 board_type;
570 u32 board_num;
571 u32 chip_id;
572 u32 chip_minor;
573 u32 chip_major;
574 u32 chip_pkg;
575 u32 chip_lot;
576
577 u32 port_mask; /* available niu ports */
578 u32 peg_mask; /* available pegs */
579 u32 icache_ok; /* can we run with icache? */
580 u32 dcache_ok; /* can we run with dcache? */
581 u32 casper_ok;
582
583 u32 mac_addr_lo_0;
584 u32 mac_addr_lo_1;
585 u32 mac_addr_lo_2;
586 u32 mac_addr_lo_3;
587
588 /* MN-related config */
589 u32 mn_sync_mode; /* enable/ sync shift cclk/ sync shift mclk */
590 u32 mn_sync_shift_cclk;
591 u32 mn_sync_shift_mclk;
592 u32 mn_wb_en;
593 u32 mn_crystal_freq; /* in MHz */
594 u32 mn_speed; /* in MHz */
595 u32 mn_org;
596 u32 mn_depth;
597 u32 mn_ranks_0; /* ranks per slot */
598 u32 mn_ranks_1; /* ranks per slot */
599 u32 mn_rd_latency_0;
600 u32 mn_rd_latency_1;
601 u32 mn_rd_latency_2;
602 u32 mn_rd_latency_3;
603 u32 mn_rd_latency_4;
604 u32 mn_rd_latency_5;
605 u32 mn_rd_latency_6;
606 u32 mn_rd_latency_7;
607 u32 mn_rd_latency_8;
608 u32 mn_dll_val[18];
609 u32 mn_mode_reg; /* MIU DDR Mode Register */
610 u32 mn_ext_mode_reg; /* MIU DDR Extended Mode Register */
611 u32 mn_timing_0; /* MIU Memory Control Timing Rgister */
612 u32 mn_timing_1; /* MIU Extended Memory Ctrl Timing Register */
613 u32 mn_timing_2; /* MIU Extended Memory Ctrl Timing2 Register */
614
615 /* SN-related config */
616 u32 sn_sync_mode; /* enable/ sync shift cclk / sync shift mclk */
617 u32 sn_pt_mode; /* pass through mode */
618 u32 sn_ecc_en;
619 u32 sn_wb_en;
620 u32 sn_crystal_freq;
621 u32 sn_speed;
622 u32 sn_org;
623 u32 sn_depth;
624 u32 sn_dll_tap;
625 u32 sn_rd_latency;
626
627 u32 mac_addr_hi_0;
628 u32 mac_addr_hi_1;
629 u32 mac_addr_hi_2;
630 u32 mac_addr_hi_3;
631
632 u32 magic; /* indicates flash has been initialized */
633
634 u32 mn_rdimm;
635 u32 mn_dll_override;
636
637 };
638
639 #define FLASH_NUM_PORTS (4)
640
641 struct netxen_flash_mac_addr {
642 u32 flash_addr[32];
643 };
644
645 struct netxen_user_old_info {
646 u8 flash_md5[16];
647 u8 crbinit_md5[16];
648 u8 brdcfg_md5[16];
649 /* bootloader */
650 u32 bootld_version;
651 u32 bootld_size;
652 u8 bootld_md5[16];
653 /* image */
654 u32 image_version;
655 u32 image_size;
656 u8 image_md5[16];
657 /* primary image status */
658 u32 primary_status;
659 u32 secondary_present;
660
661 /* MAC address , 4 ports */
662 struct netxen_flash_mac_addr mac_addr[FLASH_NUM_PORTS];
663 };
664 #define FLASH_NUM_MAC_PER_PORT 32
665 struct netxen_user_info {
666 u8 flash_md5[16 * 64];
667 /* bootloader */
668 u32 bootld_version;
669 u32 bootld_size;
670 /* image */
671 u32 image_version;
672 u32 image_size;
673 /* primary image status */
674 u32 primary_status;
675 u32 secondary_present;
676
677 /* MAC address , 4 ports, 32 address per port */
678 u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
679 u32 sub_sys_id;
680 u8 serial_num[32];
681
682 /* Any user defined data */
683 };
684
685 /*
686 * Flash Layout - new format.
687 */
688 struct netxen_new_user_info {
689 u8 flash_md5[16 * 64];
690 /* bootloader */
691 u32 bootld_version;
692 u32 bootld_size;
693 /* image */
694 u32 image_version;
695 u32 image_size;
696 /* primary image status */
697 u32 primary_status;
698 u32 secondary_present;
699
700 /* MAC address , 4 ports, 32 address per port */
701 u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
702 u32 sub_sys_id;
703 u8 serial_num[32];
704
705 /* Any user defined data */
706 };
707
708 #define SECONDARY_IMAGE_PRESENT 0xb3b4b5b6
709 #define SECONDARY_IMAGE_ABSENT 0xffffffff
710 #define PRIMARY_IMAGE_GOOD 0x5a5a5a5a
711 #define PRIMARY_IMAGE_BAD 0xffffffff
712
713 /* Flash memory map */
714 typedef enum {
715 NETXEN_CRBINIT_START = 0, /* Crbinit section */
716 NETXEN_BRDCFG_START = 0x4000, /* board config */
717 NETXEN_INITCODE_START = 0x6000, /* pegtune code */
718 NETXEN_BOOTLD_START = 0x10000, /* bootld */
719 NETXEN_IMAGE_START = 0x43000, /* compressed image */
720 NETXEN_SECONDARY_START = 0x200000, /* backup images */
721 NETXEN_PXE_START = 0x3E0000, /* user defined region */
722 NETXEN_USER_START = 0x3E8000, /* User defined region for new boards */
723 NETXEN_FIXED_START = 0x3F0000 /* backup of crbinit */
724 } netxen_flash_map_t;
725
726 #define NETXEN_USER_START_OLD NETXEN_PXE_START /* for backward compatibility */
727
728 #define NETXEN_FLASH_START (NETXEN_CRBINIT_START)
729 #define NETXEN_INIT_SECTOR (0)
730 #define NETXEN_PRIMARY_START (NETXEN_BOOTLD_START)
731 #define NETXEN_FLASH_CRBINIT_SIZE (0x4000)
732 #define NETXEN_FLASH_BRDCFG_SIZE (sizeof(struct netxen_board_info))
733 #define NETXEN_FLASH_USER_SIZE (sizeof(struct netxen_user_info)/sizeof(u32))
734 #define NETXEN_FLASH_SECONDARY_SIZE (NETXEN_USER_START-NETXEN_SECONDARY_START)
735 #define NETXEN_NUM_PRIMARY_SECTORS (0x20)
736 #define NETXEN_NUM_CONFIG_SECTORS (1)
737 #define PFX "NetXen: "
738 extern char netxen_nic_driver_name[];
739
740 /* Note: Make sure to not call this before adapter->port is valid */
741 #if !defined(NETXEN_DEBUG)
742 #define DPRINTK(klevel, fmt, args...) do { \
743 } while (0)
744 #else
745 #define DPRINTK(klevel, fmt, args...) do { \
746 printk(KERN_##klevel PFX "%s: %s: " fmt, __FUNCTION__,\
747 (adapter != NULL && adapter->netdev != NULL) ? \
748 adapter->netdev->name : NULL, \
749 ## args); } while(0)
750 #endif
751
752 /* Number of status descriptors to handle per interrupt */
753 #define MAX_STATUS_HANDLE (128)
754
755 /*
756 * netxen_skb_frag{} is to contain mapping info for each SG list. This
757 * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}.
758 */
759 struct netxen_skb_frag {
760 u64 dma;
761 u32 length;
762 };
763
764 #define _netxen_set_bits(config_word, start, bits, val) {\
765 unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start));\
766 unsigned long long __tvalue = (val); \
767 (config_word) &= ~__tmask; \
768 (config_word) |= (((__tvalue) << (start)) & __tmask); \
769 }
770
771 #define _netxen_clear_bits(config_word, start, bits) {\
772 unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start)); \
773 (config_word) &= ~__tmask; \
774 }
775
776 /* Following defines are for the state of the buffers */
777 #define NETXEN_BUFFER_FREE 0
778 #define NETXEN_BUFFER_BUSY 1
779
780 /*
781 * There will be one netxen_buffer per skb packet. These will be
782 * used to save the dma info for pci_unmap_page()
783 */
784 struct netxen_cmd_buffer {
785 struct sk_buff *skb;
786 struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1];
787 u32 total_length;
788 u32 mss;
789 u16 port;
790 u8 cmd;
791 u8 frag_count;
792 unsigned long time_stamp;
793 u32 state;
794 };
795
796 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
797 struct netxen_rx_buffer {
798 struct list_head list;
799 struct sk_buff *skb;
800 u64 dma;
801 u16 ref_handle;
802 u16 state;
803 u32 lro_expected_frags;
804 u32 lro_current_frags;
805 u32 lro_length;
806 };
807
808 /* Board types */
809 #define NETXEN_NIC_GBE 0x01
810 #define NETXEN_NIC_XGBE 0x02
811
812 /*
813 * One hardware_context{} per adapter
814 * contains interrupt info as well shared hardware info.
815 */
816 struct netxen_hardware_context {
817 void __iomem *pci_base0;
818 void __iomem *pci_base1;
819 void __iomem *pci_base2;
820 unsigned long first_page_group_end;
821 unsigned long first_page_group_start;
822 void __iomem *db_base;
823 unsigned long db_len;
824 unsigned long pci_len0;
825
826 u8 cut_through;
827 int qdr_sn_window;
828 int ddr_mn_window;
829 unsigned long mn_win_crb;
830 unsigned long ms_win_crb;
831
832 u8 revision_id;
833 u16 board_type;
834 struct netxen_board_info boardcfg;
835 u32 linkup;
836 /* Address of cmd ring in Phantom */
837 struct cmd_desc_type0 *cmd_desc_head;
838 dma_addr_t cmd_desc_phys_addr;
839 struct netxen_adapter *adapter;
840 int pci_func;
841 };
842
843 #define RCV_RING_LRO RCV_DESC_LRO
844
845 #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
846 #define ETHERNET_FCS_SIZE 4
847
848 struct netxen_adapter_stats {
849 u64 rcvdbadskb;
850 u64 xmitcalled;
851 u64 xmitedframes;
852 u64 xmitfinished;
853 u64 badskblen;
854 u64 nocmddescriptor;
855 u64 polled;
856 u64 rxdropped;
857 u64 txdropped;
858 u64 csummed;
859 u64 no_rcv;
860 u64 rxbytes;
861 u64 txbytes;
862 u64 ints;
863 };
864
865 /*
866 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
867 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
868 */
869 struct nx_host_rds_ring {
870 u32 flags;
871 u32 producer;
872 dma_addr_t phys_addr;
873 u32 crb_rcv_producer; /* reg offset */
874 struct rcv_desc *desc_head; /* address of rx ring in Phantom */
875 u32 max_rx_desc_count;
876 u32 dma_size;
877 u32 skb_size;
878 struct netxen_rx_buffer *rx_buf_arr; /* rx buffers for receive */
879 struct list_head free_list;
880 int begin_alloc;
881 };
882
883 /*
884 * Receive context. There is one such structure per instance of the
885 * receive processing. Any state information that is relevant to
886 * the receive, and is must be in this structure. The global data may be
887 * present elsewhere.
888 */
889 struct netxen_recv_context {
890 u32 state;
891 u16 context_id;
892 u16 virt_port;
893
894 struct nx_host_rds_ring rds_rings[NUM_RCV_DESC_RINGS];
895 u32 status_rx_consumer;
896 u32 crb_sts_consumer; /* reg offset */
897 dma_addr_t rcv_status_desc_phys_addr;
898 struct status_desc *rcv_status_desc_head;
899 };
900
901 /* New HW context creation */
902
903 #define NX_OS_CRB_RETRY_COUNT 4000
904 #define NX_CDRP_SIGNATURE_MAKE(pcifn, version) \
905 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
906
907 #define NX_CDRP_CLEAR 0x00000000
908 #define NX_CDRP_CMD_BIT 0x80000000
909
910 /*
911 * All responses must have the NX_CDRP_CMD_BIT cleared
912 * in the crb NX_CDRP_CRB_OFFSET.
913 */
914 #define NX_CDRP_FORM_RSP(rsp) (rsp)
915 #define NX_CDRP_IS_RSP(rsp) (((rsp) & NX_CDRP_CMD_BIT) == 0)
916
917 #define NX_CDRP_RSP_OK 0x00000001
918 #define NX_CDRP_RSP_FAIL 0x00000002
919 #define NX_CDRP_RSP_TIMEOUT 0x00000003
920
921 /*
922 * All commands must have the NX_CDRP_CMD_BIT set in
923 * the crb NX_CDRP_CRB_OFFSET.
924 */
925 #define NX_CDRP_FORM_CMD(cmd) (NX_CDRP_CMD_BIT | (cmd))
926 #define NX_CDRP_IS_CMD(cmd) (((cmd) & NX_CDRP_CMD_BIT) != 0)
927
928 #define NX_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
929 #define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
930 #define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
931 #define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
932 #define NX_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
933 #define NX_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
934 #define NX_CDRP_CMD_CREATE_RX_CTX 0x00000007
935 #define NX_CDRP_CMD_DESTROY_RX_CTX 0x00000008
936 #define NX_CDRP_CMD_CREATE_TX_CTX 0x00000009
937 #define NX_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
938 #define NX_CDRP_CMD_SETUP_STATISTICS 0x0000000e
939 #define NX_CDRP_CMD_GET_STATISTICS 0x0000000f
940 #define NX_CDRP_CMD_DELETE_STATISTICS 0x00000010
941 #define NX_CDRP_CMD_SET_MTU 0x00000012
942 #define NX_CDRP_CMD_MAX 0x00000013
943
944 #define NX_RCODE_SUCCESS 0
945 #define NX_RCODE_NO_HOST_MEM 1
946 #define NX_RCODE_NO_HOST_RESOURCE 2
947 #define NX_RCODE_NO_CARD_CRB 3
948 #define NX_RCODE_NO_CARD_MEM 4
949 #define NX_RCODE_NO_CARD_RESOURCE 5
950 #define NX_RCODE_INVALID_ARGS 6
951 #define NX_RCODE_INVALID_ACTION 7
952 #define NX_RCODE_INVALID_STATE 8
953 #define NX_RCODE_NOT_SUPPORTED 9
954 #define NX_RCODE_NOT_PERMITTED 10
955 #define NX_RCODE_NOT_READY 11
956 #define NX_RCODE_DOES_NOT_EXIST 12
957 #define NX_RCODE_ALREADY_EXISTS 13
958 #define NX_RCODE_BAD_SIGNATURE 14
959 #define NX_RCODE_CMD_NOT_IMPL 15
960 #define NX_RCODE_CMD_INVALID 16
961 #define NX_RCODE_TIMEOUT 17
962 #define NX_RCODE_CMD_FAILED 18
963 #define NX_RCODE_MAX_EXCEEDED 19
964 #define NX_RCODE_MAX 20
965
966 #define NX_DESTROY_CTX_RESET 0
967 #define NX_DESTROY_CTX_D3_RESET 1
968 #define NX_DESTROY_CTX_MAX 2
969
970 /*
971 * Capabilities
972 */
973 #define NX_CAP_BIT(class, bit) (1 << bit)
974 #define NX_CAP0_LEGACY_CONTEXT NX_CAP_BIT(0, 0)
975 #define NX_CAP0_MULTI_CONTEXT NX_CAP_BIT(0, 1)
976 #define NX_CAP0_LEGACY_MN NX_CAP_BIT(0, 2)
977 #define NX_CAP0_LEGACY_MS NX_CAP_BIT(0, 3)
978 #define NX_CAP0_CUT_THROUGH NX_CAP_BIT(0, 4)
979 #define NX_CAP0_LRO NX_CAP_BIT(0, 5)
980 #define NX_CAP0_LSO NX_CAP_BIT(0, 6)
981 #define NX_CAP0_JUMBO_CONTIGUOUS NX_CAP_BIT(0, 7)
982 #define NX_CAP0_LRO_CONTIGUOUS NX_CAP_BIT(0, 8)
983
984 /*
985 * Context state
986 */
987 #define NX_HOST_CTX_STATE_FREED 0
988 #define NX_HOST_CTX_STATE_ALLOCATED 1
989 #define NX_HOST_CTX_STATE_ACTIVE 2
990 #define NX_HOST_CTX_STATE_DISABLED 3
991 #define NX_HOST_CTX_STATE_QUIESCED 4
992 #define NX_HOST_CTX_STATE_MAX 5
993
994 /*
995 * Rx context
996 */
997
998 typedef struct {
999 u64 host_phys_addr; /* Ring base addr */
1000 u32 ring_size; /* Ring entries */
1001 u16 msi_index;
1002 u16 rsvd; /* Padding */
1003 } nx_hostrq_sds_ring_t;
1004
1005 typedef struct {
1006 u64 host_phys_addr; /* Ring base addr */
1007 u64 buff_size; /* Packet buffer size */
1008 u32 ring_size; /* Ring entries */
1009 u32 ring_kind; /* Class of ring */
1010 } nx_hostrq_rds_ring_t;
1011
1012 typedef struct {
1013 u64 host_rsp_dma_addr; /* Response dma'd here */
1014 u32 capabilities[4]; /* Flag bit vector */
1015 u32 host_int_crb_mode; /* Interrupt crb usage */
1016 u32 host_rds_crb_mode; /* RDS crb usage */
1017 /* These ring offsets are relative to data[0] below */
1018 u32 rds_ring_offset; /* Offset to RDS config */
1019 u32 sds_ring_offset; /* Offset to SDS config */
1020 u16 num_rds_rings; /* Count of RDS rings */
1021 u16 num_sds_rings; /* Count of SDS rings */
1022 u16 rsvd1; /* Padding */
1023 u16 rsvd2; /* Padding */
1024 u8 reserved[128]; /* reserve space for future expansion*/
1025 /* MUST BE 64-bit aligned.
1026 The following is packed:
1027 - N hostrq_rds_rings
1028 - N hostrq_sds_rings */
1029 char data[0];
1030 } nx_hostrq_rx_ctx_t;
1031
1032 typedef struct {
1033 u32 host_producer_crb; /* Crb to use */
1034 u32 rsvd1; /* Padding */
1035 } nx_cardrsp_rds_ring_t;
1036
1037 typedef struct {
1038 u32 host_consumer_crb; /* Crb to use */
1039 u32 interrupt_crb; /* Crb to use */
1040 } nx_cardrsp_sds_ring_t;
1041
1042 typedef struct {
1043 /* These ring offsets are relative to data[0] below */
1044 u32 rds_ring_offset; /* Offset to RDS config */
1045 u32 sds_ring_offset; /* Offset to SDS config */
1046 u32 host_ctx_state; /* Starting State */
1047 u32 num_fn_per_port; /* How many PCI fn share the port */
1048 u16 num_rds_rings; /* Count of RDS rings */
1049 u16 num_sds_rings; /* Count of SDS rings */
1050 u16 context_id; /* Handle for context */
1051 u8 phys_port; /* Physical id of port */
1052 u8 virt_port; /* Virtual/Logical id of port */
1053 u8 reserved[128]; /* save space for future expansion */
1054 /* MUST BE 64-bit aligned.
1055 The following is packed:
1056 - N cardrsp_rds_rings
1057 - N cardrs_sds_rings */
1058 char data[0];
1059 } nx_cardrsp_rx_ctx_t;
1060
1061 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
1062 (sizeof(HOSTRQ_RX) + \
1063 (rds_rings)*(sizeof(nx_hostrq_rds_ring_t)) + \
1064 (sds_rings)*(sizeof(nx_hostrq_sds_ring_t)))
1065
1066 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
1067 (sizeof(CARDRSP_RX) + \
1068 (rds_rings)*(sizeof(nx_cardrsp_rds_ring_t)) + \
1069 (sds_rings)*(sizeof(nx_cardrsp_sds_ring_t)))
1070
1071 /*
1072 * Tx context
1073 */
1074
1075 typedef struct {
1076 u64 host_phys_addr; /* Ring base addr */
1077 u32 ring_size; /* Ring entries */
1078 u32 rsvd; /* Padding */
1079 } nx_hostrq_cds_ring_t;
1080
1081 typedef struct {
1082 u64 host_rsp_dma_addr; /* Response dma'd here */
1083 u64 cmd_cons_dma_addr; /* */
1084 u64 dummy_dma_addr; /* */
1085 u32 capabilities[4]; /* Flag bit vector */
1086 u32 host_int_crb_mode; /* Interrupt crb usage */
1087 u32 rsvd1; /* Padding */
1088 u16 rsvd2; /* Padding */
1089 u16 interrupt_ctl;
1090 u16 msi_index;
1091 u16 rsvd3; /* Padding */
1092 nx_hostrq_cds_ring_t cds_ring; /* Desc of cds ring */
1093 u8 reserved[128]; /* future expansion */
1094 } nx_hostrq_tx_ctx_t;
1095
1096 typedef struct {
1097 u32 host_producer_crb; /* Crb to use */
1098 u32 interrupt_crb; /* Crb to use */
1099 } nx_cardrsp_cds_ring_t;
1100
1101 typedef struct {
1102 u32 host_ctx_state; /* Starting state */
1103 u16 context_id; /* Handle for context */
1104 u8 phys_port; /* Physical id of port */
1105 u8 virt_port; /* Virtual/Logical id of port */
1106 nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */
1107 u8 reserved[128]; /* future expansion */
1108 } nx_cardrsp_tx_ctx_t;
1109
1110 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
1111 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
1112
1113 /* CRB */
1114
1115 #define NX_HOST_RDS_CRB_MODE_UNIQUE 0
1116 #define NX_HOST_RDS_CRB_MODE_SHARED 1
1117 #define NX_HOST_RDS_CRB_MODE_CUSTOM 2
1118 #define NX_HOST_RDS_CRB_MODE_MAX 3
1119
1120 #define NX_HOST_INT_CRB_MODE_UNIQUE 0
1121 #define NX_HOST_INT_CRB_MODE_SHARED 1
1122 #define NX_HOST_INT_CRB_MODE_NORX 2
1123 #define NX_HOST_INT_CRB_MODE_NOTX 3
1124 #define NX_HOST_INT_CRB_MODE_NORXTX 4
1125
1126
1127 /* MAC */
1128
1129 #define MC_COUNT_P2 16
1130 #define MC_COUNT_P3 38
1131
1132 #define NETXEN_MAC_NOOP 0
1133 #define NETXEN_MAC_ADD 1
1134 #define NETXEN_MAC_DEL 2
1135
1136 typedef struct nx_mac_list_s {
1137 struct nx_mac_list_s *next;
1138 uint8_t mac_addr[MAX_ADDR_LEN];
1139 } nx_mac_list_t;
1140
1141 /*
1142 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
1143 * adjusted based on configured MTU.
1144 */
1145 #define NETXEN_DEFAULT_INTR_COALESCE_RX_TIME_US 3
1146 #define NETXEN_DEFAULT_INTR_COALESCE_RX_PACKETS 256
1147 #define NETXEN_DEFAULT_INTR_COALESCE_TX_PACKETS 64
1148 #define NETXEN_DEFAULT_INTR_COALESCE_TX_TIME_US 4
1149
1150 #define NETXEN_NIC_INTR_DEFAULT 0x04
1151
1152 typedef union {
1153 struct {
1154 uint16_t rx_packets;
1155 uint16_t rx_time_us;
1156 uint16_t tx_packets;
1157 uint16_t tx_time_us;
1158 } data;
1159 uint64_t word;
1160 } nx_nic_intr_coalesce_data_t;
1161
1162 typedef struct {
1163 uint16_t stats_time_us;
1164 uint16_t rate_sample_time;
1165 uint16_t flags;
1166 uint16_t rsvd_1;
1167 uint32_t low_threshold;
1168 uint32_t high_threshold;
1169 nx_nic_intr_coalesce_data_t normal;
1170 nx_nic_intr_coalesce_data_t low;
1171 nx_nic_intr_coalesce_data_t high;
1172 nx_nic_intr_coalesce_data_t irq;
1173 } nx_nic_intr_coalesce_t;
1174
1175 #define NX_HOST_REQUEST 0x13
1176 #define NX_NIC_REQUEST 0x14
1177
1178 #define NX_MAC_EVENT 0x1
1179
1180 enum {
1181 NX_NIC_H2C_OPCODE_START = 0,
1182 NX_NIC_H2C_OPCODE_CONFIG_RSS,
1183 NX_NIC_H2C_OPCODE_CONFIG_RSS_TBL,
1184 NX_NIC_H2C_OPCODE_CONFIG_INTR_COALESCE,
1185 NX_NIC_H2C_OPCODE_CONFIG_LED,
1186 NX_NIC_H2C_OPCODE_CONFIG_PROMISCUOUS,
1187 NX_NIC_H2C_OPCODE_CONFIG_L2_MAC,
1188 NX_NIC_H2C_OPCODE_LRO_REQUEST,
1189 NX_NIC_H2C_OPCODE_GET_SNMP_STATS,
1190 NX_NIC_H2C_OPCODE_PROXY_START_REQUEST,
1191 NX_NIC_H2C_OPCODE_PROXY_STOP_REQUEST,
1192 NX_NIC_H2C_OPCODE_PROXY_SET_MTU,
1193 NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE,
1194 NX_H2P_OPCODE_GET_FINGER_PRINT_REQUEST,
1195 NX_H2P_OPCODE_INSTALL_LICENSE_REQUEST,
1196 NX_H2P_OPCODE_GET_LICENSE_CAPABILITY_REQUEST,
1197 NX_NIC_H2C_OPCODE_GET_NET_STATS,
1198 NX_NIC_H2C_OPCODE_LAST
1199 };
1200
1201 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
1202 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
1203 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
1204
1205 typedef struct {
1206 u64 qhdr;
1207 u64 req_hdr;
1208 u64 words[6];
1209 } nx_nic_req_t;
1210
1211 typedef struct {
1212 u8 op;
1213 u8 tag;
1214 u8 mac_addr[6];
1215 } nx_mac_req_t;
1216
1217 #define MAX_PENDING_DESC_BLOCK_SIZE 64
1218
1219 #define NETXEN_NIC_MSI_ENABLED 0x02
1220 #define NETXEN_NIC_MSIX_ENABLED 0x04
1221 #define NETXEN_IS_MSI_FAMILY(adapter) \
1222 ((adapter)->flags & (NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED))
1223
1224 #define MSIX_ENTRIES_PER_ADAPTER 8
1225 #define NETXEN_MSIX_TBL_SPACE 8192
1226 #define NETXEN_PCI_REG_MSIX_TBL 0x44
1227
1228 #define NETXEN_DB_MAPSIZE_BYTES 0x1000
1229
1230 #define NETXEN_NETDEV_WEIGHT 120
1231 #define NETXEN_ADAPTER_UP_MAGIC 777
1232 #define NETXEN_NIC_PEG_TUNE 0
1233
1234 struct netxen_dummy_dma {
1235 void *addr;
1236 dma_addr_t phys_addr;
1237 };
1238
1239 struct netxen_adapter {
1240 struct netxen_hardware_context ahw;
1241
1242 struct net_device *netdev;
1243 struct pci_dev *pdev;
1244 int pci_using_dac;
1245 struct napi_struct napi;
1246 struct net_device_stats net_stats;
1247 int mtu;
1248 int portnum;
1249 u8 physical_port;
1250 u16 tx_context_id;
1251
1252 uint8_t mc_enabled;
1253 uint8_t max_mc_count;
1254 nx_mac_list_t *mac_list;
1255
1256 struct netxen_legacy_intr_set legacy_intr;
1257 u32 crb_intr_mask;
1258
1259 struct work_struct watchdog_task;
1260 struct timer_list watchdog_timer;
1261 struct work_struct tx_timeout_task;
1262
1263 u32 curr_window;
1264 u32 crb_win;
1265 rwlock_t adapter_lock;
1266
1267 uint64_t dma_mask;
1268
1269 u32 cmd_producer;
1270 __le32 *cmd_consumer;
1271 u32 last_cmd_consumer;
1272 u32 crb_addr_cmd_producer;
1273 u32 crb_addr_cmd_consumer;
1274
1275 u32 max_tx_desc_count;
1276 u32 max_rx_desc_count;
1277 u32 max_jumbo_rx_desc_count;
1278 u32 max_lro_rx_desc_count;
1279
1280 int max_rds_rings;
1281
1282 u32 flags;
1283 u32 irq;
1284 int driver_mismatch;
1285 u32 temp;
1286
1287 u32 fw_major;
1288
1289 u8 msix_supported;
1290 u8 max_possible_rss_rings;
1291 struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
1292
1293 struct netxen_adapter_stats stats;
1294
1295 u16 link_speed;
1296 u16 link_duplex;
1297 u16 state;
1298 u16 link_autoneg;
1299 int rx_csum;
1300 int status;
1301
1302 struct netxen_cmd_buffer *cmd_buf_arr; /* Command buffers for xmit */
1303
1304 /*
1305 * Receive instances. These can be either one per port,
1306 * or one per peg, etc.
1307 */
1308 struct netxen_recv_context recv_ctx[MAX_RCV_CTX];
1309
1310 int is_up;
1311 struct netxen_dummy_dma dummy_dma;
1312 nx_nic_intr_coalesce_t coal;
1313
1314 /* Context interface shared between card and host */
1315 struct netxen_ring_ctx *ctx_desc;
1316 dma_addr_t ctx_desc_phys_addr;
1317 int intr_scheme;
1318 int msi_mode;
1319 int (*enable_phy_interrupts) (struct netxen_adapter *);
1320 int (*disable_phy_interrupts) (struct netxen_adapter *);
1321 int (*macaddr_set) (struct netxen_adapter *, netxen_ethernet_macaddr_t);
1322 int (*set_mtu) (struct netxen_adapter *, int);
1323 int (*set_promisc) (struct netxen_adapter *, u32);
1324 int (*phy_read) (struct netxen_adapter *, long reg, u32 *);
1325 int (*phy_write) (struct netxen_adapter *, long reg, u32 val);
1326 int (*init_port) (struct netxen_adapter *, int);
1327 int (*stop_port) (struct netxen_adapter *);
1328
1329 int (*hw_read_wx)(struct netxen_adapter *, ulong, void *, int);
1330 int (*hw_write_wx)(struct netxen_adapter *, ulong, void *, int);
1331 int (*pci_mem_read)(struct netxen_adapter *, u64, void *, int);
1332 int (*pci_mem_write)(struct netxen_adapter *, u64, void *, int);
1333 int (*pci_write_immediate)(struct netxen_adapter *, u64, u32);
1334 u32 (*pci_read_immediate)(struct netxen_adapter *, u64);
1335 void (*pci_write_normalize)(struct netxen_adapter *, u64, u32);
1336 u32 (*pci_read_normalize)(struct netxen_adapter *, u64);
1337 unsigned long (*pci_set_window)(struct netxen_adapter *,
1338 unsigned long long);
1339 }; /* netxen_adapter structure */
1340
1341 /*
1342 * NetXen dma watchdog control structure
1343 *
1344 * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
1345 * Bit 1 : disable_request => 1 req disable dma watchdog
1346 * Bit 2 : enable_request => 1 req enable dma watchdog
1347 * Bit 3-31 : unused
1348 */
1349
1350 #define netxen_set_dma_watchdog_disable_req(config_word) \
1351 _netxen_set_bits(config_word, 1, 1, 1)
1352 #define netxen_set_dma_watchdog_enable_req(config_word) \
1353 _netxen_set_bits(config_word, 2, 1, 1)
1354 #define netxen_get_dma_watchdog_enabled(config_word) \
1355 ((config_word) & 0x1)
1356 #define netxen_get_dma_watchdog_disabled(config_word) \
1357 (((config_word) >> 1) & 0x1)
1358
1359 /* Max number of xmit producer threads that can run simultaneously */
1360 #define MAX_XMIT_PRODUCERS 16
1361
1362 #define PCI_OFFSET_FIRST_RANGE(adapter, off) \
1363 ((adapter)->ahw.pci_base0 + (off))
1364 #define PCI_OFFSET_SECOND_RANGE(adapter, off) \
1365 ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
1366 #define PCI_OFFSET_THIRD_RANGE(adapter, off) \
1367 ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
1368
1369 static inline void __iomem *pci_base_offset(struct netxen_adapter *adapter,
1370 unsigned long off)
1371 {
1372 if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) {
1373 return (adapter->ahw.pci_base0 + off);
1374 } else if ((off < SECOND_PAGE_GROUP_END) &&
1375 (off >= SECOND_PAGE_GROUP_START)) {
1376 return (adapter->ahw.pci_base1 + off - SECOND_PAGE_GROUP_START);
1377 } else if ((off < THIRD_PAGE_GROUP_END) &&
1378 (off >= THIRD_PAGE_GROUP_START)) {
1379 return (adapter->ahw.pci_base2 + off - THIRD_PAGE_GROUP_START);
1380 }
1381 return NULL;
1382 }
1383
1384 static inline void __iomem *pci_base(struct netxen_adapter *adapter,
1385 unsigned long off)
1386 {
1387 if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) {
1388 return adapter->ahw.pci_base0;
1389 } else if ((off < SECOND_PAGE_GROUP_END) &&
1390 (off >= SECOND_PAGE_GROUP_START)) {
1391 return adapter->ahw.pci_base1;
1392 } else if ((off < THIRD_PAGE_GROUP_END) &&
1393 (off >= THIRD_PAGE_GROUP_START)) {
1394 return adapter->ahw.pci_base2;
1395 }
1396 return NULL;
1397 }
1398
1399 int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1400 int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1401 int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter);
1402 int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter);
1403 int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
1404 __u32 * readval);
1405 int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter,
1406 long reg, __u32 val);
1407
1408 /* Functions available from netxen_nic_hw.c */
1409 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu);
1410 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu);
1411 void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val);
1412 int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off);
1413 void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value);
1414 void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 *value);
1415 void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value);
1416 void netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index, u32 *value);
1417
1418 int netxen_nic_get_board_info(struct netxen_adapter *adapter);
1419
1420 int netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter,
1421 ulong off, void *data, int len);
1422 int netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
1423 ulong off, void *data, int len);
1424 int netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1425 u64 off, void *data, int size);
1426 int netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1427 u64 off, void *data, int size);
1428 int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1429 u64 off, u32 data);
1430 u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off);
1431 void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
1432 u64 off, u32 data);
1433 u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off);
1434 unsigned long netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1435 unsigned long long addr);
1436 void netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter,
1437 u32 wndw);
1438
1439 int netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter,
1440 ulong off, void *data, int len);
1441 int netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
1442 ulong off, void *data, int len);
1443 int netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1444 u64 off, void *data, int size);
1445 int netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1446 u64 off, void *data, int size);
1447 void netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
1448 unsigned long off, int data);
1449 int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
1450 u64 off, u32 data);
1451 u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off);
1452 void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
1453 u64 off, u32 data);
1454 u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off);
1455 unsigned long netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1456 unsigned long long addr);
1457
1458 /* Functions from netxen_nic_init.c */
1459 void netxen_free_adapter_offload(struct netxen_adapter *adapter);
1460 int netxen_initialize_adapter_offload(struct netxen_adapter *adapter);
1461 int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val);
1462 int netxen_receive_peg_ready(struct netxen_adapter *adapter);
1463 int netxen_load_firmware(struct netxen_adapter *adapter);
1464 int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose);
1465
1466 int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
1467 int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
1468 u8 *bytes, size_t size);
1469 int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
1470 u8 *bytes, size_t size);
1471 int netxen_flash_unlock(struct netxen_adapter *adapter);
1472 int netxen_backup_crbinit(struct netxen_adapter *adapter);
1473 int netxen_flash_erase_secondary(struct netxen_adapter *adapter);
1474 int netxen_flash_erase_primary(struct netxen_adapter *adapter);
1475 void netxen_halt_pegs(struct netxen_adapter *adapter);
1476
1477 int netxen_rom_se(struct netxen_adapter *adapter, int addr);
1478
1479 int netxen_alloc_sw_resources(struct netxen_adapter *adapter);
1480 void netxen_free_sw_resources(struct netxen_adapter *adapter);
1481
1482 int netxen_alloc_hw_resources(struct netxen_adapter *adapter);
1483 void netxen_free_hw_resources(struct netxen_adapter *adapter);
1484
1485 void netxen_release_rx_buffers(struct netxen_adapter *adapter);
1486 void netxen_release_tx_buffers(struct netxen_adapter *adapter);
1487
1488 void netxen_initialize_adapter_ops(struct netxen_adapter *adapter);
1489 int netxen_init_firmware(struct netxen_adapter *adapter);
1490 void netxen_tso_check(struct netxen_adapter *adapter,
1491 struct cmd_desc_type0 *desc, struct sk_buff *skb);
1492 void netxen_nic_clear_stats(struct netxen_adapter *adapter);
1493 void netxen_watchdog_task(struct work_struct *work);
1494 void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx,
1495 u32 ringid);
1496 int netxen_process_cmd_ring(struct netxen_adapter *adapter);
1497 u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctx, int max);
1498 void netxen_p2_nic_set_multi(struct net_device *netdev);
1499 void netxen_p3_nic_set_multi(struct net_device *netdev);
1500 int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32);
1501 int netxen_config_intr_coalesce(struct netxen_adapter *adapter);
1502
1503 int nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu);
1504 int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
1505
1506 int netxen_nic_set_mac(struct net_device *netdev, void *p);
1507 struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev);
1508
1509 void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter,
1510 uint32_t crb_producer);
1511
1512 /*
1513 * NetXen Board information
1514 */
1515
1516 #define NETXEN_MAX_SHORT_NAME 32
1517 struct netxen_brdinfo {
1518 netxen_brdtype_t brdtype; /* type of board */
1519 long ports; /* max no of physical ports */
1520 char short_name[NETXEN_MAX_SHORT_NAME];
1521 };
1522
1523 static const struct netxen_brdinfo netxen_boards[] = {
1524 {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"},
1525 {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"},
1526 {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"},
1527 {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"},
1528 {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"},
1529 {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"},
1530 {NETXEN_BRDTYPE_P3_REF_QG, 4, "Reference Quad Gig "},
1531 {NETXEN_BRDTYPE_P3_HMEZ, 2, "Dual XGb HMEZ"},
1532 {NETXEN_BRDTYPE_P3_10G_CX4_LP, 2, "Dual XGb CX4 LP"},
1533 {NETXEN_BRDTYPE_P3_4_GB, 4, "Quad Gig LP"},
1534 {NETXEN_BRDTYPE_P3_IMEZ, 2, "Dual XGb IMEZ"},
1535 {NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"},
1536 {NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"},
1537 {NETXEN_BRDTYPE_P3_XG_LOM, 2, "Dual XGb LOM"},
1538 {NETXEN_BRDTYPE_P3_4_GB_MM, 4, "NX3031 Gigabit Ethernet"},
1539 {NETXEN_BRDTYPE_P3_10G_SFP_CT, 2, "NX3031 10 Gigabit Ethernet"},
1540 {NETXEN_BRDTYPE_P3_10G_SFP_QT, 2, "Quanta Dual XGb SFP+"},
1541 {NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"},
1542 {NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"}
1543 };
1544
1545 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards)
1546
1547 static inline void get_brd_name_by_type(u32 type, char *name)
1548 {
1549 int i, found = 0;
1550 for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
1551 if (netxen_boards[i].brdtype == type) {
1552 strcpy(name, netxen_boards[i].short_name);
1553 found = 1;
1554 break;
1555 }
1556
1557 }
1558 if (!found)
1559 name = "Unknown";
1560 }
1561
1562 static inline int
1563 dma_watchdog_shutdown_request(struct netxen_adapter *adapter)
1564 {
1565 u32 ctrl;
1566
1567 /* check if already inactive */
1568 if (adapter->hw_read_wx(adapter,
1569 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
1570 printk(KERN_ERR "failed to read dma watchdog status\n");
1571
1572 if (netxen_get_dma_watchdog_enabled(ctrl) == 0)
1573 return 1;
1574
1575 /* Send the disable request */
1576 netxen_set_dma_watchdog_disable_req(ctrl);
1577 netxen_crb_writelit_adapter(adapter,
1578 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
1579
1580 return 0;
1581 }
1582
1583 static inline int
1584 dma_watchdog_shutdown_poll_result(struct netxen_adapter *adapter)
1585 {
1586 u32 ctrl;
1587
1588 if (adapter->hw_read_wx(adapter,
1589 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
1590 printk(KERN_ERR "failed to read dma watchdog status\n");
1591
1592 return (netxen_get_dma_watchdog_enabled(ctrl) == 0);
1593 }
1594
1595 static inline int
1596 dma_watchdog_wakeup(struct netxen_adapter *adapter)
1597 {
1598 u32 ctrl;
1599
1600 if (adapter->hw_read_wx(adapter,
1601 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
1602 printk(KERN_ERR "failed to read dma watchdog status\n");
1603
1604 if (netxen_get_dma_watchdog_enabled(ctrl))
1605 return 1;
1606
1607 /* send the wakeup request */
1608 netxen_set_dma_watchdog_enable_req(ctrl);
1609
1610 netxen_crb_writelit_adapter(adapter,
1611 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
1612
1613 return 0;
1614 }
1615
1616
1617 int netxen_is_flash_supported(struct netxen_adapter *adapter);
1618 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
1619 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
1620 extern void netxen_change_ringparam(struct netxen_adapter *adapter);
1621 extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr,
1622 int *valp);
1623
1624 extern struct ethtool_ops netxen_nic_ethtool_ops;
1625
1626 #endif /* __NETXEN_NIC_H_ */
Linux kernel - Deliverables
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