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[deliverable/linux.git] / drivers / net / netxen / netxen_nic_hw.c
1 /*
2 * Copyright (C) 2003 - 2006 NetXen, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
22 *
23 * Contact Information:
24 * info@netxen.com
25 * NetXen,
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
28 *
29 *
30 * Source file for NIC routines to access the Phantom hardware
31 *
32 */
33
34 #include "netxen_nic.h"
35 #include "netxen_nic_hw.h"
36 #include "netxen_nic_phan_reg.h"
37
38
39 #include <net/ip.h>
40
41 struct netxen_recv_crb recv_crb_registers[] = {
42 /*
43 * Instance 0.
44 */
45 {
46 /* crb_rcv_producer: */
47 {
48 NETXEN_NIC_REG(0x100),
49 /* Jumbo frames */
50 NETXEN_NIC_REG(0x110),
51 /* LRO */
52 NETXEN_NIC_REG(0x120)
53 },
54 /* crb_sts_consumer: */
55 NETXEN_NIC_REG(0x138),
56 },
57 /*
58 * Instance 1,
59 */
60 {
61 /* crb_rcv_producer: */
62 {
63 NETXEN_NIC_REG(0x144),
64 /* Jumbo frames */
65 NETXEN_NIC_REG(0x154),
66 /* LRO */
67 NETXEN_NIC_REG(0x164)
68 },
69 /* crb_sts_consumer: */
70 NETXEN_NIC_REG(0x17c),
71 },
72 /*
73 * Instance 2,
74 */
75 {
76 /* crb_rcv_producer: */
77 {
78 NETXEN_NIC_REG(0x1d8),
79 /* Jumbo frames */
80 NETXEN_NIC_REG(0x1f8),
81 /* LRO */
82 NETXEN_NIC_REG(0x208)
83 },
84 /* crb_sts_consumer: */
85 NETXEN_NIC_REG(0x220),
86 },
87 /*
88 * Instance 3,
89 */
90 {
91 /* crb_rcv_producer: */
92 {
93 NETXEN_NIC_REG(0x22c),
94 /* Jumbo frames */
95 NETXEN_NIC_REG(0x23c),
96 /* LRO */
97 NETXEN_NIC_REG(0x24c)
98 },
99 /* crb_sts_consumer: */
100 NETXEN_NIC_REG(0x264),
101 },
102 };
103
104 static u64 ctx_addr_sig_regs[][3] = {
105 {NETXEN_NIC_REG(0x188), NETXEN_NIC_REG(0x18c), NETXEN_NIC_REG(0x1c0)},
106 {NETXEN_NIC_REG(0x190), NETXEN_NIC_REG(0x194), NETXEN_NIC_REG(0x1c4)},
107 {NETXEN_NIC_REG(0x198), NETXEN_NIC_REG(0x19c), NETXEN_NIC_REG(0x1c8)},
108 {NETXEN_NIC_REG(0x1a0), NETXEN_NIC_REG(0x1a4), NETXEN_NIC_REG(0x1cc)}
109 };
110 #define CRB_CTX_ADDR_REG_LO(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][0])
111 #define CRB_CTX_ADDR_REG_HI(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][2])
112 #define CRB_CTX_SIGNATURE_REG(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][1])
113
114
115 /* PCI Windowing for DDR regions. */
116
117 #define ADDR_IN_RANGE(addr, low, high) \
118 (((addr) <= (high)) && ((addr) >= (low)))
119
120 #define NETXEN_FLASH_BASE (NETXEN_BOOTLD_START)
121 #define NETXEN_PHANTOM_MEM_BASE (NETXEN_FLASH_BASE)
122 #define NETXEN_MAX_MTU 8000 + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE
123 #define NETXEN_MIN_MTU 64
124 #define NETXEN_ETH_FCS_SIZE 4
125 #define NETXEN_ENET_HEADER_SIZE 14
126 #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
127 #define NETXEN_FIRMWARE_LEN ((16 * 1024) / 4)
128 #define NETXEN_NIU_HDRSIZE (0x1 << 6)
129 #define NETXEN_NIU_TLRSIZE (0x1 << 5)
130
131 #define lower32(x) ((u32)((x) & 0xffffffff))
132 #define upper32(x) \
133 ((u32)(((unsigned long long)(x) >> 32) & 0xffffffff))
134
135 #define NETXEN_NIC_ZERO_PAUSE_ADDR 0ULL
136 #define NETXEN_NIC_UNIT_PAUSE_ADDR 0x200ULL
137 #define NETXEN_NIC_EPG_PAUSE_ADDR1 0x2200010000c28001ULL
138 #define NETXEN_NIC_EPG_PAUSE_ADDR2 0x0100088866554433ULL
139
140 #define NETXEN_NIC_WINDOW_MARGIN 0x100000
141
142 static unsigned long netxen_nic_pci_set_window(struct netxen_adapter *adapter,
143 unsigned long long addr);
144 void netxen_free_hw_resources(struct netxen_adapter *adapter);
145
146 int netxen_nic_set_mac(struct net_device *netdev, void *p)
147 {
148 struct netxen_adapter *adapter = netdev_priv(netdev);
149 struct sockaddr *addr = p;
150
151 if (netif_running(netdev))
152 return -EBUSY;
153
154 if (!is_valid_ether_addr(addr->sa_data))
155 return -EADDRNOTAVAIL;
156
157 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
158
159 if (adapter->macaddr_set)
160 adapter->macaddr_set(adapter, addr->sa_data);
161
162 return 0;
163 }
164
165 #define NETXEN_UNICAST_ADDR(port, index) \
166 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
167 #define NETXEN_MCAST_ADDR(port, index) \
168 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
169 #define MAC_HI(addr) \
170 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
171 #define MAC_LO(addr) \
172 ((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
173
174 static int
175 netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
176 {
177 u32 val = 0;
178 u16 port = adapter->physical_port;
179 u8 *addr = adapter->netdev->dev_addr;
180
181 if (adapter->mc_enabled)
182 return 0;
183
184 netxen_nic_hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
185 val |= (1UL << (28+port));
186 netxen_nic_hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
187
188 /* add broadcast addr to filter */
189 val = 0xffffff;
190 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
191 netxen_crb_writelit_adapter(adapter,
192 NETXEN_UNICAST_ADDR(port, 0)+4, val);
193
194 /* add station addr to filter */
195 val = MAC_HI(addr);
196 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
197 val = MAC_LO(addr);
198 netxen_crb_writelit_adapter(adapter,
199 NETXEN_UNICAST_ADDR(port, 1)+4, val);
200
201 adapter->mc_enabled = 1;
202 return 0;
203 }
204
205 static int
206 netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
207 {
208 u32 val = 0;
209 u16 port = adapter->physical_port;
210 u8 *addr = adapter->netdev->dev_addr;
211
212 if (!adapter->mc_enabled)
213 return 0;
214
215 netxen_nic_hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
216 val &= ~(1UL << (28+port));
217 netxen_nic_hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
218
219 val = MAC_HI(addr);
220 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
221 val = MAC_LO(addr);
222 netxen_crb_writelit_adapter(adapter,
223 NETXEN_UNICAST_ADDR(port, 0)+4, val);
224
225 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
226 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
227
228 adapter->mc_enabled = 0;
229 return 0;
230 }
231
232 static int
233 netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
234 int index, u8 *addr)
235 {
236 u32 hi = 0, lo = 0;
237 u16 port = adapter->physical_port;
238
239 lo = MAC_LO(addr);
240 hi = MAC_HI(addr);
241
242 netxen_crb_writelit_adapter(adapter,
243 NETXEN_MCAST_ADDR(port, index), hi);
244 netxen_crb_writelit_adapter(adapter,
245 NETXEN_MCAST_ADDR(port, index)+4, lo);
246
247 return 0;
248 }
249
250 /*
251 * netxen_nic_set_multi - Multicast
252 */
253 void netxen_nic_set_multi(struct net_device *netdev)
254 {
255 struct netxen_adapter *adapter = netdev_priv(netdev);
256 struct dev_mc_list *mc_ptr;
257 u8 null_addr[6];
258 int index = 0;
259
260 memset(null_addr, 0, 6);
261
262 if (netdev->flags & IFF_PROMISC) {
263
264 adapter->set_promisc(adapter,
265 NETXEN_NIU_PROMISC_MODE);
266
267 /* Full promiscuous mode */
268 netxen_nic_disable_mcast_filter(adapter);
269
270 return;
271 }
272
273 if (netdev->mc_count == 0) {
274 adapter->set_promisc(adapter,
275 NETXEN_NIU_NON_PROMISC_MODE);
276 netxen_nic_disable_mcast_filter(adapter);
277 return;
278 }
279
280 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE);
281 if (netdev->flags & IFF_ALLMULTI ||
282 netdev->mc_count > adapter->max_mc_count) {
283 netxen_nic_disable_mcast_filter(adapter);
284 return;
285 }
286
287 netxen_nic_enable_mcast_filter(adapter);
288
289 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next, index++)
290 netxen_nic_set_mcast_addr(adapter, index, mc_ptr->dmi_addr);
291
292 if (index != netdev->mc_count)
293 printk(KERN_WARNING "%s: %s multicast address count mismatch\n",
294 netxen_nic_driver_name, netdev->name);
295
296 /* Clear out remaining addresses */
297 for (; index < adapter->max_mc_count; index++)
298 netxen_nic_set_mcast_addr(adapter, index, null_addr);
299 }
300
301 /*
302 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
303 * @returns 0 on success, negative on failure
304 */
305 int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
306 {
307 struct netxen_adapter *adapter = netdev_priv(netdev);
308 int eff_mtu = mtu + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE;
309
310 if ((eff_mtu > NETXEN_MAX_MTU) || (eff_mtu < NETXEN_MIN_MTU)) {
311 printk(KERN_ERR "%s: %s %d is not supported.\n",
312 netxen_nic_driver_name, netdev->name, mtu);
313 return -EINVAL;
314 }
315
316 if (adapter->set_mtu)
317 adapter->set_mtu(adapter, mtu);
318 netdev->mtu = mtu;
319
320 return 0;
321 }
322
323 /*
324 * check if the firmware has been downloaded and ready to run and
325 * setup the address for the descriptors in the adapter
326 */
327 int netxen_nic_hw_resources(struct netxen_adapter *adapter)
328 {
329 struct netxen_hardware_context *hw = &adapter->ahw;
330 u32 state = 0;
331 void *addr;
332 int loops = 0, err = 0;
333 int ctx, ring;
334 struct netxen_recv_context *recv_ctx;
335 struct netxen_rcv_desc_ctx *rcv_desc;
336 int func_id = adapter->portnum;
337
338 DPRINTK(INFO, "crb_base: %lx %x", NETXEN_PCI_CRBSPACE,
339 PCI_OFFSET_SECOND_RANGE(adapter, NETXEN_PCI_CRBSPACE));
340 DPRINTK(INFO, "cam base: %lx %x", NETXEN_CRB_CAM,
341 pci_base_offset(adapter, NETXEN_CRB_CAM));
342 DPRINTK(INFO, "cam RAM: %lx %x", NETXEN_CAM_RAM_BASE,
343 pci_base_offset(adapter, NETXEN_CAM_RAM_BASE));
344
345
346 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
347 DPRINTK(INFO, "Command Peg ready..waiting for rcv peg\n");
348 loops = 0;
349 state = 0;
350 /* Window 1 call */
351 state = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_RCVPEG_STATE));
352 while (state != PHAN_PEG_RCV_INITIALIZED && loops < 20) {
353 msleep(1);
354 /* Window 1 call */
355 state = readl(NETXEN_CRB_NORMALIZE(adapter,
356 CRB_RCVPEG_STATE));
357 loops++;
358 }
359 if (loops >= 20) {
360 printk(KERN_ERR "Rcv Peg initialization not complete:"
361 "%x.\n", state);
362 err = -EIO;
363 return err;
364 }
365 }
366 adapter->intr_scheme = readl(
367 NETXEN_CRB_NORMALIZE(adapter, CRB_NIC_CAPABILITIES_FW));
368 adapter->msi_mode = readl(
369 NETXEN_CRB_NORMALIZE(adapter, CRB_NIC_MSI_MODE_FW));
370
371 addr = pci_alloc_consistent(adapter->pdev,
372 sizeof(struct netxen_ring_ctx) + sizeof(uint32_t),
373 &adapter->ctx_desc_phys_addr);
374
375 if (addr == NULL) {
376 DPRINTK(ERR, "bad return from pci_alloc_consistent\n");
377 err = -ENOMEM;
378 return err;
379 }
380 memset(addr, 0, sizeof(struct netxen_ring_ctx));
381 adapter->ctx_desc = (struct netxen_ring_ctx *)addr;
382 adapter->ctx_desc->ctx_id = cpu_to_le32(adapter->portnum);
383 adapter->ctx_desc->cmd_consumer_offset =
384 cpu_to_le64(adapter->ctx_desc_phys_addr +
385 sizeof(struct netxen_ring_ctx));
386 adapter->cmd_consumer = (__le32 *) (((char *)addr) +
387 sizeof(struct netxen_ring_ctx));
388
389 addr = pci_alloc_consistent(adapter->pdev,
390 sizeof(struct cmd_desc_type0) *
391 adapter->max_tx_desc_count,
392 &hw->cmd_desc_phys_addr);
393
394 if (addr == NULL) {
395 DPRINTK(ERR, "bad return from pci_alloc_consistent\n");
396 netxen_free_hw_resources(adapter);
397 return -ENOMEM;
398 }
399
400 adapter->ctx_desc->cmd_ring_addr =
401 cpu_to_le64(hw->cmd_desc_phys_addr);
402 adapter->ctx_desc->cmd_ring_size =
403 cpu_to_le32(adapter->max_tx_desc_count);
404
405 hw->cmd_desc_head = (struct cmd_desc_type0 *)addr;
406
407 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
408 recv_ctx = &adapter->recv_ctx[ctx];
409
410 for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
411 rcv_desc = &recv_ctx->rcv_desc[ring];
412 addr = pci_alloc_consistent(adapter->pdev,
413 RCV_DESC_RINGSIZE,
414 &rcv_desc->phys_addr);
415 if (addr == NULL) {
416 DPRINTK(ERR, "bad return from "
417 "pci_alloc_consistent\n");
418 netxen_free_hw_resources(adapter);
419 err = -ENOMEM;
420 return err;
421 }
422 rcv_desc->desc_head = (struct rcv_desc *)addr;
423 adapter->ctx_desc->rcv_ctx[ring].rcv_ring_addr =
424 cpu_to_le64(rcv_desc->phys_addr);
425 adapter->ctx_desc->rcv_ctx[ring].rcv_ring_size =
426 cpu_to_le32(rcv_desc->max_rx_desc_count);
427 rcv_desc->crb_rcv_producer =
428 recv_crb_registers[adapter->portnum].
429 crb_rcv_producer[ring];
430 }
431
432 addr = pci_alloc_consistent(adapter->pdev, STATUS_DESC_RINGSIZE,
433 &recv_ctx->rcv_status_desc_phys_addr);
434 if (addr == NULL) {
435 DPRINTK(ERR, "bad return from"
436 " pci_alloc_consistent\n");
437 netxen_free_hw_resources(adapter);
438 err = -ENOMEM;
439 return err;
440 }
441 recv_ctx->rcv_status_desc_head = (struct status_desc *)addr;
442 adapter->ctx_desc->sts_ring_addr =
443 cpu_to_le64(recv_ctx->rcv_status_desc_phys_addr);
444 adapter->ctx_desc->sts_ring_size =
445 cpu_to_le32(adapter->max_rx_desc_count);
446 recv_ctx->crb_sts_consumer =
447 recv_crb_registers[adapter->portnum].crb_sts_consumer;
448
449 }
450 /* Window = 1 */
451
452 writel(lower32(adapter->ctx_desc_phys_addr),
453 NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_ADDR_REG_LO(func_id)));
454 writel(upper32(adapter->ctx_desc_phys_addr),
455 NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_ADDR_REG_HI(func_id)));
456 writel(NETXEN_CTX_SIGNATURE | func_id,
457 NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_SIGNATURE_REG(func_id)));
458 return err;
459 }
460
461 void netxen_free_hw_resources(struct netxen_adapter *adapter)
462 {
463 struct netxen_recv_context *recv_ctx;
464 struct netxen_rcv_desc_ctx *rcv_desc;
465 int ctx, ring;
466
467 if (adapter->ctx_desc != NULL) {
468 pci_free_consistent(adapter->pdev,
469 sizeof(struct netxen_ring_ctx) +
470 sizeof(uint32_t),
471 adapter->ctx_desc,
472 adapter->ctx_desc_phys_addr);
473 adapter->ctx_desc = NULL;
474 }
475
476 if (adapter->ahw.cmd_desc_head != NULL) {
477 pci_free_consistent(adapter->pdev,
478 sizeof(struct cmd_desc_type0) *
479 adapter->max_tx_desc_count,
480 adapter->ahw.cmd_desc_head,
481 adapter->ahw.cmd_desc_phys_addr);
482 adapter->ahw.cmd_desc_head = NULL;
483 }
484
485 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
486 recv_ctx = &adapter->recv_ctx[ctx];
487 for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
488 rcv_desc = &recv_ctx->rcv_desc[ring];
489
490 if (rcv_desc->desc_head != NULL) {
491 pci_free_consistent(adapter->pdev,
492 RCV_DESC_RINGSIZE,
493 rcv_desc->desc_head,
494 rcv_desc->phys_addr);
495 rcv_desc->desc_head = NULL;
496 }
497 }
498
499 if (recv_ctx->rcv_status_desc_head != NULL) {
500 pci_free_consistent(adapter->pdev,
501 STATUS_DESC_RINGSIZE,
502 recv_ctx->rcv_status_desc_head,
503 recv_ctx->
504 rcv_status_desc_phys_addr);
505 recv_ctx->rcv_status_desc_head = NULL;
506 }
507 }
508 }
509
510 void netxen_tso_check(struct netxen_adapter *adapter,
511 struct cmd_desc_type0 *desc, struct sk_buff *skb)
512 {
513 if (desc->mss) {
514 desc->total_hdr_length = (sizeof(struct ethhdr) +
515 ip_hdrlen(skb) + tcp_hdrlen(skb));
516 netxen_set_cmd_desc_opcode(desc, TX_TCP_LSO);
517 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
518 if (ip_hdr(skb)->protocol == IPPROTO_TCP) {
519 netxen_set_cmd_desc_opcode(desc, TX_TCP_PKT);
520 } else if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
521 netxen_set_cmd_desc_opcode(desc, TX_UDP_PKT);
522 } else {
523 return;
524 }
525 }
526 desc->tcp_hdr_offset = skb_transport_offset(skb);
527 desc->ip_hdr_offset = skb_network_offset(skb);
528 }
529
530 int netxen_is_flash_supported(struct netxen_adapter *adapter)
531 {
532 const int locs[] = { 0, 0x4, 0x100, 0x4000, 0x4128 };
533 int addr, val01, val02, i, j;
534
535 /* if the flash size less than 4Mb, make huge war cry and die */
536 for (j = 1; j < 4; j++) {
537 addr = j * NETXEN_NIC_WINDOW_MARGIN;
538 for (i = 0; i < ARRAY_SIZE(locs); i++) {
539 if (netxen_rom_fast_read(adapter, locs[i], &val01) == 0
540 && netxen_rom_fast_read(adapter, (addr + locs[i]),
541 &val02) == 0) {
542 if (val01 == val02)
543 return -1;
544 } else
545 return -1;
546 }
547 }
548
549 return 0;
550 }
551
552 static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
553 int size, __le32 * buf)
554 {
555 int i, addr;
556 __le32 *ptr32;
557 u32 v;
558
559 addr = base;
560 ptr32 = buf;
561 for (i = 0; i < size / sizeof(u32); i++) {
562 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
563 return -1;
564 *ptr32 = cpu_to_le32(v);
565 ptr32++;
566 addr += sizeof(u32);
567 }
568 if ((char *)buf + size > (char *)ptr32) {
569 __le32 local;
570 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
571 return -1;
572 local = cpu_to_le32(v);
573 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
574 }
575
576 return 0;
577 }
578
579 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 mac[])
580 {
581 __le32 *pmac = (__le32 *) & mac[0];
582
583 if (netxen_get_flash_block(adapter,
584 NETXEN_USER_START +
585 offsetof(struct netxen_new_user_info,
586 mac_addr),
587 FLASH_NUM_PORTS * sizeof(u64), pmac) == -1) {
588 return -1;
589 }
590 if (*mac == cpu_to_le64(~0ULL)) {
591 if (netxen_get_flash_block(adapter,
592 NETXEN_USER_START_OLD +
593 offsetof(struct netxen_user_old_info,
594 mac_addr),
595 FLASH_NUM_PORTS * sizeof(u64),
596 pmac) == -1)
597 return -1;
598 if (*mac == cpu_to_le64(~0ULL))
599 return -1;
600 }
601 return 0;
602 }
603
604 /*
605 * Changes the CRB window to the specified window.
606 */
607 void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw)
608 {
609 void __iomem *offset;
610 u32 tmp;
611 int count = 0;
612 uint8_t func = adapter->ahw.pci_func;
613
614 if (adapter->curr_window == wndw)
615 return;
616 /*
617 * Move the CRB window.
618 * We need to write to the "direct access" region of PCI
619 * to avoid a race condition where the window register has
620 * not been successfully written across CRB before the target
621 * register address is received by PCI. The direct region bypasses
622 * the CRB bus.
623 */
624 offset = PCI_OFFSET_SECOND_RANGE(adapter,
625 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func)));
626
627 if (wndw & 0x1)
628 wndw = NETXEN_WINDOW_ONE;
629
630 writel(wndw, offset);
631
632 /* MUST make sure window is set before we forge on... */
633 while ((tmp = readl(offset)) != wndw) {
634 printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
635 "registered properly: 0x%08x.\n",
636 netxen_nic_driver_name, __FUNCTION__, tmp);
637 mdelay(1);
638 if (count >= 10)
639 break;
640 count++;
641 }
642
643 if (wndw == NETXEN_WINDOW_ONE)
644 adapter->curr_window = 1;
645 else
646 adapter->curr_window = 0;
647 }
648
649 int netxen_load_firmware(struct netxen_adapter *adapter)
650 {
651 int i;
652 u32 data, size = 0;
653 u32 flashaddr = NETXEN_FLASH_BASE, memaddr = NETXEN_PHANTOM_MEM_BASE;
654 u64 off;
655 void __iomem *addr;
656
657 size = NETXEN_FIRMWARE_LEN;
658 writel(1, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST));
659
660 for (i = 0; i < size; i++) {
661 int retries = 10;
662 if (netxen_rom_fast_read(adapter, flashaddr, (int *)&data) != 0)
663 return -EIO;
664
665 off = netxen_nic_pci_set_window(adapter, memaddr);
666 addr = pci_base_offset(adapter, off);
667 writel(data, addr);
668 do {
669 if (readl(addr) == data)
670 break;
671 msleep(100);
672 writel(data, addr);
673 } while (--retries);
674 if (!retries) {
675 printk(KERN_ERR "%s: firmware load aborted, write failed at 0x%x\n",
676 netxen_nic_driver_name, memaddr);
677 return -EIO;
678 }
679 flashaddr += 4;
680 memaddr += 4;
681 }
682 udelay(100);
683 /* make sure Casper is powered on */
684 writel(0x3fff,
685 NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL));
686 writel(0, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST));
687
688 return 0;
689 }
690
691 int
692 netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data,
693 int len)
694 {
695 void __iomem *addr;
696
697 if (ADDR_IN_WINDOW1(off)) {
698 addr = NETXEN_CRB_NORMALIZE(adapter, off);
699 } else { /* Window 0 */
700 addr = pci_base_offset(adapter, off);
701 netxen_nic_pci_change_crbwindow(adapter, 0);
702 }
703
704 DPRINTK(INFO, "writing to base %lx offset %llx addr %p"
705 " data %llx len %d\n",
706 pci_base(adapter, off), off, addr,
707 *(unsigned long long *)data, len);
708 if (!addr) {
709 netxen_nic_pci_change_crbwindow(adapter, 1);
710 return 1;
711 }
712
713 switch (len) {
714 case 1:
715 writeb(*(u8 *) data, addr);
716 break;
717 case 2:
718 writew(*(u16 *) data, addr);
719 break;
720 case 4:
721 writel(*(u32 *) data, addr);
722 break;
723 case 8:
724 writeq(*(u64 *) data, addr);
725 break;
726 default:
727 DPRINTK(INFO,
728 "writing data %lx to offset %llx, num words=%d\n",
729 *(unsigned long *)data, off, (len >> 3));
730
731 netxen_nic_hw_block_write64((u64 __iomem *) data, addr,
732 (len >> 3));
733 break;
734 }
735 if (!ADDR_IN_WINDOW1(off))
736 netxen_nic_pci_change_crbwindow(adapter, 1);
737
738 return 0;
739 }
740
741 int
742 netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data,
743 int len)
744 {
745 void __iomem *addr;
746
747 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
748 addr = NETXEN_CRB_NORMALIZE(adapter, off);
749 } else { /* Window 0 */
750 addr = pci_base_offset(adapter, off);
751 netxen_nic_pci_change_crbwindow(adapter, 0);
752 }
753
754 DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
755 pci_base(adapter, off), off, addr);
756 if (!addr) {
757 netxen_nic_pci_change_crbwindow(adapter, 1);
758 return 1;
759 }
760 switch (len) {
761 case 1:
762 *(u8 *) data = readb(addr);
763 break;
764 case 2:
765 *(u16 *) data = readw(addr);
766 break;
767 case 4:
768 *(u32 *) data = readl(addr);
769 break;
770 case 8:
771 *(u64 *) data = readq(addr);
772 break;
773 default:
774 netxen_nic_hw_block_read64((u64 __iomem *) data, addr,
775 (len >> 3));
776 break;
777 }
778 DPRINTK(INFO, "read %lx\n", *(unsigned long *)data);
779
780 if (!ADDR_IN_WINDOW1(off))
781 netxen_nic_pci_change_crbwindow(adapter, 1);
782
783 return 0;
784 }
785
786 void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val)
787 { /* Only for window 1 */
788 void __iomem *addr;
789
790 addr = NETXEN_CRB_NORMALIZE(adapter, off);
791 DPRINTK(INFO, "writing to base %lx offset %llx addr %p data %x\n",
792 pci_base(adapter, off), off, addr, val);
793 writel(val, addr);
794
795 }
796
797 int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off)
798 { /* Only for window 1 */
799 void __iomem *addr;
800 int val;
801
802 addr = NETXEN_CRB_NORMALIZE(adapter, off);
803 DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
804 pci_base(adapter, off), off, addr);
805 val = readl(addr);
806 writel(val, addr);
807
808 return val;
809 }
810
811 /* Change the window to 0, write and change back to window 1. */
812 void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value)
813 {
814 void __iomem *addr;
815
816 netxen_nic_pci_change_crbwindow(adapter, 0);
817 addr = pci_base_offset(adapter, index);
818 writel(value, addr);
819 netxen_nic_pci_change_crbwindow(adapter, 1);
820 }
821
822 /* Change the window to 0, read and change back to window 1. */
823 void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 * value)
824 {
825 void __iomem *addr;
826
827 addr = pci_base_offset(adapter, index);
828
829 netxen_nic_pci_change_crbwindow(adapter, 0);
830 *value = readl(addr);
831 netxen_nic_pci_change_crbwindow(adapter, 1);
832 }
833
834 static int netxen_pci_set_window_warning_count;
835
836 static unsigned long netxen_nic_pci_set_window(struct netxen_adapter *adapter,
837 unsigned long long addr)
838 {
839 void __iomem *offset;
840 static int ddr_mn_window = -1;
841 static int qdr_sn_window = -1;
842 int window;
843 uint8_t func = adapter->ahw.pci_func;
844
845 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
846 /* DDR network side */
847 addr -= NETXEN_ADDR_DDR_NET;
848 window = (addr >> 25) & 0x3ff;
849 if (ddr_mn_window != window) {
850 ddr_mn_window = window;
851 offset = PCI_OFFSET_SECOND_RANGE(adapter,
852 NETXEN_PCIX_PH_REG(PCIE_MN_WINDOW_REG(func)));
853 writel(window, offset);
854 /* MUST make sure window is set before we forge on... */
855 readl(offset);
856 }
857 addr -= (window * NETXEN_WINDOW_ONE);
858 addr += NETXEN_PCI_DDR_NET;
859 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
860 addr -= NETXEN_ADDR_OCM0;
861 addr += NETXEN_PCI_OCM0;
862 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
863 addr -= NETXEN_ADDR_OCM1;
864 addr += NETXEN_PCI_OCM1;
865 } else
866 if (ADDR_IN_RANGE
867 (addr, NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX_P2)) {
868 /* QDR network side */
869 addr -= NETXEN_ADDR_QDR_NET;
870 window = (addr >> 22) & 0x3f;
871 if (qdr_sn_window != window) {
872 qdr_sn_window = window;
873 offset = PCI_OFFSET_SECOND_RANGE(adapter,
874 NETXEN_PCIX_PH_REG(PCIE_SN_WINDOW_REG(func)));
875 writel((window << 22), offset);
876 /* MUST make sure window is set before we forge on... */
877 readl(offset);
878 }
879 addr -= (window * 0x400000);
880 addr += NETXEN_PCI_QDR_NET;
881 } else {
882 /*
883 * peg gdb frequently accesses memory that doesn't exist,
884 * this limits the chit chat so debugging isn't slowed down.
885 */
886 if ((netxen_pci_set_window_warning_count++ < 8)
887 || (netxen_pci_set_window_warning_count % 64 == 0))
888 printk("%s: Warning:netxen_nic_pci_set_window()"
889 " Unknown address range!\n",
890 netxen_nic_driver_name);
891
892 }
893 return addr;
894 }
895
896 #if 0
897 int
898 netxen_nic_erase_pxe(struct netxen_adapter *adapter)
899 {
900 if (netxen_rom_fast_write(adapter, NETXEN_PXE_START, 0) == -1) {
901 printk(KERN_ERR "%s: erase pxe failed\n",
902 netxen_nic_driver_name);
903 return -1;
904 }
905 return 0;
906 }
907 #endif /* 0 */
908
909 int netxen_nic_get_board_info(struct netxen_adapter *adapter)
910 {
911 int rv = 0;
912 int addr = NETXEN_BRDCFG_START;
913 struct netxen_board_info *boardinfo;
914 int index;
915 u32 *ptr32;
916
917 boardinfo = &adapter->ahw.boardcfg;
918 ptr32 = (u32 *) boardinfo;
919
920 for (index = 0; index < sizeof(struct netxen_board_info) / sizeof(u32);
921 index++) {
922 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
923 return -EIO;
924 }
925 ptr32++;
926 addr += sizeof(u32);
927 }
928 if (boardinfo->magic != NETXEN_BDINFO_MAGIC) {
929 printk("%s: ERROR reading %s board config."
930 " Read %x, expected %x\n", netxen_nic_driver_name,
931 netxen_nic_driver_name,
932 boardinfo->magic, NETXEN_BDINFO_MAGIC);
933 rv = -1;
934 }
935 if (boardinfo->header_version != NETXEN_BDINFO_VERSION) {
936 printk("%s: Unknown board config version."
937 " Read %x, expected %x\n", netxen_nic_driver_name,
938 boardinfo->header_version, NETXEN_BDINFO_VERSION);
939 rv = -1;
940 }
941
942 DPRINTK(INFO, "Discovered board type:0x%x ", boardinfo->board_type);
943 switch ((netxen_brdtype_t) boardinfo->board_type) {
944 case NETXEN_BRDTYPE_P2_SB35_4G:
945 adapter->ahw.board_type = NETXEN_NIC_GBE;
946 break;
947 case NETXEN_BRDTYPE_P2_SB31_10G:
948 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
949 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
950 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
951 case NETXEN_BRDTYPE_P3_HMEZ:
952 case NETXEN_BRDTYPE_P3_XG_LOM:
953 case NETXEN_BRDTYPE_P3_10G_CX4:
954 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
955 case NETXEN_BRDTYPE_P3_IMEZ:
956 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
957 case NETXEN_BRDTYPE_P3_10G_XFP:
958 case NETXEN_BRDTYPE_P3_10000_BASE_T:
959
960 adapter->ahw.board_type = NETXEN_NIC_XGBE;
961 break;
962 case NETXEN_BRDTYPE_P1_BD:
963 case NETXEN_BRDTYPE_P1_SB:
964 case NETXEN_BRDTYPE_P1_SMAX:
965 case NETXEN_BRDTYPE_P1_SOCK:
966 case NETXEN_BRDTYPE_P3_REF_QG:
967 case NETXEN_BRDTYPE_P3_4_GB:
968 case NETXEN_BRDTYPE_P3_4_GB_MM:
969
970 adapter->ahw.board_type = NETXEN_NIC_GBE;
971 break;
972 default:
973 printk("%s: Unknown(%x)\n", netxen_nic_driver_name,
974 boardinfo->board_type);
975 break;
976 }
977
978 return rv;
979 }
980
981 /* NIU access sections */
982
983 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
984 {
985 netxen_nic_write_w0(adapter,
986 NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
987 new_mtu);
988 return 0;
989 }
990
991 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
992 {
993 new_mtu += NETXEN_NIU_HDRSIZE + NETXEN_NIU_TLRSIZE;
994 if (adapter->physical_port == 0)
995 netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE,
996 new_mtu);
997 else
998 netxen_nic_write_w0(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE,
999 new_mtu);
1000 return 0;
1001 }
1002
1003 void netxen_nic_init_niu_gb(struct netxen_adapter *adapter)
1004 {
1005 netxen_niu_gbe_init_port(adapter, adapter->physical_port);
1006 }
1007
1008 void
1009 netxen_crb_writelit_adapter(struct netxen_adapter *adapter, unsigned long off,
1010 int data)
1011 {
1012 void __iomem *addr;
1013
1014 if (ADDR_IN_WINDOW1(off)) {
1015 writel(data, NETXEN_CRB_NORMALIZE(adapter, off));
1016 } else {
1017 netxen_nic_pci_change_crbwindow(adapter, 0);
1018 addr = pci_base_offset(adapter, off);
1019 writel(data, addr);
1020 netxen_nic_pci_change_crbwindow(adapter, 1);
1021 }
1022 }
1023
1024 void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
1025 {
1026 __u32 status;
1027 __u32 autoneg;
1028 __u32 mode;
1029
1030 netxen_nic_read_w0(adapter, NETXEN_NIU_MODE, &mode);
1031 if (netxen_get_niu_enable_ge(mode)) { /* Gb 10/100/1000 Mbps mode */
1032 if (adapter->phy_read
1033 && adapter->
1034 phy_read(adapter,
1035 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
1036 &status) == 0) {
1037 if (netxen_get_phy_link(status)) {
1038 switch (netxen_get_phy_speed(status)) {
1039 case 0:
1040 adapter->link_speed = SPEED_10;
1041 break;
1042 case 1:
1043 adapter->link_speed = SPEED_100;
1044 break;
1045 case 2:
1046 adapter->link_speed = SPEED_1000;
1047 break;
1048 default:
1049 adapter->link_speed = -1;
1050 break;
1051 }
1052 switch (netxen_get_phy_duplex(status)) {
1053 case 0:
1054 adapter->link_duplex = DUPLEX_HALF;
1055 break;
1056 case 1:
1057 adapter->link_duplex = DUPLEX_FULL;
1058 break;
1059 default:
1060 adapter->link_duplex = -1;
1061 break;
1062 }
1063 if (adapter->phy_read
1064 && adapter->
1065 phy_read(adapter,
1066 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
1067 &autoneg) != 0)
1068 adapter->link_autoneg = autoneg;
1069 } else
1070 goto link_down;
1071 } else {
1072 link_down:
1073 adapter->link_speed = -1;
1074 adapter->link_duplex = -1;
1075 }
1076 }
1077 }
1078
1079 void netxen_nic_flash_print(struct netxen_adapter *adapter)
1080 {
1081 u32 fw_major = 0;
1082 u32 fw_minor = 0;
1083 u32 fw_build = 0;
1084 char brd_name[NETXEN_MAX_SHORT_NAME];
1085 char serial_num[32];
1086 int i, addr;
1087 __le32 *ptr32;
1088
1089 struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
1090
1091 adapter->driver_mismatch = 0;
1092
1093 ptr32 = (u32 *)&serial_num;
1094 addr = NETXEN_USER_START +
1095 offsetof(struct netxen_new_user_info, serial_num);
1096 for (i = 0; i < 8; i++) {
1097 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
1098 printk("%s: ERROR reading %s board userarea.\n",
1099 netxen_nic_driver_name,
1100 netxen_nic_driver_name);
1101 adapter->driver_mismatch = 1;
1102 return;
1103 }
1104 ptr32++;
1105 addr += sizeof(u32);
1106 }
1107
1108 fw_major = readl(NETXEN_CRB_NORMALIZE(adapter,
1109 NETXEN_FW_VERSION_MAJOR));
1110 fw_minor = readl(NETXEN_CRB_NORMALIZE(adapter,
1111 NETXEN_FW_VERSION_MINOR));
1112 fw_build =
1113 readl(NETXEN_CRB_NORMALIZE(adapter, NETXEN_FW_VERSION_SUB));
1114
1115 if (adapter->portnum == 0) {
1116 get_brd_name_by_type(board_info->board_type, brd_name);
1117
1118 printk("NetXen %s Board S/N %s Chip id 0x%x\n",
1119 brd_name, serial_num, board_info->chip_id);
1120 printk("NetXen Firmware version %d.%d.%d\n", fw_major,
1121 fw_minor, fw_build);
1122 }
1123
1124 if (fw_major != _NETXEN_NIC_LINUX_MAJOR) {
1125 adapter->driver_mismatch = 1;
1126 }
1127 if (fw_minor != _NETXEN_NIC_LINUX_MINOR &&
1128 fw_minor != (_NETXEN_NIC_LINUX_MINOR + 1)) {
1129 adapter->driver_mismatch = 1;
1130 }
1131 if (adapter->driver_mismatch) {
1132 printk(KERN_ERR "%s: driver and firmware version mismatch\n",
1133 adapter->netdev->name);
1134 return;
1135 }
1136
1137 switch (adapter->ahw.board_type) {
1138 case NETXEN_NIC_GBE:
1139 dev_info(&adapter->pdev->dev, "%s: GbE port initialized\n",
1140 adapter->netdev->name);
1141 break;
1142 case NETXEN_NIC_XGBE:
1143 dev_info(&adapter->pdev->dev, "%s: XGbE port initialized\n",
1144 adapter->netdev->name);
1145 break;
1146 }
1147 }
1148
Linux kernel - Deliverables
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