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[deliverable/linux.git] / drivers / net / netxen / netxen_nic_hw.c
1 /*
2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
22 *
23 * Contact Information:
24 * info@netxen.com
25 * NetXen Inc,
26 * 18922 Forge Drive
27 * Cupertino, CA 95014-0701
28 *
29 */
30
31 #include "netxen_nic.h"
32 #include "netxen_nic_hw.h"
33
34 #include <net/ip.h>
35
36 #define MASK(n) ((1ULL<<(n))-1)
37 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
38 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
39 #define MS_WIN(addr) (addr & 0x0ffc0000)
40
41 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
42
43 #define CRB_BLK(off) ((off >> 20) & 0x3f)
44 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
45 #define CRB_WINDOW_2M (0x130060)
46 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
47 #define CRB_INDIRECT_2M (0x1e0000UL)
48
49 #ifndef readq
50 static inline u64 readq(void __iomem *addr)
51 {
52 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
53 }
54 #endif
55
56 #ifndef writeq
57 static inline void writeq(u64 val, void __iomem *addr)
58 {
59 writel(((u32) (val)), (addr));
60 writel(((u32) (val >> 32)), (addr + 4));
61 }
62 #endif
63
64 #define ADDR_IN_RANGE(addr, low, high) \
65 (((addr) < (high)) && ((addr) >= (low)))
66
67 #define PCI_OFFSET_FIRST_RANGE(adapter, off) \
68 ((adapter)->ahw.pci_base0 + (off))
69 #define PCI_OFFSET_SECOND_RANGE(adapter, off) \
70 ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
71 #define PCI_OFFSET_THIRD_RANGE(adapter, off) \
72 ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
73
74 static void __iomem *pci_base_offset(struct netxen_adapter *adapter,
75 unsigned long off)
76 {
77 if (ADDR_IN_RANGE(off, FIRST_PAGE_GROUP_START, FIRST_PAGE_GROUP_END))
78 return PCI_OFFSET_FIRST_RANGE(adapter, off);
79
80 if (ADDR_IN_RANGE(off, SECOND_PAGE_GROUP_START, SECOND_PAGE_GROUP_END))
81 return PCI_OFFSET_SECOND_RANGE(adapter, off);
82
83 if (ADDR_IN_RANGE(off, THIRD_PAGE_GROUP_START, THIRD_PAGE_GROUP_END))
84 return PCI_OFFSET_THIRD_RANGE(adapter, off);
85
86 return NULL;
87 }
88
89 static crb_128M_2M_block_map_t
90 crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
91 {{{0, 0, 0, 0} } }, /* 0: PCI */
92 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
93 {1, 0x0110000, 0x0120000, 0x130000},
94 {1, 0x0120000, 0x0122000, 0x124000},
95 {1, 0x0130000, 0x0132000, 0x126000},
96 {1, 0x0140000, 0x0142000, 0x128000},
97 {1, 0x0150000, 0x0152000, 0x12a000},
98 {1, 0x0160000, 0x0170000, 0x110000},
99 {1, 0x0170000, 0x0172000, 0x12e000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {1, 0x01e0000, 0x01e0800, 0x122000},
107 {0, 0x0000000, 0x0000000, 0x000000} } },
108 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
109 {{{0, 0, 0, 0} } }, /* 3: */
110 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
111 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
112 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
113 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
114 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {1, 0x08f0000, 0x08f2000, 0x172000} } },
130 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {1, 0x09f0000, 0x09f2000, 0x176000} } },
146 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
162 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
178 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
179 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
180 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
181 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
182 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
183 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
184 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
185 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
186 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
187 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
188 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
189 {{{0, 0, 0, 0} } }, /* 23: */
190 {{{0, 0, 0, 0} } }, /* 24: */
191 {{{0, 0, 0, 0} } }, /* 25: */
192 {{{0, 0, 0, 0} } }, /* 26: */
193 {{{0, 0, 0, 0} } }, /* 27: */
194 {{{0, 0, 0, 0} } }, /* 28: */
195 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
196 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
197 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
198 {{{0} } }, /* 32: PCI */
199 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
200 {1, 0x2110000, 0x2120000, 0x130000},
201 {1, 0x2120000, 0x2122000, 0x124000},
202 {1, 0x2130000, 0x2132000, 0x126000},
203 {1, 0x2140000, 0x2142000, 0x128000},
204 {1, 0x2150000, 0x2152000, 0x12a000},
205 {1, 0x2160000, 0x2170000, 0x110000},
206 {1, 0x2170000, 0x2172000, 0x12e000},
207 {0, 0x0000000, 0x0000000, 0x000000},
208 {0, 0x0000000, 0x0000000, 0x000000},
209 {0, 0x0000000, 0x0000000, 0x000000},
210 {0, 0x0000000, 0x0000000, 0x000000},
211 {0, 0x0000000, 0x0000000, 0x000000},
212 {0, 0x0000000, 0x0000000, 0x000000},
213 {0, 0x0000000, 0x0000000, 0x000000},
214 {0, 0x0000000, 0x0000000, 0x000000} } },
215 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
216 {{{0} } }, /* 35: */
217 {{{0} } }, /* 36: */
218 {{{0} } }, /* 37: */
219 {{{0} } }, /* 38: */
220 {{{0} } }, /* 39: */
221 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
222 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
223 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
224 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
225 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
226 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
227 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
228 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
229 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
230 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
231 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
232 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
233 {{{0} } }, /* 52: */
234 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
235 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
236 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
237 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
238 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
239 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
240 {{{0} } }, /* 59: I2C0 */
241 {{{0} } }, /* 60: I2C1 */
242 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
243 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
244 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
245 };
246
247 /*
248 * top 12 bits of crb internal address (hub, agent)
249 */
250 static unsigned crb_hub_agt[64] =
251 {
252 0,
253 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
254 NETXEN_HW_CRB_HUB_AGT_ADR_MN,
255 NETXEN_HW_CRB_HUB_AGT_ADR_MS,
256 0,
257 NETXEN_HW_CRB_HUB_AGT_ADR_SRE,
258 NETXEN_HW_CRB_HUB_AGT_ADR_NIU,
259 NETXEN_HW_CRB_HUB_AGT_ADR_QMN,
260 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0,
261 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1,
262 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2,
263 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3,
264 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
265 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
266 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
267 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4,
268 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
269 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0,
270 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1,
271 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2,
272 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3,
273 NETXEN_HW_CRB_HUB_AGT_ADR_PGND,
274 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI,
275 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0,
276 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1,
277 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2,
278 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3,
279 0,
280 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI,
281 NETXEN_HW_CRB_HUB_AGT_ADR_SN,
282 0,
283 NETXEN_HW_CRB_HUB_AGT_ADR_EG,
284 0,
285 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
286 NETXEN_HW_CRB_HUB_AGT_ADR_CAM,
287 0,
288 0,
289 0,
290 0,
291 0,
292 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
293 0,
294 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1,
295 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2,
296 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3,
297 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4,
298 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5,
299 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6,
300 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7,
301 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
302 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
303 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
304 0,
305 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0,
306 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8,
307 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9,
308 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0,
309 0,
310 NETXEN_HW_CRB_HUB_AGT_ADR_SMB,
311 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0,
312 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1,
313 0,
314 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC,
315 0,
316 };
317
318 /* PCI Windowing for DDR regions. */
319
320 #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
321
322 #define NETXEN_PCIE_SEM_TIMEOUT 10000
323
324 int
325 netxen_pcie_sem_lock(struct netxen_adapter *adapter, int sem, u32 id_reg)
326 {
327 int done = 0, timeout = 0;
328
329 while (!done) {
330 done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_LOCK(sem)));
331 if (done == 1)
332 break;
333 if (++timeout >= NETXEN_PCIE_SEM_TIMEOUT)
334 return -1;
335 msleep(1);
336 }
337
338 if (id_reg)
339 NXWR32(adapter, id_reg, adapter->portnum);
340
341 return 0;
342 }
343
344 void
345 netxen_pcie_sem_unlock(struct netxen_adapter *adapter, int sem)
346 {
347 int val;
348 val = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
349 }
350
351 #define NETXEN_UNICAST_ADDR(port, index) \
352 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
353 #define NETXEN_MCAST_ADDR(port, index) \
354 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
355 #define MAC_HI(addr) \
356 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
357 #define MAC_LO(addr) \
358 ((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
359
360 static int
361 netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
362 {
363 u32 val = 0;
364 u16 port = adapter->physical_port;
365 u8 *addr = adapter->netdev->dev_addr;
366
367 if (adapter->mc_enabled)
368 return 0;
369
370 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
371 val |= (1UL << (28+port));
372 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
373
374 /* add broadcast addr to filter */
375 val = 0xffffff;
376 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
377 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
378
379 /* add station addr to filter */
380 val = MAC_HI(addr);
381 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
382 val = MAC_LO(addr);
383 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, val);
384
385 adapter->mc_enabled = 1;
386 return 0;
387 }
388
389 static int
390 netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
391 {
392 u32 val = 0;
393 u16 port = adapter->physical_port;
394 u8 *addr = adapter->netdev->dev_addr;
395
396 if (!adapter->mc_enabled)
397 return 0;
398
399 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
400 val &= ~(1UL << (28+port));
401 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
402
403 val = MAC_HI(addr);
404 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
405 val = MAC_LO(addr);
406 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
407
408 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
409 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
410
411 adapter->mc_enabled = 0;
412 return 0;
413 }
414
415 static int
416 netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
417 int index, u8 *addr)
418 {
419 u32 hi = 0, lo = 0;
420 u16 port = adapter->physical_port;
421
422 lo = MAC_LO(addr);
423 hi = MAC_HI(addr);
424
425 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index), hi);
426 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index)+4, lo);
427
428 return 0;
429 }
430
431 void netxen_p2_nic_set_multi(struct net_device *netdev)
432 {
433 struct netxen_adapter *adapter = netdev_priv(netdev);
434 struct dev_mc_list *mc_ptr;
435 u8 null_addr[6];
436 int index = 0;
437
438 memset(null_addr, 0, 6);
439
440 if (netdev->flags & IFF_PROMISC) {
441
442 adapter->set_promisc(adapter,
443 NETXEN_NIU_PROMISC_MODE);
444
445 /* Full promiscuous mode */
446 netxen_nic_disable_mcast_filter(adapter);
447
448 return;
449 }
450
451 if (netdev->mc_count == 0) {
452 adapter->set_promisc(adapter,
453 NETXEN_NIU_NON_PROMISC_MODE);
454 netxen_nic_disable_mcast_filter(adapter);
455 return;
456 }
457
458 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE);
459 if (netdev->flags & IFF_ALLMULTI ||
460 netdev->mc_count > adapter->max_mc_count) {
461 netxen_nic_disable_mcast_filter(adapter);
462 return;
463 }
464
465 netxen_nic_enable_mcast_filter(adapter);
466
467 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next, index++)
468 netxen_nic_set_mcast_addr(adapter, index, mc_ptr->dmi_addr);
469
470 if (index != netdev->mc_count)
471 printk(KERN_WARNING "%s: %s multicast address count mismatch\n",
472 netxen_nic_driver_name, netdev->name);
473
474 /* Clear out remaining addresses */
475 for (; index < adapter->max_mc_count; index++)
476 netxen_nic_set_mcast_addr(adapter, index, null_addr);
477 }
478
479 static int
480 netxen_send_cmd_descs(struct netxen_adapter *adapter,
481 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
482 {
483 u32 i, producer, consumer;
484 struct netxen_cmd_buffer *pbuf;
485 struct cmd_desc_type0 *cmd_desc;
486 struct nx_host_tx_ring *tx_ring;
487
488 i = 0;
489
490 tx_ring = adapter->tx_ring;
491 __netif_tx_lock_bh(tx_ring->txq);
492
493 producer = tx_ring->producer;
494 consumer = tx_ring->sw_consumer;
495
496 if (nr_desc >= netxen_tx_avail(tx_ring)) {
497 netif_tx_stop_queue(tx_ring->txq);
498 __netif_tx_unlock_bh(tx_ring->txq);
499 return -EBUSY;
500 }
501
502 do {
503 cmd_desc = &cmd_desc_arr[i];
504
505 pbuf = &tx_ring->cmd_buf_arr[producer];
506 pbuf->skb = NULL;
507 pbuf->frag_count = 0;
508
509 memcpy(&tx_ring->desc_head[producer],
510 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
511
512 producer = get_next_index(producer, tx_ring->num_desc);
513 i++;
514
515 } while (i != nr_desc);
516
517 tx_ring->producer = producer;
518
519 netxen_nic_update_cmd_producer(adapter, tx_ring);
520
521 __netif_tx_unlock_bh(tx_ring->txq);
522
523 return 0;
524 }
525
526 static int
527 nx_p3_sre_macaddr_change(struct netxen_adapter *adapter, u8 *addr, unsigned op)
528 {
529 nx_nic_req_t req;
530 nx_mac_req_t *mac_req;
531 u64 word;
532
533 memset(&req, 0, sizeof(nx_nic_req_t));
534 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
535
536 word = NX_MAC_EVENT | ((u64)adapter->portnum << 16);
537 req.req_hdr = cpu_to_le64(word);
538
539 mac_req = (nx_mac_req_t *)&req.words[0];
540 mac_req->op = op;
541 memcpy(mac_req->mac_addr, addr, 6);
542
543 return netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
544 }
545
546 static int nx_p3_nic_add_mac(struct netxen_adapter *adapter,
547 u8 *addr, struct list_head *del_list)
548 {
549 struct list_head *head;
550 nx_mac_list_t *cur;
551
552 /* look up if already exists */
553 list_for_each(head, del_list) {
554 cur = list_entry(head, nx_mac_list_t, list);
555
556 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) {
557 list_move_tail(head, &adapter->mac_list);
558 return 0;
559 }
560 }
561
562 cur = kzalloc(sizeof(nx_mac_list_t), GFP_ATOMIC);
563 if (cur == NULL) {
564 printk(KERN_ERR "%s: failed to add mac address filter\n",
565 adapter->netdev->name);
566 return -ENOMEM;
567 }
568 memcpy(cur->mac_addr, addr, ETH_ALEN);
569 list_add_tail(&cur->list, &adapter->mac_list);
570 return nx_p3_sre_macaddr_change(adapter,
571 cur->mac_addr, NETXEN_MAC_ADD);
572 }
573
574 void netxen_p3_nic_set_multi(struct net_device *netdev)
575 {
576 struct netxen_adapter *adapter = netdev_priv(netdev);
577 struct dev_mc_list *mc_ptr;
578 u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
579 u32 mode = VPORT_MISS_MODE_DROP;
580 LIST_HEAD(del_list);
581 struct list_head *head;
582 nx_mac_list_t *cur;
583
584 list_splice_tail_init(&adapter->mac_list, &del_list);
585
586 nx_p3_nic_add_mac(adapter, netdev->dev_addr, &del_list);
587 nx_p3_nic_add_mac(adapter, bcast_addr, &del_list);
588
589 if (netdev->flags & IFF_PROMISC) {
590 mode = VPORT_MISS_MODE_ACCEPT_ALL;
591 goto send_fw_cmd;
592 }
593
594 if ((netdev->flags & IFF_ALLMULTI) ||
595 (netdev->mc_count > adapter->max_mc_count)) {
596 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
597 goto send_fw_cmd;
598 }
599
600 if (netdev->mc_count > 0) {
601 for (mc_ptr = netdev->mc_list; mc_ptr;
602 mc_ptr = mc_ptr->next) {
603 nx_p3_nic_add_mac(adapter, mc_ptr->dmi_addr, &del_list);
604 }
605 }
606
607 send_fw_cmd:
608 adapter->set_promisc(adapter, mode);
609 head = &del_list;
610 while (!list_empty(head)) {
611 cur = list_entry(head->next, nx_mac_list_t, list);
612
613 nx_p3_sre_macaddr_change(adapter,
614 cur->mac_addr, NETXEN_MAC_DEL);
615 list_del(&cur->list);
616 kfree(cur);
617 }
618 }
619
620 int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
621 {
622 nx_nic_req_t req;
623 u64 word;
624
625 memset(&req, 0, sizeof(nx_nic_req_t));
626
627 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
628
629 word = NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
630 ((u64)adapter->portnum << 16);
631 req.req_hdr = cpu_to_le64(word);
632
633 req.words[0] = cpu_to_le64(mode);
634
635 return netxen_send_cmd_descs(adapter,
636 (struct cmd_desc_type0 *)&req, 1);
637 }
638
639 void netxen_p3_free_mac_list(struct netxen_adapter *adapter)
640 {
641 nx_mac_list_t *cur;
642 struct list_head *head = &adapter->mac_list;
643
644 while (!list_empty(head)) {
645 cur = list_entry(head->next, nx_mac_list_t, list);
646 nx_p3_sre_macaddr_change(adapter,
647 cur->mac_addr, NETXEN_MAC_DEL);
648 list_del(&cur->list);
649 kfree(cur);
650 }
651 }
652
653 int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
654 {
655 /* assuming caller has already copied new addr to netdev */
656 netxen_p3_nic_set_multi(adapter->netdev);
657 return 0;
658 }
659
660 #define NETXEN_CONFIG_INTR_COALESCE 3
661
662 /*
663 * Send the interrupt coalescing parameter set by ethtool to the card.
664 */
665 int netxen_config_intr_coalesce(struct netxen_adapter *adapter)
666 {
667 nx_nic_req_t req;
668 u64 word;
669 int rv;
670
671 memset(&req, 0, sizeof(nx_nic_req_t));
672
673 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
674
675 word = NETXEN_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
676 req.req_hdr = cpu_to_le64(word);
677
678 memcpy(&req.words[0], &adapter->coal, sizeof(adapter->coal));
679
680 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
681 if (rv != 0) {
682 printk(KERN_ERR "ERROR. Could not send "
683 "interrupt coalescing parameters\n");
684 }
685
686 return rv;
687 }
688
689 int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable)
690 {
691 nx_nic_req_t req;
692 u64 word;
693 int rv = 0;
694
695 if ((adapter->flags & NETXEN_NIC_LRO_ENABLED) == enable)
696 return 0;
697
698 memset(&req, 0, sizeof(nx_nic_req_t));
699
700 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
701
702 word = NX_NIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
703 req.req_hdr = cpu_to_le64(word);
704
705 req.words[0] = cpu_to_le64(enable);
706
707 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
708 if (rv != 0) {
709 printk(KERN_ERR "ERROR. Could not send "
710 "configure hw lro request\n");
711 }
712
713 adapter->flags ^= NETXEN_NIC_LRO_ENABLED;
714
715 return rv;
716 }
717
718 #define RSS_HASHTYPE_IP_TCP 0x3
719
720 int netxen_config_rss(struct netxen_adapter *adapter, int enable)
721 {
722 nx_nic_req_t req;
723 u64 word;
724 int i, rv;
725
726 u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
727 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
728 0x255b0ec26d5a56daULL };
729
730
731 memset(&req, 0, sizeof(nx_nic_req_t));
732 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
733
734 word = NX_NIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
735 req.req_hdr = cpu_to_le64(word);
736
737 /*
738 * RSS request:
739 * bits 3-0: hash_method
740 * 5-4: hash_type_ipv4
741 * 7-6: hash_type_ipv6
742 * 8: enable
743 * 9: use indirection table
744 * 47-10: reserved
745 * 63-48: indirection table mask
746 */
747 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
748 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
749 ((u64)(enable & 0x1) << 8) |
750 ((0x7ULL) << 48);
751 req.words[0] = cpu_to_le64(word);
752 for (i = 0; i < 5; i++)
753 req.words[i+1] = cpu_to_le64(key[i]);
754
755
756 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
757 if (rv != 0) {
758 printk(KERN_ERR "%s: could not configure RSS\n",
759 adapter->netdev->name);
760 }
761
762 return rv;
763 }
764
765 int netxen_config_ipaddr(struct netxen_adapter *adapter, u32 ip, int cmd)
766 {
767 nx_nic_req_t req;
768 u64 word;
769 int rv;
770
771 memset(&req, 0, sizeof(nx_nic_req_t));
772 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
773
774 word = NX_NIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
775 req.req_hdr = cpu_to_le64(word);
776
777 req.words[0] = cpu_to_le64(cmd);
778 req.words[1] = cpu_to_le64(ip);
779
780 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
781 if (rv != 0) {
782 printk(KERN_ERR "%s: could not notify %s IP 0x%x reuqest\n",
783 adapter->netdev->name,
784 (cmd == NX_IP_UP) ? "Add" : "Remove", ip);
785 }
786 return rv;
787 }
788
789 int netxen_linkevent_request(struct netxen_adapter *adapter, int enable)
790 {
791 nx_nic_req_t req;
792 u64 word;
793 int rv;
794
795 memset(&req, 0, sizeof(nx_nic_req_t));
796 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
797
798 word = NX_NIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
799 req.req_hdr = cpu_to_le64(word);
800 req.words[0] = cpu_to_le64(enable | (enable << 8));
801
802 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
803 if (rv != 0) {
804 printk(KERN_ERR "%s: could not configure link notification\n",
805 adapter->netdev->name);
806 }
807
808 return rv;
809 }
810
811 int netxen_send_lro_cleanup(struct netxen_adapter *adapter)
812 {
813 nx_nic_req_t req;
814 u64 word;
815 int rv;
816
817 memset(&req, 0, sizeof(nx_nic_req_t));
818 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
819
820 word = NX_NIC_H2C_OPCODE_LRO_REQUEST |
821 ((u64)adapter->portnum << 16) |
822 ((u64)NX_NIC_LRO_REQUEST_CLEANUP << 56) ;
823
824 req.req_hdr = cpu_to_le64(word);
825
826 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
827 if (rv != 0) {
828 printk(KERN_ERR "%s: could not cleanup lro flows\n",
829 adapter->netdev->name);
830 }
831 return rv;
832 }
833
834 /*
835 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
836 * @returns 0 on success, negative on failure
837 */
838
839 #define MTU_FUDGE_FACTOR 100
840
841 int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
842 {
843 struct netxen_adapter *adapter = netdev_priv(netdev);
844 int max_mtu;
845 int rc = 0;
846
847 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
848 max_mtu = P3_MAX_MTU;
849 else
850 max_mtu = P2_MAX_MTU;
851
852 if (mtu > max_mtu) {
853 printk(KERN_ERR "%s: mtu > %d bytes unsupported\n",
854 netdev->name, max_mtu);
855 return -EINVAL;
856 }
857
858 if (adapter->set_mtu)
859 rc = adapter->set_mtu(adapter, mtu);
860
861 if (!rc)
862 netdev->mtu = mtu;
863
864 return rc;
865 }
866
867 static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
868 int size, __le32 * buf)
869 {
870 int i, v, addr;
871 __le32 *ptr32;
872
873 addr = base;
874 ptr32 = buf;
875 for (i = 0; i < size / sizeof(u32); i++) {
876 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
877 return -1;
878 *ptr32 = cpu_to_le32(v);
879 ptr32++;
880 addr += sizeof(u32);
881 }
882 if ((char *)buf + size > (char *)ptr32) {
883 __le32 local;
884 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
885 return -1;
886 local = cpu_to_le32(v);
887 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
888 }
889
890 return 0;
891 }
892
893 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
894 {
895 __le32 *pmac = (__le32 *) mac;
896 u32 offset;
897
898 offset = NX_FW_MAC_ADDR_OFFSET + (adapter->portnum * sizeof(u64));
899
900 if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1)
901 return -1;
902
903 if (*mac == cpu_to_le64(~0ULL)) {
904
905 offset = NX_OLD_MAC_ADDR_OFFSET +
906 (adapter->portnum * sizeof(u64));
907
908 if (netxen_get_flash_block(adapter,
909 offset, sizeof(u64), pmac) == -1)
910 return -1;
911
912 if (*mac == cpu_to_le64(~0ULL))
913 return -1;
914 }
915 return 0;
916 }
917
918 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
919 {
920 uint32_t crbaddr, mac_hi, mac_lo;
921 int pci_func = adapter->ahw.pci_func;
922
923 crbaddr = CRB_MAC_BLOCK_START +
924 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
925
926 mac_lo = NXRD32(adapter, crbaddr);
927 mac_hi = NXRD32(adapter, crbaddr+4);
928
929 if (pci_func & 1)
930 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
931 else
932 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32));
933
934 return 0;
935 }
936
937 /*
938 * Changes the CRB window to the specified window.
939 */
940 void
941 netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter, u32 wndw)
942 {
943 void __iomem *offset;
944 u32 tmp;
945 int count = 0;
946 uint8_t func = adapter->ahw.pci_func;
947
948 if (adapter->curr_window == wndw)
949 return;
950 /*
951 * Move the CRB window.
952 * We need to write to the "direct access" region of PCI
953 * to avoid a race condition where the window register has
954 * not been successfully written across CRB before the target
955 * register address is received by PCI. The direct region bypasses
956 * the CRB bus.
957 */
958 offset = PCI_OFFSET_SECOND_RANGE(adapter,
959 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func)));
960
961 if (wndw & 0x1)
962 wndw = NETXEN_WINDOW_ONE;
963
964 writel(wndw, offset);
965
966 /* MUST make sure window is set before we forge on... */
967 while ((tmp = readl(offset)) != wndw) {
968 printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
969 "registered properly: 0x%08x.\n",
970 netxen_nic_driver_name, __func__, tmp);
971 mdelay(1);
972 if (count >= 10)
973 break;
974 count++;
975 }
976
977 if (wndw == NETXEN_WINDOW_ONE)
978 adapter->curr_window = 1;
979 else
980 adapter->curr_window = 0;
981 }
982
983 /*
984 * Return -1 if off is not valid,
985 * 1 if window access is needed. 'off' is set to offset from
986 * CRB space in 128M pci map
987 * 0 if no window access is needed. 'off' is set to 2M addr
988 * In: 'off' is offset from base in 128M pci map
989 */
990 static int
991 netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter, ulong *off)
992 {
993 crb_128M_2M_sub_block_map_t *m;
994
995
996 if (*off >= NETXEN_CRB_MAX)
997 return -1;
998
999 if (*off >= NETXEN_PCI_CAMQM && (*off < NETXEN_PCI_CAMQM_2M_END)) {
1000 *off = (*off - NETXEN_PCI_CAMQM) + NETXEN_PCI_CAMQM_2M_BASE +
1001 (ulong)adapter->ahw.pci_base0;
1002 return 0;
1003 }
1004
1005 if (*off < NETXEN_PCI_CRBSPACE)
1006 return -1;
1007
1008 *off -= NETXEN_PCI_CRBSPACE;
1009
1010 /*
1011 * Try direct map
1012 */
1013 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
1014
1015 if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
1016 *off = *off + m->start_2M - m->start_128M +
1017 (ulong)adapter->ahw.pci_base0;
1018 return 0;
1019 }
1020
1021 /*
1022 * Not in direct map, use crb window
1023 */
1024 return 1;
1025 }
1026
1027 /*
1028 * In: 'off' is offset from CRB space in 128M pci map
1029 * Out: 'off' is 2M pci map addr
1030 * side effect: lock crb window
1031 */
1032 static void
1033 netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong *off)
1034 {
1035 u32 win_read;
1036
1037 adapter->crb_win = CRB_HI(*off);
1038 writel(adapter->crb_win, (adapter->ahw.pci_base0 + CRB_WINDOW_2M));
1039 /*
1040 * Read back value to make sure write has gone through before trying
1041 * to use it.
1042 */
1043 win_read = readl(adapter->ahw.pci_base0 + CRB_WINDOW_2M);
1044 if (win_read != adapter->crb_win) {
1045 printk(KERN_ERR "%s: Written crbwin (0x%x) != "
1046 "Read crbwin (0x%x), off=0x%lx\n",
1047 __func__, adapter->crb_win, win_read, *off);
1048 }
1049 *off = (*off & MASK(16)) + CRB_INDIRECT_2M +
1050 (ulong)adapter->ahw.pci_base0;
1051 }
1052
1053 int
1054 netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, ulong off, u32 data)
1055 {
1056 void __iomem *addr;
1057
1058 if (ADDR_IN_WINDOW1(off)) {
1059 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1060 } else { /* Window 0 */
1061 addr = pci_base_offset(adapter, off);
1062 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1063 }
1064
1065 if (!addr) {
1066 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1067 return 1;
1068 }
1069
1070 writel(data, addr);
1071
1072 if (!ADDR_IN_WINDOW1(off))
1073 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1074
1075 return 0;
1076 }
1077
1078 u32
1079 netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off)
1080 {
1081 void __iomem *addr;
1082 u32 data;
1083
1084 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1085 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1086 } else { /* Window 0 */
1087 addr = pci_base_offset(adapter, off);
1088 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1089 }
1090
1091 if (!addr) {
1092 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1093 return 1;
1094 }
1095
1096 data = readl(addr);
1097
1098 if (!ADDR_IN_WINDOW1(off))
1099 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1100
1101 return data;
1102 }
1103
1104 int
1105 netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, ulong off, u32 data)
1106 {
1107 unsigned long flags = 0;
1108 int rv;
1109
1110 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off);
1111
1112 if (rv == -1) {
1113 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1114 __func__, off);
1115 dump_stack();
1116 return -1;
1117 }
1118
1119 if (rv == 1) {
1120 write_lock_irqsave(&adapter->adapter_lock, flags);
1121 crb_win_lock(adapter);
1122 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1123 writel(data, (void __iomem *)off);
1124 crb_win_unlock(adapter);
1125 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1126 } else
1127 writel(data, (void __iomem *)off);
1128
1129
1130 return 0;
1131 }
1132
1133 u32
1134 netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off)
1135 {
1136 unsigned long flags = 0;
1137 int rv;
1138 u32 data;
1139
1140 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off);
1141
1142 if (rv == -1) {
1143 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1144 __func__, off);
1145 dump_stack();
1146 return -1;
1147 }
1148
1149 if (rv == 1) {
1150 write_lock_irqsave(&adapter->adapter_lock, flags);
1151 crb_win_lock(adapter);
1152 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1153 data = readl((void __iomem *)off);
1154 crb_win_unlock(adapter);
1155 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1156 } else
1157 data = readl((void __iomem *)off);
1158
1159 return data;
1160 }
1161
1162 /*
1163 * check memory access boundary.
1164 * used by test agent. support ddr access only for now
1165 */
1166 static unsigned long
1167 netxen_nic_pci_mem_bound_check(struct netxen_adapter *adapter,
1168 unsigned long long addr, int size)
1169 {
1170 if (!ADDR_IN_RANGE(addr,
1171 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1172 !ADDR_IN_RANGE(addr+size-1,
1173 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1174 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
1175 return 0;
1176 }
1177
1178 return 1;
1179 }
1180
1181 static int netxen_pci_set_window_warning_count;
1182
1183 unsigned long
1184 netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1185 unsigned long long addr)
1186 {
1187 void __iomem *offset;
1188 int window;
1189 unsigned long long qdr_max;
1190 uint8_t func = adapter->ahw.pci_func;
1191
1192 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1193 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1194 } else {
1195 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1196 }
1197
1198 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1199 /* DDR network side */
1200 addr -= NETXEN_ADDR_DDR_NET;
1201 window = (addr >> 25) & 0x3ff;
1202 if (adapter->ahw.ddr_mn_window != window) {
1203 adapter->ahw.ddr_mn_window = window;
1204 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1205 NETXEN_PCIX_PH_REG(PCIE_MN_WINDOW_REG(func)));
1206 writel(window, offset);
1207 /* MUST make sure window is set before we forge on... */
1208 readl(offset);
1209 }
1210 addr -= (window * NETXEN_WINDOW_ONE);
1211 addr += NETXEN_PCI_DDR_NET;
1212 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1213 addr -= NETXEN_ADDR_OCM0;
1214 addr += NETXEN_PCI_OCM0;
1215 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1216 addr -= NETXEN_ADDR_OCM1;
1217 addr += NETXEN_PCI_OCM1;
1218 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1219 /* QDR network side */
1220 addr -= NETXEN_ADDR_QDR_NET;
1221 window = (addr >> 22) & 0x3f;
1222 if (adapter->ahw.qdr_sn_window != window) {
1223 adapter->ahw.qdr_sn_window = window;
1224 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1225 NETXEN_PCIX_PH_REG(PCIE_SN_WINDOW_REG(func)));
1226 writel((window << 22), offset);
1227 /* MUST make sure window is set before we forge on... */
1228 readl(offset);
1229 }
1230 addr -= (window * 0x400000);
1231 addr += NETXEN_PCI_QDR_NET;
1232 } else {
1233 /*
1234 * peg gdb frequently accesses memory that doesn't exist,
1235 * this limits the chit chat so debugging isn't slowed down.
1236 */
1237 if ((netxen_pci_set_window_warning_count++ < 8)
1238 || (netxen_pci_set_window_warning_count % 64 == 0))
1239 printk("%s: Warning:netxen_nic_pci_set_window()"
1240 " Unknown address range!\n",
1241 netxen_nic_driver_name);
1242 addr = -1UL;
1243 }
1244 return addr;
1245 }
1246
1247 /*
1248 * Note : only 32-bit writes!
1249 */
1250 int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1251 u64 off, u32 data)
1252 {
1253 writel(data, (void __iomem *)(PCI_OFFSET_SECOND_RANGE(adapter, off)));
1254 return 0;
1255 }
1256
1257 u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off)
1258 {
1259 return readl((void __iomem *)(pci_base_offset(adapter, off)));
1260 }
1261
1262 unsigned long
1263 netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1264 unsigned long long addr)
1265 {
1266 int window;
1267 u32 win_read;
1268
1269 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1270 /* DDR network side */
1271 window = MN_WIN(addr);
1272 adapter->ahw.ddr_mn_window = window;
1273 NXWR32(adapter, adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1274 window);
1275 win_read = NXRD32(adapter,
1276 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE);
1277 if ((win_read << 17) != window) {
1278 printk(KERN_INFO "Written MNwin (0x%x) != "
1279 "Read MNwin (0x%x)\n", window, win_read);
1280 }
1281 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_DDR_NET;
1282 } else if (ADDR_IN_RANGE(addr,
1283 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1284 if ((addr & 0x00ff800) == 0xff800) {
1285 printk("%s: QM access not handled.\n", __func__);
1286 addr = -1UL;
1287 }
1288
1289 window = OCM_WIN(addr);
1290 adapter->ahw.ddr_mn_window = window;
1291 NXWR32(adapter, adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1292 window);
1293 win_read = NXRD32(adapter,
1294 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE);
1295 if ((win_read >> 7) != window) {
1296 printk(KERN_INFO "%s: Written OCMwin (0x%x) != "
1297 "Read OCMwin (0x%x)\n",
1298 __func__, window, win_read);
1299 }
1300 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_OCM0_2M;
1301
1302 } else if (ADDR_IN_RANGE(addr,
1303 NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX_P3)) {
1304 /* QDR network side */
1305 window = MS_WIN(addr);
1306 adapter->ahw.qdr_sn_window = window;
1307 NXWR32(adapter, adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1308 window);
1309 win_read = NXRD32(adapter,
1310 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE);
1311 if (win_read != window) {
1312 printk(KERN_INFO "%s: Written MSwin (0x%x) != "
1313 "Read MSwin (0x%x)\n",
1314 __func__, window, win_read);
1315 }
1316 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_QDR_NET;
1317
1318 } else {
1319 /*
1320 * peg gdb frequently accesses memory that doesn't exist,
1321 * this limits the chit chat so debugging isn't slowed down.
1322 */
1323 if ((netxen_pci_set_window_warning_count++ < 8)
1324 || (netxen_pci_set_window_warning_count%64 == 0)) {
1325 printk("%s: Warning:%s Unknown address range!\n",
1326 __func__, netxen_nic_driver_name);
1327 }
1328 addr = -1UL;
1329 }
1330 return addr;
1331 }
1332
1333 static int netxen_nic_pci_is_same_window(struct netxen_adapter *adapter,
1334 unsigned long long addr)
1335 {
1336 int window;
1337 unsigned long long qdr_max;
1338
1339 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1340 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1341 else
1342 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1343
1344 if (ADDR_IN_RANGE(addr,
1345 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1346 /* DDR network side */
1347 BUG(); /* MN access can not come here */
1348 } else if (ADDR_IN_RANGE(addr,
1349 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1350 return 1;
1351 } else if (ADDR_IN_RANGE(addr,
1352 NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1353 return 1;
1354 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1355 /* QDR network side */
1356 window = ((addr - NETXEN_ADDR_QDR_NET) >> 22) & 0x3f;
1357 if (adapter->ahw.qdr_sn_window == window)
1358 return 1;
1359 }
1360
1361 return 0;
1362 }
1363
1364 static int netxen_nic_pci_mem_read_direct(struct netxen_adapter *adapter,
1365 u64 off, void *data, int size)
1366 {
1367 unsigned long flags;
1368 void __iomem *addr, *mem_ptr = NULL;
1369 int ret = 0;
1370 u64 start;
1371 unsigned long mem_base;
1372 unsigned long mem_page;
1373
1374 write_lock_irqsave(&adapter->adapter_lock, flags);
1375
1376 /*
1377 * If attempting to access unknown address or straddle hw windows,
1378 * do not access.
1379 */
1380 start = adapter->pci_set_window(adapter, off);
1381 if ((start == -1UL) ||
1382 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1383 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1384 printk(KERN_ERR "%s out of bound pci memory access. "
1385 "offset is 0x%llx\n", netxen_nic_driver_name,
1386 (unsigned long long)off);
1387 return -1;
1388 }
1389
1390 addr = pci_base_offset(adapter, start);
1391 if (!addr) {
1392 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1393 mem_base = pci_resource_start(adapter->pdev, 0);
1394 mem_page = start & PAGE_MASK;
1395 /* Map two pages whenever user tries to access addresses in two
1396 consecutive pages.
1397 */
1398 if (mem_page != ((start + size - 1) & PAGE_MASK))
1399 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
1400 else
1401 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
1402 if (mem_ptr == NULL) {
1403 *(uint8_t *)data = 0;
1404 return -1;
1405 }
1406 addr = mem_ptr;
1407 addr += start & (PAGE_SIZE - 1);
1408 write_lock_irqsave(&adapter->adapter_lock, flags);
1409 }
1410
1411 switch (size) {
1412 case 1:
1413 *(uint8_t *)data = readb(addr);
1414 break;
1415 case 2:
1416 *(uint16_t *)data = readw(addr);
1417 break;
1418 case 4:
1419 *(uint32_t *)data = readl(addr);
1420 break;
1421 case 8:
1422 *(uint64_t *)data = readq(addr);
1423 break;
1424 default:
1425 ret = -1;
1426 break;
1427 }
1428 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1429
1430 if (mem_ptr)
1431 iounmap(mem_ptr);
1432 return ret;
1433 }
1434
1435 static int
1436 netxen_nic_pci_mem_write_direct(struct netxen_adapter *adapter, u64 off,
1437 void *data, int size)
1438 {
1439 unsigned long flags;
1440 void __iomem *addr, *mem_ptr = NULL;
1441 int ret = 0;
1442 u64 start;
1443 unsigned long mem_base;
1444 unsigned long mem_page;
1445
1446 write_lock_irqsave(&adapter->adapter_lock, flags);
1447
1448 /*
1449 * If attempting to access unknown address or straddle hw windows,
1450 * do not access.
1451 */
1452 start = adapter->pci_set_window(adapter, off);
1453 if ((start == -1UL) ||
1454 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1455 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1456 printk(KERN_ERR "%s out of bound pci memory access. "
1457 "offset is 0x%llx\n", netxen_nic_driver_name,
1458 (unsigned long long)off);
1459 return -1;
1460 }
1461
1462 addr = pci_base_offset(adapter, start);
1463 if (!addr) {
1464 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1465 mem_base = pci_resource_start(adapter->pdev, 0);
1466 mem_page = start & PAGE_MASK;
1467 /* Map two pages whenever user tries to access addresses in two
1468 * consecutive pages.
1469 */
1470 if (mem_page != ((start + size - 1) & PAGE_MASK))
1471 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
1472 else
1473 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
1474 if (mem_ptr == NULL)
1475 return -1;
1476 addr = mem_ptr;
1477 addr += start & (PAGE_SIZE - 1);
1478 write_lock_irqsave(&adapter->adapter_lock, flags);
1479 }
1480
1481 switch (size) {
1482 case 1:
1483 writeb(*(uint8_t *)data, addr);
1484 break;
1485 case 2:
1486 writew(*(uint16_t *)data, addr);
1487 break;
1488 case 4:
1489 writel(*(uint32_t *)data, addr);
1490 break;
1491 case 8:
1492 writeq(*(uint64_t *)data, addr);
1493 break;
1494 default:
1495 ret = -1;
1496 break;
1497 }
1498 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1499 if (mem_ptr)
1500 iounmap(mem_ptr);
1501 return ret;
1502 }
1503
1504 #define MAX_CTL_CHECK 1000
1505
1506 int
1507 netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1508 u64 off, void *data, int size)
1509 {
1510 unsigned long flags;
1511 int i, j, ret = 0, loop, sz[2], off0;
1512 uint32_t temp;
1513 uint64_t off8, tmpw, word[2] = {0, 0};
1514 void __iomem *mem_crb;
1515
1516 /*
1517 * If not MN, go check for MS or invalid.
1518 */
1519 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1520 return netxen_nic_pci_mem_write_direct(adapter,
1521 off, data, size);
1522
1523 off8 = off & 0xfffffff8;
1524 off0 = off & 0x7;
1525 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1526 sz[1] = size - sz[0];
1527 loop = ((off0 + size - 1) >> 3) + 1;
1528 mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1529
1530 if ((size != 8) || (off0 != 0)) {
1531 for (i = 0; i < loop; i++) {
1532 if (adapter->pci_mem_read(adapter,
1533 off8 + (i << 3), &word[i], 8))
1534 return -1;
1535 }
1536 }
1537
1538 switch (size) {
1539 case 1:
1540 tmpw = *((uint8_t *)data);
1541 break;
1542 case 2:
1543 tmpw = *((uint16_t *)data);
1544 break;
1545 case 4:
1546 tmpw = *((uint32_t *)data);
1547 break;
1548 case 8:
1549 default:
1550 tmpw = *((uint64_t *)data);
1551 break;
1552 }
1553 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1554 word[0] |= tmpw << (off0 * 8);
1555
1556 if (loop == 2) {
1557 word[1] &= ~(~0ULL << (sz[1] * 8));
1558 word[1] |= tmpw >> (sz[0] * 8);
1559 }
1560
1561 write_lock_irqsave(&adapter->adapter_lock, flags);
1562 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1563
1564 for (i = 0; i < loop; i++) {
1565 writel((uint32_t)(off8 + (i << 3)),
1566 (mem_crb+MIU_TEST_AGT_ADDR_LO));
1567 writel(0,
1568 (mem_crb+MIU_TEST_AGT_ADDR_HI));
1569 writel(word[i] & 0xffffffff,
1570 (mem_crb+MIU_TEST_AGT_WRDATA_LO));
1571 writel((word[i] >> 32) & 0xffffffff,
1572 (mem_crb+MIU_TEST_AGT_WRDATA_HI));
1573 writel(MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1574 (mem_crb+MIU_TEST_AGT_CTRL));
1575 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1576 (mem_crb+MIU_TEST_AGT_CTRL));
1577
1578 for (j = 0; j < MAX_CTL_CHECK; j++) {
1579 temp = readl(
1580 (mem_crb+MIU_TEST_AGT_CTRL));
1581 if ((temp & MIU_TA_CTL_BUSY) == 0)
1582 break;
1583 }
1584
1585 if (j >= MAX_CTL_CHECK) {
1586 if (printk_ratelimit())
1587 dev_err(&adapter->pdev->dev,
1588 "failed to write through agent\n");
1589 ret = -1;
1590 break;
1591 }
1592 }
1593
1594 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1595 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1596 return ret;
1597 }
1598
1599 int
1600 netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1601 u64 off, void *data, int size)
1602 {
1603 unsigned long flags;
1604 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1605 uint32_t temp;
1606 uint64_t off8, val, word[2] = {0, 0};
1607 void __iomem *mem_crb;
1608
1609
1610 /*
1611 * If not MN, go check for MS or invalid.
1612 */
1613 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1614 return netxen_nic_pci_mem_read_direct(adapter, off, data, size);
1615
1616 off8 = off & 0xfffffff8;
1617 off0[0] = off & 0x7;
1618 off0[1] = 0;
1619 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1620 sz[1] = size - sz[0];
1621 loop = ((off0[0] + size - 1) >> 3) + 1;
1622 mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1623
1624 write_lock_irqsave(&adapter->adapter_lock, flags);
1625 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1626
1627 for (i = 0; i < loop; i++) {
1628 writel((uint32_t)(off8 + (i << 3)),
1629 (mem_crb+MIU_TEST_AGT_ADDR_LO));
1630 writel(0,
1631 (mem_crb+MIU_TEST_AGT_ADDR_HI));
1632 writel(MIU_TA_CTL_ENABLE,
1633 (mem_crb+MIU_TEST_AGT_CTRL));
1634 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE,
1635 (mem_crb+MIU_TEST_AGT_CTRL));
1636
1637 for (j = 0; j < MAX_CTL_CHECK; j++) {
1638 temp = readl(
1639 (mem_crb+MIU_TEST_AGT_CTRL));
1640 if ((temp & MIU_TA_CTL_BUSY) == 0)
1641 break;
1642 }
1643
1644 if (j >= MAX_CTL_CHECK) {
1645 if (printk_ratelimit())
1646 dev_err(&adapter->pdev->dev,
1647 "failed to read through agent\n");
1648 break;
1649 }
1650
1651 start = off0[i] >> 2;
1652 end = (off0[i] + sz[i] - 1) >> 2;
1653 for (k = start; k <= end; k++) {
1654 word[i] |= ((uint64_t) readl(
1655 (mem_crb +
1656 MIU_TEST_AGT_RDDATA(k))) << (32*k));
1657 }
1658 }
1659
1660 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1661 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1662
1663 if (j >= MAX_CTL_CHECK)
1664 return -1;
1665
1666 if (sz[0] == 8) {
1667 val = word[0];
1668 } else {
1669 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1670 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1671 }
1672
1673 switch (size) {
1674 case 1:
1675 *(uint8_t *)data = val;
1676 break;
1677 case 2:
1678 *(uint16_t *)data = val;
1679 break;
1680 case 4:
1681 *(uint32_t *)data = val;
1682 break;
1683 case 8:
1684 *(uint64_t *)data = val;
1685 break;
1686 }
1687 return 0;
1688 }
1689
1690 int
1691 netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1692 u64 off, void *data, int size)
1693 {
1694 int i, j, ret = 0, loop, sz[2], off0;
1695 uint32_t temp;
1696 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1697
1698 /*
1699 * If not MN, go check for MS or invalid.
1700 */
1701 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1702 mem_crb = NETXEN_CRB_QDR_NET;
1703 else {
1704 mem_crb = NETXEN_CRB_DDR_NET;
1705 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1706 return netxen_nic_pci_mem_write_direct(adapter,
1707 off, data, size);
1708 }
1709
1710 off8 = off & 0xfffffff8;
1711 off0 = off & 0x7;
1712 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1713 sz[1] = size - sz[0];
1714 loop = ((off0 + size - 1) >> 3) + 1;
1715
1716 if ((size != 8) || (off0 != 0)) {
1717 for (i = 0; i < loop; i++) {
1718 if (adapter->pci_mem_read(adapter, off8 + (i << 3),
1719 &word[i], 8))
1720 return -1;
1721 }
1722 }
1723
1724 switch (size) {
1725 case 1:
1726 tmpw = *((uint8_t *)data);
1727 break;
1728 case 2:
1729 tmpw = *((uint16_t *)data);
1730 break;
1731 case 4:
1732 tmpw = *((uint32_t *)data);
1733 break;
1734 case 8:
1735 default:
1736 tmpw = *((uint64_t *)data);
1737 break;
1738 }
1739
1740 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1741 word[0] |= tmpw << (off0 * 8);
1742
1743 if (loop == 2) {
1744 word[1] &= ~(~0ULL << (sz[1] * 8));
1745 word[1] |= tmpw >> (sz[0] * 8);
1746 }
1747
1748 /*
1749 * don't lock here - write_wx gets the lock if each time
1750 * write_lock_irqsave(&adapter->adapter_lock, flags);
1751 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1752 */
1753
1754 for (i = 0; i < loop; i++) {
1755 temp = off8 + (i << 3);
1756 NXWR32(adapter, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1757 temp = 0;
1758 NXWR32(adapter, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1759 temp = word[i] & 0xffffffff;
1760 NXWR32(adapter, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1761 temp = (word[i] >> 32) & 0xffffffff;
1762 NXWR32(adapter, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1763 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1764 NXWR32(adapter, mem_crb+MIU_TEST_AGT_CTRL, temp);
1765 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1766 NXWR32(adapter, mem_crb+MIU_TEST_AGT_CTRL, temp);
1767
1768 for (j = 0; j < MAX_CTL_CHECK; j++) {
1769 temp = NXRD32(adapter, mem_crb + MIU_TEST_AGT_CTRL);
1770 if ((temp & MIU_TA_CTL_BUSY) == 0)
1771 break;
1772 }
1773
1774 if (j >= MAX_CTL_CHECK) {
1775 if (printk_ratelimit())
1776 dev_err(&adapter->pdev->dev,
1777 "failed to write through agent\n");
1778 ret = -1;
1779 break;
1780 }
1781 }
1782
1783 /*
1784 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1785 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1786 */
1787 return ret;
1788 }
1789
1790 int
1791 netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1792 u64 off, void *data, int size)
1793 {
1794 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1795 uint32_t temp;
1796 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1797
1798 /*
1799 * If not MN, go check for MS or invalid.
1800 */
1801
1802 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1803 mem_crb = NETXEN_CRB_QDR_NET;
1804 else {
1805 mem_crb = NETXEN_CRB_DDR_NET;
1806 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1807 return netxen_nic_pci_mem_read_direct(adapter,
1808 off, data, size);
1809 }
1810
1811 off8 = off & 0xfffffff8;
1812 off0[0] = off & 0x7;
1813 off0[1] = 0;
1814 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1815 sz[1] = size - sz[0];
1816 loop = ((off0[0] + size - 1) >> 3) + 1;
1817
1818 /*
1819 * don't lock here - write_wx gets the lock if each time
1820 * write_lock_irqsave(&adapter->adapter_lock, flags);
1821 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1822 */
1823
1824 for (i = 0; i < loop; i++) {
1825 temp = off8 + (i << 3);
1826 NXWR32(adapter, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1827 temp = 0;
1828 NXWR32(adapter, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1829 temp = MIU_TA_CTL_ENABLE;
1830 NXWR32(adapter, mem_crb + MIU_TEST_AGT_CTRL, temp);
1831 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1832 NXWR32(adapter, mem_crb + MIU_TEST_AGT_CTRL, temp);
1833
1834 for (j = 0; j < MAX_CTL_CHECK; j++) {
1835 temp = NXRD32(adapter, mem_crb + MIU_TEST_AGT_CTRL);
1836 if ((temp & MIU_TA_CTL_BUSY) == 0)
1837 break;
1838 }
1839
1840 if (j >= MAX_CTL_CHECK) {
1841 if (printk_ratelimit())
1842 dev_err(&adapter->pdev->dev,
1843 "failed to read through agent\n");
1844 break;
1845 }
1846
1847 start = off0[i] >> 2;
1848 end = (off0[i] + sz[i] - 1) >> 2;
1849 for (k = start; k <= end; k++) {
1850 temp = NXRD32(adapter,
1851 mem_crb + MIU_TEST_AGT_RDDATA(k));
1852 word[i] |= ((uint64_t)temp << (32 * k));
1853 }
1854 }
1855
1856 /*
1857 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1858 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1859 */
1860
1861 if (j >= MAX_CTL_CHECK)
1862 return -1;
1863
1864 if (sz[0] == 8) {
1865 val = word[0];
1866 } else {
1867 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1868 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1869 }
1870
1871 switch (size) {
1872 case 1:
1873 *(uint8_t *)data = val;
1874 break;
1875 case 2:
1876 *(uint16_t *)data = val;
1877 break;
1878 case 4:
1879 *(uint32_t *)data = val;
1880 break;
1881 case 8:
1882 *(uint64_t *)data = val;
1883 break;
1884 }
1885 return 0;
1886 }
1887
1888 /*
1889 * Note : only 32-bit writes!
1890 */
1891 int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
1892 u64 off, u32 data)
1893 {
1894 NXWR32(adapter, off, data);
1895
1896 return 0;
1897 }
1898
1899 u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off)
1900 {
1901 return NXRD32(adapter, off);
1902 }
1903
1904 int netxen_nic_get_board_info(struct netxen_adapter *adapter)
1905 {
1906 int offset, board_type, magic, header_version;
1907 struct pci_dev *pdev = adapter->pdev;
1908
1909 offset = NX_FW_MAGIC_OFFSET;
1910 if (netxen_rom_fast_read(adapter, offset, &magic))
1911 return -EIO;
1912
1913 offset = NX_HDR_VERSION_OFFSET;
1914 if (netxen_rom_fast_read(adapter, offset, &header_version))
1915 return -EIO;
1916
1917 if (magic != NETXEN_BDINFO_MAGIC ||
1918 header_version != NETXEN_BDINFO_VERSION) {
1919 dev_err(&pdev->dev,
1920 "invalid board config, magic=%08x, version=%08x\n",
1921 magic, header_version);
1922 return -EIO;
1923 }
1924
1925 offset = NX_BRDTYPE_OFFSET;
1926 if (netxen_rom_fast_read(adapter, offset, &board_type))
1927 return -EIO;
1928
1929 adapter->ahw.board_type = board_type;
1930
1931 if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) {
1932 u32 gpio = NXRD32(adapter, NETXEN_ROMUSB_GLB_PAD_GPIO_I);
1933 if ((gpio & 0x8000) == 0)
1934 board_type = NETXEN_BRDTYPE_P3_10G_TP;
1935 }
1936
1937 switch (board_type) {
1938 case NETXEN_BRDTYPE_P2_SB35_4G:
1939 adapter->ahw.port_type = NETXEN_NIC_GBE;
1940 break;
1941 case NETXEN_BRDTYPE_P2_SB31_10G:
1942 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
1943 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
1944 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
1945 case NETXEN_BRDTYPE_P3_HMEZ:
1946 case NETXEN_BRDTYPE_P3_XG_LOM:
1947 case NETXEN_BRDTYPE_P3_10G_CX4:
1948 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
1949 case NETXEN_BRDTYPE_P3_IMEZ:
1950 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
1951 case NETXEN_BRDTYPE_P3_10G_SFP_CT:
1952 case NETXEN_BRDTYPE_P3_10G_SFP_QT:
1953 case NETXEN_BRDTYPE_P3_10G_XFP:
1954 case NETXEN_BRDTYPE_P3_10000_BASE_T:
1955 adapter->ahw.port_type = NETXEN_NIC_XGBE;
1956 break;
1957 case NETXEN_BRDTYPE_P1_BD:
1958 case NETXEN_BRDTYPE_P1_SB:
1959 case NETXEN_BRDTYPE_P1_SMAX:
1960 case NETXEN_BRDTYPE_P1_SOCK:
1961 case NETXEN_BRDTYPE_P3_REF_QG:
1962 case NETXEN_BRDTYPE_P3_4_GB:
1963 case NETXEN_BRDTYPE_P3_4_GB_MM:
1964 adapter->ahw.port_type = NETXEN_NIC_GBE;
1965 break;
1966 case NETXEN_BRDTYPE_P3_10G_TP:
1967 adapter->ahw.port_type = (adapter->portnum < 2) ?
1968 NETXEN_NIC_XGBE : NETXEN_NIC_GBE;
1969 break;
1970 default:
1971 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1972 adapter->ahw.port_type = NETXEN_NIC_XGBE;
1973 break;
1974 }
1975
1976 return 0;
1977 }
1978
1979 /* NIU access sections */
1980
1981 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
1982 {
1983 new_mtu += MTU_FUDGE_FACTOR;
1984 NXWR32(adapter, NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
1985 new_mtu);
1986 return 0;
1987 }
1988
1989 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
1990 {
1991 new_mtu += MTU_FUDGE_FACTOR;
1992 if (adapter->physical_port == 0)
1993 NXWR32(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu);
1994 else
1995 NXWR32(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, new_mtu);
1996 return 0;
1997 }
1998
1999 void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
2000 {
2001 __u32 status;
2002 __u32 autoneg;
2003 __u32 port_mode;
2004
2005 if (!netif_carrier_ok(adapter->netdev)) {
2006 adapter->link_speed = 0;
2007 adapter->link_duplex = -1;
2008 adapter->link_autoneg = AUTONEG_ENABLE;
2009 return;
2010 }
2011
2012 if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
2013 port_mode = NXRD32(adapter, NETXEN_PORT_MODE_ADDR);
2014 if (port_mode == NETXEN_PORT_MODE_802_3_AP) {
2015 adapter->link_speed = SPEED_1000;
2016 adapter->link_duplex = DUPLEX_FULL;
2017 adapter->link_autoneg = AUTONEG_DISABLE;
2018 return;
2019 }
2020
2021 if (adapter->phy_read
2022 && adapter->phy_read(adapter,
2023 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
2024 &status) == 0) {
2025 if (netxen_get_phy_link(status)) {
2026 switch (netxen_get_phy_speed(status)) {
2027 case 0:
2028 adapter->link_speed = SPEED_10;
2029 break;
2030 case 1:
2031 adapter->link_speed = SPEED_100;
2032 break;
2033 case 2:
2034 adapter->link_speed = SPEED_1000;
2035 break;
2036 default:
2037 adapter->link_speed = 0;
2038 break;
2039 }
2040 switch (netxen_get_phy_duplex(status)) {
2041 case 0:
2042 adapter->link_duplex = DUPLEX_HALF;
2043 break;
2044 case 1:
2045 adapter->link_duplex = DUPLEX_FULL;
2046 break;
2047 default:
2048 adapter->link_duplex = -1;
2049 break;
2050 }
2051 if (adapter->phy_read
2052 && adapter->phy_read(adapter,
2053 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
2054 &autoneg) != 0)
2055 adapter->link_autoneg = autoneg;
2056 } else
2057 goto link_down;
2058 } else {
2059 link_down:
2060 adapter->link_speed = 0;
2061 adapter->link_duplex = -1;
2062 }
2063 }
2064 }
2065
2066 void netxen_nic_get_firmware_info(struct netxen_adapter *adapter)
2067 {
2068 u32 fw_major, fw_minor, fw_build;
2069 char brd_name[NETXEN_MAX_SHORT_NAME];
2070 char serial_num[32];
2071 int i, offset, val;
2072 int *ptr32;
2073 struct pci_dev *pdev = adapter->pdev;
2074
2075 adapter->driver_mismatch = 0;
2076
2077 ptr32 = (int *)&serial_num;
2078 offset = NX_FW_SERIAL_NUM_OFFSET;
2079 for (i = 0; i < 8; i++) {
2080 if (netxen_rom_fast_read(adapter, offset, &val) == -1) {
2081 dev_err(&pdev->dev, "error reading board info\n");
2082 adapter->driver_mismatch = 1;
2083 return;
2084 }
2085 ptr32[i] = cpu_to_le32(val);
2086 offset += sizeof(u32);
2087 }
2088
2089 fw_major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
2090 fw_minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
2091 fw_build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
2092
2093 adapter->fw_version = NETXEN_VERSION_CODE(fw_major, fw_minor, fw_build);
2094
2095 if (adapter->portnum == 0) {
2096 get_brd_name_by_type(adapter->ahw.board_type, brd_name);
2097
2098 printk(KERN_INFO "NetXen %s Board S/N %s Chip rev 0x%x\n",
2099 brd_name, serial_num, adapter->ahw.revision_id);
2100 }
2101
2102 if (adapter->fw_version < NETXEN_VERSION_CODE(3, 4, 216)) {
2103 adapter->driver_mismatch = 1;
2104 dev_warn(&pdev->dev, "firmware version %d.%d.%d unsupported\n",
2105 fw_major, fw_minor, fw_build);
2106 return;
2107 }
2108
2109 dev_info(&pdev->dev, "firmware version %d.%d.%d\n",
2110 fw_major, fw_minor, fw_build);
2111
2112 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
2113 i = NXRD32(adapter, NETXEN_SRE_MISC);
2114 adapter->ahw.cut_through = (i & 0x8000) ? 1 : 0;
2115 dev_info(&pdev->dev, "firmware running in %s mode\n",
2116 adapter->ahw.cut_through ? "cut-through" : "legacy");
2117 }
2118
2119 if (adapter->fw_version >= NETXEN_VERSION_CODE(4, 0, 222))
2120 adapter->capabilities = NXRD32(adapter, CRB_FW_CAPABILITIES_1);
2121
2122 adapter->flags &= ~NETXEN_NIC_LRO_ENABLED;
2123 }
2124
2125 int
2126 netxen_nic_wol_supported(struct netxen_adapter *adapter)
2127 {
2128 u32 wol_cfg;
2129
2130 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
2131 return 0;
2132
2133 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV);
2134 if (wol_cfg & (1UL << adapter->portnum)) {
2135 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG);
2136 if (wol_cfg & (1 << adapter->portnum))
2137 return 1;
2138 }
2139
2140 return 0;
2141 }
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