1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
3 * Copyright 1996-1999 Thomas Bogendoerfer
5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
7 * Copyright 1993 United States Government as represented by the
8 * Director, National Security Agency.
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
13 * This driver is for PCnet32 and PCnetPCI based ethercards
15 /**************************************************************************
17 * Fixed a few bugs, related to running the controller in 32bit mode.
19 * Carsten Langgaard, carstenl@mips.com
20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
22 *************************************************************************/
24 #include <linux/config.h>
26 #define DRV_NAME "pcnet32"
27 #ifdef CONFIG_PCNET32_NAPI
28 #define DRV_VERSION "1.33-NAPI"
30 #define DRV_VERSION "1.33"
32 #define DRV_RELDATE "27.Jun.2006"
33 #define PFX DRV_NAME ": "
35 static const char *const version
=
36 DRV_NAME
".c:v" DRV_VERSION
" " DRV_RELDATE
" tsbogend@alpha.franken.de\n";
38 #include <linux/module.h>
39 #include <linux/kernel.h>
40 #include <linux/string.h>
41 #include <linux/errno.h>
42 #include <linux/ioport.h>
43 #include <linux/slab.h>
44 #include <linux/interrupt.h>
45 #include <linux/pci.h>
46 #include <linux/delay.h>
47 #include <linux/init.h>
48 #include <linux/ethtool.h>
49 #include <linux/mii.h>
50 #include <linux/crc32.h>
51 #include <linux/netdevice.h>
52 #include <linux/etherdevice.h>
53 #include <linux/skbuff.h>
54 #include <linux/spinlock.h>
55 #include <linux/moduleparam.h>
56 #include <linux/bitops.h>
60 #include <asm/uaccess.h>
64 * PCI device identifiers for "new style" Linux PCI Device Drivers
66 static struct pci_device_id pcnet32_pci_tbl
[] = {
67 { PCI_DEVICE(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_LANCE_HOME
), },
68 { PCI_DEVICE(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_LANCE
), },
71 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
72 * the incorrect vendor id.
74 { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT
, PCI_DEVICE_ID_AMD_LANCE
),
75 .class = (PCI_CLASS_NETWORK_ETHERNET
<< 8), .class_mask
= 0xffff00, },
77 { } /* terminate list */
80 MODULE_DEVICE_TABLE(pci
, pcnet32_pci_tbl
);
82 static int cards_found
;
87 static unsigned int pcnet32_portlist
[] __initdata
=
88 { 0x300, 0x320, 0x340, 0x360, 0 };
90 static int pcnet32_debug
= 0;
91 static int tx_start
= 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
92 static int pcnet32vlb
; /* check for VLB cards ? */
94 static struct net_device
*pcnet32_dev
;
96 static int max_interrupt_work
= 2;
97 static int rx_copybreak
= 200;
99 #define PCNET32_PORT_AUI 0x00
100 #define PCNET32_PORT_10BT 0x01
101 #define PCNET32_PORT_GPSI 0x02
102 #define PCNET32_PORT_MII 0x03
104 #define PCNET32_PORT_PORTSEL 0x03
105 #define PCNET32_PORT_ASEL 0x04
106 #define PCNET32_PORT_100 0x40
107 #define PCNET32_PORT_FD 0x80
109 #define PCNET32_DMA_MASK 0xffffffff
111 #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
112 #define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4))
115 * table to translate option values from tulip
116 * to internal options
118 static const unsigned char options_mapping
[] = {
119 PCNET32_PORT_ASEL
, /* 0 Auto-select */
120 PCNET32_PORT_AUI
, /* 1 BNC/AUI */
121 PCNET32_PORT_AUI
, /* 2 AUI/BNC */
122 PCNET32_PORT_ASEL
, /* 3 not supported */
123 PCNET32_PORT_10BT
| PCNET32_PORT_FD
, /* 4 10baseT-FD */
124 PCNET32_PORT_ASEL
, /* 5 not supported */
125 PCNET32_PORT_ASEL
, /* 6 not supported */
126 PCNET32_PORT_ASEL
, /* 7 not supported */
127 PCNET32_PORT_ASEL
, /* 8 not supported */
128 PCNET32_PORT_MII
, /* 9 MII 10baseT */
129 PCNET32_PORT_MII
| PCNET32_PORT_FD
, /* 10 MII 10baseT-FD */
130 PCNET32_PORT_MII
, /* 11 MII (autosel) */
131 PCNET32_PORT_10BT
, /* 12 10BaseT */
132 PCNET32_PORT_MII
| PCNET32_PORT_100
, /* 13 MII 100BaseTx */
133 /* 14 MII 100BaseTx-FD */
134 PCNET32_PORT_MII
| PCNET32_PORT_100
| PCNET32_PORT_FD
,
135 PCNET32_PORT_ASEL
/* 15 not supported */
138 static const char pcnet32_gstrings_test
[][ETH_GSTRING_LEN
] = {
139 "Loopback test (offline)"
142 #define PCNET32_TEST_LEN (sizeof(pcnet32_gstrings_test) / ETH_GSTRING_LEN)
144 #define PCNET32_NUM_REGS 136
146 #define MAX_UNITS 8 /* More are supported, limit only on options */
147 static int options
[MAX_UNITS
];
148 static int full_duplex
[MAX_UNITS
];
149 static int homepna
[MAX_UNITS
];
152 * Theory of Operation
154 * This driver uses the same software structure as the normal lance
155 * driver. So look for a verbose description in lance.c. The differences
156 * to the normal lance driver is the use of the 32bit mode of PCnet32
157 * and PCnetPCI chips. Because these chips are 32bit chips, there is no
158 * 16MB limitation and we don't need bounce buffers.
162 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
163 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
164 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
166 #ifndef PCNET32_LOG_TX_BUFFERS
167 #define PCNET32_LOG_TX_BUFFERS 4
168 #define PCNET32_LOG_RX_BUFFERS 5
169 #define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */
170 #define PCNET32_LOG_MAX_RX_BUFFERS 9
173 #define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
174 #define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
176 #define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
177 #define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
179 #define PKT_BUF_SZ 1544
181 /* Offsets from base I/O address. */
182 #define PCNET32_WIO_RDP 0x10
183 #define PCNET32_WIO_RAP 0x12
184 #define PCNET32_WIO_RESET 0x14
185 #define PCNET32_WIO_BDP 0x16
187 #define PCNET32_DWIO_RDP 0x10
188 #define PCNET32_DWIO_RAP 0x14
189 #define PCNET32_DWIO_RESET 0x18
190 #define PCNET32_DWIO_BDP 0x1C
192 #define PCNET32_TOTAL_SIZE 0x20
195 #define CSR0_INIT 0x1
196 #define CSR0_START 0x2
197 #define CSR0_STOP 0x4
198 #define CSR0_TXPOLL 0x8
199 #define CSR0_INTEN 0x40
200 #define CSR0_IDON 0x0100
201 #define CSR0_NORMAL (CSR0_START | CSR0_INTEN)
202 #define PCNET32_INIT_LOW 1
203 #define PCNET32_INIT_HIGH 2
207 #define CSR5_SUSPEND 0x0001
209 #define PCNET32_MC_FILTER 8
211 #define PCNET32_79C970A 0x2621
213 /* The PCNET32 Rx and Tx ring descriptors. */
214 struct pcnet32_rx_head
{
216 s16 buf_length
; /* two`s complement of length */
222 struct pcnet32_tx_head
{
224 s16 length
; /* two`s complement of length */
230 /* The PCNET32 32-Bit initialization block, described in databook. */
231 struct pcnet32_init_block
{
237 /* Receive and transmit ring base, along with extra bits. */
242 /* PCnet32 access functions */
243 struct pcnet32_access
{
244 u16 (*read_csr
) (unsigned long, int);
245 void (*write_csr
) (unsigned long, int, u16
);
246 u16 (*read_bcr
) (unsigned long, int);
247 void (*write_bcr
) (unsigned long, int, u16
);
248 u16 (*read_rap
) (unsigned long);
249 void (*write_rap
) (unsigned long, u16
);
250 void (*reset
) (unsigned long);
254 * The first field of pcnet32_private is read by the ethernet device
255 * so the structure should be allocated using pci_alloc_consistent().
257 struct pcnet32_private
{
258 struct pcnet32_init_block init_block
;
259 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
260 struct pcnet32_rx_head
*rx_ring
;
261 struct pcnet32_tx_head
*tx_ring
;
262 dma_addr_t dma_addr
;/* DMA address of beginning of this
263 object, returned by pci_alloc_consistent */
264 struct pci_dev
*pci_dev
;
266 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
267 struct sk_buff
**tx_skbuff
;
268 struct sk_buff
**rx_skbuff
;
269 dma_addr_t
*tx_dma_addr
;
270 dma_addr_t
*rx_dma_addr
;
271 struct pcnet32_access a
;
272 spinlock_t lock
; /* Guard lock */
273 unsigned int cur_rx
, cur_tx
; /* The next free ring entry */
274 unsigned int rx_ring_size
; /* current rx ring size */
275 unsigned int tx_ring_size
; /* current tx ring size */
276 unsigned int rx_mod_mask
; /* rx ring modular mask */
277 unsigned int tx_mod_mask
; /* tx ring modular mask */
278 unsigned short rx_len_bits
;
279 unsigned short tx_len_bits
;
280 dma_addr_t rx_ring_dma_addr
;
281 dma_addr_t tx_ring_dma_addr
;
282 unsigned int dirty_rx
, /* ring entries to be freed. */
285 struct net_device_stats stats
;
287 char phycount
; /* number of phys found */
289 unsigned int shared_irq
:1, /* shared irq possible */
290 dxsuflo
:1, /* disable transmit stop on uflo */
291 mii
:1; /* mii port available */
292 struct net_device
*next
;
293 struct mii_if_info mii_if
;
294 struct timer_list watchdog_timer
;
295 struct timer_list blink_timer
;
296 u32 msg_enable
; /* debug message level */
298 /* each bit indicates an available PHY */
300 unsigned short chip_version
; /* which variant this is */
303 static int pcnet32_probe_pci(struct pci_dev
*, const struct pci_device_id
*);
304 static int pcnet32_probe1(unsigned long, int, struct pci_dev
*);
305 static int pcnet32_open(struct net_device
*);
306 static int pcnet32_init_ring(struct net_device
*);
307 static int pcnet32_start_xmit(struct sk_buff
*, struct net_device
*);
308 static void pcnet32_tx_timeout(struct net_device
*dev
);
309 static irqreturn_t
pcnet32_interrupt(int, void *, struct pt_regs
*);
310 static int pcnet32_close(struct net_device
*);
311 static struct net_device_stats
*pcnet32_get_stats(struct net_device
*);
312 static void pcnet32_load_multicast(struct net_device
*dev
);
313 static void pcnet32_set_multicast_list(struct net_device
*);
314 static int pcnet32_ioctl(struct net_device
*, struct ifreq
*, int);
315 static void pcnet32_watchdog(struct net_device
*);
316 static int mdio_read(struct net_device
*dev
, int phy_id
, int reg_num
);
317 static void mdio_write(struct net_device
*dev
, int phy_id
, int reg_num
,
319 static void pcnet32_restart(struct net_device
*dev
, unsigned int csr0_bits
);
320 static void pcnet32_ethtool_test(struct net_device
*dev
,
321 struct ethtool_test
*eth_test
, u64
* data
);
322 static int pcnet32_loopback_test(struct net_device
*dev
, uint64_t * data1
);
323 static int pcnet32_phys_id(struct net_device
*dev
, u32 data
);
324 static void pcnet32_led_blink_callback(struct net_device
*dev
);
325 static int pcnet32_get_regs_len(struct net_device
*dev
);
326 static void pcnet32_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
328 static void pcnet32_purge_tx_ring(struct net_device
*dev
);
329 static int pcnet32_alloc_ring(struct net_device
*dev
, char *name
);
330 static void pcnet32_free_ring(struct net_device
*dev
);
331 static void pcnet32_check_media(struct net_device
*dev
, int verbose
);
333 static u16
pcnet32_wio_read_csr(unsigned long addr
, int index
)
335 outw(index
, addr
+ PCNET32_WIO_RAP
);
336 return inw(addr
+ PCNET32_WIO_RDP
);
339 static void pcnet32_wio_write_csr(unsigned long addr
, int index
, u16 val
)
341 outw(index
, addr
+ PCNET32_WIO_RAP
);
342 outw(val
, addr
+ PCNET32_WIO_RDP
);
345 static u16
pcnet32_wio_read_bcr(unsigned long addr
, int index
)
347 outw(index
, addr
+ PCNET32_WIO_RAP
);
348 return inw(addr
+ PCNET32_WIO_BDP
);
351 static void pcnet32_wio_write_bcr(unsigned long addr
, int index
, u16 val
)
353 outw(index
, addr
+ PCNET32_WIO_RAP
);
354 outw(val
, addr
+ PCNET32_WIO_BDP
);
357 static u16
pcnet32_wio_read_rap(unsigned long addr
)
359 return inw(addr
+ PCNET32_WIO_RAP
);
362 static void pcnet32_wio_write_rap(unsigned long addr
, u16 val
)
364 outw(val
, addr
+ PCNET32_WIO_RAP
);
367 static void pcnet32_wio_reset(unsigned long addr
)
369 inw(addr
+ PCNET32_WIO_RESET
);
372 static int pcnet32_wio_check(unsigned long addr
)
374 outw(88, addr
+ PCNET32_WIO_RAP
);
375 return (inw(addr
+ PCNET32_WIO_RAP
) == 88);
378 static struct pcnet32_access pcnet32_wio
= {
379 .read_csr
= pcnet32_wio_read_csr
,
380 .write_csr
= pcnet32_wio_write_csr
,
381 .read_bcr
= pcnet32_wio_read_bcr
,
382 .write_bcr
= pcnet32_wio_write_bcr
,
383 .read_rap
= pcnet32_wio_read_rap
,
384 .write_rap
= pcnet32_wio_write_rap
,
385 .reset
= pcnet32_wio_reset
388 static u16
pcnet32_dwio_read_csr(unsigned long addr
, int index
)
390 outl(index
, addr
+ PCNET32_DWIO_RAP
);
391 return (inl(addr
+ PCNET32_DWIO_RDP
) & 0xffff);
394 static void pcnet32_dwio_write_csr(unsigned long addr
, int index
, u16 val
)
396 outl(index
, addr
+ PCNET32_DWIO_RAP
);
397 outl(val
, addr
+ PCNET32_DWIO_RDP
);
400 static u16
pcnet32_dwio_read_bcr(unsigned long addr
, int index
)
402 outl(index
, addr
+ PCNET32_DWIO_RAP
);
403 return (inl(addr
+ PCNET32_DWIO_BDP
) & 0xffff);
406 static void pcnet32_dwio_write_bcr(unsigned long addr
, int index
, u16 val
)
408 outl(index
, addr
+ PCNET32_DWIO_RAP
);
409 outl(val
, addr
+ PCNET32_DWIO_BDP
);
412 static u16
pcnet32_dwio_read_rap(unsigned long addr
)
414 return (inl(addr
+ PCNET32_DWIO_RAP
) & 0xffff);
417 static void pcnet32_dwio_write_rap(unsigned long addr
, u16 val
)
419 outl(val
, addr
+ PCNET32_DWIO_RAP
);
422 static void pcnet32_dwio_reset(unsigned long addr
)
424 inl(addr
+ PCNET32_DWIO_RESET
);
427 static int pcnet32_dwio_check(unsigned long addr
)
429 outl(88, addr
+ PCNET32_DWIO_RAP
);
430 return ((inl(addr
+ PCNET32_DWIO_RAP
) & 0xffff) == 88);
433 static struct pcnet32_access pcnet32_dwio
= {
434 .read_csr
= pcnet32_dwio_read_csr
,
435 .write_csr
= pcnet32_dwio_write_csr
,
436 .read_bcr
= pcnet32_dwio_read_bcr
,
437 .write_bcr
= pcnet32_dwio_write_bcr
,
438 .read_rap
= pcnet32_dwio_read_rap
,
439 .write_rap
= pcnet32_dwio_write_rap
,
440 .reset
= pcnet32_dwio_reset
443 static void pcnet32_netif_stop(struct net_device
*dev
)
445 dev
->trans_start
= jiffies
;
446 netif_poll_disable(dev
);
447 netif_tx_disable(dev
);
450 static void pcnet32_netif_start(struct net_device
*dev
)
452 netif_wake_queue(dev
);
453 netif_poll_enable(dev
);
457 * Allocate space for the new sized tx ring.
459 * Save new resources.
460 * Any failure keeps old resources.
461 * Must be called with lp->lock held.
463 static void pcnet32_realloc_tx_ring(struct net_device
*dev
,
464 struct pcnet32_private
*lp
,
467 dma_addr_t new_ring_dma_addr
;
468 dma_addr_t
*new_dma_addr_list
;
469 struct pcnet32_tx_head
*new_tx_ring
;
470 struct sk_buff
**new_skb_list
;
472 pcnet32_purge_tx_ring(dev
);
474 new_tx_ring
= pci_alloc_consistent(lp
->pci_dev
,
475 sizeof(struct pcnet32_tx_head
) *
478 if (new_tx_ring
== NULL
) {
479 if (netif_msg_drv(lp
))
481 "%s: Consistent memory allocation failed.\n",
485 memset(new_tx_ring
, 0, sizeof(struct pcnet32_tx_head
) * (1 << size
));
487 new_dma_addr_list
= kcalloc((1 << size
), sizeof(dma_addr_t
),
489 if (!new_dma_addr_list
) {
490 if (netif_msg_drv(lp
))
492 "%s: Memory allocation failed.\n", dev
->name
);
493 goto free_new_tx_ring
;
496 new_skb_list
= kcalloc((1 << size
), sizeof(struct sk_buff
*),
499 if (netif_msg_drv(lp
))
501 "%s: Memory allocation failed.\n", dev
->name
);
505 kfree(lp
->tx_skbuff
);
506 kfree(lp
->tx_dma_addr
);
507 pci_free_consistent(lp
->pci_dev
,
508 sizeof(struct pcnet32_tx_head
) *
509 lp
->tx_ring_size
, lp
->tx_ring
,
510 lp
->tx_ring_dma_addr
);
512 lp
->tx_ring_size
= (1 << size
);
513 lp
->tx_mod_mask
= lp
->tx_ring_size
- 1;
514 lp
->tx_len_bits
= (size
<< 12);
515 lp
->tx_ring
= new_tx_ring
;
516 lp
->tx_ring_dma_addr
= new_ring_dma_addr
;
517 lp
->tx_dma_addr
= new_dma_addr_list
;
518 lp
->tx_skbuff
= new_skb_list
;
522 kfree(new_dma_addr_list
);
524 pci_free_consistent(lp
->pci_dev
,
525 sizeof(struct pcnet32_tx_head
) *
533 * Allocate space for the new sized rx ring.
534 * Re-use old receive buffers.
535 * alloc extra buffers
536 * free unneeded buffers
537 * free unneeded buffers
538 * Save new resources.
539 * Any failure keeps old resources.
540 * Must be called with lp->lock held.
542 static void pcnet32_realloc_rx_ring(struct net_device
*dev
,
543 struct pcnet32_private
*lp
,
546 dma_addr_t new_ring_dma_addr
;
547 dma_addr_t
*new_dma_addr_list
;
548 struct pcnet32_rx_head
*new_rx_ring
;
549 struct sk_buff
**new_skb_list
;
552 new_rx_ring
= pci_alloc_consistent(lp
->pci_dev
,
553 sizeof(struct pcnet32_rx_head
) *
556 if (new_rx_ring
== NULL
) {
557 if (netif_msg_drv(lp
))
559 "%s: Consistent memory allocation failed.\n",
563 memset(new_rx_ring
, 0, sizeof(struct pcnet32_rx_head
) * (1 << size
));
565 new_dma_addr_list
= kcalloc((1 << size
), sizeof(dma_addr_t
),
567 if (!new_dma_addr_list
) {
568 if (netif_msg_drv(lp
))
570 "%s: Memory allocation failed.\n", dev
->name
);
571 goto free_new_rx_ring
;
574 new_skb_list
= kcalloc((1 << size
), sizeof(struct sk_buff
*),
577 if (netif_msg_drv(lp
))
579 "%s: Memory allocation failed.\n", dev
->name
);
583 /* first copy the current receive buffers */
584 overlap
= min(size
, lp
->rx_ring_size
);
585 for (new = 0; new < overlap
; new++) {
586 new_rx_ring
[new] = lp
->rx_ring
[new];
587 new_dma_addr_list
[new] = lp
->rx_dma_addr
[new];
588 new_skb_list
[new] = lp
->rx_skbuff
[new];
590 /* now allocate any new buffers needed */
591 for (; new < size
; new++ ) {
592 struct sk_buff
*rx_skbuff
;
593 new_skb_list
[new] = dev_alloc_skb(PKT_BUF_SZ
);
594 if (!(rx_skbuff
= new_skb_list
[new])) {
595 /* keep the original lists and buffers */
596 if (netif_msg_drv(lp
))
598 "%s: pcnet32_realloc_rx_ring dev_alloc_skb failed.\n",
602 skb_reserve(rx_skbuff
, 2);
604 new_dma_addr_list
[new] =
605 pci_map_single(lp
->pci_dev
, rx_skbuff
->data
,
606 PKT_BUF_SZ
- 2, PCI_DMA_FROMDEVICE
);
607 new_rx_ring
[new].base
= (u32
) le32_to_cpu(new_dma_addr_list
[new]);
608 new_rx_ring
[new].buf_length
= le16_to_cpu(2 - PKT_BUF_SZ
);
609 new_rx_ring
[new].status
= le16_to_cpu(0x8000);
611 /* and free any unneeded buffers */
612 for (; new < lp
->rx_ring_size
; new++) {
613 if (lp
->rx_skbuff
[new]) {
614 pci_unmap_single(lp
->pci_dev
, lp
->rx_dma_addr
[new],
615 PKT_BUF_SZ
- 2, PCI_DMA_FROMDEVICE
);
616 dev_kfree_skb(lp
->rx_skbuff
[new]);
620 kfree(lp
->rx_skbuff
);
621 kfree(lp
->rx_dma_addr
);
622 pci_free_consistent(lp
->pci_dev
,
623 sizeof(struct pcnet32_rx_head
) *
624 lp
->rx_ring_size
, lp
->rx_ring
,
625 lp
->rx_ring_dma_addr
);
627 lp
->rx_ring_size
= (1 << size
);
628 lp
->rx_mod_mask
= lp
->rx_ring_size
- 1;
629 lp
->rx_len_bits
= (size
<< 4);
630 lp
->rx_ring
= new_rx_ring
;
631 lp
->rx_ring_dma_addr
= new_ring_dma_addr
;
632 lp
->rx_dma_addr
= new_dma_addr_list
;
633 lp
->rx_skbuff
= new_skb_list
;
637 for (; --new >= lp
->rx_ring_size
; ) {
638 if (new_skb_list
[new]) {
639 pci_unmap_single(lp
->pci_dev
, new_dma_addr_list
[new],
640 PKT_BUF_SZ
- 2, PCI_DMA_FROMDEVICE
);
641 dev_kfree_skb(new_skb_list
[new]);
646 kfree(new_dma_addr_list
);
648 pci_free_consistent(lp
->pci_dev
,
649 sizeof(struct pcnet32_rx_head
) *
656 static void pcnet32_purge_rx_ring(struct net_device
*dev
)
658 struct pcnet32_private
*lp
= dev
->priv
;
661 /* free all allocated skbuffs */
662 for (i
= 0; i
< lp
->rx_ring_size
; i
++) {
663 lp
->rx_ring
[i
].status
= 0; /* CPU owns buffer */
664 wmb(); /* Make sure adapter sees owner change */
665 if (lp
->rx_skbuff
[i
]) {
666 pci_unmap_single(lp
->pci_dev
, lp
->rx_dma_addr
[i
],
667 PKT_BUF_SZ
- 2, PCI_DMA_FROMDEVICE
);
668 dev_kfree_skb_any(lp
->rx_skbuff
[i
]);
670 lp
->rx_skbuff
[i
] = NULL
;
671 lp
->rx_dma_addr
[i
] = 0;
675 #ifdef CONFIG_NET_POLL_CONTROLLER
676 static void pcnet32_poll_controller(struct net_device
*dev
)
678 disable_irq(dev
->irq
);
679 pcnet32_interrupt(0, dev
, NULL
);
680 enable_irq(dev
->irq
);
684 static int pcnet32_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
686 struct pcnet32_private
*lp
= dev
->priv
;
691 spin_lock_irqsave(&lp
->lock
, flags
);
692 mii_ethtool_gset(&lp
->mii_if
, cmd
);
693 spin_unlock_irqrestore(&lp
->lock
, flags
);
699 static int pcnet32_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
701 struct pcnet32_private
*lp
= dev
->priv
;
706 spin_lock_irqsave(&lp
->lock
, flags
);
707 r
= mii_ethtool_sset(&lp
->mii_if
, cmd
);
708 spin_unlock_irqrestore(&lp
->lock
, flags
);
713 static void pcnet32_get_drvinfo(struct net_device
*dev
,
714 struct ethtool_drvinfo
*info
)
716 struct pcnet32_private
*lp
= dev
->priv
;
718 strcpy(info
->driver
, DRV_NAME
);
719 strcpy(info
->version
, DRV_VERSION
);
721 strcpy(info
->bus_info
, pci_name(lp
->pci_dev
));
723 sprintf(info
->bus_info
, "VLB 0x%lx", dev
->base_addr
);
726 static u32
pcnet32_get_link(struct net_device
*dev
)
728 struct pcnet32_private
*lp
= dev
->priv
;
732 spin_lock_irqsave(&lp
->lock
, flags
);
734 r
= mii_link_ok(&lp
->mii_if
);
735 } else if (lp
->chip_version
>= PCNET32_79C970A
) {
736 ulong ioaddr
= dev
->base_addr
; /* card base I/O address */
737 r
= (lp
->a
.read_bcr(ioaddr
, 4) != 0xc0);
738 } else { /* can not detect link on really old chips */
741 spin_unlock_irqrestore(&lp
->lock
, flags
);
746 static u32
pcnet32_get_msglevel(struct net_device
*dev
)
748 struct pcnet32_private
*lp
= dev
->priv
;
749 return lp
->msg_enable
;
752 static void pcnet32_set_msglevel(struct net_device
*dev
, u32 value
)
754 struct pcnet32_private
*lp
= dev
->priv
;
755 lp
->msg_enable
= value
;
758 static int pcnet32_nway_reset(struct net_device
*dev
)
760 struct pcnet32_private
*lp
= dev
->priv
;
765 spin_lock_irqsave(&lp
->lock
, flags
);
766 r
= mii_nway_restart(&lp
->mii_if
);
767 spin_unlock_irqrestore(&lp
->lock
, flags
);
772 static void pcnet32_get_ringparam(struct net_device
*dev
,
773 struct ethtool_ringparam
*ering
)
775 struct pcnet32_private
*lp
= dev
->priv
;
777 ering
->tx_max_pending
= TX_MAX_RING_SIZE
;
778 ering
->tx_pending
= lp
->tx_ring_size
;
779 ering
->rx_max_pending
= RX_MAX_RING_SIZE
;
780 ering
->rx_pending
= lp
->rx_ring_size
;
783 static int pcnet32_set_ringparam(struct net_device
*dev
,
784 struct ethtool_ringparam
*ering
)
786 struct pcnet32_private
*lp
= dev
->priv
;
789 ulong ioaddr
= dev
->base_addr
;
792 if (ering
->rx_mini_pending
|| ering
->rx_jumbo_pending
)
795 if (netif_running(dev
))
796 pcnet32_netif_stop(dev
);
798 spin_lock_irqsave(&lp
->lock
, flags
);
799 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_STOP
); /* stop the chip */
801 size
= min(ering
->tx_pending
, (unsigned int)TX_MAX_RING_SIZE
);
803 /* set the minimum ring size to 4, to allow the loopback test to work
806 for (i
= 2; i
<= PCNET32_LOG_MAX_TX_BUFFERS
; i
++) {
807 if (size
<= (1 << i
))
810 if ((1 << i
) != lp
->tx_ring_size
)
811 pcnet32_realloc_tx_ring(dev
, lp
, i
);
813 size
= min(ering
->rx_pending
, (unsigned int)RX_MAX_RING_SIZE
);
814 for (i
= 2; i
<= PCNET32_LOG_MAX_RX_BUFFERS
; i
++) {
815 if (size
<= (1 << i
))
818 if ((1 << i
) != lp
->rx_ring_size
)
819 pcnet32_realloc_rx_ring(dev
, lp
, i
);
821 dev
->weight
= lp
->rx_ring_size
/ 2;
823 if (netif_running(dev
)) {
824 pcnet32_netif_start(dev
);
825 pcnet32_restart(dev
, CSR0_NORMAL
);
828 spin_unlock_irqrestore(&lp
->lock
, flags
);
830 if (netif_msg_drv(lp
))
832 "%s: Ring Param Settings: RX: %d, TX: %d\n", dev
->name
,
833 lp
->rx_ring_size
, lp
->tx_ring_size
);
838 static void pcnet32_get_strings(struct net_device
*dev
, u32 stringset
,
841 memcpy(data
, pcnet32_gstrings_test
, sizeof(pcnet32_gstrings_test
));
844 static int pcnet32_self_test_count(struct net_device
*dev
)
846 return PCNET32_TEST_LEN
;
849 static void pcnet32_ethtool_test(struct net_device
*dev
,
850 struct ethtool_test
*test
, u64
* data
)
852 struct pcnet32_private
*lp
= dev
->priv
;
855 if (test
->flags
== ETH_TEST_FL_OFFLINE
) {
856 rc
= pcnet32_loopback_test(dev
, data
);
858 if (netif_msg_hw(lp
))
859 printk(KERN_DEBUG
"%s: Loopback test failed.\n",
861 test
->flags
|= ETH_TEST_FL_FAILED
;
862 } else if (netif_msg_hw(lp
))
863 printk(KERN_DEBUG
"%s: Loopback test passed.\n",
865 } else if (netif_msg_hw(lp
))
867 "%s: No tests to run (specify 'Offline' on ethtool).",
869 } /* end pcnet32_ethtool_test */
871 static int pcnet32_loopback_test(struct net_device
*dev
, uint64_t * data1
)
873 struct pcnet32_private
*lp
= dev
->priv
;
874 struct pcnet32_access
*a
= &lp
->a
; /* access to registers */
875 ulong ioaddr
= dev
->base_addr
; /* card base I/O address */
876 struct sk_buff
*skb
; /* sk buff */
877 int x
, i
; /* counters */
878 int numbuffs
= 4; /* number of TX/RX buffers and descs */
879 u16 status
= 0x8300; /* TX ring status */
880 u16 teststatus
; /* test of ring status */
881 int rc
; /* return code */
882 int size
; /* size of packets */
883 unsigned char *packet
; /* source packet data */
884 static const int data_len
= 60; /* length of source packets */
888 rc
= 1; /* default to fail */
890 if (netif_running(dev
))
891 #ifdef CONFIG_PCNET32_NAPI
892 pcnet32_netif_stop(dev
);
897 spin_lock_irqsave(&lp
->lock
, flags
);
898 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_STOP
); /* stop the chip */
900 numbuffs
= min(numbuffs
, (int)min(lp
->rx_ring_size
, lp
->tx_ring_size
));
902 /* Reset the PCNET32 */
904 lp
->a
.write_csr(ioaddr
, CSR4
, 0x0915); /* auto tx pad */
906 /* switch pcnet32 to 32bit mode */
907 lp
->a
.write_bcr(ioaddr
, 20, 2);
909 /* purge & init rings but don't actually restart */
910 pcnet32_restart(dev
, 0x0000);
912 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_STOP
); /* Set STOP bit */
914 /* Initialize Transmit buffers. */
915 size
= data_len
+ 15;
916 for (x
= 0; x
< numbuffs
; x
++) {
917 if (!(skb
= dev_alloc_skb(size
))) {
918 if (netif_msg_hw(lp
))
920 "%s: Cannot allocate skb at line: %d!\n",
921 dev
->name
, __LINE__
);
925 skb_put(skb
, size
); /* create space for data */
926 lp
->tx_skbuff
[x
] = skb
;
927 lp
->tx_ring
[x
].length
= le16_to_cpu(-skb
->len
);
928 lp
->tx_ring
[x
].misc
= 0;
930 /* put DA and SA into the skb */
931 for (i
= 0; i
< 6; i
++)
932 *packet
++ = dev
->dev_addr
[i
];
933 for (i
= 0; i
< 6; i
++)
934 *packet
++ = dev
->dev_addr
[i
];
940 /* fill packet with data */
941 for (i
= 0; i
< data_len
; i
++)
945 pci_map_single(lp
->pci_dev
, skb
->data
, skb
->len
,
947 lp
->tx_ring
[x
].base
=
948 (u32
) le32_to_cpu(lp
->tx_dma_addr
[x
]);
949 wmb(); /* Make sure owner changes after all others are visible */
950 lp
->tx_ring
[x
].status
= le16_to_cpu(status
);
954 x
= a
->read_bcr(ioaddr
, 32); /* set internal loopback in BCR32 */
955 a
->write_bcr(ioaddr
, 32, x
| 0x0002);
957 /* set int loopback in CSR15 */
958 x
= a
->read_csr(ioaddr
, CSR15
) & 0xfffc;
959 lp
->a
.write_csr(ioaddr
, CSR15
, x
| 0x0044);
961 teststatus
= le16_to_cpu(0x8000);
962 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_START
); /* Set STRT bit */
964 /* Check status of descriptors */
965 for (x
= 0; x
< numbuffs
; x
++) {
968 while ((lp
->rx_ring
[x
].status
& teststatus
) && (ticks
< 200)) {
969 spin_unlock_irqrestore(&lp
->lock
, flags
);
971 spin_lock_irqsave(&lp
->lock
, flags
);
976 if (netif_msg_hw(lp
))
977 printk("%s: Desc %d failed to reset!\n",
983 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_STOP
); /* Set STOP bit */
985 if (netif_msg_hw(lp
) && netif_msg_pktdata(lp
)) {
986 printk(KERN_DEBUG
"%s: RX loopback packets:\n", dev
->name
);
988 for (x
= 0; x
< numbuffs
; x
++) {
989 printk(KERN_DEBUG
"%s: Packet %d:\n", dev
->name
, x
);
990 skb
= lp
->rx_skbuff
[x
];
991 for (i
= 0; i
< size
; i
++) {
992 printk("%02x ", *(skb
->data
+ i
));
1000 while (x
< numbuffs
&& !rc
) {
1001 skb
= lp
->rx_skbuff
[x
];
1002 packet
= lp
->tx_skbuff
[x
]->data
;
1003 for (i
= 0; i
< size
; i
++) {
1004 if (*(skb
->data
+ i
) != packet
[i
]) {
1005 if (netif_msg_hw(lp
))
1007 "%s: Error in compare! %2x - %02x %02x\n",
1008 dev
->name
, i
, *(skb
->data
+ i
),
1019 pcnet32_purge_tx_ring(dev
);
1021 x
= a
->read_csr(ioaddr
, CSR15
);
1022 a
->write_csr(ioaddr
, CSR15
, (x
& ~0x0044)); /* reset bits 6 and 2 */
1024 x
= a
->read_bcr(ioaddr
, 32); /* reset internal loopback */
1025 a
->write_bcr(ioaddr
, 32, (x
& ~0x0002));
1027 #ifdef CONFIG_PCNET32_NAPI
1028 if (netif_running(dev
)) {
1029 pcnet32_netif_start(dev
);
1030 pcnet32_restart(dev
, CSR0_NORMAL
);
1032 pcnet32_purge_rx_ring(dev
);
1033 lp
->a
.write_bcr(ioaddr
, 20, 4); /* return to 16bit mode */
1035 spin_unlock_irqrestore(&lp
->lock
, flags
);
1037 if (netif_running(dev
)) {
1038 spin_unlock_irqrestore(&lp
->lock
, flags
);
1041 pcnet32_purge_rx_ring(dev
);
1042 lp
->a
.write_bcr(ioaddr
, 20, 4); /* return to 16bit mode */
1043 spin_unlock_irqrestore(&lp
->lock
, flags
);
1048 } /* end pcnet32_loopback_test */
1050 static void pcnet32_led_blink_callback(struct net_device
*dev
)
1052 struct pcnet32_private
*lp
= dev
->priv
;
1053 struct pcnet32_access
*a
= &lp
->a
;
1054 ulong ioaddr
= dev
->base_addr
;
1055 unsigned long flags
;
1058 spin_lock_irqsave(&lp
->lock
, flags
);
1059 for (i
= 4; i
< 8; i
++) {
1060 a
->write_bcr(ioaddr
, i
, a
->read_bcr(ioaddr
, i
) ^ 0x4000);
1062 spin_unlock_irqrestore(&lp
->lock
, flags
);
1064 mod_timer(&lp
->blink_timer
, PCNET32_BLINK_TIMEOUT
);
1067 static int pcnet32_phys_id(struct net_device
*dev
, u32 data
)
1069 struct pcnet32_private
*lp
= dev
->priv
;
1070 struct pcnet32_access
*a
= &lp
->a
;
1071 ulong ioaddr
= dev
->base_addr
;
1072 unsigned long flags
;
1075 if (!lp
->blink_timer
.function
) {
1076 init_timer(&lp
->blink_timer
);
1077 lp
->blink_timer
.function
= (void *)pcnet32_led_blink_callback
;
1078 lp
->blink_timer
.data
= (unsigned long)dev
;
1081 /* Save the current value of the bcrs */
1082 spin_lock_irqsave(&lp
->lock
, flags
);
1083 for (i
= 4; i
< 8; i
++) {
1084 regs
[i
- 4] = a
->read_bcr(ioaddr
, i
);
1086 spin_unlock_irqrestore(&lp
->lock
, flags
);
1088 mod_timer(&lp
->blink_timer
, jiffies
);
1089 set_current_state(TASK_INTERRUPTIBLE
);
1091 if ((!data
) || (data
> (u32
) (MAX_SCHEDULE_TIMEOUT
/ HZ
)))
1092 data
= (u32
) (MAX_SCHEDULE_TIMEOUT
/ HZ
);
1094 msleep_interruptible(data
* 1000);
1095 del_timer_sync(&lp
->blink_timer
);
1097 /* Restore the original value of the bcrs */
1098 spin_lock_irqsave(&lp
->lock
, flags
);
1099 for (i
= 4; i
< 8; i
++) {
1100 a
->write_bcr(ioaddr
, i
, regs
[i
- 4]);
1102 spin_unlock_irqrestore(&lp
->lock
, flags
);
1108 * lp->lock must be held.
1110 static int pcnet32_suspend(struct net_device
*dev
, unsigned long *flags
,
1114 struct pcnet32_private
*lp
= dev
->priv
;
1115 struct pcnet32_access
*a
= &lp
->a
;
1116 ulong ioaddr
= dev
->base_addr
;
1119 /* really old chips have to be stopped. */
1120 if (lp
->chip_version
< PCNET32_79C970A
)
1123 /* set SUSPEND (SPND) - CSR5 bit 0 */
1124 csr5
= a
->read_csr(ioaddr
, CSR5
);
1125 a
->write_csr(ioaddr
, CSR5
, csr5
| CSR5_SUSPEND
);
1127 /* poll waiting for bit to be set */
1129 while (!(a
->read_csr(ioaddr
, CSR5
) & CSR5_SUSPEND
)) {
1130 spin_unlock_irqrestore(&lp
->lock
, *flags
);
1135 spin_lock_irqsave(&lp
->lock
, *flags
);
1138 if (netif_msg_hw(lp
))
1140 "%s: Error getting into suspend!\n",
1149 * process one receive descriptor entry
1152 static void pcnet32_rx_entry(struct net_device
*dev
,
1153 struct pcnet32_private
*lp
,
1154 struct pcnet32_rx_head
*rxp
,
1157 int status
= (short)le16_to_cpu(rxp
->status
) >> 8;
1158 int rx_in_place
= 0;
1159 struct sk_buff
*skb
;
1162 if (status
!= 0x03) { /* There was an error. */
1164 * There is a tricky error noted by John Murphy,
1165 * <murf@perftech.com> to Russ Nelson: Even with full-sized
1166 * buffers it's possible for a jabber packet to use two
1167 * buffers, with only the last correctly noting the error.
1169 if (status
& 0x01) /* Only count a general error at the */
1170 lp
->stats
.rx_errors
++; /* end of a packet. */
1172 lp
->stats
.rx_frame_errors
++;
1174 lp
->stats
.rx_over_errors
++;
1176 lp
->stats
.rx_crc_errors
++;
1178 lp
->stats
.rx_fifo_errors
++;
1182 pkt_len
= (le32_to_cpu(rxp
->msg_length
) & 0xfff) - 4;
1184 /* Discard oversize frames. */
1185 if (unlikely(pkt_len
> PKT_BUF_SZ
- 2)) {
1186 if (netif_msg_drv(lp
))
1187 printk(KERN_ERR
"%s: Impossible packet size %d!\n",
1188 dev
->name
, pkt_len
);
1189 lp
->stats
.rx_errors
++;
1193 if (netif_msg_rx_err(lp
))
1194 printk(KERN_ERR
"%s: Runt packet!\n", dev
->name
);
1195 lp
->stats
.rx_errors
++;
1199 if (pkt_len
> rx_copybreak
) {
1200 struct sk_buff
*newskb
;
1202 if ((newskb
= dev_alloc_skb(PKT_BUF_SZ
))) {
1203 skb_reserve(newskb
, 2);
1204 skb
= lp
->rx_skbuff
[entry
];
1205 pci_unmap_single(lp
->pci_dev
,
1206 lp
->rx_dma_addr
[entry
],
1208 PCI_DMA_FROMDEVICE
);
1209 skb_put(skb
, pkt_len
);
1210 lp
->rx_skbuff
[entry
] = newskb
;
1212 lp
->rx_dma_addr
[entry
] =
1213 pci_map_single(lp
->pci_dev
,
1216 PCI_DMA_FROMDEVICE
);
1217 rxp
->base
= le32_to_cpu(lp
->rx_dma_addr
[entry
]);
1222 skb
= dev_alloc_skb(pkt_len
+ 2);
1226 if (netif_msg_drv(lp
))
1228 "%s: Memory squeeze, dropping packet.\n",
1230 lp
->stats
.rx_dropped
++;
1235 skb_reserve(skb
, 2); /* 16 byte align */
1236 skb_put(skb
, pkt_len
); /* Make room */
1237 pci_dma_sync_single_for_cpu(lp
->pci_dev
,
1238 lp
->rx_dma_addr
[entry
],
1240 PCI_DMA_FROMDEVICE
);
1241 eth_copy_and_sum(skb
,
1242 (unsigned char *)(lp
->rx_skbuff
[entry
]->data
),
1244 pci_dma_sync_single_for_device(lp
->pci_dev
,
1245 lp
->rx_dma_addr
[entry
],
1247 PCI_DMA_FROMDEVICE
);
1249 lp
->stats
.rx_bytes
+= skb
->len
;
1250 skb
->protocol
= eth_type_trans(skb
, dev
);
1251 #ifdef CONFIG_PCNET32_NAPI
1252 netif_receive_skb(skb
);
1256 dev
->last_rx
= jiffies
;
1257 lp
->stats
.rx_packets
++;
1261 static int pcnet32_rx(struct net_device
*dev
, int quota
)
1263 struct pcnet32_private
*lp
= dev
->priv
;
1264 int entry
= lp
->cur_rx
& lp
->rx_mod_mask
;
1265 struct pcnet32_rx_head
*rxp
= &lp
->rx_ring
[entry
];
1268 /* If we own the next entry, it's a new packet. Send it up. */
1269 while (quota
> npackets
&& (short)le16_to_cpu(rxp
->status
) >= 0) {
1270 pcnet32_rx_entry(dev
, lp
, rxp
, entry
);
1273 * The docs say that the buffer length isn't touched, but Andrew
1274 * Boyd of QNX reports that some revs of the 79C965 clear it.
1276 rxp
->buf_length
= le16_to_cpu(2 - PKT_BUF_SZ
);
1277 wmb(); /* Make sure owner changes after others are visible */
1278 rxp
->status
= le16_to_cpu(0x8000);
1279 entry
= (++lp
->cur_rx
) & lp
->rx_mod_mask
;
1280 rxp
= &lp
->rx_ring
[entry
];
1286 static int pcnet32_tx(struct net_device
*dev
)
1288 struct pcnet32_private
*lp
= dev
->priv
;
1289 unsigned int dirty_tx
= lp
->dirty_tx
;
1291 int must_restart
= 0;
1293 while (dirty_tx
!= lp
->cur_tx
) {
1294 int entry
= dirty_tx
& lp
->tx_mod_mask
;
1295 int status
= (short)le16_to_cpu(lp
->tx_ring
[entry
].status
);
1298 break; /* It still hasn't been Txed */
1300 lp
->tx_ring
[entry
].base
= 0;
1302 if (status
& 0x4000) {
1303 /* There was a major error, log it. */
1304 int err_status
= le32_to_cpu(lp
->tx_ring
[entry
].misc
);
1305 lp
->stats
.tx_errors
++;
1306 if (netif_msg_tx_err(lp
))
1308 "%s: Tx error status=%04x err_status=%08x\n",
1311 if (err_status
& 0x04000000)
1312 lp
->stats
.tx_aborted_errors
++;
1313 if (err_status
& 0x08000000)
1314 lp
->stats
.tx_carrier_errors
++;
1315 if (err_status
& 0x10000000)
1316 lp
->stats
.tx_window_errors
++;
1318 if (err_status
& 0x40000000) {
1319 lp
->stats
.tx_fifo_errors
++;
1320 /* Ackk! On FIFO errors the Tx unit is turned off! */
1321 /* Remove this verbosity later! */
1322 if (netif_msg_tx_err(lp
))
1324 "%s: Tx FIFO error!\n",
1329 if (err_status
& 0x40000000) {
1330 lp
->stats
.tx_fifo_errors
++;
1331 if (!lp
->dxsuflo
) { /* If controller doesn't recover ... */
1332 /* Ackk! On FIFO errors the Tx unit is turned off! */
1333 /* Remove this verbosity later! */
1334 if (netif_msg_tx_err(lp
))
1336 "%s: Tx FIFO error!\n",
1343 if (status
& 0x1800)
1344 lp
->stats
.collisions
++;
1345 lp
->stats
.tx_packets
++;
1348 /* We must free the original skb */
1349 if (lp
->tx_skbuff
[entry
]) {
1350 pci_unmap_single(lp
->pci_dev
,
1351 lp
->tx_dma_addr
[entry
],
1352 lp
->tx_skbuff
[entry
]->
1353 len
, PCI_DMA_TODEVICE
);
1354 dev_kfree_skb_any(lp
->tx_skbuff
[entry
]);
1355 lp
->tx_skbuff
[entry
] = NULL
;
1356 lp
->tx_dma_addr
[entry
] = 0;
1361 delta
= (lp
->cur_tx
- dirty_tx
) & (lp
->tx_mod_mask
+ lp
->tx_ring_size
);
1362 if (delta
> lp
->tx_ring_size
) {
1363 if (netif_msg_drv(lp
))
1365 "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1366 dev
->name
, dirty_tx
, lp
->cur_tx
,
1368 dirty_tx
+= lp
->tx_ring_size
;
1369 delta
-= lp
->tx_ring_size
;
1373 netif_queue_stopped(dev
) &&
1374 delta
< lp
->tx_ring_size
- 2) {
1375 /* The ring is no longer full, clear tbusy. */
1377 netif_wake_queue(dev
);
1379 lp
->dirty_tx
= dirty_tx
;
1381 return must_restart
;
1384 #ifdef CONFIG_PCNET32_NAPI
1385 static int pcnet32_poll(struct net_device
*dev
, int *budget
)
1387 struct pcnet32_private
*lp
= dev
->priv
;
1388 int quota
= min(dev
->quota
, *budget
);
1389 unsigned long ioaddr
= dev
->base_addr
;
1390 unsigned long flags
;
1393 quota
= pcnet32_rx(dev
, quota
);
1395 spin_lock_irqsave(&lp
->lock
, flags
);
1396 if (pcnet32_tx(dev
)) {
1397 /* reset the chip to clear the error condition, then restart */
1398 lp
->a
.reset(ioaddr
);
1399 lp
->a
.write_csr(ioaddr
, CSR4
, 0x0915); /* auto tx pad */
1400 pcnet32_restart(dev
, CSR0_START
);
1401 netif_wake_queue(dev
);
1403 spin_unlock_irqrestore(&lp
->lock
, flags
);
1406 dev
->quota
-= quota
;
1408 if (dev
->quota
== 0) {
1412 netif_rx_complete(dev
);
1414 spin_lock_irqsave(&lp
->lock
, flags
);
1416 /* clear interrupt masks */
1417 val
= lp
->a
.read_csr(ioaddr
, CSR3
);
1419 lp
->a
.write_csr(ioaddr
, CSR3
, val
);
1421 /* Set interrupt enable. */
1422 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_INTEN
);
1424 spin_unlock_irqrestore(&lp
->lock
, flags
);
1430 #define PCNET32_REGS_PER_PHY 32
1431 #define PCNET32_MAX_PHYS 32
1432 static int pcnet32_get_regs_len(struct net_device
*dev
)
1434 struct pcnet32_private
*lp
= dev
->priv
;
1435 int j
= lp
->phycount
* PCNET32_REGS_PER_PHY
;
1437 return ((PCNET32_NUM_REGS
+ j
) * sizeof(u16
));
1440 static void pcnet32_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1445 struct pcnet32_private
*lp
= dev
->priv
;
1446 struct pcnet32_access
*a
= &lp
->a
;
1447 ulong ioaddr
= dev
->base_addr
;
1448 unsigned long flags
;
1450 spin_lock_irqsave(&lp
->lock
, flags
);
1452 csr0
= a
->read_csr(ioaddr
, CSR0
);
1453 if (!(csr0
& CSR0_STOP
)) /* If not stopped */
1454 pcnet32_suspend(dev
, &flags
, 1);
1456 /* read address PROM */
1457 for (i
= 0; i
< 16; i
+= 2)
1458 *buff
++ = inw(ioaddr
+ i
);
1460 /* read control and status registers */
1461 for (i
= 0; i
< 90; i
++) {
1462 *buff
++ = a
->read_csr(ioaddr
, i
);
1465 *buff
++ = a
->read_csr(ioaddr
, 112);
1466 *buff
++ = a
->read_csr(ioaddr
, 114);
1468 /* read bus configuration registers */
1469 for (i
= 0; i
< 30; i
++) {
1470 *buff
++ = a
->read_bcr(ioaddr
, i
);
1472 *buff
++ = 0; /* skip bcr30 so as not to hang 79C976 */
1473 for (i
= 31; i
< 36; i
++) {
1474 *buff
++ = a
->read_bcr(ioaddr
, i
);
1477 /* read mii phy registers */
1480 for (j
= 0; j
< PCNET32_MAX_PHYS
; j
++) {
1481 if (lp
->phymask
& (1 << j
)) {
1482 for (i
= 0; i
< PCNET32_REGS_PER_PHY
; i
++) {
1483 lp
->a
.write_bcr(ioaddr
, 33,
1485 *buff
++ = lp
->a
.read_bcr(ioaddr
, 34);
1491 if (!(csr0
& CSR0_STOP
)) { /* If not stopped */
1494 /* clear SUSPEND (SPND) - CSR5 bit 0 */
1495 csr5
= a
->read_csr(ioaddr
, CSR5
);
1496 a
->write_csr(ioaddr
, CSR5
, csr5
& (~CSR5_SUSPEND
));
1499 spin_unlock_irqrestore(&lp
->lock
, flags
);
1502 static const struct ethtool_ops pcnet32_ethtool_ops
= {
1503 .get_settings
= pcnet32_get_settings
,
1504 .set_settings
= pcnet32_set_settings
,
1505 .get_drvinfo
= pcnet32_get_drvinfo
,
1506 .get_msglevel
= pcnet32_get_msglevel
,
1507 .set_msglevel
= pcnet32_set_msglevel
,
1508 .nway_reset
= pcnet32_nway_reset
,
1509 .get_link
= pcnet32_get_link
,
1510 .get_ringparam
= pcnet32_get_ringparam
,
1511 .set_ringparam
= pcnet32_set_ringparam
,
1512 .get_tx_csum
= ethtool_op_get_tx_csum
,
1513 .get_sg
= ethtool_op_get_sg
,
1514 .get_tso
= ethtool_op_get_tso
,
1515 .get_strings
= pcnet32_get_strings
,
1516 .self_test_count
= pcnet32_self_test_count
,
1517 .self_test
= pcnet32_ethtool_test
,
1518 .phys_id
= pcnet32_phys_id
,
1519 .get_regs_len
= pcnet32_get_regs_len
,
1520 .get_regs
= pcnet32_get_regs
,
1521 .get_perm_addr
= ethtool_op_get_perm_addr
,
1524 /* only probes for non-PCI devices, the rest are handled by
1525 * pci_register_driver via pcnet32_probe_pci */
1527 static void __devinit
pcnet32_probe_vlbus(unsigned int *pcnet32_portlist
)
1529 unsigned int *port
, ioaddr
;
1531 /* search for PCnet32 VLB cards at known addresses */
1532 for (port
= pcnet32_portlist
; (ioaddr
= *port
); port
++) {
1534 (ioaddr
, PCNET32_TOTAL_SIZE
, "pcnet32_probe_vlbus")) {
1535 /* check if there is really a pcnet chip on that ioaddr */
1536 if ((inb(ioaddr
+ 14) == 0x57)
1537 && (inb(ioaddr
+ 15) == 0x57)) {
1538 pcnet32_probe1(ioaddr
, 0, NULL
);
1540 release_region(ioaddr
, PCNET32_TOTAL_SIZE
);
1546 static int __devinit
1547 pcnet32_probe_pci(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1549 unsigned long ioaddr
;
1552 err
= pci_enable_device(pdev
);
1554 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1556 "failed to enable device -- err=%d\n", err
);
1559 pci_set_master(pdev
);
1561 ioaddr
= pci_resource_start(pdev
, 0);
1563 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1565 "card has no PCI IO resources, aborting\n");
1569 if (!pci_dma_supported(pdev
, PCNET32_DMA_MASK
)) {
1570 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1572 "architecture does not support 32bit PCI busmaster DMA\n");
1575 if (request_region(ioaddr
, PCNET32_TOTAL_SIZE
, "pcnet32_probe_pci") ==
1577 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1579 "io address range already allocated\n");
1583 err
= pcnet32_probe1(ioaddr
, 1, pdev
);
1585 pci_disable_device(pdev
);
1591 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1592 * pdev will be NULL when called from pcnet32_probe_vlbus.
1594 static int __devinit
1595 pcnet32_probe1(unsigned long ioaddr
, int shared
, struct pci_dev
*pdev
)
1597 struct pcnet32_private
*lp
;
1598 dma_addr_t lp_dma_addr
;
1600 int fdx
, mii
, fset
, dxsuflo
;
1603 struct net_device
*dev
;
1604 struct pcnet32_access
*a
= NULL
;
1608 /* reset the chip */
1609 pcnet32_wio_reset(ioaddr
);
1611 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1612 if (pcnet32_wio_read_csr(ioaddr
, 0) == 4 && pcnet32_wio_check(ioaddr
)) {
1615 pcnet32_dwio_reset(ioaddr
);
1616 if (pcnet32_dwio_read_csr(ioaddr
, 0) == 4
1617 && pcnet32_dwio_check(ioaddr
)) {
1620 goto err_release_region
;
1624 a
->read_csr(ioaddr
, 88) | (a
->read_csr(ioaddr
, 89) << 16);
1625 if ((pcnet32_debug
& NETIF_MSG_PROBE
) && (pcnet32_debug
& NETIF_MSG_HW
))
1626 printk(KERN_INFO
" PCnet chip version is %#x.\n",
1628 if ((chip_version
& 0xfff) != 0x003) {
1629 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1630 printk(KERN_INFO PFX
"Unsupported chip version.\n");
1631 goto err_release_region
;
1634 /* initialize variables */
1635 fdx
= mii
= fset
= dxsuflo
= 0;
1636 chip_version
= (chip_version
>> 12) & 0xffff;
1638 switch (chip_version
) {
1640 chipname
= "PCnet/PCI 79C970"; /* PCI */
1644 chipname
= "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
1646 chipname
= "PCnet/32 79C965"; /* 486/VL bus */
1649 chipname
= "PCnet/PCI II 79C970A"; /* PCI */
1653 chipname
= "PCnet/FAST 79C971"; /* PCI */
1659 chipname
= "PCnet/FAST+ 79C972"; /* PCI */
1665 chipname
= "PCnet/FAST III 79C973"; /* PCI */
1670 chipname
= "PCnet/Home 79C978"; /* PCI */
1673 * This is based on specs published at www.amd.com. This section
1674 * assumes that a card with a 79C978 wants to go into standard
1675 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode,
1676 * and the module option homepna=1 can select this instead.
1678 media
= a
->read_bcr(ioaddr
, 49);
1679 media
&= ~3; /* default to 10Mb ethernet */
1680 if (cards_found
< MAX_UNITS
&& homepna
[cards_found
])
1681 media
|= 1; /* switch to home wiring mode */
1682 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1683 printk(KERN_DEBUG PFX
"media set to %sMbit mode.\n",
1684 (media
& 1) ? "1" : "10");
1685 a
->write_bcr(ioaddr
, 49, media
);
1688 chipname
= "PCnet/FAST III 79C975"; /* PCI */
1693 chipname
= "PCnet/PRO 79C976";
1698 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1699 printk(KERN_INFO PFX
1700 "PCnet version %#x, no PCnet32 chip.\n",
1702 goto err_release_region
;
1706 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1707 * starting until the packet is loaded. Strike one for reliability, lose
1708 * one for latency - although on PCI this isnt a big loss. Older chips
1709 * have FIFO's smaller than a packet, so you can't do this.
1710 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1714 a
->write_bcr(ioaddr
, 18, (a
->read_bcr(ioaddr
, 18) | 0x0860));
1715 a
->write_csr(ioaddr
, 80,
1716 (a
->read_csr(ioaddr
, 80) & 0x0C00) | 0x0c00);
1720 dev
= alloc_etherdev(0);
1722 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1723 printk(KERN_ERR PFX
"Memory allocation failed.\n");
1725 goto err_release_region
;
1727 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1729 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1730 printk(KERN_INFO PFX
"%s at %#3lx,", chipname
, ioaddr
);
1732 /* In most chips, after a chip reset, the ethernet address is read from the
1733 * station address PROM at the base address and programmed into the
1734 * "Physical Address Registers" CSR12-14.
1735 * As a precautionary measure, we read the PROM values and complain if
1736 * they disagree with the CSRs. If they miscompare, and the PROM addr
1737 * is valid, then the PROM addr is used.
1739 for (i
= 0; i
< 3; i
++) {
1741 val
= a
->read_csr(ioaddr
, i
+ 12) & 0x0ffff;
1742 /* There may be endianness issues here. */
1743 dev
->dev_addr
[2 * i
] = val
& 0x0ff;
1744 dev
->dev_addr
[2 * i
+ 1] = (val
>> 8) & 0x0ff;
1747 /* read PROM address and compare with CSR address */
1748 for (i
= 0; i
< 6; i
++)
1749 promaddr
[i
] = inb(ioaddr
+ i
);
1751 if (memcmp(promaddr
, dev
->dev_addr
, 6)
1752 || !is_valid_ether_addr(dev
->dev_addr
)) {
1753 if (is_valid_ether_addr(promaddr
)) {
1754 if (pcnet32_debug
& NETIF_MSG_PROBE
) {
1755 printk(" warning: CSR address invalid,\n");
1757 " using instead PROM address of");
1759 memcpy(dev
->dev_addr
, promaddr
, 6);
1762 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
1764 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1765 if (!is_valid_ether_addr(dev
->perm_addr
))
1766 memset(dev
->dev_addr
, 0, sizeof(dev
->dev_addr
));
1768 if (pcnet32_debug
& NETIF_MSG_PROBE
) {
1769 for (i
= 0; i
< 6; i
++)
1770 printk(" %2.2x", dev
->dev_addr
[i
]);
1772 /* Version 0x2623 and 0x2624 */
1773 if (((chip_version
+ 1) & 0xfffe) == 0x2624) {
1774 i
= a
->read_csr(ioaddr
, 80) & 0x0C00; /* Check tx_start_pt */
1775 printk("\n" KERN_INFO
" tx_start_pt(0x%04x):", i
);
1778 printk(" 20 bytes,");
1781 printk(" 64 bytes,");
1784 printk(" 128 bytes,");
1787 printk("~220 bytes,");
1790 i
= a
->read_bcr(ioaddr
, 18); /* Check Burst/Bus control */
1791 printk(" BCR18(%x):", i
& 0xffff);
1793 printk("BurstWrEn ");
1795 printk("BurstRdEn ");
1800 i
= a
->read_bcr(ioaddr
, 25);
1801 printk("\n" KERN_INFO
" SRAMSIZE=0x%04x,", i
<< 8);
1802 i
= a
->read_bcr(ioaddr
, 26);
1803 printk(" SRAM_BND=0x%04x,", i
<< 8);
1804 i
= a
->read_bcr(ioaddr
, 27);
1810 dev
->base_addr
= ioaddr
;
1811 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
1813 pci_alloc_consistent(pdev
, sizeof(*lp
), &lp_dma_addr
)) == NULL
) {
1814 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1816 "Consistent memory allocation failed.\n");
1818 goto err_free_netdev
;
1821 memset(lp
, 0, sizeof(*lp
));
1822 lp
->dma_addr
= lp_dma_addr
;
1825 spin_lock_init(&lp
->lock
);
1827 SET_MODULE_OWNER(dev
);
1828 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1830 lp
->name
= chipname
;
1831 lp
->shared_irq
= shared
;
1832 lp
->tx_ring_size
= TX_RING_SIZE
; /* default tx ring size */
1833 lp
->rx_ring_size
= RX_RING_SIZE
; /* default rx ring size */
1834 lp
->tx_mod_mask
= lp
->tx_ring_size
- 1;
1835 lp
->rx_mod_mask
= lp
->rx_ring_size
- 1;
1836 lp
->tx_len_bits
= (PCNET32_LOG_TX_BUFFERS
<< 12);
1837 lp
->rx_len_bits
= (PCNET32_LOG_RX_BUFFERS
<< 4);
1838 lp
->mii_if
.full_duplex
= fdx
;
1839 lp
->mii_if
.phy_id_mask
= 0x1f;
1840 lp
->mii_if
.reg_num_mask
= 0x1f;
1841 lp
->dxsuflo
= dxsuflo
;
1843 lp
->chip_version
= chip_version
;
1844 lp
->msg_enable
= pcnet32_debug
;
1845 if ((cards_found
>= MAX_UNITS
)
1846 || (options
[cards_found
] > sizeof(options_mapping
)))
1847 lp
->options
= PCNET32_PORT_ASEL
;
1849 lp
->options
= options_mapping
[options
[cards_found
]];
1850 lp
->mii_if
.dev
= dev
;
1851 lp
->mii_if
.mdio_read
= mdio_read
;
1852 lp
->mii_if
.mdio_write
= mdio_write
;
1854 if (fdx
&& !(lp
->options
& PCNET32_PORT_ASEL
) &&
1855 ((cards_found
>= MAX_UNITS
) || full_duplex
[cards_found
]))
1856 lp
->options
|= PCNET32_PORT_FD
;
1859 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1860 printk(KERN_ERR PFX
"No access methods\n");
1862 goto err_free_consistent
;
1866 /* prior to register_netdev, dev->name is not yet correct */
1867 if (pcnet32_alloc_ring(dev
, pci_name(lp
->pci_dev
))) {
1871 /* detect special T1/E1 WAN card by checking for MAC address */
1872 if (dev
->dev_addr
[0] == 0x00 && dev
->dev_addr
[1] == 0xe0
1873 && dev
->dev_addr
[2] == 0x75)
1874 lp
->options
= PCNET32_PORT_FD
| PCNET32_PORT_GPSI
;
1876 lp
->init_block
.mode
= le16_to_cpu(0x0003); /* Disable Rx and Tx. */
1877 lp
->init_block
.tlen_rlen
=
1878 le16_to_cpu(lp
->tx_len_bits
| lp
->rx_len_bits
);
1879 for (i
= 0; i
< 6; i
++)
1880 lp
->init_block
.phys_addr
[i
] = dev
->dev_addr
[i
];
1881 lp
->init_block
.filter
[0] = 0x00000000;
1882 lp
->init_block
.filter
[1] = 0x00000000;
1883 lp
->init_block
.rx_ring
= (u32
) le32_to_cpu(lp
->rx_ring_dma_addr
);
1884 lp
->init_block
.tx_ring
= (u32
) le32_to_cpu(lp
->tx_ring_dma_addr
);
1886 /* switch pcnet32 to 32bit mode */
1887 a
->write_bcr(ioaddr
, 20, 2);
1889 a
->write_csr(ioaddr
, 1, (lp
->dma_addr
+ offsetof(struct pcnet32_private
,
1890 init_block
)) & 0xffff);
1891 a
->write_csr(ioaddr
, 2, (lp
->dma_addr
+ offsetof(struct pcnet32_private
,
1892 init_block
)) >> 16);
1894 if (pdev
) { /* use the IRQ provided by PCI */
1895 dev
->irq
= pdev
->irq
;
1896 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1897 printk(" assigned IRQ %d.\n", dev
->irq
);
1899 unsigned long irq_mask
= probe_irq_on();
1902 * To auto-IRQ we enable the initialization-done and DMA error
1903 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1906 /* Trigger an initialization just for the interrupt. */
1907 a
->write_csr(ioaddr
, CSR0
, CSR0_INTEN
| CSR0_INIT
);
1910 dev
->irq
= probe_irq_off(irq_mask
);
1912 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1913 printk(", failed to detect IRQ line.\n");
1917 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1918 printk(", probed IRQ %d.\n", dev
->irq
);
1921 /* Set the mii phy_id so that we can query the link state */
1923 /* lp->phycount and lp->phymask are set to 0 by memset above */
1925 lp
->mii_if
.phy_id
= ((lp
->a
.read_bcr(ioaddr
, 33)) >> 5) & 0x1f;
1927 for (i
= 0; i
< PCNET32_MAX_PHYS
; i
++) {
1928 unsigned short id1
, id2
;
1930 id1
= mdio_read(dev
, i
, MII_PHYSID1
);
1933 id2
= mdio_read(dev
, i
, MII_PHYSID2
);
1936 if (i
== 31 && ((chip_version
+ 1) & 0xfffe) == 0x2624)
1937 continue; /* 79C971 & 79C972 have phantom phy at id 31 */
1939 lp
->phymask
|= (1 << i
);
1940 lp
->mii_if
.phy_id
= i
;
1941 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1942 printk(KERN_INFO PFX
1943 "Found PHY %04x:%04x at address %d.\n",
1946 lp
->a
.write_bcr(ioaddr
, 33, (lp
->mii_if
.phy_id
) << 5);
1947 if (lp
->phycount
> 1) {
1948 lp
->options
|= PCNET32_PORT_MII
;
1952 init_timer(&lp
->watchdog_timer
);
1953 lp
->watchdog_timer
.data
= (unsigned long)dev
;
1954 lp
->watchdog_timer
.function
= (void *)&pcnet32_watchdog
;
1956 /* The PCNET32-specific entries in the device structure. */
1957 dev
->open
= &pcnet32_open
;
1958 dev
->hard_start_xmit
= &pcnet32_start_xmit
;
1959 dev
->stop
= &pcnet32_close
;
1960 dev
->get_stats
= &pcnet32_get_stats
;
1961 dev
->set_multicast_list
= &pcnet32_set_multicast_list
;
1962 dev
->do_ioctl
= &pcnet32_ioctl
;
1963 dev
->ethtool_ops
= &pcnet32_ethtool_ops
;
1964 dev
->tx_timeout
= pcnet32_tx_timeout
;
1965 dev
->watchdog_timeo
= (5 * HZ
);
1966 dev
->weight
= lp
->rx_ring_size
/ 2;
1967 #ifdef CONFIG_PCNET32_NAPI
1968 dev
->poll
= pcnet32_poll
;
1971 #ifdef CONFIG_NET_POLL_CONTROLLER
1972 dev
->poll_controller
= pcnet32_poll_controller
;
1975 /* Fill in the generic fields of the device structure. */
1976 if (register_netdev(dev
))
1980 pci_set_drvdata(pdev
, dev
);
1982 lp
->next
= pcnet32_dev
;
1986 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1987 printk(KERN_INFO
"%s: registered as %s\n", dev
->name
, lp
->name
);
1990 /* enable LED writes */
1991 a
->write_bcr(ioaddr
, 2, a
->read_bcr(ioaddr
, 2) | 0x1000);
1996 pcnet32_free_ring(dev
);
1997 err_free_consistent
:
1998 pci_free_consistent(lp
->pci_dev
, sizeof(*lp
), lp
, lp
->dma_addr
);
2002 release_region(ioaddr
, PCNET32_TOTAL_SIZE
);
2006 /* if any allocation fails, caller must also call pcnet32_free_ring */
2007 static int pcnet32_alloc_ring(struct net_device
*dev
, char *name
)
2009 struct pcnet32_private
*lp
= dev
->priv
;
2011 lp
->tx_ring
= pci_alloc_consistent(lp
->pci_dev
,
2012 sizeof(struct pcnet32_tx_head
) *
2014 &lp
->tx_ring_dma_addr
);
2015 if (lp
->tx_ring
== NULL
) {
2016 if (netif_msg_drv(lp
))
2017 printk("\n" KERN_ERR PFX
2018 "%s: Consistent memory allocation failed.\n",
2023 lp
->rx_ring
= pci_alloc_consistent(lp
->pci_dev
,
2024 sizeof(struct pcnet32_rx_head
) *
2026 &lp
->rx_ring_dma_addr
);
2027 if (lp
->rx_ring
== NULL
) {
2028 if (netif_msg_drv(lp
))
2029 printk("\n" KERN_ERR PFX
2030 "%s: Consistent memory allocation failed.\n",
2035 lp
->tx_dma_addr
= kcalloc(lp
->tx_ring_size
, sizeof(dma_addr_t
),
2037 if (!lp
->tx_dma_addr
) {
2038 if (netif_msg_drv(lp
))
2039 printk("\n" KERN_ERR PFX
2040 "%s: Memory allocation failed.\n", name
);
2044 lp
->rx_dma_addr
= kcalloc(lp
->rx_ring_size
, sizeof(dma_addr_t
),
2046 if (!lp
->rx_dma_addr
) {
2047 if (netif_msg_drv(lp
))
2048 printk("\n" KERN_ERR PFX
2049 "%s: Memory allocation failed.\n", name
);
2053 lp
->tx_skbuff
= kcalloc(lp
->tx_ring_size
, sizeof(struct sk_buff
*),
2055 if (!lp
->tx_skbuff
) {
2056 if (netif_msg_drv(lp
))
2057 printk("\n" KERN_ERR PFX
2058 "%s: Memory allocation failed.\n", name
);
2062 lp
->rx_skbuff
= kcalloc(lp
->rx_ring_size
, sizeof(struct sk_buff
*),
2064 if (!lp
->rx_skbuff
) {
2065 if (netif_msg_drv(lp
))
2066 printk("\n" KERN_ERR PFX
2067 "%s: Memory allocation failed.\n", name
);
2074 static void pcnet32_free_ring(struct net_device
*dev
)
2076 struct pcnet32_private
*lp
= dev
->priv
;
2078 kfree(lp
->tx_skbuff
);
2079 lp
->tx_skbuff
= NULL
;
2081 kfree(lp
->rx_skbuff
);
2082 lp
->rx_skbuff
= NULL
;
2084 kfree(lp
->tx_dma_addr
);
2085 lp
->tx_dma_addr
= NULL
;
2087 kfree(lp
->rx_dma_addr
);
2088 lp
->rx_dma_addr
= NULL
;
2091 pci_free_consistent(lp
->pci_dev
,
2092 sizeof(struct pcnet32_tx_head
) *
2093 lp
->tx_ring_size
, lp
->tx_ring
,
2094 lp
->tx_ring_dma_addr
);
2099 pci_free_consistent(lp
->pci_dev
,
2100 sizeof(struct pcnet32_rx_head
) *
2101 lp
->rx_ring_size
, lp
->rx_ring
,
2102 lp
->rx_ring_dma_addr
);
2107 static int pcnet32_open(struct net_device
*dev
)
2109 struct pcnet32_private
*lp
= dev
->priv
;
2110 unsigned long ioaddr
= dev
->base_addr
;
2114 unsigned long flags
;
2116 if (request_irq(dev
->irq
, &pcnet32_interrupt
,
2117 lp
->shared_irq
? IRQF_SHARED
: 0, dev
->name
,
2122 spin_lock_irqsave(&lp
->lock
, flags
);
2123 /* Check for a valid station address */
2124 if (!is_valid_ether_addr(dev
->dev_addr
)) {
2129 /* Reset the PCNET32 */
2130 lp
->a
.reset(ioaddr
);
2132 /* switch pcnet32 to 32bit mode */
2133 lp
->a
.write_bcr(ioaddr
, 20, 2);
2135 if (netif_msg_ifup(lp
))
2137 "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
2138 dev
->name
, dev
->irq
, (u32
) (lp
->tx_ring_dma_addr
),
2139 (u32
) (lp
->rx_ring_dma_addr
),
2140 (u32
) (lp
->dma_addr
+
2141 offsetof(struct pcnet32_private
, init_block
)));
2143 /* set/reset autoselect bit */
2144 val
= lp
->a
.read_bcr(ioaddr
, 2) & ~2;
2145 if (lp
->options
& PCNET32_PORT_ASEL
)
2147 lp
->a
.write_bcr(ioaddr
, 2, val
);
2149 /* handle full duplex setting */
2150 if (lp
->mii_if
.full_duplex
) {
2151 val
= lp
->a
.read_bcr(ioaddr
, 9) & ~3;
2152 if (lp
->options
& PCNET32_PORT_FD
) {
2154 if (lp
->options
== (PCNET32_PORT_FD
| PCNET32_PORT_AUI
))
2156 } else if (lp
->options
& PCNET32_PORT_ASEL
) {
2157 /* workaround of xSeries250, turn on for 79C975 only */
2158 if (lp
->chip_version
== 0x2627)
2161 lp
->a
.write_bcr(ioaddr
, 9, val
);
2164 /* set/reset GPSI bit in test register */
2165 val
= lp
->a
.read_csr(ioaddr
, 124) & ~0x10;
2166 if ((lp
->options
& PCNET32_PORT_PORTSEL
) == PCNET32_PORT_GPSI
)
2168 lp
->a
.write_csr(ioaddr
, 124, val
);
2170 /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
2171 if (lp
->pci_dev
->subsystem_vendor
== PCI_VENDOR_ID_AT
&&
2172 (lp
->pci_dev
->subsystem_device
== PCI_SUBDEVICE_ID_AT_2700FX
||
2173 lp
->pci_dev
->subsystem_device
== PCI_SUBDEVICE_ID_AT_2701FX
)) {
2174 if (lp
->options
& PCNET32_PORT_ASEL
) {
2175 lp
->options
= PCNET32_PORT_FD
| PCNET32_PORT_100
;
2176 if (netif_msg_link(lp
))
2178 "%s: Setting 100Mb-Full Duplex.\n",
2182 if (lp
->phycount
< 2) {
2184 * 24 Jun 2004 according AMD, in order to change the PHY,
2185 * DANAS (or DISPM for 79C976) must be set; then select the speed,
2186 * duplex, and/or enable auto negotiation, and clear DANAS
2188 if (lp
->mii
&& !(lp
->options
& PCNET32_PORT_ASEL
)) {
2189 lp
->a
.write_bcr(ioaddr
, 32,
2190 lp
->a
.read_bcr(ioaddr
, 32) | 0x0080);
2191 /* disable Auto Negotiation, set 10Mpbs, HD */
2192 val
= lp
->a
.read_bcr(ioaddr
, 32) & ~0xb8;
2193 if (lp
->options
& PCNET32_PORT_FD
)
2195 if (lp
->options
& PCNET32_PORT_100
)
2197 lp
->a
.write_bcr(ioaddr
, 32, val
);
2199 if (lp
->options
& PCNET32_PORT_ASEL
) {
2200 lp
->a
.write_bcr(ioaddr
, 32,
2201 lp
->a
.read_bcr(ioaddr
,
2203 /* enable auto negotiate, setup, disable fd */
2204 val
= lp
->a
.read_bcr(ioaddr
, 32) & ~0x98;
2206 lp
->a
.write_bcr(ioaddr
, 32, val
);
2213 struct ethtool_cmd ecmd
;
2216 * There is really no good other way to handle multiple PHYs
2217 * other than turning off all automatics
2219 val
= lp
->a
.read_bcr(ioaddr
, 2);
2220 lp
->a
.write_bcr(ioaddr
, 2, val
& ~2);
2221 val
= lp
->a
.read_bcr(ioaddr
, 32);
2222 lp
->a
.write_bcr(ioaddr
, 32, val
& ~(1 << 7)); /* stop MII manager */
2224 if (!(lp
->options
& PCNET32_PORT_ASEL
)) {
2226 ecmd
.port
= PORT_MII
;
2227 ecmd
.transceiver
= XCVR_INTERNAL
;
2228 ecmd
.autoneg
= AUTONEG_DISABLE
;
2231 options
& PCNET32_PORT_100
? SPEED_100
: SPEED_10
;
2232 bcr9
= lp
->a
.read_bcr(ioaddr
, 9);
2234 if (lp
->options
& PCNET32_PORT_FD
) {
2235 ecmd
.duplex
= DUPLEX_FULL
;
2238 ecmd
.duplex
= DUPLEX_HALF
;
2241 lp
->a
.write_bcr(ioaddr
, 9, bcr9
);
2244 for (i
= 0; i
< PCNET32_MAX_PHYS
; i
++) {
2245 if (lp
->phymask
& (1 << i
)) {
2246 /* isolate all but the first PHY */
2247 bmcr
= mdio_read(dev
, i
, MII_BMCR
);
2248 if (first_phy
== -1) {
2250 mdio_write(dev
, i
, MII_BMCR
,
2251 bmcr
& ~BMCR_ISOLATE
);
2253 mdio_write(dev
, i
, MII_BMCR
,
2254 bmcr
| BMCR_ISOLATE
);
2256 /* use mii_ethtool_sset to setup PHY */
2257 lp
->mii_if
.phy_id
= i
;
2258 ecmd
.phy_address
= i
;
2259 if (lp
->options
& PCNET32_PORT_ASEL
) {
2260 mii_ethtool_gset(&lp
->mii_if
, &ecmd
);
2261 ecmd
.autoneg
= AUTONEG_ENABLE
;
2263 mii_ethtool_sset(&lp
->mii_if
, &ecmd
);
2266 lp
->mii_if
.phy_id
= first_phy
;
2267 if (netif_msg_link(lp
))
2268 printk(KERN_INFO
"%s: Using PHY number %d.\n",
2269 dev
->name
, first_phy
);
2273 if (lp
->dxsuflo
) { /* Disable transmit stop on underflow */
2274 val
= lp
->a
.read_csr(ioaddr
, CSR3
);
2276 lp
->a
.write_csr(ioaddr
, CSR3
, val
);
2280 lp
->init_block
.mode
=
2281 le16_to_cpu((lp
->options
& PCNET32_PORT_PORTSEL
) << 7);
2282 pcnet32_load_multicast(dev
);
2284 if (pcnet32_init_ring(dev
)) {
2289 /* Re-initialize the PCNET32, and start it when done. */
2290 lp
->a
.write_csr(ioaddr
, 1, (lp
->dma_addr
+
2291 offsetof(struct pcnet32_private
,
2292 init_block
)) & 0xffff);
2293 lp
->a
.write_csr(ioaddr
, 2,
2295 offsetof(struct pcnet32_private
, init_block
)) >> 16);
2297 lp
->a
.write_csr(ioaddr
, CSR4
, 0x0915); /* auto tx pad */
2298 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_INIT
);
2300 netif_start_queue(dev
);
2302 if (lp
->chip_version
>= PCNET32_79C970A
) {
2303 /* Print the link status and start the watchdog */
2304 pcnet32_check_media(dev
, 1);
2305 mod_timer(&(lp
->watchdog_timer
), PCNET32_WATCHDOG_TIMEOUT
);
2310 if (lp
->a
.read_csr(ioaddr
, CSR0
) & CSR0_IDON
)
2313 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
2314 * reports that doing so triggers a bug in the '974.
2316 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_NORMAL
);
2318 if (netif_msg_ifup(lp
))
2320 "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
2322 (u32
) (lp
->dma_addr
+
2323 offsetof(struct pcnet32_private
, init_block
)),
2324 lp
->a
.read_csr(ioaddr
, CSR0
));
2326 spin_unlock_irqrestore(&lp
->lock
, flags
);
2328 return 0; /* Always succeed */
2331 /* free any allocated skbuffs */
2332 pcnet32_purge_rx_ring(dev
);
2335 * Switch back to 16bit mode to avoid problems with dumb
2336 * DOS packet driver after a warm reboot
2338 lp
->a
.write_bcr(ioaddr
, 20, 4);
2341 spin_unlock_irqrestore(&lp
->lock
, flags
);
2342 free_irq(dev
->irq
, dev
);
2347 * The LANCE has been halted for one reason or another (busmaster memory
2348 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
2349 * etc.). Modern LANCE variants always reload their ring-buffer
2350 * configuration when restarted, so we must reinitialize our ring
2351 * context before restarting. As part of this reinitialization,
2352 * find all packets still on the Tx ring and pretend that they had been
2353 * sent (in effect, drop the packets on the floor) - the higher-level
2354 * protocols will time out and retransmit. It'd be better to shuffle
2355 * these skbs to a temp list and then actually re-Tx them after
2356 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
2359 static void pcnet32_purge_tx_ring(struct net_device
*dev
)
2361 struct pcnet32_private
*lp
= dev
->priv
;
2364 for (i
= 0; i
< lp
->tx_ring_size
; i
++) {
2365 lp
->tx_ring
[i
].status
= 0; /* CPU owns buffer */
2366 wmb(); /* Make sure adapter sees owner change */
2367 if (lp
->tx_skbuff
[i
]) {
2368 pci_unmap_single(lp
->pci_dev
, lp
->tx_dma_addr
[i
],
2369 lp
->tx_skbuff
[i
]->len
,
2371 dev_kfree_skb_any(lp
->tx_skbuff
[i
]);
2373 lp
->tx_skbuff
[i
] = NULL
;
2374 lp
->tx_dma_addr
[i
] = 0;
2378 /* Initialize the PCNET32 Rx and Tx rings. */
2379 static int pcnet32_init_ring(struct net_device
*dev
)
2381 struct pcnet32_private
*lp
= dev
->priv
;
2385 lp
->cur_rx
= lp
->cur_tx
= 0;
2386 lp
->dirty_rx
= lp
->dirty_tx
= 0;
2388 for (i
= 0; i
< lp
->rx_ring_size
; i
++) {
2389 struct sk_buff
*rx_skbuff
= lp
->rx_skbuff
[i
];
2390 if (rx_skbuff
== NULL
) {
2392 (rx_skbuff
= lp
->rx_skbuff
[i
] =
2393 dev_alloc_skb(PKT_BUF_SZ
))) {
2394 /* there is not much, we can do at this point */
2395 if (netif_msg_drv(lp
))
2397 "%s: pcnet32_init_ring dev_alloc_skb failed.\n",
2401 skb_reserve(rx_skbuff
, 2);
2405 if (lp
->rx_dma_addr
[i
] == 0)
2406 lp
->rx_dma_addr
[i
] =
2407 pci_map_single(lp
->pci_dev
, rx_skbuff
->data
,
2408 PKT_BUF_SZ
- 2, PCI_DMA_FROMDEVICE
);
2409 lp
->rx_ring
[i
].base
= (u32
) le32_to_cpu(lp
->rx_dma_addr
[i
]);
2410 lp
->rx_ring
[i
].buf_length
= le16_to_cpu(2 - PKT_BUF_SZ
);
2411 wmb(); /* Make sure owner changes after all others are visible */
2412 lp
->rx_ring
[i
].status
= le16_to_cpu(0x8000);
2414 /* The Tx buffer address is filled in as needed, but we do need to clear
2415 * the upper ownership bit. */
2416 for (i
= 0; i
< lp
->tx_ring_size
; i
++) {
2417 lp
->tx_ring
[i
].status
= 0; /* CPU owns buffer */
2418 wmb(); /* Make sure adapter sees owner change */
2419 lp
->tx_ring
[i
].base
= 0;
2420 lp
->tx_dma_addr
[i
] = 0;
2423 lp
->init_block
.tlen_rlen
=
2424 le16_to_cpu(lp
->tx_len_bits
| lp
->rx_len_bits
);
2425 for (i
= 0; i
< 6; i
++)
2426 lp
->init_block
.phys_addr
[i
] = dev
->dev_addr
[i
];
2427 lp
->init_block
.rx_ring
= (u32
) le32_to_cpu(lp
->rx_ring_dma_addr
);
2428 lp
->init_block
.tx_ring
= (u32
) le32_to_cpu(lp
->tx_ring_dma_addr
);
2429 wmb(); /* Make sure all changes are visible */
2433 /* the pcnet32 has been issued a stop or reset. Wait for the stop bit
2434 * then flush the pending transmit operations, re-initialize the ring,
2435 * and tell the chip to initialize.
2437 static void pcnet32_restart(struct net_device
*dev
, unsigned int csr0_bits
)
2439 struct pcnet32_private
*lp
= dev
->priv
;
2440 unsigned long ioaddr
= dev
->base_addr
;
2444 for (i
= 0; i
< 100; i
++)
2445 if (lp
->a
.read_csr(ioaddr
, CSR0
) & CSR0_STOP
)
2448 if (i
>= 100 && netif_msg_drv(lp
))
2450 "%s: pcnet32_restart timed out waiting for stop.\n",
2453 pcnet32_purge_tx_ring(dev
);
2454 if (pcnet32_init_ring(dev
))
2458 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_INIT
);
2461 if (lp
->a
.read_csr(ioaddr
, CSR0
) & CSR0_IDON
)
2464 lp
->a
.write_csr(ioaddr
, CSR0
, csr0_bits
);
2467 static void pcnet32_tx_timeout(struct net_device
*dev
)
2469 struct pcnet32_private
*lp
= dev
->priv
;
2470 unsigned long ioaddr
= dev
->base_addr
, flags
;
2472 spin_lock_irqsave(&lp
->lock
, flags
);
2473 /* Transmitter timeout, serious problems. */
2474 if (pcnet32_debug
& NETIF_MSG_DRV
)
2476 "%s: transmit timed out, status %4.4x, resetting.\n",
2477 dev
->name
, lp
->a
.read_csr(ioaddr
, CSR0
));
2478 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_STOP
);
2479 lp
->stats
.tx_errors
++;
2480 if (netif_msg_tx_err(lp
)) {
2483 " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
2484 lp
->dirty_tx
, lp
->cur_tx
, lp
->tx_full
? " (full)" : "",
2486 for (i
= 0; i
< lp
->rx_ring_size
; i
++)
2487 printk("%s %08x %04x %08x %04x", i
& 1 ? "" : "\n ",
2488 le32_to_cpu(lp
->rx_ring
[i
].base
),
2489 (-le16_to_cpu(lp
->rx_ring
[i
].buf_length
)) &
2490 0xffff, le32_to_cpu(lp
->rx_ring
[i
].msg_length
),
2491 le16_to_cpu(lp
->rx_ring
[i
].status
));
2492 for (i
= 0; i
< lp
->tx_ring_size
; i
++)
2493 printk("%s %08x %04x %08x %04x", i
& 1 ? "" : "\n ",
2494 le32_to_cpu(lp
->tx_ring
[i
].base
),
2495 (-le16_to_cpu(lp
->tx_ring
[i
].length
)) & 0xffff,
2496 le32_to_cpu(lp
->tx_ring
[i
].misc
),
2497 le16_to_cpu(lp
->tx_ring
[i
].status
));
2500 pcnet32_restart(dev
, CSR0_NORMAL
);
2502 dev
->trans_start
= jiffies
;
2503 netif_wake_queue(dev
);
2505 spin_unlock_irqrestore(&lp
->lock
, flags
);
2508 static int pcnet32_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
2510 struct pcnet32_private
*lp
= dev
->priv
;
2511 unsigned long ioaddr
= dev
->base_addr
;
2514 unsigned long flags
;
2516 spin_lock_irqsave(&lp
->lock
, flags
);
2518 if (netif_msg_tx_queued(lp
)) {
2520 "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
2521 dev
->name
, lp
->a
.read_csr(ioaddr
, CSR0
));
2524 /* Default status -- will not enable Successful-TxDone
2525 * interrupt when that option is available to us.
2529 /* Fill in a Tx ring entry */
2531 /* Mask to ring buffer boundary. */
2532 entry
= lp
->cur_tx
& lp
->tx_mod_mask
;
2534 /* Caution: the write order is important here, set the status
2535 * with the "ownership" bits last. */
2537 lp
->tx_ring
[entry
].length
= le16_to_cpu(-skb
->len
);
2539 lp
->tx_ring
[entry
].misc
= 0x00000000;
2541 lp
->tx_skbuff
[entry
] = skb
;
2542 lp
->tx_dma_addr
[entry
] =
2543 pci_map_single(lp
->pci_dev
, skb
->data
, skb
->len
, PCI_DMA_TODEVICE
);
2544 lp
->tx_ring
[entry
].base
= (u32
) le32_to_cpu(lp
->tx_dma_addr
[entry
]);
2545 wmb(); /* Make sure owner changes after all others are visible */
2546 lp
->tx_ring
[entry
].status
= le16_to_cpu(status
);
2549 lp
->stats
.tx_bytes
+= skb
->len
;
2551 /* Trigger an immediate send poll. */
2552 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_INTEN
| CSR0_TXPOLL
);
2554 dev
->trans_start
= jiffies
;
2556 if (lp
->tx_ring
[(entry
+ 1) & lp
->tx_mod_mask
].base
!= 0) {
2558 netif_stop_queue(dev
);
2560 spin_unlock_irqrestore(&lp
->lock
, flags
);
2564 /* The PCNET32 interrupt handler. */
2566 pcnet32_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
)
2568 struct net_device
*dev
= dev_id
;
2569 struct pcnet32_private
*lp
;
2570 unsigned long ioaddr
;
2572 int boguscnt
= max_interrupt_work
;
2575 if (pcnet32_debug
& NETIF_MSG_INTR
)
2576 printk(KERN_DEBUG
"%s(): irq %d for unknown device\n",
2581 ioaddr
= dev
->base_addr
;
2584 spin_lock(&lp
->lock
);
2586 csr0
= lp
->a
.read_csr(ioaddr
, CSR0
);
2587 while ((csr0
& 0x8f00) && --boguscnt
>= 0) {
2588 if (csr0
== 0xffff) {
2589 break; /* PCMCIA remove happened */
2591 /* Acknowledge all of the current interrupt sources ASAP. */
2592 lp
->a
.write_csr(ioaddr
, CSR0
, csr0
& ~0x004f);
2594 if (netif_msg_intr(lp
))
2596 "%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n",
2597 dev
->name
, csr0
, lp
->a
.read_csr(ioaddr
, CSR0
));
2599 /* Log misc errors. */
2601 lp
->stats
.tx_errors
++; /* Tx babble. */
2602 if (csr0
& 0x1000) {
2604 * This happens when our receive ring is full. This
2605 * shouldn't be a problem as we will see normal rx
2606 * interrupts for the frames in the receive ring. But
2607 * there are some PCI chipsets (I can reproduce this
2608 * on SP3G with Intel saturn chipset) which have
2609 * sometimes problems and will fill up the receive
2610 * ring with error descriptors. In this situation we
2611 * don't get a rx interrupt, but a missed frame
2612 * interrupt sooner or later.
2614 lp
->stats
.rx_errors
++; /* Missed a Rx frame. */
2616 if (csr0
& 0x0800) {
2617 if (netif_msg_drv(lp
))
2619 "%s: Bus master arbitration failure, status %4.4x.\n",
2621 /* unlike for the lance, there is no restart needed */
2623 #ifdef CONFIG_PCNET32_NAPI
2624 if (netif_rx_schedule_prep(dev
)) {
2626 /* set interrupt masks */
2627 val
= lp
->a
.read_csr(ioaddr
, CSR3
);
2629 lp
->a
.write_csr(ioaddr
, CSR3
, val
);
2631 __netif_rx_schedule(dev
);
2635 pcnet32_rx(dev
, dev
->weight
);
2636 if (pcnet32_tx(dev
)) {
2637 /* reset the chip to clear the error condition, then restart */
2638 lp
->a
.reset(ioaddr
);
2639 lp
->a
.write_csr(ioaddr
, CSR4
, 0x0915); /* auto tx pad */
2640 pcnet32_restart(dev
, CSR0_START
);
2641 netif_wake_queue(dev
);
2644 csr0
= lp
->a
.read_csr(ioaddr
, CSR0
);
2647 #ifndef CONFIG_PCNET32_NAPI
2648 /* Set interrupt enable. */
2649 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_INTEN
);
2652 if (netif_msg_intr(lp
))
2653 printk(KERN_DEBUG
"%s: exiting interrupt, csr0=%#4.4x.\n",
2654 dev
->name
, lp
->a
.read_csr(ioaddr
, CSR0
));
2656 spin_unlock(&lp
->lock
);
2661 static int pcnet32_close(struct net_device
*dev
)
2663 unsigned long ioaddr
= dev
->base_addr
;
2664 struct pcnet32_private
*lp
= dev
->priv
;
2665 unsigned long flags
;
2667 del_timer_sync(&lp
->watchdog_timer
);
2669 netif_stop_queue(dev
);
2671 spin_lock_irqsave(&lp
->lock
, flags
);
2673 lp
->stats
.rx_missed_errors
= lp
->a
.read_csr(ioaddr
, 112);
2675 if (netif_msg_ifdown(lp
))
2677 "%s: Shutting down ethercard, status was %2.2x.\n",
2678 dev
->name
, lp
->a
.read_csr(ioaddr
, CSR0
));
2680 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
2681 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_STOP
);
2684 * Switch back to 16bit mode to avoid problems with dumb
2685 * DOS packet driver after a warm reboot
2687 lp
->a
.write_bcr(ioaddr
, 20, 4);
2689 spin_unlock_irqrestore(&lp
->lock
, flags
);
2691 free_irq(dev
->irq
, dev
);
2693 spin_lock_irqsave(&lp
->lock
, flags
);
2695 pcnet32_purge_rx_ring(dev
);
2696 pcnet32_purge_tx_ring(dev
);
2698 spin_unlock_irqrestore(&lp
->lock
, flags
);
2703 static struct net_device_stats
*pcnet32_get_stats(struct net_device
*dev
)
2705 struct pcnet32_private
*lp
= dev
->priv
;
2706 unsigned long ioaddr
= dev
->base_addr
;
2707 unsigned long flags
;
2709 spin_lock_irqsave(&lp
->lock
, flags
);
2710 lp
->stats
.rx_missed_errors
= lp
->a
.read_csr(ioaddr
, 112);
2711 spin_unlock_irqrestore(&lp
->lock
, flags
);
2716 /* taken from the sunlance driver, which it took from the depca driver */
2717 static void pcnet32_load_multicast(struct net_device
*dev
)
2719 struct pcnet32_private
*lp
= dev
->priv
;
2720 volatile struct pcnet32_init_block
*ib
= &lp
->init_block
;
2721 volatile u16
*mcast_table
= (u16
*) & ib
->filter
;
2722 struct dev_mc_list
*dmi
= dev
->mc_list
;
2723 unsigned long ioaddr
= dev
->base_addr
;
2728 /* set all multicast bits */
2729 if (dev
->flags
& IFF_ALLMULTI
) {
2730 ib
->filter
[0] = 0xffffffff;
2731 ib
->filter
[1] = 0xffffffff;
2732 lp
->a
.write_csr(ioaddr
, PCNET32_MC_FILTER
, 0xffff);
2733 lp
->a
.write_csr(ioaddr
, PCNET32_MC_FILTER
+1, 0xffff);
2734 lp
->a
.write_csr(ioaddr
, PCNET32_MC_FILTER
+2, 0xffff);
2735 lp
->a
.write_csr(ioaddr
, PCNET32_MC_FILTER
+3, 0xffff);
2738 /* clear the multicast filter */
2743 for (i
= 0; i
< dev
->mc_count
; i
++) {
2744 addrs
= dmi
->dmi_addr
;
2747 /* multicast address? */
2751 crc
= ether_crc_le(6, addrs
);
2753 mcast_table
[crc
>> 4] =
2754 le16_to_cpu(le16_to_cpu(mcast_table
[crc
>> 4]) |
2755 (1 << (crc
& 0xf)));
2757 for (i
= 0; i
< 4; i
++)
2758 lp
->a
.write_csr(ioaddr
, PCNET32_MC_FILTER
+ i
,
2759 le16_to_cpu(mcast_table
[i
]));
2764 * Set or clear the multicast filter for this adaptor.
2766 static void pcnet32_set_multicast_list(struct net_device
*dev
)
2768 unsigned long ioaddr
= dev
->base_addr
, flags
;
2769 struct pcnet32_private
*lp
= dev
->priv
;
2770 int csr15
, suspended
;
2772 spin_lock_irqsave(&lp
->lock
, flags
);
2773 suspended
= pcnet32_suspend(dev
, &flags
, 0);
2774 csr15
= lp
->a
.read_csr(ioaddr
, CSR15
);
2775 if (dev
->flags
& IFF_PROMISC
) {
2776 /* Log any net taps. */
2777 if (netif_msg_hw(lp
))
2778 printk(KERN_INFO
"%s: Promiscuous mode enabled.\n",
2780 lp
->init_block
.mode
=
2781 le16_to_cpu(0x8000 | (lp
->options
& PCNET32_PORT_PORTSEL
) <<
2783 lp
->a
.write_csr(ioaddr
, CSR15
, csr15
| 0x8000);
2785 lp
->init_block
.mode
=
2786 le16_to_cpu((lp
->options
& PCNET32_PORT_PORTSEL
) << 7);
2787 lp
->a
.write_csr(ioaddr
, CSR15
, csr15
& 0x7fff);
2788 pcnet32_load_multicast(dev
);
2793 /* clear SUSPEND (SPND) - CSR5 bit 0 */
2794 csr5
= lp
->a
.read_csr(ioaddr
, CSR5
);
2795 lp
->a
.write_csr(ioaddr
, CSR5
, csr5
& (~CSR5_SUSPEND
));
2797 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_STOP
);
2798 pcnet32_restart(dev
, CSR0_NORMAL
);
2799 netif_wake_queue(dev
);
2802 spin_unlock_irqrestore(&lp
->lock
, flags
);
2805 /* This routine assumes that the lp->lock is held */
2806 static int mdio_read(struct net_device
*dev
, int phy_id
, int reg_num
)
2808 struct pcnet32_private
*lp
= dev
->priv
;
2809 unsigned long ioaddr
= dev
->base_addr
;
2815 lp
->a
.write_bcr(ioaddr
, 33, ((phy_id
& 0x1f) << 5) | (reg_num
& 0x1f));
2816 val_out
= lp
->a
.read_bcr(ioaddr
, 34);
2821 /* This routine assumes that the lp->lock is held */
2822 static void mdio_write(struct net_device
*dev
, int phy_id
, int reg_num
, int val
)
2824 struct pcnet32_private
*lp
= dev
->priv
;
2825 unsigned long ioaddr
= dev
->base_addr
;
2830 lp
->a
.write_bcr(ioaddr
, 33, ((phy_id
& 0x1f) << 5) | (reg_num
& 0x1f));
2831 lp
->a
.write_bcr(ioaddr
, 34, val
);
2834 static int pcnet32_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
2836 struct pcnet32_private
*lp
= dev
->priv
;
2838 unsigned long flags
;
2840 /* SIOC[GS]MIIxxx ioctls */
2842 spin_lock_irqsave(&lp
->lock
, flags
);
2843 rc
= generic_mii_ioctl(&lp
->mii_if
, if_mii(rq
), cmd
, NULL
);
2844 spin_unlock_irqrestore(&lp
->lock
, flags
);
2852 static int pcnet32_check_otherphy(struct net_device
*dev
)
2854 struct pcnet32_private
*lp
= dev
->priv
;
2855 struct mii_if_info mii
= lp
->mii_if
;
2859 for (i
= 0; i
< PCNET32_MAX_PHYS
; i
++) {
2860 if (i
== lp
->mii_if
.phy_id
)
2861 continue; /* skip active phy */
2862 if (lp
->phymask
& (1 << i
)) {
2864 if (mii_link_ok(&mii
)) {
2865 /* found PHY with active link */
2866 if (netif_msg_link(lp
))
2868 "%s: Using PHY number %d.\n",
2871 /* isolate inactive phy */
2873 mdio_read(dev
, lp
->mii_if
.phy_id
, MII_BMCR
);
2874 mdio_write(dev
, lp
->mii_if
.phy_id
, MII_BMCR
,
2875 bmcr
| BMCR_ISOLATE
);
2877 /* de-isolate new phy */
2878 bmcr
= mdio_read(dev
, i
, MII_BMCR
);
2879 mdio_write(dev
, i
, MII_BMCR
,
2880 bmcr
& ~BMCR_ISOLATE
);
2882 /* set new phy address */
2883 lp
->mii_if
.phy_id
= i
;
2892 * Show the status of the media. Similar to mii_check_media however it
2893 * correctly shows the link speed for all (tested) pcnet32 variants.
2894 * Devices with no mii just report link state without speed.
2896 * Caller is assumed to hold and release the lp->lock.
2899 static void pcnet32_check_media(struct net_device
*dev
, int verbose
)
2901 struct pcnet32_private
*lp
= dev
->priv
;
2903 int prev_link
= netif_carrier_ok(dev
) ? 1 : 0;
2907 curr_link
= mii_link_ok(&lp
->mii_if
);
2909 ulong ioaddr
= dev
->base_addr
; /* card base I/O address */
2910 curr_link
= (lp
->a
.read_bcr(ioaddr
, 4) != 0xc0);
2913 if (prev_link
|| verbose
) {
2914 netif_carrier_off(dev
);
2915 if (netif_msg_link(lp
))
2916 printk(KERN_INFO
"%s: link down\n", dev
->name
);
2918 if (lp
->phycount
> 1) {
2919 curr_link
= pcnet32_check_otherphy(dev
);
2922 } else if (verbose
|| !prev_link
) {
2923 netif_carrier_on(dev
);
2925 if (netif_msg_link(lp
)) {
2926 struct ethtool_cmd ecmd
;
2927 mii_ethtool_gset(&lp
->mii_if
, &ecmd
);
2929 "%s: link up, %sMbps, %s-duplex\n",
2931 (ecmd
.speed
== SPEED_100
) ? "100" : "10",
2933 DUPLEX_FULL
) ? "full" : "half");
2935 bcr9
= lp
->a
.read_bcr(dev
->base_addr
, 9);
2936 if ((bcr9
& (1 << 0)) != lp
->mii_if
.full_duplex
) {
2937 if (lp
->mii_if
.full_duplex
)
2941 lp
->a
.write_bcr(dev
->base_addr
, 9, bcr9
);
2944 if (netif_msg_link(lp
))
2945 printk(KERN_INFO
"%s: link up\n", dev
->name
);
2951 * Check for loss of link and link establishment.
2952 * Can not use mii_check_media because it does nothing if mode is forced.
2955 static void pcnet32_watchdog(struct net_device
*dev
)
2957 struct pcnet32_private
*lp
= dev
->priv
;
2958 unsigned long flags
;
2960 /* Print the link status if it has changed */
2961 spin_lock_irqsave(&lp
->lock
, flags
);
2962 pcnet32_check_media(dev
, 0);
2963 spin_unlock_irqrestore(&lp
->lock
, flags
);
2965 mod_timer(&(lp
->watchdog_timer
), PCNET32_WATCHDOG_TIMEOUT
);
2968 static void __devexit
pcnet32_remove_one(struct pci_dev
*pdev
)
2970 struct net_device
*dev
= pci_get_drvdata(pdev
);
2973 struct pcnet32_private
*lp
= dev
->priv
;
2975 unregister_netdev(dev
);
2976 pcnet32_free_ring(dev
);
2977 release_region(dev
->base_addr
, PCNET32_TOTAL_SIZE
);
2978 pci_free_consistent(lp
->pci_dev
, sizeof(*lp
), lp
, lp
->dma_addr
);
2980 pci_disable_device(pdev
);
2981 pci_set_drvdata(pdev
, NULL
);
2985 static struct pci_driver pcnet32_driver
= {
2987 .probe
= pcnet32_probe_pci
,
2988 .remove
= __devexit_p(pcnet32_remove_one
),
2989 .id_table
= pcnet32_pci_tbl
,
2992 /* An additional parameter that may be passed in... */
2993 static int debug
= -1;
2994 static int tx_start_pt
= -1;
2995 static int pcnet32_have_pci
;
2997 module_param(debug
, int, 0);
2998 MODULE_PARM_DESC(debug
, DRV_NAME
" debug level");
2999 module_param(max_interrupt_work
, int, 0);
3000 MODULE_PARM_DESC(max_interrupt_work
,
3001 DRV_NAME
" maximum events handled per interrupt");
3002 module_param(rx_copybreak
, int, 0);
3003 MODULE_PARM_DESC(rx_copybreak
,
3004 DRV_NAME
" copy breakpoint for copy-only-tiny-frames");
3005 module_param(tx_start_pt
, int, 0);
3006 MODULE_PARM_DESC(tx_start_pt
, DRV_NAME
" transmit start point (0-3)");
3007 module_param(pcnet32vlb
, int, 0);
3008 MODULE_PARM_DESC(pcnet32vlb
, DRV_NAME
" Vesa local bus (VLB) support (0/1)");
3009 module_param_array(options
, int, NULL
, 0);
3010 MODULE_PARM_DESC(options
, DRV_NAME
" initial option setting(s) (0-15)");
3011 module_param_array(full_duplex
, int, NULL
, 0);
3012 MODULE_PARM_DESC(full_duplex
, DRV_NAME
" full duplex setting(s) (1)");
3013 /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
3014 module_param_array(homepna
, int, NULL
, 0);
3015 MODULE_PARM_DESC(homepna
,
3017 " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
3019 MODULE_AUTHOR("Thomas Bogendoerfer");
3020 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
3021 MODULE_LICENSE("GPL");
3023 #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
3025 static int __init
pcnet32_init_module(void)
3027 printk(KERN_INFO
"%s", version
);
3029 pcnet32_debug
= netif_msg_init(debug
, PCNET32_MSG_DEFAULT
);
3031 if ((tx_start_pt
>= 0) && (tx_start_pt
<= 3))
3032 tx_start
= tx_start_pt
;
3034 /* find the PCI devices */
3035 if (!pci_register_driver(&pcnet32_driver
))
3036 pcnet32_have_pci
= 1;
3038 /* should we find any remaining VLbus devices ? */
3040 pcnet32_probe_vlbus(pcnet32_portlist
);
3042 if (cards_found
&& (pcnet32_debug
& NETIF_MSG_PROBE
))
3043 printk(KERN_INFO PFX
"%d cards_found.\n", cards_found
);
3045 return (pcnet32_have_pci
+ cards_found
) ? 0 : -ENODEV
;
3048 static void __exit
pcnet32_cleanup_module(void)
3050 struct net_device
*next_dev
;
3052 while (pcnet32_dev
) {
3053 struct pcnet32_private
*lp
= pcnet32_dev
->priv
;
3054 next_dev
= lp
->next
;
3055 unregister_netdev(pcnet32_dev
);
3056 pcnet32_free_ring(pcnet32_dev
);
3057 release_region(pcnet32_dev
->base_addr
, PCNET32_TOTAL_SIZE
);
3058 pci_free_consistent(lp
->pci_dev
, sizeof(*lp
), lp
, lp
->dma_addr
);
3059 free_netdev(pcnet32_dev
);
3060 pcnet32_dev
= next_dev
;
3063 if (pcnet32_have_pci
)
3064 pci_unregister_driver(&pcnet32_driver
);
3067 module_init(pcnet32_init_module
);
3068 module_exit(pcnet32_cleanup_module
);