1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
3 * Copyright 1996-1999 Thomas Bogendoerfer
5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
7 * Copyright 1993 United States Government as represented by the
8 * Director, National Security Agency.
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
13 * This driver is for PCnet32 and PCnetPCI based ethercards
15 /**************************************************************************
17 * Fixed a few bugs, related to running the controller in 32bit mode.
19 * Carsten Langgaard, carstenl@mips.com
20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
22 *************************************************************************/
24 #define DRV_NAME "pcnet32"
25 #define DRV_VERSION "1.32"
26 #define DRV_RELDATE "18.Mar.2006"
27 #define PFX DRV_NAME ": "
29 static const char *const version
=
30 DRV_NAME
".c:v" DRV_VERSION
" " DRV_RELDATE
" tsbogend@alpha.franken.de\n";
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/string.h>
35 #include <linux/errno.h>
36 #include <linux/ioport.h>
37 #include <linux/slab.h>
38 #include <linux/interrupt.h>
39 #include <linux/pci.h>
40 #include <linux/delay.h>
41 #include <linux/init.h>
42 #include <linux/ethtool.h>
43 #include <linux/mii.h>
44 #include <linux/crc32.h>
45 #include <linux/netdevice.h>
46 #include <linux/etherdevice.h>
47 #include <linux/skbuff.h>
48 #include <linux/spinlock.h>
49 #include <linux/moduleparam.h>
50 #include <linux/bitops.h>
54 #include <asm/uaccess.h>
58 * PCI device identifiers for "new style" Linux PCI Device Drivers
60 static struct pci_device_id pcnet32_pci_tbl
[] = {
61 { PCI_DEVICE(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_LANCE_HOME
), },
62 { PCI_DEVICE(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_LANCE
), },
65 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
66 * the incorrect vendor id.
68 { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT
, PCI_DEVICE_ID_AMD_LANCE
),
69 .class = (PCI_CLASS_NETWORK_ETHERNET
<< 8), .class_mask
= 0xffff00, },
71 { } /* terminate list */
74 MODULE_DEVICE_TABLE(pci
, pcnet32_pci_tbl
);
76 static int cards_found
;
81 static unsigned int pcnet32_portlist
[] __initdata
=
82 { 0x300, 0x320, 0x340, 0x360, 0 };
84 static int pcnet32_debug
= 0;
85 static int tx_start
= 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
86 static int pcnet32vlb
; /* check for VLB cards ? */
88 static struct net_device
*pcnet32_dev
;
90 static int max_interrupt_work
= 2;
91 static int rx_copybreak
= 200;
93 #define PCNET32_PORT_AUI 0x00
94 #define PCNET32_PORT_10BT 0x01
95 #define PCNET32_PORT_GPSI 0x02
96 #define PCNET32_PORT_MII 0x03
98 #define PCNET32_PORT_PORTSEL 0x03
99 #define PCNET32_PORT_ASEL 0x04
100 #define PCNET32_PORT_100 0x40
101 #define PCNET32_PORT_FD 0x80
103 #define PCNET32_DMA_MASK 0xffffffff
105 #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
106 #define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4))
109 * table to translate option values from tulip
110 * to internal options
112 static const unsigned char options_mapping
[] = {
113 PCNET32_PORT_ASEL
, /* 0 Auto-select */
114 PCNET32_PORT_AUI
, /* 1 BNC/AUI */
115 PCNET32_PORT_AUI
, /* 2 AUI/BNC */
116 PCNET32_PORT_ASEL
, /* 3 not supported */
117 PCNET32_PORT_10BT
| PCNET32_PORT_FD
, /* 4 10baseT-FD */
118 PCNET32_PORT_ASEL
, /* 5 not supported */
119 PCNET32_PORT_ASEL
, /* 6 not supported */
120 PCNET32_PORT_ASEL
, /* 7 not supported */
121 PCNET32_PORT_ASEL
, /* 8 not supported */
122 PCNET32_PORT_MII
, /* 9 MII 10baseT */
123 PCNET32_PORT_MII
| PCNET32_PORT_FD
, /* 10 MII 10baseT-FD */
124 PCNET32_PORT_MII
, /* 11 MII (autosel) */
125 PCNET32_PORT_10BT
, /* 12 10BaseT */
126 PCNET32_PORT_MII
| PCNET32_PORT_100
, /* 13 MII 100BaseTx */
127 /* 14 MII 100BaseTx-FD */
128 PCNET32_PORT_MII
| PCNET32_PORT_100
| PCNET32_PORT_FD
,
129 PCNET32_PORT_ASEL
/* 15 not supported */
132 static const char pcnet32_gstrings_test
[][ETH_GSTRING_LEN
] = {
133 "Loopback test (offline)"
136 #define PCNET32_TEST_LEN (sizeof(pcnet32_gstrings_test) / ETH_GSTRING_LEN)
138 #define PCNET32_NUM_REGS 136
140 #define MAX_UNITS 8 /* More are supported, limit only on options */
141 static int options
[MAX_UNITS
];
142 static int full_duplex
[MAX_UNITS
];
143 static int homepna
[MAX_UNITS
];
146 * Theory of Operation
148 * This driver uses the same software structure as the normal lance
149 * driver. So look for a verbose description in lance.c. The differences
150 * to the normal lance driver is the use of the 32bit mode of PCnet32
151 * and PCnetPCI chips. Because these chips are 32bit chips, there is no
152 * 16MB limitation and we don't need bounce buffers.
156 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
157 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
158 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
160 #ifndef PCNET32_LOG_TX_BUFFERS
161 #define PCNET32_LOG_TX_BUFFERS 4
162 #define PCNET32_LOG_RX_BUFFERS 5
163 #define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */
164 #define PCNET32_LOG_MAX_RX_BUFFERS 9
167 #define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
168 #define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
170 #define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
171 #define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
173 #define PKT_BUF_SZ 1544
175 /* Offsets from base I/O address. */
176 #define PCNET32_WIO_RDP 0x10
177 #define PCNET32_WIO_RAP 0x12
178 #define PCNET32_WIO_RESET 0x14
179 #define PCNET32_WIO_BDP 0x16
181 #define PCNET32_DWIO_RDP 0x10
182 #define PCNET32_DWIO_RAP 0x14
183 #define PCNET32_DWIO_RESET 0x18
184 #define PCNET32_DWIO_BDP 0x1C
186 #define PCNET32_TOTAL_SIZE 0x20
189 #define CSR0_INIT 0x1
190 #define CSR0_START 0x2
191 #define CSR0_STOP 0x4
192 #define CSR0_TXPOLL 0x8
193 #define CSR0_INTEN 0x40
194 #define CSR0_IDON 0x0100
195 #define CSR0_NORMAL (CSR0_START | CSR0_INTEN)
196 #define PCNET32_INIT_LOW 1
197 #define PCNET32_INIT_HIGH 2
201 #define CSR5_SUSPEND 0x0001
203 #define PCNET32_MC_FILTER 8
205 #define PCNET32_79C970A 0x2621
207 /* The PCNET32 Rx and Tx ring descriptors. */
208 struct pcnet32_rx_head
{
210 s16 buf_length
; /* two`s complement of length */
216 struct pcnet32_tx_head
{
218 s16 length
; /* two`s complement of length */
224 /* The PCNET32 32-Bit initialization block, described in databook. */
225 struct pcnet32_init_block
{
231 /* Receive and transmit ring base, along with extra bits. */
236 /* PCnet32 access functions */
237 struct pcnet32_access
{
238 u16 (*read_csr
) (unsigned long, int);
239 void (*write_csr
) (unsigned long, int, u16
);
240 u16 (*read_bcr
) (unsigned long, int);
241 void (*write_bcr
) (unsigned long, int, u16
);
242 u16 (*read_rap
) (unsigned long);
243 void (*write_rap
) (unsigned long, u16
);
244 void (*reset
) (unsigned long);
248 * The first field of pcnet32_private is read by the ethernet device
249 * so the structure should be allocated using pci_alloc_consistent().
251 struct pcnet32_private
{
252 struct pcnet32_init_block init_block
;
253 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
254 struct pcnet32_rx_head
*rx_ring
;
255 struct pcnet32_tx_head
*tx_ring
;
256 dma_addr_t dma_addr
;/* DMA address of beginning of this
257 object, returned by pci_alloc_consistent */
258 struct pci_dev
*pci_dev
;
260 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
261 struct sk_buff
**tx_skbuff
;
262 struct sk_buff
**rx_skbuff
;
263 dma_addr_t
*tx_dma_addr
;
264 dma_addr_t
*rx_dma_addr
;
265 struct pcnet32_access a
;
266 spinlock_t lock
; /* Guard lock */
267 unsigned int cur_rx
, cur_tx
; /* The next free ring entry */
268 unsigned int rx_ring_size
; /* current rx ring size */
269 unsigned int tx_ring_size
; /* current tx ring size */
270 unsigned int rx_mod_mask
; /* rx ring modular mask */
271 unsigned int tx_mod_mask
; /* tx ring modular mask */
272 unsigned short rx_len_bits
;
273 unsigned short tx_len_bits
;
274 dma_addr_t rx_ring_dma_addr
;
275 dma_addr_t tx_ring_dma_addr
;
276 unsigned int dirty_rx
, /* ring entries to be freed. */
279 struct net_device_stats stats
;
281 char phycount
; /* number of phys found */
283 unsigned int shared_irq
:1, /* shared irq possible */
284 dxsuflo
:1, /* disable transmit stop on uflo */
285 mii
:1; /* mii port available */
286 struct net_device
*next
;
287 struct mii_if_info mii_if
;
288 struct timer_list watchdog_timer
;
289 struct timer_list blink_timer
;
290 u32 msg_enable
; /* debug message level */
292 /* each bit indicates an available PHY */
294 unsigned short chip_version
; /* which variant this is */
297 static int pcnet32_probe_pci(struct pci_dev
*, const struct pci_device_id
*);
298 static int pcnet32_probe1(unsigned long, int, struct pci_dev
*);
299 static int pcnet32_open(struct net_device
*);
300 static int pcnet32_init_ring(struct net_device
*);
301 static int pcnet32_start_xmit(struct sk_buff
*, struct net_device
*);
302 static int pcnet32_rx(struct net_device
*);
303 static void pcnet32_tx_timeout(struct net_device
*dev
);
304 static irqreturn_t
pcnet32_interrupt(int, void *, struct pt_regs
*);
305 static int pcnet32_close(struct net_device
*);
306 static struct net_device_stats
*pcnet32_get_stats(struct net_device
*);
307 static void pcnet32_load_multicast(struct net_device
*dev
);
308 static void pcnet32_set_multicast_list(struct net_device
*);
309 static int pcnet32_ioctl(struct net_device
*, struct ifreq
*, int);
310 static void pcnet32_watchdog(struct net_device
*);
311 static int mdio_read(struct net_device
*dev
, int phy_id
, int reg_num
);
312 static void mdio_write(struct net_device
*dev
, int phy_id
, int reg_num
,
314 static void pcnet32_restart(struct net_device
*dev
, unsigned int csr0_bits
);
315 static void pcnet32_ethtool_test(struct net_device
*dev
,
316 struct ethtool_test
*eth_test
, u64
* data
);
317 static int pcnet32_loopback_test(struct net_device
*dev
, uint64_t * data1
);
318 static int pcnet32_phys_id(struct net_device
*dev
, u32 data
);
319 static void pcnet32_led_blink_callback(struct net_device
*dev
);
320 static int pcnet32_get_regs_len(struct net_device
*dev
);
321 static void pcnet32_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
323 static void pcnet32_purge_tx_ring(struct net_device
*dev
);
324 static int pcnet32_alloc_ring(struct net_device
*dev
, char *name
);
325 static void pcnet32_free_ring(struct net_device
*dev
);
326 static void pcnet32_check_media(struct net_device
*dev
, int verbose
);
328 static u16
pcnet32_wio_read_csr(unsigned long addr
, int index
)
330 outw(index
, addr
+ PCNET32_WIO_RAP
);
331 return inw(addr
+ PCNET32_WIO_RDP
);
334 static void pcnet32_wio_write_csr(unsigned long addr
, int index
, u16 val
)
336 outw(index
, addr
+ PCNET32_WIO_RAP
);
337 outw(val
, addr
+ PCNET32_WIO_RDP
);
340 static u16
pcnet32_wio_read_bcr(unsigned long addr
, int index
)
342 outw(index
, addr
+ PCNET32_WIO_RAP
);
343 return inw(addr
+ PCNET32_WIO_BDP
);
346 static void pcnet32_wio_write_bcr(unsigned long addr
, int index
, u16 val
)
348 outw(index
, addr
+ PCNET32_WIO_RAP
);
349 outw(val
, addr
+ PCNET32_WIO_BDP
);
352 static u16
pcnet32_wio_read_rap(unsigned long addr
)
354 return inw(addr
+ PCNET32_WIO_RAP
);
357 static void pcnet32_wio_write_rap(unsigned long addr
, u16 val
)
359 outw(val
, addr
+ PCNET32_WIO_RAP
);
362 static void pcnet32_wio_reset(unsigned long addr
)
364 inw(addr
+ PCNET32_WIO_RESET
);
367 static int pcnet32_wio_check(unsigned long addr
)
369 outw(88, addr
+ PCNET32_WIO_RAP
);
370 return (inw(addr
+ PCNET32_WIO_RAP
) == 88);
373 static struct pcnet32_access pcnet32_wio
= {
374 .read_csr
= pcnet32_wio_read_csr
,
375 .write_csr
= pcnet32_wio_write_csr
,
376 .read_bcr
= pcnet32_wio_read_bcr
,
377 .write_bcr
= pcnet32_wio_write_bcr
,
378 .read_rap
= pcnet32_wio_read_rap
,
379 .write_rap
= pcnet32_wio_write_rap
,
380 .reset
= pcnet32_wio_reset
383 static u16
pcnet32_dwio_read_csr(unsigned long addr
, int index
)
385 outl(index
, addr
+ PCNET32_DWIO_RAP
);
386 return (inl(addr
+ PCNET32_DWIO_RDP
) & 0xffff);
389 static void pcnet32_dwio_write_csr(unsigned long addr
, int index
, u16 val
)
391 outl(index
, addr
+ PCNET32_DWIO_RAP
);
392 outl(val
, addr
+ PCNET32_DWIO_RDP
);
395 static u16
pcnet32_dwio_read_bcr(unsigned long addr
, int index
)
397 outl(index
, addr
+ PCNET32_DWIO_RAP
);
398 return (inl(addr
+ PCNET32_DWIO_BDP
) & 0xffff);
401 static void pcnet32_dwio_write_bcr(unsigned long addr
, int index
, u16 val
)
403 outl(index
, addr
+ PCNET32_DWIO_RAP
);
404 outl(val
, addr
+ PCNET32_DWIO_BDP
);
407 static u16
pcnet32_dwio_read_rap(unsigned long addr
)
409 return (inl(addr
+ PCNET32_DWIO_RAP
) & 0xffff);
412 static void pcnet32_dwio_write_rap(unsigned long addr
, u16 val
)
414 outl(val
, addr
+ PCNET32_DWIO_RAP
);
417 static void pcnet32_dwio_reset(unsigned long addr
)
419 inl(addr
+ PCNET32_DWIO_RESET
);
422 static int pcnet32_dwio_check(unsigned long addr
)
424 outl(88, addr
+ PCNET32_DWIO_RAP
);
425 return ((inl(addr
+ PCNET32_DWIO_RAP
) & 0xffff) == 88);
428 static struct pcnet32_access pcnet32_dwio
= {
429 .read_csr
= pcnet32_dwio_read_csr
,
430 .write_csr
= pcnet32_dwio_write_csr
,
431 .read_bcr
= pcnet32_dwio_read_bcr
,
432 .write_bcr
= pcnet32_dwio_write_bcr
,
433 .read_rap
= pcnet32_dwio_read_rap
,
434 .write_rap
= pcnet32_dwio_write_rap
,
435 .reset
= pcnet32_dwio_reset
438 static void pcnet32_netif_stop(struct net_device
*dev
)
440 dev
->trans_start
= jiffies
;
441 netif_poll_disable(dev
);
442 netif_tx_disable(dev
);
445 static void pcnet32_netif_start(struct net_device
*dev
)
447 netif_wake_queue(dev
);
448 netif_poll_enable(dev
);
452 * Allocate space for the new sized tx ring.
454 * Save new resources.
455 * Any failure keeps old resources.
456 * Must be called with lp->lock held.
458 static void pcnet32_realloc_tx_ring(struct net_device
*dev
,
459 struct pcnet32_private
*lp
,
462 dma_addr_t new_ring_dma_addr
;
463 dma_addr_t
*new_dma_addr_list
;
464 struct pcnet32_tx_head
*new_tx_ring
;
465 struct sk_buff
**new_skb_list
;
467 pcnet32_purge_tx_ring(dev
);
469 new_tx_ring
= pci_alloc_consistent(lp
->pci_dev
,
470 sizeof(struct pcnet32_tx_head
) *
473 if (new_tx_ring
== NULL
) {
474 if (netif_msg_drv(lp
))
476 "%s: Consistent memory allocation failed.\n",
480 memset(new_tx_ring
, 0, sizeof(struct pcnet32_tx_head
) * (1 << size
));
482 new_dma_addr_list
= kcalloc((1 << size
), sizeof(dma_addr_t
),
484 if (!new_dma_addr_list
) {
485 if (netif_msg_drv(lp
))
487 "%s: Memory allocation failed.\n", dev
->name
);
488 goto free_new_tx_ring
;
491 new_skb_list
= kcalloc((1 << size
), sizeof(struct sk_buff
*),
494 if (netif_msg_drv(lp
))
496 "%s: Memory allocation failed.\n", dev
->name
);
500 kfree(lp
->tx_skbuff
);
501 kfree(lp
->tx_dma_addr
);
502 pci_free_consistent(lp
->pci_dev
,
503 sizeof(struct pcnet32_tx_head
) *
504 lp
->tx_ring_size
, lp
->tx_ring
,
505 lp
->tx_ring_dma_addr
);
507 lp
->tx_ring_size
= (1 << size
);
508 lp
->tx_mod_mask
= lp
->tx_ring_size
- 1;
509 lp
->tx_len_bits
= (size
<< 12);
510 lp
->tx_ring
= new_tx_ring
;
511 lp
->tx_ring_dma_addr
= new_ring_dma_addr
;
512 lp
->tx_dma_addr
= new_dma_addr_list
;
513 lp
->tx_skbuff
= new_skb_list
;
517 kfree(new_dma_addr_list
);
519 pci_free_consistent(lp
->pci_dev
,
520 sizeof(struct pcnet32_tx_head
) *
528 * Allocate space for the new sized rx ring.
529 * Re-use old receive buffers.
530 * alloc extra buffers
531 * free unneeded buffers
532 * free unneeded buffers
533 * Save new resources.
534 * Any failure keeps old resources.
535 * Must be called with lp->lock held.
537 static void pcnet32_realloc_rx_ring(struct net_device
*dev
,
538 struct pcnet32_private
*lp
,
541 dma_addr_t new_ring_dma_addr
;
542 dma_addr_t
*new_dma_addr_list
;
543 struct pcnet32_rx_head
*new_rx_ring
;
544 struct sk_buff
**new_skb_list
;
547 new_rx_ring
= pci_alloc_consistent(lp
->pci_dev
,
548 sizeof(struct pcnet32_rx_head
) *
551 if (new_rx_ring
== NULL
) {
552 if (netif_msg_drv(lp
))
554 "%s: Consistent memory allocation failed.\n",
558 memset(new_rx_ring
, 0, sizeof(struct pcnet32_rx_head
) * (1 << size
));
560 new_dma_addr_list
= kcalloc((1 << size
), sizeof(dma_addr_t
),
562 if (!new_dma_addr_list
) {
563 if (netif_msg_drv(lp
))
565 "%s: Memory allocation failed.\n", dev
->name
);
566 goto free_new_rx_ring
;
569 new_skb_list
= kcalloc((1 << size
), sizeof(struct sk_buff
*),
572 if (netif_msg_drv(lp
))
574 "%s: Memory allocation failed.\n", dev
->name
);
578 /* first copy the current receive buffers */
579 overlap
= min(size
, lp
->rx_ring_size
);
580 for (new = 0; new < overlap
; new++) {
581 new_rx_ring
[new] = lp
->rx_ring
[new];
582 new_dma_addr_list
[new] = lp
->rx_dma_addr
[new];
583 new_skb_list
[new] = lp
->rx_skbuff
[new];
585 /* now allocate any new buffers needed */
586 for (; new < size
; new++ ) {
587 struct sk_buff
*rx_skbuff
;
588 new_skb_list
[new] = dev_alloc_skb(PKT_BUF_SZ
);
589 if (!(rx_skbuff
= new_skb_list
[new])) {
590 /* keep the original lists and buffers */
591 if (netif_msg_drv(lp
))
593 "%s: pcnet32_realloc_rx_ring dev_alloc_skb failed.\n",
597 skb_reserve(rx_skbuff
, 2);
599 new_dma_addr_list
[new] =
600 pci_map_single(lp
->pci_dev
, rx_skbuff
->data
,
601 PKT_BUF_SZ
- 2, PCI_DMA_FROMDEVICE
);
602 new_rx_ring
[new].base
= (u32
) le32_to_cpu(new_dma_addr_list
[new]);
603 new_rx_ring
[new].buf_length
= le16_to_cpu(2 - PKT_BUF_SZ
);
604 new_rx_ring
[new].status
= le16_to_cpu(0x8000);
606 /* and free any unneeded buffers */
607 for (; new < lp
->rx_ring_size
; new++) {
608 if (lp
->rx_skbuff
[new]) {
609 pci_unmap_single(lp
->pci_dev
, lp
->rx_dma_addr
[new],
610 PKT_BUF_SZ
- 2, PCI_DMA_FROMDEVICE
);
611 dev_kfree_skb(lp
->rx_skbuff
[new]);
615 kfree(lp
->rx_skbuff
);
616 kfree(lp
->rx_dma_addr
);
617 pci_free_consistent(lp
->pci_dev
,
618 sizeof(struct pcnet32_rx_head
) *
619 lp
->rx_ring_size
, lp
->rx_ring
,
620 lp
->rx_ring_dma_addr
);
622 lp
->rx_ring_size
= (1 << size
);
623 lp
->rx_mod_mask
= lp
->rx_ring_size
- 1;
624 lp
->rx_len_bits
= (size
<< 4);
625 lp
->rx_ring
= new_rx_ring
;
626 lp
->rx_ring_dma_addr
= new_ring_dma_addr
;
627 lp
->rx_dma_addr
= new_dma_addr_list
;
628 lp
->rx_skbuff
= new_skb_list
;
632 for (; --new >= lp
->rx_ring_size
; ) {
633 if (new_skb_list
[new]) {
634 pci_unmap_single(lp
->pci_dev
, new_dma_addr_list
[new],
635 PKT_BUF_SZ
- 2, PCI_DMA_FROMDEVICE
);
636 dev_kfree_skb(new_skb_list
[new]);
641 kfree(new_dma_addr_list
);
643 pci_free_consistent(lp
->pci_dev
,
644 sizeof(struct pcnet32_rx_head
) *
651 static void pcnet32_purge_rx_ring(struct net_device
*dev
)
653 struct pcnet32_private
*lp
= dev
->priv
;
656 /* free all allocated skbuffs */
657 for (i
= 0; i
< lp
->rx_ring_size
; i
++) {
658 lp
->rx_ring
[i
].status
= 0; /* CPU owns buffer */
659 wmb(); /* Make sure adapter sees owner change */
660 if (lp
->rx_skbuff
[i
]) {
661 pci_unmap_single(lp
->pci_dev
, lp
->rx_dma_addr
[i
],
662 PKT_BUF_SZ
- 2, PCI_DMA_FROMDEVICE
);
663 dev_kfree_skb_any(lp
->rx_skbuff
[i
]);
665 lp
->rx_skbuff
[i
] = NULL
;
666 lp
->rx_dma_addr
[i
] = 0;
670 #ifdef CONFIG_NET_POLL_CONTROLLER
671 static void pcnet32_poll_controller(struct net_device
*dev
)
673 disable_irq(dev
->irq
);
674 pcnet32_interrupt(0, dev
, NULL
);
675 enable_irq(dev
->irq
);
679 static int pcnet32_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
681 struct pcnet32_private
*lp
= dev
->priv
;
686 spin_lock_irqsave(&lp
->lock
, flags
);
687 mii_ethtool_gset(&lp
->mii_if
, cmd
);
688 spin_unlock_irqrestore(&lp
->lock
, flags
);
694 static int pcnet32_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
696 struct pcnet32_private
*lp
= dev
->priv
;
701 spin_lock_irqsave(&lp
->lock
, flags
);
702 r
= mii_ethtool_sset(&lp
->mii_if
, cmd
);
703 spin_unlock_irqrestore(&lp
->lock
, flags
);
708 static void pcnet32_get_drvinfo(struct net_device
*dev
,
709 struct ethtool_drvinfo
*info
)
711 struct pcnet32_private
*lp
= dev
->priv
;
713 strcpy(info
->driver
, DRV_NAME
);
714 strcpy(info
->version
, DRV_VERSION
);
716 strcpy(info
->bus_info
, pci_name(lp
->pci_dev
));
718 sprintf(info
->bus_info
, "VLB 0x%lx", dev
->base_addr
);
721 static u32
pcnet32_get_link(struct net_device
*dev
)
723 struct pcnet32_private
*lp
= dev
->priv
;
727 spin_lock_irqsave(&lp
->lock
, flags
);
729 r
= mii_link_ok(&lp
->mii_if
);
730 } else if (lp
->chip_version
>= PCNET32_79C970A
) {
731 ulong ioaddr
= dev
->base_addr
; /* card base I/O address */
732 r
= (lp
->a
.read_bcr(ioaddr
, 4) != 0xc0);
733 } else { /* can not detect link on really old chips */
736 spin_unlock_irqrestore(&lp
->lock
, flags
);
741 static u32
pcnet32_get_msglevel(struct net_device
*dev
)
743 struct pcnet32_private
*lp
= dev
->priv
;
744 return lp
->msg_enable
;
747 static void pcnet32_set_msglevel(struct net_device
*dev
, u32 value
)
749 struct pcnet32_private
*lp
= dev
->priv
;
750 lp
->msg_enable
= value
;
753 static int pcnet32_nway_reset(struct net_device
*dev
)
755 struct pcnet32_private
*lp
= dev
->priv
;
760 spin_lock_irqsave(&lp
->lock
, flags
);
761 r
= mii_nway_restart(&lp
->mii_if
);
762 spin_unlock_irqrestore(&lp
->lock
, flags
);
767 static void pcnet32_get_ringparam(struct net_device
*dev
,
768 struct ethtool_ringparam
*ering
)
770 struct pcnet32_private
*lp
= dev
->priv
;
772 ering
->tx_max_pending
= TX_MAX_RING_SIZE
;
773 ering
->tx_pending
= lp
->tx_ring_size
;
774 ering
->rx_max_pending
= RX_MAX_RING_SIZE
;
775 ering
->rx_pending
= lp
->rx_ring_size
;
778 static int pcnet32_set_ringparam(struct net_device
*dev
,
779 struct ethtool_ringparam
*ering
)
781 struct pcnet32_private
*lp
= dev
->priv
;
784 ulong ioaddr
= dev
->base_addr
;
787 if (ering
->rx_mini_pending
|| ering
->rx_jumbo_pending
)
790 if (netif_running(dev
))
791 pcnet32_netif_stop(dev
);
793 spin_lock_irqsave(&lp
->lock
, flags
);
794 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_STOP
); /* stop the chip */
796 size
= min(ering
->tx_pending
, (unsigned int)TX_MAX_RING_SIZE
);
798 /* set the minimum ring size to 4, to allow the loopback test to work
801 for (i
= 2; i
<= PCNET32_LOG_MAX_TX_BUFFERS
; i
++) {
802 if (size
<= (1 << i
))
805 if ((1 << i
) != lp
->tx_ring_size
)
806 pcnet32_realloc_tx_ring(dev
, lp
, i
);
808 size
= min(ering
->rx_pending
, (unsigned int)RX_MAX_RING_SIZE
);
809 for (i
= 2; i
<= PCNET32_LOG_MAX_RX_BUFFERS
; i
++) {
810 if (size
<= (1 << i
))
813 if ((1 << i
) != lp
->rx_ring_size
)
814 pcnet32_realloc_rx_ring(dev
, lp
, i
);
816 dev
->weight
= lp
->rx_ring_size
/ 2;
818 if (netif_running(dev
)) {
819 pcnet32_netif_start(dev
);
820 pcnet32_restart(dev
, CSR0_NORMAL
);
823 spin_unlock_irqrestore(&lp
->lock
, flags
);
825 if (netif_msg_drv(lp
))
827 "%s: Ring Param Settings: RX: %d, TX: %d\n", dev
->name
,
828 lp
->rx_ring_size
, lp
->tx_ring_size
);
833 static void pcnet32_get_strings(struct net_device
*dev
, u32 stringset
,
836 memcpy(data
, pcnet32_gstrings_test
, sizeof(pcnet32_gstrings_test
));
839 static int pcnet32_self_test_count(struct net_device
*dev
)
841 return PCNET32_TEST_LEN
;
844 static void pcnet32_ethtool_test(struct net_device
*dev
,
845 struct ethtool_test
*test
, u64
* data
)
847 struct pcnet32_private
*lp
= dev
->priv
;
850 if (test
->flags
== ETH_TEST_FL_OFFLINE
) {
851 rc
= pcnet32_loopback_test(dev
, data
);
853 if (netif_msg_hw(lp
))
854 printk(KERN_DEBUG
"%s: Loopback test failed.\n",
856 test
->flags
|= ETH_TEST_FL_FAILED
;
857 } else if (netif_msg_hw(lp
))
858 printk(KERN_DEBUG
"%s: Loopback test passed.\n",
860 } else if (netif_msg_hw(lp
))
862 "%s: No tests to run (specify 'Offline' on ethtool).",
864 } /* end pcnet32_ethtool_test */
866 static int pcnet32_loopback_test(struct net_device
*dev
, uint64_t * data1
)
868 struct pcnet32_private
*lp
= dev
->priv
;
869 struct pcnet32_access
*a
= &lp
->a
; /* access to registers */
870 ulong ioaddr
= dev
->base_addr
; /* card base I/O address */
871 struct sk_buff
*skb
; /* sk buff */
872 int x
, i
; /* counters */
873 int numbuffs
= 4; /* number of TX/RX buffers and descs */
874 u16 status
= 0x8300; /* TX ring status */
875 u16 teststatus
; /* test of ring status */
876 int rc
; /* return code */
877 int size
; /* size of packets */
878 unsigned char *packet
; /* source packet data */
879 static const int data_len
= 60; /* length of source packets */
883 rc
= 1; /* default to fail */
885 if (netif_running(dev
))
888 spin_lock_irqsave(&lp
->lock
, flags
);
889 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_STOP
); /* stop the chip */
891 numbuffs
= min(numbuffs
, (int)min(lp
->rx_ring_size
, lp
->tx_ring_size
));
893 /* Reset the PCNET32 */
895 lp
->a
.write_csr(ioaddr
, CSR4
, 0x0915); /* auto tx pad */
897 /* switch pcnet32 to 32bit mode */
898 lp
->a
.write_bcr(ioaddr
, 20, 2);
900 /* purge & init rings but don't actually restart */
901 pcnet32_restart(dev
, 0x0000);
903 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_STOP
); /* Set STOP bit */
905 /* Initialize Transmit buffers. */
906 size
= data_len
+ 15;
907 for (x
= 0; x
< numbuffs
; x
++) {
908 if (!(skb
= dev_alloc_skb(size
))) {
909 if (netif_msg_hw(lp
))
911 "%s: Cannot allocate skb at line: %d!\n",
912 dev
->name
, __LINE__
);
916 skb_put(skb
, size
); /* create space for data */
917 lp
->tx_skbuff
[x
] = skb
;
918 lp
->tx_ring
[x
].length
= le16_to_cpu(-skb
->len
);
919 lp
->tx_ring
[x
].misc
= 0;
921 /* put DA and SA into the skb */
922 for (i
= 0; i
< 6; i
++)
923 *packet
++ = dev
->dev_addr
[i
];
924 for (i
= 0; i
< 6; i
++)
925 *packet
++ = dev
->dev_addr
[i
];
931 /* fill packet with data */
932 for (i
= 0; i
< data_len
; i
++)
936 pci_map_single(lp
->pci_dev
, skb
->data
, skb
->len
,
938 lp
->tx_ring
[x
].base
=
939 (u32
) le32_to_cpu(lp
->tx_dma_addr
[x
]);
940 wmb(); /* Make sure owner changes after all others are visible */
941 lp
->tx_ring
[x
].status
= le16_to_cpu(status
);
945 x
= a
->read_bcr(ioaddr
, 32); /* set internal loopback in BCR32 */
946 a
->write_bcr(ioaddr
, 32, x
| 0x0002);
948 /* set int loopback in CSR15 */
949 x
= a
->read_csr(ioaddr
, CSR15
) & 0xfffc;
950 lp
->a
.write_csr(ioaddr
, CSR15
, x
| 0x0044);
952 teststatus
= le16_to_cpu(0x8000);
953 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_START
); /* Set STRT bit */
955 /* Check status of descriptors */
956 for (x
= 0; x
< numbuffs
; x
++) {
959 while ((lp
->rx_ring
[x
].status
& teststatus
) && (ticks
< 200)) {
960 spin_unlock_irqrestore(&lp
->lock
, flags
);
962 spin_lock_irqsave(&lp
->lock
, flags
);
967 if (netif_msg_hw(lp
))
968 printk("%s: Desc %d failed to reset!\n",
974 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_STOP
); /* Set STOP bit */
976 if (netif_msg_hw(lp
) && netif_msg_pktdata(lp
)) {
977 printk(KERN_DEBUG
"%s: RX loopback packets:\n", dev
->name
);
979 for (x
= 0; x
< numbuffs
; x
++) {
980 printk(KERN_DEBUG
"%s: Packet %d:\n", dev
->name
, x
);
981 skb
= lp
->rx_skbuff
[x
];
982 for (i
= 0; i
< size
; i
++) {
983 printk("%02x ", *(skb
->data
+ i
));
991 while (x
< numbuffs
&& !rc
) {
992 skb
= lp
->rx_skbuff
[x
];
993 packet
= lp
->tx_skbuff
[x
]->data
;
994 for (i
= 0; i
< size
; i
++) {
995 if (*(skb
->data
+ i
) != packet
[i
]) {
996 if (netif_msg_hw(lp
))
998 "%s: Error in compare! %2x - %02x %02x\n",
999 dev
->name
, i
, *(skb
->data
+ i
),
1010 pcnet32_purge_tx_ring(dev
);
1012 x
= a
->read_csr(ioaddr
, CSR15
);
1013 a
->write_csr(ioaddr
, CSR15
, (x
& ~0x0044)); /* reset bits 6 and 2 */
1015 x
= a
->read_bcr(ioaddr
, 32); /* reset internal loopback */
1016 a
->write_bcr(ioaddr
, 32, (x
& ~0x0002));
1018 if (netif_running(dev
)) {
1019 spin_unlock_irqrestore(&lp
->lock
, flags
);
1022 pcnet32_purge_rx_ring(dev
);
1023 lp
->a
.write_bcr(ioaddr
, 20, 4); /* return to 16bit mode */
1024 spin_unlock_irqrestore(&lp
->lock
, flags
);
1028 } /* end pcnet32_loopback_test */
1030 static void pcnet32_led_blink_callback(struct net_device
*dev
)
1032 struct pcnet32_private
*lp
= dev
->priv
;
1033 struct pcnet32_access
*a
= &lp
->a
;
1034 ulong ioaddr
= dev
->base_addr
;
1035 unsigned long flags
;
1038 spin_lock_irqsave(&lp
->lock
, flags
);
1039 for (i
= 4; i
< 8; i
++) {
1040 a
->write_bcr(ioaddr
, i
, a
->read_bcr(ioaddr
, i
) ^ 0x4000);
1042 spin_unlock_irqrestore(&lp
->lock
, flags
);
1044 mod_timer(&lp
->blink_timer
, PCNET32_BLINK_TIMEOUT
);
1047 static int pcnet32_phys_id(struct net_device
*dev
, u32 data
)
1049 struct pcnet32_private
*lp
= dev
->priv
;
1050 struct pcnet32_access
*a
= &lp
->a
;
1051 ulong ioaddr
= dev
->base_addr
;
1052 unsigned long flags
;
1055 if (!lp
->blink_timer
.function
) {
1056 init_timer(&lp
->blink_timer
);
1057 lp
->blink_timer
.function
= (void *)pcnet32_led_blink_callback
;
1058 lp
->blink_timer
.data
= (unsigned long)dev
;
1061 /* Save the current value of the bcrs */
1062 spin_lock_irqsave(&lp
->lock
, flags
);
1063 for (i
= 4; i
< 8; i
++) {
1064 regs
[i
- 4] = a
->read_bcr(ioaddr
, i
);
1066 spin_unlock_irqrestore(&lp
->lock
, flags
);
1068 mod_timer(&lp
->blink_timer
, jiffies
);
1069 set_current_state(TASK_INTERRUPTIBLE
);
1071 if ((!data
) || (data
> (u32
) (MAX_SCHEDULE_TIMEOUT
/ HZ
)))
1072 data
= (u32
) (MAX_SCHEDULE_TIMEOUT
/ HZ
);
1074 msleep_interruptible(data
* 1000);
1075 del_timer_sync(&lp
->blink_timer
);
1077 /* Restore the original value of the bcrs */
1078 spin_lock_irqsave(&lp
->lock
, flags
);
1079 for (i
= 4; i
< 8; i
++) {
1080 a
->write_bcr(ioaddr
, i
, regs
[i
- 4]);
1082 spin_unlock_irqrestore(&lp
->lock
, flags
);
1088 * lp->lock must be held.
1090 static int pcnet32_suspend(struct net_device
*dev
, unsigned long *flags
,
1094 struct pcnet32_private
*lp
= dev
->priv
;
1095 struct pcnet32_access
*a
= &lp
->a
;
1096 ulong ioaddr
= dev
->base_addr
;
1099 /* really old chips have to be stopped. */
1100 if (lp
->chip_version
< PCNET32_79C970A
)
1103 /* set SUSPEND (SPND) - CSR5 bit 0 */
1104 csr5
= a
->read_csr(ioaddr
, CSR5
);
1105 a
->write_csr(ioaddr
, CSR5
, csr5
| CSR5_SUSPEND
);
1107 /* poll waiting for bit to be set */
1109 while (!(a
->read_csr(ioaddr
, CSR5
) & CSR5_SUSPEND
)) {
1110 spin_unlock_irqrestore(&lp
->lock
, *flags
);
1115 spin_lock_irqsave(&lp
->lock
, *flags
);
1118 if (netif_msg_hw(lp
))
1120 "%s: Error getting into suspend!\n",
1128 #define PCNET32_REGS_PER_PHY 32
1129 #define PCNET32_MAX_PHYS 32
1130 static int pcnet32_get_regs_len(struct net_device
*dev
)
1132 struct pcnet32_private
*lp
= dev
->priv
;
1133 int j
= lp
->phycount
* PCNET32_REGS_PER_PHY
;
1135 return ((PCNET32_NUM_REGS
+ j
) * sizeof(u16
));
1138 static void pcnet32_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1143 struct pcnet32_private
*lp
= dev
->priv
;
1144 struct pcnet32_access
*a
= &lp
->a
;
1145 ulong ioaddr
= dev
->base_addr
;
1146 unsigned long flags
;
1148 spin_lock_irqsave(&lp
->lock
, flags
);
1150 csr0
= a
->read_csr(ioaddr
, CSR0
);
1151 if (!(csr0
& CSR0_STOP
)) /* If not stopped */
1152 pcnet32_suspend(dev
, &flags
, 1);
1154 /* read address PROM */
1155 for (i
= 0; i
< 16; i
+= 2)
1156 *buff
++ = inw(ioaddr
+ i
);
1158 /* read control and status registers */
1159 for (i
= 0; i
< 90; i
++) {
1160 *buff
++ = a
->read_csr(ioaddr
, i
);
1163 *buff
++ = a
->read_csr(ioaddr
, 112);
1164 *buff
++ = a
->read_csr(ioaddr
, 114);
1166 /* read bus configuration registers */
1167 for (i
= 0; i
< 30; i
++) {
1168 *buff
++ = a
->read_bcr(ioaddr
, i
);
1170 *buff
++ = 0; /* skip bcr30 so as not to hang 79C976 */
1171 for (i
= 31; i
< 36; i
++) {
1172 *buff
++ = a
->read_bcr(ioaddr
, i
);
1175 /* read mii phy registers */
1178 for (j
= 0; j
< PCNET32_MAX_PHYS
; j
++) {
1179 if (lp
->phymask
& (1 << j
)) {
1180 for (i
= 0; i
< PCNET32_REGS_PER_PHY
; i
++) {
1181 lp
->a
.write_bcr(ioaddr
, 33,
1183 *buff
++ = lp
->a
.read_bcr(ioaddr
, 34);
1189 if (!(csr0
& CSR0_STOP
)) { /* If not stopped */
1192 /* clear SUSPEND (SPND) - CSR5 bit 0 */
1193 csr5
= a
->read_csr(ioaddr
, CSR5
);
1194 a
->write_csr(ioaddr
, CSR5
, csr5
& (~CSR5_SUSPEND
));
1197 spin_unlock_irqrestore(&lp
->lock
, flags
);
1200 static struct ethtool_ops pcnet32_ethtool_ops
= {
1201 .get_settings
= pcnet32_get_settings
,
1202 .set_settings
= pcnet32_set_settings
,
1203 .get_drvinfo
= pcnet32_get_drvinfo
,
1204 .get_msglevel
= pcnet32_get_msglevel
,
1205 .set_msglevel
= pcnet32_set_msglevel
,
1206 .nway_reset
= pcnet32_nway_reset
,
1207 .get_link
= pcnet32_get_link
,
1208 .get_ringparam
= pcnet32_get_ringparam
,
1209 .set_ringparam
= pcnet32_set_ringparam
,
1210 .get_tx_csum
= ethtool_op_get_tx_csum
,
1211 .get_sg
= ethtool_op_get_sg
,
1212 .get_tso
= ethtool_op_get_tso
,
1213 .get_strings
= pcnet32_get_strings
,
1214 .self_test_count
= pcnet32_self_test_count
,
1215 .self_test
= pcnet32_ethtool_test
,
1216 .phys_id
= pcnet32_phys_id
,
1217 .get_regs_len
= pcnet32_get_regs_len
,
1218 .get_regs
= pcnet32_get_regs
,
1219 .get_perm_addr
= ethtool_op_get_perm_addr
,
1222 /* only probes for non-PCI devices, the rest are handled by
1223 * pci_register_driver via pcnet32_probe_pci */
1225 static void __devinit
pcnet32_probe_vlbus(unsigned int *pcnet32_portlist
)
1227 unsigned int *port
, ioaddr
;
1229 /* search for PCnet32 VLB cards at known addresses */
1230 for (port
= pcnet32_portlist
; (ioaddr
= *port
); port
++) {
1232 (ioaddr
, PCNET32_TOTAL_SIZE
, "pcnet32_probe_vlbus")) {
1233 /* check if there is really a pcnet chip on that ioaddr */
1234 if ((inb(ioaddr
+ 14) == 0x57)
1235 && (inb(ioaddr
+ 15) == 0x57)) {
1236 pcnet32_probe1(ioaddr
, 0, NULL
);
1238 release_region(ioaddr
, PCNET32_TOTAL_SIZE
);
1244 static int __devinit
1245 pcnet32_probe_pci(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1247 unsigned long ioaddr
;
1250 err
= pci_enable_device(pdev
);
1252 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1254 "failed to enable device -- err=%d\n", err
);
1257 pci_set_master(pdev
);
1259 ioaddr
= pci_resource_start(pdev
, 0);
1261 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1263 "card has no PCI IO resources, aborting\n");
1267 if (!pci_dma_supported(pdev
, PCNET32_DMA_MASK
)) {
1268 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1270 "architecture does not support 32bit PCI busmaster DMA\n");
1273 if (request_region(ioaddr
, PCNET32_TOTAL_SIZE
, "pcnet32_probe_pci") ==
1275 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1277 "io address range already allocated\n");
1281 err
= pcnet32_probe1(ioaddr
, 1, pdev
);
1283 pci_disable_device(pdev
);
1289 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1290 * pdev will be NULL when called from pcnet32_probe_vlbus.
1292 static int __devinit
1293 pcnet32_probe1(unsigned long ioaddr
, int shared
, struct pci_dev
*pdev
)
1295 struct pcnet32_private
*lp
;
1296 dma_addr_t lp_dma_addr
;
1298 int fdx
, mii
, fset
, dxsuflo
;
1301 struct net_device
*dev
;
1302 struct pcnet32_access
*a
= NULL
;
1306 /* reset the chip */
1307 pcnet32_wio_reset(ioaddr
);
1309 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1310 if (pcnet32_wio_read_csr(ioaddr
, 0) == 4 && pcnet32_wio_check(ioaddr
)) {
1313 pcnet32_dwio_reset(ioaddr
);
1314 if (pcnet32_dwio_read_csr(ioaddr
, 0) == 4
1315 && pcnet32_dwio_check(ioaddr
)) {
1318 goto err_release_region
;
1322 a
->read_csr(ioaddr
, 88) | (a
->read_csr(ioaddr
, 89) << 16);
1323 if ((pcnet32_debug
& NETIF_MSG_PROBE
) && (pcnet32_debug
& NETIF_MSG_HW
))
1324 printk(KERN_INFO
" PCnet chip version is %#x.\n",
1326 if ((chip_version
& 0xfff) != 0x003) {
1327 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1328 printk(KERN_INFO PFX
"Unsupported chip version.\n");
1329 goto err_release_region
;
1332 /* initialize variables */
1333 fdx
= mii
= fset
= dxsuflo
= 0;
1334 chip_version
= (chip_version
>> 12) & 0xffff;
1336 switch (chip_version
) {
1338 chipname
= "PCnet/PCI 79C970"; /* PCI */
1342 chipname
= "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
1344 chipname
= "PCnet/32 79C965"; /* 486/VL bus */
1347 chipname
= "PCnet/PCI II 79C970A"; /* PCI */
1351 chipname
= "PCnet/FAST 79C971"; /* PCI */
1357 chipname
= "PCnet/FAST+ 79C972"; /* PCI */
1363 chipname
= "PCnet/FAST III 79C973"; /* PCI */
1368 chipname
= "PCnet/Home 79C978"; /* PCI */
1371 * This is based on specs published at www.amd.com. This section
1372 * assumes that a card with a 79C978 wants to go into standard
1373 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode,
1374 * and the module option homepna=1 can select this instead.
1376 media
= a
->read_bcr(ioaddr
, 49);
1377 media
&= ~3; /* default to 10Mb ethernet */
1378 if (cards_found
< MAX_UNITS
&& homepna
[cards_found
])
1379 media
|= 1; /* switch to home wiring mode */
1380 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1381 printk(KERN_DEBUG PFX
"media set to %sMbit mode.\n",
1382 (media
& 1) ? "1" : "10");
1383 a
->write_bcr(ioaddr
, 49, media
);
1386 chipname
= "PCnet/FAST III 79C975"; /* PCI */
1391 chipname
= "PCnet/PRO 79C976";
1396 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1397 printk(KERN_INFO PFX
1398 "PCnet version %#x, no PCnet32 chip.\n",
1400 goto err_release_region
;
1404 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1405 * starting until the packet is loaded. Strike one for reliability, lose
1406 * one for latency - although on PCI this isnt a big loss. Older chips
1407 * have FIFO's smaller than a packet, so you can't do this.
1408 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1412 a
->write_bcr(ioaddr
, 18, (a
->read_bcr(ioaddr
, 18) | 0x0860));
1413 a
->write_csr(ioaddr
, 80,
1414 (a
->read_csr(ioaddr
, 80) & 0x0C00) | 0x0c00);
1418 dev
= alloc_etherdev(0);
1420 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1421 printk(KERN_ERR PFX
"Memory allocation failed.\n");
1423 goto err_release_region
;
1425 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1427 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1428 printk(KERN_INFO PFX
"%s at %#3lx,", chipname
, ioaddr
);
1430 /* In most chips, after a chip reset, the ethernet address is read from the
1431 * station address PROM at the base address and programmed into the
1432 * "Physical Address Registers" CSR12-14.
1433 * As a precautionary measure, we read the PROM values and complain if
1434 * they disagree with the CSRs. If they miscompare, and the PROM addr
1435 * is valid, then the PROM addr is used.
1437 for (i
= 0; i
< 3; i
++) {
1439 val
= a
->read_csr(ioaddr
, i
+ 12) & 0x0ffff;
1440 /* There may be endianness issues here. */
1441 dev
->dev_addr
[2 * i
] = val
& 0x0ff;
1442 dev
->dev_addr
[2 * i
+ 1] = (val
>> 8) & 0x0ff;
1445 /* read PROM address and compare with CSR address */
1446 for (i
= 0; i
< 6; i
++)
1447 promaddr
[i
] = inb(ioaddr
+ i
);
1449 if (memcmp(promaddr
, dev
->dev_addr
, 6)
1450 || !is_valid_ether_addr(dev
->dev_addr
)) {
1451 if (is_valid_ether_addr(promaddr
)) {
1452 if (pcnet32_debug
& NETIF_MSG_PROBE
) {
1453 printk(" warning: CSR address invalid,\n");
1455 " using instead PROM address of");
1457 memcpy(dev
->dev_addr
, promaddr
, 6);
1460 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
1462 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1463 if (!is_valid_ether_addr(dev
->perm_addr
))
1464 memset(dev
->dev_addr
, 0, sizeof(dev
->dev_addr
));
1466 if (pcnet32_debug
& NETIF_MSG_PROBE
) {
1467 for (i
= 0; i
< 6; i
++)
1468 printk(" %2.2x", dev
->dev_addr
[i
]);
1470 /* Version 0x2623 and 0x2624 */
1471 if (((chip_version
+ 1) & 0xfffe) == 0x2624) {
1472 i
= a
->read_csr(ioaddr
, 80) & 0x0C00; /* Check tx_start_pt */
1473 printk("\n" KERN_INFO
" tx_start_pt(0x%04x):", i
);
1476 printk(" 20 bytes,");
1479 printk(" 64 bytes,");
1482 printk(" 128 bytes,");
1485 printk("~220 bytes,");
1488 i
= a
->read_bcr(ioaddr
, 18); /* Check Burst/Bus control */
1489 printk(" BCR18(%x):", i
& 0xffff);
1491 printk("BurstWrEn ");
1493 printk("BurstRdEn ");
1498 i
= a
->read_bcr(ioaddr
, 25);
1499 printk("\n" KERN_INFO
" SRAMSIZE=0x%04x,", i
<< 8);
1500 i
= a
->read_bcr(ioaddr
, 26);
1501 printk(" SRAM_BND=0x%04x,", i
<< 8);
1502 i
= a
->read_bcr(ioaddr
, 27);
1508 dev
->base_addr
= ioaddr
;
1509 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
1511 pci_alloc_consistent(pdev
, sizeof(*lp
), &lp_dma_addr
)) == NULL
) {
1512 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1514 "Consistent memory allocation failed.\n");
1516 goto err_free_netdev
;
1519 memset(lp
, 0, sizeof(*lp
));
1520 lp
->dma_addr
= lp_dma_addr
;
1523 spin_lock_init(&lp
->lock
);
1525 SET_MODULE_OWNER(dev
);
1526 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1528 lp
->name
= chipname
;
1529 lp
->shared_irq
= shared
;
1530 lp
->tx_ring_size
= TX_RING_SIZE
; /* default tx ring size */
1531 lp
->rx_ring_size
= RX_RING_SIZE
; /* default rx ring size */
1532 lp
->tx_mod_mask
= lp
->tx_ring_size
- 1;
1533 lp
->rx_mod_mask
= lp
->rx_ring_size
- 1;
1534 lp
->tx_len_bits
= (PCNET32_LOG_TX_BUFFERS
<< 12);
1535 lp
->rx_len_bits
= (PCNET32_LOG_RX_BUFFERS
<< 4);
1536 lp
->mii_if
.full_duplex
= fdx
;
1537 lp
->mii_if
.phy_id_mask
= 0x1f;
1538 lp
->mii_if
.reg_num_mask
= 0x1f;
1539 lp
->dxsuflo
= dxsuflo
;
1541 lp
->chip_version
= chip_version
;
1542 lp
->msg_enable
= pcnet32_debug
;
1543 if ((cards_found
>= MAX_UNITS
)
1544 || (options
[cards_found
] > sizeof(options_mapping
)))
1545 lp
->options
= PCNET32_PORT_ASEL
;
1547 lp
->options
= options_mapping
[options
[cards_found
]];
1548 lp
->mii_if
.dev
= dev
;
1549 lp
->mii_if
.mdio_read
= mdio_read
;
1550 lp
->mii_if
.mdio_write
= mdio_write
;
1552 if (fdx
&& !(lp
->options
& PCNET32_PORT_ASEL
) &&
1553 ((cards_found
>= MAX_UNITS
) || full_duplex
[cards_found
]))
1554 lp
->options
|= PCNET32_PORT_FD
;
1557 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1558 printk(KERN_ERR PFX
"No access methods\n");
1560 goto err_free_consistent
;
1564 /* prior to register_netdev, dev->name is not yet correct */
1565 if (pcnet32_alloc_ring(dev
, pci_name(lp
->pci_dev
))) {
1569 /* detect special T1/E1 WAN card by checking for MAC address */
1570 if (dev
->dev_addr
[0] == 0x00 && dev
->dev_addr
[1] == 0xe0
1571 && dev
->dev_addr
[2] == 0x75)
1572 lp
->options
= PCNET32_PORT_FD
| PCNET32_PORT_GPSI
;
1574 lp
->init_block
.mode
= le16_to_cpu(0x0003); /* Disable Rx and Tx. */
1575 lp
->init_block
.tlen_rlen
=
1576 le16_to_cpu(lp
->tx_len_bits
| lp
->rx_len_bits
);
1577 for (i
= 0; i
< 6; i
++)
1578 lp
->init_block
.phys_addr
[i
] = dev
->dev_addr
[i
];
1579 lp
->init_block
.filter
[0] = 0x00000000;
1580 lp
->init_block
.filter
[1] = 0x00000000;
1581 lp
->init_block
.rx_ring
= (u32
) le32_to_cpu(lp
->rx_ring_dma_addr
);
1582 lp
->init_block
.tx_ring
= (u32
) le32_to_cpu(lp
->tx_ring_dma_addr
);
1584 /* switch pcnet32 to 32bit mode */
1585 a
->write_bcr(ioaddr
, 20, 2);
1587 a
->write_csr(ioaddr
, 1, (lp
->dma_addr
+ offsetof(struct pcnet32_private
,
1588 init_block
)) & 0xffff);
1589 a
->write_csr(ioaddr
, 2, (lp
->dma_addr
+ offsetof(struct pcnet32_private
,
1590 init_block
)) >> 16);
1592 if (pdev
) { /* use the IRQ provided by PCI */
1593 dev
->irq
= pdev
->irq
;
1594 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1595 printk(" assigned IRQ %d.\n", dev
->irq
);
1597 unsigned long irq_mask
= probe_irq_on();
1600 * To auto-IRQ we enable the initialization-done and DMA error
1601 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1604 /* Trigger an initialization just for the interrupt. */
1605 a
->write_csr(ioaddr
, CSR0
, CSR0_INTEN
| CSR0_INIT
);
1608 dev
->irq
= probe_irq_off(irq_mask
);
1610 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1611 printk(", failed to detect IRQ line.\n");
1615 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1616 printk(", probed IRQ %d.\n", dev
->irq
);
1619 /* Set the mii phy_id so that we can query the link state */
1621 /* lp->phycount and lp->phymask are set to 0 by memset above */
1623 lp
->mii_if
.phy_id
= ((lp
->a
.read_bcr(ioaddr
, 33)) >> 5) & 0x1f;
1625 for (i
= 0; i
< PCNET32_MAX_PHYS
; i
++) {
1626 unsigned short id1
, id2
;
1628 id1
= mdio_read(dev
, i
, MII_PHYSID1
);
1631 id2
= mdio_read(dev
, i
, MII_PHYSID2
);
1634 if (i
== 31 && ((chip_version
+ 1) & 0xfffe) == 0x2624)
1635 continue; /* 79C971 & 79C972 have phantom phy at id 31 */
1637 lp
->phymask
|= (1 << i
);
1638 lp
->mii_if
.phy_id
= i
;
1639 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1640 printk(KERN_INFO PFX
1641 "Found PHY %04x:%04x at address %d.\n",
1644 lp
->a
.write_bcr(ioaddr
, 33, (lp
->mii_if
.phy_id
) << 5);
1645 if (lp
->phycount
> 1) {
1646 lp
->options
|= PCNET32_PORT_MII
;
1650 init_timer(&lp
->watchdog_timer
);
1651 lp
->watchdog_timer
.data
= (unsigned long)dev
;
1652 lp
->watchdog_timer
.function
= (void *)&pcnet32_watchdog
;
1654 /* The PCNET32-specific entries in the device structure. */
1655 dev
->open
= &pcnet32_open
;
1656 dev
->hard_start_xmit
= &pcnet32_start_xmit
;
1657 dev
->stop
= &pcnet32_close
;
1658 dev
->get_stats
= &pcnet32_get_stats
;
1659 dev
->set_multicast_list
= &pcnet32_set_multicast_list
;
1660 dev
->do_ioctl
= &pcnet32_ioctl
;
1661 dev
->ethtool_ops
= &pcnet32_ethtool_ops
;
1662 dev
->tx_timeout
= pcnet32_tx_timeout
;
1663 dev
->watchdog_timeo
= (5 * HZ
);
1665 #ifdef CONFIG_NET_POLL_CONTROLLER
1666 dev
->poll_controller
= pcnet32_poll_controller
;
1669 /* Fill in the generic fields of the device structure. */
1670 if (register_netdev(dev
))
1674 pci_set_drvdata(pdev
, dev
);
1676 lp
->next
= pcnet32_dev
;
1680 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1681 printk(KERN_INFO
"%s: registered as %s\n", dev
->name
, lp
->name
);
1684 /* enable LED writes */
1685 a
->write_bcr(ioaddr
, 2, a
->read_bcr(ioaddr
, 2) | 0x1000);
1690 pcnet32_free_ring(dev
);
1691 err_free_consistent
:
1692 pci_free_consistent(lp
->pci_dev
, sizeof(*lp
), lp
, lp
->dma_addr
);
1696 release_region(ioaddr
, PCNET32_TOTAL_SIZE
);
1700 /* if any allocation fails, caller must also call pcnet32_free_ring */
1701 static int pcnet32_alloc_ring(struct net_device
*dev
, char *name
)
1703 struct pcnet32_private
*lp
= dev
->priv
;
1705 lp
->tx_ring
= pci_alloc_consistent(lp
->pci_dev
,
1706 sizeof(struct pcnet32_tx_head
) *
1708 &lp
->tx_ring_dma_addr
);
1709 if (lp
->tx_ring
== NULL
) {
1710 if (netif_msg_drv(lp
))
1711 printk("\n" KERN_ERR PFX
1712 "%s: Consistent memory allocation failed.\n",
1717 lp
->rx_ring
= pci_alloc_consistent(lp
->pci_dev
,
1718 sizeof(struct pcnet32_rx_head
) *
1720 &lp
->rx_ring_dma_addr
);
1721 if (lp
->rx_ring
== NULL
) {
1722 if (netif_msg_drv(lp
))
1723 printk("\n" KERN_ERR PFX
1724 "%s: Consistent memory allocation failed.\n",
1729 lp
->tx_dma_addr
= kcalloc(lp
->tx_ring_size
, sizeof(dma_addr_t
),
1731 if (!lp
->tx_dma_addr
) {
1732 if (netif_msg_drv(lp
))
1733 printk("\n" KERN_ERR PFX
1734 "%s: Memory allocation failed.\n", name
);
1738 lp
->rx_dma_addr
= kcalloc(lp
->rx_ring_size
, sizeof(dma_addr_t
),
1740 if (!lp
->rx_dma_addr
) {
1741 if (netif_msg_drv(lp
))
1742 printk("\n" KERN_ERR PFX
1743 "%s: Memory allocation failed.\n", name
);
1747 lp
->tx_skbuff
= kcalloc(lp
->tx_ring_size
, sizeof(struct sk_buff
*),
1749 if (!lp
->tx_skbuff
) {
1750 if (netif_msg_drv(lp
))
1751 printk("\n" KERN_ERR PFX
1752 "%s: Memory allocation failed.\n", name
);
1756 lp
->rx_skbuff
= kcalloc(lp
->rx_ring_size
, sizeof(struct sk_buff
*),
1758 if (!lp
->rx_skbuff
) {
1759 if (netif_msg_drv(lp
))
1760 printk("\n" KERN_ERR PFX
1761 "%s: Memory allocation failed.\n", name
);
1768 static void pcnet32_free_ring(struct net_device
*dev
)
1770 struct pcnet32_private
*lp
= dev
->priv
;
1772 kfree(lp
->tx_skbuff
);
1773 lp
->tx_skbuff
= NULL
;
1775 kfree(lp
->rx_skbuff
);
1776 lp
->rx_skbuff
= NULL
;
1778 kfree(lp
->tx_dma_addr
);
1779 lp
->tx_dma_addr
= NULL
;
1781 kfree(lp
->rx_dma_addr
);
1782 lp
->rx_dma_addr
= NULL
;
1785 pci_free_consistent(lp
->pci_dev
,
1786 sizeof(struct pcnet32_tx_head
) *
1787 lp
->tx_ring_size
, lp
->tx_ring
,
1788 lp
->tx_ring_dma_addr
);
1793 pci_free_consistent(lp
->pci_dev
,
1794 sizeof(struct pcnet32_rx_head
) *
1795 lp
->rx_ring_size
, lp
->rx_ring
,
1796 lp
->rx_ring_dma_addr
);
1801 static int pcnet32_open(struct net_device
*dev
)
1803 struct pcnet32_private
*lp
= dev
->priv
;
1804 unsigned long ioaddr
= dev
->base_addr
;
1808 unsigned long flags
;
1810 if (request_irq(dev
->irq
, &pcnet32_interrupt
,
1811 lp
->shared_irq
? IRQF_SHARED
: 0, dev
->name
,
1816 spin_lock_irqsave(&lp
->lock
, flags
);
1817 /* Check for a valid station address */
1818 if (!is_valid_ether_addr(dev
->dev_addr
)) {
1823 /* Reset the PCNET32 */
1824 lp
->a
.reset(ioaddr
);
1826 /* switch pcnet32 to 32bit mode */
1827 lp
->a
.write_bcr(ioaddr
, 20, 2);
1829 if (netif_msg_ifup(lp
))
1831 "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
1832 dev
->name
, dev
->irq
, (u32
) (lp
->tx_ring_dma_addr
),
1833 (u32
) (lp
->rx_ring_dma_addr
),
1834 (u32
) (lp
->dma_addr
+
1835 offsetof(struct pcnet32_private
, init_block
)));
1837 /* set/reset autoselect bit */
1838 val
= lp
->a
.read_bcr(ioaddr
, 2) & ~2;
1839 if (lp
->options
& PCNET32_PORT_ASEL
)
1841 lp
->a
.write_bcr(ioaddr
, 2, val
);
1843 /* handle full duplex setting */
1844 if (lp
->mii_if
.full_duplex
) {
1845 val
= lp
->a
.read_bcr(ioaddr
, 9) & ~3;
1846 if (lp
->options
& PCNET32_PORT_FD
) {
1848 if (lp
->options
== (PCNET32_PORT_FD
| PCNET32_PORT_AUI
))
1850 } else if (lp
->options
& PCNET32_PORT_ASEL
) {
1851 /* workaround of xSeries250, turn on for 79C975 only */
1852 if (lp
->chip_version
== 0x2627)
1855 lp
->a
.write_bcr(ioaddr
, 9, val
);
1858 /* set/reset GPSI bit in test register */
1859 val
= lp
->a
.read_csr(ioaddr
, 124) & ~0x10;
1860 if ((lp
->options
& PCNET32_PORT_PORTSEL
) == PCNET32_PORT_GPSI
)
1862 lp
->a
.write_csr(ioaddr
, 124, val
);
1864 /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
1865 if (lp
->pci_dev
->subsystem_vendor
== PCI_VENDOR_ID_AT
&&
1866 (lp
->pci_dev
->subsystem_device
== PCI_SUBDEVICE_ID_AT_2700FX
||
1867 lp
->pci_dev
->subsystem_device
== PCI_SUBDEVICE_ID_AT_2701FX
)) {
1868 if (lp
->options
& PCNET32_PORT_ASEL
) {
1869 lp
->options
= PCNET32_PORT_FD
| PCNET32_PORT_100
;
1870 if (netif_msg_link(lp
))
1872 "%s: Setting 100Mb-Full Duplex.\n",
1876 if (lp
->phycount
< 2) {
1878 * 24 Jun 2004 according AMD, in order to change the PHY,
1879 * DANAS (or DISPM for 79C976) must be set; then select the speed,
1880 * duplex, and/or enable auto negotiation, and clear DANAS
1882 if (lp
->mii
&& !(lp
->options
& PCNET32_PORT_ASEL
)) {
1883 lp
->a
.write_bcr(ioaddr
, 32,
1884 lp
->a
.read_bcr(ioaddr
, 32) | 0x0080);
1885 /* disable Auto Negotiation, set 10Mpbs, HD */
1886 val
= lp
->a
.read_bcr(ioaddr
, 32) & ~0xb8;
1887 if (lp
->options
& PCNET32_PORT_FD
)
1889 if (lp
->options
& PCNET32_PORT_100
)
1891 lp
->a
.write_bcr(ioaddr
, 32, val
);
1893 if (lp
->options
& PCNET32_PORT_ASEL
) {
1894 lp
->a
.write_bcr(ioaddr
, 32,
1895 lp
->a
.read_bcr(ioaddr
,
1897 /* enable auto negotiate, setup, disable fd */
1898 val
= lp
->a
.read_bcr(ioaddr
, 32) & ~0x98;
1900 lp
->a
.write_bcr(ioaddr
, 32, val
);
1907 struct ethtool_cmd ecmd
;
1910 * There is really no good other way to handle multiple PHYs
1911 * other than turning off all automatics
1913 val
= lp
->a
.read_bcr(ioaddr
, 2);
1914 lp
->a
.write_bcr(ioaddr
, 2, val
& ~2);
1915 val
= lp
->a
.read_bcr(ioaddr
, 32);
1916 lp
->a
.write_bcr(ioaddr
, 32, val
& ~(1 << 7)); /* stop MII manager */
1918 if (!(lp
->options
& PCNET32_PORT_ASEL
)) {
1920 ecmd
.port
= PORT_MII
;
1921 ecmd
.transceiver
= XCVR_INTERNAL
;
1922 ecmd
.autoneg
= AUTONEG_DISABLE
;
1925 options
& PCNET32_PORT_100
? SPEED_100
: SPEED_10
;
1926 bcr9
= lp
->a
.read_bcr(ioaddr
, 9);
1928 if (lp
->options
& PCNET32_PORT_FD
) {
1929 ecmd
.duplex
= DUPLEX_FULL
;
1932 ecmd
.duplex
= DUPLEX_HALF
;
1935 lp
->a
.write_bcr(ioaddr
, 9, bcr9
);
1938 for (i
= 0; i
< PCNET32_MAX_PHYS
; i
++) {
1939 if (lp
->phymask
& (1 << i
)) {
1940 /* isolate all but the first PHY */
1941 bmcr
= mdio_read(dev
, i
, MII_BMCR
);
1942 if (first_phy
== -1) {
1944 mdio_write(dev
, i
, MII_BMCR
,
1945 bmcr
& ~BMCR_ISOLATE
);
1947 mdio_write(dev
, i
, MII_BMCR
,
1948 bmcr
| BMCR_ISOLATE
);
1950 /* use mii_ethtool_sset to setup PHY */
1951 lp
->mii_if
.phy_id
= i
;
1952 ecmd
.phy_address
= i
;
1953 if (lp
->options
& PCNET32_PORT_ASEL
) {
1954 mii_ethtool_gset(&lp
->mii_if
, &ecmd
);
1955 ecmd
.autoneg
= AUTONEG_ENABLE
;
1957 mii_ethtool_sset(&lp
->mii_if
, &ecmd
);
1960 lp
->mii_if
.phy_id
= first_phy
;
1961 if (netif_msg_link(lp
))
1962 printk(KERN_INFO
"%s: Using PHY number %d.\n",
1963 dev
->name
, first_phy
);
1967 if (lp
->dxsuflo
) { /* Disable transmit stop on underflow */
1968 val
= lp
->a
.read_csr(ioaddr
, CSR3
);
1970 lp
->a
.write_csr(ioaddr
, CSR3
, val
);
1974 lp
->init_block
.mode
=
1975 le16_to_cpu((lp
->options
& PCNET32_PORT_PORTSEL
) << 7);
1976 pcnet32_load_multicast(dev
);
1978 if (pcnet32_init_ring(dev
)) {
1983 /* Re-initialize the PCNET32, and start it when done. */
1984 lp
->a
.write_csr(ioaddr
, 1, (lp
->dma_addr
+
1985 offsetof(struct pcnet32_private
,
1986 init_block
)) & 0xffff);
1987 lp
->a
.write_csr(ioaddr
, 2,
1989 offsetof(struct pcnet32_private
, init_block
)) >> 16);
1991 lp
->a
.write_csr(ioaddr
, CSR4
, 0x0915); /* auto tx pad */
1992 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_INIT
);
1994 netif_start_queue(dev
);
1996 if (lp
->chip_version
>= PCNET32_79C970A
) {
1997 /* Print the link status and start the watchdog */
1998 pcnet32_check_media(dev
, 1);
1999 mod_timer(&(lp
->watchdog_timer
), PCNET32_WATCHDOG_TIMEOUT
);
2004 if (lp
->a
.read_csr(ioaddr
, CSR0
) & CSR0_IDON
)
2007 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
2008 * reports that doing so triggers a bug in the '974.
2010 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_NORMAL
);
2012 if (netif_msg_ifup(lp
))
2014 "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
2016 (u32
) (lp
->dma_addr
+
2017 offsetof(struct pcnet32_private
, init_block
)),
2018 lp
->a
.read_csr(ioaddr
, CSR0
));
2020 spin_unlock_irqrestore(&lp
->lock
, flags
);
2022 return 0; /* Always succeed */
2025 /* free any allocated skbuffs */
2026 pcnet32_purge_rx_ring(dev
);
2029 * Switch back to 16bit mode to avoid problems with dumb
2030 * DOS packet driver after a warm reboot
2032 lp
->a
.write_bcr(ioaddr
, 20, 4);
2035 spin_unlock_irqrestore(&lp
->lock
, flags
);
2036 free_irq(dev
->irq
, dev
);
2041 * The LANCE has been halted for one reason or another (busmaster memory
2042 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
2043 * etc.). Modern LANCE variants always reload their ring-buffer
2044 * configuration when restarted, so we must reinitialize our ring
2045 * context before restarting. As part of this reinitialization,
2046 * find all packets still on the Tx ring and pretend that they had been
2047 * sent (in effect, drop the packets on the floor) - the higher-level
2048 * protocols will time out and retransmit. It'd be better to shuffle
2049 * these skbs to a temp list and then actually re-Tx them after
2050 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
2053 static void pcnet32_purge_tx_ring(struct net_device
*dev
)
2055 struct pcnet32_private
*lp
= dev
->priv
;
2058 for (i
= 0; i
< lp
->tx_ring_size
; i
++) {
2059 lp
->tx_ring
[i
].status
= 0; /* CPU owns buffer */
2060 wmb(); /* Make sure adapter sees owner change */
2061 if (lp
->tx_skbuff
[i
]) {
2062 pci_unmap_single(lp
->pci_dev
, lp
->tx_dma_addr
[i
],
2063 lp
->tx_skbuff
[i
]->len
,
2065 dev_kfree_skb_any(lp
->tx_skbuff
[i
]);
2067 lp
->tx_skbuff
[i
] = NULL
;
2068 lp
->tx_dma_addr
[i
] = 0;
2072 /* Initialize the PCNET32 Rx and Tx rings. */
2073 static int pcnet32_init_ring(struct net_device
*dev
)
2075 struct pcnet32_private
*lp
= dev
->priv
;
2079 lp
->cur_rx
= lp
->cur_tx
= 0;
2080 lp
->dirty_rx
= lp
->dirty_tx
= 0;
2082 for (i
= 0; i
< lp
->rx_ring_size
; i
++) {
2083 struct sk_buff
*rx_skbuff
= lp
->rx_skbuff
[i
];
2084 if (rx_skbuff
== NULL
) {
2086 (rx_skbuff
= lp
->rx_skbuff
[i
] =
2087 dev_alloc_skb(PKT_BUF_SZ
))) {
2088 /* there is not much, we can do at this point */
2089 if (netif_msg_drv(lp
))
2091 "%s: pcnet32_init_ring dev_alloc_skb failed.\n",
2095 skb_reserve(rx_skbuff
, 2);
2099 if (lp
->rx_dma_addr
[i
] == 0)
2100 lp
->rx_dma_addr
[i
] =
2101 pci_map_single(lp
->pci_dev
, rx_skbuff
->data
,
2102 PKT_BUF_SZ
- 2, PCI_DMA_FROMDEVICE
);
2103 lp
->rx_ring
[i
].base
= (u32
) le32_to_cpu(lp
->rx_dma_addr
[i
]);
2104 lp
->rx_ring
[i
].buf_length
= le16_to_cpu(2 - PKT_BUF_SZ
);
2105 wmb(); /* Make sure owner changes after all others are visible */
2106 lp
->rx_ring
[i
].status
= le16_to_cpu(0x8000);
2108 /* The Tx buffer address is filled in as needed, but we do need to clear
2109 * the upper ownership bit. */
2110 for (i
= 0; i
< lp
->tx_ring_size
; i
++) {
2111 lp
->tx_ring
[i
].status
= 0; /* CPU owns buffer */
2112 wmb(); /* Make sure adapter sees owner change */
2113 lp
->tx_ring
[i
].base
= 0;
2114 lp
->tx_dma_addr
[i
] = 0;
2117 lp
->init_block
.tlen_rlen
=
2118 le16_to_cpu(lp
->tx_len_bits
| lp
->rx_len_bits
);
2119 for (i
= 0; i
< 6; i
++)
2120 lp
->init_block
.phys_addr
[i
] = dev
->dev_addr
[i
];
2121 lp
->init_block
.rx_ring
= (u32
) le32_to_cpu(lp
->rx_ring_dma_addr
);
2122 lp
->init_block
.tx_ring
= (u32
) le32_to_cpu(lp
->tx_ring_dma_addr
);
2123 wmb(); /* Make sure all changes are visible */
2127 /* the pcnet32 has been issued a stop or reset. Wait for the stop bit
2128 * then flush the pending transmit operations, re-initialize the ring,
2129 * and tell the chip to initialize.
2131 static void pcnet32_restart(struct net_device
*dev
, unsigned int csr0_bits
)
2133 struct pcnet32_private
*lp
= dev
->priv
;
2134 unsigned long ioaddr
= dev
->base_addr
;
2138 for (i
= 0; i
< 100; i
++)
2139 if (lp
->a
.read_csr(ioaddr
, CSR0
) & CSR0_STOP
)
2142 if (i
>= 100 && netif_msg_drv(lp
))
2144 "%s: pcnet32_restart timed out waiting for stop.\n",
2147 pcnet32_purge_tx_ring(dev
);
2148 if (pcnet32_init_ring(dev
))
2152 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_INIT
);
2155 if (lp
->a
.read_csr(ioaddr
, CSR0
) & CSR0_IDON
)
2158 lp
->a
.write_csr(ioaddr
, CSR0
, csr0_bits
);
2161 static void pcnet32_tx_timeout(struct net_device
*dev
)
2163 struct pcnet32_private
*lp
= dev
->priv
;
2164 unsigned long ioaddr
= dev
->base_addr
, flags
;
2166 spin_lock_irqsave(&lp
->lock
, flags
);
2167 /* Transmitter timeout, serious problems. */
2168 if (pcnet32_debug
& NETIF_MSG_DRV
)
2170 "%s: transmit timed out, status %4.4x, resetting.\n",
2171 dev
->name
, lp
->a
.read_csr(ioaddr
, CSR0
));
2172 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_STOP
);
2173 lp
->stats
.tx_errors
++;
2174 if (netif_msg_tx_err(lp
)) {
2177 " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
2178 lp
->dirty_tx
, lp
->cur_tx
, lp
->tx_full
? " (full)" : "",
2180 for (i
= 0; i
< lp
->rx_ring_size
; i
++)
2181 printk("%s %08x %04x %08x %04x", i
& 1 ? "" : "\n ",
2182 le32_to_cpu(lp
->rx_ring
[i
].base
),
2183 (-le16_to_cpu(lp
->rx_ring
[i
].buf_length
)) &
2184 0xffff, le32_to_cpu(lp
->rx_ring
[i
].msg_length
),
2185 le16_to_cpu(lp
->rx_ring
[i
].status
));
2186 for (i
= 0; i
< lp
->tx_ring_size
; i
++)
2187 printk("%s %08x %04x %08x %04x", i
& 1 ? "" : "\n ",
2188 le32_to_cpu(lp
->tx_ring
[i
].base
),
2189 (-le16_to_cpu(lp
->tx_ring
[i
].length
)) & 0xffff,
2190 le32_to_cpu(lp
->tx_ring
[i
].misc
),
2191 le16_to_cpu(lp
->tx_ring
[i
].status
));
2194 pcnet32_restart(dev
, CSR0_NORMAL
);
2196 dev
->trans_start
= jiffies
;
2197 netif_wake_queue(dev
);
2199 spin_unlock_irqrestore(&lp
->lock
, flags
);
2202 static int pcnet32_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
2204 struct pcnet32_private
*lp
= dev
->priv
;
2205 unsigned long ioaddr
= dev
->base_addr
;
2208 unsigned long flags
;
2210 spin_lock_irqsave(&lp
->lock
, flags
);
2212 if (netif_msg_tx_queued(lp
)) {
2214 "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
2215 dev
->name
, lp
->a
.read_csr(ioaddr
, CSR0
));
2218 /* Default status -- will not enable Successful-TxDone
2219 * interrupt when that option is available to us.
2223 /* Fill in a Tx ring entry */
2225 /* Mask to ring buffer boundary. */
2226 entry
= lp
->cur_tx
& lp
->tx_mod_mask
;
2228 /* Caution: the write order is important here, set the status
2229 * with the "ownership" bits last. */
2231 lp
->tx_ring
[entry
].length
= le16_to_cpu(-skb
->len
);
2233 lp
->tx_ring
[entry
].misc
= 0x00000000;
2235 lp
->tx_skbuff
[entry
] = skb
;
2236 lp
->tx_dma_addr
[entry
] =
2237 pci_map_single(lp
->pci_dev
, skb
->data
, skb
->len
, PCI_DMA_TODEVICE
);
2238 lp
->tx_ring
[entry
].base
= (u32
) le32_to_cpu(lp
->tx_dma_addr
[entry
]);
2239 wmb(); /* Make sure owner changes after all others are visible */
2240 lp
->tx_ring
[entry
].status
= le16_to_cpu(status
);
2243 lp
->stats
.tx_bytes
+= skb
->len
;
2245 /* Trigger an immediate send poll. */
2246 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_INTEN
| CSR0_TXPOLL
);
2248 dev
->trans_start
= jiffies
;
2250 if (lp
->tx_ring
[(entry
+ 1) & lp
->tx_mod_mask
].base
!= 0) {
2252 netif_stop_queue(dev
);
2254 spin_unlock_irqrestore(&lp
->lock
, flags
);
2258 /* The PCNET32 interrupt handler. */
2260 pcnet32_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
)
2262 struct net_device
*dev
= dev_id
;
2263 struct pcnet32_private
*lp
;
2264 unsigned long ioaddr
;
2266 int boguscnt
= max_interrupt_work
;
2270 if (pcnet32_debug
& NETIF_MSG_INTR
)
2271 printk(KERN_DEBUG
"%s(): irq %d for unknown device\n",
2276 ioaddr
= dev
->base_addr
;
2279 spin_lock(&lp
->lock
);
2281 while ((csr0
= lp
->a
.read_csr(ioaddr
, 0)) & 0x8f00 && --boguscnt
>= 0) {
2282 if (csr0
== 0xffff) {
2283 break; /* PCMCIA remove happened */
2285 /* Acknowledge all of the current interrupt sources ASAP. */
2286 lp
->a
.write_csr(ioaddr
, 0, csr0
& ~0x004f);
2290 if (netif_msg_intr(lp
))
2292 "%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n",
2293 dev
->name
, csr0
, lp
->a
.read_csr(ioaddr
, 0));
2295 if (csr0
& 0x0400) /* Rx interrupt */
2298 if (csr0
& 0x0200) { /* Tx-done interrupt */
2299 unsigned int dirty_tx
= lp
->dirty_tx
;
2302 while (dirty_tx
!= lp
->cur_tx
) {
2303 int entry
= dirty_tx
& lp
->tx_mod_mask
;
2305 (short)le16_to_cpu(lp
->tx_ring
[entry
].
2309 break; /* It still hasn't been Txed */
2311 lp
->tx_ring
[entry
].base
= 0;
2313 if (status
& 0x4000) {
2314 /* There was an major error, log it. */
2316 le32_to_cpu(lp
->tx_ring
[entry
].
2318 lp
->stats
.tx_errors
++;
2319 if (netif_msg_tx_err(lp
))
2321 "%s: Tx error status=%04x err_status=%08x\n",
2324 if (err_status
& 0x04000000)
2325 lp
->stats
.tx_aborted_errors
++;
2326 if (err_status
& 0x08000000)
2327 lp
->stats
.tx_carrier_errors
++;
2328 if (err_status
& 0x10000000)
2329 lp
->stats
.tx_window_errors
++;
2331 if (err_status
& 0x40000000) {
2332 lp
->stats
.tx_fifo_errors
++;
2333 /* Ackk! On FIFO errors the Tx unit is turned off! */
2334 /* Remove this verbosity later! */
2335 if (netif_msg_tx_err(lp
))
2337 "%s: Tx FIFO error! CSR0=%4.4x\n",
2342 if (err_status
& 0x40000000) {
2343 lp
->stats
.tx_fifo_errors
++;
2344 if (!lp
->dxsuflo
) { /* If controller doesn't recover ... */
2345 /* Ackk! On FIFO errors the Tx unit is turned off! */
2346 /* Remove this verbosity later! */
2347 if (netif_msg_tx_err
2350 "%s: Tx FIFO error! CSR0=%4.4x\n",
2359 if (status
& 0x1800)
2360 lp
->stats
.collisions
++;
2361 lp
->stats
.tx_packets
++;
2364 /* We must free the original skb */
2365 if (lp
->tx_skbuff
[entry
]) {
2366 pci_unmap_single(lp
->pci_dev
,
2367 lp
->tx_dma_addr
[entry
],
2368 lp
->tx_skbuff
[entry
]->
2369 len
, PCI_DMA_TODEVICE
);
2370 dev_kfree_skb_irq(lp
->tx_skbuff
[entry
]);
2371 lp
->tx_skbuff
[entry
] = NULL
;
2372 lp
->tx_dma_addr
[entry
] = 0;
2378 (lp
->cur_tx
- dirty_tx
) & (lp
->tx_mod_mask
+
2380 if (delta
> lp
->tx_ring_size
) {
2381 if (netif_msg_drv(lp
))
2383 "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
2384 dev
->name
, dirty_tx
, lp
->cur_tx
,
2386 dirty_tx
+= lp
->tx_ring_size
;
2387 delta
-= lp
->tx_ring_size
;
2391 netif_queue_stopped(dev
) &&
2392 delta
< lp
->tx_ring_size
- 2) {
2393 /* The ring is no longer full, clear tbusy. */
2395 netif_wake_queue(dev
);
2397 lp
->dirty_tx
= dirty_tx
;
2400 /* Log misc errors. */
2402 lp
->stats
.tx_errors
++; /* Tx babble. */
2403 if (csr0
& 0x1000) {
2405 * this happens when our receive ring is full. This shouldn't
2406 * be a problem as we will see normal rx interrupts for the frames
2407 * in the receive ring. But there are some PCI chipsets (I can
2408 * reproduce this on SP3G with Intel saturn chipset) which have
2409 * sometimes problems and will fill up the receive ring with
2410 * error descriptors. In this situation we don't get a rx
2411 * interrupt, but a missed frame interrupt sooner or later.
2412 * So we try to clean up our receive ring here.
2415 lp
->stats
.rx_errors
++; /* Missed a Rx frame. */
2417 if (csr0
& 0x0800) {
2418 if (netif_msg_drv(lp
))
2420 "%s: Bus master arbitration failure, status %4.4x.\n",
2422 /* unlike for the lance, there is no restart needed */
2426 /* reset the chip to clear the error condition, then restart */
2427 lp
->a
.reset(ioaddr
);
2428 lp
->a
.write_csr(ioaddr
, CSR4
, 0x0915); /* auto tx pad */
2429 pcnet32_restart(dev
, CSR0_START
);
2430 netif_wake_queue(dev
);
2434 /* Set interrupt enable. */
2435 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_INTEN
);
2437 if (netif_msg_intr(lp
))
2438 printk(KERN_DEBUG
"%s: exiting interrupt, csr0=%#4.4x.\n",
2439 dev
->name
, lp
->a
.read_csr(ioaddr
, CSR0
));
2441 spin_unlock(&lp
->lock
);
2446 static int pcnet32_rx(struct net_device
*dev
)
2448 struct pcnet32_private
*lp
= dev
->priv
;
2449 int entry
= lp
->cur_rx
& lp
->rx_mod_mask
;
2450 int boguscnt
= lp
->rx_ring_size
/ 2;
2452 /* If we own the next entry, it's a new packet. Send it up. */
2453 while ((short)le16_to_cpu(lp
->rx_ring
[entry
].status
) >= 0) {
2454 int status
= (short)le16_to_cpu(lp
->rx_ring
[entry
].status
) >> 8;
2456 if (status
!= 0x03) { /* There was an error. */
2458 * There is a tricky error noted by John Murphy,
2459 * <murf@perftech.com> to Russ Nelson: Even with full-sized
2460 * buffers it's possible for a jabber packet to use two
2461 * buffers, with only the last correctly noting the error.
2463 if (status
& 0x01) /* Only count a general error at the */
2464 lp
->stats
.rx_errors
++; /* end of a packet. */
2466 lp
->stats
.rx_frame_errors
++;
2468 lp
->stats
.rx_over_errors
++;
2470 lp
->stats
.rx_crc_errors
++;
2472 lp
->stats
.rx_fifo_errors
++;
2473 lp
->rx_ring
[entry
].status
&= le16_to_cpu(0x03ff);
2475 /* Malloc up new buffer, compatible with net-2e. */
2477 (le32_to_cpu(lp
->rx_ring
[entry
].msg_length
) & 0xfff)
2479 struct sk_buff
*skb
;
2481 /* Discard oversize frames. */
2482 if (unlikely(pkt_len
> PKT_BUF_SZ
- 2)) {
2483 if (netif_msg_drv(lp
))
2485 "%s: Impossible packet size %d!\n",
2486 dev
->name
, pkt_len
);
2487 lp
->stats
.rx_errors
++;
2488 } else if (pkt_len
< 60) {
2489 if (netif_msg_rx_err(lp
))
2490 printk(KERN_ERR
"%s: Runt packet!\n",
2492 lp
->stats
.rx_errors
++;
2494 int rx_in_place
= 0;
2496 if (pkt_len
> rx_copybreak
) {
2497 struct sk_buff
*newskb
;
2500 dev_alloc_skb(PKT_BUF_SZ
))) {
2501 skb_reserve(newskb
, 2);
2502 skb
= lp
->rx_skbuff
[entry
];
2503 pci_unmap_single(lp
->pci_dev
,
2508 PCI_DMA_FROMDEVICE
);
2509 skb_put(skb
, pkt_len
);
2510 lp
->rx_skbuff
[entry
] = newskb
;
2512 lp
->rx_dma_addr
[entry
] =
2513 pci_map_single(lp
->pci_dev
,
2517 PCI_DMA_FROMDEVICE
);
2518 lp
->rx_ring
[entry
].base
=
2526 skb
= dev_alloc_skb(pkt_len
+ 2);
2531 if (netif_msg_drv(lp
))
2533 "%s: Memory squeeze, deferring packet.\n",
2535 for (i
= 0; i
< lp
->rx_ring_size
; i
++)
2545 if (i
> lp
->rx_ring_size
- 2) {
2546 lp
->stats
.rx_dropped
++;
2547 lp
->rx_ring
[entry
].status
|=
2548 le16_to_cpu(0x8000);
2549 wmb(); /* Make sure adapter sees owner change */
2556 skb_reserve(skb
, 2); /* 16 byte align */
2557 skb_put(skb
, pkt_len
); /* Make room */
2558 pci_dma_sync_single_for_cpu(lp
->pci_dev
,
2564 PCI_DMA_FROMDEVICE
);
2565 eth_copy_and_sum(skb
,
2566 (unsigned char *)(lp
->
2571 pci_dma_sync_single_for_device(lp
->
2578 PCI_DMA_FROMDEVICE
);
2580 lp
->stats
.rx_bytes
+= skb
->len
;
2581 skb
->protocol
= eth_type_trans(skb
, dev
);
2583 dev
->last_rx
= jiffies
;
2584 lp
->stats
.rx_packets
++;
2588 * The docs say that the buffer length isn't touched, but Andrew Boyd
2589 * of QNX reports that some revs of the 79C965 clear it.
2591 lp
->rx_ring
[entry
].buf_length
= le16_to_cpu(2 - PKT_BUF_SZ
);
2592 wmb(); /* Make sure owner changes after all others are visible */
2593 lp
->rx_ring
[entry
].status
|= le16_to_cpu(0x8000);
2594 entry
= (++lp
->cur_rx
) & lp
->rx_mod_mask
;
2595 if (--boguscnt
<= 0)
2596 break; /* don't stay in loop forever */
2602 static int pcnet32_close(struct net_device
*dev
)
2604 unsigned long ioaddr
= dev
->base_addr
;
2605 struct pcnet32_private
*lp
= dev
->priv
;
2606 unsigned long flags
;
2608 del_timer_sync(&lp
->watchdog_timer
);
2610 netif_stop_queue(dev
);
2612 spin_lock_irqsave(&lp
->lock
, flags
);
2614 lp
->stats
.rx_missed_errors
= lp
->a
.read_csr(ioaddr
, 112);
2616 if (netif_msg_ifdown(lp
))
2618 "%s: Shutting down ethercard, status was %2.2x.\n",
2619 dev
->name
, lp
->a
.read_csr(ioaddr
, CSR0
));
2621 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
2622 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_STOP
);
2625 * Switch back to 16bit mode to avoid problems with dumb
2626 * DOS packet driver after a warm reboot
2628 lp
->a
.write_bcr(ioaddr
, 20, 4);
2630 spin_unlock_irqrestore(&lp
->lock
, flags
);
2632 free_irq(dev
->irq
, dev
);
2634 spin_lock_irqsave(&lp
->lock
, flags
);
2636 pcnet32_purge_rx_ring(dev
);
2637 pcnet32_purge_tx_ring(dev
);
2639 spin_unlock_irqrestore(&lp
->lock
, flags
);
2644 static struct net_device_stats
*pcnet32_get_stats(struct net_device
*dev
)
2646 struct pcnet32_private
*lp
= dev
->priv
;
2647 unsigned long ioaddr
= dev
->base_addr
;
2648 unsigned long flags
;
2650 spin_lock_irqsave(&lp
->lock
, flags
);
2651 lp
->stats
.rx_missed_errors
= lp
->a
.read_csr(ioaddr
, 112);
2652 spin_unlock_irqrestore(&lp
->lock
, flags
);
2657 /* taken from the sunlance driver, which it took from the depca driver */
2658 static void pcnet32_load_multicast(struct net_device
*dev
)
2660 struct pcnet32_private
*lp
= dev
->priv
;
2661 volatile struct pcnet32_init_block
*ib
= &lp
->init_block
;
2662 volatile u16
*mcast_table
= (u16
*) & ib
->filter
;
2663 struct dev_mc_list
*dmi
= dev
->mc_list
;
2664 unsigned long ioaddr
= dev
->base_addr
;
2669 /* set all multicast bits */
2670 if (dev
->flags
& IFF_ALLMULTI
) {
2671 ib
->filter
[0] = 0xffffffff;
2672 ib
->filter
[1] = 0xffffffff;
2673 lp
->a
.write_csr(ioaddr
, PCNET32_MC_FILTER
, 0xffff);
2674 lp
->a
.write_csr(ioaddr
, PCNET32_MC_FILTER
+1, 0xffff);
2675 lp
->a
.write_csr(ioaddr
, PCNET32_MC_FILTER
+2, 0xffff);
2676 lp
->a
.write_csr(ioaddr
, PCNET32_MC_FILTER
+3, 0xffff);
2679 /* clear the multicast filter */
2684 for (i
= 0; i
< dev
->mc_count
; i
++) {
2685 addrs
= dmi
->dmi_addr
;
2688 /* multicast address? */
2692 crc
= ether_crc_le(6, addrs
);
2694 mcast_table
[crc
>> 4] =
2695 le16_to_cpu(le16_to_cpu(mcast_table
[crc
>> 4]) |
2696 (1 << (crc
& 0xf)));
2698 for (i
= 0; i
< 4; i
++)
2699 lp
->a
.write_csr(ioaddr
, PCNET32_MC_FILTER
+ i
,
2700 le16_to_cpu(mcast_table
[i
]));
2705 * Set or clear the multicast filter for this adaptor.
2707 static void pcnet32_set_multicast_list(struct net_device
*dev
)
2709 unsigned long ioaddr
= dev
->base_addr
, flags
;
2710 struct pcnet32_private
*lp
= dev
->priv
;
2711 int csr15
, suspended
;
2713 spin_lock_irqsave(&lp
->lock
, flags
);
2714 suspended
= pcnet32_suspend(dev
, &flags
, 0);
2715 csr15
= lp
->a
.read_csr(ioaddr
, CSR15
);
2716 if (dev
->flags
& IFF_PROMISC
) {
2717 /* Log any net taps. */
2718 if (netif_msg_hw(lp
))
2719 printk(KERN_INFO
"%s: Promiscuous mode enabled.\n",
2721 lp
->init_block
.mode
=
2722 le16_to_cpu(0x8000 | (lp
->options
& PCNET32_PORT_PORTSEL
) <<
2724 lp
->a
.write_csr(ioaddr
, CSR15
, csr15
| 0x8000);
2726 lp
->init_block
.mode
=
2727 le16_to_cpu((lp
->options
& PCNET32_PORT_PORTSEL
) << 7);
2728 lp
->a
.write_csr(ioaddr
, CSR15
, csr15
& 0x7fff);
2729 pcnet32_load_multicast(dev
);
2734 /* clear SUSPEND (SPND) - CSR5 bit 0 */
2735 csr5
= lp
->a
.read_csr(ioaddr
, CSR5
);
2736 lp
->a
.write_csr(ioaddr
, CSR5
, csr5
& (~CSR5_SUSPEND
));
2738 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_STOP
);
2739 pcnet32_restart(dev
, CSR0_NORMAL
);
2740 netif_wake_queue(dev
);
2743 spin_unlock_irqrestore(&lp
->lock
, flags
);
2746 /* This routine assumes that the lp->lock is held */
2747 static int mdio_read(struct net_device
*dev
, int phy_id
, int reg_num
)
2749 struct pcnet32_private
*lp
= dev
->priv
;
2750 unsigned long ioaddr
= dev
->base_addr
;
2756 lp
->a
.write_bcr(ioaddr
, 33, ((phy_id
& 0x1f) << 5) | (reg_num
& 0x1f));
2757 val_out
= lp
->a
.read_bcr(ioaddr
, 34);
2762 /* This routine assumes that the lp->lock is held */
2763 static void mdio_write(struct net_device
*dev
, int phy_id
, int reg_num
, int val
)
2765 struct pcnet32_private
*lp
= dev
->priv
;
2766 unsigned long ioaddr
= dev
->base_addr
;
2771 lp
->a
.write_bcr(ioaddr
, 33, ((phy_id
& 0x1f) << 5) | (reg_num
& 0x1f));
2772 lp
->a
.write_bcr(ioaddr
, 34, val
);
2775 static int pcnet32_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
2777 struct pcnet32_private
*lp
= dev
->priv
;
2779 unsigned long flags
;
2781 /* SIOC[GS]MIIxxx ioctls */
2783 spin_lock_irqsave(&lp
->lock
, flags
);
2784 rc
= generic_mii_ioctl(&lp
->mii_if
, if_mii(rq
), cmd
, NULL
);
2785 spin_unlock_irqrestore(&lp
->lock
, flags
);
2793 static int pcnet32_check_otherphy(struct net_device
*dev
)
2795 struct pcnet32_private
*lp
= dev
->priv
;
2796 struct mii_if_info mii
= lp
->mii_if
;
2800 for (i
= 0; i
< PCNET32_MAX_PHYS
; i
++) {
2801 if (i
== lp
->mii_if
.phy_id
)
2802 continue; /* skip active phy */
2803 if (lp
->phymask
& (1 << i
)) {
2805 if (mii_link_ok(&mii
)) {
2806 /* found PHY with active link */
2807 if (netif_msg_link(lp
))
2809 "%s: Using PHY number %d.\n",
2812 /* isolate inactive phy */
2814 mdio_read(dev
, lp
->mii_if
.phy_id
, MII_BMCR
);
2815 mdio_write(dev
, lp
->mii_if
.phy_id
, MII_BMCR
,
2816 bmcr
| BMCR_ISOLATE
);
2818 /* de-isolate new phy */
2819 bmcr
= mdio_read(dev
, i
, MII_BMCR
);
2820 mdio_write(dev
, i
, MII_BMCR
,
2821 bmcr
& ~BMCR_ISOLATE
);
2823 /* set new phy address */
2824 lp
->mii_if
.phy_id
= i
;
2833 * Show the status of the media. Similar to mii_check_media however it
2834 * correctly shows the link speed for all (tested) pcnet32 variants.
2835 * Devices with no mii just report link state without speed.
2837 * Caller is assumed to hold and release the lp->lock.
2840 static void pcnet32_check_media(struct net_device
*dev
, int verbose
)
2842 struct pcnet32_private
*lp
= dev
->priv
;
2844 int prev_link
= netif_carrier_ok(dev
) ? 1 : 0;
2848 curr_link
= mii_link_ok(&lp
->mii_if
);
2850 ulong ioaddr
= dev
->base_addr
; /* card base I/O address */
2851 curr_link
= (lp
->a
.read_bcr(ioaddr
, 4) != 0xc0);
2854 if (prev_link
|| verbose
) {
2855 netif_carrier_off(dev
);
2856 if (netif_msg_link(lp
))
2857 printk(KERN_INFO
"%s: link down\n", dev
->name
);
2859 if (lp
->phycount
> 1) {
2860 curr_link
= pcnet32_check_otherphy(dev
);
2863 } else if (verbose
|| !prev_link
) {
2864 netif_carrier_on(dev
);
2866 if (netif_msg_link(lp
)) {
2867 struct ethtool_cmd ecmd
;
2868 mii_ethtool_gset(&lp
->mii_if
, &ecmd
);
2870 "%s: link up, %sMbps, %s-duplex\n",
2872 (ecmd
.speed
== SPEED_100
) ? "100" : "10",
2874 DUPLEX_FULL
) ? "full" : "half");
2876 bcr9
= lp
->a
.read_bcr(dev
->base_addr
, 9);
2877 if ((bcr9
& (1 << 0)) != lp
->mii_if
.full_duplex
) {
2878 if (lp
->mii_if
.full_duplex
)
2882 lp
->a
.write_bcr(dev
->base_addr
, 9, bcr9
);
2885 if (netif_msg_link(lp
))
2886 printk(KERN_INFO
"%s: link up\n", dev
->name
);
2892 * Check for loss of link and link establishment.
2893 * Can not use mii_check_media because it does nothing if mode is forced.
2896 static void pcnet32_watchdog(struct net_device
*dev
)
2898 struct pcnet32_private
*lp
= dev
->priv
;
2899 unsigned long flags
;
2901 /* Print the link status if it has changed */
2902 spin_lock_irqsave(&lp
->lock
, flags
);
2903 pcnet32_check_media(dev
, 0);
2904 spin_unlock_irqrestore(&lp
->lock
, flags
);
2906 mod_timer(&(lp
->watchdog_timer
), PCNET32_WATCHDOG_TIMEOUT
);
2909 static void __devexit
pcnet32_remove_one(struct pci_dev
*pdev
)
2911 struct net_device
*dev
= pci_get_drvdata(pdev
);
2914 struct pcnet32_private
*lp
= dev
->priv
;
2916 unregister_netdev(dev
);
2917 pcnet32_free_ring(dev
);
2918 release_region(dev
->base_addr
, PCNET32_TOTAL_SIZE
);
2919 pci_free_consistent(lp
->pci_dev
, sizeof(*lp
), lp
, lp
->dma_addr
);
2921 pci_disable_device(pdev
);
2922 pci_set_drvdata(pdev
, NULL
);
2926 static struct pci_driver pcnet32_driver
= {
2928 .probe
= pcnet32_probe_pci
,
2929 .remove
= __devexit_p(pcnet32_remove_one
),
2930 .id_table
= pcnet32_pci_tbl
,
2933 /* An additional parameter that may be passed in... */
2934 static int debug
= -1;
2935 static int tx_start_pt
= -1;
2936 static int pcnet32_have_pci
;
2938 module_param(debug
, int, 0);
2939 MODULE_PARM_DESC(debug
, DRV_NAME
" debug level");
2940 module_param(max_interrupt_work
, int, 0);
2941 MODULE_PARM_DESC(max_interrupt_work
,
2942 DRV_NAME
" maximum events handled per interrupt");
2943 module_param(rx_copybreak
, int, 0);
2944 MODULE_PARM_DESC(rx_copybreak
,
2945 DRV_NAME
" copy breakpoint for copy-only-tiny-frames");
2946 module_param(tx_start_pt
, int, 0);
2947 MODULE_PARM_DESC(tx_start_pt
, DRV_NAME
" transmit start point (0-3)");
2948 module_param(pcnet32vlb
, int, 0);
2949 MODULE_PARM_DESC(pcnet32vlb
, DRV_NAME
" Vesa local bus (VLB) support (0/1)");
2950 module_param_array(options
, int, NULL
, 0);
2951 MODULE_PARM_DESC(options
, DRV_NAME
" initial option setting(s) (0-15)");
2952 module_param_array(full_duplex
, int, NULL
, 0);
2953 MODULE_PARM_DESC(full_duplex
, DRV_NAME
" full duplex setting(s) (1)");
2954 /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
2955 module_param_array(homepna
, int, NULL
, 0);
2956 MODULE_PARM_DESC(homepna
,
2958 " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
2960 MODULE_AUTHOR("Thomas Bogendoerfer");
2961 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
2962 MODULE_LICENSE("GPL");
2964 #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
2966 static int __init
pcnet32_init_module(void)
2968 printk(KERN_INFO
"%s", version
);
2970 pcnet32_debug
= netif_msg_init(debug
, PCNET32_MSG_DEFAULT
);
2972 if ((tx_start_pt
>= 0) && (tx_start_pt
<= 3))
2973 tx_start
= tx_start_pt
;
2975 /* find the PCI devices */
2976 if (!pci_register_driver(&pcnet32_driver
))
2977 pcnet32_have_pci
= 1;
2979 /* should we find any remaining VLbus devices ? */
2981 pcnet32_probe_vlbus(pcnet32_portlist
);
2983 if (cards_found
&& (pcnet32_debug
& NETIF_MSG_PROBE
))
2984 printk(KERN_INFO PFX
"%d cards_found.\n", cards_found
);
2986 return (pcnet32_have_pci
+ cards_found
) ? 0 : -ENODEV
;
2989 static void __exit
pcnet32_cleanup_module(void)
2991 struct net_device
*next_dev
;
2993 while (pcnet32_dev
) {
2994 struct pcnet32_private
*lp
= pcnet32_dev
->priv
;
2995 next_dev
= lp
->next
;
2996 unregister_netdev(pcnet32_dev
);
2997 pcnet32_free_ring(pcnet32_dev
);
2998 release_region(pcnet32_dev
->base_addr
, PCNET32_TOTAL_SIZE
);
2999 pci_free_consistent(lp
->pci_dev
, sizeof(*lp
), lp
, lp
->dma_addr
);
3000 free_netdev(pcnet32_dev
);
3001 pcnet32_dev
= next_dev
;
3004 if (pcnet32_have_pci
)
3005 pci_unregister_driver(&pcnet32_driver
);
3008 module_init(pcnet32_init_module
);
3009 module_exit(pcnet32_cleanup_module
);