drivers/net/phy/at803x.c

   1 /*
   2  * drivers/net/phy/at803x.c
   3  *
   4  * Driver for Atheros 803x PHY
   5  *
   6  * Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13
  14 #include <linux/phy.h>
  15 #include <linux/module.h>
  16 #include <linux/string.h>
  17 #include <linux/netdevice.h>
  18 #include <linux/etherdevice.h>
  19 #include <linux/of_gpio.h>
  20 #include <linux/gpio/consumer.h>
  21
  22 #define AT803X_INTR_ENABLE                      0x12
  23 #define AT803X_INTR_ENABLE_INIT                 0xec00
  24 #define AT803X_INTR_STATUS                      0x13
  25
  26 #define AT803X_SMART_SPEED                      0x14
  27 #define AT803X_LED_CONTROL                      0x18
  28
  29 #define AT803X_WOL_ENABLE                       0x01
  30 #define AT803X_DEVICE_ADDR                      0x03
  31 #define AT803X_LOC_MAC_ADDR_0_15_OFFSET         0x804C
  32 #define AT803X_LOC_MAC_ADDR_16_31_OFFSET        0x804B
  33 #define AT803X_LOC_MAC_ADDR_32_47_OFFSET        0x804A
  34 #define AT803X_MMD_ACCESS_CONTROL               0x0D
  35 #define AT803X_MMD_ACCESS_CONTROL_DATA          0x0E
  36 #define AT803X_FUNC_DATA                        0x4003
  37
  38 #define AT803X_DEBUG_ADDR                       0x1D
  39 #define AT803X_DEBUG_DATA                       0x1E
  40
  41 #define AT803X_DEBUG_REG_0                      0x00
  42 #define AT803X_DEBUG_RX_CLK_DLY_EN              BIT(15)
  43
  44 #define AT803X_DEBUG_REG_5                      0x05
  45 #define AT803X_DEBUG_TX_CLK_DLY_EN              BIT(8)
  46
  47 #define ATH8030_PHY_ID 0x004dd076
  48 #define ATH8031_PHY_ID 0x004dd074
  49 #define ATH8035_PHY_ID 0x004dd072
  50
  51 MODULE_DESCRIPTION("Atheros 803x PHY driver");
  52 MODULE_AUTHOR("Matus Ujhelyi");
  53 MODULE_LICENSE("GPL");
  54
  55 struct at803x_priv {
  56         bool phy_reset:1;
  57         struct gpio_desc *gpiod_reset;
  58 };
  59
  60 struct at803x_context {
  61         u16 bmcr;
  62         u16 advertise;
  63         u16 control1000;
  64         u16 int_enable;
  65         u16 smart_speed;
  66         u16 led_control;
  67 };
  68
  69 static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
  70 {
  71         int ret;
  72
  73         ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
  74         if (ret < 0)
  75                 return ret;
  76
  77         return phy_read(phydev, AT803X_DEBUG_DATA);
  78 }
  79
  80 static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
  81                                  u16 clear, u16 set)
  82 {
  83         u16 val;
  84         int ret;
  85
  86         ret = at803x_debug_reg_read(phydev, reg);
  87         if (ret < 0)
  88                 return ret;
  89
  90         val = ret & 0xffff;
  91         val &= ~clear;
  92         val |= set;
  93
  94         return phy_write(phydev, AT803X_DEBUG_DATA, val);
  95 }
  96
  97 static inline int at803x_enable_rx_delay(struct phy_device *phydev)
  98 {
  99         return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0,
 100                                         AT803X_DEBUG_RX_CLK_DLY_EN);
 101 }
 102
 103 static inline int at803x_enable_tx_delay(struct phy_device *phydev)
 104 {
 105         return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0,
 106                                         AT803X_DEBUG_TX_CLK_DLY_EN);
 107 }
 108
 109 /* save relevant PHY registers to private copy */
 110 static void at803x_context_save(struct phy_device *phydev,
 111                                 struct at803x_context *context)
 112 {
 113         context->bmcr = phy_read(phydev, MII_BMCR);
 114         context->advertise = phy_read(phydev, MII_ADVERTISE);
 115         context->control1000 = phy_read(phydev, MII_CTRL1000);
 116         context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE);
 117         context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED);
 118         context->led_control = phy_read(phydev, AT803X_LED_CONTROL);
 119 }
 120
 121 /* restore relevant PHY registers from private copy */
 122 static void at803x_context_restore(struct phy_device *phydev,
 123                                    const struct at803x_context *context)
 124 {
 125         phy_write(phydev, MII_BMCR, context->bmcr);
 126         phy_write(phydev, MII_ADVERTISE, context->advertise);
 127         phy_write(phydev, MII_CTRL1000, context->control1000);
 128         phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable);
 129         phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed);
 130         phy_write(phydev, AT803X_LED_CONTROL, context->led_control);
 131 }
 132
 133 static int at803x_set_wol(struct phy_device *phydev,
 134                           struct ethtool_wolinfo *wol)
 135 {
 136         struct net_device *ndev = phydev->attached_dev;
 137         const u8 *mac;
 138         int ret;
 139         u32 value;
 140         unsigned int i, offsets[] = {
 141                 AT803X_LOC_MAC_ADDR_32_47_OFFSET,
 142                 AT803X_LOC_MAC_ADDR_16_31_OFFSET,
 143                 AT803X_LOC_MAC_ADDR_0_15_OFFSET,
 144         };
 145
 146         if (!ndev)
 147                 return -ENODEV;
 148
 149         if (wol->wolopts & WAKE_MAGIC) {
 150                 mac = (const u8 *) ndev->dev_addr;
 151
 152                 if (!is_valid_ether_addr(mac))
 153                         return -EFAULT;
 154
 155                 for (i = 0; i < 3; i++) {
 156                         phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
 157                                   AT803X_DEVICE_ADDR);
 158                         phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
 159                                   offsets[i]);
 160                         phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
 161                                   AT803X_FUNC_DATA);
 162                         phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
 163                                   mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
 164                 }
 165
 166                 value = phy_read(phydev, AT803X_INTR_ENABLE);
 167                 value |= AT803X_WOL_ENABLE;
 168                 ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
 169                 if (ret)
 170                         return ret;
 171                 value = phy_read(phydev, AT803X_INTR_STATUS);
 172         } else {
 173                 value = phy_read(phydev, AT803X_INTR_ENABLE);
 174                 value &= (~AT803X_WOL_ENABLE);
 175                 ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
 176                 if (ret)
 177                         return ret;
 178                 value = phy_read(phydev, AT803X_INTR_STATUS);
 179         }
 180
 181         return ret;
 182 }
 183
 184 static void at803x_get_wol(struct phy_device *phydev,
 185                            struct ethtool_wolinfo *wol)
 186 {
 187         u32 value;
 188
 189         wol->supported = WAKE_MAGIC;
 190         wol->wolopts = 0;
 191
 192         value = phy_read(phydev, AT803X_INTR_ENABLE);
 193         if (value & AT803X_WOL_ENABLE)
 194                 wol->wolopts |= WAKE_MAGIC;
 195 }
 196
 197 static int at803x_suspend(struct phy_device *phydev)
 198 {
 199         int value;
 200         int wol_enabled;
 201
 202         mutex_lock(&phydev->lock);
 203
 204         value = phy_read(phydev, AT803X_INTR_ENABLE);
 205         wol_enabled = value & AT803X_WOL_ENABLE;
 206
 207         value = phy_read(phydev, MII_BMCR);
 208
 209         if (wol_enabled)
 210                 value |= BMCR_ISOLATE;
 211         else
 212                 value |= BMCR_PDOWN;
 213
 214         phy_write(phydev, MII_BMCR, value);
 215
 216         mutex_unlock(&phydev->lock);
 217
 218         return 0;
 219 }
 220
 221 static int at803x_resume(struct phy_device *phydev)
 222 {
 223         int value;
 224
 225         mutex_lock(&phydev->lock);
 226
 227         value = phy_read(phydev, MII_BMCR);
 228         value &= ~(BMCR_PDOWN | BMCR_ISOLATE);
 229         phy_write(phydev, MII_BMCR, value);
 230
 231         mutex_unlock(&phydev->lock);
 232
 233         return 0;
 234 }
 235
 236 static int at803x_probe(struct phy_device *phydev)
 237 {
 238         struct device *dev = &phydev->mdio.dev;
 239         struct at803x_priv *priv;
 240         struct gpio_desc *gpiod_reset;
 241
 242         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 243         if (!priv)
 244                 return -ENOMEM;
 245
 246         gpiod_reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
 247         if (IS_ERR(gpiod_reset))
 248                 return PTR_ERR(gpiod_reset);
 249
 250         priv->gpiod_reset = gpiod_reset;
 251
 252         phydev->priv = priv;
 253
 254         return 0;
 255 }
 256
 257 static int at803x_config_init(struct phy_device *phydev)
 258 {
 259         int ret;
 260
 261         ret = genphy_config_init(phydev);
 262         if (ret < 0)
 263                 return ret;
 264
 265         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
 266                         phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
 267                 ret = at803x_enable_rx_delay(phydev);
 268                 if (ret < 0)
 269                         return ret;
 270         }
 271
 272         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
 273                         phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
 274                 ret = at803x_enable_tx_delay(phydev);
 275                 if (ret < 0)
 276                         return ret;
 277         }
 278
 279         return 0;
 280 }
 281
 282 static int at803x_ack_interrupt(struct phy_device *phydev)
 283 {
 284         int err;
 285
 286         err = phy_read(phydev, AT803X_INTR_STATUS);
 287
 288         return (err < 0) ? err : 0;
 289 }
 290
 291 static int at803x_config_intr(struct phy_device *phydev)
 292 {
 293         int err;
 294         int value;
 295
 296         value = phy_read(phydev, AT803X_INTR_ENABLE);
 297
 298         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 299                 err = phy_write(phydev, AT803X_INTR_ENABLE,
 300                                 value | AT803X_INTR_ENABLE_INIT);
 301         else
 302                 err = phy_write(phydev, AT803X_INTR_ENABLE, 0);
 303
 304         return err;
 305 }
 306
 307 static void at803x_link_change_notify(struct phy_device *phydev)
 308 {
 309         struct at803x_priv *priv = phydev->priv;
 310
 311         /*
 312          * Conduct a hardware reset for AT8030 every time a link loss is
 313          * signalled. This is necessary to circumvent a hardware bug that
 314          * occurs when the cable is unplugged while TX packets are pending
 315          * in the FIFO. In such cases, the FIFO enters an error mode it
 316          * cannot recover from by software.
 317          */
 318         if (phydev->drv->phy_id == ATH8030_PHY_ID) {
 319                 if (phydev->state == PHY_NOLINK) {
 320                         if (priv->gpiod_reset && !priv->phy_reset) {
 321                                 struct at803x_context context;
 322
 323                                 at803x_context_save(phydev, &context);
 324
 325                                 gpiod_set_value(priv->gpiod_reset, 0);
 326                                 msleep(1);
 327                                 gpiod_set_value(priv->gpiod_reset, 1);
 328                                 msleep(1);
 329
 330                                 at803x_context_restore(phydev, &context);
 331
 332                                 phydev_dbg(phydev, "%s(): phy was reset\n",
 333                                            __func__);
 334                                 priv->phy_reset = true;
 335                         }
 336                 } else {
 337                         priv->phy_reset = false;
 338                 }
 339         }
 340 }
 341
 342 static struct phy_driver at803x_driver[] = {
 343 {
 344         /* ATHEROS 8035 */
 345         .phy_id                 = ATH8035_PHY_ID,
 346         .name                   = "Atheros 8035 ethernet",
 347         .phy_id_mask            = 0xffffffef,
 348         .probe                  = at803x_probe,
 349         .config_init            = at803x_config_init,
 350         .link_change_notify     = at803x_link_change_notify,
 351         .set_wol                = at803x_set_wol,
 352         .get_wol                = at803x_get_wol,
 353         .suspend                = at803x_suspend,
 354         .resume                 = at803x_resume,
 355         .features               = PHY_GBIT_FEATURES,
 356         .flags                  = PHY_HAS_INTERRUPT,
 357         .config_aneg            = genphy_config_aneg,
 358         .read_status            = genphy_read_status,
 359         .ack_interrupt          = at803x_ack_interrupt,
 360         .config_intr            = at803x_config_intr,
 361 }, {
 362         /* ATHEROS 8030 */
 363         .phy_id                 = ATH8030_PHY_ID,
 364         .name                   = "Atheros 8030 ethernet",
 365         .phy_id_mask            = 0xffffffef,
 366         .probe                  = at803x_probe,
 367         .config_init            = at803x_config_init,
 368         .link_change_notify     = at803x_link_change_notify,
 369         .set_wol                = at803x_set_wol,
 370         .get_wol                = at803x_get_wol,
 371         .suspend                = at803x_suspend,
 372         .resume                 = at803x_resume,
 373         .features               = PHY_BASIC_FEATURES,
 374         .flags                  = PHY_HAS_INTERRUPT,
 375         .config_aneg            = genphy_config_aneg,
 376         .read_status            = genphy_read_status,
 377         .ack_interrupt          = at803x_ack_interrupt,
 378         .config_intr            = at803x_config_intr,
 379 }, {
 380         /* ATHEROS 8031 */
 381         .phy_id                 = ATH8031_PHY_ID,
 382         .name                   = "Atheros 8031 ethernet",
 383         .phy_id_mask            = 0xffffffef,
 384         .probe                  = at803x_probe,
 385         .config_init            = at803x_config_init,
 386         .link_change_notify     = at803x_link_change_notify,
 387         .set_wol                = at803x_set_wol,
 388         .get_wol                = at803x_get_wol,
 389         .suspend                = at803x_suspend,
 390         .resume                 = at803x_resume,
 391         .features               = PHY_GBIT_FEATURES,
 392         .flags                  = PHY_HAS_INTERRUPT,
 393         .config_aneg            = genphy_config_aneg,
 394         .read_status            = genphy_read_status,
 395         .ack_interrupt          = &at803x_ack_interrupt,
 396         .config_intr            = &at803x_config_intr,
 397 } };
 398
 399 module_phy_driver(at803x_driver);
 400
 401 static struct mdio_device_id __maybe_unused atheros_tbl[] = {
 402         { ATH8030_PHY_ID, 0xffffffef },
 403         { ATH8031_PHY_ID, 0xffffffef },
 404         { ATH8035_PHY_ID, 0xffffffef },
 405         { }
 406 };
 407
 408 MODULE_DEVICE_TABLE(mdio, atheros_tbl);