drivers/net/phy/broadcom.c

   1 /*
   2  *      drivers/net/phy/broadcom.c
   3  *
   4  *      Broadcom BCM5411, BCM5421 and BCM5461 Gigabit Ethernet
   5  *      transceivers.
   6  *
   7  *      Copyright (c) 2006  Maciej W. Rozycki
   8  *
   9  *      Inspired by code written by Amy Fong.
  10  *
  11  *      This program is free software; you can redistribute it and/or
  12  *      modify it under the terms of the GNU General Public License
  13  *      as published by the Free Software Foundation; either version
  14  *      2 of the License, or (at your option) any later version.
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/phy.h>
  19 #include <linux/brcmphy.h>
  20
  21 #define PHY_ID_BCM50610         0x0143bd60
  22 #define PHY_ID_BCM50610M        0x0143bd70
  23 #define PHY_ID_BCM57780         0x03625d90
  24
  25 #define BRCM_PHY_MODEL(phydev) \
  26         ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
  27
  28
  29 #define MII_BCM54XX_ECR         0x10    /* BCM54xx extended control register */
  30 #define MII_BCM54XX_ECR_IM      0x1000  /* Interrupt mask */
  31 #define MII_BCM54XX_ECR_IF      0x0800  /* Interrupt force */
  32
  33 #define MII_BCM54XX_ESR         0x11    /* BCM54xx extended status register */
  34 #define MII_BCM54XX_ESR_IS      0x1000  /* Interrupt status */
  35
  36 #define MII_BCM54XX_EXP_DATA    0x15    /* Expansion register data */
  37 #define MII_BCM54XX_EXP_SEL     0x17    /* Expansion register select */
  38 #define MII_BCM54XX_EXP_SEL_SSD 0x0e00  /* Secondary SerDes select */
  39 #define MII_BCM54XX_EXP_SEL_ER  0x0f00  /* Expansion register select */
  40
  41 #define MII_BCM54XX_AUX_CTL     0x18    /* Auxiliary control register */
  42 #define MII_BCM54XX_ISR         0x1a    /* BCM54xx interrupt status register */
  43 #define MII_BCM54XX_IMR         0x1b    /* BCM54xx interrupt mask register */
  44 #define MII_BCM54XX_INT_CRCERR  0x0001  /* CRC error */
  45 #define MII_BCM54XX_INT_LINK    0x0002  /* Link status changed */
  46 #define MII_BCM54XX_INT_SPEED   0x0004  /* Link speed change */
  47 #define MII_BCM54XX_INT_DUPLEX  0x0008  /* Duplex mode changed */
  48 #define MII_BCM54XX_INT_LRS     0x0010  /* Local receiver status changed */
  49 #define MII_BCM54XX_INT_RRS     0x0020  /* Remote receiver status changed */
  50 #define MII_BCM54XX_INT_SSERR   0x0040  /* Scrambler synchronization error */
  51 #define MII_BCM54XX_INT_UHCD    0x0080  /* Unsupported HCD negotiated */
  52 #define MII_BCM54XX_INT_NHCD    0x0100  /* No HCD */
  53 #define MII_BCM54XX_INT_NHCDL   0x0200  /* No HCD link */
  54 #define MII_BCM54XX_INT_ANPR    0x0400  /* Auto-negotiation page received */
  55 #define MII_BCM54XX_INT_LC      0x0800  /* All counters below 128 */
  56 #define MII_BCM54XX_INT_HC      0x1000  /* Counter above 32768 */
  57 #define MII_BCM54XX_INT_MDIX    0x2000  /* MDIX status change */
  58 #define MII_BCM54XX_INT_PSERR   0x4000  /* Pair swap error */
  59
  60 #define MII_BCM54XX_SHD         0x1c    /* 0x1c shadow registers */
  61 #define MII_BCM54XX_SHD_WRITE   0x8000
  62 #define MII_BCM54XX_SHD_VAL(x)  ((x & 0x1f) << 10)
  63 #define MII_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0)
  64
  65 /*
  66  * AUXILIARY CONTROL SHADOW ACCESS REGISTERS.  (PHY REG 0x18)
  67  */
  68 #define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL       0x0000
  69 #define MII_BCM54XX_AUXCTL_ACTL_TX_6DB          0x0400
  70 #define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA       0x0800
  71
  72 #define MII_BCM54XX_AUXCTL_MISC_WREN    0x8000
  73 #define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX     0x0200
  74 #define MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC      0x7000
  75 #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x0007
  76
  77 #define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL       0x0000
  78
  79
  80 /*
  81  * Broadcom LED source encodings.  These are used in BCM5461, BCM5481,
  82  * BCM5482, and possibly some others.
  83  */
  84 #define BCM_LED_SRC_LINKSPD1    0x0
  85 #define BCM_LED_SRC_LINKSPD2    0x1
  86 #define BCM_LED_SRC_XMITLED     0x2
  87 #define BCM_LED_SRC_ACTIVITYLED 0x3
  88 #define BCM_LED_SRC_FDXLED      0x4
  89 #define BCM_LED_SRC_SLAVE       0x5
  90 #define BCM_LED_SRC_INTR        0x6
  91 #define BCM_LED_SRC_QUALITY     0x7
  92 #define BCM_LED_SRC_RCVLED      0x8
  93 #define BCM_LED_SRC_MULTICOLOR1 0xa
  94 #define BCM_LED_SRC_OPENSHORT   0xb
  95 #define BCM_LED_SRC_OFF         0xe     /* Tied high */
  96 #define BCM_LED_SRC_ON          0xf     /* Tied low */
  97
  98 /*
  99  * BCM5482: Shadow registers
 100  * Shadow values go into bits [14:10] of register 0x1c to select a shadow
 101  * register to access.
 102  */
 103 #define BCM5482_SHD_LEDS1       0x0d    /* 01101: LED Selector 1 */
 104                                         /* LED3 / ~LINKSPD[2] selector */
 105 #define BCM5482_SHD_LEDS1_LED3(src)     ((src & 0xf) << 4)
 106                                         /* LED1 / ~LINKSPD[1] selector */
 107 #define BCM5482_SHD_LEDS1_LED1(src)     ((src & 0xf) << 0)
 108 #define BCM5482_SHD_SSD         0x14    /* 10100: Secondary SerDes control */
 109 #define BCM5482_SHD_SSD_LEDM    0x0008  /* SSD LED Mode enable */
 110 #define BCM5482_SHD_SSD_EN      0x0001  /* SSD enable */
 111 #define BCM5482_SHD_MODE        0x1f    /* 11111: Mode Control Register */
 112 #define BCM5482_SHD_MODE_1000BX 0x0001  /* Enable 1000BASE-X registers */
 113
 114 /*
 115  * EXPANSION SHADOW ACCESS REGISTERS.  (PHY REG 0x15, 0x16, and 0x17)
 116  */
 117 #define MII_BCM54XX_EXP_AADJ1CH0                0x001f
 118 #define  MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN  0x0200
 119 #define  MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF    0x0100
 120 #define MII_BCM54XX_EXP_AADJ1CH3                0x601f
 121 #define  MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ      0x0002
 122 #define MII_BCM54XX_EXP_EXP08                   0x0F08
 123 #define  MII_BCM54XX_EXP_EXP08_RJCT_2MHZ        0x0001
 124 #define  MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE   0x0200
 125 #define MII_BCM54XX_EXP_EXP75                   0x0f75
 126 #define  MII_BCM54XX_EXP_EXP75_VDACCTRL         0x003c
 127 #define  MII_BCM54XX_EXP_EXP75_CM_OSC           0x0001
 128 #define MII_BCM54XX_EXP_EXP96                   0x0f96
 129 #define  MII_BCM54XX_EXP_EXP96_MYST             0x0010
 130 #define MII_BCM54XX_EXP_EXP97                   0x0f97
 131 #define  MII_BCM54XX_EXP_EXP97_MYST             0x0c0c
 132
 133 /*
 134  * BCM5482: Secondary SerDes registers
 135  */
 136 #define BCM5482_SSD_1000BX_CTL          0x00    /* 1000BASE-X Control */
 137 #define BCM5482_SSD_1000BX_CTL_PWRDOWN  0x0800  /* Power-down SSD */
 138 #define BCM5482_SSD_SGMII_SLAVE         0x15    /* SGMII Slave Register */
 139 #define BCM5482_SSD_SGMII_SLAVE_EN      0x0002  /* Slave mode enable */
 140 #define BCM5482_SSD_SGMII_SLAVE_AD      0x0001  /* Slave auto-detection */
 141
 142
 143 /*****************************************************************************/
 144 /* Fast Ethernet Transceiver definitions. */
 145 /*****************************************************************************/
 146
 147 #define MII_BRCM_FET_INTREG             0x1a    /* Interrupt register */
 148 #define MII_BRCM_FET_IR_MASK            0x0100  /* Mask all interrupts */
 149 #define MII_BRCM_FET_IR_LINK_EN         0x0200  /* Link status change enable */
 150 #define MII_BRCM_FET_IR_SPEED_EN        0x0400  /* Link speed change enable */
 151 #define MII_BRCM_FET_IR_DUPLEX_EN       0x0800  /* Duplex mode change enable */
 152 #define MII_BRCM_FET_IR_ENABLE          0x4000  /* Interrupt enable */
 153
 154 #define MII_BRCM_FET_BRCMTEST           0x1f    /* Brcm test register */
 155 #define MII_BRCM_FET_BT_SRE             0x0080  /* Shadow register enable */
 156
 157
 158 /*** Shadow register definitions ***/
 159
 160 #define MII_BRCM_FET_SHDW_MISCCTRL      0x10    /* Shadow misc ctrl */
 161 #define MII_BRCM_FET_SHDW_MC_FAME       0x4000  /* Force Auto MDIX enable */
 162
 163 #define MII_BRCM_FET_SHDW_AUXMODE4      0x1a    /* Auxiliary mode 4 */
 164 #define MII_BRCM_FET_SHDW_AM4_LED_MASK  0x0003
 165 #define MII_BRCM_FET_SHDW_AM4_LED_MODE1 0x0001
 166
 167 #define MII_BRCM_FET_SHDW_AUXSTAT2      0x1b    /* Auxiliary status 2 */
 168 #define MII_BRCM_FET_SHDW_AS2_APDE      0x0020  /* Auto power down enable */
 169
 170
 171 MODULE_DESCRIPTION("Broadcom PHY driver");
 172 MODULE_AUTHOR("Maciej W. Rozycki");
 173 MODULE_LICENSE("GPL");
 174
 175 /*
 176  * Indirect register access functions for the 1000BASE-T/100BASE-TX/10BASE-T
 177  * 0x1c shadow registers.
 178  */
 179 static int bcm54xx_shadow_read(struct phy_device *phydev, u16 shadow)
 180 {
 181         phy_write(phydev, MII_BCM54XX_SHD, MII_BCM54XX_SHD_VAL(shadow));
 182         return MII_BCM54XX_SHD_DATA(phy_read(phydev, MII_BCM54XX_SHD));
 183 }
 184
 185 static int bcm54xx_shadow_write(struct phy_device *phydev, u16 shadow, u16 val)
 186 {
 187         return phy_write(phydev, MII_BCM54XX_SHD,
 188                          MII_BCM54XX_SHD_WRITE |
 189                          MII_BCM54XX_SHD_VAL(shadow) |
 190                          MII_BCM54XX_SHD_DATA(val));
 191 }
 192
 193 /* Indirect register access functions for the Expansion Registers */
 194 static int bcm54xx_exp_read(struct phy_device *phydev, u16 regnum)
 195 {
 196         int val;
 197
 198         val = phy_write(phydev, MII_BCM54XX_EXP_SEL, regnum);
 199         if (val < 0)
 200                 return val;
 201
 202         val = phy_read(phydev, MII_BCM54XX_EXP_DATA);
 203
 204         /* Restore default value.  It's O.K. if this write fails. */
 205         phy_write(phydev, MII_BCM54XX_EXP_SEL, 0);
 206
 207         return val;
 208 }
 209
 210 static int bcm54xx_exp_write(struct phy_device *phydev, u16 regnum, u16 val)
 211 {
 212         int ret;
 213
 214         ret = phy_write(phydev, MII_BCM54XX_EXP_SEL, regnum);
 215         if (ret < 0)
 216                 return ret;
 217
 218         ret = phy_write(phydev, MII_BCM54XX_EXP_DATA, val);
 219
 220         /* Restore default value.  It's O.K. if this write fails. */
 221         phy_write(phydev, MII_BCM54XX_EXP_SEL, 0);
 222
 223         return ret;
 224 }
 225
 226 static int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val)
 227 {
 228         return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val);
 229 }
 230
 231 /* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */
 232 static int bcm50610_a0_workaround(struct phy_device *phydev)
 233 {
 234         int err;
 235
 236         err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_AADJ1CH0,
 237                                 MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN |
 238                                 MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF);
 239         if (err < 0)
 240                 return err;
 241
 242         err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_AADJ1CH3,
 243                                         MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ);
 244         if (err < 0)
 245                 return err;
 246
 247         err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_EXP75,
 248                                 MII_BCM54XX_EXP_EXP75_VDACCTRL);
 249         if (err < 0)
 250                 return err;
 251
 252         err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_EXP96,
 253                                 MII_BCM54XX_EXP_EXP96_MYST);
 254         if (err < 0)
 255                 return err;
 256
 257         err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_EXP97,
 258                                 MII_BCM54XX_EXP_EXP97_MYST);
 259
 260         return err;
 261 }
 262
 263 static int bcm54xx_phydsp_config(struct phy_device *phydev)
 264 {
 265         int err, err2;
 266
 267         /* Enable the SMDSP clock */
 268         err = bcm54xx_auxctl_write(phydev,
 269                                    MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
 270                                    MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA |
 271                                    MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
 272         if (err < 0)
 273                 return err;
 274
 275         if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
 276             BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) {
 277                 /* Clear bit 9 to fix a phy interop issue. */
 278                 err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_EXP08,
 279                                         MII_BCM54XX_EXP_EXP08_RJCT_2MHZ);
 280                 if (err < 0)
 281                         goto error;
 282
 283                 if (phydev->drv->phy_id == PHY_ID_BCM50610) {
 284                         err = bcm50610_a0_workaround(phydev);
 285                         if (err < 0)
 286                                 goto error;
 287                 }
 288         }
 289
 290         if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM57780) {
 291                 int val;
 292
 293                 val = bcm54xx_exp_read(phydev, MII_BCM54XX_EXP_EXP75);
 294                 if (val < 0)
 295                         goto error;
 296
 297                 val |= MII_BCM54XX_EXP_EXP75_CM_OSC;
 298                 err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_EXP75, val);
 299         }
 300
 301 error:
 302         /* Disable the SMDSP clock */
 303         err2 = bcm54xx_auxctl_write(phydev,
 304                                     MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
 305                                     MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
 306
 307         /* Return the first error reported. */
 308         return err ? err : err2;
 309 }
 310
 311 static int bcm54xx_config_init(struct phy_device *phydev)
 312 {
 313         int reg, err;
 314
 315         reg = phy_read(phydev, MII_BCM54XX_ECR);
 316         if (reg < 0)
 317                 return reg;
 318
 319         /* Mask interrupts globally.  */
 320         reg |= MII_BCM54XX_ECR_IM;
 321         err = phy_write(phydev, MII_BCM54XX_ECR, reg);
 322         if (err < 0)
 323                 return err;
 324
 325         /* Unmask events we are interested in.  */
 326         reg = ~(MII_BCM54XX_INT_DUPLEX |
 327                 MII_BCM54XX_INT_SPEED |
 328                 MII_BCM54XX_INT_LINK);
 329         err = phy_write(phydev, MII_BCM54XX_IMR, reg);
 330         if (err < 0)
 331                 return err;
 332
 333         bcm54xx_phydsp_config(phydev);
 334
 335         return 0;
 336 }
 337
 338 static int bcm5482_config_init(struct phy_device *phydev)
 339 {
 340         int err, reg;
 341
 342         err = bcm54xx_config_init(phydev);
 343
 344         if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {
 345                 /*
 346                  * Enable secondary SerDes and its use as an LED source
 347                  */
 348                 reg = bcm54xx_shadow_read(phydev, BCM5482_SHD_SSD);
 349                 bcm54xx_shadow_write(phydev, BCM5482_SHD_SSD,
 350                                      reg |
 351                                      BCM5482_SHD_SSD_LEDM |
 352                                      BCM5482_SHD_SSD_EN);
 353
 354                 /*
 355                  * Enable SGMII slave mode and auto-detection
 356                  */
 357                 reg = BCM5482_SSD_SGMII_SLAVE | MII_BCM54XX_EXP_SEL_SSD;
 358                 err = bcm54xx_exp_read(phydev, reg);
 359                 if (err < 0)
 360                         return err;
 361                 err = bcm54xx_exp_write(phydev, reg, err |
 362                                         BCM5482_SSD_SGMII_SLAVE_EN |
 363                                         BCM5482_SSD_SGMII_SLAVE_AD);
 364                 if (err < 0)
 365                         return err;
 366
 367                 /*
 368                  * Disable secondary SerDes powerdown
 369                  */
 370                 reg = BCM5482_SSD_1000BX_CTL | MII_BCM54XX_EXP_SEL_SSD;
 371                 err = bcm54xx_exp_read(phydev, reg);
 372                 if (err < 0)
 373                         return err;
 374                 err = bcm54xx_exp_write(phydev, reg,
 375                                         err & ~BCM5482_SSD_1000BX_CTL_PWRDOWN);
 376                 if (err < 0)
 377                         return err;
 378
 379                 /*
 380                  * Select 1000BASE-X register set (primary SerDes)
 381                  */
 382                 reg = bcm54xx_shadow_read(phydev, BCM5482_SHD_MODE);
 383                 bcm54xx_shadow_write(phydev, BCM5482_SHD_MODE,
 384                                      reg | BCM5482_SHD_MODE_1000BX);
 385
 386                 /*
 387                  * LED1=ACTIVITYLED, LED3=LINKSPD[2]
 388                  * (Use LED1 as secondary SerDes ACTIVITY LED)
 389                  */
 390                 bcm54xx_shadow_write(phydev, BCM5482_SHD_LEDS1,
 391                         BCM5482_SHD_LEDS1_LED1(BCM_LED_SRC_ACTIVITYLED) |
 392                         BCM5482_SHD_LEDS1_LED3(BCM_LED_SRC_LINKSPD2));
 393
 394                 /*
 395                  * Auto-negotiation doesn't seem to work quite right
 396                  * in this mode, so we disable it and force it to the
 397                  * right speed/duplex setting.  Only 'link status'
 398                  * is important.
 399                  */
 400                 phydev->autoneg = AUTONEG_DISABLE;
 401                 phydev->speed = SPEED_1000;
 402                 phydev->duplex = DUPLEX_FULL;
 403         }
 404
 405         return err;
 406 }
 407
 408 static int bcm5482_read_status(struct phy_device *phydev)
 409 {
 410         int err;
 411
 412         err = genphy_read_status(phydev);
 413
 414         if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {
 415                 /*
 416                  * Only link status matters for 1000Base-X mode, so force
 417                  * 1000 Mbit/s full-duplex status
 418                  */
 419                 if (phydev->link) {
 420                         phydev->speed = SPEED_1000;
 421                         phydev->duplex = DUPLEX_FULL;
 422                 }
 423         }
 424
 425         return err;
 426 }
 427
 428 static int bcm54xx_ack_interrupt(struct phy_device *phydev)
 429 {
 430         int reg;
 431
 432         /* Clear pending interrupts.  */
 433         reg = phy_read(phydev, MII_BCM54XX_ISR);
 434         if (reg < 0)
 435                 return reg;
 436
 437         return 0;
 438 }
 439
 440 static int bcm54xx_config_intr(struct phy_device *phydev)
 441 {
 442         int reg, err;
 443
 444         reg = phy_read(phydev, MII_BCM54XX_ECR);
 445         if (reg < 0)
 446                 return reg;
 447
 448         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 449                 reg &= ~MII_BCM54XX_ECR_IM;
 450         else
 451                 reg |= MII_BCM54XX_ECR_IM;
 452
 453         err = phy_write(phydev, MII_BCM54XX_ECR, reg);
 454         return err;
 455 }
 456
 457 static int bcm5481_config_aneg(struct phy_device *phydev)
 458 {
 459         int ret;
 460
 461         /* Aneg firsly. */
 462         ret = genphy_config_aneg(phydev);
 463
 464         /* Then we can set up the delay. */
 465         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
 466                 u16 reg;
 467
 468                 /*
 469                  * There is no BCM5481 specification available, so down
 470                  * here is everything we know about "register 0x18". This
 471                  * at least helps BCM5481 to successfuly receive packets
 472                  * on MPC8360E-RDK board. Peter Barada <peterb@logicpd.com>
 473                  * says: "This sets delay between the RXD and RXC signals
 474                  * instead of using trace lengths to achieve timing".
 475                  */
 476
 477                 /* Set RDX clk delay. */
 478                 reg = 0x7 | (0x7 << 12);
 479                 phy_write(phydev, 0x18, reg);
 480
 481                 reg = phy_read(phydev, 0x18);
 482                 /* Set RDX-RXC skew. */
 483                 reg |= (1 << 8);
 484                 /* Write bits 14:0. */
 485                 reg |= (1 << 15);
 486                 phy_write(phydev, 0x18, reg);
 487         }
 488
 489         return ret;
 490 }
 491
 492 static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)
 493 {
 494         int val;
 495
 496         val = phy_read(phydev, reg);
 497         if (val < 0)
 498                 return val;
 499
 500         return phy_write(phydev, reg, val | set);
 501 }
 502
 503 static int brcm_fet_config_init(struct phy_device *phydev)
 504 {
 505         int reg, err, err2, brcmtest;
 506
 507         /* Reset the PHY to bring it to a known state. */
 508         err = phy_write(phydev, MII_BMCR, BMCR_RESET);
 509         if (err < 0)
 510                 return err;
 511
 512         reg = phy_read(phydev, MII_BRCM_FET_INTREG);
 513         if (reg < 0)
 514                 return reg;
 515
 516         /* Unmask events we are interested in and mask interrupts globally. */
 517         reg = MII_BRCM_FET_IR_DUPLEX_EN |
 518               MII_BRCM_FET_IR_SPEED_EN |
 519               MII_BRCM_FET_IR_LINK_EN |
 520               MII_BRCM_FET_IR_ENABLE |
 521               MII_BRCM_FET_IR_MASK;
 522
 523         err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
 524         if (err < 0)
 525                 return err;
 526
 527         /* Enable shadow register access */
 528         brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST);
 529         if (brcmtest < 0)
 530                 return brcmtest;
 531
 532         reg = brcmtest | MII_BRCM_FET_BT_SRE;
 533
 534         err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg);
 535         if (err < 0)
 536                 return err;
 537
 538         /* Set the LED mode */
 539         reg = phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4);
 540         if (reg < 0) {
 541                 err = reg;
 542                 goto done;
 543         }
 544
 545         reg &= ~MII_BRCM_FET_SHDW_AM4_LED_MASK;
 546         reg |= MII_BRCM_FET_SHDW_AM4_LED_MODE1;
 547
 548         err = phy_write(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg);
 549         if (err < 0)
 550                 goto done;
 551
 552         /* Enable auto MDIX */
 553         err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_MISCCTRL,
 554                                        MII_BRCM_FET_SHDW_MC_FAME);
 555         if (err < 0)
 556                 goto done;
 557
 558         /* Enable auto power down */
 559         err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,
 560                                        MII_BRCM_FET_SHDW_AS2_APDE);
 561
 562 done:
 563         /* Disable shadow register access */
 564         err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest);
 565         if (!err)
 566                 err = err2;
 567
 568         return err;
 569 }
 570
 571 static int brcm_fet_ack_interrupt(struct phy_device *phydev)
 572 {
 573         int reg;
 574
 575         /* Clear pending interrupts.  */
 576         reg = phy_read(phydev, MII_BRCM_FET_INTREG);
 577         if (reg < 0)
 578                 return reg;
 579
 580         return 0;
 581 }
 582
 583 static int brcm_fet_config_intr(struct phy_device *phydev)
 584 {
 585         int reg, err;
 586
 587         reg = phy_read(phydev, MII_BRCM_FET_INTREG);
 588         if (reg < 0)
 589                 return reg;
 590
 591         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 592                 reg &= ~MII_BRCM_FET_IR_MASK;
 593         else
 594                 reg |= MII_BRCM_FET_IR_MASK;
 595
 596         err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
 597         return err;
 598 }
 599
 600 static struct phy_driver bcm5411_driver = {
 601         .phy_id         = 0x00206070,
 602         .phy_id_mask    = 0xfffffff0,
 603         .name           = "Broadcom BCM5411",
 604         .features       = PHY_GBIT_FEATURES |
 605                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 606         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 607         .config_init    = bcm54xx_config_init,
 608         .config_aneg    = genphy_config_aneg,
 609         .read_status    = genphy_read_status,
 610         .ack_interrupt  = bcm54xx_ack_interrupt,
 611         .config_intr    = bcm54xx_config_intr,
 612         .driver         = { .owner = THIS_MODULE },
 613 };
 614
 615 static struct phy_driver bcm5421_driver = {
 616         .phy_id         = 0x002060e0,
 617         .phy_id_mask    = 0xfffffff0,
 618         .name           = "Broadcom BCM5421",
 619         .features       = PHY_GBIT_FEATURES |
 620                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 621         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 622         .config_init    = bcm54xx_config_init,
 623         .config_aneg    = genphy_config_aneg,
 624         .read_status    = genphy_read_status,
 625         .ack_interrupt  = bcm54xx_ack_interrupt,
 626         .config_intr    = bcm54xx_config_intr,
 627         .driver         = { .owner = THIS_MODULE },
 628 };
 629
 630 static struct phy_driver bcm5461_driver = {
 631         .phy_id         = 0x002060c0,
 632         .phy_id_mask    = 0xfffffff0,
 633         .name           = "Broadcom BCM5461",
 634         .features       = PHY_GBIT_FEATURES |
 635                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 636         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 637         .config_init    = bcm54xx_config_init,
 638         .config_aneg    = genphy_config_aneg,
 639         .read_status    = genphy_read_status,
 640         .ack_interrupt  = bcm54xx_ack_interrupt,
 641         .config_intr    = bcm54xx_config_intr,
 642         .driver         = { .owner = THIS_MODULE },
 643 };
 644
 645 static struct phy_driver bcm5464_driver = {
 646         .phy_id         = 0x002060b0,
 647         .phy_id_mask    = 0xfffffff0,
 648         .name           = "Broadcom BCM5464",
 649         .features       = PHY_GBIT_FEATURES |
 650                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 651         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 652         .config_init    = bcm54xx_config_init,
 653         .config_aneg    = genphy_config_aneg,
 654         .read_status    = genphy_read_status,
 655         .ack_interrupt  = bcm54xx_ack_interrupt,
 656         .config_intr    = bcm54xx_config_intr,
 657         .driver         = { .owner = THIS_MODULE },
 658 };
 659
 660 static struct phy_driver bcm5481_driver = {
 661         .phy_id         = 0x0143bca0,
 662         .phy_id_mask    = 0xfffffff0,
 663         .name           = "Broadcom BCM5481",
 664         .features       = PHY_GBIT_FEATURES |
 665                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 666         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 667         .config_init    = bcm54xx_config_init,
 668         .config_aneg    = bcm5481_config_aneg,
 669         .read_status    = genphy_read_status,
 670         .ack_interrupt  = bcm54xx_ack_interrupt,
 671         .config_intr    = bcm54xx_config_intr,
 672         .driver         = { .owner = THIS_MODULE },
 673 };
 674
 675 static struct phy_driver bcm5482_driver = {
 676         .phy_id         = 0x0143bcb0,
 677         .phy_id_mask    = 0xfffffff0,
 678         .name           = "Broadcom BCM5482",
 679         .features       = PHY_GBIT_FEATURES |
 680                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 681         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 682         .config_init    = bcm5482_config_init,
 683         .config_aneg    = genphy_config_aneg,
 684         .read_status    = bcm5482_read_status,
 685         .ack_interrupt  = bcm54xx_ack_interrupt,
 686         .config_intr    = bcm54xx_config_intr,
 687         .driver         = { .owner = THIS_MODULE },
 688 };
 689
 690 static struct phy_driver bcm50610_driver = {
 691         .phy_id         = PHY_ID_BCM50610,
 692         .phy_id_mask    = 0xfffffff0,
 693         .name           = "Broadcom BCM50610",
 694         .features       = PHY_GBIT_FEATURES |
 695                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 696         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 697         .config_init    = bcm54xx_config_init,
 698         .config_aneg    = genphy_config_aneg,
 699         .read_status    = genphy_read_status,
 700         .ack_interrupt  = bcm54xx_ack_interrupt,
 701         .config_intr    = bcm54xx_config_intr,
 702         .driver         = { .owner = THIS_MODULE },
 703 };
 704
 705 static struct phy_driver bcm50610m_driver = {
 706         .phy_id         = PHY_ID_BCM50610M,
 707         .phy_id_mask    = 0xfffffff0,
 708         .name           = "Broadcom BCM50610M",
 709         .features       = PHY_GBIT_FEATURES |
 710                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 711         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 712         .config_init    = bcm54xx_config_init,
 713         .config_aneg    = genphy_config_aneg,
 714         .read_status    = genphy_read_status,
 715         .ack_interrupt  = bcm54xx_ack_interrupt,
 716         .config_intr    = bcm54xx_config_intr,
 717         .driver         = { .owner = THIS_MODULE },
 718 };
 719
 720 static struct phy_driver bcm57780_driver = {
 721         .phy_id         = PHY_ID_BCM57780,
 722         .phy_id_mask    = 0xfffffff0,
 723         .name           = "Broadcom BCM57780",
 724         .features       = PHY_GBIT_FEATURES |
 725                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 726         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 727         .config_init    = bcm54xx_config_init,
 728         .config_aneg    = genphy_config_aneg,
 729         .read_status    = genphy_read_status,
 730         .ack_interrupt  = bcm54xx_ack_interrupt,
 731         .config_intr    = bcm54xx_config_intr,
 732         .driver         = { .owner = THIS_MODULE },
 733 };
 734
 735 static struct phy_driver bcmac131_driver = {
 736         .phy_id         = 0x0143bc70,
 737         .phy_id_mask    = 0xfffffff0,
 738         .name           = "Broadcom BCMAC131",
 739         .features       = PHY_BASIC_FEATURES |
 740                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 741         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 742         .config_init    = brcm_fet_config_init,
 743         .config_aneg    = genphy_config_aneg,
 744         .read_status    = genphy_read_status,
 745         .ack_interrupt  = brcm_fet_ack_interrupt,
 746         .config_intr    = brcm_fet_config_intr,
 747         .driver         = { .owner = THIS_MODULE },
 748 };
 749
 750 static int __init broadcom_init(void)
 751 {
 752         int ret;
 753
 754         ret = phy_driver_register(&bcm5411_driver);
 755         if (ret)
 756                 goto out_5411;
 757         ret = phy_driver_register(&bcm5421_driver);
 758         if (ret)
 759                 goto out_5421;
 760         ret = phy_driver_register(&bcm5461_driver);
 761         if (ret)
 762                 goto out_5461;
 763         ret = phy_driver_register(&bcm5464_driver);
 764         if (ret)
 765                 goto out_5464;
 766         ret = phy_driver_register(&bcm5481_driver);
 767         if (ret)
 768                 goto out_5481;
 769         ret = phy_driver_register(&bcm5482_driver);
 770         if (ret)
 771                 goto out_5482;
 772         ret = phy_driver_register(&bcm50610_driver);
 773         if (ret)
 774                 goto out_50610;
 775         ret = phy_driver_register(&bcm50610m_driver);
 776         if (ret)
 777                 goto out_50610m;
 778         ret = phy_driver_register(&bcm57780_driver);
 779         if (ret)
 780                 goto out_57780;
 781         ret = phy_driver_register(&bcmac131_driver);
 782         if (ret)
 783                 goto out_ac131;
 784         return ret;
 785
 786 out_ac131:
 787         phy_driver_unregister(&bcm57780_driver);
 788 out_57780:
 789         phy_driver_unregister(&bcm50610m_driver);
 790 out_50610m:
 791         phy_driver_unregister(&bcm50610_driver);
 792 out_50610:
 793         phy_driver_unregister(&bcm5482_driver);
 794 out_5482:
 795         phy_driver_unregister(&bcm5481_driver);
 796 out_5481:
 797         phy_driver_unregister(&bcm5464_driver);
 798 out_5464:
 799         phy_driver_unregister(&bcm5461_driver);
 800 out_5461:
 801         phy_driver_unregister(&bcm5421_driver);
 802 out_5421:
 803         phy_driver_unregister(&bcm5411_driver);
 804 out_5411:
 805         return ret;
 806 }
 807
 808 static void __exit broadcom_exit(void)
 809 {
 810         phy_driver_unregister(&bcmac131_driver);
 811         phy_driver_unregister(&bcm57780_driver);
 812         phy_driver_unregister(&bcm50610m_driver);
 813         phy_driver_unregister(&bcm50610_driver);
 814         phy_driver_unregister(&bcm5482_driver);
 815         phy_driver_unregister(&bcm5481_driver);
 816         phy_driver_unregister(&bcm5464_driver);
 817         phy_driver_unregister(&bcm5461_driver);
 818         phy_driver_unregister(&bcm5421_driver);
 819         phy_driver_unregister(&bcm5411_driver);
 820 }
 821
 822 module_init(broadcom_init);
 823 module_exit(broadcom_exit);