drivers/net/qla3xxx.h

   1 /*
   2  * QLogic QLA3xxx NIC HBA Driver
   3  * Copyright (c)  2003-2006 QLogic Corporation
   4  *
   5  * See LICENSE.qla3xxx for copyright and licensing details.
   6  */
   7 #ifndef _QLA3XXX_H_
   8 #define _QLA3XXX_H_
   9
  10 /*
  11  * IOCB Definitions...
  12  */
  13 #pragma pack(1)
  14
  15 #define OPCODE_OB_MAC_IOCB_FN0          0x01
  16 #define OPCODE_OB_MAC_IOCB_FN2          0x21
  17 #define OPCODE_OB_TCP_IOCB_FN0          0x03
  18 #define OPCODE_OB_TCP_IOCB_FN2          0x23
  19 #define OPCODE_UPDATE_NCB_IOCB_FN0      0x00
  20 #define OPCODE_UPDATE_NCB_IOCB_FN2      0x20
  21
  22 #define OPCODE_UPDATE_NCB_IOCB      0xF0
  23 #define OPCODE_IB_MAC_IOCB          0xF9
  24 #define OPCODE_IB_3032_MAC_IOCB     0x09
  25 #define OPCODE_IB_IP_IOCB           0xFA
  26 #define OPCODE_IB_3032_IP_IOCB      0x0A
  27 #define OPCODE_IB_TCP_IOCB          0xFB
  28 #define OPCODE_DUMP_PROTO_IOCB      0xFE
  29 #define OPCODE_BUFFER_ALERT_IOCB    0xFB
  30
  31 #define OPCODE_FUNC_ID_MASK                 0x30
  32 #define OUTBOUND_MAC_IOCB                   0x01        /* plus function bits */
  33 #define OUTBOUND_TCP_IOCB                   0x03        /* plus function bits */
  34 #define UPDATE_NCB_IOCB                     0x00        /* plus function bits */
  35
  36 #define FN0_MA_BITS_MASK    0x00
  37 #define FN1_MA_BITS_MASK    0x80
  38
  39 struct ob_mac_iocb_req {
  40         u8 opcode;
  41         u8 flags;
  42 #define OB_MAC_IOCB_REQ_MA  0xe0
  43 #define OB_MAC_IOCB_REQ_F   0x10
  44 #define OB_MAC_IOCB_REQ_X   0x08
  45 #define OB_MAC_IOCB_REQ_D   0x02
  46 #define OB_MAC_IOCB_REQ_I   0x01
  47         u8 flags1;
  48 #define OB_3032MAC_IOCB_REQ_IC  0x04
  49 #define OB_3032MAC_IOCB_REQ_TC  0x02
  50 #define OB_3032MAC_IOCB_REQ_UC  0x01
  51         u8 reserved0;
  52
  53         __le32 transaction_id;
  54         __le16 data_len;
  55         u8 ip_hdr_off;
  56         u8 ip_hdr_len;
  57         __le32 reserved1;
  58         __le32 reserved2;
  59         __le32 buf_addr0_low;
  60         __le32 buf_addr0_high;
  61         __le32 buf_0_len;
  62         __le32 buf_addr1_low;
  63         __le32 buf_addr1_high;
  64         __le32 buf_1_len;
  65         __le32 buf_addr2_low;
  66         __le32 buf_addr2_high;
  67         __le32 buf_2_len;
  68         __le32 reserved3;
  69         __le32 reserved4;
  70 };
  71 /*
  72  * The following constants define control bits for buffer
  73  * length fields for all IOCB's.
  74  */
  75 #define OB_MAC_IOCB_REQ_E   0x80000000  /* Last valid buffer in list. */
  76 #define OB_MAC_IOCB_REQ_C   0x40000000  /* points to an OAL. (continuation) */
  77 #define OB_MAC_IOCB_REQ_L   0x20000000  /* Auburn local address pointer. */
  78 #define OB_MAC_IOCB_REQ_R   0x10000000  /* 32-bit address pointer. */
  79
  80 struct ob_mac_iocb_rsp {
  81         u8 opcode;
  82         u8 flags;
  83 #define OB_MAC_IOCB_RSP_P   0x08
  84 #define OB_MAC_IOCB_RSP_L   0x04
  85 #define OB_MAC_IOCB_RSP_S   0x02
  86 #define OB_MAC_IOCB_RSP_I   0x01
  87
  88         __le16 reserved0;
  89         __le32 transaction_id;
  90         __le32 reserved1;
  91         __le32 reserved2;
  92 };
  93
  94 struct ib_mac_iocb_rsp {
  95         u8 opcode;
  96 #define IB_MAC_IOCB_RSP_V   0x80
  97         u8 flags;
  98 #define IB_MAC_IOCB_RSP_S   0x80
  99 #define IB_MAC_IOCB_RSP_H1  0x40
 100 #define IB_MAC_IOCB_RSP_H0  0x20
 101 #define IB_MAC_IOCB_RSP_B   0x10
 102 #define IB_MAC_IOCB_RSP_M   0x08
 103 #define IB_MAC_IOCB_RSP_MA  0x07
 104
 105         __le16 length;
 106         __le32 reserved;
 107         __le32 ial_low;
 108         __le32 ial_high;
 109
 110 };
 111
 112 struct ob_ip_iocb_req {
 113         u8 opcode;
 114         __le16 flags;
 115 #define OB_IP_IOCB_REQ_O        0x100
 116 #define OB_IP_IOCB_REQ_H        0x008
 117 #define OB_IP_IOCB_REQ_U        0x004
 118 #define OB_IP_IOCB_REQ_D        0x002
 119 #define OB_IP_IOCB_REQ_I        0x001
 120
 121         u8 reserved0;
 122
 123         __le32 transaction_id;
 124         __le16 data_len;
 125         __le16 reserved1;
 126         __le32 hncb_ptr_low;
 127         __le32 hncb_ptr_high;
 128         __le32 buf_addr0_low;
 129         __le32 buf_addr0_high;
 130         __le32 buf_0_len;
 131         __le32 buf_addr1_low;
 132         __le32 buf_addr1_high;
 133         __le32 buf_1_len;
 134         __le32 buf_addr2_low;
 135         __le32 buf_addr2_high;
 136         __le32 buf_2_len;
 137         __le32 reserved2;
 138         __le32 reserved3;
 139 };
 140
 141 /* defines for BufferLength fields above */
 142 #define OB_IP_IOCB_REQ_E    0x80000000
 143 #define OB_IP_IOCB_REQ_C    0x40000000
 144 #define OB_IP_IOCB_REQ_L    0x20000000
 145 #define OB_IP_IOCB_REQ_R    0x10000000
 146
 147 struct ob_ip_iocb_rsp {
 148         u8 opcode;
 149         u8 flags;
 150 #define OB_MAC_IOCB_RSP_H       0x10
 151 #define OB_MAC_IOCB_RSP_E       0x08
 152 #define OB_MAC_IOCB_RSP_L       0x04
 153 #define OB_MAC_IOCB_RSP_S       0x02
 154 #define OB_MAC_IOCB_RSP_I       0x01
 155
 156         __le16 reserved0;
 157         __le32 transaction_id;
 158         __le32 reserved1;
 159         __le32 reserved2;
 160 };
 161
 162 struct ob_tcp_iocb_req {
 163         u8 opcode;
 164
 165         u8 flags0;
 166 #define OB_TCP_IOCB_REQ_P       0x80
 167 #define OB_TCP_IOCB_REQ_CI      0x20
 168 #define OB_TCP_IOCB_REQ_H       0x10
 169 #define OB_TCP_IOCB_REQ_LN      0x08
 170 #define OB_TCP_IOCB_REQ_K       0x04
 171 #define OB_TCP_IOCB_REQ_D       0x02
 172 #define OB_TCP_IOCB_REQ_I       0x01
 173
 174         u8 flags1;
 175 #define OB_TCP_IOCB_REQ_OSM     0x40
 176 #define OB_TCP_IOCB_REQ_URG     0x20
 177 #define OB_TCP_IOCB_REQ_ACK     0x10
 178 #define OB_TCP_IOCB_REQ_PSH     0x08
 179 #define OB_TCP_IOCB_REQ_RST     0x04
 180 #define OB_TCP_IOCB_REQ_SYN     0x02
 181 #define OB_TCP_IOCB_REQ_FIN     0x01
 182
 183         u8 options_len;
 184 #define OB_TCP_IOCB_REQ_OMASK   0xF0
 185 #define OB_TCP_IOCB_REQ_SHIFT   4
 186
 187         __le32 transaction_id;
 188         __le32 data_len;
 189         __le32 hncb_ptr_low;
 190         __le32 hncb_ptr_high;
 191         __le32 buf_addr0_low;
 192         __le32 buf_addr0_high;
 193         __le32 buf_0_len;
 194         __le32 buf_addr1_low;
 195         __le32 buf_addr1_high;
 196         __le32 buf_1_len;
 197         __le32 buf_addr2_low;
 198         __le32 buf_addr2_high;
 199         __le32 buf_2_len;
 200         __le32 time_stamp;
 201         __le32 reserved1;
 202 };
 203
 204 struct ob_tcp_iocb_rsp {
 205         u8 opcode;
 206
 207         u8 flags0;
 208 #define OB_TCP_IOCB_RSP_C       0x20
 209 #define OB_TCP_IOCB_RSP_H       0x10
 210 #define OB_TCP_IOCB_RSP_LN      0x08
 211 #define OB_TCP_IOCB_RSP_K       0x04
 212 #define OB_TCP_IOCB_RSP_D       0x02
 213 #define OB_TCP_IOCB_RSP_I       0x01
 214
 215         u8 flags1;
 216 #define OB_TCP_IOCB_RSP_E       0x10
 217 #define OB_TCP_IOCB_RSP_W       0x08
 218 #define OB_TCP_IOCB_RSP_P       0x04
 219 #define OB_TCP_IOCB_RSP_T       0x02
 220 #define OB_TCP_IOCB_RSP_F       0x01
 221
 222         u8 state;
 223 #define OB_TCP_IOCB_RSP_SMASK   0xF0
 224 #define OB_TCP_IOCB_RSP_SHIFT   4
 225
 226         __le32 transaction_id;
 227         __le32 local_ncb_ptr;
 228         __le32 reserved0;
 229 };
 230
 231 struct ib_ip_iocb_rsp {
 232         u8 opcode;
 233 #define IB_IP_IOCB_RSP_3032_V   0x80
 234 #define IB_IP_IOCB_RSP_3032_O   0x40
 235 #define IB_IP_IOCB_RSP_3032_I   0x20
 236 #define IB_IP_IOCB_RSP_3032_R   0x10
 237         u8 flags;
 238 #define IB_IP_IOCB_RSP_S        0x80
 239 #define IB_IP_IOCB_RSP_H1       0x40
 240 #define IB_IP_IOCB_RSP_H0       0x20
 241 #define IB_IP_IOCB_RSP_B        0x10
 242 #define IB_IP_IOCB_RSP_M        0x08
 243 #define IB_IP_IOCB_RSP_MA       0x07
 244
 245         __le16 length;
 246         __le16 checksum;
 247 #define IB_IP_IOCB_RSP_3032_ICE         0x01
 248 #define IB_IP_IOCB_RSP_3032_CE          0x02
 249 #define IB_IP_IOCB_RSP_3032_NUC         0x04
 250 #define IB_IP_IOCB_RSP_3032_UDP         0x08
 251 #define IB_IP_IOCB_RSP_3032_TCP         0x10
 252 #define IB_IP_IOCB_RSP_3032_IPE         0x20
 253         __le16 reserved;
 254 #define IB_IP_IOCB_RSP_R        0x01
 255         __le32 ial_low;
 256         __le32 ial_high;
 257 };
 258
 259 struct ib_tcp_iocb_rsp {
 260         u8 opcode;
 261         u8 flags;
 262 #define IB_TCP_IOCB_RSP_P       0x80
 263 #define IB_TCP_IOCB_RSP_T       0x40
 264 #define IB_TCP_IOCB_RSP_D       0x20
 265 #define IB_TCP_IOCB_RSP_N       0x10
 266 #define IB_TCP_IOCB_RSP_IP      0x03
 267 #define IB_TCP_FLAG_MASK        0xf0
 268 #define IB_TCP_FLAG_IOCB_SYN    0x00
 269
 270 #define TCP_IB_RSP_FLAGS(x) (x->flags & ~IB_TCP_FLAG_MASK)
 271
 272         __le16 length;
 273         __le32 hncb_ref_num;
 274         __le32 ial_low;
 275         __le32 ial_high;
 276 };
 277
 278 struct net_rsp_iocb {
 279         u8 opcode;
 280         u8 flags;
 281         __le16 reserved0;
 282         __le32 reserved[3];
 283 };
 284 #pragma pack()
 285
 286 /*
 287  * Register Definitions...
 288  */
 289 #define PORT0_PHY_ADDRESS   0x1e00
 290 #define PORT1_PHY_ADDRESS   0x1f00
 291
 292 #define ETHERNET_CRC_SIZE   4
 293
 294 #define MII_SCAN_REGISTER 0x00000001
 295
 296 /* 32-bit ispControlStatus */
 297 enum {
 298         ISP_CONTROL_NP_MASK = 0x0003,
 299         ISP_CONTROL_NP_PCSR = 0x0000,
 300         ISP_CONTROL_NP_HMCR = 0x0001,
 301         ISP_CONTROL_NP_LRAMCR = 0x0002,
 302         ISP_CONTROL_NP_PSR = 0x0003,
 303         ISP_CONTROL_RI = 0x0008,
 304         ISP_CONTROL_CI = 0x0010,
 305         ISP_CONTROL_PI = 0x0020,
 306         ISP_CONTROL_IN = 0x0040,
 307         ISP_CONTROL_BE = 0x0080,
 308         ISP_CONTROL_FN_MASK = 0x0700,
 309         ISP_CONTROL_FN0_NET = 0x0400,
 310         ISP_CONTROL_FN0_SCSI = 0x0500,
 311         ISP_CONTROL_FN1_NET = 0x0600,
 312         ISP_CONTROL_FN1_SCSI = 0x0700,
 313         ISP_CONTROL_LINK_DN_0 = 0x0800,
 314         ISP_CONTROL_LINK_DN_1 = 0x1000,
 315         ISP_CONTROL_FSR = 0x2000,
 316         ISP_CONTROL_FE = 0x4000,
 317         ISP_CONTROL_SR = 0x8000,
 318 };
 319
 320 /* 32-bit ispInterruptMaskReg */
 321 enum {
 322         ISP_IMR_ENABLE_INT = 0x0004,
 323         ISP_IMR_DISABLE_RESET_INT = 0x0008,
 324         ISP_IMR_DISABLE_CMPL_INT = 0x0010,
 325         ISP_IMR_DISABLE_PROC_INT = 0x0020,
 326 };
 327
 328 /* 32-bit serialPortInterfaceReg */
 329 enum {
 330         ISP_SERIAL_PORT_IF_CLK = 0x0001,
 331         ISP_SERIAL_PORT_IF_CS = 0x0002,
 332         ISP_SERIAL_PORT_IF_D0 = 0x0004,
 333         ISP_SERIAL_PORT_IF_DI = 0x0008,
 334         ISP_NVRAM_MASK = (0x000F << 16),
 335         ISP_SERIAL_PORT_IF_WE = 0x0010,
 336         ISP_SERIAL_PORT_IF_NVR_MASK = 0x001F,
 337         ISP_SERIAL_PORT_IF_SCI = 0x0400,
 338         ISP_SERIAL_PORT_IF_SC0 = 0x0800,
 339         ISP_SERIAL_PORT_IF_SCE = 0x1000,
 340         ISP_SERIAL_PORT_IF_SDI = 0x2000,
 341         ISP_SERIAL_PORT_IF_SDO = 0x4000,
 342         ISP_SERIAL_PORT_IF_SDE = 0x8000,
 343         ISP_SERIAL_PORT_IF_I2C_MASK = 0xFC00,
 344 };
 345
 346 /* semaphoreReg */
 347 enum {
 348         QL_RESOURCE_MASK_BASE_CODE = 0x7,
 349         QL_RESOURCE_BITS_BASE_CODE = 0x4,
 350         QL_DRVR_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 1),
 351         QL_DDR_RAM_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 4),
 352         QL_PHY_GIO_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 7),
 353         QL_NVRAM_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 10),
 354         QL_FLASH_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 13),
 355         QL_DRVR_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (1 + 16)),
 356         QL_DDR_RAM_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (4 + 16)),
 357         QL_PHY_GIO_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (7 + 16)),
 358         QL_NVRAM_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (10 + 16)),
 359         QL_FLASH_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (13 + 16)),
 360 };
 361
 362  /*
 363   * QL3XXX memory-mapped registers
 364   * QL3XXX has 4 "pages" of registers, each page occupying
 365   * 256 bytes.  Each page has a "common" area at the start and then
 366   * page-specific registers after that.
 367   */
 368 struct ql3xxx_common_registers {
 369         u32 MB0;                /* Offset 0x00 */
 370         u32 MB1;                /* Offset 0x04 */
 371         u32 MB2;                /* Offset 0x08 */
 372         u32 MB3;                /* Offset 0x0c */
 373         u32 MB4;                /* Offset 0x10 */
 374         u32 MB5;                /* Offset 0x14 */
 375         u32 MB6;                /* Offset 0x18 */
 376         u32 MB7;                /* Offset 0x1c */
 377         u32 flashBiosAddr;
 378         u32 flashBiosData;
 379         u32 ispControlStatus;
 380         u32 ispInterruptMaskReg;
 381         u32 serialPortInterfaceReg;
 382         u32 semaphoreReg;
 383         u32 reqQProducerIndex;
 384         u32 rspQConsumerIndex;
 385
 386         u32 rxLargeQProducerIndex;
 387         u32 rxSmallQProducerIndex;
 388         u32 arcMadiCommand;
 389         u32 arcMadiData;
 390 };
 391
 392 enum {
 393         EXT_HW_CONFIG_SP_MASK = 0x0006,
 394         EXT_HW_CONFIG_SP_NONE = 0x0000,
 395         EXT_HW_CONFIG_SP_BYTE_PARITY = 0x0002,
 396         EXT_HW_CONFIG_SP_ECC = 0x0004,
 397         EXT_HW_CONFIG_SP_ECCx = 0x0006,
 398         EXT_HW_CONFIG_SIZE_MASK = 0x0060,
 399         EXT_HW_CONFIG_SIZE_128M = 0x0000,
 400         EXT_HW_CONFIG_SIZE_256M = 0x0020,
 401         EXT_HW_CONFIG_SIZE_512M = 0x0040,
 402         EXT_HW_CONFIG_SIZE_INVALID = 0x0060,
 403         EXT_HW_CONFIG_PD = 0x0080,
 404         EXT_HW_CONFIG_FW = 0x0200,
 405         EXT_HW_CONFIG_US = 0x0400,
 406         EXT_HW_CONFIG_DCS_MASK = 0x1800,
 407         EXT_HW_CONFIG_DCS_9MA = 0x0000,
 408         EXT_HW_CONFIG_DCS_15MA = 0x0800,
 409         EXT_HW_CONFIG_DCS_18MA = 0x1000,
 410         EXT_HW_CONFIG_DCS_24MA = 0x1800,
 411         EXT_HW_CONFIG_DDS_MASK = 0x6000,
 412         EXT_HW_CONFIG_DDS_9MA = 0x0000,
 413         EXT_HW_CONFIG_DDS_15MA = 0x2000,
 414         EXT_HW_CONFIG_DDS_18MA = 0x4000,
 415         EXT_HW_CONFIG_DDS_24MA = 0x6000,
 416 };
 417
 418 /* InternalChipConfig */
 419 enum {
 420         INTERNAL_CHIP_DM = 0x0001,
 421         INTERNAL_CHIP_SD = 0x0002,
 422         INTERNAL_CHIP_RAP_MASK = 0x000C,
 423         INTERNAL_CHIP_RAP_RR = 0x0000,
 424         INTERNAL_CHIP_RAP_NRM = 0x0004,
 425         INTERNAL_CHIP_RAP_ERM = 0x0008,
 426         INTERNAL_CHIP_RAP_ERMx = 0x000C,
 427         INTERNAL_CHIP_WE = 0x0010,
 428         INTERNAL_CHIP_EF = 0x0020,
 429         INTERNAL_CHIP_FR = 0x0040,
 430         INTERNAL_CHIP_FW = 0x0080,
 431         INTERNAL_CHIP_FI = 0x0100,
 432         INTERNAL_CHIP_FT = 0x0200,
 433 };
 434
 435 /* portControl */
 436 enum {
 437         PORT_CONTROL_DS = 0x0001,
 438         PORT_CONTROL_HH = 0x0002,
 439         PORT_CONTROL_EI = 0x0004,
 440         PORT_CONTROL_ET = 0x0008,
 441         PORT_CONTROL_EF = 0x0010,
 442         PORT_CONTROL_DRM = 0x0020,
 443         PORT_CONTROL_RLB = 0x0040,
 444         PORT_CONTROL_RCB = 0x0080,
 445         PORT_CONTROL_MAC = 0x0100,
 446         PORT_CONTROL_IPV = 0x0200,
 447         PORT_CONTROL_IFP = 0x0400,
 448         PORT_CONTROL_ITP = 0x0800,
 449         PORT_CONTROL_FI = 0x1000,
 450         PORT_CONTROL_DFP = 0x2000,
 451         PORT_CONTROL_OI = 0x4000,
 452         PORT_CONTROL_CC = 0x8000,
 453 };
 454
 455 /* portStatus */
 456 enum {
 457         PORT_STATUS_SM0 = 0x0001,
 458         PORT_STATUS_SM1 = 0x0002,
 459         PORT_STATUS_X = 0x0008,
 460         PORT_STATUS_DL = 0x0080,
 461         PORT_STATUS_IC = 0x0200,
 462         PORT_STATUS_MRC = 0x0400,
 463         PORT_STATUS_NL = 0x0800,
 464         PORT_STATUS_REV_ID_MASK = 0x7000,
 465         PORT_STATUS_REV_ID_1 = 0x1000,
 466         PORT_STATUS_REV_ID_2 = 0x2000,
 467         PORT_STATUS_REV_ID_3 = 0x3000,
 468         PORT_STATUS_64 = 0x8000,
 469         PORT_STATUS_UP0 = 0x10000,
 470         PORT_STATUS_AC0 = 0x20000,
 471         PORT_STATUS_AE0 = 0x40000,
 472         PORT_STATUS_UP1 = 0x100000,
 473         PORT_STATUS_AC1 = 0x200000,
 474         PORT_STATUS_AE1 = 0x400000,
 475         PORT_STATUS_F0_ENABLED = 0x1000000,
 476         PORT_STATUS_F1_ENABLED = 0x2000000,
 477         PORT_STATUS_F2_ENABLED = 0x4000000,
 478         PORT_STATUS_F3_ENABLED = 0x8000000,
 479 };
 480
 481 /* macMIIMgmtControlReg */
 482 enum {
 483         MAC_ADDR_INDIRECT_PTR_REG_RP_MASK = 0x0003,
 484         MAC_ADDR_INDIRECT_PTR_REG_RP_PRI_LWR = 0x0000,
 485         MAC_ADDR_INDIRECT_PTR_REG_RP_PRI_UPR = 0x0001,
 486         MAC_ADDR_INDIRECT_PTR_REG_RP_SEC_LWR = 0x0002,
 487         MAC_ADDR_INDIRECT_PTR_REG_RP_SEC_UPR = 0x0003,
 488         MAC_ADDR_INDIRECT_PTR_REG_PR = 0x0008,
 489         MAC_ADDR_INDIRECT_PTR_REG_SS = 0x0010,
 490         MAC_ADDR_INDIRECT_PTR_REG_SE = 0x0020,
 491         MAC_ADDR_INDIRECT_PTR_REG_SP = 0x0040,
 492         MAC_ADDR_INDIRECT_PTR_REG_PE = 0x0080,
 493 };
 494
 495 /* macMIIMgmtControlReg */
 496 enum {
 497         MAC_MII_CONTROL_RC = 0x0001,
 498         MAC_MII_CONTROL_SC = 0x0002,
 499         MAC_MII_CONTROL_AS = 0x0004,
 500         MAC_MII_CONTROL_NP = 0x0008,
 501         MAC_MII_CONTROL_CLK_SEL_MASK = 0x0070,
 502         MAC_MII_CONTROL_CLK_SEL_DIV2 = 0x0000,
 503         MAC_MII_CONTROL_CLK_SEL_DIV4 = 0x0010,
 504         MAC_MII_CONTROL_CLK_SEL_DIV6 = 0x0020,
 505         MAC_MII_CONTROL_CLK_SEL_DIV8 = 0x0030,
 506         MAC_MII_CONTROL_CLK_SEL_DIV10 = 0x0040,
 507         MAC_MII_CONTROL_CLK_SEL_DIV14 = 0x0050,
 508         MAC_MII_CONTROL_CLK_SEL_DIV20 = 0x0060,
 509         MAC_MII_CONTROL_CLK_SEL_DIV28 = 0x0070,
 510         MAC_MII_CONTROL_RM = 0x8000,
 511 };
 512
 513 /* macMIIStatusReg */
 514 enum {
 515         MAC_MII_STATUS_BSY = 0x0001,
 516         MAC_MII_STATUS_SC = 0x0002,
 517         MAC_MII_STATUS_NV = 0x0004,
 518 };
 519
 520 enum {
 521         MAC_CONFIG_REG_PE = 0x0001,
 522         MAC_CONFIG_REG_TF = 0x0002,
 523         MAC_CONFIG_REG_RF = 0x0004,
 524         MAC_CONFIG_REG_FD = 0x0008,
 525         MAC_CONFIG_REG_GM = 0x0010,
 526         MAC_CONFIG_REG_LB = 0x0020,
 527         MAC_CONFIG_REG_SR = 0x8000,
 528 };
 529
 530 enum {
 531         MAC_HALF_DUPLEX_REG_ED = 0x10000,
 532         MAC_HALF_DUPLEX_REG_NB = 0x20000,
 533         MAC_HALF_DUPLEX_REG_BNB = 0x40000,
 534         MAC_HALF_DUPLEX_REG_ALT = 0x80000,
 535 };
 536
 537 enum {
 538         IP_ADDR_INDEX_REG_MASK = 0x000f,
 539         IP_ADDR_INDEX_REG_FUNC_0_PRI = 0x0000,
 540         IP_ADDR_INDEX_REG_FUNC_0_SEC = 0x0001,
 541         IP_ADDR_INDEX_REG_FUNC_1_PRI = 0x0002,
 542         IP_ADDR_INDEX_REG_FUNC_1_SEC = 0x0003,
 543         IP_ADDR_INDEX_REG_FUNC_2_PRI = 0x0004,
 544         IP_ADDR_INDEX_REG_FUNC_2_SEC = 0x0005,
 545         IP_ADDR_INDEX_REG_FUNC_3_PRI = 0x0006,
 546         IP_ADDR_INDEX_REG_FUNC_3_SEC = 0x0007,
 547         IP_ADDR_INDEX_REG_6 = 0x0008,
 548         IP_ADDR_INDEX_REG_OFFSET_MASK = 0x0030,
 549         IP_ADDR_INDEX_REG_E = 0x0040,
 550 };
 551 enum {
 552         QL3032_PORT_CONTROL_DS = 0x0001,
 553         QL3032_PORT_CONTROL_HH = 0x0002,
 554         QL3032_PORT_CONTROL_EIv6 = 0x0004,
 555         QL3032_PORT_CONTROL_EIv4 = 0x0008,
 556         QL3032_PORT_CONTROL_ET = 0x0010,
 557         QL3032_PORT_CONTROL_EF = 0x0020,
 558         QL3032_PORT_CONTROL_DRM = 0x0040,
 559         QL3032_PORT_CONTROL_RLB = 0x0080,
 560         QL3032_PORT_CONTROL_RCB = 0x0100,
 561         QL3032_PORT_CONTROL_KIE = 0x0200,
 562 };
 563
 564 enum {
 565         PROBE_MUX_ADDR_REG_MUX_SEL_MASK = 0x003f,
 566         PROBE_MUX_ADDR_REG_SYSCLK = 0x0000,
 567         PROBE_MUX_ADDR_REG_PCICLK = 0x0040,
 568         PROBE_MUX_ADDR_REG_NRXCLK = 0x0080,
 569         PROBE_MUX_ADDR_REG_CPUCLK = 0x00C0,
 570         PROBE_MUX_ADDR_REG_MODULE_SEL_MASK = 0x3f00,
 571         PROBE_MUX_ADDR_REG_UP = 0x4000,
 572         PROBE_MUX_ADDR_REG_RE = 0x8000,
 573 };
 574
 575 enum {
 576         STATISTICS_INDEX_REG_MASK = 0x01ff,
 577         STATISTICS_INDEX_REG_MAC0_TX_FRAME = 0x0000,
 578         STATISTICS_INDEX_REG_MAC0_TX_BYTES = 0x0001,
 579         STATISTICS_INDEX_REG_MAC0_TX_STAT1 = 0x0002,
 580         STATISTICS_INDEX_REG_MAC0_TX_STAT2 = 0x0003,
 581         STATISTICS_INDEX_REG_MAC0_TX_STAT3 = 0x0004,
 582         STATISTICS_INDEX_REG_MAC0_TX_STAT4 = 0x0005,
 583         STATISTICS_INDEX_REG_MAC0_TX_STAT5 = 0x0006,
 584         STATISTICS_INDEX_REG_MAC0_RX_FRAME = 0x0007,
 585         STATISTICS_INDEX_REG_MAC0_RX_BYTES = 0x0008,
 586         STATISTICS_INDEX_REG_MAC0_RX_STAT1 = 0x0009,
 587         STATISTICS_INDEX_REG_MAC0_RX_STAT2 = 0x000a,
 588         STATISTICS_INDEX_REG_MAC0_RX_STAT3 = 0x000b,
 589         STATISTICS_INDEX_REG_MAC0_RX_ERR_CRC = 0x000c,
 590         STATISTICS_INDEX_REG_MAC0_RX_ERR_ENC = 0x000d,
 591         STATISTICS_INDEX_REG_MAC0_RX_ERR_LEN = 0x000e,
 592         STATISTICS_INDEX_REG_MAC0_RX_STAT4 = 0x000f,
 593         STATISTICS_INDEX_REG_MAC1_TX_FRAME = 0x0010,
 594         STATISTICS_INDEX_REG_MAC1_TX_BYTES = 0x0011,
 595         STATISTICS_INDEX_REG_MAC1_TX_STAT1 = 0x0012,
 596         STATISTICS_INDEX_REG_MAC1_TX_STAT2 = 0x0013,
 597         STATISTICS_INDEX_REG_MAC1_TX_STAT3 = 0x0014,
 598         STATISTICS_INDEX_REG_MAC1_TX_STAT4 = 0x0015,
 599         STATISTICS_INDEX_REG_MAC1_TX_STAT5 = 0x0016,
 600         STATISTICS_INDEX_REG_MAC1_RX_FRAME = 0x0017,
 601         STATISTICS_INDEX_REG_MAC1_RX_BYTES = 0x0018,
 602         STATISTICS_INDEX_REG_MAC1_RX_STAT1 = 0x0019,
 603         STATISTICS_INDEX_REG_MAC1_RX_STAT2 = 0x001a,
 604         STATISTICS_INDEX_REG_MAC1_RX_STAT3 = 0x001b,
 605         STATISTICS_INDEX_REG_MAC1_RX_ERR_CRC = 0x001c,
 606         STATISTICS_INDEX_REG_MAC1_RX_ERR_ENC = 0x001d,
 607         STATISTICS_INDEX_REG_MAC1_RX_ERR_LEN = 0x001e,
 608         STATISTICS_INDEX_REG_MAC1_RX_STAT4 = 0x001f,
 609         STATISTICS_INDEX_REG_IP_TX_PKTS = 0x0020,
 610         STATISTICS_INDEX_REG_IP_TX_BYTES = 0x0021,
 611         STATISTICS_INDEX_REG_IP_TX_FRAG = 0x0022,
 612         STATISTICS_INDEX_REG_IP_RX_PKTS = 0x0023,
 613         STATISTICS_INDEX_REG_IP_RX_BYTES = 0x0024,
 614         STATISTICS_INDEX_REG_IP_RX_FRAG = 0x0025,
 615         STATISTICS_INDEX_REG_IP_DGRM_REASSEMBLY = 0x0026,
 616         STATISTICS_INDEX_REG_IP_V6_RX_PKTS = 0x0027,
 617         STATISTICS_INDEX_REG_IP_RX_PKTERR = 0x0028,
 618         STATISTICS_INDEX_REG_IP_REASSEMBLY_ERR = 0x0029,
 619         STATISTICS_INDEX_REG_TCP_TX_SEG = 0x0030,
 620         STATISTICS_INDEX_REG_TCP_TX_BYTES = 0x0031,
 621         STATISTICS_INDEX_REG_TCP_RX_SEG = 0x0032,
 622         STATISTICS_INDEX_REG_TCP_RX_BYTES = 0x0033,
 623         STATISTICS_INDEX_REG_TCP_TIMER_EXP = 0x0034,
 624         STATISTICS_INDEX_REG_TCP_RX_ACK = 0x0035,
 625         STATISTICS_INDEX_REG_TCP_TX_ACK = 0x0036,
 626         STATISTICS_INDEX_REG_TCP_RX_ERR = 0x0037,
 627         STATISTICS_INDEX_REG_TCP_RX_WIN_PROBE = 0x0038,
 628         STATISTICS_INDEX_REG_TCP_ECC_ERR_CORR = 0x003f,
 629 };
 630
 631 enum {
 632         PORT_FATAL_ERROR_STATUS_OFB_RE_MAC0 = 0x00000001,
 633         PORT_FATAL_ERROR_STATUS_OFB_RE_MAC1 = 0x00000002,
 634         PORT_FATAL_ERROR_STATUS_OFB_WE = 0x00000004,
 635         PORT_FATAL_ERROR_STATUS_IFB_RE = 0x00000008,
 636         PORT_FATAL_ERROR_STATUS_IFB_WE_MAC0 = 0x00000010,
 637         PORT_FATAL_ERROR_STATUS_IFB_WE_MAC1 = 0x00000020,
 638         PORT_FATAL_ERROR_STATUS_ODE_RE = 0x00000040,
 639         PORT_FATAL_ERROR_STATUS_ODE_WE = 0x00000080,
 640         PORT_FATAL_ERROR_STATUS_IDE_RE = 0x00000100,
 641         PORT_FATAL_ERROR_STATUS_IDE_WE = 0x00000200,
 642         PORT_FATAL_ERROR_STATUS_SDE_RE = 0x00000400,
 643         PORT_FATAL_ERROR_STATUS_SDE_WE = 0x00000800,
 644         PORT_FATAL_ERROR_STATUS_BLE = 0x00001000,
 645         PORT_FATAL_ERROR_STATUS_SPE = 0x00002000,
 646         PORT_FATAL_ERROR_STATUS_EP0 = 0x00004000,
 647         PORT_FATAL_ERROR_STATUS_EP1 = 0x00008000,
 648         PORT_FATAL_ERROR_STATUS_ICE = 0x00010000,
 649         PORT_FATAL_ERROR_STATUS_ILE = 0x00020000,
 650         PORT_FATAL_ERROR_STATUS_OPE = 0x00040000,
 651         PORT_FATAL_ERROR_STATUS_TA = 0x00080000,
 652         PORT_FATAL_ERROR_STATUS_MA = 0x00100000,
 653         PORT_FATAL_ERROR_STATUS_SCE = 0x00200000,
 654         PORT_FATAL_ERROR_STATUS_RPE = 0x00400000,
 655         PORT_FATAL_ERROR_STATUS_MPE = 0x00800000,
 656         PORT_FATAL_ERROR_STATUS_OCE = 0x01000000,
 657 };
 658
 659 /*
 660  *  port control and status page - page 0
 661  */
 662
 663 struct ql3xxx_port_registers {
 664         struct ql3xxx_common_registers CommonRegs;
 665
 666         u32 ExternalHWConfig;
 667         u32 InternalChipConfig;
 668         u32 portControl;
 669         u32 portStatus;
 670         u32 macAddrIndirectPtrReg;
 671         u32 macAddrDataReg;
 672         u32 macMIIMgmtControlReg;
 673         u32 macMIIMgmtAddrReg;
 674         u32 macMIIMgmtDataReg;
 675         u32 macMIIStatusReg;
 676         u32 mac0ConfigReg;
 677         u32 mac0IpgIfgReg;
 678         u32 mac0HalfDuplexReg;
 679         u32 mac0MaxFrameLengthReg;
 680         u32 mac0PauseThresholdReg;
 681         u32 mac1ConfigReg;
 682         u32 mac1IpgIfgReg;
 683         u32 mac1HalfDuplexReg;
 684         u32 mac1MaxFrameLengthReg;
 685         u32 mac1PauseThresholdReg;
 686         u32 ipAddrIndexReg;
 687         u32 ipAddrDataReg;
 688         u32 ipReassemblyTimeout;
 689         u32 tcpMaxWindow;
 690         u32 currentTcpTimestamp[2];
 691         u32 internalRamRWAddrReg;
 692         u32 internalRamWDataReg;
 693         u32 reclaimedBufferAddrRegLow;
 694         u32 reclaimedBufferAddrRegHigh;
 695         u32 tcpConfiguration;
 696         u32 functionControl;
 697         u32 fpgaRevID;
 698         u32 localRamAddr;
 699         u32 localRamDataAutoIncr;
 700         u32 localRamDataNonIncr;
 701         u32 gpOutput;
 702         u32 gpInput;
 703         u32 probeMuxAddr;
 704         u32 probeMuxData;
 705         u32 statisticsIndexReg;
 706         u32 statisticsReadDataRegAutoIncr;
 707         u32 statisticsReadDataRegNoIncr;
 708         u32 PortFatalErrStatus;
 709 };
 710
 711 /*
 712  * port host memory config page - page 1
 713  */
 714 struct ql3xxx_host_memory_registers {
 715         struct ql3xxx_common_registers CommonRegs;
 716
 717         u32 reserved[12];
 718
 719         /* Network Request Queue */
 720         u32 reqConsumerIndex;
 721         u32 reqConsumerIndexAddrLow;
 722         u32 reqConsumerIndexAddrHigh;
 723         u32 reqBaseAddrLow;
 724         u32 reqBaseAddrHigh;
 725         u32 reqLength;
 726
 727         /* Network Completion Queue */
 728         u32 rspProducerIndex;
 729         u32 rspProducerIndexAddrLow;
 730         u32 rspProducerIndexAddrHigh;
 731         u32 rspBaseAddrLow;
 732         u32 rspBaseAddrHigh;
 733         u32 rspLength;
 734
 735         /* RX Large Buffer Queue */
 736         u32 rxLargeQConsumerIndex;
 737         u32 rxLargeQBaseAddrLow;
 738         u32 rxLargeQBaseAddrHigh;
 739         u32 rxLargeQLength;
 740         u32 rxLargeBufferLength;
 741
 742         /* RX Small Buffer Queue */
 743         u32 rxSmallQConsumerIndex;
 744         u32 rxSmallQBaseAddrLow;
 745         u32 rxSmallQBaseAddrHigh;
 746         u32 rxSmallQLength;
 747         u32 rxSmallBufferLength;
 748
 749 };
 750
 751 /*
 752  *  port local RAM page - page 2
 753  */
 754 struct ql3xxx_local_ram_registers {
 755         struct ql3xxx_common_registers CommonRegs;
 756         u32 bufletSize;
 757         u32 maxBufletCount;
 758         u32 currentBufletCount;
 759         u32 reserved;
 760         u32 freeBufletThresholdLow;
 761         u32 freeBufletThresholdHigh;
 762         u32 ipHashTableBase;
 763         u32 ipHashTableCount;
 764         u32 tcpHashTableBase;
 765         u32 tcpHashTableCount;
 766         u32 ncbBase;
 767         u32 maxNcbCount;
 768         u32 currentNcbCount;
 769         u32 drbBase;
 770         u32 maxDrbCount;
 771         u32 currentDrbCount;
 772 };
 773
 774 /*
 775  * definitions for Semaphore bits in Semaphore/Serial NVRAM interface register
 776  */
 777
 778 #define LS_64BITS(x)    (u32)(0xffffffff & ((u64)x))
 779 #define MS_64BITS(x)    (u32)(0xffffffff & (((u64)x)>>16>>16) )
 780
 781 /*
 782  * I/O register
 783  */
 784
 785 enum {
 786         CONTROL_REG = 0,
 787         STATUS_REG = 1,
 788         PHY_STAT_LINK_UP = 0x0004,
 789         PHY_CTRL_LOOPBACK = 0x4000,
 790
 791         PETBI_CONTROL_REG = 0x00,
 792         PETBI_CTRL_SOFT_RESET = 0x8000,
 793         PETBI_CTRL_AUTO_NEG = 0x1000,
 794         PETBI_CTRL_RESTART_NEG = 0x0200,
 795         PETBI_CTRL_FULL_DUPLEX = 0x0100,
 796         PETBI_CTRL_SPEED_1000 = 0x0040,
 797
 798         PETBI_STATUS_REG = 0x01,
 799         PETBI_STAT_NEG_DONE = 0x0020,
 800         PETBI_STAT_LINK_UP = 0x0004,
 801
 802         PETBI_NEG_ADVER = 0x04,
 803         PETBI_NEG_PAUSE = 0x0080,
 804         PETBI_NEG_PAUSE_MASK = 0x0180,
 805         PETBI_NEG_DUPLEX = 0x0020,
 806         PETBI_NEG_DUPLEX_MASK = 0x0060,
 807
 808         PETBI_NEG_PARTNER = 0x05,
 809         PETBI_NEG_ERROR_MASK = 0x3000,
 810
 811         PETBI_EXPANSION_REG = 0x06,
 812         PETBI_EXP_PAGE_RX = 0x0002,
 813
 814         PETBI_TBI_CTRL = 0x11,
 815         PETBI_TBI_RESET = 0x8000,
 816         PETBI_TBI_AUTO_SENSE = 0x0100,
 817         PETBI_TBI_SERDES_MODE = 0x0010,
 818         PETBI_TBI_SERDES_WRAP = 0x0002,
 819
 820         AUX_CONTROL_STATUS = 0x1c,
 821         PHY_AUX_NEG_DONE = 0x8000,
 822         PHY_NEG_PARTNER = 5,
 823         PHY_AUX_DUPLEX_STAT = 0x0020,
 824         PHY_AUX_SPEED_STAT = 0x0018,
 825         PHY_AUX_NO_HW_STRAP = 0x0004,
 826         PHY_AUX_RESET_STICK = 0x0002,
 827         PHY_NEG_PAUSE = 0x0400,
 828         PHY_CTRL_SOFT_RESET = 0x8000,
 829         PHY_NEG_ADVER = 4,
 830         PHY_NEG_ADV_SPEED = 0x01e0,
 831         PHY_CTRL_RESTART_NEG = 0x0200,
 832 };
 833 enum {
 834 /* AM29LV Flash definitions     */
 835         FM93C56A_START = 0x1,
 836 /* Commands */
 837         FM93C56A_READ = 0x2,
 838         FM93C56A_WEN = 0x0,
 839         FM93C56A_WRITE = 0x1,
 840         FM93C56A_WRITE_ALL = 0x0,
 841         FM93C56A_WDS = 0x0,
 842         FM93C56A_ERASE = 0x3,
 843         FM93C56A_ERASE_ALL = 0x0,
 844 /* Command Extentions */
 845         FM93C56A_WEN_EXT = 0x3,
 846         FM93C56A_WRITE_ALL_EXT = 0x1,
 847         FM93C56A_WDS_EXT = 0x0,
 848         FM93C56A_ERASE_ALL_EXT = 0x2,
 849 /* Special Bits */
 850         FM93C56A_READ_DUMMY_BITS = 1,
 851         FM93C56A_READY = 0,
 852         FM93C56A_BUSY = 1,
 853         FM93C56A_CMD_BITS = 2,
 854 /* AM29LV Flash definitions     */
 855         FM93C56A_SIZE_8 = 0x100,
 856         FM93C56A_SIZE_16 = 0x80,
 857         FM93C66A_SIZE_8 = 0x200,
 858         FM93C66A_SIZE_16 = 0x100,
 859         FM93C86A_SIZE_16 = 0x400,
 860 /* Address Bits */
 861         FM93C56A_NO_ADDR_BITS_16 = 8,
 862         FM93C56A_NO_ADDR_BITS_8 = 9,
 863         FM93C86A_NO_ADDR_BITS_16 = 10,
 864 /* Data Bits */
 865         FM93C56A_DATA_BITS_16 = 16,
 866         FM93C56A_DATA_BITS_8 = 8,
 867 };
 868 enum {
 869 /* Auburn Bits */
 870             AUBURN_EEPROM_DI = 0x8,
 871         AUBURN_EEPROM_DI_0 = 0x0,
 872         AUBURN_EEPROM_DI_1 = 0x8,
 873         AUBURN_EEPROM_DO = 0x4,
 874         AUBURN_EEPROM_DO_0 = 0x0,
 875         AUBURN_EEPROM_DO_1 = 0x4,
 876         AUBURN_EEPROM_CS = 0x2,
 877         AUBURN_EEPROM_CS_0 = 0x0,
 878         AUBURN_EEPROM_CS_1 = 0x2,
 879         AUBURN_EEPROM_CLK_RISE = 0x1,
 880         AUBURN_EEPROM_CLK_FALL = 0x0,
 881 };
 882 enum {EEPROM_SIZE = FM93C86A_SIZE_16,
 883         EEPROM_NO_ADDR_BITS = FM93C86A_NO_ADDR_BITS_16,
 884         EEPROM_NO_DATA_BITS = FM93C56A_DATA_BITS_16,
 885 };
 886
 887 /*
 888  *  MAC Config data structure
 889  */
 890     struct eeprom_port_cfg {
 891         u16 etherMtu_mac;
 892         u16 pauseThreshold_mac;
 893         u16 resumeThreshold_mac;
 894         u16 portConfiguration;
 895 #define PORT_CONFIG_AUTO_NEG_ENABLED        0x8000
 896 #define PORT_CONFIG_SYM_PAUSE_ENABLED       0x4000
 897 #define PORT_CONFIG_FULL_DUPLEX_ENABLED     0x2000
 898 #define PORT_CONFIG_HALF_DUPLEX_ENABLED     0x1000
 899 #define PORT_CONFIG_1000MB_SPEED            0x0400
 900 #define PORT_CONFIG_100MB_SPEED             0x0200
 901 #define PORT_CONFIG_10MB_SPEED              0x0100
 902 #define PORT_CONFIG_LINK_SPEED_MASK         0x0F00
 903         u16 reserved[12];
 904
 905 };
 906
 907 /*
 908  * BIOS data structure
 909  */
 910 struct eeprom_bios_cfg {
 911         u16 SpinDlyEn:1, disBios:1, EnMemMap:1, EnSelectBoot:1, Reserved:12;
 912
 913         u8 bootID0:7, boodID0Valid:1;
 914         u8 bootLun0[8];
 915
 916         u8 bootID1:7, boodID1Valid:1;
 917         u8 bootLun1[8];
 918
 919         u16 MaxLunsTrgt;
 920         u8 reserved[10];
 921 };
 922
 923 /*
 924  *  Function Specific Data structure
 925  */
 926 struct eeprom_function_cfg {
 927         u8 reserved[30];
 928         u8 macAddress[6];
 929         u8 macAddressSecondary[6];
 930
 931         u16 subsysVendorId;
 932         u16 subsysDeviceId;
 933 };
 934
 935 /*
 936  *  EEPROM format
 937  */
 938 struct eeprom_data {
 939         u8 asicId[4];
 940         u8 version;
 941         u8 numPorts;
 942         u16 boardId;
 943
 944 #define EEPROM_BOARDID_STR_SIZE   16
 945 #define EEPROM_SERIAL_NUM_SIZE    16
 946
 947         u8 boardIdStr[16];
 948         u8 serialNumber[16];
 949         u16 extHwConfig;
 950         struct eeprom_port_cfg macCfg_port0;
 951         struct eeprom_port_cfg macCfg_port1;
 952         u16 bufletSize;
 953         u16 bufletCount;
 954         u16 tcpWindowThreshold50;
 955         u16 tcpWindowThreshold25;
 956         u16 tcpWindowThreshold0;
 957         u16 ipHashTableBaseHi;
 958         u16 ipHashTableBaseLo;
 959         u16 ipHashTableSize;
 960         u16 tcpHashTableBaseHi;
 961         u16 tcpHashTableBaseLo;
 962         u16 tcpHashTableSize;
 963         u16 ncbTableBaseHi;
 964         u16 ncbTableBaseLo;
 965         u16 ncbTableSize;
 966         u16 drbTableBaseHi;
 967         u16 drbTableBaseLo;
 968         u16 drbTableSize;
 969         u16 reserved_142[4];
 970         u16 ipReassemblyTimeout;
 971         u16 tcpMaxWindowSize;
 972         u16 ipSecurity;
 973 #define IPSEC_CONFIG_PRESENT 0x0001
 974         u8 reserved_156[294];
 975         u16 qDebug[8];
 976         struct eeprom_function_cfg funcCfg_fn0;
 977         u16 reserved_510;
 978         u8 oemSpace[432];
 979         struct eeprom_bios_cfg biosCfg_fn1;
 980         struct eeprom_function_cfg funcCfg_fn1;
 981         u16 reserved_1022;
 982         u8 reserved_1024[464];
 983         struct eeprom_function_cfg funcCfg_fn2;
 984         u16 reserved_1534;
 985         u8 reserved_1536[432];
 986         struct eeprom_bios_cfg biosCfg_fn3;
 987         struct eeprom_function_cfg funcCfg_fn3;
 988         u16 checksum;
 989 };
 990
 991 /*
 992  * General definitions...
 993  */
 994
 995 /*
 996  * Below are a number compiler switches for controlling driver behavior.
 997  * Some are not supported under certain conditions and are notated as such.
 998  */
 999
1000 #define QL3XXX_VENDOR_ID    0x1077
1001 #define QL3022_DEVICE_ID    0x3022
1002 #define QL3032_DEVICE_ID    0x3032
1003
1004 /* MTU & Frame Size stuff */
1005 #define NORMAL_MTU_SIZE                 ETH_DATA_LEN
1006 #define JUMBO_MTU_SIZE                  9000
1007 #define VLAN_ID_LEN                         2
1008
1009 /* Request Queue Related Definitions */
1010 #define NUM_REQ_Q_ENTRIES   256 /* so that 64 * 64  = 4096 (1 page) */
1011
1012 /* Response Queue Related Definitions */
1013 #define NUM_RSP_Q_ENTRIES   256 /* so that 256 * 16  = 4096 (1 page) */
1014
1015 /* Transmit and Receive Buffers */
1016 #define NUM_LBUFQ_ENTRIES       128
1017 #define JUMBO_NUM_LBUFQ_ENTRIES 32
1018 #define NUM_SBUFQ_ENTRIES       64
1019 #define QL_SMALL_BUFFER_SIZE    32
1020 #define QL_ADDR_ELE_PER_BUFQ_ENTRY \
1021 (sizeof(struct lrg_buf_q_entry) / sizeof(struct bufq_addr_element))
1022     /* Each send has at least control block.  This is how many we keep. */
1023 #define NUM_SMALL_BUFFERS       NUM_SBUFQ_ENTRIES * QL_ADDR_ELE_PER_BUFQ_ENTRY
1024
1025 #define QL_HEADER_SPACE 32      /* make header space at top of skb. */
1026 /*
1027  * Large & Small Buffers for Receives
1028  */
1029 struct lrg_buf_q_entry {
1030
1031         u32 addr0_lower;
1032 #define IAL_LAST_ENTRY 0x00000001
1033 #define IAL_CONT_ENTRY 0x00000002
1034 #define IAL_FLAG_MASK  0x00000003
1035         u32 addr0_upper;
1036         u32 addr1_lower;
1037         u32 addr1_upper;
1038         u32 addr2_lower;
1039         u32 addr2_upper;
1040         u32 addr3_lower;
1041         u32 addr3_upper;
1042         u32 addr4_lower;
1043         u32 addr4_upper;
1044         u32 addr5_lower;
1045         u32 addr5_upper;
1046         u32 addr6_lower;
1047         u32 addr6_upper;
1048         u32 addr7_lower;
1049         u32 addr7_upper;
1050
1051 };
1052
1053 struct bufq_addr_element {
1054         u32 addr_low;
1055         u32 addr_high;
1056 };
1057
1058 #define QL_NO_RESET                     0
1059 #define QL_DO_RESET                     1
1060
1061 enum link_state_t {
1062         LS_UNKNOWN = 0,
1063         LS_DOWN,
1064         LS_DEGRADE,
1065         LS_RECOVER,
1066         LS_UP,
1067 };
1068
1069 struct ql_rcv_buf_cb {
1070         struct ql_rcv_buf_cb *next;
1071         struct sk_buff *skb;
1072          DECLARE_PCI_UNMAP_ADDR(mapaddr);
1073          DECLARE_PCI_UNMAP_LEN(maplen);
1074         __le32 buf_phy_addr_low;
1075         __le32 buf_phy_addr_high;
1076         int index;
1077 };
1078
1079 /*
1080  * Original IOCB has 3 sg entries:
1081  * first points to skb-data area
1082  * second points to first frag
1083  * third points to next oal.
1084  * OAL has 5 entries:
1085  * 1 thru 4 point to frags
1086  * fifth points to next oal.
1087  */
1088 #define MAX_OAL_CNT ((MAX_SKB_FRAGS-1)/4 + 1)
1089
1090 struct oal_entry {
1091         u32 dma_lo;
1092         u32 dma_hi;
1093         u32 len;
1094 #define OAL_LAST_ENTRY   0x80000000     /* Last valid buffer in list. */
1095 #define OAL_CONT_ENTRY   0x40000000     /* points to an OAL. (continuation) */
1096 };
1097
1098 struct oal {
1099         struct oal_entry oal_entry[5];
1100 };
1101
1102 struct map_list {
1103          DECLARE_PCI_UNMAP_ADDR(mapaddr);
1104          DECLARE_PCI_UNMAP_LEN(maplen);
1105 };
1106
1107 struct ql_tx_buf_cb {
1108         struct sk_buff *skb;
1109         struct ob_mac_iocb_req *queue_entry ;
1110         int seg_count;
1111         struct oal *oal;
1112         struct map_list map[MAX_SKB_FRAGS+1];
1113 };
1114
1115 /* definitions for type field */
1116 #define QL_BUF_TYPE_MACIOCB 0x01
1117 #define QL_BUF_TYPE_IPIOCB  0x02
1118 #define QL_BUF_TYPE_TCPIOCB 0x03
1119
1120 /* qdev->flags definitions. */
1121 enum { QL_RESET_DONE = 1,       /* Reset finished. */
1122         QL_RESET_ACTIVE = 2,    /* Waiting for reset to finish. */
1123         QL_RESET_START = 3,     /* Please reset the chip. */
1124         QL_RESET_PER_SCSI = 4,  /* SCSI driver requests reset. */
1125         QL_TX_TIMEOUT = 5,      /* Timeout in progress. */
1126         QL_LINK_MASTER = 6,     /* This driver controls the link. */
1127         QL_ADAPTER_UP = 7,      /* Adapter has been brought up. */
1128         QL_THREAD_UP = 8,       /* This flag is available. */
1129         QL_LINK_UP = 9, /* Link Status. */
1130         QL_ALLOC_REQ_RSP_Q_DONE = 10,
1131         QL_ALLOC_BUFQS_DONE = 11,
1132         QL_ALLOC_SMALL_BUF_DONE = 12,
1133         QL_LINK_OPTICAL = 13,
1134         QL_MSI_ENABLED = 14,
1135 };
1136
1137 /*
1138  * ql3_adapter - The main Adapter structure definition.
1139  * This structure has all fields relevant to the hardware.
1140  */
1141
1142 struct ql3_adapter {
1143         u32 reserved_00;
1144         unsigned long flags;
1145
1146         /* PCI Configuration information for this device */
1147         struct pci_dev *pdev;
1148         struct net_device *ndev;        /* Parent NET device */
1149
1150         /* Hardware information */
1151         u8 chip_rev_id;
1152         u8 pci_slot;
1153         u8 pci_width;
1154         u8 pci_x;
1155         u32 msi;
1156         int index;
1157         struct timer_list adapter_timer;        /* timer used for various functions */
1158
1159         spinlock_t adapter_lock;
1160         spinlock_t hw_lock;
1161
1162         /* PCI Bus Relative Register Addresses */
1163         u8 __iomem *mmap_virt_base;     /* stores return value from ioremap() */
1164         struct ql3xxx_port_registers __iomem *mem_map_registers;
1165         u32 current_page;       /* tracks current register page */
1166
1167         u32 msg_enable;
1168         u8 reserved_01[2];
1169         u8 reserved_02[2];
1170
1171         /* Page for Shadow Registers */
1172         void *shadow_reg_virt_addr;
1173         dma_addr_t shadow_reg_phy_addr;
1174
1175         /* Net Request Queue */
1176         u32 req_q_size;
1177         u32 reserved_03;
1178         struct ob_mac_iocb_req *req_q_virt_addr;
1179         dma_addr_t req_q_phy_addr;
1180         u16 req_producer_index;
1181         u16 reserved_04;
1182         u16 *preq_consumer_index;
1183         u32 req_consumer_index_phy_addr_high;
1184         u32 req_consumer_index_phy_addr_low;
1185         atomic_t tx_count;
1186         struct ql_tx_buf_cb tx_buf[NUM_REQ_Q_ENTRIES];
1187
1188         /* Net Response Queue */
1189         u32 rsp_q_size;
1190         u32 eeprom_cmd_data;
1191         struct net_rsp_iocb *rsp_q_virt_addr;
1192         dma_addr_t rsp_q_phy_addr;
1193         struct net_rsp_iocb *rsp_current;
1194         u16 rsp_consumer_index;
1195         u16 reserved_06;
1196         volatile u32 *prsp_producer_index;
1197         u32 rsp_producer_index_phy_addr_high;
1198         u32 rsp_producer_index_phy_addr_low;
1199
1200         /* Large Buffer Queue */
1201         u32 lrg_buf_q_alloc_size;
1202         u32 lrg_buf_q_size;
1203         void *lrg_buf_q_alloc_virt_addr;
1204         void *lrg_buf_q_virt_addr;
1205         dma_addr_t lrg_buf_q_alloc_phy_addr;
1206         dma_addr_t lrg_buf_q_phy_addr;
1207         u32 lrg_buf_q_producer_index;
1208         u32 lrg_buf_release_cnt;
1209         struct bufq_addr_element *lrg_buf_next_free;
1210         u32 num_large_buffers;
1211         u32 num_lbufq_entries;
1212
1213         /* Large (Receive) Buffers */
1214         struct ql_rcv_buf_cb *lrg_buf;
1215         struct ql_rcv_buf_cb *lrg_buf_free_head;
1216         struct ql_rcv_buf_cb *lrg_buf_free_tail;
1217         u32 lrg_buf_free_count;
1218         u32 lrg_buffer_len;
1219         u32 lrg_buf_index;
1220         u32 lrg_buf_skb_check;
1221
1222         /* Small Buffer Queue */
1223         u32 small_buf_q_alloc_size;
1224         u32 small_buf_q_size;
1225         u32 small_buf_q_producer_index;
1226         void *small_buf_q_alloc_virt_addr;
1227         void *small_buf_q_virt_addr;
1228         dma_addr_t small_buf_q_alloc_phy_addr;
1229         dma_addr_t small_buf_q_phy_addr;
1230         u32 small_buf_index;
1231
1232         /* Small (Receive) Buffers */
1233         void *small_buf_virt_addr;
1234         dma_addr_t small_buf_phy_addr;
1235         u32 small_buf_phy_addr_low;
1236         u32 small_buf_phy_addr_high;
1237         u32 small_buf_release_cnt;
1238         u32 small_buf_total_size;
1239
1240         /* ISR related, saves status for DPC. */
1241         u32 control_status;
1242
1243         struct eeprom_data nvram_data;
1244         struct timer_list ioctl_timer;
1245         u32 port_link_state;
1246         u32 last_rsp_offset;
1247
1248         /* 4022 specific */
1249         u32 mac_index;          /* Driver's MAC number can be 0 or 1 for first and second networking functions respectively */
1250         u32 PHYAddr;            /* Address of PHY 0x1e00 Port 0 and 0x1f00 Port 1 */
1251         u32 mac_ob_opcode;      /* Opcode to use on mac transmission */
1252         u32 tcp_ob_opcode;      /* Opcode to use on tcp transmission */
1253         u32 update_ob_opcode;   /* Opcode to use for updating NCB */
1254         u32 mb_bit_mask;        /* MA Bits mask to use on transmission */
1255         u32 numPorts;
1256         struct net_device_stats stats;
1257         struct workqueue_struct *workqueue;
1258         struct delayed_work reset_work;
1259         struct delayed_work tx_timeout_work;
1260         u32 max_frame_size;
1261         u32 device_id;
1262 };
1263
1264 #endif                          /* _QLA3XXX_H_ */