drivers/net/qlcnic/qlcnic.h

   1 /*
   2  * QLogic qlcnic NIC Driver
   3  * Copyright (c)  2009-2010 QLogic Corporation
   4  *
   5  * See LICENSE.qlcnic for copyright and licensing details.
   6  */
   7
   8 #ifndef _QLCNIC_H_
   9 #define _QLCNIC_H_
  10
  11 #include <linux/module.h>
  12 #include <linux/kernel.h>
  13 #include <linux/types.h>
  14 #include <linux/ioport.h>
  15 #include <linux/pci.h>
  16 #include <linux/netdevice.h>
  17 #include <linux/etherdevice.h>
  18 #include <linux/ip.h>
  19 #include <linux/in.h>
  20 #include <linux/tcp.h>
  21 #include <linux/skbuff.h>
  22 #include <linux/firmware.h>
  23
  24 #include <linux/ethtool.h>
  25 #include <linux/mii.h>
  26 #include <linux/timer.h>
  27
  28 #include <linux/vmalloc.h>
  29
  30 #include <linux/io.h>
  31 #include <asm/byteorder.h>
  32 #include <linux/bitops.h>
  33 #include <linux/if_vlan.h>
  34
  35 #include "qlcnic_hdr.h"
  36
  37 #define _QLCNIC_LINUX_MAJOR 5
  38 #define _QLCNIC_LINUX_MINOR 0
  39 #define _QLCNIC_LINUX_SUBVERSION 20
  40 #define QLCNIC_LINUX_VERSIONID  "5.0.20"
  41 #define QLCNIC_DRV_IDC_VER  0x01
  42 #define QLCNIC_DRIVER_VERSION  ((_QLCNIC_LINUX_MAJOR << 16) |\
  43                  (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION))
  44
  45 #define QLCNIC_VERSION_CODE(a, b, c)    (((a) << 24) + ((b) << 16) + (c))
  46 #define _major(v)       (((v) >> 24) & 0xff)
  47 #define _minor(v)       (((v) >> 16) & 0xff)
  48 #define _build(v)       ((v) & 0xffff)
  49
  50 /* version in image has weird encoding:
  51  *  7:0  - major
  52  * 15:8  - minor
  53  * 31:16 - build (little endian)
  54  */
  55 #define QLCNIC_DECODE_VERSION(v) \
  56         QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
  57
  58 #define QLCNIC_MIN_FW_VERSION     QLCNIC_VERSION_CODE(4, 4, 2)
  59 #define QLCNIC_NUM_FLASH_SECTORS (64)
  60 #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024)
  61 #define QLCNIC_FLASH_TOTAL_SIZE  (QLCNIC_NUM_FLASH_SECTORS \
  62                                         * QLCNIC_FLASH_SECTOR_SIZE)
  63
  64 #define RCV_DESC_RINGSIZE(rds_ring)     \
  65         (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
  66 #define RCV_BUFF_RINGSIZE(rds_ring)     \
  67         (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc)
  68 #define STATUS_DESC_RINGSIZE(sds_ring)  \
  69         (sizeof(struct status_desc) * (sds_ring)->num_desc)
  70 #define TX_BUFF_RINGSIZE(tx_ring)       \
  71         (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc)
  72 #define TX_DESC_RINGSIZE(tx_ring)       \
  73         (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
  74
  75 #define QLCNIC_P3P_A0           0x50
  76
  77 #define QLCNIC_IS_REVISION_P3P(REVISION)     (REVISION >= QLCNIC_P3P_A0)
  78
  79 #define FIRST_PAGE_GROUP_START  0
  80 #define FIRST_PAGE_GROUP_END    0x100000
  81
  82 #define P3P_MAX_MTU                     (9600)
  83 #define P3P_MIN_MTU                     (68)
  84 #define QLCNIC_MAX_ETHERHDR                32 /* This contains some padding */
  85
  86 #define QLCNIC_P3P_RX_BUF_MAX_LEN         (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN)
  87 #define QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN   (QLCNIC_MAX_ETHERHDR + P3P_MAX_MTU)
  88 #define QLCNIC_CT_DEFAULT_RX_BUF_LEN    2048
  89 #define QLCNIC_LRO_BUFFER_EXTRA         2048
  90
  91 /* Opcodes to be used with the commands */
  92 #define TX_ETHER_PKT    0x01
  93 #define TX_TCP_PKT      0x02
  94 #define TX_UDP_PKT      0x03
  95 #define TX_IP_PKT       0x04
  96 #define TX_TCP_LSO      0x05
  97 #define TX_TCP_LSO6     0x06
  98 #define TX_TCPV6_PKT    0x0b
  99 #define TX_UDPV6_PKT    0x0c
 100
 101 /* Tx defines */
 102 #define QLCNIC_MAX_FRAGS_PER_TX 14
 103 #define MAX_TSO_HEADER_DESC     2
 104 #define MGMT_CMD_DESC_RESV      4
 105 #define TX_STOP_THRESH          ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \
 106                                                         + MGMT_CMD_DESC_RESV)
 107 #define QLCNIC_MAX_TX_TIMEOUTS  2
 108
 109 /*
 110  * Following are the states of the Phantom. Phantom will set them and
 111  * Host will read to check if the fields are correct.
 112  */
 113 #define PHAN_INITIALIZE_FAILED          0xffff
 114 #define PHAN_INITIALIZE_COMPLETE        0xff01
 115
 116 /* Host writes the following to notify that it has done the init-handshake */
 117 #define PHAN_INITIALIZE_ACK             0xf00f
 118 #define PHAN_PEG_RCV_INITIALIZED        0xff01
 119
 120 #define NUM_RCV_DESC_RINGS      3
 121
 122 #define RCV_RING_NORMAL 0
 123 #define RCV_RING_JUMBO  1
 124
 125 #define MIN_CMD_DESCRIPTORS             64
 126 #define MIN_RCV_DESCRIPTORS             64
 127 #define MIN_JUMBO_DESCRIPTORS           32
 128
 129 #define MAX_CMD_DESCRIPTORS             1024
 130 #define MAX_RCV_DESCRIPTORS_1G          4096
 131 #define MAX_RCV_DESCRIPTORS_10G         8192
 132 #define MAX_RCV_DESCRIPTORS_VF          2048
 133 #define MAX_JUMBO_RCV_DESCRIPTORS_1G    512
 134 #define MAX_JUMBO_RCV_DESCRIPTORS_10G   1024
 135
 136 #define DEFAULT_RCV_DESCRIPTORS_1G      2048
 137 #define DEFAULT_RCV_DESCRIPTORS_10G     4096
 138 #define DEFAULT_RCV_DESCRIPTORS_VF      1024
 139 #define MAX_RDS_RINGS                   2
 140
 141 #define get_next_index(index, length)   \
 142         (((index) + 1) & ((length) - 1))
 143
 144 /*
 145  * Following data structures describe the descriptors that will be used.
 146  * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
 147  * we are doing LSO (above the 1500 size packet) only.
 148  */
 149
 150 #define FLAGS_VLAN_TAGGED       0x10
 151 #define FLAGS_VLAN_OOB          0x40
 152
 153 #define qlcnic_set_tx_vlan_tci(cmd_desc, v)     \
 154         (cmd_desc)->vlan_TCI = cpu_to_le16(v);
 155 #define qlcnic_set_cmd_desc_port(cmd_desc, var) \
 156         ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
 157 #define qlcnic_set_cmd_desc_ctxid(cmd_desc, var)        \
 158         ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
 159
 160 #define qlcnic_set_tx_port(_desc, _port) \
 161         ((_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0))
 162
 163 #define qlcnic_set_tx_flags_opcode(_desc, _flags, _opcode) \
 164         ((_desc)->flags_opcode |= \
 165         cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7)))
 166
 167 #define qlcnic_set_tx_frags_len(_desc, _frags, _len) \
 168         ((_desc)->nfrags__length = \
 169         cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8)))
 170
 171 struct cmd_desc_type0 {
 172         u8 tcp_hdr_offset;      /* For LSO only */
 173         u8 ip_hdr_offset;       /* For LSO only */
 174         __le16 flags_opcode;    /* 15:13 unused, 12:7 opcode, 6:0 flags */
 175         __le32 nfrags__length;  /* 31:8 total len, 7:0 frag count */
 176
 177         __le64 addr_buffer2;
 178
 179         __le16 reference_handle;
 180         __le16 mss;
 181         u8 port_ctxid;          /* 7:4 ctxid 3:0 port */
 182         u8 total_hdr_length;    /* LSO only : MAC+IP+TCP Hdr size */
 183         __le16 conn_id;         /* IPSec offoad only */
 184
 185         __le64 addr_buffer3;
 186         __le64 addr_buffer1;
 187
 188         __le16 buffer_length[4];
 189
 190         __le64 addr_buffer4;
 191
 192         u8 eth_addr[ETH_ALEN];
 193         __le16 vlan_TCI;
 194
 195 } __attribute__ ((aligned(64)));
 196
 197 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
 198 struct rcv_desc {
 199         __le16 reference_handle;
 200         __le16 reserved;
 201         __le32 buffer_length;   /* allocated buffer length (usually 2K) */
 202         __le64 addr_buffer;
 203 } __packed;
 204
 205 /* opcode field in status_desc */
 206 #define QLCNIC_SYN_OFFLOAD      0x03
 207 #define QLCNIC_RXPKT_DESC       0x04
 208 #define QLCNIC_OLD_RXPKT_DESC   0x3f
 209 #define QLCNIC_RESPONSE_DESC    0x05
 210 #define QLCNIC_LRO_DESC         0x12
 211
 212 /* for status field in status_desc */
 213 #define STATUS_CKSUM_LOOP       0
 214 #define STATUS_CKSUM_OK         2
 215
 216 /* owner bits of status_desc */
 217 #define STATUS_OWNER_HOST       (0x1ULL << 56)
 218 #define STATUS_OWNER_PHANTOM    (0x2ULL << 56)
 219
 220 /* Status descriptor:
 221    0-3 port, 4-7 status, 8-11 type, 12-27 total_length
 222    28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
 223    53-55 desc_cnt, 56-57 owner, 58-63 opcode
 224  */
 225 #define qlcnic_get_sts_port(sts_data)   \
 226         ((sts_data) & 0x0F)
 227 #define qlcnic_get_sts_status(sts_data) \
 228         (((sts_data) >> 4) & 0x0F)
 229 #define qlcnic_get_sts_type(sts_data)   \
 230         (((sts_data) >> 8) & 0x0F)
 231 #define qlcnic_get_sts_totallength(sts_data)    \
 232         (((sts_data) >> 12) & 0xFFFF)
 233 #define qlcnic_get_sts_refhandle(sts_data)      \
 234         (((sts_data) >> 28) & 0xFFFF)
 235 #define qlcnic_get_sts_prot(sts_data)   \
 236         (((sts_data) >> 44) & 0x0F)
 237 #define qlcnic_get_sts_pkt_offset(sts_data)     \
 238         (((sts_data) >> 48) & 0x1F)
 239 #define qlcnic_get_sts_desc_cnt(sts_data)       \
 240         (((sts_data) >> 53) & 0x7)
 241 #define qlcnic_get_sts_opcode(sts_data) \
 242         (((sts_data) >> 58) & 0x03F)
 243
 244 #define qlcnic_get_lro_sts_refhandle(sts_data)  \
 245         ((sts_data) & 0x0FFFF)
 246 #define qlcnic_get_lro_sts_length(sts_data)     \
 247         (((sts_data) >> 16) & 0x0FFFF)
 248 #define qlcnic_get_lro_sts_l2_hdr_offset(sts_data)      \
 249         (((sts_data) >> 32) & 0x0FF)
 250 #define qlcnic_get_lro_sts_l4_hdr_offset(sts_data)      \
 251         (((sts_data) >> 40) & 0x0FF)
 252 #define qlcnic_get_lro_sts_timestamp(sts_data)  \
 253         (((sts_data) >> 48) & 0x1)
 254 #define qlcnic_get_lro_sts_type(sts_data)       \
 255         (((sts_data) >> 49) & 0x7)
 256 #define qlcnic_get_lro_sts_push_flag(sts_data)          \
 257         (((sts_data) >> 52) & 0x1)
 258 #define qlcnic_get_lro_sts_seq_number(sts_data)         \
 259         ((sts_data) & 0x0FFFFFFFF)
 260
 261
 262 struct status_desc {
 263         __le64 status_desc_data[2];
 264 } __attribute__ ((aligned(16)));
 265
 266 /* UNIFIED ROMIMAGE */
 267 #define QLCNIC_UNI_FW_MIN_SIZE          0xc8000
 268 #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0
 269 #define QLCNIC_UNI_DIR_SECT_BOOTLD      0x6
 270 #define QLCNIC_UNI_DIR_SECT_FW          0x7
 271
 272 /*Offsets */
 273 #define QLCNIC_UNI_CHIP_REV_OFF         10
 274 #define QLCNIC_UNI_FLAGS_OFF            11
 275 #define QLCNIC_UNI_BIOS_VERSION_OFF     12
 276 #define QLCNIC_UNI_BOOTLD_IDX_OFF       27
 277 #define QLCNIC_UNI_FIRMWARE_IDX_OFF     29
 278
 279 struct uni_table_desc{
 280         u32     findex;
 281         u32     num_entries;
 282         u32     entry_size;
 283         u32     reserved[5];
 284 };
 285
 286 struct uni_data_desc{
 287         u32     findex;
 288         u32     size;
 289         u32     reserved[5];
 290 };
 291
 292 /* Flash Defines and Structures */
 293 #define QLCNIC_FLT_LOCATION     0x3F1000
 294 #define QLCNIC_FW_IMAGE_REGION  0x74
 295 #define QLCNIC_BOOTLD_REGION    0X72
 296 struct qlcnic_flt_header {
 297         u16 version;
 298         u16 len;
 299         u16 checksum;
 300         u16 reserved;
 301 };
 302
 303 struct qlcnic_flt_entry {
 304         u8 region;
 305         u8 reserved0;
 306         u8 attrib;
 307         u8 reserved1;
 308         u32 size;
 309         u32 start_addr;
 310         u32 end_addr;
 311 };
 312
 313 /* Magic number to let user know flash is programmed */
 314 #define QLCNIC_BDINFO_MAGIC 0x12345678
 315
 316 #define QLCNIC_BRDTYPE_P3P_REF_QG       0x0021
 317 #define QLCNIC_BRDTYPE_P3P_HMEZ         0x0022
 318 #define QLCNIC_BRDTYPE_P3P_10G_CX4_LP   0x0023
 319 #define QLCNIC_BRDTYPE_P3P_4_GB         0x0024
 320 #define QLCNIC_BRDTYPE_P3P_IMEZ         0x0025
 321 #define QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS 0x0026
 322 #define QLCNIC_BRDTYPE_P3P_10000_BASE_T 0x0027
 323 #define QLCNIC_BRDTYPE_P3P_XG_LOM       0x0028
 324 #define QLCNIC_BRDTYPE_P3P_4_GB_MM      0x0029
 325 #define QLCNIC_BRDTYPE_P3P_10G_SFP_CT   0x002a
 326 #define QLCNIC_BRDTYPE_P3P_10G_SFP_QT   0x002b
 327 #define QLCNIC_BRDTYPE_P3P_10G_CX4      0x0031
 328 #define QLCNIC_BRDTYPE_P3P_10G_XFP      0x0032
 329 #define QLCNIC_BRDTYPE_P3P_10G_TP       0x0080
 330
 331 #define QLCNIC_MSIX_TABLE_OFFSET        0x44
 332
 333 /* Flash memory map */
 334 #define QLCNIC_BRDCFG_START     0x4000          /* board config */
 335 #define QLCNIC_BOOTLD_START     0x10000         /* bootld */
 336 #define QLCNIC_IMAGE_START      0x43000         /* compressed image */
 337 #define QLCNIC_USER_START       0x3E8000        /* Firmare info */
 338
 339 #define QLCNIC_FW_VERSION_OFFSET        (QLCNIC_USER_START+0x408)
 340 #define QLCNIC_FW_SIZE_OFFSET           (QLCNIC_USER_START+0x40c)
 341 #define QLCNIC_FW_SERIAL_NUM_OFFSET     (QLCNIC_USER_START+0x81c)
 342 #define QLCNIC_BIOS_VERSION_OFFSET      (QLCNIC_USER_START+0x83c)
 343
 344 #define QLCNIC_BRDTYPE_OFFSET           (QLCNIC_BRDCFG_START+0x8)
 345 #define QLCNIC_FW_MAGIC_OFFSET          (QLCNIC_BRDCFG_START+0x128)
 346
 347 #define QLCNIC_FW_MIN_SIZE              (0x3fffff)
 348 #define QLCNIC_UNIFIED_ROMIMAGE         0
 349 #define QLCNIC_FLASH_ROMIMAGE           1
 350 #define QLCNIC_UNKNOWN_ROMIMAGE         0xff
 351
 352 #define QLCNIC_UNIFIED_ROMIMAGE_NAME    "phanfw.bin"
 353 #define QLCNIC_FLASH_ROMIMAGE_NAME      "flash"
 354
 355 extern char qlcnic_driver_name[];
 356
 357 /* Number of status descriptors to handle per interrupt */
 358 #define MAX_STATUS_HANDLE       (64)
 359
 360 /*
 361  * qlcnic_skb_frag{} is to contain mapping info for each SG list. This
 362  * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}.
 363  */
 364 struct qlcnic_skb_frag {
 365         u64 dma;
 366         u64 length;
 367 };
 368
 369 /*    Following defines are for the state of the buffers    */
 370 #define QLCNIC_BUFFER_FREE      0
 371 #define QLCNIC_BUFFER_BUSY      1
 372
 373 /*
 374  * There will be one qlcnic_buffer per skb packet.    These will be
 375  * used to save the dma info for pci_unmap_page()
 376  */
 377 struct qlcnic_cmd_buffer {
 378         struct sk_buff *skb;
 379         struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1];
 380         u32 frag_count;
 381 };
 382
 383 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
 384 struct qlcnic_rx_buffer {
 385         u16 ref_handle;
 386         struct sk_buff *skb;
 387         struct list_head list;
 388         u64 dma;
 389 };
 390
 391 /* Board types */
 392 #define QLCNIC_GBE      0x01
 393 #define QLCNIC_XGBE     0x02
 394
 395 /*
 396  * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
 397  * adjusted based on configured MTU.
 398  */
 399 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_TIME_US 3
 400 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_PACKETS 256
 401
 402 #define QLCNIC_INTR_DEFAULT                     0x04
 403 #define QLCNIC_CONFIG_INTR_COALESCE             3
 404
 405 struct qlcnic_nic_intr_coalesce {
 406         u8      type;
 407         u8      sts_ring_mask;
 408         u16     rx_packets;
 409         u16     rx_time_us;
 410         u16     flag;
 411         u32     timer_out;
 412 };
 413
 414 struct qlcnic_dump_template_hdr {
 415         __le32  type;
 416         __le32  offset;
 417         __le32  size;
 418         __le32  cap_mask;
 419         __le32  num_entries;
 420         __le32  version;
 421         __le32  timestamp;
 422         __le32  checksum;
 423         __le32  drv_cap_mask;
 424         __le32  sys_info[3];
 425         __le32  saved_state[16];
 426         __le32  cap_sizes[8];
 427         __le32  rsvd[0];
 428 };
 429
 430 struct qlcnic_fw_dump {
 431         u8      clr;    /* flag to indicate if dump is cleared */
 432         u8      enable; /* enable/disable dump */
 433         u32     size;   /* total size of the dump */
 434         void    *data;  /* dump data area */
 435         struct  qlcnic_dump_template_hdr *tmpl_hdr;
 436 };
 437
 438 /*
 439  * One hardware_context{} per adapter
 440  * contains interrupt info as well shared hardware info.
 441  */
 442 struct qlcnic_hardware_context {
 443         void __iomem *pci_base0;
 444         void __iomem *ocm_win_crb;
 445
 446         unsigned long pci_len0;
 447
 448         rwlock_t crb_lock;
 449         struct mutex mem_lock;
 450
 451         u8 revision_id;
 452         u8 pci_func;
 453         u8 linkup;
 454         u8 loopback_state;
 455         u16 port_type;
 456         u16 board_type;
 457
 458         struct qlcnic_nic_intr_coalesce coal;
 459         struct qlcnic_fw_dump fw_dump;
 460 };
 461
 462 struct qlcnic_adapter_stats {
 463         u64  xmitcalled;
 464         u64  xmitfinished;
 465         u64  rxdropped;
 466         u64  txdropped;
 467         u64  csummed;
 468         u64  rx_pkts;
 469         u64  lro_pkts;
 470         u64  rxbytes;
 471         u64  txbytes;
 472         u64  lrobytes;
 473         u64  lso_frames;
 474         u64  xmit_on;
 475         u64  xmit_off;
 476         u64  skb_alloc_failure;
 477         u64  null_rxbuf;
 478         u64  rx_dma_map_error;
 479         u64  tx_dma_map_error;
 480 };
 481
 482 /*
 483  * Rcv Descriptor Context. One such per Rcv Descriptor. There may
 484  * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
 485  */
 486 struct qlcnic_host_rds_ring {
 487         void __iomem *crb_rcv_producer;
 488         struct rcv_desc *desc_head;
 489         struct qlcnic_rx_buffer *rx_buf_arr;
 490         u32 num_desc;
 491         u32 producer;
 492         u32 dma_size;
 493         u32 skb_size;
 494         u32 flags;
 495         struct list_head free_list;
 496         spinlock_t lock;
 497         dma_addr_t phys_addr;
 498 } ____cacheline_internodealigned_in_smp;
 499
 500 struct qlcnic_host_sds_ring {
 501         u32 consumer;
 502         u32 num_desc;
 503         void __iomem *crb_sts_consumer;
 504
 505         struct status_desc *desc_head;
 506         struct qlcnic_adapter *adapter;
 507         struct napi_struct napi;
 508         struct list_head free_list[NUM_RCV_DESC_RINGS];
 509
 510         void __iomem *crb_intr_mask;
 511         int irq;
 512
 513         dma_addr_t phys_addr;
 514         char name[IFNAMSIZ+4];
 515 } ____cacheline_internodealigned_in_smp;
 516
 517 struct qlcnic_host_tx_ring {
 518         u32 producer;
 519         u32 sw_consumer;
 520         u32 num_desc;
 521         void __iomem *crb_cmd_producer;
 522         struct cmd_desc_type0 *desc_head;
 523         struct qlcnic_cmd_buffer *cmd_buf_arr;
 524         __le32 *hw_consumer;
 525
 526         dma_addr_t phys_addr;
 527         dma_addr_t hw_cons_phys_addr;
 528         struct netdev_queue *txq;
 529 } ____cacheline_internodealigned_in_smp;
 530
 531 /*
 532  * Receive context. There is one such structure per instance of the
 533  * receive processing. Any state information that is relevant to
 534  * the receive, and is must be in this structure. The global data may be
 535  * present elsewhere.
 536  */
 537 struct qlcnic_recv_context {
 538         struct qlcnic_host_rds_ring *rds_rings;
 539         struct qlcnic_host_sds_ring *sds_rings;
 540         u32 state;
 541         u16 context_id;
 542         u16 virt_port;
 543
 544 };
 545
 546 /* HW context creation */
 547
 548 #define QLCNIC_OS_CRB_RETRY_COUNT       4000
 549 #define QLCNIC_CDRP_SIGNATURE_MAKE(pcifn, version) \
 550         (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
 551
 552 #define QLCNIC_CDRP_CMD_BIT             0x80000000
 553
 554 /*
 555  * All responses must have the QLCNIC_CDRP_CMD_BIT cleared
 556  * in the crb QLCNIC_CDRP_CRB_OFFSET.
 557  */
 558 #define QLCNIC_CDRP_FORM_RSP(rsp)       (rsp)
 559 #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0)
 560
 561 #define QLCNIC_CDRP_RSP_OK              0x00000001
 562 #define QLCNIC_CDRP_RSP_FAIL            0x00000002
 563 #define QLCNIC_CDRP_RSP_TIMEOUT         0x00000003
 564
 565 /*
 566  * All commands must have the QLCNIC_CDRP_CMD_BIT set in
 567  * the crb QLCNIC_CDRP_CRB_OFFSET.
 568  */
 569 #define QLCNIC_CDRP_FORM_CMD(cmd)       (QLCNIC_CDRP_CMD_BIT | (cmd))
 570 #define QLCNIC_CDRP_IS_CMD(cmd) (((cmd) & QLCNIC_CDRP_CMD_BIT) != 0)
 571
 572 #define QLCNIC_CDRP_CMD_SUBMIT_CAPABILITIES     0x00000001
 573 #define QLCNIC_CDRP_CMD_READ_MAX_RDS_PER_CTX    0x00000002
 574 #define QLCNIC_CDRP_CMD_READ_MAX_SDS_PER_CTX    0x00000003
 575 #define QLCNIC_CDRP_CMD_READ_MAX_RULES_PER_CTX  0x00000004
 576 #define QLCNIC_CDRP_CMD_READ_MAX_RX_CTX         0x00000005
 577 #define QLCNIC_CDRP_CMD_READ_MAX_TX_CTX         0x00000006
 578 #define QLCNIC_CDRP_CMD_CREATE_RX_CTX           0x00000007
 579 #define QLCNIC_CDRP_CMD_DESTROY_RX_CTX          0x00000008
 580 #define QLCNIC_CDRP_CMD_CREATE_TX_CTX           0x00000009
 581 #define QLCNIC_CDRP_CMD_DESTROY_TX_CTX          0x0000000a
 582 #define QLCNIC_CDRP_CMD_SET_MTU                 0x00000012
 583 #define QLCNIC_CDRP_CMD_READ_PHY                0x00000013
 584 #define QLCNIC_CDRP_CMD_WRITE_PHY               0x00000014
 585 #define QLCNIC_CDRP_CMD_READ_HW_REG             0x00000015
 586 #define QLCNIC_CDRP_CMD_GET_FLOW_CTL            0x00000016
 587 #define QLCNIC_CDRP_CMD_SET_FLOW_CTL            0x00000017
 588 #define QLCNIC_CDRP_CMD_READ_MAX_MTU            0x00000018
 589 #define QLCNIC_CDRP_CMD_READ_MAX_LRO            0x00000019
 590 #define QLCNIC_CDRP_CMD_MAC_ADDRESS             0x0000001f
 591
 592 #define QLCNIC_CDRP_CMD_GET_PCI_INFO            0x00000020
 593 #define QLCNIC_CDRP_CMD_GET_NIC_INFO            0x00000021
 594 #define QLCNIC_CDRP_CMD_SET_NIC_INFO            0x00000022
 595 #define QLCNIC_CDRP_CMD_GET_ESWITCH_CAPABILITY  0x00000024
 596 #define QLCNIC_CDRP_CMD_TOGGLE_ESWITCH          0x00000025
 597 #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATUS      0x00000026
 598 #define QLCNIC_CDRP_CMD_SET_PORTMIRRORING       0x00000027
 599 #define QLCNIC_CDRP_CMD_CONFIGURE_ESWITCH       0x00000028
 600 #define QLCNIC_CDRP_CMD_GET_ESWITCH_PORT_CONFIG 0x00000029
 601 #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATS       0x0000002a
 602 #define QLCNIC_CDRP_CMD_CONFIG_PORT             0x0000002E
 603 #define QLCNIC_CDRP_CMD_TEMP_SIZE               0x0000002f
 604 #define QLCNIC_CDRP_CMD_GET_TEMP_HDR            0x00000030
 605
 606 #define QLCNIC_RCODE_SUCCESS            0
 607 #define QLCNIC_RCODE_NOT_SUPPORTED      9
 608 #define QLCNIC_RCODE_TIMEOUT            17
 609 #define QLCNIC_DESTROY_CTX_RESET        0
 610
 611 /*
 612  * Capabilities Announced
 613  */
 614 #define QLCNIC_CAP0_LEGACY_CONTEXT      (1)
 615 #define QLCNIC_CAP0_LEGACY_MN           (1 << 2)
 616 #define QLCNIC_CAP0_LSO                 (1 << 6)
 617 #define QLCNIC_CAP0_JUMBO_CONTIGUOUS    (1 << 7)
 618 #define QLCNIC_CAP0_LRO_CONTIGUOUS      (1 << 8)
 619 #define QLCNIC_CAP0_VALIDOFF            (1 << 11)
 620
 621 /*
 622  * Context state
 623  */
 624 #define QLCNIC_HOST_CTX_STATE_FREED     0
 625 #define QLCNIC_HOST_CTX_STATE_ACTIVE    2
 626
 627 /*
 628  * Rx context
 629  */
 630
 631 struct qlcnic_hostrq_sds_ring {
 632         __le64 host_phys_addr;  /* Ring base addr */
 633         __le32 ring_size;               /* Ring entries */
 634         __le16 msi_index;
 635         __le16 rsvd;            /* Padding */
 636 } __packed;
 637
 638 struct qlcnic_hostrq_rds_ring {
 639         __le64 host_phys_addr;  /* Ring base addr */
 640         __le64 buff_size;               /* Packet buffer size */
 641         __le32 ring_size;               /* Ring entries */
 642         __le32 ring_kind;               /* Class of ring */
 643 } __packed;
 644
 645 struct qlcnic_hostrq_rx_ctx {
 646         __le64 host_rsp_dma_addr;       /* Response dma'd here */
 647         __le32 capabilities[4]; /* Flag bit vector */
 648         __le32 host_int_crb_mode;       /* Interrupt crb usage */
 649         __le32 host_rds_crb_mode;       /* RDS crb usage */
 650         /* These ring offsets are relative to data[0] below */
 651         __le32 rds_ring_offset; /* Offset to RDS config */
 652         __le32 sds_ring_offset; /* Offset to SDS config */
 653         __le16 num_rds_rings;   /* Count of RDS rings */
 654         __le16 num_sds_rings;   /* Count of SDS rings */
 655         __le16 valid_field_offset;
 656         u8  txrx_sds_binding;
 657         u8  msix_handler;
 658         u8  reserved[128];      /* reserve space for future expansion*/
 659         /* MUST BE 64-bit aligned.
 660            The following is packed:
 661            - N hostrq_rds_rings
 662            - N hostrq_sds_rings */
 663         char data[0];
 664 } __packed;
 665
 666 struct qlcnic_cardrsp_rds_ring{
 667         __le32 host_producer_crb;       /* Crb to use */
 668         __le32 rsvd1;           /* Padding */
 669 } __packed;
 670
 671 struct qlcnic_cardrsp_sds_ring {
 672         __le32 host_consumer_crb;       /* Crb to use */
 673         __le32 interrupt_crb;   /* Crb to use */
 674 } __packed;
 675
 676 struct qlcnic_cardrsp_rx_ctx {
 677         /* These ring offsets are relative to data[0] below */
 678         __le32 rds_ring_offset; /* Offset to RDS config */
 679         __le32 sds_ring_offset; /* Offset to SDS config */
 680         __le32 host_ctx_state;  /* Starting State */
 681         __le32 num_fn_per_port; /* How many PCI fn share the port */
 682         __le16 num_rds_rings;   /* Count of RDS rings */
 683         __le16 num_sds_rings;   /* Count of SDS rings */
 684         __le16 context_id;              /* Handle for context */
 685         u8  phys_port;          /* Physical id of port */
 686         u8  virt_port;          /* Virtual/Logical id of port */
 687         u8  reserved[128];      /* save space for future expansion */
 688         /*  MUST BE 64-bit aligned.
 689            The following is packed:
 690            - N cardrsp_rds_rings
 691            - N cardrs_sds_rings */
 692         char data[0];
 693 } __packed;
 694
 695 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings)       \
 696         (sizeof(HOSTRQ_RX) +                                    \
 697         (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) +           \
 698         (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring)))
 699
 700 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings)     \
 701         (sizeof(CARDRSP_RX) +                                   \
 702         (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) +          \
 703         (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring)))
 704
 705 /*
 706  * Tx context
 707  */
 708
 709 struct qlcnic_hostrq_cds_ring {
 710         __le64 host_phys_addr;  /* Ring base addr */
 711         __le32 ring_size;               /* Ring entries */
 712         __le32 rsvd;            /* Padding */
 713 } __packed;
 714
 715 struct qlcnic_hostrq_tx_ctx {
 716         __le64 host_rsp_dma_addr;       /* Response dma'd here */
 717         __le64 cmd_cons_dma_addr;       /*  */
 718         __le64 dummy_dma_addr;  /*  */
 719         __le32 capabilities[4]; /* Flag bit vector */
 720         __le32 host_int_crb_mode;       /* Interrupt crb usage */
 721         __le32 rsvd1;           /* Padding */
 722         __le16 rsvd2;           /* Padding */
 723         __le16 interrupt_ctl;
 724         __le16 msi_index;
 725         __le16 rsvd3;           /* Padding */
 726         struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */
 727         u8  reserved[128];      /* future expansion */
 728 } __packed;
 729
 730 struct qlcnic_cardrsp_cds_ring {
 731         __le32 host_producer_crb;       /* Crb to use */
 732         __le32 interrupt_crb;   /* Crb to use */
 733 } __packed;
 734
 735 struct qlcnic_cardrsp_tx_ctx {
 736         __le32 host_ctx_state;  /* Starting state */
 737         __le16 context_id;              /* Handle for context */
 738         u8  phys_port;          /* Physical id of port */
 739         u8  virt_port;          /* Virtual/Logical id of port */
 740         struct qlcnic_cardrsp_cds_ring cds_ring;        /* Card cds settings */
 741         u8  reserved[128];      /* future expansion */
 742 } __packed;
 743
 744 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX)     (sizeof(HOSTRQ_TX))
 745 #define SIZEOF_CARDRSP_TX(CARDRSP_TX)   (sizeof(CARDRSP_TX))
 746
 747 /* CRB */
 748
 749 #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0
 750 #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1
 751 #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2
 752 #define QLCNIC_HOST_RDS_CRB_MODE_MAX    3
 753
 754 #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0
 755 #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1
 756 #define QLCNIC_HOST_INT_CRB_MODE_NORX   2
 757 #define QLCNIC_HOST_INT_CRB_MODE_NOTX   3
 758 #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4
 759
 760
 761 /* MAC */
 762
 763 #define MC_COUNT_P3P    38
 764
 765 #define QLCNIC_MAC_NOOP 0
 766 #define QLCNIC_MAC_ADD  1
 767 #define QLCNIC_MAC_DEL  2
 768 #define QLCNIC_MAC_VLAN_ADD     3
 769 #define QLCNIC_MAC_VLAN_DEL     4
 770
 771 struct qlcnic_mac_list_s {
 772         struct list_head list;
 773         uint8_t mac_addr[ETH_ALEN+2];
 774 };
 775
 776 #define QLCNIC_HOST_REQUEST     0x13
 777 #define QLCNIC_REQUEST          0x14
 778
 779 #define QLCNIC_MAC_EVENT        0x1
 780
 781 #define QLCNIC_IP_UP            2
 782 #define QLCNIC_IP_DOWN          3
 783
 784 #define QLCNIC_ILB_MODE         0x1
 785 #define QLCNIC_ELB_MODE         0x2
 786
 787 #define QLCNIC_LINKEVENT        0x1
 788 #define QLCNIC_LB_RESPONSE      0x2
 789 #define QLCNIC_IS_LB_CONFIGURED(VAL)    \
 790                 (VAL == (QLCNIC_LINKEVENT | QLCNIC_LB_RESPONSE))
 791
 792 /*
 793  * Driver --> Firmware
 794  */
 795 #define QLCNIC_H2C_OPCODE_CONFIG_RSS                    0x1
 796 #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE          0x3
 797 #define QLCNIC_H2C_OPCODE_CONFIG_LED                    0x4
 798 #define QLCNIC_H2C_OPCODE_LRO_REQUEST                   0x7
 799 #define QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE          0xc
 800 #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR         0x12
 801
 802 #define QLCNIC_H2C_OPCODE_GET_LINKEVENT         0x15
 803 #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING               0x17
 804 #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO         0x18
 805 #define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK               0x13
 806
 807 /*
 808  * Firmware --> Driver
 809  */
 810
 811 #define QLCNIC_C2H_OPCODE_CONFIG_LOOPBACK               0x8f
 812 #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE        141
 813
 814 #define VPORT_MISS_MODE_DROP            0 /* drop all unmatched */
 815 #define VPORT_MISS_MODE_ACCEPT_ALL      1 /* accept all packets */
 816 #define VPORT_MISS_MODE_ACCEPT_MULTI    2 /* accept unmatched multicast */
 817
 818 #define QLCNIC_LRO_REQUEST_CLEANUP      4
 819
 820 /* Capabilites received */
 821 #define QLCNIC_FW_CAPABILITY_TSO                BIT_1
 822 #define QLCNIC_FW_CAPABILITY_BDG                BIT_8
 823 #define QLCNIC_FW_CAPABILITY_FVLANTX            BIT_9
 824 #define QLCNIC_FW_CAPABILITY_HW_LRO             BIT_10
 825
 826 /* module types */
 827 #define LINKEVENT_MODULE_NOT_PRESENT                    1
 828 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN                2
 829 #define LINKEVENT_MODULE_OPTICAL_SRLR                   3
 830 #define LINKEVENT_MODULE_OPTICAL_LRM                    4
 831 #define LINKEVENT_MODULE_OPTICAL_SFP_1G                 5
 832 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE       6
 833 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN    7
 834 #define LINKEVENT_MODULE_TWINAX                         8
 835
 836 #define LINKSPEED_10GBPS        10000
 837 #define LINKSPEED_1GBPS         1000
 838 #define LINKSPEED_100MBPS       100
 839 #define LINKSPEED_10MBPS        10
 840
 841 #define LINKSPEED_ENCODED_10MBPS        0
 842 #define LINKSPEED_ENCODED_100MBPS       1
 843 #define LINKSPEED_ENCODED_1GBPS         2
 844
 845 #define LINKEVENT_AUTONEG_DISABLED      0
 846 #define LINKEVENT_AUTONEG_ENABLED       1
 847
 848 #define LINKEVENT_HALF_DUPLEX           0
 849 #define LINKEVENT_FULL_DUPLEX           1
 850
 851 #define LINKEVENT_LINKSPEED_MBPS        0
 852 #define LINKEVENT_LINKSPEED_ENCODED     1
 853
 854 /* firmware response header:
 855  *      63:58 - message type
 856  *      57:56 - owner
 857  *      55:53 - desc count
 858  *      52:48 - reserved
 859  *      47:40 - completion id
 860  *      39:32 - opcode
 861  *      31:16 - error code
 862  *      15:00 - reserved
 863  */
 864 #define qlcnic_get_nic_msg_opcode(msg_hdr)      \
 865         ((msg_hdr >> 32) & 0xFF)
 866
 867 struct qlcnic_fw_msg {
 868         union {
 869                 struct {
 870                         u64 hdr;
 871                         u64 body[7];
 872                 };
 873                 u64 words[8];
 874         };
 875 };
 876
 877 struct qlcnic_nic_req {
 878         __le64 qhdr;
 879         __le64 req_hdr;
 880         __le64 words[6];
 881 } __packed;
 882
 883 struct qlcnic_mac_req {
 884         u8 op;
 885         u8 tag;
 886         u8 mac_addr[6];
 887 };
 888
 889 struct qlcnic_vlan_req {
 890         __le16 vlan_id;
 891         __le16 rsvd[3];
 892 } __packed;
 893
 894 struct qlcnic_ipaddr {
 895         __be32 ipv4;
 896         __be32 ipv6[4];
 897 };
 898
 899 #define QLCNIC_MSI_ENABLED              0x02
 900 #define QLCNIC_MSIX_ENABLED             0x04
 901 #define QLCNIC_LRO_ENABLED              0x08
 902 #define QLCNIC_LRO_DISABLED             0x00
 903 #define QLCNIC_BRIDGE_ENABLED           0X10
 904 #define QLCNIC_DIAG_ENABLED             0x20
 905 #define QLCNIC_ESWITCH_ENABLED          0x40
 906 #define QLCNIC_ADAPTER_INITIALIZED      0x80
 907 #define QLCNIC_TAGGING_ENABLED          0x100
 908 #define QLCNIC_MACSPOOF                 0x200
 909 #define QLCNIC_MAC_OVERRIDE_DISABLED    0x400
 910 #define QLCNIC_PROMISC_DISABLED         0x800
 911 #define QLCNIC_NEED_FLR                 0x1000
 912 #define QLCNIC_FW_RESET_OWNER           0x2000
 913 #define QLCNIC_IS_MSI_FAMILY(adapter) \
 914         ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED))
 915
 916 #define QLCNIC_DEF_NUM_STS_DESC_RINGS   4
 917 #define QLCNIC_MSIX_TBL_SPACE           8192
 918 #define QLCNIC_PCI_REG_MSIX_TBL         0x44
 919 #define QLCNIC_MSIX_TBL_PGSIZE          4096
 920
 921 #define QLCNIC_NETDEV_WEIGHT    128
 922 #define QLCNIC_ADAPTER_UP_MAGIC 777
 923
 924 #define __QLCNIC_FW_ATTACHED            0
 925 #define __QLCNIC_DEV_UP                 1
 926 #define __QLCNIC_RESETTING              2
 927 #define __QLCNIC_START_FW               4
 928 #define __QLCNIC_AER                    5
 929 #define __QLCNIC_DIAG_RES_ALLOC         6
 930
 931 #define QLCNIC_INTERRUPT_TEST           1
 932 #define QLCNIC_LOOPBACK_TEST            2
 933 #define QLCNIC_LED_TEST         3
 934
 935 #define QLCNIC_FILTER_AGE       80
 936 #define QLCNIC_READD_AGE        20
 937 #define QLCNIC_LB_MAX_FILTERS   64
 938
 939 struct qlcnic_filter {
 940         struct hlist_node fnode;
 941         u8 faddr[ETH_ALEN];
 942         __le16 vlan_id;
 943         unsigned long ftime;
 944 };
 945
 946 struct qlcnic_filter_hash {
 947         struct hlist_head *fhead;
 948         u8 fnum;
 949         u8 fmax;
 950 };
 951
 952 struct qlcnic_adapter {
 953         struct qlcnic_hardware_context *ahw;
 954         struct qlcnic_recv_context *recv_ctx;
 955         struct qlcnic_host_tx_ring *tx_ring;
 956         struct net_device *netdev;
 957         struct pci_dev *pdev;
 958
 959         unsigned long state;
 960         u32 flags;
 961
 962         u16 num_txd;
 963         u16 num_rxd;
 964         u16 num_jumbo_rxd;
 965         u16 max_rxd;
 966         u16 max_jumbo_rxd;
 967
 968         u8 max_rds_rings;
 969         u8 max_sds_rings;
 970         u8 msix_supported;
 971         u8 portnum;
 972         u8 physical_port;
 973         u8 reset_context;
 974
 975         u8 mc_enabled;
 976         u8 max_mc_count;
 977         u8 fw_wait_cnt;
 978         u8 fw_fail_cnt;
 979         u8 tx_timeo_cnt;
 980         u8 need_fw_reset;
 981
 982         u8 has_link_events;
 983         u8 fw_type;
 984         u16 tx_context_id;
 985         u16 is_up;
 986
 987         u16 link_speed;
 988         u16 link_duplex;
 989         u16 link_autoneg;
 990         u16 module_type;
 991
 992         u16 op_mode;
 993         u16 switch_mode;
 994         u16 max_tx_ques;
 995         u16 max_rx_ques;
 996         u16 max_mtu;
 997         u16 pvid;
 998
 999         u32 fw_hal_version;
1000         u32 capabilities;
1001         u32 irq;
1002         u32 temp;
1003
1004         u32 int_vec_bit;
1005         u32 heartbeat;
1006
1007         u8 max_mac_filters;
1008         u8 dev_state;
1009         u8 diag_test;
1010         u8 diag_cnt;
1011         u8 reset_ack_timeo;
1012         u8 dev_init_timeo;
1013         u16 msg_enable;
1014
1015         u8 mac_addr[ETH_ALEN];
1016
1017         u64 dev_rst_time;
1018         unsigned long vlans[BITS_TO_LONGS(VLAN_N_VID)];
1019
1020         struct qlcnic_npar_info *npars;
1021         struct qlcnic_eswitch *eswitch;
1022         struct qlcnic_nic_template *nic_ops;
1023
1024         struct qlcnic_adapter_stats stats;
1025         struct list_head mac_list;
1026
1027         void __iomem    *tgt_mask_reg;
1028         void __iomem    *tgt_status_reg;
1029         void __iomem    *crb_int_state_reg;
1030         void __iomem    *isr_int_vec;
1031
1032         struct msix_entry *msix_entries;
1033
1034         struct delayed_work fw_work;
1035
1036
1037         struct qlcnic_filter_hash fhash;
1038
1039         spinlock_t tx_clean_lock;
1040         spinlock_t mac_learn_lock;
1041         __le32 file_prd_off;    /*File fw product offset*/
1042         u32 fw_version;
1043         const struct firmware *fw;
1044 };
1045
1046 struct qlcnic_info {
1047         __le16  pci_func;
1048         __le16  op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */
1049         __le16  phys_port;
1050         __le16  switch_mode; /* 0 = disabled, 1 = int, 2 = ext */
1051
1052         __le32  capabilities;
1053         u8      max_mac_filters;
1054         u8      reserved1;
1055         __le16  max_mtu;
1056
1057         __le16  max_tx_ques;
1058         __le16  max_rx_ques;
1059         __le16  min_tx_bw;
1060         __le16  max_tx_bw;
1061         u8      reserved2[104];
1062 } __packed;
1063
1064 struct qlcnic_pci_info {
1065         __le16  id; /* pci function id */
1066         __le16  active; /* 1 = Enabled */
1067         __le16  type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */
1068         __le16  default_port; /* default port number */
1069
1070         __le16  tx_min_bw; /* Multiple of 100mbpc */
1071         __le16  tx_max_bw;
1072         __le16  reserved1[2];
1073
1074         u8      mac[ETH_ALEN];
1075         u8      reserved2[106];
1076 } __packed;
1077
1078 struct qlcnic_npar_info {
1079         u16     pvid;
1080         u16     min_bw;
1081         u16     max_bw;
1082         u8      phy_port;
1083         u8      type;
1084         u8      active;
1085         u8      enable_pm;
1086         u8      dest_npar;
1087         u8      discard_tagged;
1088         u8      mac_override;
1089         u8      mac_anti_spoof;
1090         u8      promisc_mode;
1091         u8      offload_flags;
1092 };
1093
1094 struct qlcnic_eswitch {
1095         u8      port;
1096         u8      active_vports;
1097         u8      active_vlans;
1098         u8      active_ucast_filters;
1099         u8      max_ucast_filters;
1100         u8      max_active_vlans;
1101
1102         u32     flags;
1103 #define QLCNIC_SWITCH_ENABLE            BIT_1
1104 #define QLCNIC_SWITCH_VLAN_FILTERING    BIT_2
1105 #define QLCNIC_SWITCH_PROMISC_MODE      BIT_3
1106 #define QLCNIC_SWITCH_PORT_MIRRORING    BIT_4
1107 };
1108
1109
1110 /* Return codes for Error handling */
1111 #define QL_STATUS_INVALID_PARAM -1
1112
1113 #define MAX_BW                  100     /* % of link speed */
1114 #define MAX_VLAN_ID             4095
1115 #define MIN_VLAN_ID             2
1116 #define DEFAULT_MAC_LEARN       1
1117
1118 #define IS_VALID_VLAN(vlan)     (vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID)
1119 #define IS_VALID_BW(bw)         (bw <= MAX_BW)
1120
1121 struct qlcnic_pci_func_cfg {
1122         u16     func_type;
1123         u16     min_bw;
1124         u16     max_bw;
1125         u16     port_num;
1126         u8      pci_func;
1127         u8      func_state;
1128         u8      def_mac_addr[6];
1129 };
1130
1131 struct qlcnic_npar_func_cfg {
1132         u32     fw_capab;
1133         u16     port_num;
1134         u16     min_bw;
1135         u16     max_bw;
1136         u16     max_tx_queues;
1137         u16     max_rx_queues;
1138         u8      pci_func;
1139         u8      op_mode;
1140 };
1141
1142 struct qlcnic_pm_func_cfg {
1143         u8      pci_func;
1144         u8      action;
1145         u8      dest_npar;
1146         u8      reserved[5];
1147 };
1148
1149 struct qlcnic_esw_func_cfg {
1150         u16     vlan_id;
1151         u8      op_mode;
1152         u8      op_type;
1153         u8      pci_func;
1154         u8      host_vlan_tag;
1155         u8      promisc_mode;
1156         u8      discard_tagged;
1157         u8      mac_override;
1158         u8      mac_anti_spoof;
1159         u8      offload_flags;
1160         u8      reserved[5];
1161 };
1162
1163 #define QLCNIC_STATS_VERSION            1
1164 #define QLCNIC_STATS_PORT               1
1165 #define QLCNIC_STATS_ESWITCH            2
1166 #define QLCNIC_QUERY_RX_COUNTER         0
1167 #define QLCNIC_QUERY_TX_COUNTER         1
1168 #define QLCNIC_ESW_STATS_NOT_AVAIL      0xffffffffffffffffULL
1169
1170 #define QLCNIC_ADD_ESW_STATS(VAL1, VAL2)\
1171 do {    \
1172         if (((VAL1) == QLCNIC_ESW_STATS_NOT_AVAIL) && \
1173             ((VAL2) != QLCNIC_ESW_STATS_NOT_AVAIL)) \
1174                 (VAL1) = (VAL2); \
1175         else if (((VAL1) != QLCNIC_ESW_STATS_NOT_AVAIL) && \
1176                  ((VAL2) != QLCNIC_ESW_STATS_NOT_AVAIL)) \
1177                         (VAL1) += (VAL2); \
1178 } while (0)
1179
1180 struct __qlcnic_esw_statistics {
1181         __le16 context_id;
1182         __le16 version;
1183         __le16 size;
1184         __le16 unused;
1185         __le64 unicast_frames;
1186         __le64 multicast_frames;
1187         __le64 broadcast_frames;
1188         __le64 dropped_frames;
1189         __le64 errors;
1190         __le64 local_frames;
1191         __le64 numbytes;
1192         __le64 rsvd[3];
1193 } __packed;
1194
1195 struct qlcnic_esw_statistics {
1196         struct __qlcnic_esw_statistics rx;
1197         struct __qlcnic_esw_statistics tx;
1198 };
1199
1200 struct qlcnic_common_entry_hdr {
1201         __le32  type;
1202         __le32  offset;
1203         __le32  cap_size;
1204         u8      mask;
1205         u8      rsvd[2];
1206         u8      flags;
1207 } __packed;
1208
1209 struct __crb {
1210         __le32  addr;
1211         u8      stride;
1212         u8      rsvd1[3];
1213         __le32  data_size;
1214         __le32  no_ops;
1215         __le32  rsvd2[4];
1216 } __packed;
1217
1218 struct __ctrl {
1219         __le32  addr;
1220         u8      stride;
1221         u8      index_a;
1222         __le16  timeout;
1223         __le32  data_size;
1224         __le32  no_ops;
1225         u8      opcode;
1226         u8      index_v;
1227         u8      shl_val;
1228         u8      shr_val;
1229         __le32  val1;
1230         __le32  val2;
1231         __le32  val3;
1232 } __packed;
1233
1234 struct __cache {
1235         __le32  addr;
1236         __le16  stride;
1237         __le16  init_tag_val;
1238         __le32  size;
1239         __le32  no_ops;
1240         __le32  ctrl_addr;
1241         __le32  ctrl_val;
1242         __le32  read_addr;
1243         u8      read_addr_stride;
1244         u8      read_addr_num;
1245         u8      rsvd1[2];
1246 } __packed;
1247
1248 struct __ocm {
1249         u8      rsvd[8];
1250         __le32  size;
1251         __le32  no_ops;
1252         u8      rsvd1[8];
1253         __le32  read_addr;
1254         __le32  read_addr_stride;
1255 } __packed;
1256
1257 struct __mem {
1258         u8      rsvd[24];
1259         __le32  addr;
1260         __le32  size;
1261 } __packed;
1262
1263 struct __mux {
1264         __le32  addr;
1265         u8      rsvd[4];
1266         __le32  size;
1267         __le32  no_ops;
1268         __le32  val;
1269         __le32  val_stride;
1270         __le32  read_addr;
1271         u8      rsvd2[4];
1272 } __packed;
1273
1274 struct __queue {
1275         __le32  sel_addr;
1276         __le16  stride;
1277         u8      rsvd[2];
1278         __le32  size;
1279         __le32  no_ops;
1280         u8      rsvd2[8];
1281         __le32  read_addr;
1282         u8      read_addr_stride;
1283         u8      read_addr_cnt;
1284         u8      rsvd3[2];
1285 } __packed;
1286
1287 struct qlcnic_dump_entry {
1288         struct qlcnic_common_entry_hdr hdr;
1289         union {
1290                 struct __crb    crb;
1291                 struct __cache  cache;
1292                 struct __ocm    ocm;
1293                 struct __mem    mem;
1294                 struct __mux    mux;
1295                 struct __queue  que;
1296                 struct __ctrl   ctrl;
1297         } region;
1298 } __packed;
1299
1300 enum op_codes {
1301         QLCNIC_DUMP_NOP         = 0,
1302         QLCNIC_DUMP_READ_CRB    = 1,
1303         QLCNIC_DUMP_READ_MUX    = 2,
1304         QLCNIC_DUMP_QUEUE       = 3,
1305         QLCNIC_DUMP_BRD_CONFIG  = 4,
1306         QLCNIC_DUMP_READ_OCM    = 6,
1307         QLCNIC_DUMP_PEG_REG     = 7,
1308         QLCNIC_DUMP_L1_DTAG     = 8,
1309         QLCNIC_DUMP_L1_ITAG     = 9,
1310         QLCNIC_DUMP_L1_DATA     = 11,
1311         QLCNIC_DUMP_L1_INST     = 12,
1312         QLCNIC_DUMP_L2_DTAG     = 21,
1313         QLCNIC_DUMP_L2_ITAG     = 22,
1314         QLCNIC_DUMP_L2_DATA     = 23,
1315         QLCNIC_DUMP_L2_INST     = 24,
1316         QLCNIC_DUMP_READ_ROM    = 71,
1317         QLCNIC_DUMP_READ_MEM    = 72,
1318         QLCNIC_DUMP_READ_CTRL   = 98,
1319         QLCNIC_DUMP_TLHDR       = 99,
1320         QLCNIC_DUMP_RDEND       = 255
1321 };
1322
1323 #define QLCNIC_DUMP_WCRB        BIT_0
1324 #define QLCNIC_DUMP_RWCRB       BIT_1
1325 #define QLCNIC_DUMP_ANDCRB      BIT_2
1326 #define QLCNIC_DUMP_ORCRB       BIT_3
1327 #define QLCNIC_DUMP_POLLCRB     BIT_4
1328 #define QLCNIC_DUMP_RD_SAVE     BIT_5
1329 #define QLCNIC_DUMP_WRT_SAVED   BIT_6
1330 #define QLCNIC_DUMP_MOD_SAVE_ST BIT_7
1331 #define QLCNIC_DUMP_SKIP        BIT_7
1332
1333 #define QLCNIC_DUMP_MASK_MIN            3
1334 #define QLCNIC_DUMP_MASK_DEF            0x7f
1335 #define QLCNIC_DUMP_MASK_MAX            0xff
1336 #define QLCNIC_FORCE_FW_DUMP_KEY        0xdeadfeed
1337 #define QLCNIC_ENABLE_FW_DUMP           0xaddfeed
1338 #define QLCNIC_DISABLE_FW_DUMP          0xbadfeed
1339
1340 struct qlcnic_dump_operations {
1341         enum op_codes opcode;
1342         u32 (*handler)(struct qlcnic_adapter *,
1343                         struct qlcnic_dump_entry *, u32 *);
1344 };
1345
1346 int qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter);
1347 int qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config);
1348
1349 u32 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off);
1350 int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *, ulong off, u32 data);
1351 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data);
1352 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data);
1353 void qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *, u64, u64 *);
1354 void qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *, u64, u64);
1355
1356 #define ADDR_IN_RANGE(addr, low, high)  \
1357         (((addr) < (high)) && ((addr) >= (low)))
1358
1359 #define QLCRD32(adapter, off) \
1360         (qlcnic_hw_read_wx_2M(adapter, off))
1361 #define QLCWR32(adapter, off, val) \
1362         (qlcnic_hw_write_wx_2M(adapter, off, val))
1363
1364 int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32);
1365 void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int);
1366
1367 #define qlcnic_rom_lock(a)      \
1368         qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID)
1369 #define qlcnic_rom_unlock(a)    \
1370         qlcnic_pcie_sem_unlock((a), 2)
1371 #define qlcnic_phy_lock(a)      \
1372         qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID)
1373 #define qlcnic_phy_unlock(a)    \
1374         qlcnic_pcie_sem_unlock((a), 3)
1375 #define qlcnic_api_lock(a)      \
1376         qlcnic_pcie_sem_lock((a), 5, 0)
1377 #define qlcnic_api_unlock(a)    \
1378         qlcnic_pcie_sem_unlock((a), 5)
1379 #define qlcnic_sw_lock(a)       \
1380         qlcnic_pcie_sem_lock((a), 6, 0)
1381 #define qlcnic_sw_unlock(a)     \
1382         qlcnic_pcie_sem_unlock((a), 6)
1383 #define crb_win_lock(a) \
1384         qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID)
1385 #define crb_win_unlock(a)       \
1386         qlcnic_pcie_sem_unlock((a), 7)
1387
1388 int qlcnic_get_board_info(struct qlcnic_adapter *adapter);
1389 int qlcnic_wol_supported(struct qlcnic_adapter *adapter);
1390 int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate);
1391 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter);
1392 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter);
1393 int qlcnic_dump_fw(struct qlcnic_adapter *);
1394
1395 /* Functions from qlcnic_init.c */
1396 int qlcnic_load_firmware(struct qlcnic_adapter *adapter);
1397 int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter);
1398 void qlcnic_request_firmware(struct qlcnic_adapter *adapter);
1399 void qlcnic_release_firmware(struct qlcnic_adapter *adapter);
1400 int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter);
1401 int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter);
1402 int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter);
1403
1404 int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, u32 addr, u32 *valp);
1405 int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
1406                                 u8 *bytes, size_t size);
1407 int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter);
1408 void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter);
1409
1410 void __iomem *qlcnic_get_ioaddr(struct qlcnic_adapter *, u32);
1411
1412 int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter);
1413 void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter);
1414
1415 int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter);
1416 void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter);
1417
1418 void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter);
1419 void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter);
1420 void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter);
1421
1422 int qlcnic_check_fw_status(struct qlcnic_adapter *adapter);
1423 void qlcnic_watchdog_task(struct work_struct *work);
1424 void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter,
1425                 struct qlcnic_host_rds_ring *rds_ring);
1426 int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max);
1427 void qlcnic_set_multi(struct net_device *netdev);
1428 void qlcnic_free_mac_list(struct qlcnic_adapter *adapter);
1429 int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32);
1430 int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter);
1431 int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable);
1432 int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip, int cmd);
1433 int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable);
1434 void qlcnic_advert_link_change(struct qlcnic_adapter *adapter, int linkup);
1435
1436 int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu);
1437 int qlcnic_change_mtu(struct net_device *netdev, int new_mtu);
1438 u32 qlcnic_fix_features(struct net_device *netdev, u32 features);
1439 int qlcnic_set_features(struct net_device *netdev, u32 features);
1440 int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable);
1441 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable);
1442 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter);
1443 void qlcnic_update_cmd_producer(struct qlcnic_adapter *adapter,
1444                 struct qlcnic_host_tx_ring *tx_ring);
1445 void qlcnic_fetch_mac(struct qlcnic_adapter *, u32, u32, u8, u8 *);
1446 void qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring);
1447 void qlcnic_clear_lb_mode(struct qlcnic_adapter *adapter);
1448 int qlcnic_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode);
1449
1450 /* Functions from qlcnic_ethtool.c */
1451 int qlcnic_check_loopback_buff(unsigned char *data, u8 mac[]);
1452
1453 /* Functions from qlcnic_main.c */
1454 int qlcnic_reset_context(struct qlcnic_adapter *);
1455 u32 qlcnic_issue_cmd(struct qlcnic_adapter *adapter,
1456         u32 pci_fn, u32 version, u32 arg1, u32 arg2, u32 arg3, u32 cmd);
1457 void qlcnic_diag_free_res(struct net_device *netdev, int max_sds_rings);
1458 int qlcnic_diag_alloc_res(struct net_device *netdev, int test);
1459 netdev_tx_t qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
1460 int qlcnic_validate_max_rss(struct net_device *netdev, u8 max_hw, u8 val);
1461 int qlcnic_set_max_rss(struct qlcnic_adapter *adapter, u8 data);
1462 void qlcnic_dev_request_reset(struct qlcnic_adapter *);
1463
1464 /* Management functions */
1465 int qlcnic_get_mac_address(struct qlcnic_adapter *, u8*);
1466 int qlcnic_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8);
1467 int qlcnic_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *);
1468 int qlcnic_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info*);
1469
1470 /*  eSwitch management functions */
1471 int qlcnic_config_switch_port(struct qlcnic_adapter *,
1472                                 struct qlcnic_esw_func_cfg *);
1473 int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *,
1474                                 struct qlcnic_esw_func_cfg *);
1475 int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8);
1476 int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8,
1477                                         struct __qlcnic_esw_statistics *);
1478 int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8,
1479                                         struct __qlcnic_esw_statistics *);
1480 int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8);
1481 extern int qlcnic_config_tso;
1482
1483 /*
1484  * QLOGIC Board information
1485  */
1486
1487 #define QLCNIC_MAX_BOARD_NAME_LEN 100
1488 struct qlcnic_brdinfo {
1489         unsigned short  vendor;
1490         unsigned short  device;
1491         unsigned short  sub_vendor;
1492         unsigned short  sub_device;
1493         char short_name[QLCNIC_MAX_BOARD_NAME_LEN];
1494 };
1495
1496 static const struct qlcnic_brdinfo qlcnic_boards[] = {
1497         {0x1077, 0x8020, 0x1077, 0x203,
1498                 "8200 Series Single Port 10GbE Converged Network Adapter "
1499                 "(TCP/IP Networking)"},
1500         {0x1077, 0x8020, 0x1077, 0x207,
1501                 "8200 Series Dual Port 10GbE Converged Network Adapter "
1502                 "(TCP/IP Networking)"},
1503         {0x1077, 0x8020, 0x1077, 0x20b,
1504                 "3200 Series Dual Port 10Gb Intelligent Ethernet Adapter"},
1505         {0x1077, 0x8020, 0x1077, 0x20c,
1506                 "3200 Series Quad Port 1Gb Intelligent Ethernet Adapter"},
1507         {0x1077, 0x8020, 0x1077, 0x20f,
1508                 "3200 Series Single Port 10Gb Intelligent Ethernet Adapter"},
1509         {0x1077, 0x8020, 0x103c, 0x3733,
1510                 "NC523SFP 10Gb 2-port Server Adapter"},
1511         {0x1077, 0x8020, 0x103c, 0x3346,
1512                 "CN1000Q Dual Port Converged Network Adapter"},
1513         {0x1077, 0x8020, 0x0, 0x0, "cLOM8214 1/10GbE Controller"},
1514 };
1515
1516 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(qlcnic_boards)
1517
1518 static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring)
1519 {
1520         if (likely(tx_ring->producer < tx_ring->sw_consumer))
1521                 return tx_ring->sw_consumer - tx_ring->producer;
1522         else
1523                 return tx_ring->sw_consumer + tx_ring->num_desc -
1524                                 tx_ring->producer;
1525 }
1526
1527 extern const struct ethtool_ops qlcnic_ethtool_ops;
1528
1529 struct qlcnic_nic_template {
1530         int (*config_bridged_mode) (struct qlcnic_adapter *, u32);
1531         int (*config_led) (struct qlcnic_adapter *, u32, u32);
1532         int (*start_firmware) (struct qlcnic_adapter *);
1533 };
1534
1535 #define QLCDB(adapter, lvl, _fmt, _args...) do {        \
1536         if (NETIF_MSG_##lvl & adapter->msg_enable)      \
1537                 printk(KERN_INFO "%s: %s: " _fmt,       \
1538                          dev_name(&adapter->pdev->dev), \
1539                         __func__, ##_args);             \
1540         } while (0)
1541
1542 #endif                          /* __QLCNIC_H_ */