2 * Copyright (C) 2009 - QLogic Corporation.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
20 * The full GNU General Public License is included in this distribution
21 * in the file called "COPYING".
28 #include <linux/module.h>
29 #include <linux/kernel.h>
30 #include <linux/types.h>
31 #include <linux/ioport.h>
32 #include <linux/pci.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
37 #include <linux/tcp.h>
38 #include <linux/skbuff.h>
39 #include <linux/firmware.h>
41 #include <linux/ethtool.h>
42 #include <linux/mii.h>
43 #include <linux/timer.h>
45 #include <linux/vmalloc.h>
48 #include <asm/byteorder.h>
50 #include "qlcnic_hdr.h"
52 #define _QLCNIC_LINUX_MAJOR 5
53 #define _QLCNIC_LINUX_MINOR 0
54 #define _QLCNIC_LINUX_SUBVERSION 5
55 #define QLCNIC_LINUX_VERSIONID "5.0.5"
56 #define QLCNIC_DRV_IDC_VER 0x01
58 #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c))
59 #define _major(v) (((v) >> 24) & 0xff)
60 #define _minor(v) (((v) >> 16) & 0xff)
61 #define _build(v) ((v) & 0xffff)
63 /* version in image has weird encoding:
66 * 31:16 - build (little endian)
68 #define QLCNIC_DECODE_VERSION(v) \
69 QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
71 #define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2)
72 #define QLCNIC_NUM_FLASH_SECTORS (64)
73 #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024)
74 #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \
75 * QLCNIC_FLASH_SECTOR_SIZE)
77 #define RCV_DESC_RINGSIZE(rds_ring) \
78 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
79 #define RCV_BUFF_RINGSIZE(rds_ring) \
80 (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc)
81 #define STATUS_DESC_RINGSIZE(sds_ring) \
82 (sizeof(struct status_desc) * (sds_ring)->num_desc)
83 #define TX_BUFF_RINGSIZE(tx_ring) \
84 (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc)
85 #define TX_DESC_RINGSIZE(tx_ring) \
86 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
88 #define QLCNIC_P3P_A0 0x50
90 #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0)
92 #define FIRST_PAGE_GROUP_START 0
93 #define FIRST_PAGE_GROUP_END 0x100000
95 #define P3_MAX_MTU (9600)
96 #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */
98 #define QLCNIC_P3_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN)
99 #define QLCNIC_P3_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3_MAX_MTU)
100 #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048
101 #define QLCNIC_LRO_BUFFER_EXTRA 2048
103 /* Opcodes to be used with the commands */
104 #define TX_ETHER_PKT 0x01
105 #define TX_TCP_PKT 0x02
106 #define TX_UDP_PKT 0x03
107 #define TX_IP_PKT 0x04
108 #define TX_TCP_LSO 0x05
109 #define TX_TCP_LSO6 0x06
110 #define TX_IPSEC 0x07
111 #define TX_IPSEC_CMD 0x0a
112 #define TX_TCPV6_PKT 0x0b
113 #define TX_UDPV6_PKT 0x0c
116 #define MAX_BUFFERS_PER_CMD 32
117 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + 4)
118 #define QLCNIC_MAX_TX_TIMEOUTS 2
121 * Following are the states of the Phantom. Phantom will set them and
122 * Host will read to check if the fields are correct.
124 #define PHAN_INITIALIZE_FAILED 0xffff
125 #define PHAN_INITIALIZE_COMPLETE 0xff01
127 /* Host writes the following to notify that it has done the init-handshake */
128 #define PHAN_INITIALIZE_ACK 0xf00f
129 #define PHAN_PEG_RCV_INITIALIZED 0xff01
131 #define NUM_RCV_DESC_RINGS 3
132 #define NUM_STS_DESC_RINGS 4
134 #define RCV_RING_NORMAL 0
135 #define RCV_RING_JUMBO 1
137 #define MIN_CMD_DESCRIPTORS 64
138 #define MIN_RCV_DESCRIPTORS 64
139 #define MIN_JUMBO_DESCRIPTORS 32
141 #define MAX_CMD_DESCRIPTORS 1024
142 #define MAX_RCV_DESCRIPTORS_1G 4096
143 #define MAX_RCV_DESCRIPTORS_10G 8192
144 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512
145 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024
147 #define DEFAULT_RCV_DESCRIPTORS_1G 2048
148 #define DEFAULT_RCV_DESCRIPTORS_10G 4096
150 #define get_next_index(index, length) \
151 (((index) + 1) & ((length) - 1))
154 * Following data structures describe the descriptors that will be used.
155 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
156 * we are doing LSO (above the 1500 size packet) only.
159 #define FLAGS_VLAN_TAGGED 0x10
160 #define FLAGS_VLAN_OOB 0x40
162 #define qlcnic_set_tx_vlan_tci(cmd_desc, v) \
163 (cmd_desc)->vlan_TCI = cpu_to_le16(v);
164 #define qlcnic_set_cmd_desc_port(cmd_desc, var) \
165 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
166 #define qlcnic_set_cmd_desc_ctxid(cmd_desc, var) \
167 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
169 #define qlcnic_set_tx_port(_desc, _port) \
170 ((_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0))
172 #define qlcnic_set_tx_flags_opcode(_desc, _flags, _opcode) \
173 ((_desc)->flags_opcode = \
174 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7)))
176 #define qlcnic_set_tx_frags_len(_desc, _frags, _len) \
177 ((_desc)->nfrags__length = \
178 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8)))
180 struct cmd_desc_type0
{
181 u8 tcp_hdr_offset
; /* For LSO only */
182 u8 ip_hdr_offset
; /* For LSO only */
183 __le16 flags_opcode
; /* 15:13 unused, 12:7 opcode, 6:0 flags */
184 __le32 nfrags__length
; /* 31:8 total len, 7:0 frag count */
188 __le16 reference_handle
;
190 u8 port_ctxid
; /* 7:4 ctxid 3:0 port */
191 u8 total_hdr_length
; /* LSO only : MAC+IP+TCP Hdr size */
192 __le16 conn_id
; /* IPSec offoad only */
197 __le16 buffer_length
[4];
201 u8 eth_addr
[ETH_ALEN
];
204 } __attribute__ ((aligned(64)));
206 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
208 __le16 reference_handle
;
210 __le32 buffer_length
; /* allocated buffer length (usually 2K) */
214 /* opcode field in status_desc */
215 #define QLCNIC_SYN_OFFLOAD 0x03
216 #define QLCNIC_RXPKT_DESC 0x04
217 #define QLCNIC_OLD_RXPKT_DESC 0x3f
218 #define QLCNIC_RESPONSE_DESC 0x05
219 #define QLCNIC_LRO_DESC 0x12
221 /* for status field in status_desc */
222 #define STATUS_CKSUM_OK (2)
224 /* owner bits of status_desc */
225 #define STATUS_OWNER_HOST (0x1ULL << 56)
226 #define STATUS_OWNER_PHANTOM (0x2ULL << 56)
228 /* Status descriptor:
229 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
230 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
231 53-55 desc_cnt, 56-57 owner, 58-63 opcode
233 #define qlcnic_get_sts_port(sts_data) \
235 #define qlcnic_get_sts_status(sts_data) \
236 (((sts_data) >> 4) & 0x0F)
237 #define qlcnic_get_sts_type(sts_data) \
238 (((sts_data) >> 8) & 0x0F)
239 #define qlcnic_get_sts_totallength(sts_data) \
240 (((sts_data) >> 12) & 0xFFFF)
241 #define qlcnic_get_sts_refhandle(sts_data) \
242 (((sts_data) >> 28) & 0xFFFF)
243 #define qlcnic_get_sts_prot(sts_data) \
244 (((sts_data) >> 44) & 0x0F)
245 #define qlcnic_get_sts_pkt_offset(sts_data) \
246 (((sts_data) >> 48) & 0x1F)
247 #define qlcnic_get_sts_desc_cnt(sts_data) \
248 (((sts_data) >> 53) & 0x7)
249 #define qlcnic_get_sts_opcode(sts_data) \
250 (((sts_data) >> 58) & 0x03F)
252 #define qlcnic_get_lro_sts_refhandle(sts_data) \
253 ((sts_data) & 0x0FFFF)
254 #define qlcnic_get_lro_sts_length(sts_data) \
255 (((sts_data) >> 16) & 0x0FFFF)
256 #define qlcnic_get_lro_sts_l2_hdr_offset(sts_data) \
257 (((sts_data) >> 32) & 0x0FF)
258 #define qlcnic_get_lro_sts_l4_hdr_offset(sts_data) \
259 (((sts_data) >> 40) & 0x0FF)
260 #define qlcnic_get_lro_sts_timestamp(sts_data) \
261 (((sts_data) >> 48) & 0x1)
262 #define qlcnic_get_lro_sts_type(sts_data) \
263 (((sts_data) >> 49) & 0x7)
264 #define qlcnic_get_lro_sts_push_flag(sts_data) \
265 (((sts_data) >> 52) & 0x1)
266 #define qlcnic_get_lro_sts_seq_number(sts_data) \
267 ((sts_data) & 0x0FFFFFFFF)
271 __le64 status_desc_data
[2];
272 } __attribute__ ((aligned(16)));
274 /* UNIFIED ROMIMAGE */
275 #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000
276 #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0
277 #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6
278 #define QLCNIC_UNI_DIR_SECT_FW 0x7
281 #define QLCNIC_UNI_CHIP_REV_OFF 10
282 #define QLCNIC_UNI_FLAGS_OFF 11
283 #define QLCNIC_UNI_BIOS_VERSION_OFF 12
284 #define QLCNIC_UNI_BOOTLD_IDX_OFF 27
285 #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29
287 struct uni_table_desc
{
294 struct uni_data_desc
{
300 /* Magic number to let user know flash is programmed */
301 #define QLCNIC_BDINFO_MAGIC 0x12345678
303 #define QLCNIC_BRDTYPE_P3_REF_QG 0x0021
304 #define QLCNIC_BRDTYPE_P3_HMEZ 0x0022
305 #define QLCNIC_BRDTYPE_P3_10G_CX4_LP 0x0023
306 #define QLCNIC_BRDTYPE_P3_4_GB 0x0024
307 #define QLCNIC_BRDTYPE_P3_IMEZ 0x0025
308 #define QLCNIC_BRDTYPE_P3_10G_SFP_PLUS 0x0026
309 #define QLCNIC_BRDTYPE_P3_10000_BASE_T 0x0027
310 #define QLCNIC_BRDTYPE_P3_XG_LOM 0x0028
311 #define QLCNIC_BRDTYPE_P3_4_GB_MM 0x0029
312 #define QLCNIC_BRDTYPE_P3_10G_SFP_CT 0x002a
313 #define QLCNIC_BRDTYPE_P3_10G_SFP_QT 0x002b
314 #define QLCNIC_BRDTYPE_P3_10G_CX4 0x0031
315 #define QLCNIC_BRDTYPE_P3_10G_XFP 0x0032
316 #define QLCNIC_BRDTYPE_P3_10G_TP 0x0080
318 #define QLCNIC_MSIX_TABLE_OFFSET 0x44
320 /* Flash memory map */
321 #define QLCNIC_BRDCFG_START 0x4000 /* board config */
322 #define QLCNIC_BOOTLD_START 0x10000 /* bootld */
323 #define QLCNIC_IMAGE_START 0x43000 /* compressed image */
324 #define QLCNIC_USER_START 0x3E8000 /* Firmare info */
326 #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408)
327 #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c)
328 #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c)
329 #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c)
331 #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8)
332 #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128)
334 #define QLCNIC_FW_MIN_SIZE (0x3fffff)
335 #define QLCNIC_UNIFIED_ROMIMAGE 0
336 #define QLCNIC_FLASH_ROMIMAGE 1
337 #define QLCNIC_UNKNOWN_ROMIMAGE 0xff
339 #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin"
340 #define QLCNIC_FLASH_ROMIMAGE_NAME "flash"
342 extern char qlcnic_driver_name
[];
344 /* Number of status descriptors to handle per interrupt */
345 #define MAX_STATUS_HANDLE (64)
348 * qlcnic_skb_frag{} is to contain mapping info for each SG list. This
349 * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}.
351 struct qlcnic_skb_frag
{
356 struct qlcnic_recv_crb
{
357 u32 crb_rcv_producer
[NUM_RCV_DESC_RINGS
];
358 u32 crb_sts_consumer
[NUM_STS_DESC_RINGS
];
359 u32 sw_int_mask
[NUM_STS_DESC_RINGS
];
362 /* Following defines are for the state of the buffers */
363 #define QLCNIC_BUFFER_FREE 0
364 #define QLCNIC_BUFFER_BUSY 1
367 * There will be one qlcnic_buffer per skb packet. These will be
368 * used to save the dma info for pci_unmap_page()
370 struct qlcnic_cmd_buffer
{
372 struct qlcnic_skb_frag frag_array
[MAX_BUFFERS_PER_CMD
+ 1];
376 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
377 struct qlcnic_rx_buffer
{
378 struct list_head list
;
386 #define QLCNIC_GBE 0x01
387 #define QLCNIC_XGBE 0x02
390 * One hardware_context{} per adapter
391 * contains interrupt info as well shared hardware info.
393 struct qlcnic_hardware_context
{
394 void __iomem
*pci_base0
;
395 void __iomem
*ocm_win_crb
;
397 unsigned long pci_len0
;
400 struct mutex mem_lock
;
409 struct qlcnic_adapter_stats
{
423 u64 skb_alloc_failure
;
426 u64 rx_dma_map_error
;
427 u64 tx_dma_map_error
;
431 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
432 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
434 struct qlcnic_host_rds_ring
{
440 void __iomem
*crb_rcv_producer
;
441 struct rcv_desc
*desc_head
;
442 struct qlcnic_rx_buffer
*rx_buf_arr
;
443 struct list_head free_list
;
445 dma_addr_t phys_addr
;
448 struct qlcnic_host_sds_ring
{
451 void __iomem
*crb_sts_consumer
;
452 void __iomem
*crb_intr_mask
;
454 struct status_desc
*desc_head
;
455 struct qlcnic_adapter
*adapter
;
456 struct napi_struct napi
;
457 struct list_head free_list
[NUM_RCV_DESC_RINGS
];
461 dma_addr_t phys_addr
;
462 char name
[IFNAMSIZ
+4];
465 struct qlcnic_host_tx_ring
{
469 void __iomem
*crb_cmd_producer
;
472 struct netdev_queue
*txq
;
474 struct qlcnic_cmd_buffer
*cmd_buf_arr
;
475 struct cmd_desc_type0
*desc_head
;
476 dma_addr_t phys_addr
;
477 dma_addr_t hw_cons_phys_addr
;
481 * Receive context. There is one such structure per instance of the
482 * receive processing. Any state information that is relevant to
483 * the receive, and is must be in this structure. The global data may be
486 struct qlcnic_recv_context
{
491 struct qlcnic_host_rds_ring
*rds_rings
;
492 struct qlcnic_host_sds_ring
*sds_rings
;
495 /* HW context creation */
497 #define QLCNIC_OS_CRB_RETRY_COUNT 4000
498 #define QLCNIC_CDRP_SIGNATURE_MAKE(pcifn, version) \
499 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
501 #define QLCNIC_CDRP_CMD_BIT 0x80000000
504 * All responses must have the QLCNIC_CDRP_CMD_BIT cleared
505 * in the crb QLCNIC_CDRP_CRB_OFFSET.
507 #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp)
508 #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0)
510 #define QLCNIC_CDRP_RSP_OK 0x00000001
511 #define QLCNIC_CDRP_RSP_FAIL 0x00000002
512 #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003
515 * All commands must have the QLCNIC_CDRP_CMD_BIT set in
516 * the crb QLCNIC_CDRP_CRB_OFFSET.
518 #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd))
519 #define QLCNIC_CDRP_IS_CMD(cmd) (((cmd) & QLCNIC_CDRP_CMD_BIT) != 0)
521 #define QLCNIC_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
522 #define QLCNIC_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
523 #define QLCNIC_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
524 #define QLCNIC_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
525 #define QLCNIC_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
526 #define QLCNIC_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
527 #define QLCNIC_CDRP_CMD_CREATE_RX_CTX 0x00000007
528 #define QLCNIC_CDRP_CMD_DESTROY_RX_CTX 0x00000008
529 #define QLCNIC_CDRP_CMD_CREATE_TX_CTX 0x00000009
530 #define QLCNIC_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
531 #define QLCNIC_CDRP_CMD_SETUP_STATISTICS 0x0000000e
532 #define QLCNIC_CDRP_CMD_GET_STATISTICS 0x0000000f
533 #define QLCNIC_CDRP_CMD_DELETE_STATISTICS 0x00000010
534 #define QLCNIC_CDRP_CMD_SET_MTU 0x00000012
535 #define QLCNIC_CDRP_CMD_READ_PHY 0x00000013
536 #define QLCNIC_CDRP_CMD_WRITE_PHY 0x00000014
537 #define QLCNIC_CDRP_CMD_READ_HW_REG 0x00000015
538 #define QLCNIC_CDRP_CMD_GET_FLOW_CTL 0x00000016
539 #define QLCNIC_CDRP_CMD_SET_FLOW_CTL 0x00000017
540 #define QLCNIC_CDRP_CMD_READ_MAX_MTU 0x00000018
541 #define QLCNIC_CDRP_CMD_READ_MAX_LRO 0x00000019
542 #define QLCNIC_CDRP_CMD_CONFIGURE_TOE 0x0000001a
543 #define QLCNIC_CDRP_CMD_FUNC_ATTRIB 0x0000001b
544 #define QLCNIC_CDRP_CMD_READ_PEXQ_PARAMETERS 0x0000001c
545 #define QLCNIC_CDRP_CMD_GET_LIC_CAPABILITIES 0x0000001d
546 #define QLCNIC_CDRP_CMD_READ_MAX_LRO_PER_BOARD 0x0000001e
547 #define QLCNIC_CDRP_CMD_MAC_ADDRESS 0x0000001f
549 #define QLCNIC_CDRP_CMD_GET_PCI_INFO 0x00000020
550 #define QLCNIC_CDRP_CMD_GET_NIC_INFO 0x00000021
551 #define QLCNIC_CDRP_CMD_SET_NIC_INFO 0x00000022
552 #define QLCNIC_CDRP_CMD_RESET_NPAR 0x00000023
553 #define QLCNIC_CDRP_CMD_GET_ESWITCH_CAPABILITY 0x00000024
554 #define QLCNIC_CDRP_CMD_TOGGLE_ESWITCH 0x00000025
555 #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATUS 0x00000026
556 #define QLCNIC_CDRP_CMD_SET_PORTMIRRORING 0x00000027
557 #define QLCNIC_CDRP_CMD_CONFIGURE_ESWITCH 0x00000028
559 #define QLCNIC_RCODE_SUCCESS 0
560 #define QLCNIC_RCODE_TIMEOUT 17
561 #define QLCNIC_DESTROY_CTX_RESET 0
564 * Capabilities Announced
566 #define QLCNIC_CAP0_LEGACY_CONTEXT (1)
567 #define QLCNIC_CAP0_LEGACY_MN (1 << 2)
568 #define QLCNIC_CAP0_LSO (1 << 6)
569 #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7)
570 #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8)
571 #define QLCNIC_CAP0_VALIDOFF (1 << 11)
577 #define QLCNIC_HOST_CTX_STATE_ACTIVE 2
583 struct qlcnic_hostrq_sds_ring
{
584 __le64 host_phys_addr
; /* Ring base addr */
585 __le32 ring_size
; /* Ring entries */
587 __le16 rsvd
; /* Padding */
590 struct qlcnic_hostrq_rds_ring
{
591 __le64 host_phys_addr
; /* Ring base addr */
592 __le64 buff_size
; /* Packet buffer size */
593 __le32 ring_size
; /* Ring entries */
594 __le32 ring_kind
; /* Class of ring */
597 struct qlcnic_hostrq_rx_ctx
{
598 __le64 host_rsp_dma_addr
; /* Response dma'd here */
599 __le32 capabilities
[4]; /* Flag bit vector */
600 __le32 host_int_crb_mode
; /* Interrupt crb usage */
601 __le32 host_rds_crb_mode
; /* RDS crb usage */
602 /* These ring offsets are relative to data[0] below */
603 __le32 rds_ring_offset
; /* Offset to RDS config */
604 __le32 sds_ring_offset
; /* Offset to SDS config */
605 __le16 num_rds_rings
; /* Count of RDS rings */
606 __le16 num_sds_rings
; /* Count of SDS rings */
607 __le16 valid_field_offset
;
610 u8 reserved
[128]; /* reserve space for future expansion*/
611 /* MUST BE 64-bit aligned.
612 The following is packed:
614 - N hostrq_sds_rings */
618 struct qlcnic_cardrsp_rds_ring
{
619 __le32 host_producer_crb
; /* Crb to use */
620 __le32 rsvd1
; /* Padding */
623 struct qlcnic_cardrsp_sds_ring
{
624 __le32 host_consumer_crb
; /* Crb to use */
625 __le32 interrupt_crb
; /* Crb to use */
628 struct qlcnic_cardrsp_rx_ctx
{
629 /* These ring offsets are relative to data[0] below */
630 __le32 rds_ring_offset
; /* Offset to RDS config */
631 __le32 sds_ring_offset
; /* Offset to SDS config */
632 __le32 host_ctx_state
; /* Starting State */
633 __le32 num_fn_per_port
; /* How many PCI fn share the port */
634 __le16 num_rds_rings
; /* Count of RDS rings */
635 __le16 num_sds_rings
; /* Count of SDS rings */
636 __le16 context_id
; /* Handle for context */
637 u8 phys_port
; /* Physical id of port */
638 u8 virt_port
; /* Virtual/Logical id of port */
639 u8 reserved
[128]; /* save space for future expansion */
640 /* MUST BE 64-bit aligned.
641 The following is packed:
642 - N cardrsp_rds_rings
643 - N cardrs_sds_rings */
647 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
648 (sizeof(HOSTRQ_RX) + \
649 (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \
650 (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring)))
652 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
653 (sizeof(CARDRSP_RX) + \
654 (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \
655 (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring)))
661 struct qlcnic_hostrq_cds_ring
{
662 __le64 host_phys_addr
; /* Ring base addr */
663 __le32 ring_size
; /* Ring entries */
664 __le32 rsvd
; /* Padding */
667 struct qlcnic_hostrq_tx_ctx
{
668 __le64 host_rsp_dma_addr
; /* Response dma'd here */
669 __le64 cmd_cons_dma_addr
; /* */
670 __le64 dummy_dma_addr
; /* */
671 __le32 capabilities
[4]; /* Flag bit vector */
672 __le32 host_int_crb_mode
; /* Interrupt crb usage */
673 __le32 rsvd1
; /* Padding */
674 __le16 rsvd2
; /* Padding */
675 __le16 interrupt_ctl
;
677 __le16 rsvd3
; /* Padding */
678 struct qlcnic_hostrq_cds_ring cds_ring
; /* Desc of cds ring */
679 u8 reserved
[128]; /* future expansion */
682 struct qlcnic_cardrsp_cds_ring
{
683 __le32 host_producer_crb
; /* Crb to use */
684 __le32 interrupt_crb
; /* Crb to use */
687 struct qlcnic_cardrsp_tx_ctx
{
688 __le32 host_ctx_state
; /* Starting state */
689 __le16 context_id
; /* Handle for context */
690 u8 phys_port
; /* Physical id of port */
691 u8 virt_port
; /* Virtual/Logical id of port */
692 struct qlcnic_cardrsp_cds_ring cds_ring
; /* Card cds settings */
693 u8 reserved
[128]; /* future expansion */
696 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
697 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
701 #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0
702 #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1
703 #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2
704 #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3
706 #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0
707 #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1
708 #define QLCNIC_HOST_INT_CRB_MODE_NORX 2
709 #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3
710 #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4
715 #define MC_COUNT_P3 38
717 #define QLCNIC_MAC_NOOP 0
718 #define QLCNIC_MAC_ADD 1
719 #define QLCNIC_MAC_DEL 2
721 struct qlcnic_mac_list_s
{
722 struct list_head list
;
723 uint8_t mac_addr
[ETH_ALEN
+2];
727 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
728 * adjusted based on configured MTU.
730 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_TIME_US 3
731 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_PACKETS 256
732 #define QLCNIC_DEFAULT_INTR_COALESCE_TX_PACKETS 64
733 #define QLCNIC_DEFAULT_INTR_COALESCE_TX_TIME_US 4
735 #define QLCNIC_INTR_DEFAULT 0x04
737 union qlcnic_nic_intr_coalesce_data
{
747 struct qlcnic_nic_intr_coalesce
{
749 u16 rate_sample_time
;
754 union qlcnic_nic_intr_coalesce_data normal
;
755 union qlcnic_nic_intr_coalesce_data low
;
756 union qlcnic_nic_intr_coalesce_data high
;
757 union qlcnic_nic_intr_coalesce_data irq
;
760 #define QLCNIC_HOST_REQUEST 0x13
761 #define QLCNIC_REQUEST 0x14
763 #define QLCNIC_MAC_EVENT 0x1
765 #define QLCNIC_IP_UP 2
766 #define QLCNIC_IP_DOWN 3
769 * Driver --> Firmware
771 #define QLCNIC_H2C_OPCODE_START 0
772 #define QLCNIC_H2C_OPCODE_CONFIG_RSS 1
773 #define QLCNIC_H2C_OPCODE_CONFIG_RSS_TBL 2
774 #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 3
775 #define QLCNIC_H2C_OPCODE_CONFIG_LED 4
776 #define QLCNIC_H2C_OPCODE_CONFIG_PROMISCUOUS 5
777 #define QLCNIC_H2C_OPCODE_CONFIG_L2_MAC 6
778 #define QLCNIC_H2C_OPCODE_LRO_REQUEST 7
779 #define QLCNIC_H2C_OPCODE_GET_SNMP_STATS 8
780 #define QLCNIC_H2C_OPCODE_PROXY_START_REQUEST 9
781 #define QLCNIC_H2C_OPCODE_PROXY_STOP_REQUEST 10
782 #define QLCNIC_H2C_OPCODE_PROXY_SET_MTU 11
783 #define QLCNIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE 12
784 #define QLCNIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST 13
785 #define QLCNIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST 14
786 #define QLCNIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST 15
787 #define QLCNIC_H2C_OPCODE_GET_NET_STATS 16
788 #define QLCNIC_H2C_OPCODE_PROXY_UPDATE_P2V 17
789 #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 18
790 #define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 19
791 #define QLCNIC_H2C_OPCODE_PROXY_STOP_DONE 20
792 #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 21
793 #define QLCNIC_C2C_OPCODE 22
794 #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 23
795 #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 24
796 #define QLCNIC_H2C_OPCODE_LAST 25
798 * Firmware --> Driver
801 #define QLCNIC_C2H_OPCODE_START 128
802 #define QLCNIC_C2H_OPCODE_CONFIG_RSS_RESPONSE 129
803 #define QLCNIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE 130
804 #define QLCNIC_C2H_OPCODE_CONFIG_MAC_RESPONSE 131
805 #define QLCNIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE 132
806 #define QLCNIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE 133
807 #define QLCNIC_C2H_OPCODE_LRO_DELETE_RESPONSE 134
808 #define QLCNIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE 135
809 #define QLCNIC_C2H_OPCODE_GET_SNMP_STATS 136
810 #define QLCNIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY 137
811 #define QLCNIC_C2H_OPCODE_INSTALL_LICENSE_REPLY 138
812 #define QLCNIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139
813 #define QLCNIC_C2H_OPCODE_GET_NET_STATS_RESPONSE 140
814 #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141
815 #define QLCNIC_C2H_OPCODE_LAST 142
817 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
818 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
819 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
821 #define QLCNIC_LRO_REQUEST_CLEANUP 4
823 /* Capabilites received */
824 #define QLCNIC_FW_CAPABILITY_BDG (1 << 8)
825 #define QLCNIC_FW_CAPABILITY_FVLANTX (1 << 9)
826 #define QLCNIC_FW_CAPABILITY_HW_LRO (1 << 10)
829 #define LINKEVENT_MODULE_NOT_PRESENT 1
830 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
831 #define LINKEVENT_MODULE_OPTICAL_SRLR 3
832 #define LINKEVENT_MODULE_OPTICAL_LRM 4
833 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
834 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
835 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
836 #define LINKEVENT_MODULE_TWINAX 8
838 #define LINKSPEED_10GBPS 10000
839 #define LINKSPEED_1GBPS 1000
840 #define LINKSPEED_100MBPS 100
841 #define LINKSPEED_10MBPS 10
843 #define LINKSPEED_ENCODED_10MBPS 0
844 #define LINKSPEED_ENCODED_100MBPS 1
845 #define LINKSPEED_ENCODED_1GBPS 2
847 #define LINKEVENT_AUTONEG_DISABLED 0
848 #define LINKEVENT_AUTONEG_ENABLED 1
850 #define LINKEVENT_HALF_DUPLEX 0
851 #define LINKEVENT_FULL_DUPLEX 1
853 #define LINKEVENT_LINKSPEED_MBPS 0
854 #define LINKEVENT_LINKSPEED_ENCODED 1
856 #define AUTO_FW_RESET_ENABLED 0x01
857 /* firmware response header:
858 * 63:58 - message type
862 * 47:40 - completion id
867 #define qlcnic_get_nic_msg_opcode(msg_hdr) \
868 ((msg_hdr >> 32) & 0xFF)
870 struct qlcnic_fw_msg
{
880 struct qlcnic_nic_req
{
886 struct qlcnic_mac_req
{
892 #define QLCNIC_MSI_ENABLED 0x02
893 #define QLCNIC_MSIX_ENABLED 0x04
894 #define QLCNIC_LRO_ENABLED 0x08
895 #define QLCNIC_BRIDGE_ENABLED 0X10
896 #define QLCNIC_DIAG_ENABLED 0x20
897 #define QLCNIC_ESWITCH_ENABLED 0x40
898 #define QLCNIC_IS_MSI_FAMILY(adapter) \
899 ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED))
901 #define MSIX_ENTRIES_PER_ADAPTER NUM_STS_DESC_RINGS
902 #define QLCNIC_MSIX_TBL_SPACE 8192
903 #define QLCNIC_PCI_REG_MSIX_TBL 0x44
904 #define QLCNIC_MSIX_TBL_PGSIZE 4096
906 #define QLCNIC_NETDEV_WEIGHT 128
907 #define QLCNIC_ADAPTER_UP_MAGIC 777
909 #define __QLCNIC_FW_ATTACHED 0
910 #define __QLCNIC_DEV_UP 1
911 #define __QLCNIC_RESETTING 2
912 #define __QLCNIC_START_FW 4
914 #define QLCNIC_INTERRUPT_TEST 1
915 #define QLCNIC_LOOPBACK_TEST 2
917 struct qlcnic_adapter
{
918 struct qlcnic_hardware_context ahw
;
920 struct net_device
*netdev
;
921 struct pci_dev
*pdev
;
922 struct list_head mac_list
;
924 spinlock_t tx_clean_lock
;
982 u8 mac_addr
[ETH_ALEN
];
986 struct qlcnic_pci_info
*npars
;
987 struct qlcnic_eswitch
*eswitch
;
988 struct qlcnic_nic_template
*nic_ops
;
990 struct qlcnic_adapter_stats stats
;
992 struct qlcnic_recv_context recv_ctx
;
993 struct qlcnic_host_tx_ring
*tx_ring
;
995 void __iomem
*tgt_mask_reg
;
996 void __iomem
*tgt_status_reg
;
997 void __iomem
*crb_int_state_reg
;
998 void __iomem
*isr_int_vec
;
1000 struct msix_entry msix_entries
[MSIX_ENTRIES_PER_ADAPTER
];
1002 struct delayed_work fw_work
;
1004 struct work_struct tx_timeout_task
;
1006 struct qlcnic_nic_intr_coalesce coal
;
1008 unsigned long state
;
1009 __le32 file_prd_off
; /*File fw product offset*/
1011 const struct firmware
*fw
;
1014 struct qlcnic_info
{
1016 __le16 op_mode
; /* 1 = Priv, 2 = NP, 3 = NP passthru */
1018 __le16 switch_mode
; /* 0 = disabled, 1 = int, 2 = ext */
1020 __le32 capabilities
;
1032 struct qlcnic_pci_info
{
1033 __le16 id
; /* pci function id */
1034 __le16 active
; /* 1 = Enabled */
1035 __le16 type
; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */
1036 __le16 default_port
; /* default port number */
1038 __le16 tx_min_bw
; /* Multiple of 100mbpc */
1040 __le16 reserved1
[2];
1046 struct qlcnic_eswitch
{
1050 u8 active_ucast_filters
;
1051 u8 max_ucast_filters
;
1052 u8 max_active_vlans
;
1055 #define QLCNIC_SWITCH_ENABLE BIT_1
1056 #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2
1057 #define QLCNIC_SWITCH_PROMISC_MODE BIT_3
1058 #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4
1061 int qlcnic_fw_cmd_query_phy(struct qlcnic_adapter
*adapter
, u32 reg
, u32
*val
);
1062 int qlcnic_fw_cmd_set_phy(struct qlcnic_adapter
*adapter
, u32 reg
, u32 val
);
1064 u32
qlcnic_hw_read_wx_2M(struct qlcnic_adapter
*adapter
, ulong off
);
1065 int qlcnic_hw_write_wx_2M(struct qlcnic_adapter
*, ulong off
, u32 data
);
1066 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter
*, u64 off
, u64 data
);
1067 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter
*, u64 off
, u64
*data
);
1068 void qlcnic_pci_camqm_read_2M(struct qlcnic_adapter
*, u64
, u64
*);
1069 void qlcnic_pci_camqm_write_2M(struct qlcnic_adapter
*, u64
, u64
);
1071 #define ADDR_IN_RANGE(addr, low, high) \
1072 (((addr) < (high)) && ((addr) >= (low)))
1074 #define QLCRD32(adapter, off) \
1075 (qlcnic_hw_read_wx_2M(adapter, off))
1076 #define QLCWR32(adapter, off, val) \
1077 (qlcnic_hw_write_wx_2M(adapter, off, val))
1079 int qlcnic_pcie_sem_lock(struct qlcnic_adapter
*, int, u32
);
1080 void qlcnic_pcie_sem_unlock(struct qlcnic_adapter
*, int);
1082 #define qlcnic_rom_lock(a) \
1083 qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID)
1084 #define qlcnic_rom_unlock(a) \
1085 qlcnic_pcie_sem_unlock((a), 2)
1086 #define qlcnic_phy_lock(a) \
1087 qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID)
1088 #define qlcnic_phy_unlock(a) \
1089 qlcnic_pcie_sem_unlock((a), 3)
1090 #define qlcnic_api_lock(a) \
1091 qlcnic_pcie_sem_lock((a), 5, 0)
1092 #define qlcnic_api_unlock(a) \
1093 qlcnic_pcie_sem_unlock((a), 5)
1094 #define qlcnic_sw_lock(a) \
1095 qlcnic_pcie_sem_lock((a), 6, 0)
1096 #define qlcnic_sw_unlock(a) \
1097 qlcnic_pcie_sem_unlock((a), 6)
1098 #define crb_win_lock(a) \
1099 qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID)
1100 #define crb_win_unlock(a) \
1101 qlcnic_pcie_sem_unlock((a), 7)
1103 int qlcnic_get_board_info(struct qlcnic_adapter
*adapter
);
1104 int qlcnic_wol_supported(struct qlcnic_adapter
*adapter
);
1105 int qlcnic_config_led(struct qlcnic_adapter
*adapter
, u32 state
, u32 rate
);
1107 /* Functions from qlcnic_init.c */
1108 int qlcnic_phantom_init(struct qlcnic_adapter
*adapter
);
1109 int qlcnic_load_firmware(struct qlcnic_adapter
*adapter
);
1110 int qlcnic_need_fw_reset(struct qlcnic_adapter
*adapter
);
1111 void qlcnic_request_firmware(struct qlcnic_adapter
*adapter
);
1112 void qlcnic_release_firmware(struct qlcnic_adapter
*adapter
);
1113 int qlcnic_pinit_from_rom(struct qlcnic_adapter
*adapter
);
1114 int qlcnic_setup_idc_param(struct qlcnic_adapter
*adapter
);
1115 int qlcnic_check_flash_fw_ver(struct qlcnic_adapter
*adapter
);
1117 int qlcnic_rom_fast_read(struct qlcnic_adapter
*adapter
, int addr
, int *valp
);
1118 int qlcnic_rom_fast_read_words(struct qlcnic_adapter
*adapter
, int addr
,
1119 u8
*bytes
, size_t size
);
1120 int qlcnic_alloc_sw_resources(struct qlcnic_adapter
*adapter
);
1121 void qlcnic_free_sw_resources(struct qlcnic_adapter
*adapter
);
1123 void __iomem
*qlcnic_get_ioaddr(struct qlcnic_adapter
*, u32
);
1125 int qlcnic_alloc_hw_resources(struct qlcnic_adapter
*adapter
);
1126 void qlcnic_free_hw_resources(struct qlcnic_adapter
*adapter
);
1128 void qlcnic_release_rx_buffers(struct qlcnic_adapter
*adapter
);
1129 void qlcnic_release_tx_buffers(struct qlcnic_adapter
*adapter
);
1131 int qlcnic_init_firmware(struct qlcnic_adapter
*adapter
);
1132 void qlcnic_watchdog_task(struct work_struct
*work
);
1133 void qlcnic_post_rx_buffers(struct qlcnic_adapter
*adapter
, u32 ringid
,
1134 struct qlcnic_host_rds_ring
*rds_ring
);
1135 int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring
*sds_ring
, int max
);
1136 void qlcnic_set_multi(struct net_device
*netdev
);
1137 void qlcnic_free_mac_list(struct qlcnic_adapter
*adapter
);
1138 int qlcnic_nic_set_promisc(struct qlcnic_adapter
*adapter
, u32
);
1139 int qlcnic_config_intr_coalesce(struct qlcnic_adapter
*adapter
);
1140 int qlcnic_config_rss(struct qlcnic_adapter
*adapter
, int enable
);
1141 int qlcnic_config_ipaddr(struct qlcnic_adapter
*adapter
, u32 ip
, int cmd
);
1142 int qlcnic_linkevent_request(struct qlcnic_adapter
*adapter
, int enable
);
1143 void qlcnic_advert_link_change(struct qlcnic_adapter
*adapter
, int linkup
);
1145 int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter
*adapter
, int mtu
);
1146 int qlcnic_change_mtu(struct net_device
*netdev
, int new_mtu
);
1147 int qlcnic_config_hw_lro(struct qlcnic_adapter
*adapter
, int enable
);
1148 int qlcnic_config_bridged_mode(struct qlcnic_adapter
*adapter
, u32 enable
);
1149 int qlcnic_send_lro_cleanup(struct qlcnic_adapter
*adapter
);
1150 void qlcnic_update_cmd_producer(struct qlcnic_adapter
*adapter
,
1151 struct qlcnic_host_tx_ring
*tx_ring
);
1152 int qlcnic_get_mac_addr(struct qlcnic_adapter
*adapter
, u8
*mac
);
1153 void qlcnic_clear_ilb_mode(struct qlcnic_adapter
*adapter
);
1154 int qlcnic_set_ilb_mode(struct qlcnic_adapter
*adapter
);
1155 void qlcnic_fetch_mac(struct qlcnic_adapter
*, u32
, u32
, u8
, u8
*);
1157 /* Functions from qlcnic_main.c */
1158 int qlcnic_reset_context(struct qlcnic_adapter
*);
1159 u32
qlcnic_issue_cmd(struct qlcnic_adapter
*adapter
,
1160 u32 pci_fn
, u32 version
, u32 arg1
, u32 arg2
, u32 arg3
, u32 cmd
);
1161 void qlcnic_diag_free_res(struct net_device
*netdev
, int max_sds_rings
);
1162 int qlcnic_diag_alloc_res(struct net_device
*netdev
, int test
);
1163 int qlcnic_check_loopback_buff(unsigned char *data
);
1164 netdev_tx_t
qlcnic_xmit_frame(struct sk_buff
*skb
, struct net_device
*netdev
);
1165 void qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring
*sds_ring
);
1167 /* Management functions */
1168 int qlcnic_set_mac_address(struct qlcnic_adapter
*, u8
*);
1169 int qlcnic_get_mac_address(struct qlcnic_adapter
*, u8
*);
1170 int qlcnic_get_nic_info(struct qlcnic_adapter
*, u8
);
1171 int qlcnic_set_nic_info(struct qlcnic_adapter
*, struct qlcnic_info
*);
1172 int qlcnic_get_pci_info(struct qlcnic_adapter
*);
1173 int qlcnic_reset_partition(struct qlcnic_adapter
*, u8
);
1175 /* eSwitch management functions */
1176 int qlcnic_get_eswitch_capabilities(struct qlcnic_adapter
*, u8
,
1177 struct qlcnic_eswitch
*);
1178 int qlcnic_get_eswitch_status(struct qlcnic_adapter
*, u8
,
1179 struct qlcnic_eswitch
*);
1180 int qlcnic_toggle_eswitch(struct qlcnic_adapter
*, u8
, u8
);
1181 int qlcnic_config_switch_port(struct qlcnic_adapter
*, u8
, int, u8
, u8
,
1183 int qlcnic_config_port_mirroring(struct qlcnic_adapter
*, u8
, u8
, u8
);
1184 extern int qlcnic_config_tso
;
1187 * QLOGIC Board information
1190 #define QLCNIC_MAX_BOARD_NAME_LEN 100
1191 struct qlcnic_brdinfo
{
1192 unsigned short vendor
;
1193 unsigned short device
;
1194 unsigned short sub_vendor
;
1195 unsigned short sub_device
;
1196 char short_name
[QLCNIC_MAX_BOARD_NAME_LEN
];
1199 static const struct qlcnic_brdinfo qlcnic_boards
[] = {
1200 {0x1077, 0x8020, 0x1077, 0x203,
1201 "8200 Series Single Port 10GbE Converged Network Adapter "
1202 "(TCP/IP Networking)"},
1203 {0x1077, 0x8020, 0x1077, 0x207,
1204 "8200 Series Dual Port 10GbE Converged Network Adapter "
1205 "(TCP/IP Networking)"},
1206 {0x1077, 0x8020, 0x1077, 0x20b,
1207 "3200 Series Dual Port 10Gb Intelligent Ethernet Adapter"},
1208 {0x1077, 0x8020, 0x1077, 0x20c,
1209 "3200 Series Quad Port 1Gb Intelligent Ethernet Adapter"},
1210 {0x1077, 0x8020, 0x1077, 0x20f,
1211 "3200 Series Single Port 10Gb Intelligent Ethernet Adapter"},
1212 {0x1077, 0x8020, 0x0, 0x0, "cLOM8214 1/10GbE Controller"},
1215 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(qlcnic_boards)
1217 static inline u32
qlcnic_tx_avail(struct qlcnic_host_tx_ring
*tx_ring
)
1220 if (tx_ring
->producer
< tx_ring
->sw_consumer
)
1221 return tx_ring
->sw_consumer
- tx_ring
->producer
;
1223 return tx_ring
->sw_consumer
+ tx_ring
->num_desc
-
1227 extern const struct ethtool_ops qlcnic_ethtool_ops
;
1229 struct qlcnic_nic_template
{
1230 int (*get_mac_addr
) (struct qlcnic_adapter
*, u8
*);
1231 int (*config_bridged_mode
) (struct qlcnic_adapter
*, u32
);
1232 int (*config_led
) (struct qlcnic_adapter
*, u32
, u32
);
1233 int (*set_ilb_mode
) (struct qlcnic_adapter
*);
1234 void (*clear_ilb_mode
) (struct qlcnic_adapter
*);
1235 int (*start_firmware
) (struct qlcnic_adapter
*);
1238 #define QLCDB(adapter, lvl, _fmt, _args...) do { \
1239 if (NETIF_MSG_##lvl & adapter->msg_enable) \
1240 printk(KERN_INFO "%s: %s: " _fmt, \
1241 dev_name(&adapter->pdev->dev), \
1242 __func__, ##_args); \
1245 #endif /* __QLCNIC_H_ */