2 * Copyright (C) 2009 - QLogic Corporation.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
20 * The full GNU General Public License is included in this distribution
21 * in the file called "COPYING".
25 #ifndef __QLCNIC_HDR_H_
26 #define __QLCNIC_HDR_H_
28 #include <linux/kernel.h>
29 #include <linux/types.h>
32 * The basic unit of access when reading/writing control registers.
36 QLCNIC_HW_H0_CH_HUB_ADR
= 0x05,
37 QLCNIC_HW_H1_CH_HUB_ADR
= 0x0E,
38 QLCNIC_HW_H2_CH_HUB_ADR
= 0x03,
39 QLCNIC_HW_H3_CH_HUB_ADR
= 0x01,
40 QLCNIC_HW_H4_CH_HUB_ADR
= 0x06,
41 QLCNIC_HW_H5_CH_HUB_ADR
= 0x07,
42 QLCNIC_HW_H6_CH_HUB_ADR
= 0x08
47 QLCNIC_HW_MN_CRB_AGT_ADR
= 0x15,
48 QLCNIC_HW_MS_CRB_AGT_ADR
= 0x25
53 QLCNIC_HW_PS_CRB_AGT_ADR
= 0x73,
54 QLCNIC_HW_SS_CRB_AGT_ADR
= 0x20,
55 QLCNIC_HW_RPMX3_CRB_AGT_ADR
= 0x0b,
56 QLCNIC_HW_QMS_CRB_AGT_ADR
= 0x00,
57 QLCNIC_HW_SQGS0_CRB_AGT_ADR
= 0x01,
58 QLCNIC_HW_SQGS1_CRB_AGT_ADR
= 0x02,
59 QLCNIC_HW_SQGS2_CRB_AGT_ADR
= 0x03,
60 QLCNIC_HW_SQGS3_CRB_AGT_ADR
= 0x04,
61 QLCNIC_HW_C2C0_CRB_AGT_ADR
= 0x58,
62 QLCNIC_HW_C2C1_CRB_AGT_ADR
= 0x59,
63 QLCNIC_HW_C2C2_CRB_AGT_ADR
= 0x5a,
64 QLCNIC_HW_RPMX2_CRB_AGT_ADR
= 0x0a,
65 QLCNIC_HW_RPMX4_CRB_AGT_ADR
= 0x0c,
66 QLCNIC_HW_RPMX7_CRB_AGT_ADR
= 0x0f,
67 QLCNIC_HW_RPMX9_CRB_AGT_ADR
= 0x12,
68 QLCNIC_HW_SMB_CRB_AGT_ADR
= 0x18
73 QLCNIC_HW_NIU_CRB_AGT_ADR
= 0x31,
74 QLCNIC_HW_I2C0_CRB_AGT_ADR
= 0x19,
75 QLCNIC_HW_I2C1_CRB_AGT_ADR
= 0x29,
77 QLCNIC_HW_SN_CRB_AGT_ADR
= 0x10,
78 QLCNIC_HW_I2Q_CRB_AGT_ADR
= 0x20,
79 QLCNIC_HW_LPC_CRB_AGT_ADR
= 0x22,
80 QLCNIC_HW_ROMUSB_CRB_AGT_ADR
= 0x21,
81 QLCNIC_HW_QM_CRB_AGT_ADR
= 0x66,
82 QLCNIC_HW_SQG0_CRB_AGT_ADR
= 0x60,
83 QLCNIC_HW_SQG1_CRB_AGT_ADR
= 0x61,
84 QLCNIC_HW_SQG2_CRB_AGT_ADR
= 0x62,
85 QLCNIC_HW_SQG3_CRB_AGT_ADR
= 0x63,
86 QLCNIC_HW_RPMX1_CRB_AGT_ADR
= 0x09,
87 QLCNIC_HW_RPMX5_CRB_AGT_ADR
= 0x0d,
88 QLCNIC_HW_RPMX6_CRB_AGT_ADR
= 0x0e,
89 QLCNIC_HW_RPMX8_CRB_AGT_ADR
= 0x11
94 QLCNIC_HW_PH_CRB_AGT_ADR
= 0x1A,
95 QLCNIC_HW_SRE_CRB_AGT_ADR
= 0x50,
96 QLCNIC_HW_EG_CRB_AGT_ADR
= 0x51,
97 QLCNIC_HW_RPMX0_CRB_AGT_ADR
= 0x08
102 QLCNIC_HW_PEGN0_CRB_AGT_ADR
= 0x40,
103 QLCNIC_HW_PEGN1_CRB_AGT_ADR
,
104 QLCNIC_HW_PEGN2_CRB_AGT_ADR
,
105 QLCNIC_HW_PEGN3_CRB_AGT_ADR
,
106 QLCNIC_HW_PEGNI_CRB_AGT_ADR
,
107 QLCNIC_HW_PEGND_CRB_AGT_ADR
,
108 QLCNIC_HW_PEGNC_CRB_AGT_ADR
,
109 QLCNIC_HW_PEGR0_CRB_AGT_ADR
,
110 QLCNIC_HW_PEGR1_CRB_AGT_ADR
,
111 QLCNIC_HW_PEGR2_CRB_AGT_ADR
,
112 QLCNIC_HW_PEGR3_CRB_AGT_ADR
,
113 QLCNIC_HW_PEGN4_CRB_AGT_ADR
118 QLCNIC_HW_PEGS0_CRB_AGT_ADR
= 0x40,
119 QLCNIC_HW_PEGS1_CRB_AGT_ADR
,
120 QLCNIC_HW_PEGS2_CRB_AGT_ADR
,
121 QLCNIC_HW_PEGS3_CRB_AGT_ADR
,
122 QLCNIC_HW_PEGSI_CRB_AGT_ADR
,
123 QLCNIC_HW_PEGSD_CRB_AGT_ADR
,
124 QLCNIC_HW_PEGSC_CRB_AGT_ADR
129 QLCNIC_HW_CAS0_CRB_AGT_ADR
= 0x46,
130 QLCNIC_HW_CAS1_CRB_AGT_ADR
= 0x47,
131 QLCNIC_HW_CAS2_CRB_AGT_ADR
= 0x48,
132 QLCNIC_HW_CAS3_CRB_AGT_ADR
= 0x49,
133 QLCNIC_HW_NCM_CRB_AGT_ADR
= 0x16,
134 QLCNIC_HW_TMR_CRB_AGT_ADR
= 0x17,
135 QLCNIC_HW_XDMA_CRB_AGT_ADR
= 0x05,
136 QLCNIC_HW_OCM0_CRB_AGT_ADR
= 0x06,
137 QLCNIC_HW_OCM1_CRB_AGT_ADR
= 0x07
140 /* Floaters - non existent modules */
141 #define QLCNIC_HW_EFC_RPMX0_CRB_AGT_ADR 0x67
143 /* This field defines PCI/X adr [25:20] of agents on the CRB */
145 QLCNIC_HW_PX_MAP_CRB_PH
= 0,
146 QLCNIC_HW_PX_MAP_CRB_PS
,
147 QLCNIC_HW_PX_MAP_CRB_MN
,
148 QLCNIC_HW_PX_MAP_CRB_MS
,
149 QLCNIC_HW_PX_MAP_CRB_PGR1
,
150 QLCNIC_HW_PX_MAP_CRB_SRE
,
151 QLCNIC_HW_PX_MAP_CRB_NIU
,
152 QLCNIC_HW_PX_MAP_CRB_QMN
,
153 QLCNIC_HW_PX_MAP_CRB_SQN0
,
154 QLCNIC_HW_PX_MAP_CRB_SQN1
,
155 QLCNIC_HW_PX_MAP_CRB_SQN2
,
156 QLCNIC_HW_PX_MAP_CRB_SQN3
,
157 QLCNIC_HW_PX_MAP_CRB_QMS
,
158 QLCNIC_HW_PX_MAP_CRB_SQS0
,
159 QLCNIC_HW_PX_MAP_CRB_SQS1
,
160 QLCNIC_HW_PX_MAP_CRB_SQS2
,
161 QLCNIC_HW_PX_MAP_CRB_SQS3
,
162 QLCNIC_HW_PX_MAP_CRB_PGN0
,
163 QLCNIC_HW_PX_MAP_CRB_PGN1
,
164 QLCNIC_HW_PX_MAP_CRB_PGN2
,
165 QLCNIC_HW_PX_MAP_CRB_PGN3
,
166 QLCNIC_HW_PX_MAP_CRB_PGND
,
167 QLCNIC_HW_PX_MAP_CRB_PGNI
,
168 QLCNIC_HW_PX_MAP_CRB_PGS0
,
169 QLCNIC_HW_PX_MAP_CRB_PGS1
,
170 QLCNIC_HW_PX_MAP_CRB_PGS2
,
171 QLCNIC_HW_PX_MAP_CRB_PGS3
,
172 QLCNIC_HW_PX_MAP_CRB_PGSD
,
173 QLCNIC_HW_PX_MAP_CRB_PGSI
,
174 QLCNIC_HW_PX_MAP_CRB_SN
,
175 QLCNIC_HW_PX_MAP_CRB_PGR2
,
176 QLCNIC_HW_PX_MAP_CRB_EG
,
177 QLCNIC_HW_PX_MAP_CRB_PH2
,
178 QLCNIC_HW_PX_MAP_CRB_PS2
,
179 QLCNIC_HW_PX_MAP_CRB_CAM
,
180 QLCNIC_HW_PX_MAP_CRB_CAS0
,
181 QLCNIC_HW_PX_MAP_CRB_CAS1
,
182 QLCNIC_HW_PX_MAP_CRB_CAS2
,
183 QLCNIC_HW_PX_MAP_CRB_C2C0
,
184 QLCNIC_HW_PX_MAP_CRB_C2C1
,
185 QLCNIC_HW_PX_MAP_CRB_TIMR
,
186 QLCNIC_HW_PX_MAP_CRB_PGR3
,
187 QLCNIC_HW_PX_MAP_CRB_RPMX1
,
188 QLCNIC_HW_PX_MAP_CRB_RPMX2
,
189 QLCNIC_HW_PX_MAP_CRB_RPMX3
,
190 QLCNIC_HW_PX_MAP_CRB_RPMX4
,
191 QLCNIC_HW_PX_MAP_CRB_RPMX5
,
192 QLCNIC_HW_PX_MAP_CRB_RPMX6
,
193 QLCNIC_HW_PX_MAP_CRB_RPMX7
,
194 QLCNIC_HW_PX_MAP_CRB_XDMA
,
195 QLCNIC_HW_PX_MAP_CRB_I2Q
,
196 QLCNIC_HW_PX_MAP_CRB_ROMUSB
,
197 QLCNIC_HW_PX_MAP_CRB_CAS3
,
198 QLCNIC_HW_PX_MAP_CRB_RPMX0
,
199 QLCNIC_HW_PX_MAP_CRB_RPMX8
,
200 QLCNIC_HW_PX_MAP_CRB_RPMX9
,
201 QLCNIC_HW_PX_MAP_CRB_OCM0
,
202 QLCNIC_HW_PX_MAP_CRB_OCM1
,
203 QLCNIC_HW_PX_MAP_CRB_SMB
,
204 QLCNIC_HW_PX_MAP_CRB_I2C0
,
205 QLCNIC_HW_PX_MAP_CRB_I2C1
,
206 QLCNIC_HW_PX_MAP_CRB_LPC
,
207 QLCNIC_HW_PX_MAP_CRB_PGNC
,
208 QLCNIC_HW_PX_MAP_CRB_PGR0
223 #define BIT_12 0x1000
224 #define BIT_13 0x2000
225 #define BIT_14 0x4000
226 #define BIT_15 0x8000
227 #define BIT_16 0x10000
228 #define BIT_17 0x20000
229 #define BIT_18 0x40000
230 #define BIT_19 0x80000
231 #define BIT_20 0x100000
232 #define BIT_21 0x200000
233 #define BIT_22 0x400000
234 #define BIT_23 0x800000
235 #define BIT_24 0x1000000
236 #define BIT_25 0x2000000
237 #define BIT_26 0x4000000
238 #define BIT_27 0x8000000
239 #define BIT_28 0x10000000
240 #define BIT_29 0x20000000
241 #define BIT_30 0x40000000
242 #define BIT_31 0x80000000
244 /* This field defines CRB adr [31:20] of the agents */
246 #define QLCNIC_HW_CRB_HUB_AGT_ADR_MN \
247 ((QLCNIC_HW_H0_CH_HUB_ADR << 7) | QLCNIC_HW_MN_CRB_AGT_ADR)
248 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PH \
249 ((QLCNIC_HW_H0_CH_HUB_ADR << 7) | QLCNIC_HW_PH_CRB_AGT_ADR)
250 #define QLCNIC_HW_CRB_HUB_AGT_ADR_MS \
251 ((QLCNIC_HW_H0_CH_HUB_ADR << 7) | QLCNIC_HW_MS_CRB_AGT_ADR)
253 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PS \
254 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_PS_CRB_AGT_ADR)
255 #define QLCNIC_HW_CRB_HUB_AGT_ADR_SS \
256 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SS_CRB_AGT_ADR)
257 #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3 \
258 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX3_CRB_AGT_ADR)
259 #define QLCNIC_HW_CRB_HUB_AGT_ADR_QMS \
260 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_QMS_CRB_AGT_ADR)
261 #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS0 \
262 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS0_CRB_AGT_ADR)
263 #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS1 \
264 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS1_CRB_AGT_ADR)
265 #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS2 \
266 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS2_CRB_AGT_ADR)
267 #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS3 \
268 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS3_CRB_AGT_ADR)
269 #define QLCNIC_HW_CRB_HUB_AGT_ADR_C2C0 \
270 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_C2C0_CRB_AGT_ADR)
271 #define QLCNIC_HW_CRB_HUB_AGT_ADR_C2C1 \
272 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_C2C1_CRB_AGT_ADR)
273 #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2 \
274 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX2_CRB_AGT_ADR)
275 #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4 \
276 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX4_CRB_AGT_ADR)
277 #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7 \
278 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX7_CRB_AGT_ADR)
279 #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9 \
280 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX9_CRB_AGT_ADR)
281 #define QLCNIC_HW_CRB_HUB_AGT_ADR_SMB \
282 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SMB_CRB_AGT_ADR)
284 #define QLCNIC_HW_CRB_HUB_AGT_ADR_NIU \
285 ((QLCNIC_HW_H2_CH_HUB_ADR << 7) | QLCNIC_HW_NIU_CRB_AGT_ADR)
286 #define QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0 \
287 ((QLCNIC_HW_H2_CH_HUB_ADR << 7) | QLCNIC_HW_I2C0_CRB_AGT_ADR)
288 #define QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1 \
289 ((QLCNIC_HW_H2_CH_HUB_ADR << 7) | QLCNIC_HW_I2C1_CRB_AGT_ADR)
291 #define QLCNIC_HW_CRB_HUB_AGT_ADR_SRE \
292 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SRE_CRB_AGT_ADR)
293 #define QLCNIC_HW_CRB_HUB_AGT_ADR_EG \
294 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_EG_CRB_AGT_ADR)
295 #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0 \
296 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX0_CRB_AGT_ADR)
297 #define QLCNIC_HW_CRB_HUB_AGT_ADR_QMN \
298 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_QM_CRB_AGT_ADR)
299 #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0 \
300 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG0_CRB_AGT_ADR)
301 #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1 \
302 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG1_CRB_AGT_ADR)
303 #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2 \
304 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG2_CRB_AGT_ADR)
305 #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3 \
306 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG3_CRB_AGT_ADR)
307 #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1 \
308 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX1_CRB_AGT_ADR)
309 #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5 \
310 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX5_CRB_AGT_ADR)
311 #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6 \
312 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX6_CRB_AGT_ADR)
313 #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8 \
314 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX8_CRB_AGT_ADR)
315 #define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS0 \
316 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS0_CRB_AGT_ADR)
317 #define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS1 \
318 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS1_CRB_AGT_ADR)
319 #define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS2 \
320 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS2_CRB_AGT_ADR)
321 #define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS3 \
322 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS3_CRB_AGT_ADR)
324 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI \
325 ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGNI_CRB_AGT_ADR)
326 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGND \
327 ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGND_CRB_AGT_ADR)
328 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0 \
329 ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN0_CRB_AGT_ADR)
330 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1 \
331 ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN1_CRB_AGT_ADR)
332 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2 \
333 ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN2_CRB_AGT_ADR)
334 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3 \
335 ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN3_CRB_AGT_ADR)
336 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4 \
337 ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN4_CRB_AGT_ADR)
338 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC \
339 ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGNC_CRB_AGT_ADR)
340 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR0 \
341 ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR0_CRB_AGT_ADR)
342 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR1 \
343 ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR1_CRB_AGT_ADR)
344 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR2 \
345 ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR2_CRB_AGT_ADR)
346 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR3 \
347 ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR3_CRB_AGT_ADR)
349 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI \
350 ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGSI_CRB_AGT_ADR)
351 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGSD \
352 ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGSD_CRB_AGT_ADR)
353 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0 \
354 ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS0_CRB_AGT_ADR)
355 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1 \
356 ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS1_CRB_AGT_ADR)
357 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2 \
358 ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS2_CRB_AGT_ADR)
359 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3 \
360 ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS3_CRB_AGT_ADR)
361 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGSC \
362 ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGSC_CRB_AGT_ADR)
364 #define QLCNIC_HW_CRB_HUB_AGT_ADR_CAM \
365 ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_NCM_CRB_AGT_ADR)
366 #define QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR \
367 ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_TMR_CRB_AGT_ADR)
368 #define QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA \
369 ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_XDMA_CRB_AGT_ADR)
370 #define QLCNIC_HW_CRB_HUB_AGT_ADR_SN \
371 ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_SN_CRB_AGT_ADR)
372 #define QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q \
373 ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_I2Q_CRB_AGT_ADR)
374 #define QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB \
375 ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_ROMUSB_CRB_AGT_ADR)
376 #define QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0 \
377 ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_OCM0_CRB_AGT_ADR)
378 #define QLCNIC_HW_CRB_HUB_AGT_ADR_OCM1 \
379 ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_OCM1_CRB_AGT_ADR)
380 #define QLCNIC_HW_CRB_HUB_AGT_ADR_LPC \
381 ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_LPC_CRB_AGT_ADR)
383 #define QLCNIC_SRE_MISC (QLCNIC_CRB_SRE + 0x0002c)
385 #define QLCNIC_I2Q_CLR_PCI_HI (QLCNIC_CRB_I2Q + 0x00034)
387 #define ROMUSB_GLB (QLCNIC_CRB_ROMUSB + 0x00000)
388 #define ROMUSB_ROM (QLCNIC_CRB_ROMUSB + 0x10000)
390 #define QLCNIC_ROMUSB_GLB_STATUS (ROMUSB_GLB + 0x0004)
391 #define QLCNIC_ROMUSB_GLB_SW_RESET (ROMUSB_GLB + 0x0008)
392 #define QLCNIC_ROMUSB_GLB_PAD_GPIO_I (ROMUSB_GLB + 0x000c)
393 #define QLCNIC_ROMUSB_GLB_CAS_RST (ROMUSB_GLB + 0x0038)
394 #define QLCNIC_ROMUSB_GLB_TEST_MUX_SEL (ROMUSB_GLB + 0x0044)
395 #define QLCNIC_ROMUSB_GLB_PEGTUNE_DONE (ROMUSB_GLB + 0x005c)
396 #define QLCNIC_ROMUSB_GLB_CHIP_CLK_CTRL (ROMUSB_GLB + 0x00A8)
398 #define QLCNIC_ROMUSB_GPIO(n) (ROMUSB_GLB + 0x60 + (4 * (n)))
400 #define QLCNIC_ROMUSB_ROM_INSTR_OPCODE (ROMUSB_ROM + 0x0004)
401 #define QLCNIC_ROMUSB_ROM_ADDRESS (ROMUSB_ROM + 0x0008)
402 #define QLCNIC_ROMUSB_ROM_WDATA (ROMUSB_ROM + 0x000c)
403 #define QLCNIC_ROMUSB_ROM_ABYTE_CNT (ROMUSB_ROM + 0x0010)
404 #define QLCNIC_ROMUSB_ROM_DUMMY_BYTE_CNT (ROMUSB_ROM + 0x0014)
405 #define QLCNIC_ROMUSB_ROM_RDATA (ROMUSB_ROM + 0x0018)
407 /* Lock IDs for ROM lock */
408 #define ROM_LOCK_DRIVER 0x0d417340
410 /******************************************************************************
412 * Definitions specific to M25P flash
414 *******************************************************************************
417 /* all are 1MB windows */
419 #define QLCNIC_PCI_CRB_WINDOWSIZE 0x00100000
420 #define QLCNIC_PCI_CRB_WINDOW(A) \
421 (QLCNIC_PCI_CRBSPACE + (A)*QLCNIC_PCI_CRB_WINDOWSIZE)
423 #define QLCNIC_CRB_NIU QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_NIU)
424 #define QLCNIC_CRB_SRE QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SRE)
425 #define QLCNIC_CRB_ROMUSB \
426 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_ROMUSB)
427 #define QLCNIC_CRB_I2Q QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_I2Q)
428 #define QLCNIC_CRB_I2C0 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_I2C0)
429 #define QLCNIC_CRB_SMB QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SMB)
430 #define QLCNIC_CRB_MAX QLCNIC_PCI_CRB_WINDOW(64)
432 #define QLCNIC_CRB_PCIX_HOST QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PH)
433 #define QLCNIC_CRB_PCIX_HOST2 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PH2)
434 #define QLCNIC_CRB_PEG_NET_0 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN0)
435 #define QLCNIC_CRB_PEG_NET_1 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN1)
436 #define QLCNIC_CRB_PEG_NET_2 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN2)
437 #define QLCNIC_CRB_PEG_NET_3 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN3)
438 #define QLCNIC_CRB_PEG_NET_4 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SQS2)
439 #define QLCNIC_CRB_PEG_NET_D QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGND)
440 #define QLCNIC_CRB_PEG_NET_I QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGNI)
441 #define QLCNIC_CRB_DDR_NET QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_MN)
442 #define QLCNIC_CRB_QDR_NET QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SN)
444 #define QLCNIC_CRB_PCIX_MD QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PS)
445 #define QLCNIC_CRB_PCIE QLCNIC_CRB_PCIX_MD
447 #define ISR_INT_VECTOR (QLCNIC_PCIX_PS_REG(PCIX_INT_VECTOR))
448 #define ISR_INT_MASK (QLCNIC_PCIX_PS_REG(PCIX_INT_MASK))
449 #define ISR_INT_MASK_SLOW (QLCNIC_PCIX_PS_REG(PCIX_INT_MASK))
450 #define ISR_INT_TARGET_STATUS (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS))
451 #define ISR_INT_TARGET_MASK (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK))
452 #define ISR_INT_TARGET_STATUS_F1 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F1))
453 #define ISR_INT_TARGET_MASK_F1 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F1))
454 #define ISR_INT_TARGET_STATUS_F2 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F2))
455 #define ISR_INT_TARGET_MASK_F2 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F2))
456 #define ISR_INT_TARGET_STATUS_F3 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F3))
457 #define ISR_INT_TARGET_MASK_F3 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F3))
458 #define ISR_INT_TARGET_STATUS_F4 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F4))
459 #define ISR_INT_TARGET_MASK_F4 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F4))
460 #define ISR_INT_TARGET_STATUS_F5 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F5))
461 #define ISR_INT_TARGET_MASK_F5 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F5))
462 #define ISR_INT_TARGET_STATUS_F6 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F6))
463 #define ISR_INT_TARGET_MASK_F6 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F6))
464 #define ISR_INT_TARGET_STATUS_F7 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F7))
465 #define ISR_INT_TARGET_MASK_F7 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F7))
467 #define QLCNIC_PCI_MN_2M (0)
468 #define QLCNIC_PCI_MS_2M (0x80000)
469 #define QLCNIC_PCI_OCM0_2M (0x000c0000UL)
470 #define QLCNIC_PCI_CRBSPACE (0x06000000UL)
471 #define QLCNIC_PCI_CAMQM (0x04800000UL)
472 #define QLCNIC_PCI_CAMQM_END (0x04800800UL)
473 #define QLCNIC_PCI_2MB_SIZE (0x00200000UL)
474 #define QLCNIC_PCI_CAMQM_2M_BASE (0x000ff800UL)
476 #define QLCNIC_CRB_CAM QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_CAM)
478 #define QLCNIC_ADDR_DDR_NET (0x0000000000000000ULL)
479 #define QLCNIC_ADDR_DDR_NET_MAX (0x000000000fffffffULL)
480 #define QLCNIC_ADDR_OCM0 (0x0000000200000000ULL)
481 #define QLCNIC_ADDR_OCM0_MAX (0x00000002000fffffULL)
482 #define QLCNIC_ADDR_OCM1 (0x0000000200400000ULL)
483 #define QLCNIC_ADDR_OCM1_MAX (0x00000002004fffffULL)
484 #define QLCNIC_ADDR_QDR_NET (0x0000000300000000ULL)
485 #define QLCNIC_ADDR_QDR_NET_MAX (0x0000000307ffffffULL)
488 * Register offsets for MN
490 #define QLCNIC_MIU_CONTROL (0x000)
491 #define QLCNIC_MIU_MN_CONTROL (QLCNIC_CRB_DDR_NET+QLCNIC_MIU_CONTROL)
493 /* 200ms delay in each loop */
494 #define QLCNIC_NIU_PHY_WAITLEN 200000
495 /* 10 seconds before we give up */
496 #define QLCNIC_NIU_PHY_WAITMAX 50
497 #define QLCNIC_NIU_MAX_GBE_PORTS 4
498 #define QLCNIC_NIU_MAX_XG_PORTS 2
500 #define QLCNIC_NIU_MODE (QLCNIC_CRB_NIU + 0x00000)
501 #define QLCNIC_NIU_GB_PAUSE_CTL (QLCNIC_CRB_NIU + 0x0030c)
502 #define QLCNIC_NIU_XG_PAUSE_CTL (QLCNIC_CRB_NIU + 0x00098)
504 #define QLCNIC_NIU_GB_MAC_CONFIG_0(I) \
505 (QLCNIC_CRB_NIU + 0x30000 + (I)*0x10000)
506 #define QLCNIC_NIU_GB_MAC_CONFIG_1(I) \
507 (QLCNIC_CRB_NIU + 0x30004 + (I)*0x10000)
510 #define TEST_AGT_CTRL (0x00)
512 #define TA_CTL_START 1
513 #define TA_CTL_ENABLE 2
514 #define TA_CTL_WRITE 4
515 #define TA_CTL_BUSY 8
518 * Register offsets for MN
520 #define MIU_TEST_AGT_BASE (0x90)
522 #define MIU_TEST_AGT_ADDR_LO (0x04)
523 #define MIU_TEST_AGT_ADDR_HI (0x08)
524 #define MIU_TEST_AGT_WRDATA_LO (0x10)
525 #define MIU_TEST_AGT_WRDATA_HI (0x14)
526 #define MIU_TEST_AGT_WRDATA_UPPER_LO (0x20)
527 #define MIU_TEST_AGT_WRDATA_UPPER_HI (0x24)
528 #define MIU_TEST_AGT_WRDATA(i) (0x10+(0x10*((i)>>1))+(4*((i)&1)))
529 #define MIU_TEST_AGT_RDDATA_LO (0x18)
530 #define MIU_TEST_AGT_RDDATA_HI (0x1c)
531 #define MIU_TEST_AGT_RDDATA_UPPER_LO (0x28)
532 #define MIU_TEST_AGT_RDDATA_UPPER_HI (0x2c)
533 #define MIU_TEST_AGT_RDDATA(i) (0x18+(0x10*((i)>>1))+(4*((i)&1)))
535 #define MIU_TEST_AGT_ADDR_MASK 0xfffffff8
536 #define MIU_TEST_AGT_UPPER_ADDR(off) (0)
539 * Register offsets for MS
541 #define SIU_TEST_AGT_BASE (0x60)
543 #define SIU_TEST_AGT_ADDR_LO (0x04)
544 #define SIU_TEST_AGT_ADDR_HI (0x18)
545 #define SIU_TEST_AGT_WRDATA_LO (0x08)
546 #define SIU_TEST_AGT_WRDATA_HI (0x0c)
547 #define SIU_TEST_AGT_WRDATA(i) (0x08+(4*(i)))
548 #define SIU_TEST_AGT_RDDATA_LO (0x10)
549 #define SIU_TEST_AGT_RDDATA_HI (0x14)
550 #define SIU_TEST_AGT_RDDATA(i) (0x10+(4*(i)))
552 #define SIU_TEST_AGT_ADDR_MASK 0x3ffff8
553 #define SIU_TEST_AGT_UPPER_ADDR(off) ((off)>>22)
556 #define XG_LINK_UP 0x10
557 #define XG_LINK_DOWN 0x20
559 #define XG_LINK_UP_P3 0x01
560 #define XG_LINK_DOWN_P3 0x02
561 #define XG_LINK_STATE_P3_MASK 0xf
562 #define XG_LINK_STATE_P3(pcifn, val) \
563 (((val) >> ((pcifn) * 4)) & XG_LINK_STATE_P3_MASK)
565 #define P3_LINK_SPEED_MHZ 100
566 #define P3_LINK_SPEED_MASK 0xff
567 #define P3_LINK_SPEED_REG(pcifn) \
568 (CRB_PF_LINK_SPEED_1 + (((pcifn) / 4) * 4))
569 #define P3_LINK_SPEED_VAL(pcifn, reg) \
570 (((reg) >> (8 * ((pcifn) & 0x3))) & P3_LINK_SPEED_MASK)
572 #define QLCNIC_CAM_RAM_BASE (QLCNIC_CRB_CAM + 0x02000)
573 #define QLCNIC_CAM_RAM(reg) (QLCNIC_CAM_RAM_BASE + (reg))
574 #define QLCNIC_FW_VERSION_MAJOR (QLCNIC_CAM_RAM(0x150))
575 #define QLCNIC_FW_VERSION_MINOR (QLCNIC_CAM_RAM(0x154))
576 #define QLCNIC_FW_VERSION_SUB (QLCNIC_CAM_RAM(0x158))
577 #define QLCNIC_ROM_LOCK_ID (QLCNIC_CAM_RAM(0x100))
578 #define QLCNIC_PHY_LOCK_ID (QLCNIC_CAM_RAM(0x120))
579 #define QLCNIC_CRB_WIN_LOCK_ID (QLCNIC_CAM_RAM(0x124))
581 #define NIC_CRB_BASE (QLCNIC_CAM_RAM(0x200))
582 #define NIC_CRB_BASE_2 (QLCNIC_CAM_RAM(0x700))
583 #define QLCNIC_REG(X) (NIC_CRB_BASE+(X))
584 #define QLCNIC_REG_2(X) (NIC_CRB_BASE_2+(X))
586 #define QLCNIC_CDRP_CRB_OFFSET (QLCNIC_REG(0x18))
587 #define QLCNIC_ARG1_CRB_OFFSET (QLCNIC_REG(0x1c))
588 #define QLCNIC_ARG2_CRB_OFFSET (QLCNIC_REG(0x20))
589 #define QLCNIC_ARG3_CRB_OFFSET (QLCNIC_REG(0x24))
590 #define QLCNIC_SIGN_CRB_OFFSET (QLCNIC_REG(0x28))
592 #define CRB_CMDPEG_STATE (QLCNIC_REG(0x50))
593 #define CRB_RCVPEG_STATE (QLCNIC_REG(0x13c))
595 #define CRB_XG_STATE_P3 (QLCNIC_REG(0x98))
596 #define CRB_PF_LINK_SPEED_1 (QLCNIC_REG(0xe8))
597 #define CRB_PF_LINK_SPEED_2 (QLCNIC_REG(0xec))
599 #define CRB_TEMP_STATE (QLCNIC_REG(0x1b4))
601 #define CRB_V2P_0 (QLCNIC_REG(0x290))
602 #define CRB_V2P(port) (CRB_V2P_0+((port)*4))
603 #define CRB_DRIVER_VERSION (QLCNIC_REG(0x2a0))
605 #define CRB_FW_CAPABILITIES_1 (QLCNIC_CAM_RAM(0x128))
606 #define CRB_MAC_BLOCK_START (QLCNIC_CAM_RAM(0x1c0))
609 * CrbPortPhanCntrHi/Lo is used to pass the address of HostPhantomIndex address
610 * which can be read by the Phantom host to get producer/consumer indexes from
611 * Phantom/Casper. If it is not HOST_SHARED_MEMORY, then the following
612 * registers will be used for the addresses of the ring's shared memory
616 #define qlcnic_get_temp_val(x) ((x) >> 16)
617 #define qlcnic_get_temp_state(x) ((x) & 0xffff)
618 #define qlcnic_encode_temp(val, state) (((val) << 16) | (state))
621 * Temperature control.
624 QLCNIC_TEMP_NORMAL
= 0x1, /* Normal operating range */
625 QLCNIC_TEMP_WARN
, /* Sound alert, temperature getting high */
626 QLCNIC_TEMP_PANIC
/* Fatal error, hardware has shut down. */
629 /* Lock IDs for PHY lock */
630 #define PHY_LOCK_DRIVER 0x44524956
632 /* Used for PS PCI Memory access */
633 #define PCIX_PS_OP_ADDR_LO (0x10000)
634 /* via CRB (PS side only) */
635 #define PCIX_PS_OP_ADDR_HI (0x10004)
637 #define PCIX_INT_VECTOR (0x10100)
638 #define PCIX_INT_MASK (0x10104)
640 #define PCIX_OCM_WINDOW (0x10800)
641 #define PCIX_OCM_WINDOW_REG(func) (PCIX_OCM_WINDOW + 0x20 * (func))
643 #define PCIX_TARGET_STATUS (0x10118)
644 #define PCIX_TARGET_STATUS_F1 (0x10160)
645 #define PCIX_TARGET_STATUS_F2 (0x10164)
646 #define PCIX_TARGET_STATUS_F3 (0x10168)
647 #define PCIX_TARGET_STATUS_F4 (0x10360)
648 #define PCIX_TARGET_STATUS_F5 (0x10364)
649 #define PCIX_TARGET_STATUS_F6 (0x10368)
650 #define PCIX_TARGET_STATUS_F7 (0x1036c)
652 #define PCIX_TARGET_MASK (0x10128)
653 #define PCIX_TARGET_MASK_F1 (0x10170)
654 #define PCIX_TARGET_MASK_F2 (0x10174)
655 #define PCIX_TARGET_MASK_F3 (0x10178)
656 #define PCIX_TARGET_MASK_F4 (0x10370)
657 #define PCIX_TARGET_MASK_F5 (0x10374)
658 #define PCIX_TARGET_MASK_F6 (0x10378)
659 #define PCIX_TARGET_MASK_F7 (0x1037c)
661 #define PCIX_MSI_F(i) (0x13000+((i)*4))
663 #define QLCNIC_PCIX_PH_REG(reg) (QLCNIC_CRB_PCIE + (reg))
664 #define QLCNIC_PCIX_PS_REG(reg) (QLCNIC_CRB_PCIX_MD + (reg))
665 #define QLCNIC_PCIE_REG(reg) (QLCNIC_CRB_PCIE + (reg))
667 #define PCIE_SEM0_LOCK (0x1c000)
668 #define PCIE_SEM0_UNLOCK (0x1c004)
669 #define PCIE_SEM_LOCK(N) (PCIE_SEM0_LOCK + 8*(N))
670 #define PCIE_SEM_UNLOCK(N) (PCIE_SEM0_UNLOCK + 8*(N))
672 #define PCIE_SETUP_FUNCTION (0x12040)
673 #define PCIE_SETUP_FUNCTION2 (0x12048)
674 #define PCIE_MISCCFG_RC (0x1206c)
675 #define PCIE_TGT_SPLIT_CHICKEN (0x12080)
676 #define PCIE_CHICKEN3 (0x120c8)
678 #define ISR_INT_STATE_REG (QLCNIC_PCIX_PS_REG(PCIE_MISCCFG_RC))
679 #define PCIE_MAX_MASTER_SPLIT (0x14048)
681 #define QLCNIC_PORT_MODE_NONE 0
682 #define QLCNIC_PORT_MODE_XG 1
683 #define QLCNIC_PORT_MODE_GB 2
684 #define QLCNIC_PORT_MODE_802_3_AP 3
685 #define QLCNIC_PORT_MODE_AUTO_NEG 4
686 #define QLCNIC_PORT_MODE_AUTO_NEG_1G 5
687 #define QLCNIC_PORT_MODE_AUTO_NEG_XG 6
688 #define QLCNIC_PORT_MODE_ADDR (QLCNIC_CAM_RAM(0x24))
689 #define QLCNIC_WOL_PORT_MODE (QLCNIC_CAM_RAM(0x198))
691 #define QLCNIC_WOL_CONFIG_NV (QLCNIC_CAM_RAM(0x184))
692 #define QLCNIC_WOL_CONFIG (QLCNIC_CAM_RAM(0x188))
694 #define QLCNIC_PEG_TUNE_MN_PRESENT 0x1
695 #define QLCNIC_PEG_TUNE_CAPABILITY (QLCNIC_CAM_RAM(0x02c))
697 #define QLCNIC_DMA_WATCHDOG_CTRL (QLCNIC_CAM_RAM(0x14))
698 #define QLCNIC_PEG_ALIVE_COUNTER (QLCNIC_CAM_RAM(0xb0))
699 #define QLCNIC_PEG_HALT_STATUS1 (QLCNIC_CAM_RAM(0xa8))
700 #define QLCNIC_PEG_HALT_STATUS2 (QLCNIC_CAM_RAM(0xac))
701 #define QLCNIC_CRB_DEV_REF_COUNT (QLCNIC_CAM_RAM(0x138))
702 #define QLCNIC_CRB_DEV_STATE (QLCNIC_CAM_RAM(0x140))
704 #define QLCNIC_CRB_DRV_STATE (QLCNIC_CAM_RAM(0x144))
705 #define QLCNIC_CRB_DRV_SCRATCH (QLCNIC_CAM_RAM(0x148))
706 #define QLCNIC_CRB_DEV_PARTITION_INFO (QLCNIC_CAM_RAM(0x14c))
707 #define QLCNIC_CRB_DRV_IDC_VER (QLCNIC_CAM_RAM(0x174))
708 #define QLCNIC_CRB_DEV_NPAR_STATE (QLCNIC_CAM_RAM(0x19c))
709 #define QLCNIC_ROM_DEV_INIT_TIMEOUT (0x3e885c)
710 #define QLCNIC_ROM_DRV_RESET_TIMEOUT (0x3e8860)
713 #define QLCNIC_DEV_COLD 0x1
714 #define QLCNIC_DEV_INITIALIZING 0x2
715 #define QLCNIC_DEV_READY 0x3
716 #define QLCNIC_DEV_NEED_RESET 0x4
717 #define QLCNIC_DEV_NEED_QUISCENT 0x5
718 #define QLCNIC_DEV_FAILED 0x6
719 #define QLCNIC_DEV_QUISCENT 0x7
721 #define QLCNIC_DEV_NPAR_NOT_RDY 0
722 #define QLCNIC_DEV_NPAR_RDY 1
724 #define QLC_DEV_CHECK_ACTIVE(VAL, FN) ((VAL) &= (1 << (FN * 4)))
725 #define QLC_DEV_SET_REF_CNT(VAL, FN) ((VAL) |= (1 << (FN * 4)))
726 #define QLC_DEV_CLR_REF_CNT(VAL, FN) ((VAL) &= ~(1 << (FN * 4)))
727 #define QLC_DEV_SET_RST_RDY(VAL, FN) ((VAL) |= (1 << (FN * 4)))
728 #define QLC_DEV_SET_QSCNT_RDY(VAL, FN) ((VAL) |= (2 << (FN * 4)))
729 #define QLC_DEV_CLR_RST_QSCNT(VAL, FN) ((VAL) &= ~(3 << (FN * 4)))
731 #define QLC_DEV_GET_DRV(VAL, FN) (0xf & ((VAL) >> (FN * 4)))
732 #define QLC_DEV_SET_DRV(VAL, FN) ((VAL) << (FN * 4))
734 #define QLCNIC_TYPE_NIC 1
735 #define QLCNIC_TYPE_FCOE 2
736 #define QLCNIC_TYPE_ISCSI 3
738 #define QLCNIC_RCODE_DRIVER_INFO 0x20000000
739 #define QLCNIC_RCODE_DRIVER_CAN_RELOAD BIT_30
740 #define QLCNIC_RCODE_FATAL_ERROR BIT_31
741 #define QLCNIC_FWERROR_PEGNUM(code) ((code) & 0xff)
742 #define QLCNIC_FWERROR_CODE(code) ((code >> 8) & 0xfffff)
744 #define FW_POLL_DELAY (1 * HZ)
745 #define FW_FAIL_THRESH 2
747 #define ISR_MSI_INT_TRIGGER(FUNC) (QLCNIC_PCIX_PS_REG(PCIX_MSI_F(FUNC)))
748 #define ISR_LEGACY_INT_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200)
751 * PCI Interrupt Vector Values.
753 #define PCIX_INT_VECTOR_BIT_F0 0x0080
754 #define PCIX_INT_VECTOR_BIT_F1 0x0100
755 #define PCIX_INT_VECTOR_BIT_F2 0x0200
756 #define PCIX_INT_VECTOR_BIT_F3 0x0400
757 #define PCIX_INT_VECTOR_BIT_F4 0x0800
758 #define PCIX_INT_VECTOR_BIT_F5 0x1000
759 #define PCIX_INT_VECTOR_BIT_F6 0x2000
760 #define PCIX_INT_VECTOR_BIT_F7 0x4000
762 struct qlcnic_legacy_intr_set
{
769 #define QLCNIC_FW_API 0x1b216c
770 #define QLCNIC_DRV_OP_MODE 0x1b2170
771 #define QLCNIC_MSIX_BASE 0x132110
772 #define QLCNIC_MAX_PCI_FUNC 8
774 /* PCI function operational mode */
776 QLCNIC_MGMT_FUNC
= 0,
777 QLCNIC_PRIV_FUNC
= 1,
778 QLCNIC_NON_PRIV_FUNC
= 2
781 #define QLC_DEV_DRV_DEFAULT 0x11111111
783 #define LSB(x) ((uint8_t)(x))
784 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
786 #define LSW(x) ((uint16_t)((uint32_t)(x)))
787 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
789 #define LSD(x) ((uint32_t)((uint64_t)(x)))
790 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
792 #define QLCNIC_LEGACY_INTR_CONFIG \
795 .int_vec_bit = PCIX_INT_VECTOR_BIT_F0, \
796 .tgt_status_reg = ISR_INT_TARGET_STATUS, \
797 .tgt_mask_reg = ISR_INT_TARGET_MASK, \
798 .pci_int_reg = ISR_MSI_INT_TRIGGER(0) }, \
801 .int_vec_bit = PCIX_INT_VECTOR_BIT_F1, \
802 .tgt_status_reg = ISR_INT_TARGET_STATUS_F1, \
803 .tgt_mask_reg = ISR_INT_TARGET_MASK_F1, \
804 .pci_int_reg = ISR_MSI_INT_TRIGGER(1) }, \
807 .int_vec_bit = PCIX_INT_VECTOR_BIT_F2, \
808 .tgt_status_reg = ISR_INT_TARGET_STATUS_F2, \
809 .tgt_mask_reg = ISR_INT_TARGET_MASK_F2, \
810 .pci_int_reg = ISR_MSI_INT_TRIGGER(2) }, \
813 .int_vec_bit = PCIX_INT_VECTOR_BIT_F3, \
814 .tgt_status_reg = ISR_INT_TARGET_STATUS_F3, \
815 .tgt_mask_reg = ISR_INT_TARGET_MASK_F3, \
816 .pci_int_reg = ISR_MSI_INT_TRIGGER(3) }, \
819 .int_vec_bit = PCIX_INT_VECTOR_BIT_F4, \
820 .tgt_status_reg = ISR_INT_TARGET_STATUS_F4, \
821 .tgt_mask_reg = ISR_INT_TARGET_MASK_F4, \
822 .pci_int_reg = ISR_MSI_INT_TRIGGER(4) }, \
825 .int_vec_bit = PCIX_INT_VECTOR_BIT_F5, \
826 .tgt_status_reg = ISR_INT_TARGET_STATUS_F5, \
827 .tgt_mask_reg = ISR_INT_TARGET_MASK_F5, \
828 .pci_int_reg = ISR_MSI_INT_TRIGGER(5) }, \
831 .int_vec_bit = PCIX_INT_VECTOR_BIT_F6, \
832 .tgt_status_reg = ISR_INT_TARGET_STATUS_F6, \
833 .tgt_mask_reg = ISR_INT_TARGET_MASK_F6, \
834 .pci_int_reg = ISR_MSI_INT_TRIGGER(6) }, \
837 .int_vec_bit = PCIX_INT_VECTOR_BIT_F7, \
838 .tgt_status_reg = ISR_INT_TARGET_STATUS_F7, \
839 .tgt_mask_reg = ISR_INT_TARGET_MASK_F7, \
840 .pci_int_reg = ISR_MSI_INT_TRIGGER(7) }, \
845 #define _qlcnic_crb_get_bit(var, bit) ((var >> bit) & 0x1)
848 * NIU GB MAC Config Register 0 (applies to GB0, GB1, GB2, GB3)
850 * Bit 0 : enable_tx => 1:enable frame xmit, 0:disable
851 * Bit 1 : tx_synced => R/O: xmit enable synched to xmit stream
852 * Bit 2 : enable_rx => 1:enable frame recv, 0:disable
853 * Bit 3 : rx_synced => R/O: recv enable synched to recv stream
854 * Bit 4 : tx_flowctl => 1:enable pause frame generation, 0:disable
855 * Bit 5 : rx_flowctl => 1:act on recv'd pause frames, 0:ignore
856 * Bit 8 : loopback => 1:loop MAC xmits to MAC recvs, 0:normal
857 * Bit 16: tx_reset_pb => 1:reset frame xmit protocol blk, 0:no-op
858 * Bit 17: rx_reset_pb => 1:reset frame recv protocol blk, 0:no-op
859 * Bit 18: tx_reset_mac => 1:reset data/ctl multiplexer blk, 0:no-op
860 * Bit 19: rx_reset_mac => 1:reset ctl frames & timers blk, 0:no-op
861 * Bit 31: soft_reset => 1:reset the MAC and the SERDES, 0:no-op
863 #define qlcnic_gb_rx_flowctl(config_word) \
864 ((config_word) |= 1 << 5)
865 #define qlcnic_gb_get_rx_flowctl(config_word) \
866 _qlcnic_crb_get_bit((config_word), 5)
867 #define qlcnic_gb_unset_rx_flowctl(config_word) \
868 ((config_word) &= ~(1 << 5))
871 * NIU GB Pause Ctl Register
874 #define qlcnic_gb_set_gb0_mask(config_word) \
875 ((config_word) |= 1 << 0)
876 #define qlcnic_gb_set_gb1_mask(config_word) \
877 ((config_word) |= 1 << 2)
878 #define qlcnic_gb_set_gb2_mask(config_word) \
879 ((config_word) |= 1 << 4)
880 #define qlcnic_gb_set_gb3_mask(config_word) \
881 ((config_word) |= 1 << 6)
883 #define qlcnic_gb_get_gb0_mask(config_word) \
884 _qlcnic_crb_get_bit((config_word), 0)
885 #define qlcnic_gb_get_gb1_mask(config_word) \
886 _qlcnic_crb_get_bit((config_word), 2)
887 #define qlcnic_gb_get_gb2_mask(config_word) \
888 _qlcnic_crb_get_bit((config_word), 4)
889 #define qlcnic_gb_get_gb3_mask(config_word) \
890 _qlcnic_crb_get_bit((config_word), 6)
892 #define qlcnic_gb_unset_gb0_mask(config_word) \
893 ((config_word) &= ~(1 << 0))
894 #define qlcnic_gb_unset_gb1_mask(config_word) \
895 ((config_word) &= ~(1 << 2))
896 #define qlcnic_gb_unset_gb2_mask(config_word) \
897 ((config_word) &= ~(1 << 4))
898 #define qlcnic_gb_unset_gb3_mask(config_word) \
899 ((config_word) &= ~(1 << 6))
902 * NIU XG Pause Ctl Register
904 * Bit 0 : xg0_mask => 1:disable tx pause frames
905 * Bit 1 : xg0_request => 1:request single pause frame
906 * Bit 2 : xg0_on_off => 1:request is pause on, 0:off
907 * Bit 3 : xg1_mask => 1:disable tx pause frames
908 * Bit 4 : xg1_request => 1:request single pause frame
909 * Bit 5 : xg1_on_off => 1:request is pause on, 0:off
912 #define qlcnic_xg_set_xg0_mask(config_word) \
913 ((config_word) |= 1 << 0)
914 #define qlcnic_xg_set_xg1_mask(config_word) \
915 ((config_word) |= 1 << 3)
917 #define qlcnic_xg_get_xg0_mask(config_word) \
918 _qlcnic_crb_get_bit((config_word), 0)
919 #define qlcnic_xg_get_xg1_mask(config_word) \
920 _qlcnic_crb_get_bit((config_word), 3)
922 #define qlcnic_xg_unset_xg0_mask(config_word) \
923 ((config_word) &= ~(1 << 0))
924 #define qlcnic_xg_unset_xg1_mask(config_word) \
925 ((config_word) &= ~(1 << 3))
928 * NIU XG Pause Ctl Register
930 * Bit 0 : xg0_mask => 1:disable tx pause frames
931 * Bit 1 : xg0_request => 1:request single pause frame
932 * Bit 2 : xg0_on_off => 1:request is pause on, 0:off
933 * Bit 3 : xg1_mask => 1:disable tx pause frames
934 * Bit 4 : xg1_request => 1:request single pause frame
935 * Bit 5 : xg1_on_off => 1:request is pause on, 0:off
939 * PHY-Specific MII control/status registers.
941 #define QLCNIC_NIU_GB_MII_MGMT_ADDR_AUTONEG 4
942 #define QLCNIC_NIU_GB_MII_MGMT_ADDR_PHY_STATUS 17
945 * PHY-Specific Status Register (reg 17).
947 * Bit 0 : jabber => 1:jabber detected, 0:not
948 * Bit 1 : polarity => 1:polarity reversed, 0:normal
949 * Bit 2 : recvpause => 1:receive pause enabled, 0:disabled
950 * Bit 3 : xmitpause => 1:transmit pause enabled, 0:disabled
951 * Bit 4 : energydetect => 1:sleep, 0:active
952 * Bit 5 : downshift => 1:downshift, 0:no downshift
953 * Bit 6 : crossover => 1:MDIX (crossover), 0:MDI (no crossover)
954 * Bits 7-9 : cablelen => not valid in 10Mb/s mode
955 * 0:<50m, 1:50-80m, 2:80-110m, 3:110-140m, 4:>140m
956 * Bit 10 : link => 1:link up, 0:link down
957 * Bit 11 : resolved => 1:speed and duplex resolved, 0:not yet
958 * Bit 12 : pagercvd => 1:page received, 0:page not received
959 * Bit 13 : duplex => 1:full duplex, 0:half duplex
960 * Bits 14-15 : speed => 0:10Mb/s, 1:100Mb/s, 2:1000Mb/s, 3:rsvd
963 #define qlcnic_get_phy_speed(config_word) (((config_word) >> 14) & 0x03)
965 #define qlcnic_set_phy_speed(config_word, val) \
966 ((config_word) |= ((val & 0x03) << 14))
967 #define qlcnic_set_phy_duplex(config_word) \
968 ((config_word) |= 1 << 13)
969 #define qlcnic_clear_phy_duplex(config_word) \
970 ((config_word) &= ~(1 << 13))
972 #define qlcnic_get_phy_link(config_word) \
973 _qlcnic_crb_get_bit(config_word, 10)
974 #define qlcnic_get_phy_duplex(config_word) \
975 _qlcnic_crb_get_bit(config_word, 13)
977 #define QLCNIC_NIU_NON_PROMISC_MODE 0
978 #define QLCNIC_NIU_PROMISC_MODE 1
979 #define QLCNIC_NIU_ALLMULTI_MODE 2
981 struct crb_128M_2M_sub_block_map
{
988 struct crb_128M_2M_block_map
{
989 struct crb_128M_2M_sub_block_map sub_block
[16];
991 #endif /* __QLCNIC_HDR_H_ */