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qlge: Add basic firmware dump.
[deliverable/linux.git] / drivers / net / qlge / qlge_dbg.c
1 #include "qlge.h"
2
3
4 static int ql_get_ets_regs(struct ql_adapter *qdev, u32 * buf)
5 {
6 int status = 0;
7 int i;
8
9 for (i = 0; i < 8; i++, buf++) {
10 ql_write32(qdev, NIC_ETS, i << 29 | 0x08000000);
11 *buf = ql_read32(qdev, NIC_ETS);
12 }
13
14 for (i = 0; i < 2; i++, buf++) {
15 ql_write32(qdev, CNA_ETS, i << 29 | 0x08000000);
16 *buf = ql_read32(qdev, CNA_ETS);
17 }
18
19 return status;
20 }
21
22 static void ql_get_intr_states(struct ql_adapter *qdev, u32 * buf)
23 {
24 int i;
25
26 for (i = 0; i < qdev->rx_ring_count; i++, buf++) {
27 ql_write32(qdev, INTR_EN,
28 qdev->intr_context[i].intr_read_mask);
29 *buf = ql_read32(qdev, INTR_EN);
30 }
31 }
32
33 static int ql_get_cam_entries(struct ql_adapter *qdev, u32 * buf)
34 {
35 int i, status;
36 u32 value[3];
37
38 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
39 if (status)
40 return status;
41
42 for (i = 0; i < 16; i++) {
43 status = ql_get_mac_addr_reg(qdev,
44 MAC_ADDR_TYPE_CAM_MAC, i, value);
45 if (status) {
46 QPRINTK(qdev, DRV, ERR,
47 "Failed read of mac index register.\n");
48 goto err;
49 }
50 *buf++ = value[0]; /* lower MAC address */
51 *buf++ = value[1]; /* upper MAC address */
52 *buf++ = value[2]; /* output */
53 }
54 for (i = 0; i < 32; i++) {
55 status = ql_get_mac_addr_reg(qdev,
56 MAC_ADDR_TYPE_MULTI_MAC, i, value);
57 if (status) {
58 QPRINTK(qdev, DRV, ERR,
59 "Failed read of mac index register.\n");
60 goto err;
61 }
62 *buf++ = value[0]; /* lower Mcast address */
63 *buf++ = value[1]; /* upper Mcast address */
64 }
65 err:
66 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
67 return status;
68 }
69
70 static int ql_get_routing_entries(struct ql_adapter *qdev, u32 * buf)
71 {
72 int status;
73 u32 value, i;
74
75 status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
76 if (status)
77 return status;
78
79 for (i = 0; i < 16; i++) {
80 status = ql_get_routing_reg(qdev, i, &value);
81 if (status) {
82 QPRINTK(qdev, DRV, ERR,
83 "Failed read of routing index register.\n");
84 goto err;
85 } else {
86 *buf++ = value;
87 }
88 }
89 err:
90 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
91 return status;
92 }
93
94 /* Read the MPI Processor shadow registers */
95 static int ql_get_mpi_shadow_regs(struct ql_adapter *qdev, u32 * buf)
96 {
97 u32 i;
98 int status;
99
100 for (i = 0; i < MPI_CORE_SH_REGS_CNT; i++, buf++) {
101 status = ql_write_mpi_reg(qdev, RISC_124,
102 (SHADOW_OFFSET | i << SHADOW_REG_SHIFT));
103 if (status)
104 goto end;
105 status = ql_read_mpi_reg(qdev, RISC_127, buf);
106 if (status)
107 goto end;
108 }
109 end:
110 return status;
111 }
112
113 /* Read the MPI Processor core registers */
114 static int ql_get_mpi_regs(struct ql_adapter *qdev, u32 * buf,
115 u32 offset, u32 count)
116 {
117 int i, status = 0;
118 for (i = 0; i < count; i++, buf++) {
119 status = ql_read_mpi_reg(qdev, offset + i, buf);
120 if (status)
121 return status;
122 }
123 return status;
124 }
125
126
127 /* Read out the routing index registers */
128 static int ql_get_routing_index_registers(struct ql_adapter *qdev, u32 *buf)
129 {
130 int status;
131 u32 type, index, index_max;
132 u32 result_index;
133 u32 result_data;
134 u32 val;
135
136 status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
137 if (status)
138 return status;
139
140 for (type = 0; type < 4; type++) {
141 if (type < 2)
142 index_max = 8;
143 else
144 index_max = 16;
145 for (index = 0; index < index_max; index++) {
146 val = RT_IDX_RS
147 | (type << RT_IDX_TYPE_SHIFT)
148 | (index << RT_IDX_IDX_SHIFT);
149 ql_write32(qdev, RT_IDX, val);
150 result_index = 0;
151 while ((result_index & RT_IDX_MR) == 0)
152 result_index = ql_read32(qdev, RT_IDX);
153 result_data = ql_read32(qdev, RT_DATA);
154 *buf = type;
155 buf++;
156 *buf = index;
157 buf++;
158 *buf = result_index;
159 buf++;
160 *buf = result_data;
161 buf++;
162 }
163 }
164 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
165 return status;
166 }
167
168 /* Read out the MAC protocol registers */
169 static void ql_get_mac_protocol_registers(struct ql_adapter *qdev, u32 *buf)
170 {
171 u32 result_index, result_data;
172 u32 type;
173 u32 index;
174 u32 offset;
175 u32 val;
176 u32 initial_val = MAC_ADDR_RS;
177 u32 max_index;
178 u32 max_offset;
179
180 for (type = 0; type < MAC_ADDR_TYPE_COUNT; type++) {
181 switch (type) {
182
183 case 0: /* CAM */
184 initial_val |= MAC_ADDR_ADR;
185 max_index = MAC_ADDR_MAX_CAM_ENTRIES;
186 max_offset = MAC_ADDR_MAX_CAM_WCOUNT;
187 break;
188 case 1: /* Multicast MAC Address */
189 max_index = MAC_ADDR_MAX_CAM_WCOUNT;
190 max_offset = MAC_ADDR_MAX_CAM_WCOUNT;
191 break;
192 case 2: /* VLAN filter mask */
193 case 3: /* MC filter mask */
194 max_index = MAC_ADDR_MAX_CAM_WCOUNT;
195 max_offset = MAC_ADDR_MAX_CAM_WCOUNT;
196 break;
197 case 4: /* FC MAC addresses */
198 max_index = MAC_ADDR_MAX_FC_MAC_ENTRIES;
199 max_offset = MAC_ADDR_MAX_FC_MAC_WCOUNT;
200 break;
201 case 5: /* Mgmt MAC addresses */
202 max_index = MAC_ADDR_MAX_MGMT_MAC_ENTRIES;
203 max_offset = MAC_ADDR_MAX_MGMT_MAC_WCOUNT;
204 break;
205 case 6: /* Mgmt VLAN addresses */
206 max_index = MAC_ADDR_MAX_MGMT_VLAN_ENTRIES;
207 max_offset = MAC_ADDR_MAX_MGMT_VLAN_WCOUNT;
208 break;
209 case 7: /* Mgmt IPv4 address */
210 max_index = MAC_ADDR_MAX_MGMT_V4_ENTRIES;
211 max_offset = MAC_ADDR_MAX_MGMT_V4_WCOUNT;
212 break;
213 case 8: /* Mgmt IPv6 address */
214 max_index = MAC_ADDR_MAX_MGMT_V6_ENTRIES;
215 max_offset = MAC_ADDR_MAX_MGMT_V6_WCOUNT;
216 break;
217 case 9: /* Mgmt TCP/UDP Dest port */
218 max_index = MAC_ADDR_MAX_MGMT_TU_DP_ENTRIES;
219 max_offset = MAC_ADDR_MAX_MGMT_TU_DP_WCOUNT;
220 break;
221 default:
222 printk(KERN_ERR"Bad type!!! 0x%08x\n", type);
223 max_index = 0;
224 max_offset = 0;
225 break;
226 }
227 for (index = 0; index < max_index; index++) {
228 for (offset = 0; offset < max_offset; offset++) {
229 val = initial_val
230 | (type << MAC_ADDR_TYPE_SHIFT)
231 | (index << MAC_ADDR_IDX_SHIFT)
232 | (offset);
233 ql_write32(qdev, MAC_ADDR_IDX, val);
234 result_index = 0;
235 while ((result_index & MAC_ADDR_MR) == 0) {
236 result_index = ql_read32(qdev,
237 MAC_ADDR_IDX);
238 }
239 result_data = ql_read32(qdev, MAC_ADDR_DATA);
240 *buf = result_index;
241 buf++;
242 *buf = result_data;
243 buf++;
244 }
245 }
246 }
247 }
248
249 static void ql_get_sem_registers(struct ql_adapter *qdev, u32 *buf)
250 {
251 u32 func_num, reg, reg_val;
252 int status;
253
254 for (func_num = 0; func_num < MAX_SEMAPHORE_FUNCTIONS ; func_num++) {
255 reg = MPI_NIC_REG_BLOCK
256 | (func_num << MPI_NIC_FUNCTION_SHIFT)
257 | (SEM / 4);
258 status = ql_read_mpi_reg(qdev, reg, &reg_val);
259 *buf = reg_val;
260 /* if the read failed then dead fill the element. */
261 if (!status)
262 *buf = 0xdeadbeef;
263 buf++;
264 }
265 }
266
267 /* Create a coredump segment header */
268 static void ql_build_coredump_seg_header(
269 struct mpi_coredump_segment_header *seg_hdr,
270 u32 seg_number, u32 seg_size, u8 *desc)
271 {
272 memset(seg_hdr, 0, sizeof(struct mpi_coredump_segment_header));
273 seg_hdr->cookie = MPI_COREDUMP_COOKIE;
274 seg_hdr->segNum = seg_number;
275 seg_hdr->segSize = seg_size;
276 memcpy(seg_hdr->description, desc, (sizeof(seg_hdr->description)) - 1);
277 }
278
279 /*
280 * This function should be called when a coredump / probedump
281 * is to be extracted from the HBA. It is assumed there is a
282 * qdev structure that contains the base address of the register
283 * space for this function as well as a coredump structure that
284 * will contain the dump.
285 */
286 int ql_core_dump(struct ql_adapter *qdev, struct ql_mpi_coredump *mpi_coredump)
287 {
288 int status;
289 int i;
290
291 if (!mpi_coredump) {
292 QPRINTK(qdev, DRV, ERR,
293 "No memory available.\n");
294 return -ENOMEM;
295 }
296
297 /* Try to get the spinlock, but dont worry if
298 * it isn't available. If the firmware died it
299 * might be holding the sem.
300 */
301 ql_sem_spinlock(qdev, SEM_PROC_REG_MASK);
302
303 status = ql_pause_mpi_risc(qdev);
304 if (status) {
305 QPRINTK(qdev, DRV, ERR,
306 "Failed RISC pause. Status = 0x%.08x\n", status);
307 goto err;
308 }
309
310 /* Insert the global header */
311 memset(&(mpi_coredump->mpi_global_header), 0,
312 sizeof(struct mpi_coredump_global_header));
313 mpi_coredump->mpi_global_header.cookie = MPI_COREDUMP_COOKIE;
314 mpi_coredump->mpi_global_header.headerSize =
315 sizeof(struct mpi_coredump_global_header);
316 mpi_coredump->mpi_global_header.imageSize =
317 sizeof(struct ql_mpi_coredump);
318 memcpy(mpi_coredump->mpi_global_header.idString, "MPI Coredump",
319 sizeof(mpi_coredump->mpi_global_header.idString));
320
321 /* Get generic NIC reg dump */
322 ql_build_coredump_seg_header(&mpi_coredump->nic_regs_seg_hdr,
323 NIC1_CONTROL_SEG_NUM,
324 sizeof(struct mpi_coredump_segment_header) +
325 sizeof(mpi_coredump->nic_regs), "NIC1 Registers");
326
327 if (qdev->func & 1) {
328 /* Odd means our function is NIC 2 */
329 for (i = 0; i < NIC_REGS_DUMP_WORD_COUNT; i++)
330 mpi_coredump->nic2_regs[i] =
331 ql_read32(qdev, i * sizeof(u32));
332 } else {
333 /* Even means our function is NIC 1 */
334 for (i = 0; i < NIC_REGS_DUMP_WORD_COUNT; i++)
335 mpi_coredump->nic_regs[i] =
336 ql_read32(qdev, i * sizeof(u32));
337 }
338
339 ql_build_coredump_seg_header(&mpi_coredump->core_regs_seg_hdr,
340 CORE_SEG_NUM,
341 sizeof(mpi_coredump->core_regs_seg_hdr) +
342 sizeof(mpi_coredump->mpi_core_regs) +
343 sizeof(mpi_coredump->mpi_core_sh_regs),
344 "Core Registers");
345
346 /* Get the MPI Core Registers */
347 status = ql_get_mpi_regs(qdev, &mpi_coredump->mpi_core_regs[0],
348 MPI_CORE_REGS_ADDR, MPI_CORE_REGS_CNT);
349 if (status)
350 goto err;
351 /* Get the 16 MPI shadow registers */
352 status = ql_get_mpi_shadow_regs(qdev,
353 &mpi_coredump->mpi_core_sh_regs[0]);
354 if (status)
355 goto err;
356
357 /* Get the Test Logic Registers */
358 ql_build_coredump_seg_header(&mpi_coredump->test_logic_regs_seg_hdr,
359 TEST_LOGIC_SEG_NUM,
360 sizeof(struct mpi_coredump_segment_header)
361 + sizeof(mpi_coredump->test_logic_regs),
362 "Test Logic Regs");
363 status = ql_get_mpi_regs(qdev, &mpi_coredump->test_logic_regs[0],
364 TEST_REGS_ADDR, TEST_REGS_CNT);
365 if (status)
366 goto err;
367
368 /* Get the RMII Registers */
369 ql_build_coredump_seg_header(&mpi_coredump->rmii_regs_seg_hdr,
370 RMII_SEG_NUM,
371 sizeof(struct mpi_coredump_segment_header)
372 + sizeof(mpi_coredump->rmii_regs),
373 "RMII Registers");
374 status = ql_get_mpi_regs(qdev, &mpi_coredump->rmii_regs[0],
375 RMII_REGS_ADDR, RMII_REGS_CNT);
376 if (status)
377 goto err;
378
379 /* Get the FCMAC1 Registers */
380 ql_build_coredump_seg_header(&mpi_coredump->fcmac1_regs_seg_hdr,
381 FCMAC1_SEG_NUM,
382 sizeof(struct mpi_coredump_segment_header)
383 + sizeof(mpi_coredump->fcmac1_regs),
384 "FCMAC1 Registers");
385 status = ql_get_mpi_regs(qdev, &mpi_coredump->fcmac1_regs[0],
386 FCMAC1_REGS_ADDR, FCMAC_REGS_CNT);
387 if (status)
388 goto err;
389
390 /* Get the FCMAC2 Registers */
391
392 ql_build_coredump_seg_header(&mpi_coredump->fcmac2_regs_seg_hdr,
393 FCMAC2_SEG_NUM,
394 sizeof(struct mpi_coredump_segment_header)
395 + sizeof(mpi_coredump->fcmac2_regs),
396 "FCMAC2 Registers");
397
398 status = ql_get_mpi_regs(qdev, &mpi_coredump->fcmac2_regs[0],
399 FCMAC2_REGS_ADDR, FCMAC_REGS_CNT);
400 if (status)
401 goto err;
402
403 /* Get the FC1 MBX Registers */
404 ql_build_coredump_seg_header(&mpi_coredump->fc1_mbx_regs_seg_hdr,
405 FC1_MBOX_SEG_NUM,
406 sizeof(struct mpi_coredump_segment_header)
407 + sizeof(mpi_coredump->fc1_mbx_regs),
408 "FC1 MBox Regs");
409 status = ql_get_mpi_regs(qdev, &mpi_coredump->fc1_mbx_regs[0],
410 FC1_MBX_REGS_ADDR, FC_MBX_REGS_CNT);
411 if (status)
412 goto err;
413
414 /* Get the IDE Registers */
415 ql_build_coredump_seg_header(&mpi_coredump->ide_regs_seg_hdr,
416 IDE_SEG_NUM,
417 sizeof(struct mpi_coredump_segment_header)
418 + sizeof(mpi_coredump->ide_regs),
419 "IDE Registers");
420 status = ql_get_mpi_regs(qdev, &mpi_coredump->ide_regs[0],
421 IDE_REGS_ADDR, IDE_REGS_CNT);
422 if (status)
423 goto err;
424
425 /* Get the NIC1 MBX Registers */
426 ql_build_coredump_seg_header(&mpi_coredump->nic1_mbx_regs_seg_hdr,
427 NIC1_MBOX_SEG_NUM,
428 sizeof(struct mpi_coredump_segment_header)
429 + sizeof(mpi_coredump->nic1_mbx_regs),
430 "NIC1 MBox Regs");
431 status = ql_get_mpi_regs(qdev, &mpi_coredump->nic1_mbx_regs[0],
432 NIC1_MBX_REGS_ADDR, NIC_MBX_REGS_CNT);
433 if (status)
434 goto err;
435
436 /* Get the SMBus Registers */
437 ql_build_coredump_seg_header(&mpi_coredump->smbus_regs_seg_hdr,
438 SMBUS_SEG_NUM,
439 sizeof(struct mpi_coredump_segment_header)
440 + sizeof(mpi_coredump->smbus_regs),
441 "SMBus Registers");
442 status = ql_get_mpi_regs(qdev, &mpi_coredump->smbus_regs[0],
443 SMBUS_REGS_ADDR, SMBUS_REGS_CNT);
444 if (status)
445 goto err;
446
447 /* Get the FC2 MBX Registers */
448 ql_build_coredump_seg_header(&mpi_coredump->fc2_mbx_regs_seg_hdr,
449 FC2_MBOX_SEG_NUM,
450 sizeof(struct mpi_coredump_segment_header)
451 + sizeof(mpi_coredump->fc2_mbx_regs),
452 "FC2 MBox Regs");
453 status = ql_get_mpi_regs(qdev, &mpi_coredump->fc2_mbx_regs[0],
454 FC2_MBX_REGS_ADDR, FC_MBX_REGS_CNT);
455 if (status)
456 goto err;
457
458 /* Get the NIC2 MBX Registers */
459 ql_build_coredump_seg_header(&mpi_coredump->nic2_mbx_regs_seg_hdr,
460 NIC2_MBOX_SEG_NUM,
461 sizeof(struct mpi_coredump_segment_header)
462 + sizeof(mpi_coredump->nic2_mbx_regs),
463 "NIC2 MBox Regs");
464 status = ql_get_mpi_regs(qdev, &mpi_coredump->nic2_mbx_regs[0],
465 NIC2_MBX_REGS_ADDR, NIC_MBX_REGS_CNT);
466 if (status)
467 goto err;
468
469 /* Get the I2C Registers */
470 ql_build_coredump_seg_header(&mpi_coredump->i2c_regs_seg_hdr,
471 I2C_SEG_NUM,
472 sizeof(struct mpi_coredump_segment_header)
473 + sizeof(mpi_coredump->i2c_regs),
474 "I2C Registers");
475 status = ql_get_mpi_regs(qdev, &mpi_coredump->i2c_regs[0],
476 I2C_REGS_ADDR, I2C_REGS_CNT);
477 if (status)
478 goto err;
479
480 /* Get the MEMC Registers */
481 ql_build_coredump_seg_header(&mpi_coredump->memc_regs_seg_hdr,
482 MEMC_SEG_NUM,
483 sizeof(struct mpi_coredump_segment_header)
484 + sizeof(mpi_coredump->memc_regs),
485 "MEMC Registers");
486 status = ql_get_mpi_regs(qdev, &mpi_coredump->memc_regs[0],
487 MEMC_REGS_ADDR, MEMC_REGS_CNT);
488 if (status)
489 goto err;
490
491 /* Get the PBus Registers */
492 ql_build_coredump_seg_header(&mpi_coredump->pbus_regs_seg_hdr,
493 PBUS_SEG_NUM,
494 sizeof(struct mpi_coredump_segment_header)
495 + sizeof(mpi_coredump->pbus_regs),
496 "PBUS Registers");
497 status = ql_get_mpi_regs(qdev, &mpi_coredump->pbus_regs[0],
498 PBUS_REGS_ADDR, PBUS_REGS_CNT);
499 if (status)
500 goto err;
501
502 /* Get the MDE Registers */
503 ql_build_coredump_seg_header(&mpi_coredump->mde_regs_seg_hdr,
504 MDE_SEG_NUM,
505 sizeof(struct mpi_coredump_segment_header)
506 + sizeof(mpi_coredump->mde_regs),
507 "MDE Registers");
508 status = ql_get_mpi_regs(qdev, &mpi_coredump->mde_regs[0],
509 MDE_REGS_ADDR, MDE_REGS_CNT);
510 if (status)
511 goto err;
512
513 ql_build_coredump_seg_header(&mpi_coredump->misc_nic_seg_hdr,
514 MISC_NIC_INFO_SEG_NUM,
515 sizeof(struct mpi_coredump_segment_header)
516 + sizeof(mpi_coredump->misc_nic_info),
517 "MISC NIC INFO");
518 mpi_coredump->misc_nic_info.rx_ring_count = qdev->rx_ring_count;
519 mpi_coredump->misc_nic_info.tx_ring_count = qdev->tx_ring_count;
520 mpi_coredump->misc_nic_info.intr_count = qdev->intr_count;
521 mpi_coredump->misc_nic_info.function = qdev->func;
522
523 /* Segment 31 */
524 /* Get indexed register values. */
525 ql_build_coredump_seg_header(&mpi_coredump->intr_states_seg_hdr,
526 INTR_STATES_SEG_NUM,
527 sizeof(struct mpi_coredump_segment_header)
528 + sizeof(mpi_coredump->intr_states),
529 "INTR States");
530 ql_get_intr_states(qdev, &mpi_coredump->intr_states[0]);
531
532 ql_build_coredump_seg_header(&mpi_coredump->cam_entries_seg_hdr,
533 CAM_ENTRIES_SEG_NUM,
534 sizeof(struct mpi_coredump_segment_header)
535 + sizeof(mpi_coredump->cam_entries),
536 "CAM Entries");
537 status = ql_get_cam_entries(qdev, &mpi_coredump->cam_entries[0]);
538 if (status)
539 goto err;
540
541 ql_build_coredump_seg_header(&mpi_coredump->nic_routing_words_seg_hdr,
542 ROUTING_WORDS_SEG_NUM,
543 sizeof(struct mpi_coredump_segment_header)
544 + sizeof(mpi_coredump->nic_routing_words),
545 "Routing Words");
546 status = ql_get_routing_entries(qdev,
547 &mpi_coredump->nic_routing_words[0]);
548 if (status)
549 goto err;
550
551 /* Segment 34 (Rev C. step 23) */
552 ql_build_coredump_seg_header(&mpi_coredump->ets_seg_hdr,
553 ETS_SEG_NUM,
554 sizeof(struct mpi_coredump_segment_header)
555 + sizeof(mpi_coredump->ets),
556 "ETS Registers");
557 status = ql_get_ets_regs(qdev, &mpi_coredump->ets[0]);
558 if (status)
559 goto err;
560
561 ql_build_coredump_seg_header(&mpi_coredump->routing_reg_seg_hdr,
562 ROUTING_INDEX_SEG_NUM,
563 sizeof(struct mpi_coredump_segment_header)
564 + sizeof(mpi_coredump->routing_regs),
565 "Routing Regs");
566 status = ql_get_routing_index_registers(qdev,
567 &mpi_coredump->routing_regs[0]);
568 if (status)
569 goto err;
570
571 ql_build_coredump_seg_header(&mpi_coredump->mac_prot_reg_seg_hdr,
572 MAC_PROTOCOL_SEG_NUM,
573 sizeof(struct mpi_coredump_segment_header)
574 + sizeof(mpi_coredump->mac_prot_regs),
575 "MAC Prot Regs");
576 ql_get_mac_protocol_registers(qdev, &mpi_coredump->mac_prot_regs[0]);
577
578 /* Get the semaphore registers for all 5 functions */
579 ql_build_coredump_seg_header(&mpi_coredump->sem_regs_seg_hdr,
580 SEM_REGS_SEG_NUM,
581 sizeof(struct mpi_coredump_segment_header) +
582 sizeof(mpi_coredump->sem_regs), "Sem Registers");
583
584 ql_get_sem_registers(qdev, &mpi_coredump->sem_regs[0]);
585
586 /* Prevent the mpi restarting while we dump the memory.*/
587 ql_write_mpi_reg(qdev, MPI_TEST_FUNC_RST_STS, MPI_TEST_FUNC_RST_FRC);
588
589 /* clear the pause */
590 status = ql_unpause_mpi_risc(qdev);
591 if (status) {
592 QPRINTK(qdev, DRV, ERR,
593 "Failed RISC unpause. Status = 0x%.08x\n", status);
594 goto err;
595 }
596 err:
597 ql_sem_unlock(qdev, SEM_PROC_REG_MASK); /* does flush too */
598 return status;
599
600 }
601
602 void ql_gen_reg_dump(struct ql_adapter *qdev,
603 struct ql_reg_dump *mpi_coredump)
604 {
605 int i, status;
606
607
608 memset(&(mpi_coredump->mpi_global_header), 0,
609 sizeof(struct mpi_coredump_global_header));
610 mpi_coredump->mpi_global_header.cookie = MPI_COREDUMP_COOKIE;
611 mpi_coredump->mpi_global_header.headerSize =
612 sizeof(struct mpi_coredump_global_header);
613 mpi_coredump->mpi_global_header.imageSize =
614 sizeof(struct ql_reg_dump);
615 memcpy(mpi_coredump->mpi_global_header.idString, "MPI Coredump",
616 sizeof(mpi_coredump->mpi_global_header.idString));
617
618
619 /* segment 16 */
620 ql_build_coredump_seg_header(&mpi_coredump->misc_nic_seg_hdr,
621 MISC_NIC_INFO_SEG_NUM,
622 sizeof(struct mpi_coredump_segment_header)
623 + sizeof(mpi_coredump->misc_nic_info),
624 "MISC NIC INFO");
625 mpi_coredump->misc_nic_info.rx_ring_count = qdev->rx_ring_count;
626 mpi_coredump->misc_nic_info.tx_ring_count = qdev->tx_ring_count;
627 mpi_coredump->misc_nic_info.intr_count = qdev->intr_count;
628 mpi_coredump->misc_nic_info.function = qdev->func;
629
630 /* Segment 16, Rev C. Step 18 */
631 ql_build_coredump_seg_header(&mpi_coredump->nic_regs_seg_hdr,
632 NIC1_CONTROL_SEG_NUM,
633 sizeof(struct mpi_coredump_segment_header)
634 + sizeof(mpi_coredump->nic_regs),
635 "NIC Registers");
636 /* Get generic reg dump */
637 for (i = 0; i < 64; i++)
638 mpi_coredump->nic_regs[i] = ql_read32(qdev, i * sizeof(u32));
639
640 /* Segment 31 */
641 /* Get indexed register values. */
642 ql_build_coredump_seg_header(&mpi_coredump->intr_states_seg_hdr,
643 INTR_STATES_SEG_NUM,
644 sizeof(struct mpi_coredump_segment_header)
645 + sizeof(mpi_coredump->intr_states),
646 "INTR States");
647 ql_get_intr_states(qdev, &mpi_coredump->intr_states[0]);
648
649 ql_build_coredump_seg_header(&mpi_coredump->cam_entries_seg_hdr,
650 CAM_ENTRIES_SEG_NUM,
651 sizeof(struct mpi_coredump_segment_header)
652 + sizeof(mpi_coredump->cam_entries),
653 "CAM Entries");
654 status = ql_get_cam_entries(qdev, &mpi_coredump->cam_entries[0]);
655 if (status)
656 return;
657
658 ql_build_coredump_seg_header(&mpi_coredump->nic_routing_words_seg_hdr,
659 ROUTING_WORDS_SEG_NUM,
660 sizeof(struct mpi_coredump_segment_header)
661 + sizeof(mpi_coredump->nic_routing_words),
662 "Routing Words");
663 status = ql_get_routing_entries(qdev,
664 &mpi_coredump->nic_routing_words[0]);
665 if (status)
666 return;
667
668 /* Segment 34 (Rev C. step 23) */
669 ql_build_coredump_seg_header(&mpi_coredump->ets_seg_hdr,
670 ETS_SEG_NUM,
671 sizeof(struct mpi_coredump_segment_header)
672 + sizeof(mpi_coredump->ets),
673 "ETS Registers");
674 status = ql_get_ets_regs(qdev, &mpi_coredump->ets[0]);
675 if (status)
676 return;
677 }
678
679 /* Coredump to messages log file using separate worker thread */
680 void ql_mpi_core_to_log(struct work_struct *work)
681 {
682 struct ql_adapter *qdev =
683 container_of(work, struct ql_adapter, mpi_core_to_log.work);
684 u32 *tmp, count;
685 int i;
686
687 count = sizeof(struct ql_mpi_coredump) / sizeof(u32);
688 tmp = (u32 *)qdev->mpi_coredump;
689 QPRINTK(qdev, DRV, DEBUG, "Core is dumping to log file!\n");
690
691 for (i = 0; i < count; i += 8) {
692 printk(KERN_ERR "%.08x: %.08x %.08x %.08x %.08x %.08x "
693 "%.08x %.08x %.08x \n", i,
694 tmp[i + 0],
695 tmp[i + 1],
696 tmp[i + 2],
697 tmp[i + 3],
698 tmp[i + 4],
699 tmp[i + 5],
700 tmp[i + 6],
701 tmp[i + 7]);
702 msleep(5);
703 }
704 }
705
706 #ifdef QL_REG_DUMP
707 static void ql_dump_intr_states(struct ql_adapter *qdev)
708 {
709 int i;
710 u32 value;
711 for (i = 0; i < qdev->intr_count; i++) {
712 ql_write32(qdev, INTR_EN, qdev->intr_context[i].intr_read_mask);
713 value = ql_read32(qdev, INTR_EN);
714 printk(KERN_ERR PFX
715 "%s: Interrupt %d is %s.\n",
716 qdev->ndev->name, i,
717 (value & INTR_EN_EN ? "enabled" : "disabled"));
718 }
719 }
720
721 void ql_dump_xgmac_control_regs(struct ql_adapter *qdev)
722 {
723 u32 data;
724 if (ql_sem_spinlock(qdev, qdev->xg_sem_mask)) {
725 printk(KERN_ERR "%s: Couldn't get xgmac sem.\n", __func__);
726 return;
727 }
728 ql_read_xgmac_reg(qdev, PAUSE_SRC_LO, &data);
729 printk(KERN_ERR PFX "%s: PAUSE_SRC_LO = 0x%.08x.\n", qdev->ndev->name,
730 data);
731 ql_read_xgmac_reg(qdev, PAUSE_SRC_HI, &data);
732 printk(KERN_ERR PFX "%s: PAUSE_SRC_HI = 0x%.08x.\n", qdev->ndev->name,
733 data);
734 ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data);
735 printk(KERN_ERR PFX "%s: GLOBAL_CFG = 0x%.08x.\n", qdev->ndev->name,
736 data);
737 ql_read_xgmac_reg(qdev, TX_CFG, &data);
738 printk(KERN_ERR PFX "%s: TX_CFG = 0x%.08x.\n", qdev->ndev->name, data);
739 ql_read_xgmac_reg(qdev, RX_CFG, &data);
740 printk(KERN_ERR PFX "%s: RX_CFG = 0x%.08x.\n", qdev->ndev->name, data);
741 ql_read_xgmac_reg(qdev, FLOW_CTL, &data);
742 printk(KERN_ERR PFX "%s: FLOW_CTL = 0x%.08x.\n", qdev->ndev->name,
743 data);
744 ql_read_xgmac_reg(qdev, PAUSE_OPCODE, &data);
745 printk(KERN_ERR PFX "%s: PAUSE_OPCODE = 0x%.08x.\n", qdev->ndev->name,
746 data);
747 ql_read_xgmac_reg(qdev, PAUSE_TIMER, &data);
748 printk(KERN_ERR PFX "%s: PAUSE_TIMER = 0x%.08x.\n", qdev->ndev->name,
749 data);
750 ql_read_xgmac_reg(qdev, PAUSE_FRM_DEST_LO, &data);
751 printk(KERN_ERR PFX "%s: PAUSE_FRM_DEST_LO = 0x%.08x.\n",
752 qdev->ndev->name, data);
753 ql_read_xgmac_reg(qdev, PAUSE_FRM_DEST_HI, &data);
754 printk(KERN_ERR PFX "%s: PAUSE_FRM_DEST_HI = 0x%.08x.\n",
755 qdev->ndev->name, data);
756 ql_read_xgmac_reg(qdev, MAC_TX_PARAMS, &data);
757 printk(KERN_ERR PFX "%s: MAC_TX_PARAMS = 0x%.08x.\n", qdev->ndev->name,
758 data);
759 ql_read_xgmac_reg(qdev, MAC_RX_PARAMS, &data);
760 printk(KERN_ERR PFX "%s: MAC_RX_PARAMS = 0x%.08x.\n", qdev->ndev->name,
761 data);
762 ql_read_xgmac_reg(qdev, MAC_SYS_INT, &data);
763 printk(KERN_ERR PFX "%s: MAC_SYS_INT = 0x%.08x.\n", qdev->ndev->name,
764 data);
765 ql_read_xgmac_reg(qdev, MAC_SYS_INT_MASK, &data);
766 printk(KERN_ERR PFX "%s: MAC_SYS_INT_MASK = 0x%.08x.\n",
767 qdev->ndev->name, data);
768 ql_read_xgmac_reg(qdev, MAC_MGMT_INT, &data);
769 printk(KERN_ERR PFX "%s: MAC_MGMT_INT = 0x%.08x.\n", qdev->ndev->name,
770 data);
771 ql_read_xgmac_reg(qdev, MAC_MGMT_IN_MASK, &data);
772 printk(KERN_ERR PFX "%s: MAC_MGMT_IN_MASK = 0x%.08x.\n",
773 qdev->ndev->name, data);
774 ql_read_xgmac_reg(qdev, EXT_ARB_MODE, &data);
775 printk(KERN_ERR PFX "%s: EXT_ARB_MODE = 0x%.08x.\n", qdev->ndev->name,
776 data);
777 ql_sem_unlock(qdev, qdev->xg_sem_mask);
778
779 }
780
781 static void ql_dump_ets_regs(struct ql_adapter *qdev)
782 {
783 }
784
785 static void ql_dump_cam_entries(struct ql_adapter *qdev)
786 {
787 int i;
788 u32 value[3];
789
790 i = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
791 if (i)
792 return;
793 for (i = 0; i < 4; i++) {
794 if (ql_get_mac_addr_reg(qdev, MAC_ADDR_TYPE_CAM_MAC, i, value)) {
795 printk(KERN_ERR PFX
796 "%s: Failed read of mac index register.\n",
797 __func__);
798 return;
799 } else {
800 if (value[0])
801 printk(KERN_ERR PFX
802 "%s: CAM index %d CAM Lookup Lower = 0x%.08x:%.08x, Output = 0x%.08x.\n",
803 qdev->ndev->name, i, value[1], value[0],
804 value[2]);
805 }
806 }
807 for (i = 0; i < 32; i++) {
808 if (ql_get_mac_addr_reg
809 (qdev, MAC_ADDR_TYPE_MULTI_MAC, i, value)) {
810 printk(KERN_ERR PFX
811 "%s: Failed read of mac index register.\n",
812 __func__);
813 return;
814 } else {
815 if (value[0])
816 printk(KERN_ERR PFX
817 "%s: MCAST index %d CAM Lookup Lower = 0x%.08x:%.08x.\n",
818 qdev->ndev->name, i, value[1], value[0]);
819 }
820 }
821 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
822 }
823
824 void ql_dump_routing_entries(struct ql_adapter *qdev)
825 {
826 int i;
827 u32 value;
828 i = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
829 if (i)
830 return;
831 for (i = 0; i < 16; i++) {
832 value = 0;
833 if (ql_get_routing_reg(qdev, i, &value)) {
834 printk(KERN_ERR PFX
835 "%s: Failed read of routing index register.\n",
836 __func__);
837 return;
838 } else {
839 if (value)
840 printk(KERN_ERR PFX
841 "%s: Routing Mask %d = 0x%.08x.\n",
842 qdev->ndev->name, i, value);
843 }
844 }
845 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
846 }
847
848 void ql_dump_regs(struct ql_adapter *qdev)
849 {
850 printk(KERN_ERR PFX "reg dump for function #%d.\n", qdev->func);
851 printk(KERN_ERR PFX "SYS = 0x%x.\n",
852 ql_read32(qdev, SYS));
853 printk(KERN_ERR PFX "RST_FO = 0x%x.\n",
854 ql_read32(qdev, RST_FO));
855 printk(KERN_ERR PFX "FSC = 0x%x.\n",
856 ql_read32(qdev, FSC));
857 printk(KERN_ERR PFX "CSR = 0x%x.\n",
858 ql_read32(qdev, CSR));
859 printk(KERN_ERR PFX "ICB_RID = 0x%x.\n",
860 ql_read32(qdev, ICB_RID));
861 printk(KERN_ERR PFX "ICB_L = 0x%x.\n",
862 ql_read32(qdev, ICB_L));
863 printk(KERN_ERR PFX "ICB_H = 0x%x.\n",
864 ql_read32(qdev, ICB_H));
865 printk(KERN_ERR PFX "CFG = 0x%x.\n",
866 ql_read32(qdev, CFG));
867 printk(KERN_ERR PFX "BIOS_ADDR = 0x%x.\n",
868 ql_read32(qdev, BIOS_ADDR));
869 printk(KERN_ERR PFX "STS = 0x%x.\n",
870 ql_read32(qdev, STS));
871 printk(KERN_ERR PFX "INTR_EN = 0x%x.\n",
872 ql_read32(qdev, INTR_EN));
873 printk(KERN_ERR PFX "INTR_MASK = 0x%x.\n",
874 ql_read32(qdev, INTR_MASK));
875 printk(KERN_ERR PFX "ISR1 = 0x%x.\n",
876 ql_read32(qdev, ISR1));
877 printk(KERN_ERR PFX "ISR2 = 0x%x.\n",
878 ql_read32(qdev, ISR2));
879 printk(KERN_ERR PFX "ISR3 = 0x%x.\n",
880 ql_read32(qdev, ISR3));
881 printk(KERN_ERR PFX "ISR4 = 0x%x.\n",
882 ql_read32(qdev, ISR4));
883 printk(KERN_ERR PFX "REV_ID = 0x%x.\n",
884 ql_read32(qdev, REV_ID));
885 printk(KERN_ERR PFX "FRC_ECC_ERR = 0x%x.\n",
886 ql_read32(qdev, FRC_ECC_ERR));
887 printk(KERN_ERR PFX "ERR_STS = 0x%x.\n",
888 ql_read32(qdev, ERR_STS));
889 printk(KERN_ERR PFX "RAM_DBG_ADDR = 0x%x.\n",
890 ql_read32(qdev, RAM_DBG_ADDR));
891 printk(KERN_ERR PFX "RAM_DBG_DATA = 0x%x.\n",
892 ql_read32(qdev, RAM_DBG_DATA));
893 printk(KERN_ERR PFX "ECC_ERR_CNT = 0x%x.\n",
894 ql_read32(qdev, ECC_ERR_CNT));
895 printk(KERN_ERR PFX "SEM = 0x%x.\n",
896 ql_read32(qdev, SEM));
897 printk(KERN_ERR PFX "GPIO_1 = 0x%x.\n",
898 ql_read32(qdev, GPIO_1));
899 printk(KERN_ERR PFX "GPIO_2 = 0x%x.\n",
900 ql_read32(qdev, GPIO_2));
901 printk(KERN_ERR PFX "GPIO_3 = 0x%x.\n",
902 ql_read32(qdev, GPIO_3));
903 printk(KERN_ERR PFX "XGMAC_ADDR = 0x%x.\n",
904 ql_read32(qdev, XGMAC_ADDR));
905 printk(KERN_ERR PFX "XGMAC_DATA = 0x%x.\n",
906 ql_read32(qdev, XGMAC_DATA));
907 printk(KERN_ERR PFX "NIC_ETS = 0x%x.\n",
908 ql_read32(qdev, NIC_ETS));
909 printk(KERN_ERR PFX "CNA_ETS = 0x%x.\n",
910 ql_read32(qdev, CNA_ETS));
911 printk(KERN_ERR PFX "FLASH_ADDR = 0x%x.\n",
912 ql_read32(qdev, FLASH_ADDR));
913 printk(KERN_ERR PFX "FLASH_DATA = 0x%x.\n",
914 ql_read32(qdev, FLASH_DATA));
915 printk(KERN_ERR PFX "CQ_STOP = 0x%x.\n",
916 ql_read32(qdev, CQ_STOP));
917 printk(KERN_ERR PFX "PAGE_TBL_RID = 0x%x.\n",
918 ql_read32(qdev, PAGE_TBL_RID));
919 printk(KERN_ERR PFX "WQ_PAGE_TBL_LO = 0x%x.\n",
920 ql_read32(qdev, WQ_PAGE_TBL_LO));
921 printk(KERN_ERR PFX "WQ_PAGE_TBL_HI = 0x%x.\n",
922 ql_read32(qdev, WQ_PAGE_TBL_HI));
923 printk(KERN_ERR PFX "CQ_PAGE_TBL_LO = 0x%x.\n",
924 ql_read32(qdev, CQ_PAGE_TBL_LO));
925 printk(KERN_ERR PFX "CQ_PAGE_TBL_HI = 0x%x.\n",
926 ql_read32(qdev, CQ_PAGE_TBL_HI));
927 printk(KERN_ERR PFX "COS_DFLT_CQ1 = 0x%x.\n",
928 ql_read32(qdev, COS_DFLT_CQ1));
929 printk(KERN_ERR PFX "COS_DFLT_CQ2 = 0x%x.\n",
930 ql_read32(qdev, COS_DFLT_CQ2));
931 printk(KERN_ERR PFX "SPLT_HDR = 0x%x.\n",
932 ql_read32(qdev, SPLT_HDR));
933 printk(KERN_ERR PFX "FC_PAUSE_THRES = 0x%x.\n",
934 ql_read32(qdev, FC_PAUSE_THRES));
935 printk(KERN_ERR PFX "NIC_PAUSE_THRES = 0x%x.\n",
936 ql_read32(qdev, NIC_PAUSE_THRES));
937 printk(KERN_ERR PFX "FC_ETHERTYPE = 0x%x.\n",
938 ql_read32(qdev, FC_ETHERTYPE));
939 printk(KERN_ERR PFX "FC_RCV_CFG = 0x%x.\n",
940 ql_read32(qdev, FC_RCV_CFG));
941 printk(KERN_ERR PFX "NIC_RCV_CFG = 0x%x.\n",
942 ql_read32(qdev, NIC_RCV_CFG));
943 printk(KERN_ERR PFX "FC_COS_TAGS = 0x%x.\n",
944 ql_read32(qdev, FC_COS_TAGS));
945 printk(KERN_ERR PFX "NIC_COS_TAGS = 0x%x.\n",
946 ql_read32(qdev, NIC_COS_TAGS));
947 printk(KERN_ERR PFX "MGMT_RCV_CFG = 0x%x.\n",
948 ql_read32(qdev, MGMT_RCV_CFG));
949 printk(KERN_ERR PFX "XG_SERDES_ADDR = 0x%x.\n",
950 ql_read32(qdev, XG_SERDES_ADDR));
951 printk(KERN_ERR PFX "XG_SERDES_DATA = 0x%x.\n",
952 ql_read32(qdev, XG_SERDES_DATA));
953 printk(KERN_ERR PFX "PRB_MX_ADDR = 0x%x.\n",
954 ql_read32(qdev, PRB_MX_ADDR));
955 printk(KERN_ERR PFX "PRB_MX_DATA = 0x%x.\n",
956 ql_read32(qdev, PRB_MX_DATA));
957 ql_dump_intr_states(qdev);
958 ql_dump_xgmac_control_regs(qdev);
959 ql_dump_ets_regs(qdev);
960 ql_dump_cam_entries(qdev);
961 ql_dump_routing_entries(qdev);
962 }
963 #endif
964
965 #ifdef QL_STAT_DUMP
966 void ql_dump_stat(struct ql_adapter *qdev)
967 {
968 printk(KERN_ERR "%s: Enter.\n", __func__);
969 printk(KERN_ERR "tx_pkts = %ld\n",
970 (unsigned long)qdev->nic_stats.tx_pkts);
971 printk(KERN_ERR "tx_bytes = %ld\n",
972 (unsigned long)qdev->nic_stats.tx_bytes);
973 printk(KERN_ERR "tx_mcast_pkts = %ld.\n",
974 (unsigned long)qdev->nic_stats.tx_mcast_pkts);
975 printk(KERN_ERR "tx_bcast_pkts = %ld.\n",
976 (unsigned long)qdev->nic_stats.tx_bcast_pkts);
977 printk(KERN_ERR "tx_ucast_pkts = %ld.\n",
978 (unsigned long)qdev->nic_stats.tx_ucast_pkts);
979 printk(KERN_ERR "tx_ctl_pkts = %ld.\n",
980 (unsigned long)qdev->nic_stats.tx_ctl_pkts);
981 printk(KERN_ERR "tx_pause_pkts = %ld.\n",
982 (unsigned long)qdev->nic_stats.tx_pause_pkts);
983 printk(KERN_ERR "tx_64_pkt = %ld.\n",
984 (unsigned long)qdev->nic_stats.tx_64_pkt);
985 printk(KERN_ERR "tx_65_to_127_pkt = %ld.\n",
986 (unsigned long)qdev->nic_stats.tx_65_to_127_pkt);
987 printk(KERN_ERR "tx_128_to_255_pkt = %ld.\n",
988 (unsigned long)qdev->nic_stats.tx_128_to_255_pkt);
989 printk(KERN_ERR "tx_256_511_pkt = %ld.\n",
990 (unsigned long)qdev->nic_stats.tx_256_511_pkt);
991 printk(KERN_ERR "tx_512_to_1023_pkt = %ld.\n",
992 (unsigned long)qdev->nic_stats.tx_512_to_1023_pkt);
993 printk(KERN_ERR "tx_1024_to_1518_pkt = %ld.\n",
994 (unsigned long)qdev->nic_stats.tx_1024_to_1518_pkt);
995 printk(KERN_ERR "tx_1519_to_max_pkt = %ld.\n",
996 (unsigned long)qdev->nic_stats.tx_1519_to_max_pkt);
997 printk(KERN_ERR "tx_undersize_pkt = %ld.\n",
998 (unsigned long)qdev->nic_stats.tx_undersize_pkt);
999 printk(KERN_ERR "tx_oversize_pkt = %ld.\n",
1000 (unsigned long)qdev->nic_stats.tx_oversize_pkt);
1001 printk(KERN_ERR "rx_bytes = %ld.\n",
1002 (unsigned long)qdev->nic_stats.rx_bytes);
1003 printk(KERN_ERR "rx_bytes_ok = %ld.\n",
1004 (unsigned long)qdev->nic_stats.rx_bytes_ok);
1005 printk(KERN_ERR "rx_pkts = %ld.\n",
1006 (unsigned long)qdev->nic_stats.rx_pkts);
1007 printk(KERN_ERR "rx_pkts_ok = %ld.\n",
1008 (unsigned long)qdev->nic_stats.rx_pkts_ok);
1009 printk(KERN_ERR "rx_bcast_pkts = %ld.\n",
1010 (unsigned long)qdev->nic_stats.rx_bcast_pkts);
1011 printk(KERN_ERR "rx_mcast_pkts = %ld.\n",
1012 (unsigned long)qdev->nic_stats.rx_mcast_pkts);
1013 printk(KERN_ERR "rx_ucast_pkts = %ld.\n",
1014 (unsigned long)qdev->nic_stats.rx_ucast_pkts);
1015 printk(KERN_ERR "rx_undersize_pkts = %ld.\n",
1016 (unsigned long)qdev->nic_stats.rx_undersize_pkts);
1017 printk(KERN_ERR "rx_oversize_pkts = %ld.\n",
1018 (unsigned long)qdev->nic_stats.rx_oversize_pkts);
1019 printk(KERN_ERR "rx_jabber_pkts = %ld.\n",
1020 (unsigned long)qdev->nic_stats.rx_jabber_pkts);
1021 printk(KERN_ERR "rx_undersize_fcerr_pkts = %ld.\n",
1022 (unsigned long)qdev->nic_stats.rx_undersize_fcerr_pkts);
1023 printk(KERN_ERR "rx_drop_events = %ld.\n",
1024 (unsigned long)qdev->nic_stats.rx_drop_events);
1025 printk(KERN_ERR "rx_fcerr_pkts = %ld.\n",
1026 (unsigned long)qdev->nic_stats.rx_fcerr_pkts);
1027 printk(KERN_ERR "rx_align_err = %ld.\n",
1028 (unsigned long)qdev->nic_stats.rx_align_err);
1029 printk(KERN_ERR "rx_symbol_err = %ld.\n",
1030 (unsigned long)qdev->nic_stats.rx_symbol_err);
1031 printk(KERN_ERR "rx_mac_err = %ld.\n",
1032 (unsigned long)qdev->nic_stats.rx_mac_err);
1033 printk(KERN_ERR "rx_ctl_pkts = %ld.\n",
1034 (unsigned long)qdev->nic_stats.rx_ctl_pkts);
1035 printk(KERN_ERR "rx_pause_pkts = %ld.\n",
1036 (unsigned long)qdev->nic_stats.rx_pause_pkts);
1037 printk(KERN_ERR "rx_64_pkts = %ld.\n",
1038 (unsigned long)qdev->nic_stats.rx_64_pkts);
1039 printk(KERN_ERR "rx_65_to_127_pkts = %ld.\n",
1040 (unsigned long)qdev->nic_stats.rx_65_to_127_pkts);
1041 printk(KERN_ERR "rx_128_255_pkts = %ld.\n",
1042 (unsigned long)qdev->nic_stats.rx_128_255_pkts);
1043 printk(KERN_ERR "rx_256_511_pkts = %ld.\n",
1044 (unsigned long)qdev->nic_stats.rx_256_511_pkts);
1045 printk(KERN_ERR "rx_512_to_1023_pkts = %ld.\n",
1046 (unsigned long)qdev->nic_stats.rx_512_to_1023_pkts);
1047 printk(KERN_ERR "rx_1024_to_1518_pkts = %ld.\n",
1048 (unsigned long)qdev->nic_stats.rx_1024_to_1518_pkts);
1049 printk(KERN_ERR "rx_1519_to_max_pkts = %ld.\n",
1050 (unsigned long)qdev->nic_stats.rx_1519_to_max_pkts);
1051 printk(KERN_ERR "rx_len_err_pkts = %ld.\n",
1052 (unsigned long)qdev->nic_stats.rx_len_err_pkts);
1053 };
1054 #endif
1055
1056 #ifdef QL_DEV_DUMP
1057 void ql_dump_qdev(struct ql_adapter *qdev)
1058 {
1059 int i;
1060 printk(KERN_ERR PFX "qdev->flags = %lx.\n",
1061 qdev->flags);
1062 printk(KERN_ERR PFX "qdev->vlgrp = %p.\n",
1063 qdev->vlgrp);
1064 printk(KERN_ERR PFX "qdev->pdev = %p.\n",
1065 qdev->pdev);
1066 printk(KERN_ERR PFX "qdev->ndev = %p.\n",
1067 qdev->ndev);
1068 printk(KERN_ERR PFX "qdev->chip_rev_id = %d.\n",
1069 qdev->chip_rev_id);
1070 printk(KERN_ERR PFX "qdev->reg_base = %p.\n",
1071 qdev->reg_base);
1072 printk(KERN_ERR PFX "qdev->doorbell_area = %p.\n",
1073 qdev->doorbell_area);
1074 printk(KERN_ERR PFX "qdev->doorbell_area_size = %d.\n",
1075 qdev->doorbell_area_size);
1076 printk(KERN_ERR PFX "msg_enable = %x.\n",
1077 qdev->msg_enable);
1078 printk(KERN_ERR PFX "qdev->rx_ring_shadow_reg_area = %p.\n",
1079 qdev->rx_ring_shadow_reg_area);
1080 printk(KERN_ERR PFX "qdev->rx_ring_shadow_reg_dma = %llx.\n",
1081 (unsigned long long) qdev->rx_ring_shadow_reg_dma);
1082 printk(KERN_ERR PFX "qdev->tx_ring_shadow_reg_area = %p.\n",
1083 qdev->tx_ring_shadow_reg_area);
1084 printk(KERN_ERR PFX "qdev->tx_ring_shadow_reg_dma = %llx.\n",
1085 (unsigned long long) qdev->tx_ring_shadow_reg_dma);
1086 printk(KERN_ERR PFX "qdev->intr_count = %d.\n",
1087 qdev->intr_count);
1088 if (qdev->msi_x_entry)
1089 for (i = 0; i < qdev->intr_count; i++) {
1090 printk(KERN_ERR PFX
1091 "msi_x_entry.[%d]vector = %d.\n", i,
1092 qdev->msi_x_entry[i].vector);
1093 printk(KERN_ERR PFX
1094 "msi_x_entry.[%d]entry = %d.\n", i,
1095 qdev->msi_x_entry[i].entry);
1096 }
1097 for (i = 0; i < qdev->intr_count; i++) {
1098 printk(KERN_ERR PFX
1099 "intr_context[%d].qdev = %p.\n", i,
1100 qdev->intr_context[i].qdev);
1101 printk(KERN_ERR PFX
1102 "intr_context[%d].intr = %d.\n", i,
1103 qdev->intr_context[i].intr);
1104 printk(KERN_ERR PFX
1105 "intr_context[%d].hooked = %d.\n", i,
1106 qdev->intr_context[i].hooked);
1107 printk(KERN_ERR PFX
1108 "intr_context[%d].intr_en_mask = 0x%08x.\n", i,
1109 qdev->intr_context[i].intr_en_mask);
1110 printk(KERN_ERR PFX
1111 "intr_context[%d].intr_dis_mask = 0x%08x.\n", i,
1112 qdev->intr_context[i].intr_dis_mask);
1113 printk(KERN_ERR PFX
1114 "intr_context[%d].intr_read_mask = 0x%08x.\n", i,
1115 qdev->intr_context[i].intr_read_mask);
1116 }
1117 printk(KERN_ERR PFX "qdev->tx_ring_count = %d.\n", qdev->tx_ring_count);
1118 printk(KERN_ERR PFX "qdev->rx_ring_count = %d.\n", qdev->rx_ring_count);
1119 printk(KERN_ERR PFX "qdev->ring_mem_size = %d.\n", qdev->ring_mem_size);
1120 printk(KERN_ERR PFX "qdev->ring_mem = %p.\n", qdev->ring_mem);
1121 printk(KERN_ERR PFX "qdev->intr_count = %d.\n", qdev->intr_count);
1122 printk(KERN_ERR PFX "qdev->tx_ring = %p.\n",
1123 qdev->tx_ring);
1124 printk(KERN_ERR PFX "qdev->rss_ring_count = %d.\n",
1125 qdev->rss_ring_count);
1126 printk(KERN_ERR PFX "qdev->rx_ring = %p.\n", qdev->rx_ring);
1127 printk(KERN_ERR PFX "qdev->default_rx_queue = %d.\n",
1128 qdev->default_rx_queue);
1129 printk(KERN_ERR PFX "qdev->xg_sem_mask = 0x%08x.\n",
1130 qdev->xg_sem_mask);
1131 printk(KERN_ERR PFX "qdev->port_link_up = 0x%08x.\n",
1132 qdev->port_link_up);
1133 printk(KERN_ERR PFX "qdev->port_init = 0x%08x.\n",
1134 qdev->port_init);
1135
1136 }
1137 #endif
1138
1139 #ifdef QL_CB_DUMP
1140 void ql_dump_wqicb(struct wqicb *wqicb)
1141 {
1142 printk(KERN_ERR PFX "Dumping wqicb stuff...\n");
1143 printk(KERN_ERR PFX "wqicb->len = 0x%x.\n", le16_to_cpu(wqicb->len));
1144 printk(KERN_ERR PFX "wqicb->flags = %x.\n", le16_to_cpu(wqicb->flags));
1145 printk(KERN_ERR PFX "wqicb->cq_id_rss = %d.\n",
1146 le16_to_cpu(wqicb->cq_id_rss));
1147 printk(KERN_ERR PFX "wqicb->rid = 0x%x.\n", le16_to_cpu(wqicb->rid));
1148 printk(KERN_ERR PFX "wqicb->wq_addr = 0x%llx.\n",
1149 (unsigned long long) le64_to_cpu(wqicb->addr));
1150 printk(KERN_ERR PFX "wqicb->wq_cnsmr_idx_addr = 0x%llx.\n",
1151 (unsigned long long) le64_to_cpu(wqicb->cnsmr_idx_addr));
1152 }
1153
1154 void ql_dump_tx_ring(struct tx_ring *tx_ring)
1155 {
1156 if (tx_ring == NULL)
1157 return;
1158 printk(KERN_ERR PFX
1159 "===================== Dumping tx_ring %d ===============.\n",
1160 tx_ring->wq_id);
1161 printk(KERN_ERR PFX "tx_ring->base = %p.\n", tx_ring->wq_base);
1162 printk(KERN_ERR PFX "tx_ring->base_dma = 0x%llx.\n",
1163 (unsigned long long) tx_ring->wq_base_dma);
1164 printk(KERN_ERR PFX
1165 "tx_ring->cnsmr_idx_sh_reg, addr = 0x%p, value = %d.\n",
1166 tx_ring->cnsmr_idx_sh_reg,
1167 tx_ring->cnsmr_idx_sh_reg
1168 ? ql_read_sh_reg(tx_ring->cnsmr_idx_sh_reg) : 0);
1169 printk(KERN_ERR PFX "tx_ring->size = %d.\n", tx_ring->wq_size);
1170 printk(KERN_ERR PFX "tx_ring->len = %d.\n", tx_ring->wq_len);
1171 printk(KERN_ERR PFX "tx_ring->prod_idx_db_reg = %p.\n",
1172 tx_ring->prod_idx_db_reg);
1173 printk(KERN_ERR PFX "tx_ring->valid_db_reg = %p.\n",
1174 tx_ring->valid_db_reg);
1175 printk(KERN_ERR PFX "tx_ring->prod_idx = %d.\n", tx_ring->prod_idx);
1176 printk(KERN_ERR PFX "tx_ring->cq_id = %d.\n", tx_ring->cq_id);
1177 printk(KERN_ERR PFX "tx_ring->wq_id = %d.\n", tx_ring->wq_id);
1178 printk(KERN_ERR PFX "tx_ring->q = %p.\n", tx_ring->q);
1179 printk(KERN_ERR PFX "tx_ring->tx_count = %d.\n",
1180 atomic_read(&tx_ring->tx_count));
1181 }
1182
1183 void ql_dump_ricb(struct ricb *ricb)
1184 {
1185 int i;
1186 printk(KERN_ERR PFX
1187 "===================== Dumping ricb ===============.\n");
1188 printk(KERN_ERR PFX "Dumping ricb stuff...\n");
1189
1190 printk(KERN_ERR PFX "ricb->base_cq = %d.\n", ricb->base_cq & 0x1f);
1191 printk(KERN_ERR PFX "ricb->flags = %s%s%s%s%s%s%s%s%s.\n",
1192 ricb->base_cq & RSS_L4K ? "RSS_L4K " : "",
1193 ricb->flags & RSS_L6K ? "RSS_L6K " : "",
1194 ricb->flags & RSS_LI ? "RSS_LI " : "",
1195 ricb->flags & RSS_LB ? "RSS_LB " : "",
1196 ricb->flags & RSS_LM ? "RSS_LM " : "",
1197 ricb->flags & RSS_RI4 ? "RSS_RI4 " : "",
1198 ricb->flags & RSS_RT4 ? "RSS_RT4 " : "",
1199 ricb->flags & RSS_RI6 ? "RSS_RI6 " : "",
1200 ricb->flags & RSS_RT6 ? "RSS_RT6 " : "");
1201 printk(KERN_ERR PFX "ricb->mask = 0x%.04x.\n", le16_to_cpu(ricb->mask));
1202 for (i = 0; i < 16; i++)
1203 printk(KERN_ERR PFX "ricb->hash_cq_id[%d] = 0x%.08x.\n", i,
1204 le32_to_cpu(ricb->hash_cq_id[i]));
1205 for (i = 0; i < 10; i++)
1206 printk(KERN_ERR PFX "ricb->ipv6_hash_key[%d] = 0x%.08x.\n", i,
1207 le32_to_cpu(ricb->ipv6_hash_key[i]));
1208 for (i = 0; i < 4; i++)
1209 printk(KERN_ERR PFX "ricb->ipv4_hash_key[%d] = 0x%.08x.\n", i,
1210 le32_to_cpu(ricb->ipv4_hash_key[i]));
1211 }
1212
1213 void ql_dump_cqicb(struct cqicb *cqicb)
1214 {
1215 printk(KERN_ERR PFX "Dumping cqicb stuff...\n");
1216
1217 printk(KERN_ERR PFX "cqicb->msix_vect = %d.\n", cqicb->msix_vect);
1218 printk(KERN_ERR PFX "cqicb->flags = %x.\n", cqicb->flags);
1219 printk(KERN_ERR PFX "cqicb->len = %d.\n", le16_to_cpu(cqicb->len));
1220 printk(KERN_ERR PFX "cqicb->addr = 0x%llx.\n",
1221 (unsigned long long) le64_to_cpu(cqicb->addr));
1222 printk(KERN_ERR PFX "cqicb->prod_idx_addr = 0x%llx.\n",
1223 (unsigned long long) le64_to_cpu(cqicb->prod_idx_addr));
1224 printk(KERN_ERR PFX "cqicb->pkt_delay = 0x%.04x.\n",
1225 le16_to_cpu(cqicb->pkt_delay));
1226 printk(KERN_ERR PFX "cqicb->irq_delay = 0x%.04x.\n",
1227 le16_to_cpu(cqicb->irq_delay));
1228 printk(KERN_ERR PFX "cqicb->lbq_addr = 0x%llx.\n",
1229 (unsigned long long) le64_to_cpu(cqicb->lbq_addr));
1230 printk(KERN_ERR PFX "cqicb->lbq_buf_size = 0x%.04x.\n",
1231 le16_to_cpu(cqicb->lbq_buf_size));
1232 printk(KERN_ERR PFX "cqicb->lbq_len = 0x%.04x.\n",
1233 le16_to_cpu(cqicb->lbq_len));
1234 printk(KERN_ERR PFX "cqicb->sbq_addr = 0x%llx.\n",
1235 (unsigned long long) le64_to_cpu(cqicb->sbq_addr));
1236 printk(KERN_ERR PFX "cqicb->sbq_buf_size = 0x%.04x.\n",
1237 le16_to_cpu(cqicb->sbq_buf_size));
1238 printk(KERN_ERR PFX "cqicb->sbq_len = 0x%.04x.\n",
1239 le16_to_cpu(cqicb->sbq_len));
1240 }
1241
1242 void ql_dump_rx_ring(struct rx_ring *rx_ring)
1243 {
1244 if (rx_ring == NULL)
1245 return;
1246 printk(KERN_ERR PFX
1247 "===================== Dumping rx_ring %d ===============.\n",
1248 rx_ring->cq_id);
1249 printk(KERN_ERR PFX "Dumping rx_ring %d, type = %s%s%s.\n",
1250 rx_ring->cq_id, rx_ring->type == DEFAULT_Q ? "DEFAULT" : "",
1251 rx_ring->type == TX_Q ? "OUTBOUND COMPLETIONS" : "",
1252 rx_ring->type == RX_Q ? "INBOUND_COMPLETIONS" : "");
1253 printk(KERN_ERR PFX "rx_ring->cqicb = %p.\n", &rx_ring->cqicb);
1254 printk(KERN_ERR PFX "rx_ring->cq_base = %p.\n", rx_ring->cq_base);
1255 printk(KERN_ERR PFX "rx_ring->cq_base_dma = %llx.\n",
1256 (unsigned long long) rx_ring->cq_base_dma);
1257 printk(KERN_ERR PFX "rx_ring->cq_size = %d.\n", rx_ring->cq_size);
1258 printk(KERN_ERR PFX "rx_ring->cq_len = %d.\n", rx_ring->cq_len);
1259 printk(KERN_ERR PFX
1260 "rx_ring->prod_idx_sh_reg, addr = 0x%p, value = %d.\n",
1261 rx_ring->prod_idx_sh_reg,
1262 rx_ring->prod_idx_sh_reg
1263 ? ql_read_sh_reg(rx_ring->prod_idx_sh_reg) : 0);
1264 printk(KERN_ERR PFX "rx_ring->prod_idx_sh_reg_dma = %llx.\n",
1265 (unsigned long long) rx_ring->prod_idx_sh_reg_dma);
1266 printk(KERN_ERR PFX "rx_ring->cnsmr_idx_db_reg = %p.\n",
1267 rx_ring->cnsmr_idx_db_reg);
1268 printk(KERN_ERR PFX "rx_ring->cnsmr_idx = %d.\n", rx_ring->cnsmr_idx);
1269 printk(KERN_ERR PFX "rx_ring->curr_entry = %p.\n", rx_ring->curr_entry);
1270 printk(KERN_ERR PFX "rx_ring->valid_db_reg = %p.\n",
1271 rx_ring->valid_db_reg);
1272
1273 printk(KERN_ERR PFX "rx_ring->lbq_base = %p.\n", rx_ring->lbq_base);
1274 printk(KERN_ERR PFX "rx_ring->lbq_base_dma = %llx.\n",
1275 (unsigned long long) rx_ring->lbq_base_dma);
1276 printk(KERN_ERR PFX "rx_ring->lbq_base_indirect = %p.\n",
1277 rx_ring->lbq_base_indirect);
1278 printk(KERN_ERR PFX "rx_ring->lbq_base_indirect_dma = %llx.\n",
1279 (unsigned long long) rx_ring->lbq_base_indirect_dma);
1280 printk(KERN_ERR PFX "rx_ring->lbq = %p.\n", rx_ring->lbq);
1281 printk(KERN_ERR PFX "rx_ring->lbq_len = %d.\n", rx_ring->lbq_len);
1282 printk(KERN_ERR PFX "rx_ring->lbq_size = %d.\n", rx_ring->lbq_size);
1283 printk(KERN_ERR PFX "rx_ring->lbq_prod_idx_db_reg = %p.\n",
1284 rx_ring->lbq_prod_idx_db_reg);
1285 printk(KERN_ERR PFX "rx_ring->lbq_prod_idx = %d.\n",
1286 rx_ring->lbq_prod_idx);
1287 printk(KERN_ERR PFX "rx_ring->lbq_curr_idx = %d.\n",
1288 rx_ring->lbq_curr_idx);
1289 printk(KERN_ERR PFX "rx_ring->lbq_clean_idx = %d.\n",
1290 rx_ring->lbq_clean_idx);
1291 printk(KERN_ERR PFX "rx_ring->lbq_free_cnt = %d.\n",
1292 rx_ring->lbq_free_cnt);
1293 printk(KERN_ERR PFX "rx_ring->lbq_buf_size = %d.\n",
1294 rx_ring->lbq_buf_size);
1295
1296 printk(KERN_ERR PFX "rx_ring->sbq_base = %p.\n", rx_ring->sbq_base);
1297 printk(KERN_ERR PFX "rx_ring->sbq_base_dma = %llx.\n",
1298 (unsigned long long) rx_ring->sbq_base_dma);
1299 printk(KERN_ERR PFX "rx_ring->sbq_base_indirect = %p.\n",
1300 rx_ring->sbq_base_indirect);
1301 printk(KERN_ERR PFX "rx_ring->sbq_base_indirect_dma = %llx.\n",
1302 (unsigned long long) rx_ring->sbq_base_indirect_dma);
1303 printk(KERN_ERR PFX "rx_ring->sbq = %p.\n", rx_ring->sbq);
1304 printk(KERN_ERR PFX "rx_ring->sbq_len = %d.\n", rx_ring->sbq_len);
1305 printk(KERN_ERR PFX "rx_ring->sbq_size = %d.\n", rx_ring->sbq_size);
1306 printk(KERN_ERR PFX "rx_ring->sbq_prod_idx_db_reg addr = %p.\n",
1307 rx_ring->sbq_prod_idx_db_reg);
1308 printk(KERN_ERR PFX "rx_ring->sbq_prod_idx = %d.\n",
1309 rx_ring->sbq_prod_idx);
1310 printk(KERN_ERR PFX "rx_ring->sbq_curr_idx = %d.\n",
1311 rx_ring->sbq_curr_idx);
1312 printk(KERN_ERR PFX "rx_ring->sbq_clean_idx = %d.\n",
1313 rx_ring->sbq_clean_idx);
1314 printk(KERN_ERR PFX "rx_ring->sbq_free_cnt = %d.\n",
1315 rx_ring->sbq_free_cnt);
1316 printk(KERN_ERR PFX "rx_ring->sbq_buf_size = %d.\n",
1317 rx_ring->sbq_buf_size);
1318 printk(KERN_ERR PFX "rx_ring->cq_id = %d.\n", rx_ring->cq_id);
1319 printk(KERN_ERR PFX "rx_ring->irq = %d.\n", rx_ring->irq);
1320 printk(KERN_ERR PFX "rx_ring->cpu = %d.\n", rx_ring->cpu);
1321 printk(KERN_ERR PFX "rx_ring->qdev = %p.\n", rx_ring->qdev);
1322 }
1323
1324 void ql_dump_hw_cb(struct ql_adapter *qdev, int size, u32 bit, u16 q_id)
1325 {
1326 void *ptr;
1327
1328 printk(KERN_ERR PFX "%s: Enter.\n", __func__);
1329
1330 ptr = kmalloc(size, GFP_ATOMIC);
1331 if (ptr == NULL) {
1332 printk(KERN_ERR PFX "%s: Couldn't allocate a buffer.\n",
1333 __func__);
1334 return;
1335 }
1336
1337 if (ql_write_cfg(qdev, ptr, size, bit, q_id)) {
1338 printk(KERN_ERR "%s: Failed to upload control block!\n",
1339 __func__);
1340 goto fail_it;
1341 }
1342 switch (bit) {
1343 case CFG_DRQ:
1344 ql_dump_wqicb((struct wqicb *)ptr);
1345 break;
1346 case CFG_DCQ:
1347 ql_dump_cqicb((struct cqicb *)ptr);
1348 break;
1349 case CFG_DR:
1350 ql_dump_ricb((struct ricb *)ptr);
1351 break;
1352 default:
1353 printk(KERN_ERR PFX "%s: Invalid bit value = %x.\n",
1354 __func__, bit);
1355 break;
1356 }
1357 fail_it:
1358 kfree(ptr);
1359 }
1360 #endif
1361
1362 #ifdef QL_OB_DUMP
1363 void ql_dump_tx_desc(struct tx_buf_desc *tbd)
1364 {
1365 printk(KERN_ERR PFX "tbd->addr = 0x%llx\n",
1366 le64_to_cpu((u64) tbd->addr));
1367 printk(KERN_ERR PFX "tbd->len = %d\n",
1368 le32_to_cpu(tbd->len & TX_DESC_LEN_MASK));
1369 printk(KERN_ERR PFX "tbd->flags = %s %s\n",
1370 tbd->len & TX_DESC_C ? "C" : ".",
1371 tbd->len & TX_DESC_E ? "E" : ".");
1372 tbd++;
1373 printk(KERN_ERR PFX "tbd->addr = 0x%llx\n",
1374 le64_to_cpu((u64) tbd->addr));
1375 printk(KERN_ERR PFX "tbd->len = %d\n",
1376 le32_to_cpu(tbd->len & TX_DESC_LEN_MASK));
1377 printk(KERN_ERR PFX "tbd->flags = %s %s\n",
1378 tbd->len & TX_DESC_C ? "C" : ".",
1379 tbd->len & TX_DESC_E ? "E" : ".");
1380 tbd++;
1381 printk(KERN_ERR PFX "tbd->addr = 0x%llx\n",
1382 le64_to_cpu((u64) tbd->addr));
1383 printk(KERN_ERR PFX "tbd->len = %d\n",
1384 le32_to_cpu(tbd->len & TX_DESC_LEN_MASK));
1385 printk(KERN_ERR PFX "tbd->flags = %s %s\n",
1386 tbd->len & TX_DESC_C ? "C" : ".",
1387 tbd->len & TX_DESC_E ? "E" : ".");
1388
1389 }
1390
1391 void ql_dump_ob_mac_iocb(struct ob_mac_iocb_req *ob_mac_iocb)
1392 {
1393 struct ob_mac_tso_iocb_req *ob_mac_tso_iocb =
1394 (struct ob_mac_tso_iocb_req *)ob_mac_iocb;
1395 struct tx_buf_desc *tbd;
1396 u16 frame_len;
1397
1398 printk(KERN_ERR PFX "%s\n", __func__);
1399 printk(KERN_ERR PFX "opcode = %s\n",
1400 (ob_mac_iocb->opcode == OPCODE_OB_MAC_IOCB) ? "MAC" : "TSO");
1401 printk(KERN_ERR PFX "flags1 = %s %s %s %s %s\n",
1402 ob_mac_tso_iocb->flags1 & OB_MAC_TSO_IOCB_OI ? "OI" : "",
1403 ob_mac_tso_iocb->flags1 & OB_MAC_TSO_IOCB_I ? "I" : "",
1404 ob_mac_tso_iocb->flags1 & OB_MAC_TSO_IOCB_D ? "D" : "",
1405 ob_mac_tso_iocb->flags1 & OB_MAC_TSO_IOCB_IP4 ? "IP4" : "",
1406 ob_mac_tso_iocb->flags1 & OB_MAC_TSO_IOCB_IP6 ? "IP6" : "");
1407 printk(KERN_ERR PFX "flags2 = %s %s %s\n",
1408 ob_mac_tso_iocb->flags2 & OB_MAC_TSO_IOCB_LSO ? "LSO" : "",
1409 ob_mac_tso_iocb->flags2 & OB_MAC_TSO_IOCB_UC ? "UC" : "",
1410 ob_mac_tso_iocb->flags2 & OB_MAC_TSO_IOCB_TC ? "TC" : "");
1411 printk(KERN_ERR PFX "flags3 = %s %s %s \n",
1412 ob_mac_tso_iocb->flags3 & OB_MAC_TSO_IOCB_IC ? "IC" : "",
1413 ob_mac_tso_iocb->flags3 & OB_MAC_TSO_IOCB_DFP ? "DFP" : "",
1414 ob_mac_tso_iocb->flags3 & OB_MAC_TSO_IOCB_V ? "V" : "");
1415 printk(KERN_ERR PFX "tid = %x\n", ob_mac_iocb->tid);
1416 printk(KERN_ERR PFX "txq_idx = %d\n", ob_mac_iocb->txq_idx);
1417 printk(KERN_ERR PFX "vlan_tci = %x\n", ob_mac_tso_iocb->vlan_tci);
1418 if (ob_mac_iocb->opcode == OPCODE_OB_MAC_TSO_IOCB) {
1419 printk(KERN_ERR PFX "frame_len = %d\n",
1420 le32_to_cpu(ob_mac_tso_iocb->frame_len));
1421 printk(KERN_ERR PFX "mss = %d\n",
1422 le16_to_cpu(ob_mac_tso_iocb->mss));
1423 printk(KERN_ERR PFX "prot_hdr_len = %d\n",
1424 le16_to_cpu(ob_mac_tso_iocb->total_hdrs_len));
1425 printk(KERN_ERR PFX "hdr_offset = 0x%.04x\n",
1426 le16_to_cpu(ob_mac_tso_iocb->net_trans_offset));
1427 frame_len = le32_to_cpu(ob_mac_tso_iocb->frame_len);
1428 } else {
1429 printk(KERN_ERR PFX "frame_len = %d\n",
1430 le16_to_cpu(ob_mac_iocb->frame_len));
1431 frame_len = le16_to_cpu(ob_mac_iocb->frame_len);
1432 }
1433 tbd = &ob_mac_iocb->tbd[0];
1434 ql_dump_tx_desc(tbd);
1435 }
1436
1437 void ql_dump_ob_mac_rsp(struct ob_mac_iocb_rsp *ob_mac_rsp)
1438 {
1439 printk(KERN_ERR PFX "%s\n", __func__);
1440 printk(KERN_ERR PFX "opcode = %d\n", ob_mac_rsp->opcode);
1441 printk(KERN_ERR PFX "flags = %s %s %s %s %s %s %s\n",
1442 ob_mac_rsp->flags1 & OB_MAC_IOCB_RSP_OI ? "OI" : ".",
1443 ob_mac_rsp->flags1 & OB_MAC_IOCB_RSP_I ? "I" : ".",
1444 ob_mac_rsp->flags1 & OB_MAC_IOCB_RSP_E ? "E" : ".",
1445 ob_mac_rsp->flags1 & OB_MAC_IOCB_RSP_S ? "S" : ".",
1446 ob_mac_rsp->flags1 & OB_MAC_IOCB_RSP_L ? "L" : ".",
1447 ob_mac_rsp->flags1 & OB_MAC_IOCB_RSP_P ? "P" : ".",
1448 ob_mac_rsp->flags2 & OB_MAC_IOCB_RSP_B ? "B" : ".");
1449 printk(KERN_ERR PFX "tid = %x\n", ob_mac_rsp->tid);
1450 }
1451 #endif
1452
1453 #ifdef QL_IB_DUMP
1454 void ql_dump_ib_mac_rsp(struct ib_mac_iocb_rsp *ib_mac_rsp)
1455 {
1456 printk(KERN_ERR PFX "%s\n", __func__);
1457 printk(KERN_ERR PFX "opcode = 0x%x\n", ib_mac_rsp->opcode);
1458 printk(KERN_ERR PFX "flags1 = %s%s%s%s%s%s\n",
1459 ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_OI ? "OI " : "",
1460 ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_I ? "I " : "",
1461 ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_TE ? "TE " : "",
1462 ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_NU ? "NU " : "",
1463 ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_IE ? "IE " : "",
1464 ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_B ? "B " : "");
1465
1466 if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK)
1467 printk(KERN_ERR PFX "%s%s%s Multicast.\n",
1468 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1469 IB_MAC_IOCB_RSP_M_HASH ? "Hash" : "",
1470 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1471 IB_MAC_IOCB_RSP_M_REG ? "Registered" : "",
1472 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1473 IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
1474
1475 printk(KERN_ERR PFX "flags2 = %s%s%s%s%s\n",
1476 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) ? "P " : "",
1477 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ? "V " : "",
1478 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) ? "U " : "",
1479 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) ? "T " : "",
1480 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_FO) ? "FO " : "");
1481
1482 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK)
1483 printk(KERN_ERR PFX "%s%s%s%s%s error.\n",
1484 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) ==
1485 IB_MAC_IOCB_RSP_ERR_OVERSIZE ? "oversize" : "",
1486 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) ==
1487 IB_MAC_IOCB_RSP_ERR_UNDERSIZE ? "undersize" : "",
1488 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) ==
1489 IB_MAC_IOCB_RSP_ERR_PREAMBLE ? "preamble" : "",
1490 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) ==
1491 IB_MAC_IOCB_RSP_ERR_FRAME_LEN ? "frame length" : "",
1492 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) ==
1493 IB_MAC_IOCB_RSP_ERR_CRC ? "CRC" : "");
1494
1495 printk(KERN_ERR PFX "flags3 = %s%s.\n",
1496 ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS ? "DS " : "",
1497 ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL ? "DL " : "");
1498
1499 if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_RSS_MASK)
1500 printk(KERN_ERR PFX "RSS flags = %s%s%s%s.\n",
1501 ((ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_RSS_MASK) ==
1502 IB_MAC_IOCB_RSP_M_IPV4) ? "IPv4 RSS" : "",
1503 ((ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_RSS_MASK) ==
1504 IB_MAC_IOCB_RSP_M_IPV6) ? "IPv6 RSS " : "",
1505 ((ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_RSS_MASK) ==
1506 IB_MAC_IOCB_RSP_M_TCP_V4) ? "TCP/IPv4 RSS" : "",
1507 ((ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_RSS_MASK) ==
1508 IB_MAC_IOCB_RSP_M_TCP_V6) ? "TCP/IPv6 RSS" : "");
1509
1510 printk(KERN_ERR PFX "data_len = %d\n",
1511 le32_to_cpu(ib_mac_rsp->data_len));
1512 printk(KERN_ERR PFX "data_addr = 0x%llx\n",
1513 (unsigned long long) le64_to_cpu(ib_mac_rsp->data_addr));
1514 if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_RSS_MASK)
1515 printk(KERN_ERR PFX "rss = %x\n",
1516 le32_to_cpu(ib_mac_rsp->rss));
1517 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V)
1518 printk(KERN_ERR PFX "vlan_id = %x\n",
1519 le16_to_cpu(ib_mac_rsp->vlan_id));
1520
1521 printk(KERN_ERR PFX "flags4 = %s%s%s.\n",
1522 ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV ? "HV " : "",
1523 ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS ? "HS " : "",
1524 ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HL ? "HL " : "");
1525
1526 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV) {
1527 printk(KERN_ERR PFX "hdr length = %d.\n",
1528 le32_to_cpu(ib_mac_rsp->hdr_len));
1529 printk(KERN_ERR PFX "hdr addr = 0x%llx.\n",
1530 (unsigned long long) le64_to_cpu(ib_mac_rsp->hdr_addr));
1531 }
1532 }
1533 #endif
1534
1535 #ifdef QL_ALL_DUMP
1536 void ql_dump_all(struct ql_adapter *qdev)
1537 {
1538 int i;
1539
1540 QL_DUMP_REGS(qdev);
1541 QL_DUMP_QDEV(qdev);
1542 for (i = 0; i < qdev->tx_ring_count; i++) {
1543 QL_DUMP_TX_RING(&qdev->tx_ring[i]);
1544 QL_DUMP_WQICB((struct wqicb *)&qdev->tx_ring[i]);
1545 }
1546 for (i = 0; i < qdev->rx_ring_count; i++) {
1547 QL_DUMP_RX_RING(&qdev->rx_ring[i]);
1548 QL_DUMP_CQICB((struct cqicb *)&qdev->rx_ring[i]);
1549 }
1550 }
1551 #endif
Linux kernel - Deliverables
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