2 =========================================================================
3 r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver for Linux kernel 2.4.x.
4 --------------------------------------------------------------------
7 Feb 4 2002 - created initially by ShuChen <shuchen@realtek.com.tw>.
8 May 20 2002 - Add link status force-mode and TBI mode support.
9 2004 - Massive updates. See kernel SCM system for details.
10 =========================================================================
11 1. [DEPRECATED: use ethtool instead] The media can be forced in 5 modes.
12 Command: 'insmod r8169 media = SET_MEDIA'
13 Ex: 'insmod r8169 media = 0x04' will force PHY to operate in 100Mpbs Half-duplex.
23 =========================================================================
24 VERSION 1.1 <2002/10/4>
26 The bit4:0 of MII register 4 is called "selector field", and have to be
27 00001b to indicate support of IEEE std 802.3 during NWay process of
28 exchanging Link Code Word (FLP).
30 VERSION 1.2 <2002/11/30>
33 - Use ether_crc in stock kernel (linux/crc32.h)
34 - Copy mc_filter setup code from 8139cp
35 (includes an optimization, and avoids set_bit use)
37 VERSION 1.6LK <2004/04/14>
39 - Merge of Realtek's version 1.6
40 - Conversion to DMA API
45 VERSION 2.2LK <2005/01/25>
47 - RX csum, TX csum/SG, TSO
49 - baby (< 7200) Jumbo frames support
50 - Merge of Realtek's version 2.2 (new phy)
53 #include <linux/module.h>
54 #include <linux/moduleparam.h>
55 #include <linux/pci.h>
56 #include <linux/netdevice.h>
57 #include <linux/etherdevice.h>
58 #include <linux/delay.h>
59 #include <linux/ethtool.h>
60 #include <linux/mii.h>
61 #include <linux/if_vlan.h>
62 #include <linux/crc32.h>
65 #include <linux/tcp.h>
66 #include <linux/init.h>
67 #include <linux/dma-mapping.h>
69 #include <asm/system.h>
73 #ifdef CONFIG_R8169_NAPI
74 #define NAPI_SUFFIX "-NAPI"
76 #define NAPI_SUFFIX ""
79 #define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
80 #define MODULENAME "r8169"
81 #define PFX MODULENAME ": "
84 #define assert(expr) \
86 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
87 #expr,__FILE__,__FUNCTION__,__LINE__); \
89 #define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0)
91 #define assert(expr) do {} while (0)
92 #define dprintk(fmt, args...) do {} while (0)
93 #endif /* RTL8169_DEBUG */
95 #define R8169_MSG_DEFAULT \
96 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
98 #define TX_BUFFS_AVAIL(tp) \
99 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
101 #ifdef CONFIG_R8169_NAPI
102 #define rtl8169_rx_skb netif_receive_skb
103 #define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
104 #define rtl8169_rx_quota(count, quota) min(count, quota)
106 #define rtl8169_rx_skb netif_rx
107 #define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
108 #define rtl8169_rx_quota(count, quota) count
113 static int media
[MAX_UNITS
] = { -1, -1, -1, -1, -1, -1, -1, -1 };
114 static int num_media
= 0;
116 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
117 static const int max_interrupt_work
= 20;
119 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
120 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
121 static const int multicast_filter_limit
= 32;
123 /* MAC address length */
124 #define MAC_ADDR_LEN 6
126 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
127 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
128 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
129 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
130 #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
131 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
132 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
134 #define R8169_REGS_SIZE 256
135 #define R8169_NAPI_WEIGHT 64
136 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
137 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
138 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
139 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
140 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
142 #define RTL8169_TX_TIMEOUT (6*HZ)
143 #define RTL8169_PHY_TIMEOUT (10*HZ)
145 /* write/read MMIO register */
146 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
147 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
148 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
149 #define RTL_R8(reg) readb (ioaddr + (reg))
150 #define RTL_R16(reg) readw (ioaddr + (reg))
151 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
154 RTL_GIGA_MAC_VER_01
= 0x01, // 8169
155 RTL_GIGA_MAC_VER_02
= 0x02, // 8169S
156 RTL_GIGA_MAC_VER_03
= 0x03, // 8110S
157 RTL_GIGA_MAC_VER_04
= 0x04, // 8169SB
158 RTL_GIGA_MAC_VER_05
= 0x05, // 8110SCd
159 RTL_GIGA_MAC_VER_06
= 0x06, // 8110SCe
160 RTL_GIGA_MAC_VER_11
= 0x0b, // 8168Bb
161 RTL_GIGA_MAC_VER_12
= 0x0c, // 8168Be 8168Bf
162 RTL_GIGA_MAC_VER_13
= 0x0d, // 8101Eb 8101Ec
163 RTL_GIGA_MAC_VER_14
= 0x0e, // 8101
164 RTL_GIGA_MAC_VER_15
= 0x0f // 8101
168 RTL_GIGA_PHY_VER_C
= 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
169 RTL_GIGA_PHY_VER_D
= 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
170 RTL_GIGA_PHY_VER_E
= 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
171 RTL_GIGA_PHY_VER_F
= 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
172 RTL_GIGA_PHY_VER_G
= 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
173 RTL_GIGA_PHY_VER_H
= 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
176 #define _R(NAME,MAC,MASK) \
177 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
179 static const struct {
182 u32 RxConfigMask
; /* Clears the bits supported by this chip */
183 } rtl_chip_info
[] = {
184 _R("RTL8169", RTL_GIGA_MAC_VER_01
, 0xff7e1880), // 8169
185 _R("RTL8169s", RTL_GIGA_MAC_VER_02
, 0xff7e1880), // 8169S
186 _R("RTL8110s", RTL_GIGA_MAC_VER_03
, 0xff7e1880), // 8110S
187 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04
, 0xff7e1880), // 8169SB
188 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05
, 0xff7e1880), // 8110SCd
189 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06
, 0xff7e1880), // 8110SCe
190 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11
, 0xff7e1880), // PCI-E
191 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12
, 0xff7e1880), // PCI-E
192 _R("RTL8101e", RTL_GIGA_MAC_VER_13
, 0xff7e1880), // PCI-E 8139
193 _R("RTL8100e", RTL_GIGA_MAC_VER_14
, 0xff7e1880), // PCI-E 8139
194 _R("RTL8100e", RTL_GIGA_MAC_VER_15
, 0xff7e1880) // PCI-E 8139
204 static void rtl_hw_start_8169(struct net_device
*);
205 static void rtl_hw_start_8168(struct net_device
*);
206 static void rtl_hw_start_8101(struct net_device
*);
208 static struct pci_device_id rtl8169_pci_tbl
[] = {
209 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8129), 0, 0, RTL_CFG_0
},
210 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8136), 0, 0, RTL_CFG_2
},
211 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8167), 0, 0, RTL_CFG_0
},
212 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8168), 0, 0, RTL_CFG_1
},
213 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8169), 0, 0, RTL_CFG_0
},
214 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4300), 0, 0, RTL_CFG_0
},
215 { PCI_DEVICE(0x1259, 0xc107), 0, 0, RTL_CFG_0
},
216 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0
},
217 { PCI_VENDOR_ID_LINKSYS
, 0x1032,
218 PCI_ANY_ID
, 0x0024, 0, 0, RTL_CFG_0
},
222 MODULE_DEVICE_TABLE(pci
, rtl8169_pci_tbl
);
224 static int rx_copybreak
= 200;
230 enum RTL8169_registers
{
231 MAC0
= 0, /* Ethernet hardware address. */
232 MAR0
= 8, /* Multicast filter. */
233 CounterAddrLow
= 0x10,
234 CounterAddrHigh
= 0x14,
235 TxDescStartAddrLow
= 0x20,
236 TxDescStartAddrHigh
= 0x24,
237 TxHDescStartAddrLow
= 0x28,
238 TxHDescStartAddrHigh
= 0x2c,
264 RxDescAddrLow
= 0xE4,
265 RxDescAddrHigh
= 0xE8,
268 FuncEventMask
= 0xF4,
269 FuncPresetState
= 0xF8,
270 FuncForceEvent
= 0xFC,
273 enum RTL8169_register_content
{
274 /* InterruptStatusBits */
278 TxDescUnavail
= 0x80,
302 Cfg9346_Unlock
= 0xC0,
307 AcceptBroadcast
= 0x08,
308 AcceptMulticast
= 0x04,
310 AcceptAllPhys
= 0x01,
317 TxInterFrameGapShift
= 24,
318 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
320 /* Config1 register p.24 */
321 PMEnable
= (1 << 0), /* Power Management Enable */
323 /* Config2 register p. 25 */
324 PCI_Clock_66MHz
= 0x01,
325 PCI_Clock_33MHz
= 0x00,
327 /* Config3 register p.25 */
328 MagicPacket
= (1 << 5), /* Wake up when receives a Magic Packet */
329 LinkUp
= (1 << 4), /* Wake up when the cable connection is re-established */
331 /* Config5 register p.27 */
332 BWF
= (1 << 6), /* Accept Broadcast wakeup frame */
333 MWF
= (1 << 5), /* Accept Multicast wakeup frame */
334 UWF
= (1 << 4), /* Accept Unicast wakeup frame */
335 LanWake
= (1 << 1), /* LanWake enable/disable */
336 PMEStatus
= (1 << 0), /* PME status can be reset by PCI RST# */
339 TBIReset
= 0x80000000,
340 TBILoopback
= 0x40000000,
341 TBINwEnable
= 0x20000000,
342 TBINwRestart
= 0x10000000,
343 TBILinkOk
= 0x02000000,
344 TBINwComplete
= 0x01000000,
347 PktCntrDisable
= (1 << 7), // 8168
352 INTT_0
= 0x0000, // 8168
353 INTT_1
= 0x0001, // 8168
354 INTT_2
= 0x0002, // 8168
355 INTT_3
= 0x0003, // 8168
357 /* rtl8169_PHYstatus */
375 TBILinkOK
= 0x02000000,
377 /* DumpCounterCommand */
381 enum _DescStatusBit
{
382 DescOwn
= (1 << 31), /* Descriptor is owned by NIC */
383 RingEnd
= (1 << 30), /* End of descriptor ring */
384 FirstFrag
= (1 << 29), /* First segment of a packet */
385 LastFrag
= (1 << 28), /* Final segment of a packet */
388 LargeSend
= (1 << 27), /* TCP Large Send Offload (TSO) */
389 MSSShift
= 16, /* MSS value position */
390 MSSMask
= 0xfff, /* MSS value + LargeSend bit: 12 bits */
391 IPCS
= (1 << 18), /* Calculate IP checksum */
392 UDPCS
= (1 << 17), /* Calculate UDP/IP checksum */
393 TCPCS
= (1 << 16), /* Calculate TCP/IP checksum */
394 TxVlanTag
= (1 << 17), /* Add VLAN tag */
397 PID1
= (1 << 18), /* Protocol ID bit 1/2 */
398 PID0
= (1 << 17), /* Protocol ID bit 2/2 */
400 #define RxProtoUDP (PID1)
401 #define RxProtoTCP (PID0)
402 #define RxProtoIP (PID1 | PID0)
403 #define RxProtoMask RxProtoIP
405 IPFail
= (1 << 16), /* IP checksum failed */
406 UDPFail
= (1 << 15), /* UDP/IP checksum failed */
407 TCPFail
= (1 << 14), /* TCP/IP checksum failed */
408 RxVlanTag
= (1 << 16), /* VLAN tag available */
411 #define RsvdMask 0x3fffc000
428 u8 __pad
[sizeof(void *) - sizeof(u32
)];
431 struct rtl8169_private
{
432 void __iomem
*mmio_addr
; /* memory map physical address */
433 struct pci_dev
*pci_dev
; /* Index of PCI device */
434 struct net_device
*dev
;
435 struct net_device_stats stats
; /* statistics of net device */
436 spinlock_t lock
; /* spin lock flag */
441 u32 cur_rx
; /* Index into the Rx descriptor buffer of next Rx pkt. */
442 u32 cur_tx
; /* Index into the Tx descriptor buffer of next Rx pkt. */
445 struct TxDesc
*TxDescArray
; /* 256-aligned Tx descriptor ring */
446 struct RxDesc
*RxDescArray
; /* 256-aligned Rx descriptor ring */
447 dma_addr_t TxPhyAddr
;
448 dma_addr_t RxPhyAddr
;
449 struct sk_buff
*Rx_skbuff
[NUM_RX_DESC
]; /* Rx data buffers */
450 struct ring_info tx_skb
[NUM_TX_DESC
]; /* Tx data buffers */
453 struct timer_list timer
;
458 int phy_auto_nego_reg
;
459 int phy_1000_ctrl_reg
;
460 #ifdef CONFIG_R8169_VLAN
461 struct vlan_group
*vlgrp
;
463 int (*set_speed
)(struct net_device
*, u8 autoneg
, u16 speed
, u8 duplex
);
464 void (*get_settings
)(struct net_device
*, struct ethtool_cmd
*);
465 void (*phy_reset_enable
)(void __iomem
*);
466 void (*hw_start
)(struct net_device
*);
467 unsigned int (*phy_reset_pending
)(void __iomem
*);
468 unsigned int (*link_ok
)(void __iomem
*);
469 struct delayed_work task
;
470 unsigned wol_enabled
: 1;
473 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
474 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
475 module_param_array(media
, int, &num_media
, 0);
476 MODULE_PARM_DESC(media
, "force phy operation. Deprecated by ethtool (8).");
477 module_param(rx_copybreak
, int, 0);
478 MODULE_PARM_DESC(rx_copybreak
, "Copy breakpoint for copy-only-tiny-frames");
479 module_param(use_dac
, int, 0);
480 MODULE_PARM_DESC(use_dac
, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
481 module_param_named(debug
, debug
.msg_enable
, int, 0);
482 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 16=all)");
483 MODULE_LICENSE("GPL");
484 MODULE_VERSION(RTL8169_VERSION
);
486 static int rtl8169_open(struct net_device
*dev
);
487 static int rtl8169_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
488 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
);
489 static int rtl8169_init_ring(struct net_device
*dev
);
490 static void rtl_hw_start(struct net_device
*dev
);
491 static int rtl8169_close(struct net_device
*dev
);
492 static void rtl_set_rx_mode(struct net_device
*dev
);
493 static void rtl8169_tx_timeout(struct net_device
*dev
);
494 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
);
495 static int rtl8169_rx_interrupt(struct net_device
*, struct rtl8169_private
*,
497 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
);
498 static void rtl8169_down(struct net_device
*dev
);
499 static void rtl8169_rx_clear(struct rtl8169_private
*tp
);
501 #ifdef CONFIG_R8169_NAPI
502 static int rtl8169_poll(struct net_device
*dev
, int *budget
);
505 static const unsigned int rtl8169_rx_config
=
506 (RX_FIFO_THRESH
<< RxCfgFIFOShift
) | (RX_DMA_BURST
<< RxCfgDMAShift
);
508 static void mdio_write(void __iomem
*ioaddr
, int RegAddr
, int value
)
512 RTL_W32(PHYAR
, 0x80000000 | (RegAddr
& 0xFF) << 16 | value
);
514 for (i
= 20; i
> 0; i
--) {
515 /* Check if the RTL8169 has completed writing to the specified MII register */
516 if (!(RTL_R32(PHYAR
) & 0x80000000))
522 static int mdio_read(void __iomem
*ioaddr
, int RegAddr
)
526 RTL_W32(PHYAR
, 0x0 | (RegAddr
& 0xFF) << 16);
528 for (i
= 20; i
> 0; i
--) {
529 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
530 if (RTL_R32(PHYAR
) & 0x80000000) {
531 value
= (int) (RTL_R32(PHYAR
) & 0xFFFF);
539 static void rtl8169_irq_mask_and_ack(void __iomem
*ioaddr
)
541 RTL_W16(IntrMask
, 0x0000);
543 RTL_W16(IntrStatus
, 0xffff);
546 static void rtl8169_asic_down(void __iomem
*ioaddr
)
548 RTL_W8(ChipCmd
, 0x00);
549 rtl8169_irq_mask_and_ack(ioaddr
);
553 static unsigned int rtl8169_tbi_reset_pending(void __iomem
*ioaddr
)
555 return RTL_R32(TBICSR
) & TBIReset
;
558 static unsigned int rtl8169_xmii_reset_pending(void __iomem
*ioaddr
)
560 return mdio_read(ioaddr
, MII_BMCR
) & BMCR_RESET
;
563 static unsigned int rtl8169_tbi_link_ok(void __iomem
*ioaddr
)
565 return RTL_R32(TBICSR
) & TBILinkOk
;
568 static unsigned int rtl8169_xmii_link_ok(void __iomem
*ioaddr
)
570 return RTL_R8(PHYstatus
) & LinkStatus
;
573 static void rtl8169_tbi_reset_enable(void __iomem
*ioaddr
)
575 RTL_W32(TBICSR
, RTL_R32(TBICSR
) | TBIReset
);
578 static void rtl8169_xmii_reset_enable(void __iomem
*ioaddr
)
582 val
= mdio_read(ioaddr
, MII_BMCR
) | BMCR_RESET
;
583 mdio_write(ioaddr
, MII_BMCR
, val
& 0xffff);
586 static void rtl8169_check_link_status(struct net_device
*dev
,
587 struct rtl8169_private
*tp
, void __iomem
*ioaddr
)
591 spin_lock_irqsave(&tp
->lock
, flags
);
592 if (tp
->link_ok(ioaddr
)) {
593 netif_carrier_on(dev
);
594 if (netif_msg_ifup(tp
))
595 printk(KERN_INFO PFX
"%s: link up\n", dev
->name
);
597 if (netif_msg_ifdown(tp
))
598 printk(KERN_INFO PFX
"%s: link down\n", dev
->name
);
599 netif_carrier_off(dev
);
601 spin_unlock_irqrestore(&tp
->lock
, flags
);
604 static void rtl8169_link_option(int idx
, u8
*autoneg
, u16
*speed
, u8
*duplex
)
611 } link_settings
[] = {
612 { SPEED_10
, DUPLEX_HALF
, AUTONEG_DISABLE
, _10_Half
},
613 { SPEED_10
, DUPLEX_FULL
, AUTONEG_DISABLE
, _10_Full
},
614 { SPEED_100
, DUPLEX_HALF
, AUTONEG_DISABLE
, _100_Half
},
615 { SPEED_100
, DUPLEX_FULL
, AUTONEG_DISABLE
, _100_Full
},
616 { SPEED_1000
, DUPLEX_FULL
, AUTONEG_DISABLE
, _1000_Full
},
618 { SPEED_1000
, DUPLEX_FULL
, AUTONEG_ENABLE
, 0xff }
620 unsigned char option
;
622 option
= ((idx
< MAX_UNITS
) && (idx
>= 0)) ? media
[idx
] : 0xff;
624 if ((option
!= 0xff) && !idx
&& netif_msg_drv(&debug
))
625 printk(KERN_WARNING PFX
"media option is deprecated.\n");
627 for (p
= link_settings
; p
->media
!= 0xff; p
++) {
628 if (p
->media
== option
)
631 *autoneg
= p
->autoneg
;
636 static void rtl8169_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
638 struct rtl8169_private
*tp
= netdev_priv(dev
);
639 void __iomem
*ioaddr
= tp
->mmio_addr
;
644 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
645 wol
->supported
= WAKE_ANY
;
647 spin_lock_irq(&tp
->lock
);
649 options
= RTL_R8(Config1
);
650 if (!(options
& PMEnable
))
653 options
= RTL_R8(Config3
);
654 if (options
& LinkUp
)
655 wol
->wolopts
|= WAKE_PHY
;
656 if (options
& MagicPacket
)
657 wol
->wolopts
|= WAKE_MAGIC
;
659 options
= RTL_R8(Config5
);
661 wol
->wolopts
|= WAKE_UCAST
;
663 wol
->wolopts
|= WAKE_BCAST
;
665 wol
->wolopts
|= WAKE_MCAST
;
668 spin_unlock_irq(&tp
->lock
);
671 static int rtl8169_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
673 struct rtl8169_private
*tp
= netdev_priv(dev
);
674 void __iomem
*ioaddr
= tp
->mmio_addr
;
681 { WAKE_ANY
, Config1
, PMEnable
},
682 { WAKE_PHY
, Config3
, LinkUp
},
683 { WAKE_MAGIC
, Config3
, MagicPacket
},
684 { WAKE_UCAST
, Config5
, UWF
},
685 { WAKE_BCAST
, Config5
, BWF
},
686 { WAKE_MCAST
, Config5
, MWF
},
687 { WAKE_ANY
, Config5
, LanWake
}
690 spin_lock_irq(&tp
->lock
);
692 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
694 for (i
= 0; i
< ARRAY_SIZE(cfg
); i
++) {
695 u8 options
= RTL_R8(cfg
[i
].reg
) & ~cfg
[i
].mask
;
696 if (wol
->wolopts
& cfg
[i
].opt
)
697 options
|= cfg
[i
].mask
;
698 RTL_W8(cfg
[i
].reg
, options
);
701 RTL_W8(Cfg9346
, Cfg9346_Lock
);
703 tp
->wol_enabled
= (wol
->wolopts
) ? 1 : 0;
705 spin_unlock_irq(&tp
->lock
);
710 static void rtl8169_get_drvinfo(struct net_device
*dev
,
711 struct ethtool_drvinfo
*info
)
713 struct rtl8169_private
*tp
= netdev_priv(dev
);
715 strcpy(info
->driver
, MODULENAME
);
716 strcpy(info
->version
, RTL8169_VERSION
);
717 strcpy(info
->bus_info
, pci_name(tp
->pci_dev
));
720 static int rtl8169_get_regs_len(struct net_device
*dev
)
722 return R8169_REGS_SIZE
;
725 static int rtl8169_set_speed_tbi(struct net_device
*dev
,
726 u8 autoneg
, u16 speed
, u8 duplex
)
728 struct rtl8169_private
*tp
= netdev_priv(dev
);
729 void __iomem
*ioaddr
= tp
->mmio_addr
;
733 reg
= RTL_R32(TBICSR
);
734 if ((autoneg
== AUTONEG_DISABLE
) && (speed
== SPEED_1000
) &&
735 (duplex
== DUPLEX_FULL
)) {
736 RTL_W32(TBICSR
, reg
& ~(TBINwEnable
| TBINwRestart
));
737 } else if (autoneg
== AUTONEG_ENABLE
)
738 RTL_W32(TBICSR
, reg
| TBINwEnable
| TBINwRestart
);
740 if (netif_msg_link(tp
)) {
741 printk(KERN_WARNING
"%s: "
742 "incorrect speed setting refused in TBI mode\n",
751 static int rtl8169_set_speed_xmii(struct net_device
*dev
,
752 u8 autoneg
, u16 speed
, u8 duplex
)
754 struct rtl8169_private
*tp
= netdev_priv(dev
);
755 void __iomem
*ioaddr
= tp
->mmio_addr
;
756 int auto_nego
, giga_ctrl
;
758 auto_nego
= mdio_read(ioaddr
, MII_ADVERTISE
);
759 auto_nego
&= ~(ADVERTISE_10HALF
| ADVERTISE_10FULL
|
760 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
761 giga_ctrl
= mdio_read(ioaddr
, MII_CTRL1000
);
762 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
764 if (autoneg
== AUTONEG_ENABLE
) {
765 auto_nego
|= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
766 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
767 giga_ctrl
|= ADVERTISE_1000FULL
| ADVERTISE_1000HALF
;
769 if (speed
== SPEED_10
)
770 auto_nego
|= ADVERTISE_10HALF
| ADVERTISE_10FULL
;
771 else if (speed
== SPEED_100
)
772 auto_nego
|= ADVERTISE_100HALF
| ADVERTISE_100FULL
;
773 else if (speed
== SPEED_1000
)
774 giga_ctrl
|= ADVERTISE_1000FULL
| ADVERTISE_1000HALF
;
776 if (duplex
== DUPLEX_HALF
)
777 auto_nego
&= ~(ADVERTISE_10FULL
| ADVERTISE_100FULL
);
779 if (duplex
== DUPLEX_FULL
)
780 auto_nego
&= ~(ADVERTISE_10HALF
| ADVERTISE_100HALF
);
782 /* This tweak comes straight from Realtek's driver. */
783 if ((speed
== SPEED_100
) && (duplex
== DUPLEX_HALF
) &&
784 (tp
->mac_version
== RTL_GIGA_MAC_VER_13
)) {
785 auto_nego
= ADVERTISE_100HALF
| ADVERTISE_CSMA
;
789 /* The 8100e/8101e do Fast Ethernet only. */
790 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_13
) ||
791 (tp
->mac_version
== RTL_GIGA_MAC_VER_14
) ||
792 (tp
->mac_version
== RTL_GIGA_MAC_VER_15
)) {
793 if ((giga_ctrl
& (ADVERTISE_1000FULL
| ADVERTISE_1000HALF
)) &&
794 netif_msg_link(tp
)) {
795 printk(KERN_INFO
"%s: PHY does not support 1000Mbps.\n",
798 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
801 auto_nego
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
803 tp
->phy_auto_nego_reg
= auto_nego
;
804 tp
->phy_1000_ctrl_reg
= giga_ctrl
;
806 mdio_write(ioaddr
, MII_ADVERTISE
, auto_nego
);
807 mdio_write(ioaddr
, MII_CTRL1000
, giga_ctrl
);
808 mdio_write(ioaddr
, MII_BMCR
, BMCR_ANENABLE
| BMCR_ANRESTART
);
812 static int rtl8169_set_speed(struct net_device
*dev
,
813 u8 autoneg
, u16 speed
, u8 duplex
)
815 struct rtl8169_private
*tp
= netdev_priv(dev
);
818 ret
= tp
->set_speed(dev
, autoneg
, speed
, duplex
);
820 if (netif_running(dev
) && (tp
->phy_1000_ctrl_reg
& ADVERTISE_1000FULL
))
821 mod_timer(&tp
->timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
826 static int rtl8169_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
828 struct rtl8169_private
*tp
= netdev_priv(dev
);
832 spin_lock_irqsave(&tp
->lock
, flags
);
833 ret
= rtl8169_set_speed(dev
, cmd
->autoneg
, cmd
->speed
, cmd
->duplex
);
834 spin_unlock_irqrestore(&tp
->lock
, flags
);
839 static u32
rtl8169_get_rx_csum(struct net_device
*dev
)
841 struct rtl8169_private
*tp
= netdev_priv(dev
);
843 return tp
->cp_cmd
& RxChkSum
;
846 static int rtl8169_set_rx_csum(struct net_device
*dev
, u32 data
)
848 struct rtl8169_private
*tp
= netdev_priv(dev
);
849 void __iomem
*ioaddr
= tp
->mmio_addr
;
852 spin_lock_irqsave(&tp
->lock
, flags
);
855 tp
->cp_cmd
|= RxChkSum
;
857 tp
->cp_cmd
&= ~RxChkSum
;
859 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
862 spin_unlock_irqrestore(&tp
->lock
, flags
);
867 #ifdef CONFIG_R8169_VLAN
869 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
872 return (tp
->vlgrp
&& vlan_tx_tag_present(skb
)) ?
873 TxVlanTag
| swab16(vlan_tx_tag_get(skb
)) : 0x00;
876 static void rtl8169_vlan_rx_register(struct net_device
*dev
,
877 struct vlan_group
*grp
)
879 struct rtl8169_private
*tp
= netdev_priv(dev
);
880 void __iomem
*ioaddr
= tp
->mmio_addr
;
883 spin_lock_irqsave(&tp
->lock
, flags
);
886 tp
->cp_cmd
|= RxVlan
;
888 tp
->cp_cmd
&= ~RxVlan
;
889 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
891 spin_unlock_irqrestore(&tp
->lock
, flags
);
894 static int rtl8169_rx_vlan_skb(struct rtl8169_private
*tp
, struct RxDesc
*desc
,
897 u32 opts2
= le32_to_cpu(desc
->opts2
);
900 if (tp
->vlgrp
&& (opts2
& RxVlanTag
)) {
901 rtl8169_rx_hwaccel_skb(skb
, tp
->vlgrp
,
902 swab16(opts2
& 0xffff));
910 #else /* !CONFIG_R8169_VLAN */
912 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
918 static int rtl8169_rx_vlan_skb(struct rtl8169_private
*tp
, struct RxDesc
*desc
,
926 static void rtl8169_gset_tbi(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
928 struct rtl8169_private
*tp
= netdev_priv(dev
);
929 void __iomem
*ioaddr
= tp
->mmio_addr
;
933 SUPPORTED_1000baseT_Full
| SUPPORTED_Autoneg
| SUPPORTED_FIBRE
;
934 cmd
->port
= PORT_FIBRE
;
935 cmd
->transceiver
= XCVR_INTERNAL
;
937 status
= RTL_R32(TBICSR
);
938 cmd
->advertising
= (status
& TBINwEnable
) ? ADVERTISED_Autoneg
: 0;
939 cmd
->autoneg
= !!(status
& TBINwEnable
);
941 cmd
->speed
= SPEED_1000
;
942 cmd
->duplex
= DUPLEX_FULL
; /* Always set */
945 static void rtl8169_gset_xmii(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
947 struct rtl8169_private
*tp
= netdev_priv(dev
);
948 void __iomem
*ioaddr
= tp
->mmio_addr
;
951 cmd
->supported
= SUPPORTED_10baseT_Half
|
952 SUPPORTED_10baseT_Full
|
953 SUPPORTED_100baseT_Half
|
954 SUPPORTED_100baseT_Full
|
955 SUPPORTED_1000baseT_Full
|
960 cmd
->advertising
= ADVERTISED_TP
| ADVERTISED_Autoneg
;
962 if (tp
->phy_auto_nego_reg
& ADVERTISE_10HALF
)
963 cmd
->advertising
|= ADVERTISED_10baseT_Half
;
964 if (tp
->phy_auto_nego_reg
& ADVERTISE_10FULL
)
965 cmd
->advertising
|= ADVERTISED_10baseT_Full
;
966 if (tp
->phy_auto_nego_reg
& ADVERTISE_100HALF
)
967 cmd
->advertising
|= ADVERTISED_100baseT_Half
;
968 if (tp
->phy_auto_nego_reg
& ADVERTISE_100FULL
)
969 cmd
->advertising
|= ADVERTISED_100baseT_Full
;
970 if (tp
->phy_1000_ctrl_reg
& ADVERTISE_1000FULL
)
971 cmd
->advertising
|= ADVERTISED_1000baseT_Full
;
973 status
= RTL_R8(PHYstatus
);
975 if (status
& _1000bpsF
)
976 cmd
->speed
= SPEED_1000
;
977 else if (status
& _100bps
)
978 cmd
->speed
= SPEED_100
;
979 else if (status
& _10bps
)
980 cmd
->speed
= SPEED_10
;
982 if (status
& TxFlowCtrl
)
983 cmd
->advertising
|= ADVERTISED_Asym_Pause
;
984 if (status
& RxFlowCtrl
)
985 cmd
->advertising
|= ADVERTISED_Pause
;
987 cmd
->duplex
= ((status
& _1000bpsF
) || (status
& FullDup
)) ?
988 DUPLEX_FULL
: DUPLEX_HALF
;
991 static int rtl8169_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
993 struct rtl8169_private
*tp
= netdev_priv(dev
);
996 spin_lock_irqsave(&tp
->lock
, flags
);
998 tp
->get_settings(dev
, cmd
);
1000 spin_unlock_irqrestore(&tp
->lock
, flags
);
1004 static void rtl8169_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1007 struct rtl8169_private
*tp
= netdev_priv(dev
);
1008 unsigned long flags
;
1010 if (regs
->len
> R8169_REGS_SIZE
)
1011 regs
->len
= R8169_REGS_SIZE
;
1013 spin_lock_irqsave(&tp
->lock
, flags
);
1014 memcpy_fromio(p
, tp
->mmio_addr
, regs
->len
);
1015 spin_unlock_irqrestore(&tp
->lock
, flags
);
1018 static u32
rtl8169_get_msglevel(struct net_device
*dev
)
1020 struct rtl8169_private
*tp
= netdev_priv(dev
);
1022 return tp
->msg_enable
;
1025 static void rtl8169_set_msglevel(struct net_device
*dev
, u32 value
)
1027 struct rtl8169_private
*tp
= netdev_priv(dev
);
1029 tp
->msg_enable
= value
;
1032 static const char rtl8169_gstrings
[][ETH_GSTRING_LEN
] = {
1039 "tx_single_collisions",
1040 "tx_multi_collisions",
1048 struct rtl8169_counters
{
1055 u32 tx_one_collision
;
1056 u32 tx_multi_collision
;
1064 static int rtl8169_get_stats_count(struct net_device
*dev
)
1066 return ARRAY_SIZE(rtl8169_gstrings
);
1069 static void rtl8169_get_ethtool_stats(struct net_device
*dev
,
1070 struct ethtool_stats
*stats
, u64
*data
)
1072 struct rtl8169_private
*tp
= netdev_priv(dev
);
1073 void __iomem
*ioaddr
= tp
->mmio_addr
;
1074 struct rtl8169_counters
*counters
;
1080 counters
= pci_alloc_consistent(tp
->pci_dev
, sizeof(*counters
), &paddr
);
1084 RTL_W32(CounterAddrHigh
, (u64
)paddr
>> 32);
1085 cmd
= (u64
)paddr
& DMA_32BIT_MASK
;
1086 RTL_W32(CounterAddrLow
, cmd
);
1087 RTL_W32(CounterAddrLow
, cmd
| CounterDump
);
1089 while (RTL_R32(CounterAddrLow
) & CounterDump
) {
1090 if (msleep_interruptible(1))
1094 RTL_W32(CounterAddrLow
, 0);
1095 RTL_W32(CounterAddrHigh
, 0);
1097 data
[0] = le64_to_cpu(counters
->tx_packets
);
1098 data
[1] = le64_to_cpu(counters
->rx_packets
);
1099 data
[2] = le64_to_cpu(counters
->tx_errors
);
1100 data
[3] = le32_to_cpu(counters
->rx_errors
);
1101 data
[4] = le16_to_cpu(counters
->rx_missed
);
1102 data
[5] = le16_to_cpu(counters
->align_errors
);
1103 data
[6] = le32_to_cpu(counters
->tx_one_collision
);
1104 data
[7] = le32_to_cpu(counters
->tx_multi_collision
);
1105 data
[8] = le64_to_cpu(counters
->rx_unicast
);
1106 data
[9] = le64_to_cpu(counters
->rx_broadcast
);
1107 data
[10] = le32_to_cpu(counters
->rx_multicast
);
1108 data
[11] = le16_to_cpu(counters
->tx_aborted
);
1109 data
[12] = le16_to_cpu(counters
->tx_underun
);
1111 pci_free_consistent(tp
->pci_dev
, sizeof(*counters
), counters
, paddr
);
1114 static void rtl8169_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1118 memcpy(data
, *rtl8169_gstrings
, sizeof(rtl8169_gstrings
));
1124 static const struct ethtool_ops rtl8169_ethtool_ops
= {
1125 .get_drvinfo
= rtl8169_get_drvinfo
,
1126 .get_regs_len
= rtl8169_get_regs_len
,
1127 .get_link
= ethtool_op_get_link
,
1128 .get_settings
= rtl8169_get_settings
,
1129 .set_settings
= rtl8169_set_settings
,
1130 .get_msglevel
= rtl8169_get_msglevel
,
1131 .set_msglevel
= rtl8169_set_msglevel
,
1132 .get_rx_csum
= rtl8169_get_rx_csum
,
1133 .set_rx_csum
= rtl8169_set_rx_csum
,
1134 .get_tx_csum
= ethtool_op_get_tx_csum
,
1135 .set_tx_csum
= ethtool_op_set_tx_csum
,
1136 .get_sg
= ethtool_op_get_sg
,
1137 .set_sg
= ethtool_op_set_sg
,
1138 .get_tso
= ethtool_op_get_tso
,
1139 .set_tso
= ethtool_op_set_tso
,
1140 .get_regs
= rtl8169_get_regs
,
1141 .get_wol
= rtl8169_get_wol
,
1142 .set_wol
= rtl8169_set_wol
,
1143 .get_strings
= rtl8169_get_strings
,
1144 .get_stats_count
= rtl8169_get_stats_count
,
1145 .get_ethtool_stats
= rtl8169_get_ethtool_stats
,
1146 .get_perm_addr
= ethtool_op_get_perm_addr
,
1149 static void rtl8169_write_gmii_reg_bit(void __iomem
*ioaddr
, int reg
, int bitnum
,
1154 val
= mdio_read(ioaddr
, reg
);
1155 val
= (bitval
== 1) ?
1156 val
| (bitval
<< bitnum
) : val
& ~(0x0001 << bitnum
);
1157 mdio_write(ioaddr
, reg
, val
& 0xffff);
1160 static void rtl8169_get_mac_version(struct rtl8169_private
*tp
, void __iomem
*ioaddr
)
1163 * The driver currently handles the 8168Bf and the 8168Be identically
1164 * but they can be identified more specifically through the test below
1167 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1169 * Same thing for the 8101Eb and the 8101Ec:
1171 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1177 { 0x38800000, RTL_GIGA_MAC_VER_15
},
1178 { 0x38000000, RTL_GIGA_MAC_VER_12
},
1179 { 0x34000000, RTL_GIGA_MAC_VER_13
},
1180 { 0x30800000, RTL_GIGA_MAC_VER_14
},
1181 { 0x30000000, RTL_GIGA_MAC_VER_11
},
1182 { 0x98000000, RTL_GIGA_MAC_VER_06
},
1183 { 0x18000000, RTL_GIGA_MAC_VER_05
},
1184 { 0x10000000, RTL_GIGA_MAC_VER_04
},
1185 { 0x04000000, RTL_GIGA_MAC_VER_03
},
1186 { 0x00800000, RTL_GIGA_MAC_VER_02
},
1187 { 0x00000000, RTL_GIGA_MAC_VER_01
} /* Catch-all */
1191 reg
= RTL_R32(TxConfig
) & 0xfc800000;
1192 while ((reg
& p
->mask
) != p
->mask
)
1194 tp
->mac_version
= p
->mac_version
;
1197 static void rtl8169_print_mac_version(struct rtl8169_private
*tp
)
1199 dprintk("mac_version = 0x%02x\n", tp
->mac_version
);
1202 static void rtl8169_get_phy_version(struct rtl8169_private
*tp
, void __iomem
*ioaddr
)
1209 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G
},
1210 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F
},
1211 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E
},
1212 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D
} /* Catch-all */
1216 reg
= mdio_read(ioaddr
, MII_PHYSID2
) & 0xffff;
1217 while ((reg
& p
->mask
) != p
->set
)
1219 tp
->phy_version
= p
->phy_version
;
1222 static void rtl8169_print_phy_version(struct rtl8169_private
*tp
)
1229 { RTL_GIGA_PHY_VER_G
, "RTL_GIGA_PHY_VER_G", 0x0002 },
1230 { RTL_GIGA_PHY_VER_F
, "RTL_GIGA_PHY_VER_F", 0x0001 },
1231 { RTL_GIGA_PHY_VER_E
, "RTL_GIGA_PHY_VER_E", 0x0000 },
1232 { RTL_GIGA_PHY_VER_D
, "RTL_GIGA_PHY_VER_D", 0x0000 },
1236 for (p
= phy_print
; p
->msg
; p
++) {
1237 if (tp
->phy_version
== p
->version
) {
1238 dprintk("phy_version == %s (%04x)\n", p
->msg
, p
->reg
);
1242 dprintk("phy_version == Unknown\n");
1245 static void rtl8169_hw_phy_config(struct net_device
*dev
)
1247 struct rtl8169_private
*tp
= netdev_priv(dev
);
1248 void __iomem
*ioaddr
= tp
->mmio_addr
;
1250 u16 regs
[5]; /* Beware of bit-sign propagation */
1251 } phy_magic
[5] = { {
1252 { 0x0000, //w 4 15 12 0
1253 0x00a1, //w 3 15 0 00a1
1254 0x0008, //w 2 15 0 0008
1255 0x1020, //w 1 15 0 1020
1256 0x1000 } },{ //w 0 15 0 1000
1257 { 0x7000, //w 4 15 12 7
1258 0xff41, //w 3 15 0 ff41
1259 0xde60, //w 2 15 0 de60
1260 0x0140, //w 1 15 0 0140
1261 0x0077 } },{ //w 0 15 0 0077
1262 { 0xa000, //w 4 15 12 a
1263 0xdf01, //w 3 15 0 df01
1264 0xdf20, //w 2 15 0 df20
1265 0xff95, //w 1 15 0 ff95
1266 0xfa00 } },{ //w 0 15 0 fa00
1267 { 0xb000, //w 4 15 12 b
1268 0xff41, //w 3 15 0 ff41
1269 0xde20, //w 2 15 0 de20
1270 0x0140, //w 1 15 0 0140
1271 0x00bb } },{ //w 0 15 0 00bb
1272 { 0xf000, //w 4 15 12 f
1273 0xdf01, //w 3 15 0 df01
1274 0xdf20, //w 2 15 0 df20
1275 0xff95, //w 1 15 0 ff95
1276 0xbf00 } //w 0 15 0 bf00
1281 rtl8169_print_mac_version(tp
);
1282 rtl8169_print_phy_version(tp
);
1284 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_01
)
1286 if (tp
->phy_version
>= RTL_GIGA_PHY_VER_H
)
1289 dprintk("MAC version != 0 && PHY version == 0 or 1\n");
1290 dprintk("Do final_reg2.cfg\n");
1294 if (tp
->mac_version
== RTL_GIGA_MAC_VER_04
) {
1295 mdio_write(ioaddr
, 31, 0x0002);
1296 mdio_write(ioaddr
, 1, 0x90d0);
1297 mdio_write(ioaddr
, 31, 0x0000);
1301 /* phy config for RTL8169s mac_version C chip */
1302 mdio_write(ioaddr
, 31, 0x0001); //w 31 2 0 1
1303 mdio_write(ioaddr
, 21, 0x1000); //w 21 15 0 1000
1304 mdio_write(ioaddr
, 24, 0x65c7); //w 24 15 0 65c7
1305 rtl8169_write_gmii_reg_bit(ioaddr
, 4, 11, 0); //w 4 11 11 0
1307 for (i
= 0; i
< ARRAY_SIZE(phy_magic
); i
++, p
++) {
1310 val
= (mdio_read(ioaddr
, pos
) & 0x0fff) | (p
->regs
[0] & 0xffff);
1311 mdio_write(ioaddr
, pos
, val
);
1313 mdio_write(ioaddr
, pos
, p
->regs
[4 - pos
] & 0xffff);
1314 rtl8169_write_gmii_reg_bit(ioaddr
, 4, 11, 1); //w 4 11 11 1
1315 rtl8169_write_gmii_reg_bit(ioaddr
, 4, 11, 0); //w 4 11 11 0
1317 mdio_write(ioaddr
, 31, 0x0000); //w 31 2 0 0
1320 static void rtl8169_phy_timer(unsigned long __opaque
)
1322 struct net_device
*dev
= (struct net_device
*)__opaque
;
1323 struct rtl8169_private
*tp
= netdev_priv(dev
);
1324 struct timer_list
*timer
= &tp
->timer
;
1325 void __iomem
*ioaddr
= tp
->mmio_addr
;
1326 unsigned long timeout
= RTL8169_PHY_TIMEOUT
;
1328 assert(tp
->mac_version
> RTL_GIGA_MAC_VER_01
);
1329 assert(tp
->phy_version
< RTL_GIGA_PHY_VER_H
);
1331 if (!(tp
->phy_1000_ctrl_reg
& ADVERTISE_1000FULL
))
1334 spin_lock_irq(&tp
->lock
);
1336 if (tp
->phy_reset_pending(ioaddr
)) {
1338 * A busy loop could burn quite a few cycles on nowadays CPU.
1339 * Let's delay the execution of the timer for a few ticks.
1345 if (tp
->link_ok(ioaddr
))
1348 if (netif_msg_link(tp
))
1349 printk(KERN_WARNING
"%s: PHY reset until link up\n", dev
->name
);
1351 tp
->phy_reset_enable(ioaddr
);
1354 mod_timer(timer
, jiffies
+ timeout
);
1356 spin_unlock_irq(&tp
->lock
);
1359 static inline void rtl8169_delete_timer(struct net_device
*dev
)
1361 struct rtl8169_private
*tp
= netdev_priv(dev
);
1362 struct timer_list
*timer
= &tp
->timer
;
1364 if ((tp
->mac_version
<= RTL_GIGA_MAC_VER_01
) ||
1365 (tp
->phy_version
>= RTL_GIGA_PHY_VER_H
))
1368 del_timer_sync(timer
);
1371 static inline void rtl8169_request_timer(struct net_device
*dev
)
1373 struct rtl8169_private
*tp
= netdev_priv(dev
);
1374 struct timer_list
*timer
= &tp
->timer
;
1376 if ((tp
->mac_version
<= RTL_GIGA_MAC_VER_01
) ||
1377 (tp
->phy_version
>= RTL_GIGA_PHY_VER_H
))
1380 mod_timer(timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
1383 #ifdef CONFIG_NET_POLL_CONTROLLER
1385 * Polling 'interrupt' - used by things like netconsole to send skbs
1386 * without having to re-enable interrupts. It's not called while
1387 * the interrupt routine is executing.
1389 static void rtl8169_netpoll(struct net_device
*dev
)
1391 struct rtl8169_private
*tp
= netdev_priv(dev
);
1392 struct pci_dev
*pdev
= tp
->pci_dev
;
1394 disable_irq(pdev
->irq
);
1395 rtl8169_interrupt(pdev
->irq
, dev
);
1396 enable_irq(pdev
->irq
);
1400 static void rtl8169_release_board(struct pci_dev
*pdev
, struct net_device
*dev
,
1401 void __iomem
*ioaddr
)
1404 pci_release_regions(pdev
);
1405 pci_disable_device(pdev
);
1409 static void rtl8169_phy_reset(struct net_device
*dev
,
1410 struct rtl8169_private
*tp
)
1412 void __iomem
*ioaddr
= tp
->mmio_addr
;
1415 tp
->phy_reset_enable(ioaddr
);
1416 for (i
= 0; i
< 100; i
++) {
1417 if (!tp
->phy_reset_pending(ioaddr
))
1421 if (netif_msg_link(tp
))
1422 printk(KERN_ERR
"%s: PHY reset failed.\n", dev
->name
);
1425 static void rtl8169_init_phy(struct net_device
*dev
, struct rtl8169_private
*tp
)
1427 void __iomem
*ioaddr
= tp
->mmio_addr
;
1428 static int board_idx
= -1;
1434 rtl8169_hw_phy_config(dev
);
1436 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1439 pci_write_config_byte(tp
->pci_dev
, PCI_LATENCY_TIMER
, 0x40);
1441 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
1442 pci_write_config_byte(tp
->pci_dev
, PCI_CACHE_LINE_SIZE
, 0x08);
1444 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) {
1445 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1447 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1448 mdio_write(ioaddr
, 0x0b, 0x0000); //w 0x0b 15 0 0
1451 rtl8169_link_option(board_idx
, &autoneg
, &speed
, &duplex
);
1453 rtl8169_phy_reset(dev
, tp
);
1455 rtl8169_set_speed(dev
, autoneg
, speed
, duplex
);
1457 if ((RTL_R8(PHYstatus
) & TBI_Enable
) && netif_msg_link(tp
))
1458 printk(KERN_INFO PFX
"%s: TBI auto-negotiating\n", dev
->name
);
1461 static int rtl8169_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1463 struct rtl8169_private
*tp
= netdev_priv(dev
);
1464 struct mii_ioctl_data
*data
= if_mii(ifr
);
1466 if (!netif_running(dev
))
1471 data
->phy_id
= 32; /* Internal PHY */
1475 data
->val_out
= mdio_read(tp
->mmio_addr
, data
->reg_num
& 0x1f);
1479 if (!capable(CAP_NET_ADMIN
))
1481 mdio_write(tp
->mmio_addr
, data
->reg_num
& 0x1f, data
->val_in
);
1487 static const struct rtl_cfg_info
{
1488 void (*hw_start
)(struct net_device
*);
1489 unsigned int region
;
1493 } rtl_cfg_infos
[] = {
1495 .hw_start
= rtl_hw_start_8169
,
1498 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
1499 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
1500 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
1503 .hw_start
= rtl_hw_start_8168
,
1506 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
1507 TxErr
| TxOK
| RxOK
| RxErr
,
1508 .napi_event
= TxErr
| TxOK
| RxOK
| RxOverflow
1511 .hw_start
= rtl_hw_start_8101
,
1514 .intr_event
= SYSErr
| LinkChg
| RxOverflow
| PCSTimeout
|
1515 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
1516 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
1520 static int __devinit
1521 rtl8169_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1523 const struct rtl_cfg_info
*cfg
= rtl_cfg_infos
+ ent
->driver_data
;
1524 const unsigned int region
= cfg
->region
;
1525 struct rtl8169_private
*tp
;
1526 struct net_device
*dev
;
1527 void __iomem
*ioaddr
;
1528 unsigned int pm_cap
;
1531 if (netif_msg_drv(&debug
)) {
1532 printk(KERN_INFO
"%s Gigabit Ethernet driver %s loaded\n",
1533 MODULENAME
, RTL8169_VERSION
);
1536 dev
= alloc_etherdev(sizeof (*tp
));
1538 if (netif_msg_drv(&debug
))
1539 dev_err(&pdev
->dev
, "unable to alloc new ethernet\n");
1544 SET_MODULE_OWNER(dev
);
1545 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1546 tp
= netdev_priv(dev
);
1548 tp
->msg_enable
= netif_msg_init(debug
.msg_enable
, R8169_MSG_DEFAULT
);
1550 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1551 rc
= pci_enable_device(pdev
);
1553 if (netif_msg_probe(tp
))
1554 dev_err(&pdev
->dev
, "enable failure\n");
1555 goto err_out_free_dev_1
;
1558 rc
= pci_set_mwi(pdev
);
1560 goto err_out_disable_2
;
1562 /* save power state before pci_enable_device overwrites it */
1563 pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
1565 u16 pwr_command
, acpi_idle_state
;
1567 pci_read_config_word(pdev
, pm_cap
+ PCI_PM_CTRL
, &pwr_command
);
1568 acpi_idle_state
= pwr_command
& PCI_PM_CTRL_STATE_MASK
;
1570 if (netif_msg_probe(tp
)) {
1572 "PowerManagement capability not found.\n");
1576 /* make sure PCI base addr 1 is MMIO */
1577 if (!(pci_resource_flags(pdev
, region
) & IORESOURCE_MEM
)) {
1578 if (netif_msg_probe(tp
)) {
1580 "region #%d not an MMIO resource, aborting\n",
1587 /* check for weird/broken PCI region reporting */
1588 if (pci_resource_len(pdev
, region
) < R8169_REGS_SIZE
) {
1589 if (netif_msg_probe(tp
)) {
1591 "Invalid PCI region size(s), aborting\n");
1597 rc
= pci_request_regions(pdev
, MODULENAME
);
1599 if (netif_msg_probe(tp
))
1600 dev_err(&pdev
->dev
, "could not request regions.\n");
1604 tp
->cp_cmd
= PCIMulRW
| RxChkSum
;
1606 if ((sizeof(dma_addr_t
) > 4) &&
1607 !pci_set_dma_mask(pdev
, DMA_64BIT_MASK
) && use_dac
) {
1608 tp
->cp_cmd
|= PCIDAC
;
1609 dev
->features
|= NETIF_F_HIGHDMA
;
1611 rc
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
1613 if (netif_msg_probe(tp
)) {
1615 "DMA configuration failed.\n");
1617 goto err_out_free_res_4
;
1621 pci_set_master(pdev
);
1623 /* ioremap MMIO region */
1624 ioaddr
= ioremap(pci_resource_start(pdev
, region
), R8169_REGS_SIZE
);
1626 if (netif_msg_probe(tp
))
1627 dev_err(&pdev
->dev
, "cannot remap MMIO, aborting\n");
1629 goto err_out_free_res_4
;
1632 /* Unneeded ? Don't mess with Mrs. Murphy. */
1633 rtl8169_irq_mask_and_ack(ioaddr
);
1635 /* Soft reset the chip. */
1636 RTL_W8(ChipCmd
, CmdReset
);
1638 /* Check that the chip has finished the reset. */
1639 for (i
= 100; i
> 0; i
--) {
1640 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
1642 msleep_interruptible(1);
1645 /* Identify chip attached to board */
1646 rtl8169_get_mac_version(tp
, ioaddr
);
1647 rtl8169_get_phy_version(tp
, ioaddr
);
1649 rtl8169_print_mac_version(tp
);
1650 rtl8169_print_phy_version(tp
);
1652 for (i
= ARRAY_SIZE(rtl_chip_info
) - 1; i
>= 0; i
--) {
1653 if (tp
->mac_version
== rtl_chip_info
[i
].mac_version
)
1657 /* Unknown chip: assume array element #0, original RTL-8169 */
1658 if (netif_msg_probe(tp
)) {
1659 dev_printk(KERN_DEBUG
, &pdev
->dev
,
1660 "unknown chip version, assuming %s\n",
1661 rtl_chip_info
[0].name
);
1667 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
1668 RTL_W8(Config1
, RTL_R8(Config1
) | PMEnable
);
1669 RTL_W8(Config5
, RTL_R8(Config5
) & PMEStatus
);
1670 RTL_W8(Cfg9346
, Cfg9346_Lock
);
1672 if (RTL_R8(PHYstatus
) & TBI_Enable
) {
1673 tp
->set_speed
= rtl8169_set_speed_tbi
;
1674 tp
->get_settings
= rtl8169_gset_tbi
;
1675 tp
->phy_reset_enable
= rtl8169_tbi_reset_enable
;
1676 tp
->phy_reset_pending
= rtl8169_tbi_reset_pending
;
1677 tp
->link_ok
= rtl8169_tbi_link_ok
;
1679 tp
->phy_1000_ctrl_reg
= ADVERTISE_1000FULL
; /* Implied by TBI */
1681 tp
->set_speed
= rtl8169_set_speed_xmii
;
1682 tp
->get_settings
= rtl8169_gset_xmii
;
1683 tp
->phy_reset_enable
= rtl8169_xmii_reset_enable
;
1684 tp
->phy_reset_pending
= rtl8169_xmii_reset_pending
;
1685 tp
->link_ok
= rtl8169_xmii_link_ok
;
1687 dev
->do_ioctl
= rtl8169_ioctl
;
1690 /* Get MAC address. FIXME: read EEPROM */
1691 for (i
= 0; i
< MAC_ADDR_LEN
; i
++)
1692 dev
->dev_addr
[i
] = RTL_R8(MAC0
+ i
);
1693 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
1695 dev
->open
= rtl8169_open
;
1696 dev
->hard_start_xmit
= rtl8169_start_xmit
;
1697 dev
->get_stats
= rtl8169_get_stats
;
1698 SET_ETHTOOL_OPS(dev
, &rtl8169_ethtool_ops
);
1699 dev
->stop
= rtl8169_close
;
1700 dev
->tx_timeout
= rtl8169_tx_timeout
;
1701 dev
->set_multicast_list
= rtl_set_rx_mode
;
1702 dev
->watchdog_timeo
= RTL8169_TX_TIMEOUT
;
1703 dev
->irq
= pdev
->irq
;
1704 dev
->base_addr
= (unsigned long) ioaddr
;
1705 dev
->change_mtu
= rtl8169_change_mtu
;
1707 #ifdef CONFIG_R8169_NAPI
1708 dev
->poll
= rtl8169_poll
;
1709 dev
->weight
= R8169_NAPI_WEIGHT
;
1712 #ifdef CONFIG_R8169_VLAN
1713 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
1714 dev
->vlan_rx_register
= rtl8169_vlan_rx_register
;
1717 #ifdef CONFIG_NET_POLL_CONTROLLER
1718 dev
->poll_controller
= rtl8169_netpoll
;
1721 tp
->intr_mask
= 0xffff;
1723 tp
->mmio_addr
= ioaddr
;
1724 tp
->align
= cfg
->align
;
1725 tp
->hw_start
= cfg
->hw_start
;
1726 tp
->intr_event
= cfg
->intr_event
;
1727 tp
->napi_event
= cfg
->napi_event
;
1729 init_timer(&tp
->timer
);
1730 tp
->timer
.data
= (unsigned long) dev
;
1731 tp
->timer
.function
= rtl8169_phy_timer
;
1733 spin_lock_init(&tp
->lock
);
1735 rc
= register_netdev(dev
);
1737 goto err_out_unmap_5
;
1739 pci_set_drvdata(pdev
, dev
);
1741 if (netif_msg_probe(tp
)) {
1742 printk(KERN_INFO
"%s: %s at 0x%lx, "
1743 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1746 rtl_chip_info
[tp
->chipset
].name
,
1748 dev
->dev_addr
[0], dev
->dev_addr
[1],
1749 dev
->dev_addr
[2], dev
->dev_addr
[3],
1750 dev
->dev_addr
[4], dev
->dev_addr
[5], dev
->irq
);
1753 rtl8169_init_phy(dev
, tp
);
1761 pci_release_regions(pdev
);
1763 pci_clear_mwi(pdev
);
1765 pci_disable_device(pdev
);
1771 static void __devexit
1772 rtl8169_remove_one(struct pci_dev
*pdev
)
1774 struct net_device
*dev
= pci_get_drvdata(pdev
);
1775 struct rtl8169_private
*tp
= netdev_priv(dev
);
1777 assert(dev
!= NULL
);
1780 flush_scheduled_work();
1782 unregister_netdev(dev
);
1783 rtl8169_release_board(pdev
, dev
, tp
->mmio_addr
);
1784 pci_set_drvdata(pdev
, NULL
);
1787 static void rtl8169_set_rxbufsize(struct rtl8169_private
*tp
,
1788 struct net_device
*dev
)
1790 unsigned int mtu
= dev
->mtu
;
1792 tp
->rx_buf_sz
= (mtu
> RX_BUF_SIZE
) ? mtu
+ ETH_HLEN
+ 8 : RX_BUF_SIZE
;
1795 static int rtl8169_open(struct net_device
*dev
)
1797 struct rtl8169_private
*tp
= netdev_priv(dev
);
1798 struct pci_dev
*pdev
= tp
->pci_dev
;
1799 int retval
= -ENOMEM
;
1802 rtl8169_set_rxbufsize(tp
, dev
);
1805 * Rx and Tx desscriptors needs 256 bytes alignment.
1806 * pci_alloc_consistent provides more.
1808 tp
->TxDescArray
= pci_alloc_consistent(pdev
, R8169_TX_RING_BYTES
,
1810 if (!tp
->TxDescArray
)
1813 tp
->RxDescArray
= pci_alloc_consistent(pdev
, R8169_RX_RING_BYTES
,
1815 if (!tp
->RxDescArray
)
1818 retval
= rtl8169_init_ring(dev
);
1822 INIT_DELAYED_WORK(&tp
->task
, NULL
);
1826 retval
= request_irq(dev
->irq
, rtl8169_interrupt
, IRQF_SHARED
,
1829 goto err_release_ring_2
;
1833 rtl8169_request_timer(dev
);
1835 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
1840 rtl8169_rx_clear(tp
);
1842 pci_free_consistent(pdev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
1845 pci_free_consistent(pdev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
1850 static void rtl8169_hw_reset(void __iomem
*ioaddr
)
1852 /* Disable interrupts */
1853 rtl8169_irq_mask_and_ack(ioaddr
);
1855 /* Reset the chipset */
1856 RTL_W8(ChipCmd
, CmdReset
);
1862 static void rtl_set_rx_tx_config_registers(struct rtl8169_private
*tp
)
1864 void __iomem
*ioaddr
= tp
->mmio_addr
;
1865 u32 cfg
= rtl8169_rx_config
;
1867 cfg
|= (RTL_R32(RxConfig
) & rtl_chip_info
[tp
->chipset
].RxConfigMask
);
1868 RTL_W32(RxConfig
, cfg
);
1870 /* Set DMA burst size and Interframe Gap Time */
1871 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
1872 (InterFrameGap
<< TxInterFrameGapShift
));
1875 static void rtl_hw_start(struct net_device
*dev
)
1877 struct rtl8169_private
*tp
= netdev_priv(dev
);
1878 void __iomem
*ioaddr
= tp
->mmio_addr
;
1881 /* Soft reset the chip. */
1882 RTL_W8(ChipCmd
, CmdReset
);
1884 /* Check that the chip has finished the reset. */
1885 for (i
= 100; i
> 0; i
--) {
1886 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
1888 msleep_interruptible(1);
1893 netif_start_queue(dev
);
1897 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private
*tp
,
1898 void __iomem
*ioaddr
)
1901 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1902 * register to be written before TxDescAddrLow to work.
1903 * Switching from MMIO to I/O access fixes the issue as well.
1905 RTL_W32(TxDescStartAddrHigh
, ((u64
) tp
->TxPhyAddr
) >> 32);
1906 RTL_W32(TxDescStartAddrLow
, ((u64
) tp
->TxPhyAddr
) & DMA_32BIT_MASK
);
1907 RTL_W32(RxDescAddrHigh
, ((u64
) tp
->RxPhyAddr
) >> 32);
1908 RTL_W32(RxDescAddrLow
, ((u64
) tp
->RxPhyAddr
) & DMA_32BIT_MASK
);
1911 static u16
rtl_rw_cpluscmd(void __iomem
*ioaddr
)
1915 cmd
= RTL_R16(CPlusCmd
);
1916 RTL_W16(CPlusCmd
, cmd
);
1920 static void rtl_set_rx_max_size(void __iomem
*ioaddr
)
1922 /* Low hurts. Let's disable the filtering. */
1923 RTL_W16(RxMaxSize
, 16383);
1926 static void rtl8169_set_magic_reg(void __iomem
*ioaddr
, unsigned mac_version
)
1933 { RTL_GIGA_MAC_VER_05
, PCI_Clock_33MHz
, 0x000fff00 }, // 8110SCd
1934 { RTL_GIGA_MAC_VER_05
, PCI_Clock_66MHz
, 0x000fffff },
1935 { RTL_GIGA_MAC_VER_06
, PCI_Clock_33MHz
, 0x00ffff00 }, // 8110SCe
1936 { RTL_GIGA_MAC_VER_06
, PCI_Clock_66MHz
, 0x00ffffff }
1941 clk
= RTL_R8(Config2
) & PCI_Clock_66MHz
;
1942 for (i
= 0; i
< ARRAY_SIZE(cfg2_info
); i
++) {
1943 if ((p
->mac_version
== mac_version
) && (p
->clk
== clk
)) {
1944 RTL_W32(0x7c, p
->val
);
1950 static void rtl_hw_start_8169(struct net_device
*dev
)
1952 struct rtl8169_private
*tp
= netdev_priv(dev
);
1953 void __iomem
*ioaddr
= tp
->mmio_addr
;
1954 struct pci_dev
*pdev
= tp
->pci_dev
;
1956 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
) {
1957 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | PCIMulRW
);
1958 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, 0x08);
1961 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
1962 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_01
) ||
1963 (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
1964 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
) ||
1965 (tp
->mac_version
== RTL_GIGA_MAC_VER_04
))
1966 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
1968 RTL_W8(EarlyTxThres
, EarlyTxThld
);
1970 rtl_set_rx_max_size(ioaddr
);
1972 rtl_set_rx_tx_config_registers(tp
);
1974 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
1976 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
1977 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
)) {
1978 dprintk(KERN_INFO PFX
"Set MAC Reg C+CR Offset 0xE0. "
1979 "Bit-3 and bit-14 MUST be 1\n");
1980 tp
->cp_cmd
|= (1 << 14);
1983 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
1985 rtl8169_set_magic_reg(ioaddr
, tp
->mac_version
);
1988 * Undocumented corner. Supposedly:
1989 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1991 RTL_W16(IntrMitigate
, 0x0000);
1993 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
1995 RTL_W8(Cfg9346
, Cfg9346_Lock
);
1997 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2000 RTL_W32(RxMissed
, 0);
2002 rtl_set_rx_mode(dev
);
2004 /* no early-rx interrupts */
2005 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
2007 /* Enable all known interrupts by setting the interrupt mask. */
2008 RTL_W16(IntrMask
, tp
->intr_event
);
2010 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2013 static void rtl_hw_start_8168(struct net_device
*dev
)
2015 struct rtl8169_private
*tp
= netdev_priv(dev
);
2016 void __iomem
*ioaddr
= tp
->mmio_addr
;
2017 struct pci_dev
*pdev
= tp
->pci_dev
;
2020 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2022 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2024 rtl_set_rx_max_size(ioaddr
);
2026 rtl_set_rx_tx_config_registers(tp
);
2028 tp
->cp_cmd
|= RTL_R16(CPlusCmd
) | PktCntrDisable
| INTT_1
;
2030 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2032 /* Tx performance tweak. */
2033 pci_read_config_byte(pdev
, 0x69, &ctl
);
2034 ctl
= (ctl
& ~0x70) | 0x50;
2035 pci_write_config_byte(pdev
, 0x69, ctl
);
2037 RTL_W16(IntrMitigate
, 0x5151);
2039 /* Work around for RxFIFO overflow. */
2040 if (tp
->mac_version
== RTL_GIGA_MAC_VER_11
) {
2041 tp
->intr_event
|= RxFIFOOver
| PCSTimeout
;
2042 tp
->intr_event
&= ~RxOverflow
;
2045 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
2047 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2051 RTL_W32(RxMissed
, 0);
2053 rtl_set_rx_mode(dev
);
2055 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2057 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
2059 RTL_W16(IntrMask
, tp
->intr_event
);
2062 static void rtl_hw_start_8101(struct net_device
*dev
)
2064 struct rtl8169_private
*tp
= netdev_priv(dev
);
2065 void __iomem
*ioaddr
= tp
->mmio_addr
;
2066 struct pci_dev
*pdev
= tp
->pci_dev
;
2068 if (tp
->mac_version
== RTL_GIGA_MAC_VER_13
) {
2069 pci_write_config_word(pdev
, 0x68, 0x00);
2070 pci_write_config_word(pdev
, 0x69, 0x08);
2073 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2075 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2077 rtl_set_rx_max_size(ioaddr
);
2079 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
2081 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2083 RTL_W16(IntrMitigate
, 0x0000);
2085 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
2087 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2088 rtl_set_rx_tx_config_registers(tp
);
2090 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2094 RTL_W32(RxMissed
, 0);
2096 rtl_set_rx_mode(dev
);
2098 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2100 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
2102 RTL_W16(IntrMask
, tp
->intr_event
);
2105 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
)
2107 struct rtl8169_private
*tp
= netdev_priv(dev
);
2110 if (new_mtu
< ETH_ZLEN
|| new_mtu
> SafeMtu
)
2115 if (!netif_running(dev
))
2120 rtl8169_set_rxbufsize(tp
, dev
);
2122 ret
= rtl8169_init_ring(dev
);
2126 netif_poll_enable(dev
);
2130 rtl8169_request_timer(dev
);
2136 static inline void rtl8169_make_unusable_by_asic(struct RxDesc
*desc
)
2138 desc
->addr
= 0x0badbadbadbadbadull
;
2139 desc
->opts1
&= ~cpu_to_le32(DescOwn
| RsvdMask
);
2142 static void rtl8169_free_rx_skb(struct rtl8169_private
*tp
,
2143 struct sk_buff
**sk_buff
, struct RxDesc
*desc
)
2145 struct pci_dev
*pdev
= tp
->pci_dev
;
2147 pci_unmap_single(pdev
, le64_to_cpu(desc
->addr
), tp
->rx_buf_sz
,
2148 PCI_DMA_FROMDEVICE
);
2149 dev_kfree_skb(*sk_buff
);
2151 rtl8169_make_unusable_by_asic(desc
);
2154 static inline void rtl8169_mark_to_asic(struct RxDesc
*desc
, u32 rx_buf_sz
)
2156 u32 eor
= le32_to_cpu(desc
->opts1
) & RingEnd
;
2158 desc
->opts1
= cpu_to_le32(DescOwn
| eor
| rx_buf_sz
);
2161 static inline void rtl8169_map_to_asic(struct RxDesc
*desc
, dma_addr_t mapping
,
2164 desc
->addr
= cpu_to_le64(mapping
);
2166 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
2169 static struct sk_buff
*rtl8169_alloc_rx_skb(struct pci_dev
*pdev
,
2170 struct net_device
*dev
,
2171 struct RxDesc
*desc
, int rx_buf_sz
,
2174 struct sk_buff
*skb
;
2177 skb
= netdev_alloc_skb(dev
, rx_buf_sz
+ align
);
2181 skb_reserve(skb
, (align
- 1) & (unsigned long)skb
->data
);
2183 mapping
= pci_map_single(pdev
, skb
->data
, rx_buf_sz
,
2184 PCI_DMA_FROMDEVICE
);
2186 rtl8169_map_to_asic(desc
, mapping
, rx_buf_sz
);
2191 rtl8169_make_unusable_by_asic(desc
);
2195 static void rtl8169_rx_clear(struct rtl8169_private
*tp
)
2199 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
2200 if (tp
->Rx_skbuff
[i
]) {
2201 rtl8169_free_rx_skb(tp
, tp
->Rx_skbuff
+ i
,
2202 tp
->RxDescArray
+ i
);
2207 static u32
rtl8169_rx_fill(struct rtl8169_private
*tp
, struct net_device
*dev
,
2212 for (cur
= start
; end
- cur
!= 0; cur
++) {
2213 struct sk_buff
*skb
;
2214 unsigned int i
= cur
% NUM_RX_DESC
;
2216 WARN_ON((s32
)(end
- cur
) < 0);
2218 if (tp
->Rx_skbuff
[i
])
2221 skb
= rtl8169_alloc_rx_skb(tp
->pci_dev
, dev
,
2222 tp
->RxDescArray
+ i
,
2223 tp
->rx_buf_sz
, tp
->align
);
2227 tp
->Rx_skbuff
[i
] = skb
;
2232 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc
*desc
)
2234 desc
->opts1
|= cpu_to_le32(RingEnd
);
2237 static void rtl8169_init_ring_indexes(struct rtl8169_private
*tp
)
2239 tp
->dirty_tx
= tp
->dirty_rx
= tp
->cur_tx
= tp
->cur_rx
= 0;
2242 static int rtl8169_init_ring(struct net_device
*dev
)
2244 struct rtl8169_private
*tp
= netdev_priv(dev
);
2246 rtl8169_init_ring_indexes(tp
);
2248 memset(tp
->tx_skb
, 0x0, NUM_TX_DESC
* sizeof(struct ring_info
));
2249 memset(tp
->Rx_skbuff
, 0x0, NUM_RX_DESC
* sizeof(struct sk_buff
*));
2251 if (rtl8169_rx_fill(tp
, dev
, 0, NUM_RX_DESC
) != NUM_RX_DESC
)
2254 rtl8169_mark_as_last_descriptor(tp
->RxDescArray
+ NUM_RX_DESC
- 1);
2259 rtl8169_rx_clear(tp
);
2263 static void rtl8169_unmap_tx_skb(struct pci_dev
*pdev
, struct ring_info
*tx_skb
,
2264 struct TxDesc
*desc
)
2266 unsigned int len
= tx_skb
->len
;
2268 pci_unmap_single(pdev
, le64_to_cpu(desc
->addr
), len
, PCI_DMA_TODEVICE
);
2275 static void rtl8169_tx_clear(struct rtl8169_private
*tp
)
2279 for (i
= tp
->dirty_tx
; i
< tp
->dirty_tx
+ NUM_TX_DESC
; i
++) {
2280 unsigned int entry
= i
% NUM_TX_DESC
;
2281 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
2282 unsigned int len
= tx_skb
->len
;
2285 struct sk_buff
*skb
= tx_skb
->skb
;
2287 rtl8169_unmap_tx_skb(tp
->pci_dev
, tx_skb
,
2288 tp
->TxDescArray
+ entry
);
2293 tp
->stats
.tx_dropped
++;
2296 tp
->cur_tx
= tp
->dirty_tx
= 0;
2299 static void rtl8169_schedule_work(struct net_device
*dev
, work_func_t task
)
2301 struct rtl8169_private
*tp
= netdev_priv(dev
);
2303 PREPARE_DELAYED_WORK(&tp
->task
, task
);
2304 schedule_delayed_work(&tp
->task
, 4);
2307 static void rtl8169_wait_for_quiescence(struct net_device
*dev
)
2309 struct rtl8169_private
*tp
= netdev_priv(dev
);
2310 void __iomem
*ioaddr
= tp
->mmio_addr
;
2312 synchronize_irq(dev
->irq
);
2314 /* Wait for any pending NAPI task to complete */
2315 netif_poll_disable(dev
);
2317 rtl8169_irq_mask_and_ack(ioaddr
);
2319 netif_poll_enable(dev
);
2322 static void rtl8169_reinit_task(struct work_struct
*work
)
2324 struct rtl8169_private
*tp
=
2325 container_of(work
, struct rtl8169_private
, task
.work
);
2326 struct net_device
*dev
= tp
->dev
;
2331 if (!netif_running(dev
))
2334 rtl8169_wait_for_quiescence(dev
);
2337 ret
= rtl8169_open(dev
);
2338 if (unlikely(ret
< 0)) {
2339 if (net_ratelimit()) {
2340 struct rtl8169_private
*tp
= netdev_priv(dev
);
2342 if (netif_msg_drv(tp
)) {
2344 "%s: reinit failure (status = %d)."
2345 " Rescheduling.\n", dev
->name
, ret
);
2348 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
2355 static void rtl8169_reset_task(struct work_struct
*work
)
2357 struct rtl8169_private
*tp
=
2358 container_of(work
, struct rtl8169_private
, task
.work
);
2359 struct net_device
*dev
= tp
->dev
;
2363 if (!netif_running(dev
))
2366 rtl8169_wait_for_quiescence(dev
);
2368 rtl8169_rx_interrupt(dev
, tp
, tp
->mmio_addr
);
2369 rtl8169_tx_clear(tp
);
2371 if (tp
->dirty_rx
== tp
->cur_rx
) {
2372 rtl8169_init_ring_indexes(tp
);
2374 netif_wake_queue(dev
);
2376 if (net_ratelimit()) {
2377 struct rtl8169_private
*tp
= netdev_priv(dev
);
2379 if (netif_msg_intr(tp
)) {
2380 printk(PFX KERN_EMERG
2381 "%s: Rx buffers shortage\n", dev
->name
);
2384 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
2391 static void rtl8169_tx_timeout(struct net_device
*dev
)
2393 struct rtl8169_private
*tp
= netdev_priv(dev
);
2395 rtl8169_hw_reset(tp
->mmio_addr
);
2397 /* Let's wait a bit while any (async) irq lands on */
2398 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
2401 static int rtl8169_xmit_frags(struct rtl8169_private
*tp
, struct sk_buff
*skb
,
2404 struct skb_shared_info
*info
= skb_shinfo(skb
);
2405 unsigned int cur_frag
, entry
;
2409 for (cur_frag
= 0; cur_frag
< info
->nr_frags
; cur_frag
++) {
2410 skb_frag_t
*frag
= info
->frags
+ cur_frag
;
2415 entry
= (entry
+ 1) % NUM_TX_DESC
;
2417 txd
= tp
->TxDescArray
+ entry
;
2419 addr
= ((void *) page_address(frag
->page
)) + frag
->page_offset
;
2420 mapping
= pci_map_single(tp
->pci_dev
, addr
, len
, PCI_DMA_TODEVICE
);
2422 /* anti gcc 2.95.3 bugware (sic) */
2423 status
= opts1
| len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
2425 txd
->opts1
= cpu_to_le32(status
);
2426 txd
->addr
= cpu_to_le64(mapping
);
2428 tp
->tx_skb
[entry
].len
= len
;
2432 tp
->tx_skb
[entry
].skb
= skb
;
2433 txd
->opts1
|= cpu_to_le32(LastFrag
);
2439 static inline u32
rtl8169_tso_csum(struct sk_buff
*skb
, struct net_device
*dev
)
2441 if (dev
->features
& NETIF_F_TSO
) {
2442 u32 mss
= skb_shinfo(skb
)->gso_size
;
2445 return LargeSend
| ((mss
& MSSMask
) << MSSShift
);
2447 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
2448 const struct iphdr
*ip
= ip_hdr(skb
);
2450 if (ip
->protocol
== IPPROTO_TCP
)
2451 return IPCS
| TCPCS
;
2452 else if (ip
->protocol
== IPPROTO_UDP
)
2453 return IPCS
| UDPCS
;
2454 WARN_ON(1); /* we need a WARN() */
2459 static int rtl8169_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
2461 struct rtl8169_private
*tp
= netdev_priv(dev
);
2462 unsigned int frags
, entry
= tp
->cur_tx
% NUM_TX_DESC
;
2463 struct TxDesc
*txd
= tp
->TxDescArray
+ entry
;
2464 void __iomem
*ioaddr
= tp
->mmio_addr
;
2468 int ret
= NETDEV_TX_OK
;
2470 if (unlikely(TX_BUFFS_AVAIL(tp
) < skb_shinfo(skb
)->nr_frags
)) {
2471 if (netif_msg_drv(tp
)) {
2473 "%s: BUG! Tx Ring full when queue awake!\n",
2479 if (unlikely(le32_to_cpu(txd
->opts1
) & DescOwn
))
2482 opts1
= DescOwn
| rtl8169_tso_csum(skb
, dev
);
2484 frags
= rtl8169_xmit_frags(tp
, skb
, opts1
);
2486 len
= skb_headlen(skb
);
2491 if (unlikely(len
< ETH_ZLEN
)) {
2492 if (skb_padto(skb
, ETH_ZLEN
))
2493 goto err_update_stats
;
2497 opts1
|= FirstFrag
| LastFrag
;
2498 tp
->tx_skb
[entry
].skb
= skb
;
2501 mapping
= pci_map_single(tp
->pci_dev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
2503 tp
->tx_skb
[entry
].len
= len
;
2504 txd
->addr
= cpu_to_le64(mapping
);
2505 txd
->opts2
= cpu_to_le32(rtl8169_tx_vlan_tag(tp
, skb
));
2509 /* anti gcc 2.95.3 bugware (sic) */
2510 status
= opts1
| len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
2511 txd
->opts1
= cpu_to_le32(status
);
2513 dev
->trans_start
= jiffies
;
2515 tp
->cur_tx
+= frags
+ 1;
2519 RTL_W8(TxPoll
, 0x40); /* set polling bit */
2521 if (TX_BUFFS_AVAIL(tp
) < MAX_SKB_FRAGS
) {
2522 netif_stop_queue(dev
);
2524 if (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)
2525 netif_wake_queue(dev
);
2532 netif_stop_queue(dev
);
2533 ret
= NETDEV_TX_BUSY
;
2535 tp
->stats
.tx_dropped
++;
2539 static void rtl8169_pcierr_interrupt(struct net_device
*dev
)
2541 struct rtl8169_private
*tp
= netdev_priv(dev
);
2542 struct pci_dev
*pdev
= tp
->pci_dev
;
2543 void __iomem
*ioaddr
= tp
->mmio_addr
;
2544 u16 pci_status
, pci_cmd
;
2546 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
2547 pci_read_config_word(pdev
, PCI_STATUS
, &pci_status
);
2549 if (netif_msg_intr(tp
)) {
2551 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2552 dev
->name
, pci_cmd
, pci_status
);
2556 * The recovery sequence below admits a very elaborated explanation:
2557 * - it seems to work;
2558 * - I did not see what else could be done;
2559 * - it makes iop3xx happy.
2561 * Feel free to adjust to your needs.
2563 if (pdev
->broken_parity_status
)
2564 pci_cmd
&= ~PCI_COMMAND_PARITY
;
2566 pci_cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
;
2568 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
2570 pci_write_config_word(pdev
, PCI_STATUS
,
2571 pci_status
& (PCI_STATUS_DETECTED_PARITY
|
2572 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_REC_MASTER_ABORT
|
2573 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_SIG_TARGET_ABORT
));
2575 /* The infamous DAC f*ckup only happens at boot time */
2576 if ((tp
->cp_cmd
& PCIDAC
) && !tp
->dirty_rx
&& !tp
->cur_rx
) {
2577 if (netif_msg_intr(tp
))
2578 printk(KERN_INFO
"%s: disabling PCI DAC.\n", dev
->name
);
2579 tp
->cp_cmd
&= ~PCIDAC
;
2580 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2581 dev
->features
&= ~NETIF_F_HIGHDMA
;
2584 rtl8169_hw_reset(ioaddr
);
2586 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
2590 rtl8169_tx_interrupt(struct net_device
*dev
, struct rtl8169_private
*tp
,
2591 void __iomem
*ioaddr
)
2593 unsigned int dirty_tx
, tx_left
;
2595 assert(dev
!= NULL
);
2597 assert(ioaddr
!= NULL
);
2599 dirty_tx
= tp
->dirty_tx
;
2601 tx_left
= tp
->cur_tx
- dirty_tx
;
2603 while (tx_left
> 0) {
2604 unsigned int entry
= dirty_tx
% NUM_TX_DESC
;
2605 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
2606 u32 len
= tx_skb
->len
;
2610 status
= le32_to_cpu(tp
->TxDescArray
[entry
].opts1
);
2611 if (status
& DescOwn
)
2614 tp
->stats
.tx_bytes
+= len
;
2615 tp
->stats
.tx_packets
++;
2617 rtl8169_unmap_tx_skb(tp
->pci_dev
, tx_skb
, tp
->TxDescArray
+ entry
);
2619 if (status
& LastFrag
) {
2620 dev_kfree_skb_irq(tx_skb
->skb
);
2627 if (tp
->dirty_tx
!= dirty_tx
) {
2628 tp
->dirty_tx
= dirty_tx
;
2630 if (netif_queue_stopped(dev
) &&
2631 (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)) {
2632 netif_wake_queue(dev
);
2637 static inline int rtl8169_fragmented_frame(u32 status
)
2639 return (status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
);
2642 static inline void rtl8169_rx_csum(struct sk_buff
*skb
, struct RxDesc
*desc
)
2644 u32 opts1
= le32_to_cpu(desc
->opts1
);
2645 u32 status
= opts1
& RxProtoMask
;
2647 if (((status
== RxProtoTCP
) && !(opts1
& TCPFail
)) ||
2648 ((status
== RxProtoUDP
) && !(opts1
& UDPFail
)) ||
2649 ((status
== RxProtoIP
) && !(opts1
& IPFail
)))
2650 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2652 skb
->ip_summed
= CHECKSUM_NONE
;
2655 static inline bool rtl8169_try_rx_copy(struct sk_buff
**sk_buff
, int pkt_size
,
2656 struct pci_dev
*pdev
, dma_addr_t addr
)
2658 struct sk_buff
*skb
;
2661 if (pkt_size
>= rx_copybreak
)
2664 skb
= dev_alloc_skb(pkt_size
+ NET_IP_ALIGN
);
2668 pci_dma_sync_single_for_cpu(pdev
, addr
, pkt_size
, PCI_DMA_FROMDEVICE
);
2669 skb_reserve(skb
, NET_IP_ALIGN
);
2670 skb_copy_from_linear_data(*sk_buff
, skb
->data
, pkt_size
);
2678 rtl8169_rx_interrupt(struct net_device
*dev
, struct rtl8169_private
*tp
,
2679 void __iomem
*ioaddr
)
2681 unsigned int cur_rx
, rx_left
;
2682 unsigned int delta
, count
;
2684 assert(dev
!= NULL
);
2686 assert(ioaddr
!= NULL
);
2688 cur_rx
= tp
->cur_rx
;
2689 rx_left
= NUM_RX_DESC
+ tp
->dirty_rx
- cur_rx
;
2690 rx_left
= rtl8169_rx_quota(rx_left
, (u32
) dev
->quota
);
2692 for (; rx_left
> 0; rx_left
--, cur_rx
++) {
2693 unsigned int entry
= cur_rx
% NUM_RX_DESC
;
2694 struct RxDesc
*desc
= tp
->RxDescArray
+ entry
;
2698 status
= le32_to_cpu(desc
->opts1
);
2700 if (status
& DescOwn
)
2702 if (unlikely(status
& RxRES
)) {
2703 if (netif_msg_rx_err(tp
)) {
2705 "%s: Rx ERROR. status = %08x\n",
2708 tp
->stats
.rx_errors
++;
2709 if (status
& (RxRWT
| RxRUNT
))
2710 tp
->stats
.rx_length_errors
++;
2712 tp
->stats
.rx_crc_errors
++;
2713 if (status
& RxFOVF
) {
2714 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
2715 tp
->stats
.rx_fifo_errors
++;
2717 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
2719 struct sk_buff
*skb
= tp
->Rx_skbuff
[entry
];
2720 dma_addr_t addr
= le64_to_cpu(desc
->addr
);
2721 int pkt_size
= (status
& 0x00001FFF) - 4;
2722 struct pci_dev
*pdev
= tp
->pci_dev
;
2725 * The driver does not support incoming fragmented
2726 * frames. They are seen as a symptom of over-mtu
2729 if (unlikely(rtl8169_fragmented_frame(status
))) {
2730 tp
->stats
.rx_dropped
++;
2731 tp
->stats
.rx_length_errors
++;
2732 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
2736 rtl8169_rx_csum(skb
, desc
);
2738 if (rtl8169_try_rx_copy(&skb
, pkt_size
, pdev
, addr
)) {
2739 pci_dma_sync_single_for_device(pdev
, addr
,
2740 pkt_size
, PCI_DMA_FROMDEVICE
);
2741 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
2743 pci_unmap_single(pdev
, addr
, pkt_size
,
2744 PCI_DMA_FROMDEVICE
);
2745 tp
->Rx_skbuff
[entry
] = NULL
;
2748 skb_put(skb
, pkt_size
);
2749 skb
->protocol
= eth_type_trans(skb
, dev
);
2751 if (rtl8169_rx_vlan_skb(tp
, desc
, skb
) < 0)
2752 rtl8169_rx_skb(skb
);
2754 dev
->last_rx
= jiffies
;
2755 tp
->stats
.rx_bytes
+= pkt_size
;
2756 tp
->stats
.rx_packets
++;
2759 /* Work around for AMD plateform. */
2760 if ((desc
->opts2
& 0xfffe000) &&
2761 (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)) {
2767 count
= cur_rx
- tp
->cur_rx
;
2768 tp
->cur_rx
= cur_rx
;
2770 delta
= rtl8169_rx_fill(tp
, dev
, tp
->dirty_rx
, tp
->cur_rx
);
2771 if (!delta
&& count
&& netif_msg_intr(tp
))
2772 printk(KERN_INFO
"%s: no Rx buffer allocated\n", dev
->name
);
2773 tp
->dirty_rx
+= delta
;
2776 * FIXME: until there is periodic timer to try and refill the ring,
2777 * a temporary shortage may definitely kill the Rx process.
2778 * - disable the asic to try and avoid an overflow and kick it again
2780 * - how do others driver handle this condition (Uh oh...).
2782 if ((tp
->dirty_rx
+ NUM_RX_DESC
== tp
->cur_rx
) && netif_msg_intr(tp
))
2783 printk(KERN_EMERG
"%s: Rx buffers exhausted\n", dev
->name
);
2788 /* The interrupt handler does all of the Rx thread work and cleans up after the Tx thread. */
2790 rtl8169_interrupt(int irq
, void *dev_instance
)
2792 struct net_device
*dev
= (struct net_device
*) dev_instance
;
2793 struct rtl8169_private
*tp
= netdev_priv(dev
);
2794 int boguscnt
= max_interrupt_work
;
2795 void __iomem
*ioaddr
= tp
->mmio_addr
;
2800 status
= RTL_R16(IntrStatus
);
2802 /* hotplug/major error/no more work/shared irq */
2803 if ((status
== 0xFFFF) || !status
)
2808 if (unlikely(!netif_running(dev
))) {
2809 rtl8169_asic_down(ioaddr
);
2813 status
&= tp
->intr_mask
;
2815 (status
& RxFIFOOver
) ? (status
| RxOverflow
) : status
);
2817 if (!(status
& tp
->intr_event
))
2820 /* Work around for rx fifo overflow */
2821 if (unlikely(status
& RxFIFOOver
) &&
2822 (tp
->mac_version
== RTL_GIGA_MAC_VER_11
)) {
2823 netif_stop_queue(dev
);
2824 rtl8169_tx_timeout(dev
);
2828 if (unlikely(status
& SYSErr
)) {
2829 rtl8169_pcierr_interrupt(dev
);
2833 if (status
& LinkChg
)
2834 rtl8169_check_link_status(dev
, tp
, ioaddr
);
2836 #ifdef CONFIG_R8169_NAPI
2837 RTL_W16(IntrMask
, tp
->intr_event
& ~tp
->napi_event
);
2838 tp
->intr_mask
= ~tp
->napi_event
;
2840 if (likely(netif_rx_schedule_prep(dev
)))
2841 __netif_rx_schedule(dev
);
2842 else if (netif_msg_intr(tp
)) {
2843 printk(KERN_INFO
"%s: interrupt %04x taken in poll\n",
2849 if (status
& (RxOK
| RxOverflow
| RxFIFOOver
)) {
2850 rtl8169_rx_interrupt(dev
, tp
, ioaddr
);
2853 if (status
& (TxOK
| TxErr
))
2854 rtl8169_tx_interrupt(dev
, tp
, ioaddr
);
2858 } while (boguscnt
> 0);
2860 if (boguscnt
<= 0) {
2861 if (netif_msg_intr(tp
) && net_ratelimit() ) {
2863 "%s: Too much work at interrupt!\n", dev
->name
);
2865 /* Clear all interrupt sources. */
2866 RTL_W16(IntrStatus
, 0xffff);
2869 return IRQ_RETVAL(handled
);
2872 #ifdef CONFIG_R8169_NAPI
2873 static int rtl8169_poll(struct net_device
*dev
, int *budget
)
2875 unsigned int work_done
, work_to_do
= min(*budget
, dev
->quota
);
2876 struct rtl8169_private
*tp
= netdev_priv(dev
);
2877 void __iomem
*ioaddr
= tp
->mmio_addr
;
2879 work_done
= rtl8169_rx_interrupt(dev
, tp
, ioaddr
);
2880 rtl8169_tx_interrupt(dev
, tp
, ioaddr
);
2882 *budget
-= work_done
;
2883 dev
->quota
-= work_done
;
2885 if (work_done
< work_to_do
) {
2886 netif_rx_complete(dev
);
2887 tp
->intr_mask
= 0xffff;
2889 * 20040426: the barrier is not strictly required but the
2890 * behavior of the irq handler could be less predictable
2891 * without it. Btw, the lack of flush for the posted pci
2892 * write is safe - FR
2895 RTL_W16(IntrMask
, tp
->intr_event
);
2898 return (work_done
>= work_to_do
);
2902 static void rtl8169_down(struct net_device
*dev
)
2904 struct rtl8169_private
*tp
= netdev_priv(dev
);
2905 void __iomem
*ioaddr
= tp
->mmio_addr
;
2906 unsigned int poll_locked
= 0;
2907 unsigned int intrmask
;
2909 rtl8169_delete_timer(dev
);
2911 netif_stop_queue(dev
);
2914 spin_lock_irq(&tp
->lock
);
2916 rtl8169_asic_down(ioaddr
);
2918 /* Update the error counts. */
2919 tp
->stats
.rx_missed_errors
+= RTL_R32(RxMissed
);
2920 RTL_W32(RxMissed
, 0);
2922 spin_unlock_irq(&tp
->lock
);
2924 synchronize_irq(dev
->irq
);
2927 netif_poll_disable(dev
);
2931 /* Give a racing hard_start_xmit a few cycles to complete. */
2932 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
2935 * And now for the 50k$ question: are IRQ disabled or not ?
2937 * Two paths lead here:
2939 * -> netif_running() is available to sync the current code and the
2940 * IRQ handler. See rtl8169_interrupt for details.
2941 * 2) dev->change_mtu
2942 * -> rtl8169_poll can not be issued again and re-enable the
2943 * interruptions. Let's simply issue the IRQ down sequence again.
2945 * No loop if hotpluged or major error (0xffff).
2947 intrmask
= RTL_R16(IntrMask
);
2948 if (intrmask
&& (intrmask
!= 0xffff))
2951 rtl8169_tx_clear(tp
);
2953 rtl8169_rx_clear(tp
);
2956 static int rtl8169_close(struct net_device
*dev
)
2958 struct rtl8169_private
*tp
= netdev_priv(dev
);
2959 struct pci_dev
*pdev
= tp
->pci_dev
;
2963 free_irq(dev
->irq
, dev
);
2965 netif_poll_enable(dev
);
2967 pci_free_consistent(pdev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
2969 pci_free_consistent(pdev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
2971 tp
->TxDescArray
= NULL
;
2972 tp
->RxDescArray
= NULL
;
2977 static void rtl_set_rx_mode(struct net_device
*dev
)
2979 struct rtl8169_private
*tp
= netdev_priv(dev
);
2980 void __iomem
*ioaddr
= tp
->mmio_addr
;
2981 unsigned long flags
;
2982 u32 mc_filter
[2]; /* Multicast hash filter */
2986 if (dev
->flags
& IFF_PROMISC
) {
2987 /* Unconditionally log net taps. */
2988 if (netif_msg_link(tp
)) {
2989 printk(KERN_NOTICE
"%s: Promiscuous mode enabled.\n",
2993 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
|
2995 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
2996 } else if ((dev
->mc_count
> multicast_filter_limit
)
2997 || (dev
->flags
& IFF_ALLMULTI
)) {
2998 /* Too many to filter perfectly -- accept all multicasts. */
2999 rx_mode
= AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
;
3000 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
3002 struct dev_mc_list
*mclist
;
3003 rx_mode
= AcceptBroadcast
| AcceptMyPhys
;
3004 mc_filter
[1] = mc_filter
[0] = 0;
3005 for (i
= 0, mclist
= dev
->mc_list
; mclist
&& i
< dev
->mc_count
;
3006 i
++, mclist
= mclist
->next
) {
3007 int bit_nr
= ether_crc(ETH_ALEN
, mclist
->dmi_addr
) >> 26;
3008 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
3009 rx_mode
|= AcceptMulticast
;
3013 spin_lock_irqsave(&tp
->lock
, flags
);
3015 tmp
= rtl8169_rx_config
| rx_mode
|
3016 (RTL_R32(RxConfig
) & rtl_chip_info
[tp
->chipset
].RxConfigMask
);
3018 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_11
) ||
3019 (tp
->mac_version
== RTL_GIGA_MAC_VER_12
) ||
3020 (tp
->mac_version
== RTL_GIGA_MAC_VER_13
) ||
3021 (tp
->mac_version
== RTL_GIGA_MAC_VER_14
) ||
3022 (tp
->mac_version
== RTL_GIGA_MAC_VER_15
)) {
3023 mc_filter
[0] = 0xffffffff;
3024 mc_filter
[1] = 0xffffffff;
3027 RTL_W32(RxConfig
, tmp
);
3028 RTL_W32(MAR0
+ 0, mc_filter
[0]);
3029 RTL_W32(MAR0
+ 4, mc_filter
[1]);
3031 spin_unlock_irqrestore(&tp
->lock
, flags
);
3035 * rtl8169_get_stats - Get rtl8169 read/write statistics
3036 * @dev: The Ethernet Device to get statistics for
3038 * Get TX/RX statistics for rtl8169
3040 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
)
3042 struct rtl8169_private
*tp
= netdev_priv(dev
);
3043 void __iomem
*ioaddr
= tp
->mmio_addr
;
3044 unsigned long flags
;
3046 if (netif_running(dev
)) {
3047 spin_lock_irqsave(&tp
->lock
, flags
);
3048 tp
->stats
.rx_missed_errors
+= RTL_R32(RxMissed
);
3049 RTL_W32(RxMissed
, 0);
3050 spin_unlock_irqrestore(&tp
->lock
, flags
);
3058 static int rtl8169_suspend(struct pci_dev
*pdev
, pm_message_t state
)
3060 struct net_device
*dev
= pci_get_drvdata(pdev
);
3061 struct rtl8169_private
*tp
= netdev_priv(dev
);
3062 void __iomem
*ioaddr
= tp
->mmio_addr
;
3064 if (!netif_running(dev
))
3065 goto out_pci_suspend
;
3067 netif_device_detach(dev
);
3068 netif_stop_queue(dev
);
3070 spin_lock_irq(&tp
->lock
);
3072 rtl8169_asic_down(ioaddr
);
3074 tp
->stats
.rx_missed_errors
+= RTL_R32(RxMissed
);
3075 RTL_W32(RxMissed
, 0);
3077 spin_unlock_irq(&tp
->lock
);
3080 pci_save_state(pdev
);
3081 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
), tp
->wol_enabled
);
3082 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
3087 static int rtl8169_resume(struct pci_dev
*pdev
)
3089 struct net_device
*dev
= pci_get_drvdata(pdev
);
3091 pci_set_power_state(pdev
, PCI_D0
);
3092 pci_restore_state(pdev
);
3093 pci_enable_wake(pdev
, PCI_D0
, 0);
3095 if (!netif_running(dev
))
3098 netif_device_attach(dev
);
3100 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
3105 #endif /* CONFIG_PM */
3107 static struct pci_driver rtl8169_pci_driver
= {
3109 .id_table
= rtl8169_pci_tbl
,
3110 .probe
= rtl8169_init_one
,
3111 .remove
= __devexit_p(rtl8169_remove_one
),
3113 .suspend
= rtl8169_suspend
,
3114 .resume
= rtl8169_resume
,
3119 rtl8169_init_module(void)
3121 return pci_register_driver(&rtl8169_pci_driver
);
3125 rtl8169_cleanup_module(void)
3127 pci_unregister_driver(&rtl8169_pci_driver
);
3130 module_init(rtl8169_init_module
);
3131 module_exit(rtl8169_cleanup_module
);