2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
28 #include <asm/system.h>
32 #define RTL8169_VERSION "2.3LK-NAPI"
33 #define MODULENAME "r8169"
34 #define PFX MODULENAME ": "
37 #define assert(expr) \
39 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
40 #expr,__FILE__,__func__,__LINE__); \
42 #define dprintk(fmt, args...) \
43 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
45 #define assert(expr) do {} while (0)
46 #define dprintk(fmt, args...) do {} while (0)
47 #endif /* RTL8169_DEBUG */
49 #define R8169_MSG_DEFAULT \
50 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
52 #define TX_BUFFS_AVAIL(tp) \
53 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
55 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
56 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
57 static const int multicast_filter_limit
= 32;
59 /* MAC address length */
60 #define MAC_ADDR_LEN 6
62 #define MAX_READ_REQUEST_SHIFT 12
63 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
64 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
65 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
66 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
67 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
68 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
70 #define R8169_REGS_SIZE 256
71 #define R8169_NAPI_WEIGHT 64
72 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
73 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
74 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
75 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
76 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
78 #define RTL8169_TX_TIMEOUT (6*HZ)
79 #define RTL8169_PHY_TIMEOUT (10*HZ)
81 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
82 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
83 #define RTL_EEPROM_SIG_ADDR 0x0000
85 /* write/read MMIO register */
86 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
87 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
88 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
89 #define RTL_R8(reg) readb (ioaddr + (reg))
90 #define RTL_R16(reg) readw (ioaddr + (reg))
91 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
94 RTL_GIGA_MAC_NONE
= 0x00,
95 RTL_GIGA_MAC_VER_01
= 0x01, // 8169
96 RTL_GIGA_MAC_VER_02
= 0x02, // 8169S
97 RTL_GIGA_MAC_VER_03
= 0x03, // 8110S
98 RTL_GIGA_MAC_VER_04
= 0x04, // 8169SB
99 RTL_GIGA_MAC_VER_05
= 0x05, // 8110SCd
100 RTL_GIGA_MAC_VER_06
= 0x06, // 8110SCe
101 RTL_GIGA_MAC_VER_07
= 0x07, // 8102e
102 RTL_GIGA_MAC_VER_08
= 0x08, // 8102e
103 RTL_GIGA_MAC_VER_09
= 0x09, // 8102e
104 RTL_GIGA_MAC_VER_10
= 0x0a, // 8101e
105 RTL_GIGA_MAC_VER_11
= 0x0b, // 8168Bb
106 RTL_GIGA_MAC_VER_12
= 0x0c, // 8168Be
107 RTL_GIGA_MAC_VER_13
= 0x0d, // 8101Eb
108 RTL_GIGA_MAC_VER_14
= 0x0e, // 8101 ?
109 RTL_GIGA_MAC_VER_15
= 0x0f, // 8101 ?
110 RTL_GIGA_MAC_VER_16
= 0x11, // 8101Ec
111 RTL_GIGA_MAC_VER_17
= 0x10, // 8168Bf
112 RTL_GIGA_MAC_VER_18
= 0x12, // 8168CP
113 RTL_GIGA_MAC_VER_19
= 0x13, // 8168C
114 RTL_GIGA_MAC_VER_20
= 0x14, // 8168C
115 RTL_GIGA_MAC_VER_21
= 0x15, // 8168C
116 RTL_GIGA_MAC_VER_22
= 0x16, // 8168C
117 RTL_GIGA_MAC_VER_23
= 0x17, // 8168CP
118 RTL_GIGA_MAC_VER_24
= 0x18, // 8168CP
119 RTL_GIGA_MAC_VER_25
= 0x19, // 8168D
120 RTL_GIGA_MAC_VER_26
= 0x1a, // 8168D
121 RTL_GIGA_MAC_VER_27
= 0x1b // 8168DP
124 #define _R(NAME,MAC,MASK) \
125 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
127 static const struct {
130 u32 RxConfigMask
; /* Clears the bits supported by this chip */
131 } rtl_chip_info
[] = {
132 _R("RTL8169", RTL_GIGA_MAC_VER_01
, 0xff7e1880), // 8169
133 _R("RTL8169s", RTL_GIGA_MAC_VER_02
, 0xff7e1880), // 8169S
134 _R("RTL8110s", RTL_GIGA_MAC_VER_03
, 0xff7e1880), // 8110S
135 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04
, 0xff7e1880), // 8169SB
136 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05
, 0xff7e1880), // 8110SCd
137 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06
, 0xff7e1880), // 8110SCe
138 _R("RTL8102e", RTL_GIGA_MAC_VER_07
, 0xff7e1880), // PCI-E
139 _R("RTL8102e", RTL_GIGA_MAC_VER_08
, 0xff7e1880), // PCI-E
140 _R("RTL8102e", RTL_GIGA_MAC_VER_09
, 0xff7e1880), // PCI-E
141 _R("RTL8101e", RTL_GIGA_MAC_VER_10
, 0xff7e1880), // PCI-E
142 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11
, 0xff7e1880), // PCI-E
143 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12
, 0xff7e1880), // PCI-E
144 _R("RTL8101e", RTL_GIGA_MAC_VER_13
, 0xff7e1880), // PCI-E 8139
145 _R("RTL8100e", RTL_GIGA_MAC_VER_14
, 0xff7e1880), // PCI-E 8139
146 _R("RTL8100e", RTL_GIGA_MAC_VER_15
, 0xff7e1880), // PCI-E 8139
147 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17
, 0xff7e1880), // PCI-E
148 _R("RTL8101e", RTL_GIGA_MAC_VER_16
, 0xff7e1880), // PCI-E
149 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18
, 0xff7e1880), // PCI-E
150 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19
, 0xff7e1880), // PCI-E
151 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20
, 0xff7e1880), // PCI-E
152 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21
, 0xff7e1880), // PCI-E
153 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22
, 0xff7e1880), // PCI-E
154 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23
, 0xff7e1880), // PCI-E
155 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24
, 0xff7e1880), // PCI-E
156 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25
, 0xff7e1880), // PCI-E
157 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26
, 0xff7e1880), // PCI-E
158 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27
, 0xff7e1880) // PCI-E
168 static void rtl_hw_start_8169(struct net_device
*);
169 static void rtl_hw_start_8168(struct net_device
*);
170 static void rtl_hw_start_8101(struct net_device
*);
172 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl
) = {
173 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8129), 0, 0, RTL_CFG_0
},
174 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8136), 0, 0, RTL_CFG_2
},
175 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8167), 0, 0, RTL_CFG_0
},
176 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8168), 0, 0, RTL_CFG_1
},
177 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8169), 0, 0, RTL_CFG_0
},
178 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4300), 0, 0, RTL_CFG_0
},
179 { PCI_DEVICE(PCI_VENDOR_ID_AT
, 0xc107), 0, 0, RTL_CFG_0
},
180 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0
},
181 { PCI_VENDOR_ID_LINKSYS
, 0x1032,
182 PCI_ANY_ID
, 0x0024, 0, 0, RTL_CFG_0
},
184 PCI_ANY_ID
, 0x2410, 0, 0, RTL_CFG_2
},
188 MODULE_DEVICE_TABLE(pci
, rtl8169_pci_tbl
);
191 * we set our copybreak very high so that we don't have
192 * to allocate 16k frames all the time (see note in
195 static int rx_copybreak
= 16383;
202 MAC0
= 0, /* Ethernet hardware address. */
204 MAR0
= 8, /* Multicast filter. */
205 CounterAddrLow
= 0x10,
206 CounterAddrHigh
= 0x14,
207 TxDescStartAddrLow
= 0x20,
208 TxDescStartAddrHigh
= 0x24,
209 TxHDescStartAddrLow
= 0x28,
210 TxHDescStartAddrHigh
= 0x2c,
233 RxDescAddrLow
= 0xe4,
234 RxDescAddrHigh
= 0xe8,
237 FuncEventMask
= 0xf4,
238 FuncPresetState
= 0xf8,
239 FuncForceEvent
= 0xfc,
242 enum rtl8110_registers
{
248 enum rtl8168_8101_registers
{
251 #define CSIAR_FLAG 0x80000000
252 #define CSIAR_WRITE_CMD 0x80000000
253 #define CSIAR_BYTE_ENABLE 0x0f
254 #define CSIAR_BYTE_ENABLE_SHIFT 12
255 #define CSIAR_ADDR_MASK 0x0fff
258 #define EPHYAR_FLAG 0x80000000
259 #define EPHYAR_WRITE_CMD 0x80000000
260 #define EPHYAR_REG_MASK 0x1f
261 #define EPHYAR_REG_SHIFT 16
262 #define EPHYAR_DATA_MASK 0xffff
264 #define FIX_NAK_1 (1 << 4)
265 #define FIX_NAK_2 (1 << 3)
267 #define EFUSEAR_FLAG 0x80000000
268 #define EFUSEAR_WRITE_CMD 0x80000000
269 #define EFUSEAR_READ_CMD 0x00000000
270 #define EFUSEAR_REG_MASK 0x03ff
271 #define EFUSEAR_REG_SHIFT 8
272 #define EFUSEAR_DATA_MASK 0xff
275 enum rtl_register_content
{
276 /* InterruptStatusBits */
280 TxDescUnavail
= 0x0080,
302 /* TXPoll register p.5 */
303 HPQ
= 0x80, /* Poll cmd on the high prio queue */
304 NPQ
= 0x40, /* Poll cmd on the low prio queue */
305 FSWInt
= 0x01, /* Forced software interrupt */
309 Cfg9346_Unlock
= 0xc0,
314 AcceptBroadcast
= 0x08,
315 AcceptMulticast
= 0x04,
317 AcceptAllPhys
= 0x01,
324 TxInterFrameGapShift
= 24,
325 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
327 /* Config1 register p.24 */
330 MSIEnable
= (1 << 5), /* Enable Message Signaled Interrupt */
331 Speed_down
= (1 << 4),
335 PMEnable
= (1 << 0), /* Power Management Enable */
337 /* Config2 register p. 25 */
338 PCI_Clock_66MHz
= 0x01,
339 PCI_Clock_33MHz
= 0x00,
341 /* Config3 register p.25 */
342 MagicPacket
= (1 << 5), /* Wake up when receives a Magic Packet */
343 LinkUp
= (1 << 4), /* Wake up when the cable connection is re-established */
344 Beacon_en
= (1 << 0), /* 8168 only. Reserved in the 8168b */
346 /* Config5 register p.27 */
347 BWF
= (1 << 6), /* Accept Broadcast wakeup frame */
348 MWF
= (1 << 5), /* Accept Multicast wakeup frame */
349 UWF
= (1 << 4), /* Accept Unicast wakeup frame */
350 LanWake
= (1 << 1), /* LanWake enable/disable */
351 PMEStatus
= (1 << 0), /* PME status can be reset by PCI RST# */
354 TBIReset
= 0x80000000,
355 TBILoopback
= 0x40000000,
356 TBINwEnable
= 0x20000000,
357 TBINwRestart
= 0x10000000,
358 TBILinkOk
= 0x02000000,
359 TBINwComplete
= 0x01000000,
362 EnableBist
= (1 << 15), // 8168 8101
363 Mac_dbgo_oe
= (1 << 14), // 8168 8101
364 Normal_mode
= (1 << 13), // unused
365 Force_half_dup
= (1 << 12), // 8168 8101
366 Force_rxflow_en
= (1 << 11), // 8168 8101
367 Force_txflow_en
= (1 << 10), // 8168 8101
368 Cxpl_dbg_sel
= (1 << 9), // 8168 8101
369 ASF
= (1 << 8), // 8168 8101
370 PktCntrDisable
= (1 << 7), // 8168 8101
371 Mac_dbgo_sel
= 0x001c, // 8168
376 INTT_0
= 0x0000, // 8168
377 INTT_1
= 0x0001, // 8168
378 INTT_2
= 0x0002, // 8168
379 INTT_3
= 0x0003, // 8168
381 /* rtl8169_PHYstatus */
392 TBILinkOK
= 0x02000000,
394 /* DumpCounterCommand */
398 enum desc_status_bit
{
399 DescOwn
= (1 << 31), /* Descriptor is owned by NIC */
400 RingEnd
= (1 << 30), /* End of descriptor ring */
401 FirstFrag
= (1 << 29), /* First segment of a packet */
402 LastFrag
= (1 << 28), /* Final segment of a packet */
405 LargeSend
= (1 << 27), /* TCP Large Send Offload (TSO) */
406 MSSShift
= 16, /* MSS value position */
407 MSSMask
= 0xfff, /* MSS value + LargeSend bit: 12 bits */
408 IPCS
= (1 << 18), /* Calculate IP checksum */
409 UDPCS
= (1 << 17), /* Calculate UDP/IP checksum */
410 TCPCS
= (1 << 16), /* Calculate TCP/IP checksum */
411 TxVlanTag
= (1 << 17), /* Add VLAN tag */
414 PID1
= (1 << 18), /* Protocol ID bit 1/2 */
415 PID0
= (1 << 17), /* Protocol ID bit 2/2 */
417 #define RxProtoUDP (PID1)
418 #define RxProtoTCP (PID0)
419 #define RxProtoIP (PID1 | PID0)
420 #define RxProtoMask RxProtoIP
422 IPFail
= (1 << 16), /* IP checksum failed */
423 UDPFail
= (1 << 15), /* UDP/IP checksum failed */
424 TCPFail
= (1 << 14), /* TCP/IP checksum failed */
425 RxVlanTag
= (1 << 16), /* VLAN tag available */
428 #define RsvdMask 0x3fffc000
445 u8 __pad
[sizeof(void *) - sizeof(u32
)];
449 RTL_FEATURE_WOL
= (1 << 0),
450 RTL_FEATURE_MSI
= (1 << 1),
451 RTL_FEATURE_GMII
= (1 << 2),
454 struct rtl8169_counters
{
461 __le32 tx_one_collision
;
462 __le32 tx_multi_collision
;
470 struct rtl8169_private
{
471 void __iomem
*mmio_addr
; /* memory map physical address */
472 struct pci_dev
*pci_dev
; /* Index of PCI device */
473 struct net_device
*dev
;
474 struct napi_struct napi
;
475 spinlock_t lock
; /* spin lock flag */
479 u32 cur_rx
; /* Index into the Rx descriptor buffer of next Rx pkt. */
480 u32 cur_tx
; /* Index into the Tx descriptor buffer of next Rx pkt. */
483 struct TxDesc
*TxDescArray
; /* 256-aligned Tx descriptor ring */
484 struct RxDesc
*RxDescArray
; /* 256-aligned Rx descriptor ring */
485 dma_addr_t TxPhyAddr
;
486 dma_addr_t RxPhyAddr
;
487 struct sk_buff
*Rx_skbuff
[NUM_RX_DESC
]; /* Rx data buffers */
488 struct ring_info tx_skb
[NUM_TX_DESC
]; /* Tx data buffers */
491 struct timer_list timer
;
496 int phy_1000_ctrl_reg
;
497 #ifdef CONFIG_R8169_VLAN
498 struct vlan_group
*vlgrp
;
500 int (*set_speed
)(struct net_device
*, u8 autoneg
, u16 speed
, u8 duplex
);
501 int (*get_settings
)(struct net_device
*, struct ethtool_cmd
*);
502 void (*phy_reset_enable
)(void __iomem
*);
503 void (*hw_start
)(struct net_device
*);
504 unsigned int (*phy_reset_pending
)(void __iomem
*);
505 unsigned int (*link_ok
)(void __iomem
*);
506 int (*do_ioctl
)(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
);
508 struct delayed_work task
;
511 struct mii_if_info mii
;
512 struct rtl8169_counters counters
;
516 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
517 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
518 module_param(rx_copybreak
, int, 0);
519 MODULE_PARM_DESC(rx_copybreak
, "Copy breakpoint for copy-only-tiny-frames");
520 module_param(use_dac
, int, 0);
521 MODULE_PARM_DESC(use_dac
, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
522 module_param_named(debug
, debug
.msg_enable
, int, 0);
523 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 16=all)");
524 MODULE_LICENSE("GPL");
525 MODULE_VERSION(RTL8169_VERSION
);
527 static int rtl8169_open(struct net_device
*dev
);
528 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
529 struct net_device
*dev
);
530 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
);
531 static int rtl8169_init_ring(struct net_device
*dev
);
532 static void rtl_hw_start(struct net_device
*dev
);
533 static int rtl8169_close(struct net_device
*dev
);
534 static void rtl_set_rx_mode(struct net_device
*dev
);
535 static void rtl8169_tx_timeout(struct net_device
*dev
);
536 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
);
537 static int rtl8169_rx_interrupt(struct net_device
*, struct rtl8169_private
*,
538 void __iomem
*, u32 budget
);
539 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
);
540 static void rtl8169_down(struct net_device
*dev
);
541 static void rtl8169_rx_clear(struct rtl8169_private
*tp
);
542 static int rtl8169_poll(struct napi_struct
*napi
, int budget
);
544 static const unsigned int rtl8169_rx_config
=
545 (RX_FIFO_THRESH
<< RxCfgFIFOShift
) | (RX_DMA_BURST
<< RxCfgDMAShift
);
547 static void mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
551 RTL_W32(PHYAR
, 0x80000000 | (reg_addr
& 0x1f) << 16 | (value
& 0xffff));
553 for (i
= 20; i
> 0; i
--) {
555 * Check if the RTL8169 has completed writing to the specified
558 if (!(RTL_R32(PHYAR
) & 0x80000000))
564 static int mdio_read(void __iomem
*ioaddr
, int reg_addr
)
568 RTL_W32(PHYAR
, 0x0 | (reg_addr
& 0x1f) << 16);
570 for (i
= 20; i
> 0; i
--) {
572 * Check if the RTL8169 has completed retrieving data from
573 * the specified MII register.
575 if (RTL_R32(PHYAR
) & 0x80000000) {
576 value
= RTL_R32(PHYAR
) & 0xffff;
584 static void mdio_patch(void __iomem
*ioaddr
, int reg_addr
, int value
)
586 mdio_write(ioaddr
, reg_addr
, mdio_read(ioaddr
, reg_addr
) | value
);
589 static void mdio_plus_minus(void __iomem
*ioaddr
, int reg_addr
, int p
, int m
)
593 val
= mdio_read(ioaddr
, reg_addr
);
594 mdio_write(ioaddr
, reg_addr
, (val
| p
) & ~m
);
597 static void rtl_mdio_write(struct net_device
*dev
, int phy_id
, int location
,
600 struct rtl8169_private
*tp
= netdev_priv(dev
);
601 void __iomem
*ioaddr
= tp
->mmio_addr
;
603 mdio_write(ioaddr
, location
, val
);
606 static int rtl_mdio_read(struct net_device
*dev
, int phy_id
, int location
)
608 struct rtl8169_private
*tp
= netdev_priv(dev
);
609 void __iomem
*ioaddr
= tp
->mmio_addr
;
611 return mdio_read(ioaddr
, location
);
614 static void rtl_ephy_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
618 RTL_W32(EPHYAR
, EPHYAR_WRITE_CMD
| (value
& EPHYAR_DATA_MASK
) |
619 (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
621 for (i
= 0; i
< 100; i
++) {
622 if (!(RTL_R32(EPHYAR
) & EPHYAR_FLAG
))
628 static u16
rtl_ephy_read(void __iomem
*ioaddr
, int reg_addr
)
633 RTL_W32(EPHYAR
, (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
635 for (i
= 0; i
< 100; i
++) {
636 if (RTL_R32(EPHYAR
) & EPHYAR_FLAG
) {
637 value
= RTL_R32(EPHYAR
) & EPHYAR_DATA_MASK
;
646 static void rtl_csi_write(void __iomem
*ioaddr
, int addr
, int value
)
650 RTL_W32(CSIDR
, value
);
651 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
652 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
654 for (i
= 0; i
< 100; i
++) {
655 if (!(RTL_R32(CSIAR
) & CSIAR_FLAG
))
661 static u32
rtl_csi_read(void __iomem
*ioaddr
, int addr
)
666 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) |
667 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
669 for (i
= 0; i
< 100; i
++) {
670 if (RTL_R32(CSIAR
) & CSIAR_FLAG
) {
671 value
= RTL_R32(CSIDR
);
680 static u8
rtl8168d_efuse_read(void __iomem
*ioaddr
, int reg_addr
)
685 RTL_W32(EFUSEAR
, (reg_addr
& EFUSEAR_REG_MASK
) << EFUSEAR_REG_SHIFT
);
687 for (i
= 0; i
< 300; i
++) {
688 if (RTL_R32(EFUSEAR
) & EFUSEAR_FLAG
) {
689 value
= RTL_R32(EFUSEAR
) & EFUSEAR_DATA_MASK
;
698 static void rtl8169_irq_mask_and_ack(void __iomem
*ioaddr
)
700 RTL_W16(IntrMask
, 0x0000);
702 RTL_W16(IntrStatus
, 0xffff);
705 static void rtl8169_asic_down(void __iomem
*ioaddr
)
707 RTL_W8(ChipCmd
, 0x00);
708 rtl8169_irq_mask_and_ack(ioaddr
);
712 static unsigned int rtl8169_tbi_reset_pending(void __iomem
*ioaddr
)
714 return RTL_R32(TBICSR
) & TBIReset
;
717 static unsigned int rtl8169_xmii_reset_pending(void __iomem
*ioaddr
)
719 return mdio_read(ioaddr
, MII_BMCR
) & BMCR_RESET
;
722 static unsigned int rtl8169_tbi_link_ok(void __iomem
*ioaddr
)
724 return RTL_R32(TBICSR
) & TBILinkOk
;
727 static unsigned int rtl8169_xmii_link_ok(void __iomem
*ioaddr
)
729 return RTL_R8(PHYstatus
) & LinkStatus
;
732 static void rtl8169_tbi_reset_enable(void __iomem
*ioaddr
)
734 RTL_W32(TBICSR
, RTL_R32(TBICSR
) | TBIReset
);
737 static void rtl8169_xmii_reset_enable(void __iomem
*ioaddr
)
741 val
= mdio_read(ioaddr
, MII_BMCR
) | BMCR_RESET
;
742 mdio_write(ioaddr
, MII_BMCR
, val
& 0xffff);
745 static void rtl8169_check_link_status(struct net_device
*dev
,
746 struct rtl8169_private
*tp
,
747 void __iomem
*ioaddr
)
751 spin_lock_irqsave(&tp
->lock
, flags
);
752 if (tp
->link_ok(ioaddr
)) {
753 /* This is to cancel a scheduled suspend if there's one. */
754 pm_request_resume(&tp
->pci_dev
->dev
);
755 netif_carrier_on(dev
);
756 netif_info(tp
, ifup
, dev
, "link up\n");
758 netif_carrier_off(dev
);
759 netif_info(tp
, ifdown
, dev
, "link down\n");
760 pm_schedule_suspend(&tp
->pci_dev
->dev
, 100);
762 spin_unlock_irqrestore(&tp
->lock
, flags
);
765 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
767 static u32
__rtl8169_get_wol(struct rtl8169_private
*tp
)
769 void __iomem
*ioaddr
= tp
->mmio_addr
;
773 options
= RTL_R8(Config1
);
774 if (!(options
& PMEnable
))
777 options
= RTL_R8(Config3
);
778 if (options
& LinkUp
)
780 if (options
& MagicPacket
)
781 wolopts
|= WAKE_MAGIC
;
783 options
= RTL_R8(Config5
);
785 wolopts
|= WAKE_UCAST
;
787 wolopts
|= WAKE_BCAST
;
789 wolopts
|= WAKE_MCAST
;
794 static void rtl8169_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
796 struct rtl8169_private
*tp
= netdev_priv(dev
);
798 spin_lock_irq(&tp
->lock
);
800 wol
->supported
= WAKE_ANY
;
801 wol
->wolopts
= __rtl8169_get_wol(tp
);
803 spin_unlock_irq(&tp
->lock
);
806 static void __rtl8169_set_wol(struct rtl8169_private
*tp
, u32 wolopts
)
808 void __iomem
*ioaddr
= tp
->mmio_addr
;
810 static const struct {
815 { WAKE_ANY
, Config1
, PMEnable
},
816 { WAKE_PHY
, Config3
, LinkUp
},
817 { WAKE_MAGIC
, Config3
, MagicPacket
},
818 { WAKE_UCAST
, Config5
, UWF
},
819 { WAKE_BCAST
, Config5
, BWF
},
820 { WAKE_MCAST
, Config5
, MWF
},
821 { WAKE_ANY
, Config5
, LanWake
}
824 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
826 for (i
= 0; i
< ARRAY_SIZE(cfg
); i
++) {
827 u8 options
= RTL_R8(cfg
[i
].reg
) & ~cfg
[i
].mask
;
828 if (wolopts
& cfg
[i
].opt
)
829 options
|= cfg
[i
].mask
;
830 RTL_W8(cfg
[i
].reg
, options
);
833 RTL_W8(Cfg9346
, Cfg9346_Lock
);
836 static int rtl8169_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
838 struct rtl8169_private
*tp
= netdev_priv(dev
);
840 spin_lock_irq(&tp
->lock
);
843 tp
->features
|= RTL_FEATURE_WOL
;
845 tp
->features
&= ~RTL_FEATURE_WOL
;
846 __rtl8169_set_wol(tp
, wol
->wolopts
);
847 device_set_wakeup_enable(&tp
->pci_dev
->dev
, wol
->wolopts
);
849 spin_unlock_irq(&tp
->lock
);
854 static void rtl8169_get_drvinfo(struct net_device
*dev
,
855 struct ethtool_drvinfo
*info
)
857 struct rtl8169_private
*tp
= netdev_priv(dev
);
859 strcpy(info
->driver
, MODULENAME
);
860 strcpy(info
->version
, RTL8169_VERSION
);
861 strcpy(info
->bus_info
, pci_name(tp
->pci_dev
));
864 static int rtl8169_get_regs_len(struct net_device
*dev
)
866 return R8169_REGS_SIZE
;
869 static int rtl8169_set_speed_tbi(struct net_device
*dev
,
870 u8 autoneg
, u16 speed
, u8 duplex
)
872 struct rtl8169_private
*tp
= netdev_priv(dev
);
873 void __iomem
*ioaddr
= tp
->mmio_addr
;
877 reg
= RTL_R32(TBICSR
);
878 if ((autoneg
== AUTONEG_DISABLE
) && (speed
== SPEED_1000
) &&
879 (duplex
== DUPLEX_FULL
)) {
880 RTL_W32(TBICSR
, reg
& ~(TBINwEnable
| TBINwRestart
));
881 } else if (autoneg
== AUTONEG_ENABLE
)
882 RTL_W32(TBICSR
, reg
| TBINwEnable
| TBINwRestart
);
884 netif_warn(tp
, link
, dev
,
885 "incorrect speed setting refused in TBI mode\n");
892 static int rtl8169_set_speed_xmii(struct net_device
*dev
,
893 u8 autoneg
, u16 speed
, u8 duplex
)
895 struct rtl8169_private
*tp
= netdev_priv(dev
);
896 void __iomem
*ioaddr
= tp
->mmio_addr
;
899 if (autoneg
== AUTONEG_ENABLE
) {
902 auto_nego
= mdio_read(ioaddr
, MII_ADVERTISE
);
903 auto_nego
|= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
904 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
905 auto_nego
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
907 giga_ctrl
= mdio_read(ioaddr
, MII_CTRL1000
);
908 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
910 /* The 8100e/8101e/8102e do Fast Ethernet only. */
911 if ((tp
->mac_version
!= RTL_GIGA_MAC_VER_07
) &&
912 (tp
->mac_version
!= RTL_GIGA_MAC_VER_08
) &&
913 (tp
->mac_version
!= RTL_GIGA_MAC_VER_09
) &&
914 (tp
->mac_version
!= RTL_GIGA_MAC_VER_10
) &&
915 (tp
->mac_version
!= RTL_GIGA_MAC_VER_13
) &&
916 (tp
->mac_version
!= RTL_GIGA_MAC_VER_14
) &&
917 (tp
->mac_version
!= RTL_GIGA_MAC_VER_15
) &&
918 (tp
->mac_version
!= RTL_GIGA_MAC_VER_16
)) {
919 giga_ctrl
|= ADVERTISE_1000FULL
| ADVERTISE_1000HALF
;
921 netif_info(tp
, link
, dev
,
922 "PHY does not support 1000Mbps\n");
925 bmcr
= BMCR_ANENABLE
| BMCR_ANRESTART
;
927 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_11
) ||
928 (tp
->mac_version
== RTL_GIGA_MAC_VER_12
) ||
929 (tp
->mac_version
>= RTL_GIGA_MAC_VER_17
)) {
932 * Vendor specific (0x1f) and reserved (0x0e) MII
935 mdio_write(ioaddr
, 0x1f, 0x0000);
936 mdio_write(ioaddr
, 0x0e, 0x0000);
939 mdio_write(ioaddr
, MII_ADVERTISE
, auto_nego
);
940 mdio_write(ioaddr
, MII_CTRL1000
, giga_ctrl
);
944 if (speed
== SPEED_10
)
946 else if (speed
== SPEED_100
)
947 bmcr
= BMCR_SPEED100
;
951 if (duplex
== DUPLEX_FULL
)
952 bmcr
|= BMCR_FULLDPLX
;
954 mdio_write(ioaddr
, 0x1f, 0x0000);
957 tp
->phy_1000_ctrl_reg
= giga_ctrl
;
959 mdio_write(ioaddr
, MII_BMCR
, bmcr
);
961 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
962 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
)) {
963 if ((speed
== SPEED_100
) && (autoneg
!= AUTONEG_ENABLE
)) {
964 mdio_write(ioaddr
, 0x17, 0x2138);
965 mdio_write(ioaddr
, 0x0e, 0x0260);
967 mdio_write(ioaddr
, 0x17, 0x2108);
968 mdio_write(ioaddr
, 0x0e, 0x0000);
975 static int rtl8169_set_speed(struct net_device
*dev
,
976 u8 autoneg
, u16 speed
, u8 duplex
)
978 struct rtl8169_private
*tp
= netdev_priv(dev
);
981 ret
= tp
->set_speed(dev
, autoneg
, speed
, duplex
);
983 if (netif_running(dev
) && (tp
->phy_1000_ctrl_reg
& ADVERTISE_1000FULL
))
984 mod_timer(&tp
->timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
989 static int rtl8169_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
991 struct rtl8169_private
*tp
= netdev_priv(dev
);
995 spin_lock_irqsave(&tp
->lock
, flags
);
996 ret
= rtl8169_set_speed(dev
, cmd
->autoneg
, cmd
->speed
, cmd
->duplex
);
997 spin_unlock_irqrestore(&tp
->lock
, flags
);
1002 static u32
rtl8169_get_rx_csum(struct net_device
*dev
)
1004 struct rtl8169_private
*tp
= netdev_priv(dev
);
1006 return tp
->cp_cmd
& RxChkSum
;
1009 static int rtl8169_set_rx_csum(struct net_device
*dev
, u32 data
)
1011 struct rtl8169_private
*tp
= netdev_priv(dev
);
1012 void __iomem
*ioaddr
= tp
->mmio_addr
;
1013 unsigned long flags
;
1015 spin_lock_irqsave(&tp
->lock
, flags
);
1018 tp
->cp_cmd
|= RxChkSum
;
1020 tp
->cp_cmd
&= ~RxChkSum
;
1022 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
1025 spin_unlock_irqrestore(&tp
->lock
, flags
);
1030 #ifdef CONFIG_R8169_VLAN
1032 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
1033 struct sk_buff
*skb
)
1035 return (tp
->vlgrp
&& vlan_tx_tag_present(skb
)) ?
1036 TxVlanTag
| swab16(vlan_tx_tag_get(skb
)) : 0x00;
1039 static void rtl8169_vlan_rx_register(struct net_device
*dev
,
1040 struct vlan_group
*grp
)
1042 struct rtl8169_private
*tp
= netdev_priv(dev
);
1043 void __iomem
*ioaddr
= tp
->mmio_addr
;
1044 unsigned long flags
;
1046 spin_lock_irqsave(&tp
->lock
, flags
);
1049 * Do not disable RxVlan on 8110SCd.
1051 if (tp
->vlgrp
|| (tp
->mac_version
== RTL_GIGA_MAC_VER_05
))
1052 tp
->cp_cmd
|= RxVlan
;
1054 tp
->cp_cmd
&= ~RxVlan
;
1055 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
1057 spin_unlock_irqrestore(&tp
->lock
, flags
);
1060 static int rtl8169_rx_vlan_skb(struct rtl8169_private
*tp
, struct RxDesc
*desc
,
1061 struct sk_buff
*skb
, int polling
)
1063 u32 opts2
= le32_to_cpu(desc
->opts2
);
1064 struct vlan_group
*vlgrp
= tp
->vlgrp
;
1067 if (vlgrp
&& (opts2
& RxVlanTag
)) {
1068 __vlan_hwaccel_rx(skb
, vlgrp
, swab16(opts2
& 0xffff), polling
);
1076 #else /* !CONFIG_R8169_VLAN */
1078 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
1079 struct sk_buff
*skb
)
1084 static int rtl8169_rx_vlan_skb(struct rtl8169_private
*tp
, struct RxDesc
*desc
,
1085 struct sk_buff
*skb
, int polling
)
1092 static int rtl8169_gset_tbi(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1094 struct rtl8169_private
*tp
= netdev_priv(dev
);
1095 void __iomem
*ioaddr
= tp
->mmio_addr
;
1099 SUPPORTED_1000baseT_Full
| SUPPORTED_Autoneg
| SUPPORTED_FIBRE
;
1100 cmd
->port
= PORT_FIBRE
;
1101 cmd
->transceiver
= XCVR_INTERNAL
;
1103 status
= RTL_R32(TBICSR
);
1104 cmd
->advertising
= (status
& TBINwEnable
) ? ADVERTISED_Autoneg
: 0;
1105 cmd
->autoneg
= !!(status
& TBINwEnable
);
1107 cmd
->speed
= SPEED_1000
;
1108 cmd
->duplex
= DUPLEX_FULL
; /* Always set */
1113 static int rtl8169_gset_xmii(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1115 struct rtl8169_private
*tp
= netdev_priv(dev
);
1117 return mii_ethtool_gset(&tp
->mii
, cmd
);
1120 static int rtl8169_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1122 struct rtl8169_private
*tp
= netdev_priv(dev
);
1123 unsigned long flags
;
1126 spin_lock_irqsave(&tp
->lock
, flags
);
1128 rc
= tp
->get_settings(dev
, cmd
);
1130 spin_unlock_irqrestore(&tp
->lock
, flags
);
1134 static void rtl8169_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1137 struct rtl8169_private
*tp
= netdev_priv(dev
);
1138 unsigned long flags
;
1140 if (regs
->len
> R8169_REGS_SIZE
)
1141 regs
->len
= R8169_REGS_SIZE
;
1143 spin_lock_irqsave(&tp
->lock
, flags
);
1144 memcpy_fromio(p
, tp
->mmio_addr
, regs
->len
);
1145 spin_unlock_irqrestore(&tp
->lock
, flags
);
1148 static u32
rtl8169_get_msglevel(struct net_device
*dev
)
1150 struct rtl8169_private
*tp
= netdev_priv(dev
);
1152 return tp
->msg_enable
;
1155 static void rtl8169_set_msglevel(struct net_device
*dev
, u32 value
)
1157 struct rtl8169_private
*tp
= netdev_priv(dev
);
1159 tp
->msg_enable
= value
;
1162 static const char rtl8169_gstrings
[][ETH_GSTRING_LEN
] = {
1169 "tx_single_collisions",
1170 "tx_multi_collisions",
1178 static int rtl8169_get_sset_count(struct net_device
*dev
, int sset
)
1182 return ARRAY_SIZE(rtl8169_gstrings
);
1188 static void rtl8169_update_counters(struct net_device
*dev
)
1190 struct rtl8169_private
*tp
= netdev_priv(dev
);
1191 void __iomem
*ioaddr
= tp
->mmio_addr
;
1192 struct rtl8169_counters
*counters
;
1198 * Some chips are unable to dump tally counters when the receiver
1201 if ((RTL_R8(ChipCmd
) & CmdRxEnb
) == 0)
1204 counters
= pci_alloc_consistent(tp
->pci_dev
, sizeof(*counters
), &paddr
);
1208 RTL_W32(CounterAddrHigh
, (u64
)paddr
>> 32);
1209 cmd
= (u64
)paddr
& DMA_BIT_MASK(32);
1210 RTL_W32(CounterAddrLow
, cmd
);
1211 RTL_W32(CounterAddrLow
, cmd
| CounterDump
);
1214 if ((RTL_R32(CounterAddrLow
) & CounterDump
) == 0) {
1215 /* copy updated counters */
1216 memcpy(&tp
->counters
, counters
, sizeof(*counters
));
1222 RTL_W32(CounterAddrLow
, 0);
1223 RTL_W32(CounterAddrHigh
, 0);
1225 pci_free_consistent(tp
->pci_dev
, sizeof(*counters
), counters
, paddr
);
1228 static void rtl8169_get_ethtool_stats(struct net_device
*dev
,
1229 struct ethtool_stats
*stats
, u64
*data
)
1231 struct rtl8169_private
*tp
= netdev_priv(dev
);
1235 rtl8169_update_counters(dev
);
1237 data
[0] = le64_to_cpu(tp
->counters
.tx_packets
);
1238 data
[1] = le64_to_cpu(tp
->counters
.rx_packets
);
1239 data
[2] = le64_to_cpu(tp
->counters
.tx_errors
);
1240 data
[3] = le32_to_cpu(tp
->counters
.rx_errors
);
1241 data
[4] = le16_to_cpu(tp
->counters
.rx_missed
);
1242 data
[5] = le16_to_cpu(tp
->counters
.align_errors
);
1243 data
[6] = le32_to_cpu(tp
->counters
.tx_one_collision
);
1244 data
[7] = le32_to_cpu(tp
->counters
.tx_multi_collision
);
1245 data
[8] = le64_to_cpu(tp
->counters
.rx_unicast
);
1246 data
[9] = le64_to_cpu(tp
->counters
.rx_broadcast
);
1247 data
[10] = le32_to_cpu(tp
->counters
.rx_multicast
);
1248 data
[11] = le16_to_cpu(tp
->counters
.tx_aborted
);
1249 data
[12] = le16_to_cpu(tp
->counters
.tx_underun
);
1252 static void rtl8169_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1256 memcpy(data
, *rtl8169_gstrings
, sizeof(rtl8169_gstrings
));
1261 static const struct ethtool_ops rtl8169_ethtool_ops
= {
1262 .get_drvinfo
= rtl8169_get_drvinfo
,
1263 .get_regs_len
= rtl8169_get_regs_len
,
1264 .get_link
= ethtool_op_get_link
,
1265 .get_settings
= rtl8169_get_settings
,
1266 .set_settings
= rtl8169_set_settings
,
1267 .get_msglevel
= rtl8169_get_msglevel
,
1268 .set_msglevel
= rtl8169_set_msglevel
,
1269 .get_rx_csum
= rtl8169_get_rx_csum
,
1270 .set_rx_csum
= rtl8169_set_rx_csum
,
1271 .set_tx_csum
= ethtool_op_set_tx_csum
,
1272 .set_sg
= ethtool_op_set_sg
,
1273 .set_tso
= ethtool_op_set_tso
,
1274 .get_regs
= rtl8169_get_regs
,
1275 .get_wol
= rtl8169_get_wol
,
1276 .set_wol
= rtl8169_set_wol
,
1277 .get_strings
= rtl8169_get_strings
,
1278 .get_sset_count
= rtl8169_get_sset_count
,
1279 .get_ethtool_stats
= rtl8169_get_ethtool_stats
,
1282 static void rtl8169_get_mac_version(struct rtl8169_private
*tp
,
1283 void __iomem
*ioaddr
)
1286 * The driver currently handles the 8168Bf and the 8168Be identically
1287 * but they can be identified more specifically through the test below
1290 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1292 * Same thing for the 8101Eb and the 8101Ec:
1294 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1296 static const struct {
1302 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26
},
1303 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25
},
1304 { 0x7c800000, 0x28800000, RTL_GIGA_MAC_VER_27
},
1305 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26
},
1308 { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24
},
1309 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23
},
1310 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18
},
1311 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24
},
1312 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19
},
1313 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20
},
1314 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21
},
1315 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22
},
1316 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22
},
1319 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12
},
1320 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17
},
1321 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17
},
1322 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11
},
1325 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09
},
1326 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09
},
1327 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08
},
1328 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08
},
1329 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07
},
1330 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07
},
1331 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13
},
1332 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10
},
1333 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16
},
1334 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09
},
1335 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09
},
1336 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16
},
1337 /* FIXME: where did these entries come from ? -- FR */
1338 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15
},
1339 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14
},
1342 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06
},
1343 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05
},
1344 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04
},
1345 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03
},
1346 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02
},
1347 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01
},
1350 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE
}
1354 reg
= RTL_R32(TxConfig
);
1355 while ((reg
& p
->mask
) != p
->val
)
1357 tp
->mac_version
= p
->mac_version
;
1360 static void rtl8169_print_mac_version(struct rtl8169_private
*tp
)
1362 dprintk("mac_version = 0x%02x\n", tp
->mac_version
);
1370 static void rtl_phy_write(void __iomem
*ioaddr
, const struct phy_reg
*regs
, int len
)
1373 mdio_write(ioaddr
, regs
->reg
, regs
->val
);
1378 static void rtl8169s_hw_phy_config(void __iomem
*ioaddr
)
1380 static const struct phy_reg phy_reg_init
[] = {
1442 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1445 static void rtl8169sb_hw_phy_config(void __iomem
*ioaddr
)
1447 static const struct phy_reg phy_reg_init
[] = {
1453 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1456 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private
*tp
,
1457 void __iomem
*ioaddr
)
1459 struct pci_dev
*pdev
= tp
->pci_dev
;
1460 u16 vendor_id
, device_id
;
1462 pci_read_config_word(pdev
, PCI_SUBSYSTEM_VENDOR_ID
, &vendor_id
);
1463 pci_read_config_word(pdev
, PCI_SUBSYSTEM_ID
, &device_id
);
1465 if ((vendor_id
!= PCI_VENDOR_ID_GIGABYTE
) || (device_id
!= 0xe000))
1468 mdio_write(ioaddr
, 0x1f, 0x0001);
1469 mdio_write(ioaddr
, 0x10, 0xf01b);
1470 mdio_write(ioaddr
, 0x1f, 0x0000);
1473 static void rtl8169scd_hw_phy_config(struct rtl8169_private
*tp
,
1474 void __iomem
*ioaddr
)
1476 static const struct phy_reg phy_reg_init
[] = {
1516 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1518 rtl8169scd_hw_phy_config_quirk(tp
, ioaddr
);
1521 static void rtl8169sce_hw_phy_config(void __iomem
*ioaddr
)
1523 static const struct phy_reg phy_reg_init
[] = {
1571 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1574 static void rtl8168bb_hw_phy_config(void __iomem
*ioaddr
)
1576 static const struct phy_reg phy_reg_init
[] = {
1581 mdio_write(ioaddr
, 0x1f, 0x0001);
1582 mdio_patch(ioaddr
, 0x16, 1 << 0);
1584 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1587 static void rtl8168bef_hw_phy_config(void __iomem
*ioaddr
)
1589 static const struct phy_reg phy_reg_init
[] = {
1595 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1598 static void rtl8168cp_1_hw_phy_config(void __iomem
*ioaddr
)
1600 static const struct phy_reg phy_reg_init
[] = {
1608 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1611 static void rtl8168cp_2_hw_phy_config(void __iomem
*ioaddr
)
1613 static const struct phy_reg phy_reg_init
[] = {
1619 mdio_write(ioaddr
, 0x1f, 0x0000);
1620 mdio_patch(ioaddr
, 0x14, 1 << 5);
1621 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1623 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1626 static void rtl8168c_1_hw_phy_config(void __iomem
*ioaddr
)
1628 static const struct phy_reg phy_reg_init
[] = {
1648 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1650 mdio_patch(ioaddr
, 0x14, 1 << 5);
1651 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1652 mdio_write(ioaddr
, 0x1f, 0x0000);
1655 static void rtl8168c_2_hw_phy_config(void __iomem
*ioaddr
)
1657 static const struct phy_reg phy_reg_init
[] = {
1675 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1677 mdio_patch(ioaddr
, 0x16, 1 << 0);
1678 mdio_patch(ioaddr
, 0x14, 1 << 5);
1679 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1680 mdio_write(ioaddr
, 0x1f, 0x0000);
1683 static void rtl8168c_3_hw_phy_config(void __iomem
*ioaddr
)
1685 static const struct phy_reg phy_reg_init
[] = {
1697 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1699 mdio_patch(ioaddr
, 0x16, 1 << 0);
1700 mdio_patch(ioaddr
, 0x14, 1 << 5);
1701 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1702 mdio_write(ioaddr
, 0x1f, 0x0000);
1705 static void rtl8168c_4_hw_phy_config(void __iomem
*ioaddr
)
1707 rtl8168c_3_hw_phy_config(ioaddr
);
1710 static void rtl8168d_1_hw_phy_config(void __iomem
*ioaddr
)
1712 static const struct phy_reg phy_reg_init_0
[] = {
1731 static const struct phy_reg phy_reg_init_1
[] = {
1738 static const struct phy_reg phy_reg_init_2
[] = {
2094 rtl_phy_write(ioaddr
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
2096 mdio_write(ioaddr
, 0x1f, 0x0002);
2097 mdio_plus_minus(ioaddr
, 0x0b, 0x0010, 0x00ef);
2098 mdio_plus_minus(ioaddr
, 0x0c, 0xa200, 0x5d00);
2100 rtl_phy_write(ioaddr
, phy_reg_init_1
, ARRAY_SIZE(phy_reg_init_1
));
2102 if (rtl8168d_efuse_read(ioaddr
, 0x01) == 0xb1) {
2103 static const struct phy_reg phy_reg_init
[] = {
2113 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2115 val
= mdio_read(ioaddr
, 0x0d);
2117 if ((val
& 0x00ff) != 0x006c) {
2118 static const u32 set
[] = {
2119 0x0065, 0x0066, 0x0067, 0x0068,
2120 0x0069, 0x006a, 0x006b, 0x006c
2124 mdio_write(ioaddr
, 0x1f, 0x0002);
2127 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2128 mdio_write(ioaddr
, 0x0d, val
| set
[i
]);
2131 static const struct phy_reg phy_reg_init
[] = {
2139 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2142 mdio_write(ioaddr
, 0x1f, 0x0002);
2143 mdio_patch(ioaddr
, 0x0d, 0x0300);
2144 mdio_patch(ioaddr
, 0x0f, 0x0010);
2146 mdio_write(ioaddr
, 0x1f, 0x0002);
2147 mdio_plus_minus(ioaddr
, 0x02, 0x0100, 0x0600);
2148 mdio_plus_minus(ioaddr
, 0x03, 0x0000, 0xe000);
2150 rtl_phy_write(ioaddr
, phy_reg_init_2
, ARRAY_SIZE(phy_reg_init_2
));
2153 static void rtl8168d_2_hw_phy_config(void __iomem
*ioaddr
)
2155 static const struct phy_reg phy_reg_init_0
[] = {
2180 static const struct phy_reg phy_reg_init_1
[] = {
2493 rtl_phy_write(ioaddr
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
2495 if (rtl8168d_efuse_read(ioaddr
, 0x01) == 0xb1) {
2496 static const struct phy_reg phy_reg_init
[] = {
2507 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2509 val
= mdio_read(ioaddr
, 0x0d);
2510 if ((val
& 0x00ff) != 0x006c) {
2512 0x0065, 0x0066, 0x0067, 0x0068,
2513 0x0069, 0x006a, 0x006b, 0x006c
2517 mdio_write(ioaddr
, 0x1f, 0x0002);
2520 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2521 mdio_write(ioaddr
, 0x0d, val
| set
[i
]);
2524 static const struct phy_reg phy_reg_init
[] = {
2532 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2535 mdio_write(ioaddr
, 0x1f, 0x0002);
2536 mdio_plus_minus(ioaddr
, 0x02, 0x0100, 0x0600);
2537 mdio_plus_minus(ioaddr
, 0x03, 0x0000, 0xe000);
2539 mdio_write(ioaddr
, 0x1f, 0x0001);
2540 mdio_write(ioaddr
, 0x17, 0x0cc0);
2542 mdio_write(ioaddr
, 0x1f, 0x0002);
2543 mdio_patch(ioaddr
, 0x0f, 0x0017);
2545 rtl_phy_write(ioaddr
, phy_reg_init_1
, ARRAY_SIZE(phy_reg_init_1
));
2548 static void rtl8168d_3_hw_phy_config(void __iomem
*ioaddr
)
2550 static const struct phy_reg phy_reg_init
[] = {
2606 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2609 static void rtl8102e_hw_phy_config(void __iomem
*ioaddr
)
2611 static const struct phy_reg phy_reg_init
[] = {
2618 mdio_write(ioaddr
, 0x1f, 0x0000);
2619 mdio_patch(ioaddr
, 0x11, 1 << 12);
2620 mdio_patch(ioaddr
, 0x19, 1 << 13);
2621 mdio_patch(ioaddr
, 0x10, 1 << 15);
2623 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2626 static void rtl_hw_phy_config(struct net_device
*dev
)
2628 struct rtl8169_private
*tp
= netdev_priv(dev
);
2629 void __iomem
*ioaddr
= tp
->mmio_addr
;
2631 rtl8169_print_mac_version(tp
);
2633 switch (tp
->mac_version
) {
2634 case RTL_GIGA_MAC_VER_01
:
2636 case RTL_GIGA_MAC_VER_02
:
2637 case RTL_GIGA_MAC_VER_03
:
2638 rtl8169s_hw_phy_config(ioaddr
);
2640 case RTL_GIGA_MAC_VER_04
:
2641 rtl8169sb_hw_phy_config(ioaddr
);
2643 case RTL_GIGA_MAC_VER_05
:
2644 rtl8169scd_hw_phy_config(tp
, ioaddr
);
2646 case RTL_GIGA_MAC_VER_06
:
2647 rtl8169sce_hw_phy_config(ioaddr
);
2649 case RTL_GIGA_MAC_VER_07
:
2650 case RTL_GIGA_MAC_VER_08
:
2651 case RTL_GIGA_MAC_VER_09
:
2652 rtl8102e_hw_phy_config(ioaddr
);
2654 case RTL_GIGA_MAC_VER_11
:
2655 rtl8168bb_hw_phy_config(ioaddr
);
2657 case RTL_GIGA_MAC_VER_12
:
2658 rtl8168bef_hw_phy_config(ioaddr
);
2660 case RTL_GIGA_MAC_VER_17
:
2661 rtl8168bef_hw_phy_config(ioaddr
);
2663 case RTL_GIGA_MAC_VER_18
:
2664 rtl8168cp_1_hw_phy_config(ioaddr
);
2666 case RTL_GIGA_MAC_VER_19
:
2667 rtl8168c_1_hw_phy_config(ioaddr
);
2669 case RTL_GIGA_MAC_VER_20
:
2670 rtl8168c_2_hw_phy_config(ioaddr
);
2672 case RTL_GIGA_MAC_VER_21
:
2673 rtl8168c_3_hw_phy_config(ioaddr
);
2675 case RTL_GIGA_MAC_VER_22
:
2676 rtl8168c_4_hw_phy_config(ioaddr
);
2678 case RTL_GIGA_MAC_VER_23
:
2679 case RTL_GIGA_MAC_VER_24
:
2680 rtl8168cp_2_hw_phy_config(ioaddr
);
2682 case RTL_GIGA_MAC_VER_25
:
2683 rtl8168d_1_hw_phy_config(ioaddr
);
2685 case RTL_GIGA_MAC_VER_26
:
2686 rtl8168d_2_hw_phy_config(ioaddr
);
2688 case RTL_GIGA_MAC_VER_27
:
2689 rtl8168d_3_hw_phy_config(ioaddr
);
2697 static void rtl8169_phy_timer(unsigned long __opaque
)
2699 struct net_device
*dev
= (struct net_device
*)__opaque
;
2700 struct rtl8169_private
*tp
= netdev_priv(dev
);
2701 struct timer_list
*timer
= &tp
->timer
;
2702 void __iomem
*ioaddr
= tp
->mmio_addr
;
2703 unsigned long timeout
= RTL8169_PHY_TIMEOUT
;
2705 assert(tp
->mac_version
> RTL_GIGA_MAC_VER_01
);
2707 if (!(tp
->phy_1000_ctrl_reg
& ADVERTISE_1000FULL
))
2710 spin_lock_irq(&tp
->lock
);
2712 if (tp
->phy_reset_pending(ioaddr
)) {
2714 * A busy loop could burn quite a few cycles on nowadays CPU.
2715 * Let's delay the execution of the timer for a few ticks.
2721 if (tp
->link_ok(ioaddr
))
2724 netif_warn(tp
, link
, dev
, "PHY reset until link up\n");
2726 tp
->phy_reset_enable(ioaddr
);
2729 mod_timer(timer
, jiffies
+ timeout
);
2731 spin_unlock_irq(&tp
->lock
);
2734 static inline void rtl8169_delete_timer(struct net_device
*dev
)
2736 struct rtl8169_private
*tp
= netdev_priv(dev
);
2737 struct timer_list
*timer
= &tp
->timer
;
2739 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_01
)
2742 del_timer_sync(timer
);
2745 static inline void rtl8169_request_timer(struct net_device
*dev
)
2747 struct rtl8169_private
*tp
= netdev_priv(dev
);
2748 struct timer_list
*timer
= &tp
->timer
;
2750 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_01
)
2753 mod_timer(timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
2756 #ifdef CONFIG_NET_POLL_CONTROLLER
2758 * Polling 'interrupt' - used by things like netconsole to send skbs
2759 * without having to re-enable interrupts. It's not called while
2760 * the interrupt routine is executing.
2762 static void rtl8169_netpoll(struct net_device
*dev
)
2764 struct rtl8169_private
*tp
= netdev_priv(dev
);
2765 struct pci_dev
*pdev
= tp
->pci_dev
;
2767 disable_irq(pdev
->irq
);
2768 rtl8169_interrupt(pdev
->irq
, dev
);
2769 enable_irq(pdev
->irq
);
2773 static void rtl8169_release_board(struct pci_dev
*pdev
, struct net_device
*dev
,
2774 void __iomem
*ioaddr
)
2777 pci_release_regions(pdev
);
2778 pci_disable_device(pdev
);
2782 static void rtl8169_phy_reset(struct net_device
*dev
,
2783 struct rtl8169_private
*tp
)
2785 void __iomem
*ioaddr
= tp
->mmio_addr
;
2788 tp
->phy_reset_enable(ioaddr
);
2789 for (i
= 0; i
< 100; i
++) {
2790 if (!tp
->phy_reset_pending(ioaddr
))
2794 netif_err(tp
, link
, dev
, "PHY reset failed\n");
2797 static void rtl8169_init_phy(struct net_device
*dev
, struct rtl8169_private
*tp
)
2799 void __iomem
*ioaddr
= tp
->mmio_addr
;
2801 rtl_hw_phy_config(dev
);
2803 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) {
2804 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2808 pci_write_config_byte(tp
->pci_dev
, PCI_LATENCY_TIMER
, 0x40);
2810 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
2811 pci_write_config_byte(tp
->pci_dev
, PCI_CACHE_LINE_SIZE
, 0x08);
2813 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) {
2814 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2816 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2817 mdio_write(ioaddr
, 0x0b, 0x0000); //w 0x0b 15 0 0
2820 rtl8169_phy_reset(dev
, tp
);
2823 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2824 * only 8101. Don't panic.
2826 rtl8169_set_speed(dev
, AUTONEG_ENABLE
, SPEED_1000
, DUPLEX_FULL
);
2828 if (RTL_R8(PHYstatus
) & TBI_Enable
)
2829 netif_info(tp
, link
, dev
, "TBI auto-negotiating\n");
2832 static void rtl_rar_set(struct rtl8169_private
*tp
, u8
*addr
)
2834 void __iomem
*ioaddr
= tp
->mmio_addr
;
2838 low
= addr
[0] | (addr
[1] << 8) | (addr
[2] << 16) | (addr
[3] << 24);
2839 high
= addr
[4] | (addr
[5] << 8);
2841 spin_lock_irq(&tp
->lock
);
2843 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2844 RTL_W32(MAC4
, high
);
2846 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2848 spin_unlock_irq(&tp
->lock
);
2851 static int rtl_set_mac_address(struct net_device
*dev
, void *p
)
2853 struct rtl8169_private
*tp
= netdev_priv(dev
);
2854 struct sockaddr
*addr
= p
;
2856 if (!is_valid_ether_addr(addr
->sa_data
))
2857 return -EADDRNOTAVAIL
;
2859 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
2861 rtl_rar_set(tp
, dev
->dev_addr
);
2866 static int rtl8169_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
2868 struct rtl8169_private
*tp
= netdev_priv(dev
);
2869 struct mii_ioctl_data
*data
= if_mii(ifr
);
2871 return netif_running(dev
) ? tp
->do_ioctl(tp
, data
, cmd
) : -ENODEV
;
2874 static int rtl_xmii_ioctl(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
)
2878 data
->phy_id
= 32; /* Internal PHY */
2882 data
->val_out
= mdio_read(tp
->mmio_addr
, data
->reg_num
& 0x1f);
2886 mdio_write(tp
->mmio_addr
, data
->reg_num
& 0x1f, data
->val_in
);
2892 static int rtl_tbi_ioctl(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
)
2897 static const struct rtl_cfg_info
{
2898 void (*hw_start
)(struct net_device
*);
2899 unsigned int region
;
2905 } rtl_cfg_infos
[] = {
2907 .hw_start
= rtl_hw_start_8169
,
2910 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
2911 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
2912 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
2913 .features
= RTL_FEATURE_GMII
,
2914 .default_ver
= RTL_GIGA_MAC_VER_01
,
2917 .hw_start
= rtl_hw_start_8168
,
2920 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
2921 TxErr
| TxOK
| RxOK
| RxErr
,
2922 .napi_event
= TxErr
| TxOK
| RxOK
| RxOverflow
,
2923 .features
= RTL_FEATURE_GMII
| RTL_FEATURE_MSI
,
2924 .default_ver
= RTL_GIGA_MAC_VER_11
,
2927 .hw_start
= rtl_hw_start_8101
,
2930 .intr_event
= SYSErr
| LinkChg
| RxOverflow
| PCSTimeout
|
2931 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
2932 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
2933 .features
= RTL_FEATURE_MSI
,
2934 .default_ver
= RTL_GIGA_MAC_VER_13
,
2938 /* Cfg9346_Unlock assumed. */
2939 static unsigned rtl_try_msi(struct pci_dev
*pdev
, void __iomem
*ioaddr
,
2940 const struct rtl_cfg_info
*cfg
)
2945 cfg2
= RTL_R8(Config2
) & ~MSIEnable
;
2946 if (cfg
->features
& RTL_FEATURE_MSI
) {
2947 if (pci_enable_msi(pdev
)) {
2948 dev_info(&pdev
->dev
, "no MSI. Back to INTx.\n");
2951 msi
= RTL_FEATURE_MSI
;
2954 RTL_W8(Config2
, cfg2
);
2958 static void rtl_disable_msi(struct pci_dev
*pdev
, struct rtl8169_private
*tp
)
2960 if (tp
->features
& RTL_FEATURE_MSI
) {
2961 pci_disable_msi(pdev
);
2962 tp
->features
&= ~RTL_FEATURE_MSI
;
2966 static const struct net_device_ops rtl8169_netdev_ops
= {
2967 .ndo_open
= rtl8169_open
,
2968 .ndo_stop
= rtl8169_close
,
2969 .ndo_get_stats
= rtl8169_get_stats
,
2970 .ndo_start_xmit
= rtl8169_start_xmit
,
2971 .ndo_tx_timeout
= rtl8169_tx_timeout
,
2972 .ndo_validate_addr
= eth_validate_addr
,
2973 .ndo_change_mtu
= rtl8169_change_mtu
,
2974 .ndo_set_mac_address
= rtl_set_mac_address
,
2975 .ndo_do_ioctl
= rtl8169_ioctl
,
2976 .ndo_set_multicast_list
= rtl_set_rx_mode
,
2977 #ifdef CONFIG_R8169_VLAN
2978 .ndo_vlan_rx_register
= rtl8169_vlan_rx_register
,
2980 #ifdef CONFIG_NET_POLL_CONTROLLER
2981 .ndo_poll_controller
= rtl8169_netpoll
,
2986 static int __devinit
2987 rtl8169_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
2989 const struct rtl_cfg_info
*cfg
= rtl_cfg_infos
+ ent
->driver_data
;
2990 const unsigned int region
= cfg
->region
;
2991 struct rtl8169_private
*tp
;
2992 struct mii_if_info
*mii
;
2993 struct net_device
*dev
;
2994 void __iomem
*ioaddr
;
2998 if (netif_msg_drv(&debug
)) {
2999 printk(KERN_INFO
"%s Gigabit Ethernet driver %s loaded\n",
3000 MODULENAME
, RTL8169_VERSION
);
3003 dev
= alloc_etherdev(sizeof (*tp
));
3005 if (netif_msg_drv(&debug
))
3006 dev_err(&pdev
->dev
, "unable to alloc new ethernet\n");
3011 SET_NETDEV_DEV(dev
, &pdev
->dev
);
3012 dev
->netdev_ops
= &rtl8169_netdev_ops
;
3013 tp
= netdev_priv(dev
);
3016 tp
->msg_enable
= netif_msg_init(debug
.msg_enable
, R8169_MSG_DEFAULT
);
3020 mii
->mdio_read
= rtl_mdio_read
;
3021 mii
->mdio_write
= rtl_mdio_write
;
3022 mii
->phy_id_mask
= 0x1f;
3023 mii
->reg_num_mask
= 0x1f;
3024 mii
->supports_gmii
= !!(cfg
->features
& RTL_FEATURE_GMII
);
3026 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3027 rc
= pci_enable_device(pdev
);
3029 netif_err(tp
, probe
, dev
, "enable failure\n");
3030 goto err_out_free_dev_1
;
3033 rc
= pci_set_mwi(pdev
);
3035 goto err_out_disable_2
;
3037 /* make sure PCI base addr 1 is MMIO */
3038 if (!(pci_resource_flags(pdev
, region
) & IORESOURCE_MEM
)) {
3039 netif_err(tp
, probe
, dev
,
3040 "region #%d not an MMIO resource, aborting\n",
3046 /* check for weird/broken PCI region reporting */
3047 if (pci_resource_len(pdev
, region
) < R8169_REGS_SIZE
) {
3048 netif_err(tp
, probe
, dev
,
3049 "Invalid PCI region size(s), aborting\n");
3054 rc
= pci_request_regions(pdev
, MODULENAME
);
3056 netif_err(tp
, probe
, dev
, "could not request regions\n");
3060 tp
->cp_cmd
= PCIMulRW
| RxChkSum
;
3062 if ((sizeof(dma_addr_t
) > 4) &&
3063 !pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)) && use_dac
) {
3064 tp
->cp_cmd
|= PCIDAC
;
3065 dev
->features
|= NETIF_F_HIGHDMA
;
3067 rc
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
3069 netif_err(tp
, probe
, dev
, "DMA configuration failed\n");
3070 goto err_out_free_res_4
;
3074 /* ioremap MMIO region */
3075 ioaddr
= ioremap(pci_resource_start(pdev
, region
), R8169_REGS_SIZE
);
3077 netif_err(tp
, probe
, dev
, "cannot remap MMIO, aborting\n");
3079 goto err_out_free_res_4
;
3082 tp
->pcie_cap
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
3084 netif_info(tp
, probe
, dev
, "no PCI Express capability\n");
3086 RTL_W16(IntrMask
, 0x0000);
3088 /* Soft reset the chip. */
3089 RTL_W8(ChipCmd
, CmdReset
);
3091 /* Check that the chip has finished the reset. */
3092 for (i
= 0; i
< 100; i
++) {
3093 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
3095 msleep_interruptible(1);
3098 RTL_W16(IntrStatus
, 0xffff);
3100 pci_set_master(pdev
);
3102 /* Identify chip attached to board */
3103 rtl8169_get_mac_version(tp
, ioaddr
);
3105 /* Use appropriate default if unknown */
3106 if (tp
->mac_version
== RTL_GIGA_MAC_NONE
) {
3107 netif_notice(tp
, probe
, dev
,
3108 "unknown MAC, using family default\n");
3109 tp
->mac_version
= cfg
->default_ver
;
3112 rtl8169_print_mac_version(tp
);
3114 for (i
= 0; i
< ARRAY_SIZE(rtl_chip_info
); i
++) {
3115 if (tp
->mac_version
== rtl_chip_info
[i
].mac_version
)
3118 if (i
== ARRAY_SIZE(rtl_chip_info
)) {
3120 "driver bug, MAC version not found in rtl_chip_info\n");
3125 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3126 RTL_W8(Config1
, RTL_R8(Config1
) | PMEnable
);
3127 RTL_W8(Config5
, RTL_R8(Config5
) & PMEStatus
);
3128 if ((RTL_R8(Config3
) & (LinkUp
| MagicPacket
)) != 0)
3129 tp
->features
|= RTL_FEATURE_WOL
;
3130 if ((RTL_R8(Config5
) & (UWF
| BWF
| MWF
)) != 0)
3131 tp
->features
|= RTL_FEATURE_WOL
;
3132 tp
->features
|= rtl_try_msi(pdev
, ioaddr
, cfg
);
3133 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3135 if ((tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) &&
3136 (RTL_R8(PHYstatus
) & TBI_Enable
)) {
3137 tp
->set_speed
= rtl8169_set_speed_tbi
;
3138 tp
->get_settings
= rtl8169_gset_tbi
;
3139 tp
->phy_reset_enable
= rtl8169_tbi_reset_enable
;
3140 tp
->phy_reset_pending
= rtl8169_tbi_reset_pending
;
3141 tp
->link_ok
= rtl8169_tbi_link_ok
;
3142 tp
->do_ioctl
= rtl_tbi_ioctl
;
3144 tp
->phy_1000_ctrl_reg
= ADVERTISE_1000FULL
; /* Implied by TBI */
3146 tp
->set_speed
= rtl8169_set_speed_xmii
;
3147 tp
->get_settings
= rtl8169_gset_xmii
;
3148 tp
->phy_reset_enable
= rtl8169_xmii_reset_enable
;
3149 tp
->phy_reset_pending
= rtl8169_xmii_reset_pending
;
3150 tp
->link_ok
= rtl8169_xmii_link_ok
;
3151 tp
->do_ioctl
= rtl_xmii_ioctl
;
3154 spin_lock_init(&tp
->lock
);
3156 tp
->mmio_addr
= ioaddr
;
3158 /* Get MAC address */
3159 for (i
= 0; i
< MAC_ADDR_LEN
; i
++)
3160 dev
->dev_addr
[i
] = RTL_R8(MAC0
+ i
);
3161 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3163 SET_ETHTOOL_OPS(dev
, &rtl8169_ethtool_ops
);
3164 dev
->watchdog_timeo
= RTL8169_TX_TIMEOUT
;
3165 dev
->irq
= pdev
->irq
;
3166 dev
->base_addr
= (unsigned long) ioaddr
;
3168 netif_napi_add(dev
, &tp
->napi
, rtl8169_poll
, R8169_NAPI_WEIGHT
);
3170 #ifdef CONFIG_R8169_VLAN
3171 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3174 tp
->intr_mask
= 0xffff;
3175 tp
->align
= cfg
->align
;
3176 tp
->hw_start
= cfg
->hw_start
;
3177 tp
->intr_event
= cfg
->intr_event
;
3178 tp
->napi_event
= cfg
->napi_event
;
3180 init_timer(&tp
->timer
);
3181 tp
->timer
.data
= (unsigned long) dev
;
3182 tp
->timer
.function
= rtl8169_phy_timer
;
3184 rc
= register_netdev(dev
);
3188 pci_set_drvdata(pdev
, dev
);
3190 netif_info(tp
, probe
, dev
, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3191 rtl_chip_info
[tp
->chipset
].name
,
3192 dev
->base_addr
, dev
->dev_addr
,
3193 (u32
)(RTL_R32(TxConfig
) & 0x9cf0f8ff), dev
->irq
);
3195 rtl8169_init_phy(dev
, tp
);
3198 * Pretend we are using VLANs; This bypasses a nasty bug where
3199 * Interrupts stop flowing on high load on 8110SCd controllers.
3201 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
3202 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | RxVlan
);
3204 device_set_wakeup_enable(&pdev
->dev
, tp
->features
& RTL_FEATURE_WOL
);
3206 if (pci_dev_run_wake(pdev
)) {
3207 pm_runtime_set_active(&pdev
->dev
);
3208 pm_runtime_enable(&pdev
->dev
);
3210 pm_runtime_idle(&pdev
->dev
);
3216 rtl_disable_msi(pdev
, tp
);
3219 pci_release_regions(pdev
);
3221 pci_clear_mwi(pdev
);
3223 pci_disable_device(pdev
);
3229 static void __devexit
rtl8169_remove_one(struct pci_dev
*pdev
)
3231 struct net_device
*dev
= pci_get_drvdata(pdev
);
3232 struct rtl8169_private
*tp
= netdev_priv(dev
);
3234 pm_runtime_get_sync(&pdev
->dev
);
3236 flush_scheduled_work();
3238 unregister_netdev(dev
);
3240 if (pci_dev_run_wake(pdev
)) {
3241 pm_runtime_disable(&pdev
->dev
);
3242 pm_runtime_set_suspended(&pdev
->dev
);
3244 pm_runtime_put_noidle(&pdev
->dev
);
3246 /* restore original MAC address */
3247 rtl_rar_set(tp
, dev
->perm_addr
);
3249 rtl_disable_msi(pdev
, tp
);
3250 rtl8169_release_board(pdev
, dev
, tp
->mmio_addr
);
3251 pci_set_drvdata(pdev
, NULL
);
3254 static void rtl8169_set_rxbufsize(struct rtl8169_private
*tp
,
3257 unsigned int max_frame
= mtu
+ VLAN_ETH_HLEN
+ ETH_FCS_LEN
;
3259 if (max_frame
!= 16383)
3260 printk(KERN_WARNING PFX
"WARNING! Changing of MTU on this "
3261 "NIC may lead to frame reception errors!\n");
3263 tp
->rx_buf_sz
= (max_frame
> RX_BUF_SIZE
) ? max_frame
: RX_BUF_SIZE
;
3266 static int rtl8169_open(struct net_device
*dev
)
3268 struct rtl8169_private
*tp
= netdev_priv(dev
);
3269 struct pci_dev
*pdev
= tp
->pci_dev
;
3270 int retval
= -ENOMEM
;
3272 pm_runtime_get_sync(&pdev
->dev
);
3275 * Note that we use a magic value here, its wierd I know
3276 * its done because, some subset of rtl8169 hardware suffers from
3277 * a problem in which frames received that are longer than
3278 * the size set in RxMaxSize register return garbage sizes
3279 * when received. To avoid this we need to turn off filtering,
3280 * which is done by setting a value of 16383 in the RxMaxSize register
3281 * and allocating 16k frames to handle the largest possible rx value
3282 * thats what the magic math below does.
3284 rtl8169_set_rxbufsize(tp
, 16383 - VLAN_ETH_HLEN
- ETH_FCS_LEN
);
3287 * Rx and Tx desscriptors needs 256 bytes alignment.
3288 * pci_alloc_consistent provides more.
3290 tp
->TxDescArray
= pci_alloc_consistent(pdev
, R8169_TX_RING_BYTES
,
3292 if (!tp
->TxDescArray
)
3293 goto err_pm_runtime_put
;
3295 tp
->RxDescArray
= pci_alloc_consistent(pdev
, R8169_RX_RING_BYTES
,
3297 if (!tp
->RxDescArray
)
3300 retval
= rtl8169_init_ring(dev
);
3304 INIT_DELAYED_WORK(&tp
->task
, NULL
);
3308 retval
= request_irq(dev
->irq
, rtl8169_interrupt
,
3309 (tp
->features
& RTL_FEATURE_MSI
) ? 0 : IRQF_SHARED
,
3312 goto err_release_ring_2
;
3314 napi_enable(&tp
->napi
);
3318 rtl8169_request_timer(dev
);
3320 tp
->saved_wolopts
= 0;
3321 pm_runtime_put_noidle(&pdev
->dev
);
3323 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
3328 rtl8169_rx_clear(tp
);
3330 pci_free_consistent(pdev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
3332 tp
->RxDescArray
= NULL
;
3334 pci_free_consistent(pdev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
3336 tp
->TxDescArray
= NULL
;
3338 pm_runtime_put_noidle(&pdev
->dev
);
3342 static void rtl8169_hw_reset(void __iomem
*ioaddr
)
3344 /* Disable interrupts */
3345 rtl8169_irq_mask_and_ack(ioaddr
);
3347 /* Reset the chipset */
3348 RTL_W8(ChipCmd
, CmdReset
);
3354 static void rtl_set_rx_tx_config_registers(struct rtl8169_private
*tp
)
3356 void __iomem
*ioaddr
= tp
->mmio_addr
;
3357 u32 cfg
= rtl8169_rx_config
;
3359 cfg
|= (RTL_R32(RxConfig
) & rtl_chip_info
[tp
->chipset
].RxConfigMask
);
3360 RTL_W32(RxConfig
, cfg
);
3362 /* Set DMA burst size and Interframe Gap Time */
3363 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
3364 (InterFrameGap
<< TxInterFrameGapShift
));
3367 static void rtl_hw_start(struct net_device
*dev
)
3369 struct rtl8169_private
*tp
= netdev_priv(dev
);
3370 void __iomem
*ioaddr
= tp
->mmio_addr
;
3373 /* Soft reset the chip. */
3374 RTL_W8(ChipCmd
, CmdReset
);
3376 /* Check that the chip has finished the reset. */
3377 for (i
= 0; i
< 100; i
++) {
3378 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
3380 msleep_interruptible(1);
3385 netif_start_queue(dev
);
3389 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private
*tp
,
3390 void __iomem
*ioaddr
)
3393 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3394 * register to be written before TxDescAddrLow to work.
3395 * Switching from MMIO to I/O access fixes the issue as well.
3397 RTL_W32(TxDescStartAddrHigh
, ((u64
) tp
->TxPhyAddr
) >> 32);
3398 RTL_W32(TxDescStartAddrLow
, ((u64
) tp
->TxPhyAddr
) & DMA_BIT_MASK(32));
3399 RTL_W32(RxDescAddrHigh
, ((u64
) tp
->RxPhyAddr
) >> 32);
3400 RTL_W32(RxDescAddrLow
, ((u64
) tp
->RxPhyAddr
) & DMA_BIT_MASK(32));
3403 static u16
rtl_rw_cpluscmd(void __iomem
*ioaddr
)
3407 cmd
= RTL_R16(CPlusCmd
);
3408 RTL_W16(CPlusCmd
, cmd
);
3412 static void rtl_set_rx_max_size(void __iomem
*ioaddr
, unsigned int rx_buf_sz
)
3414 /* Low hurts. Let's disable the filtering. */
3415 RTL_W16(RxMaxSize
, rx_buf_sz
+ 1);
3418 static void rtl8169_set_magic_reg(void __iomem
*ioaddr
, unsigned mac_version
)
3420 static const struct {
3425 { RTL_GIGA_MAC_VER_05
, PCI_Clock_33MHz
, 0x000fff00 }, // 8110SCd
3426 { RTL_GIGA_MAC_VER_05
, PCI_Clock_66MHz
, 0x000fffff },
3427 { RTL_GIGA_MAC_VER_06
, PCI_Clock_33MHz
, 0x00ffff00 }, // 8110SCe
3428 { RTL_GIGA_MAC_VER_06
, PCI_Clock_66MHz
, 0x00ffffff }
3433 clk
= RTL_R8(Config2
) & PCI_Clock_66MHz
;
3434 for (i
= 0; i
< ARRAY_SIZE(cfg2_info
); i
++, p
++) {
3435 if ((p
->mac_version
== mac_version
) && (p
->clk
== clk
)) {
3436 RTL_W32(0x7c, p
->val
);
3442 static void rtl_hw_start_8169(struct net_device
*dev
)
3444 struct rtl8169_private
*tp
= netdev_priv(dev
);
3445 void __iomem
*ioaddr
= tp
->mmio_addr
;
3446 struct pci_dev
*pdev
= tp
->pci_dev
;
3448 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
) {
3449 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | PCIMulRW
);
3450 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, 0x08);
3453 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3454 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_01
) ||
3455 (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
3456 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
) ||
3457 (tp
->mac_version
== RTL_GIGA_MAC_VER_04
))
3458 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3460 RTL_W8(EarlyTxThres
, EarlyTxThld
);
3462 rtl_set_rx_max_size(ioaddr
, tp
->rx_buf_sz
);
3464 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_01
) ||
3465 (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
3466 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
) ||
3467 (tp
->mac_version
== RTL_GIGA_MAC_VER_04
))
3468 rtl_set_rx_tx_config_registers(tp
);
3470 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
3472 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
3473 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
)) {
3474 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3475 "Bit-3 and bit-14 MUST be 1\n");
3476 tp
->cp_cmd
|= (1 << 14);
3479 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
3481 rtl8169_set_magic_reg(ioaddr
, tp
->mac_version
);
3484 * Undocumented corner. Supposedly:
3485 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3487 RTL_W16(IntrMitigate
, 0x0000);
3489 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
3491 if ((tp
->mac_version
!= RTL_GIGA_MAC_VER_01
) &&
3492 (tp
->mac_version
!= RTL_GIGA_MAC_VER_02
) &&
3493 (tp
->mac_version
!= RTL_GIGA_MAC_VER_03
) &&
3494 (tp
->mac_version
!= RTL_GIGA_MAC_VER_04
)) {
3495 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3496 rtl_set_rx_tx_config_registers(tp
);
3499 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3501 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3504 RTL_W32(RxMissed
, 0);
3506 rtl_set_rx_mode(dev
);
3508 /* no early-rx interrupts */
3509 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
3511 /* Enable all known interrupts by setting the interrupt mask. */
3512 RTL_W16(IntrMask
, tp
->intr_event
);
3515 static void rtl_tx_performance_tweak(struct pci_dev
*pdev
, u16 force
)
3517 struct net_device
*dev
= pci_get_drvdata(pdev
);
3518 struct rtl8169_private
*tp
= netdev_priv(dev
);
3519 int cap
= tp
->pcie_cap
;
3524 pci_read_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
3525 ctl
= (ctl
& ~PCI_EXP_DEVCTL_READRQ
) | force
;
3526 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
3530 static void rtl_csi_access_enable(void __iomem
*ioaddr
)
3534 csi
= rtl_csi_read(ioaddr
, 0x070c) & 0x00ffffff;
3535 rtl_csi_write(ioaddr
, 0x070c, csi
| 0x27000000);
3539 unsigned int offset
;
3544 static void rtl_ephy_init(void __iomem
*ioaddr
, const struct ephy_info
*e
, int len
)
3549 w
= (rtl_ephy_read(ioaddr
, e
->offset
) & ~e
->mask
) | e
->bits
;
3550 rtl_ephy_write(ioaddr
, e
->offset
, w
);
3555 static void rtl_disable_clock_request(struct pci_dev
*pdev
)
3557 struct net_device
*dev
= pci_get_drvdata(pdev
);
3558 struct rtl8169_private
*tp
= netdev_priv(dev
);
3559 int cap
= tp
->pcie_cap
;
3564 pci_read_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, &ctl
);
3565 ctl
&= ~PCI_EXP_LNKCTL_CLKREQ_EN
;
3566 pci_write_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, ctl
);
3570 #define R8168_CPCMD_QUIRK_MASK (\
3581 static void rtl_hw_start_8168bb(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3583 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3585 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3587 rtl_tx_performance_tweak(pdev
,
3588 (0x5 << MAX_READ_REQUEST_SHIFT
) | PCI_EXP_DEVCTL_NOSNOOP_EN
);
3591 static void rtl_hw_start_8168bef(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3593 rtl_hw_start_8168bb(ioaddr
, pdev
);
3595 RTL_W8(EarlyTxThres
, EarlyTxThld
);
3597 RTL_W8(Config4
, RTL_R8(Config4
) & ~(1 << 0));
3600 static void __rtl_hw_start_8168cp(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3602 RTL_W8(Config1
, RTL_R8(Config1
) | Speed_down
);
3604 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3606 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3608 rtl_disable_clock_request(pdev
);
3610 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3613 static void rtl_hw_start_8168cp_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3615 static const struct ephy_info e_info_8168cp
[] = {
3616 { 0x01, 0, 0x0001 },
3617 { 0x02, 0x0800, 0x1000 },
3618 { 0x03, 0, 0x0042 },
3619 { 0x06, 0x0080, 0x0000 },
3623 rtl_csi_access_enable(ioaddr
);
3625 rtl_ephy_init(ioaddr
, e_info_8168cp
, ARRAY_SIZE(e_info_8168cp
));
3627 __rtl_hw_start_8168cp(ioaddr
, pdev
);
3630 static void rtl_hw_start_8168cp_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3632 rtl_csi_access_enable(ioaddr
);
3634 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3636 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3638 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3641 static void rtl_hw_start_8168cp_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3643 rtl_csi_access_enable(ioaddr
);
3645 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3648 RTL_W8(DBG_REG
, 0x20);
3650 RTL_W8(EarlyTxThres
, EarlyTxThld
);
3652 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3654 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3657 static void rtl_hw_start_8168c_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3659 static const struct ephy_info e_info_8168c_1
[] = {
3660 { 0x02, 0x0800, 0x1000 },
3661 { 0x03, 0, 0x0002 },
3662 { 0x06, 0x0080, 0x0000 }
3665 rtl_csi_access_enable(ioaddr
);
3667 RTL_W8(DBG_REG
, 0x06 | FIX_NAK_1
| FIX_NAK_2
);
3669 rtl_ephy_init(ioaddr
, e_info_8168c_1
, ARRAY_SIZE(e_info_8168c_1
));
3671 __rtl_hw_start_8168cp(ioaddr
, pdev
);
3674 static void rtl_hw_start_8168c_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3676 static const struct ephy_info e_info_8168c_2
[] = {
3677 { 0x01, 0, 0x0001 },
3678 { 0x03, 0x0400, 0x0220 }
3681 rtl_csi_access_enable(ioaddr
);
3683 rtl_ephy_init(ioaddr
, e_info_8168c_2
, ARRAY_SIZE(e_info_8168c_2
));
3685 __rtl_hw_start_8168cp(ioaddr
, pdev
);
3688 static void rtl_hw_start_8168c_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3690 rtl_hw_start_8168c_2(ioaddr
, pdev
);
3693 static void rtl_hw_start_8168c_4(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3695 rtl_csi_access_enable(ioaddr
);
3697 __rtl_hw_start_8168cp(ioaddr
, pdev
);
3700 static void rtl_hw_start_8168d(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3702 rtl_csi_access_enable(ioaddr
);
3704 rtl_disable_clock_request(pdev
);
3706 RTL_W8(EarlyTxThres
, EarlyTxThld
);
3708 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3710 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3713 static void rtl_hw_start_8168(struct net_device
*dev
)
3715 struct rtl8169_private
*tp
= netdev_priv(dev
);
3716 void __iomem
*ioaddr
= tp
->mmio_addr
;
3717 struct pci_dev
*pdev
= tp
->pci_dev
;
3719 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3721 RTL_W8(EarlyTxThres
, EarlyTxThld
);
3723 rtl_set_rx_max_size(ioaddr
, tp
->rx_buf_sz
);
3725 tp
->cp_cmd
|= RTL_R16(CPlusCmd
) | PktCntrDisable
| INTT_1
;
3727 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
3729 RTL_W16(IntrMitigate
, 0x5151);
3731 /* Work around for RxFIFO overflow. */
3732 if (tp
->mac_version
== RTL_GIGA_MAC_VER_11
) {
3733 tp
->intr_event
|= RxFIFOOver
| PCSTimeout
;
3734 tp
->intr_event
&= ~RxOverflow
;
3737 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
3739 rtl_set_rx_mode(dev
);
3741 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
3742 (InterFrameGap
<< TxInterFrameGapShift
));
3746 switch (tp
->mac_version
) {
3747 case RTL_GIGA_MAC_VER_11
:
3748 rtl_hw_start_8168bb(ioaddr
, pdev
);
3751 case RTL_GIGA_MAC_VER_12
:
3752 case RTL_GIGA_MAC_VER_17
:
3753 rtl_hw_start_8168bef(ioaddr
, pdev
);
3756 case RTL_GIGA_MAC_VER_18
:
3757 rtl_hw_start_8168cp_1(ioaddr
, pdev
);
3760 case RTL_GIGA_MAC_VER_19
:
3761 rtl_hw_start_8168c_1(ioaddr
, pdev
);
3764 case RTL_GIGA_MAC_VER_20
:
3765 rtl_hw_start_8168c_2(ioaddr
, pdev
);
3768 case RTL_GIGA_MAC_VER_21
:
3769 rtl_hw_start_8168c_3(ioaddr
, pdev
);
3772 case RTL_GIGA_MAC_VER_22
:
3773 rtl_hw_start_8168c_4(ioaddr
, pdev
);
3776 case RTL_GIGA_MAC_VER_23
:
3777 rtl_hw_start_8168cp_2(ioaddr
, pdev
);
3780 case RTL_GIGA_MAC_VER_24
:
3781 rtl_hw_start_8168cp_3(ioaddr
, pdev
);
3784 case RTL_GIGA_MAC_VER_25
:
3785 case RTL_GIGA_MAC_VER_26
:
3786 case RTL_GIGA_MAC_VER_27
:
3787 rtl_hw_start_8168d(ioaddr
, pdev
);
3791 printk(KERN_ERR PFX
"%s: unknown chipset (mac_version = %d).\n",
3792 dev
->name
, tp
->mac_version
);
3796 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3798 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3800 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
3802 RTL_W16(IntrMask
, tp
->intr_event
);
3805 #define R810X_CPCMD_QUIRK_MASK (\
3817 static void rtl_hw_start_8102e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3819 static const struct ephy_info e_info_8102e_1
[] = {
3820 { 0x01, 0, 0x6e65 },
3821 { 0x02, 0, 0x091f },
3822 { 0x03, 0, 0xc2f9 },
3823 { 0x06, 0, 0xafb5 },
3824 { 0x07, 0, 0x0e00 },
3825 { 0x19, 0, 0xec80 },
3826 { 0x01, 0, 0x2e65 },
3831 rtl_csi_access_enable(ioaddr
);
3833 RTL_W8(DBG_REG
, FIX_NAK_1
);
3835 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3838 LEDS1
| LEDS0
| Speed_down
| MEMMAP
| IOMAP
| VPD
| PMEnable
);
3839 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3841 cfg1
= RTL_R8(Config1
);
3842 if ((cfg1
& LEDS0
) && (cfg1
& LEDS1
))
3843 RTL_W8(Config1
, cfg1
& ~LEDS0
);
3845 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R810X_CPCMD_QUIRK_MASK
);
3847 rtl_ephy_init(ioaddr
, e_info_8102e_1
, ARRAY_SIZE(e_info_8102e_1
));
3850 static void rtl_hw_start_8102e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3852 rtl_csi_access_enable(ioaddr
);
3854 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3856 RTL_W8(Config1
, MEMMAP
| IOMAP
| VPD
| PMEnable
);
3857 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3859 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R810X_CPCMD_QUIRK_MASK
);
3862 static void rtl_hw_start_8102e_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3864 rtl_hw_start_8102e_2(ioaddr
, pdev
);
3866 rtl_ephy_write(ioaddr
, 0x03, 0xc2f9);
3869 static void rtl_hw_start_8101(struct net_device
*dev
)
3871 struct rtl8169_private
*tp
= netdev_priv(dev
);
3872 void __iomem
*ioaddr
= tp
->mmio_addr
;
3873 struct pci_dev
*pdev
= tp
->pci_dev
;
3875 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_13
) ||
3876 (tp
->mac_version
== RTL_GIGA_MAC_VER_16
)) {
3877 int cap
= tp
->pcie_cap
;
3880 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
,
3881 PCI_EXP_DEVCTL_NOSNOOP_EN
);
3885 switch (tp
->mac_version
) {
3886 case RTL_GIGA_MAC_VER_07
:
3887 rtl_hw_start_8102e_1(ioaddr
, pdev
);
3890 case RTL_GIGA_MAC_VER_08
:
3891 rtl_hw_start_8102e_3(ioaddr
, pdev
);
3894 case RTL_GIGA_MAC_VER_09
:
3895 rtl_hw_start_8102e_2(ioaddr
, pdev
);
3899 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3901 RTL_W8(EarlyTxThres
, EarlyTxThld
);
3903 rtl_set_rx_max_size(ioaddr
, tp
->rx_buf_sz
);
3905 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
3907 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
3909 RTL_W16(IntrMitigate
, 0x0000);
3911 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
3913 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3914 rtl_set_rx_tx_config_registers(tp
);
3916 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3920 rtl_set_rx_mode(dev
);
3922 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3924 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
3926 RTL_W16(IntrMask
, tp
->intr_event
);
3929 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
)
3931 struct rtl8169_private
*tp
= netdev_priv(dev
);
3934 if (new_mtu
< ETH_ZLEN
|| new_mtu
> SafeMtu
)
3939 if (!netif_running(dev
))
3944 rtl8169_set_rxbufsize(tp
, dev
->mtu
);
3946 ret
= rtl8169_init_ring(dev
);
3950 napi_enable(&tp
->napi
);
3954 rtl8169_request_timer(dev
);
3960 static inline void rtl8169_make_unusable_by_asic(struct RxDesc
*desc
)
3962 desc
->addr
= cpu_to_le64(0x0badbadbadbadbadull
);
3963 desc
->opts1
&= ~cpu_to_le32(DescOwn
| RsvdMask
);
3966 static void rtl8169_free_rx_skb(struct rtl8169_private
*tp
,
3967 struct sk_buff
**sk_buff
, struct RxDesc
*desc
)
3969 struct pci_dev
*pdev
= tp
->pci_dev
;
3971 pci_unmap_single(pdev
, le64_to_cpu(desc
->addr
), tp
->rx_buf_sz
,
3972 PCI_DMA_FROMDEVICE
);
3973 dev_kfree_skb(*sk_buff
);
3975 rtl8169_make_unusable_by_asic(desc
);
3978 static inline void rtl8169_mark_to_asic(struct RxDesc
*desc
, u32 rx_buf_sz
)
3980 u32 eor
= le32_to_cpu(desc
->opts1
) & RingEnd
;
3982 desc
->opts1
= cpu_to_le32(DescOwn
| eor
| rx_buf_sz
);
3985 static inline void rtl8169_map_to_asic(struct RxDesc
*desc
, dma_addr_t mapping
,
3988 desc
->addr
= cpu_to_le64(mapping
);
3990 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
3993 static struct sk_buff
*rtl8169_alloc_rx_skb(struct pci_dev
*pdev
,
3994 struct net_device
*dev
,
3995 struct RxDesc
*desc
, int rx_buf_sz
,
3998 struct sk_buff
*skb
;
4002 pad
= align
? align
: NET_IP_ALIGN
;
4004 skb
= netdev_alloc_skb(dev
, rx_buf_sz
+ pad
);
4008 skb_reserve(skb
, align
? ((pad
- 1) & (unsigned long)skb
->data
) : pad
);
4010 mapping
= pci_map_single(pdev
, skb
->data
, rx_buf_sz
,
4011 PCI_DMA_FROMDEVICE
);
4013 rtl8169_map_to_asic(desc
, mapping
, rx_buf_sz
);
4018 rtl8169_make_unusable_by_asic(desc
);
4022 static void rtl8169_rx_clear(struct rtl8169_private
*tp
)
4026 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
4027 if (tp
->Rx_skbuff
[i
]) {
4028 rtl8169_free_rx_skb(tp
, tp
->Rx_skbuff
+ i
,
4029 tp
->RxDescArray
+ i
);
4034 static u32
rtl8169_rx_fill(struct rtl8169_private
*tp
, struct net_device
*dev
,
4039 for (cur
= start
; end
- cur
!= 0; cur
++) {
4040 struct sk_buff
*skb
;
4041 unsigned int i
= cur
% NUM_RX_DESC
;
4043 WARN_ON((s32
)(end
- cur
) < 0);
4045 if (tp
->Rx_skbuff
[i
])
4048 skb
= rtl8169_alloc_rx_skb(tp
->pci_dev
, dev
,
4049 tp
->RxDescArray
+ i
,
4050 tp
->rx_buf_sz
, tp
->align
);
4054 tp
->Rx_skbuff
[i
] = skb
;
4059 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc
*desc
)
4061 desc
->opts1
|= cpu_to_le32(RingEnd
);
4064 static void rtl8169_init_ring_indexes(struct rtl8169_private
*tp
)
4066 tp
->dirty_tx
= tp
->dirty_rx
= tp
->cur_tx
= tp
->cur_rx
= 0;
4069 static int rtl8169_init_ring(struct net_device
*dev
)
4071 struct rtl8169_private
*tp
= netdev_priv(dev
);
4073 rtl8169_init_ring_indexes(tp
);
4075 memset(tp
->tx_skb
, 0x0, NUM_TX_DESC
* sizeof(struct ring_info
));
4076 memset(tp
->Rx_skbuff
, 0x0, NUM_RX_DESC
* sizeof(struct sk_buff
*));
4078 if (rtl8169_rx_fill(tp
, dev
, 0, NUM_RX_DESC
) != NUM_RX_DESC
)
4081 rtl8169_mark_as_last_descriptor(tp
->RxDescArray
+ NUM_RX_DESC
- 1);
4086 rtl8169_rx_clear(tp
);
4090 static void rtl8169_unmap_tx_skb(struct pci_dev
*pdev
, struct ring_info
*tx_skb
,
4091 struct TxDesc
*desc
)
4093 unsigned int len
= tx_skb
->len
;
4095 pci_unmap_single(pdev
, le64_to_cpu(desc
->addr
), len
, PCI_DMA_TODEVICE
);
4102 static void rtl8169_tx_clear(struct rtl8169_private
*tp
)
4106 for (i
= tp
->dirty_tx
; i
< tp
->dirty_tx
+ NUM_TX_DESC
; i
++) {
4107 unsigned int entry
= i
% NUM_TX_DESC
;
4108 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
4109 unsigned int len
= tx_skb
->len
;
4112 struct sk_buff
*skb
= tx_skb
->skb
;
4114 rtl8169_unmap_tx_skb(tp
->pci_dev
, tx_skb
,
4115 tp
->TxDescArray
+ entry
);
4120 tp
->dev
->stats
.tx_dropped
++;
4123 tp
->cur_tx
= tp
->dirty_tx
= 0;
4126 static void rtl8169_schedule_work(struct net_device
*dev
, work_func_t task
)
4128 struct rtl8169_private
*tp
= netdev_priv(dev
);
4130 PREPARE_DELAYED_WORK(&tp
->task
, task
);
4131 schedule_delayed_work(&tp
->task
, 4);
4134 static void rtl8169_wait_for_quiescence(struct net_device
*dev
)
4136 struct rtl8169_private
*tp
= netdev_priv(dev
);
4137 void __iomem
*ioaddr
= tp
->mmio_addr
;
4139 synchronize_irq(dev
->irq
);
4141 /* Wait for any pending NAPI task to complete */
4142 napi_disable(&tp
->napi
);
4144 rtl8169_irq_mask_and_ack(ioaddr
);
4146 tp
->intr_mask
= 0xffff;
4147 RTL_W16(IntrMask
, tp
->intr_event
);
4148 napi_enable(&tp
->napi
);
4151 static void rtl8169_reinit_task(struct work_struct
*work
)
4153 struct rtl8169_private
*tp
=
4154 container_of(work
, struct rtl8169_private
, task
.work
);
4155 struct net_device
*dev
= tp
->dev
;
4160 if (!netif_running(dev
))
4163 rtl8169_wait_for_quiescence(dev
);
4166 ret
= rtl8169_open(dev
);
4167 if (unlikely(ret
< 0)) {
4168 if (net_ratelimit())
4169 netif_err(tp
, drv
, dev
,
4170 "reinit failure (status = %d). Rescheduling\n",
4172 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
4179 static void rtl8169_reset_task(struct work_struct
*work
)
4181 struct rtl8169_private
*tp
=
4182 container_of(work
, struct rtl8169_private
, task
.work
);
4183 struct net_device
*dev
= tp
->dev
;
4187 if (!netif_running(dev
))
4190 rtl8169_wait_for_quiescence(dev
);
4192 rtl8169_rx_interrupt(dev
, tp
, tp
->mmio_addr
, ~(u32
)0);
4193 rtl8169_tx_clear(tp
);
4195 if (tp
->dirty_rx
== tp
->cur_rx
) {
4196 rtl8169_init_ring_indexes(tp
);
4198 netif_wake_queue(dev
);
4199 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
4201 if (net_ratelimit())
4202 netif_emerg(tp
, intr
, dev
, "Rx buffers shortage\n");
4203 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
4210 static void rtl8169_tx_timeout(struct net_device
*dev
)
4212 struct rtl8169_private
*tp
= netdev_priv(dev
);
4214 rtl8169_hw_reset(tp
->mmio_addr
);
4216 /* Let's wait a bit while any (async) irq lands on */
4217 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
4220 static int rtl8169_xmit_frags(struct rtl8169_private
*tp
, struct sk_buff
*skb
,
4223 struct skb_shared_info
*info
= skb_shinfo(skb
);
4224 unsigned int cur_frag
, entry
;
4225 struct TxDesc
* uninitialized_var(txd
);
4228 for (cur_frag
= 0; cur_frag
< info
->nr_frags
; cur_frag
++) {
4229 skb_frag_t
*frag
= info
->frags
+ cur_frag
;
4234 entry
= (entry
+ 1) % NUM_TX_DESC
;
4236 txd
= tp
->TxDescArray
+ entry
;
4238 addr
= ((void *) page_address(frag
->page
)) + frag
->page_offset
;
4239 mapping
= pci_map_single(tp
->pci_dev
, addr
, len
, PCI_DMA_TODEVICE
);
4241 /* anti gcc 2.95.3 bugware (sic) */
4242 status
= opts1
| len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
4244 txd
->opts1
= cpu_to_le32(status
);
4245 txd
->addr
= cpu_to_le64(mapping
);
4247 tp
->tx_skb
[entry
].len
= len
;
4251 tp
->tx_skb
[entry
].skb
= skb
;
4252 txd
->opts1
|= cpu_to_le32(LastFrag
);
4258 static inline u32
rtl8169_tso_csum(struct sk_buff
*skb
, struct net_device
*dev
)
4260 if (dev
->features
& NETIF_F_TSO
) {
4261 u32 mss
= skb_shinfo(skb
)->gso_size
;
4264 return LargeSend
| ((mss
& MSSMask
) << MSSShift
);
4266 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
4267 const struct iphdr
*ip
= ip_hdr(skb
);
4269 if (ip
->protocol
== IPPROTO_TCP
)
4270 return IPCS
| TCPCS
;
4271 else if (ip
->protocol
== IPPROTO_UDP
)
4272 return IPCS
| UDPCS
;
4273 WARN_ON(1); /* we need a WARN() */
4278 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
4279 struct net_device
*dev
)
4281 struct rtl8169_private
*tp
= netdev_priv(dev
);
4282 unsigned int frags
, entry
= tp
->cur_tx
% NUM_TX_DESC
;
4283 struct TxDesc
*txd
= tp
->TxDescArray
+ entry
;
4284 void __iomem
*ioaddr
= tp
->mmio_addr
;
4289 if (unlikely(TX_BUFFS_AVAIL(tp
) < skb_shinfo(skb
)->nr_frags
)) {
4290 netif_err(tp
, drv
, dev
, "BUG! Tx Ring full when queue awake!\n");
4294 if (unlikely(le32_to_cpu(txd
->opts1
) & DescOwn
))
4297 opts1
= DescOwn
| rtl8169_tso_csum(skb
, dev
);
4299 frags
= rtl8169_xmit_frags(tp
, skb
, opts1
);
4301 len
= skb_headlen(skb
);
4305 opts1
|= FirstFrag
| LastFrag
;
4306 tp
->tx_skb
[entry
].skb
= skb
;
4309 mapping
= pci_map_single(tp
->pci_dev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
4311 tp
->tx_skb
[entry
].len
= len
;
4312 txd
->addr
= cpu_to_le64(mapping
);
4313 txd
->opts2
= cpu_to_le32(rtl8169_tx_vlan_tag(tp
, skb
));
4317 /* anti gcc 2.95.3 bugware (sic) */
4318 status
= opts1
| len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
4319 txd
->opts1
= cpu_to_le32(status
);
4321 tp
->cur_tx
+= frags
+ 1;
4325 RTL_W8(TxPoll
, NPQ
); /* set polling bit */
4327 if (TX_BUFFS_AVAIL(tp
) < MAX_SKB_FRAGS
) {
4328 netif_stop_queue(dev
);
4330 if (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)
4331 netif_wake_queue(dev
);
4334 return NETDEV_TX_OK
;
4337 netif_stop_queue(dev
);
4338 dev
->stats
.tx_dropped
++;
4339 return NETDEV_TX_BUSY
;
4342 static void rtl8169_pcierr_interrupt(struct net_device
*dev
)
4344 struct rtl8169_private
*tp
= netdev_priv(dev
);
4345 struct pci_dev
*pdev
= tp
->pci_dev
;
4346 void __iomem
*ioaddr
= tp
->mmio_addr
;
4347 u16 pci_status
, pci_cmd
;
4349 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
4350 pci_read_config_word(pdev
, PCI_STATUS
, &pci_status
);
4352 netif_err(tp
, intr
, dev
, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4353 pci_cmd
, pci_status
);
4356 * The recovery sequence below admits a very elaborated explanation:
4357 * - it seems to work;
4358 * - I did not see what else could be done;
4359 * - it makes iop3xx happy.
4361 * Feel free to adjust to your needs.
4363 if (pdev
->broken_parity_status
)
4364 pci_cmd
&= ~PCI_COMMAND_PARITY
;
4366 pci_cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
;
4368 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
4370 pci_write_config_word(pdev
, PCI_STATUS
,
4371 pci_status
& (PCI_STATUS_DETECTED_PARITY
|
4372 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_REC_MASTER_ABORT
|
4373 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_SIG_TARGET_ABORT
));
4375 /* The infamous DAC f*ckup only happens at boot time */
4376 if ((tp
->cp_cmd
& PCIDAC
) && !tp
->dirty_rx
&& !tp
->cur_rx
) {
4377 netif_info(tp
, intr
, dev
, "disabling PCI DAC\n");
4378 tp
->cp_cmd
&= ~PCIDAC
;
4379 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
4380 dev
->features
&= ~NETIF_F_HIGHDMA
;
4383 rtl8169_hw_reset(ioaddr
);
4385 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
4388 static void rtl8169_tx_interrupt(struct net_device
*dev
,
4389 struct rtl8169_private
*tp
,
4390 void __iomem
*ioaddr
)
4392 unsigned int dirty_tx
, tx_left
;
4394 dirty_tx
= tp
->dirty_tx
;
4396 tx_left
= tp
->cur_tx
- dirty_tx
;
4398 while (tx_left
> 0) {
4399 unsigned int entry
= dirty_tx
% NUM_TX_DESC
;
4400 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
4401 u32 len
= tx_skb
->len
;
4405 status
= le32_to_cpu(tp
->TxDescArray
[entry
].opts1
);
4406 if (status
& DescOwn
)
4409 dev
->stats
.tx_bytes
+= len
;
4410 dev
->stats
.tx_packets
++;
4412 rtl8169_unmap_tx_skb(tp
->pci_dev
, tx_skb
, tp
->TxDescArray
+ entry
);
4414 if (status
& LastFrag
) {
4415 dev_kfree_skb(tx_skb
->skb
);
4422 if (tp
->dirty_tx
!= dirty_tx
) {
4423 tp
->dirty_tx
= dirty_tx
;
4425 if (netif_queue_stopped(dev
) &&
4426 (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)) {
4427 netif_wake_queue(dev
);
4430 * 8168 hack: TxPoll requests are lost when the Tx packets are
4431 * too close. Let's kick an extra TxPoll request when a burst
4432 * of start_xmit activity is detected (if it is not detected,
4433 * it is slow enough). -- FR
4436 if (tp
->cur_tx
!= dirty_tx
)
4437 RTL_W8(TxPoll
, NPQ
);
4441 static inline int rtl8169_fragmented_frame(u32 status
)
4443 return (status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
);
4446 static inline void rtl8169_rx_csum(struct sk_buff
*skb
, struct RxDesc
*desc
)
4448 u32 opts1
= le32_to_cpu(desc
->opts1
);
4449 u32 status
= opts1
& RxProtoMask
;
4451 if (((status
== RxProtoTCP
) && !(opts1
& TCPFail
)) ||
4452 ((status
== RxProtoUDP
) && !(opts1
& UDPFail
)) ||
4453 ((status
== RxProtoIP
) && !(opts1
& IPFail
)))
4454 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
4456 skb
->ip_summed
= CHECKSUM_NONE
;
4459 static inline bool rtl8169_try_rx_copy(struct sk_buff
**sk_buff
,
4460 struct rtl8169_private
*tp
, int pkt_size
,
4463 struct sk_buff
*skb
;
4466 if (pkt_size
>= rx_copybreak
)
4469 skb
= netdev_alloc_skb_ip_align(tp
->dev
, pkt_size
);
4473 pci_dma_sync_single_for_cpu(tp
->pci_dev
, addr
, pkt_size
,
4474 PCI_DMA_FROMDEVICE
);
4475 skb_copy_from_linear_data(*sk_buff
, skb
->data
, pkt_size
);
4483 * Warning : rtl8169_rx_interrupt() might be called :
4484 * 1) from NAPI (softirq) context
4485 * (polling = 1 : we should call netif_receive_skb())
4486 * 2) from process context (rtl8169_reset_task())
4487 * (polling = 0 : we must call netif_rx() instead)
4489 static int rtl8169_rx_interrupt(struct net_device
*dev
,
4490 struct rtl8169_private
*tp
,
4491 void __iomem
*ioaddr
, u32 budget
)
4493 unsigned int cur_rx
, rx_left
;
4494 unsigned int delta
, count
;
4495 int polling
= (budget
!= ~(u32
)0) ? 1 : 0;
4497 cur_rx
= tp
->cur_rx
;
4498 rx_left
= NUM_RX_DESC
+ tp
->dirty_rx
- cur_rx
;
4499 rx_left
= min(rx_left
, budget
);
4501 for (; rx_left
> 0; rx_left
--, cur_rx
++) {
4502 unsigned int entry
= cur_rx
% NUM_RX_DESC
;
4503 struct RxDesc
*desc
= tp
->RxDescArray
+ entry
;
4507 status
= le32_to_cpu(desc
->opts1
);
4509 if (status
& DescOwn
)
4511 if (unlikely(status
& RxRES
)) {
4512 netif_info(tp
, rx_err
, dev
, "Rx ERROR. status = %08x\n",
4514 dev
->stats
.rx_errors
++;
4515 if (status
& (RxRWT
| RxRUNT
))
4516 dev
->stats
.rx_length_errors
++;
4518 dev
->stats
.rx_crc_errors
++;
4519 if (status
& RxFOVF
) {
4520 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
4521 dev
->stats
.rx_fifo_errors
++;
4523 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
4525 struct sk_buff
*skb
= tp
->Rx_skbuff
[entry
];
4526 dma_addr_t addr
= le64_to_cpu(desc
->addr
);
4527 int pkt_size
= (status
& 0x00001FFF) - 4;
4528 struct pci_dev
*pdev
= tp
->pci_dev
;
4531 * The driver does not support incoming fragmented
4532 * frames. They are seen as a symptom of over-mtu
4535 if (unlikely(rtl8169_fragmented_frame(status
))) {
4536 dev
->stats
.rx_dropped
++;
4537 dev
->stats
.rx_length_errors
++;
4538 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
4542 rtl8169_rx_csum(skb
, desc
);
4544 if (rtl8169_try_rx_copy(&skb
, tp
, pkt_size
, addr
)) {
4545 pci_dma_sync_single_for_device(pdev
, addr
,
4546 pkt_size
, PCI_DMA_FROMDEVICE
);
4547 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
4549 pci_unmap_single(pdev
, addr
, tp
->rx_buf_sz
,
4550 PCI_DMA_FROMDEVICE
);
4551 tp
->Rx_skbuff
[entry
] = NULL
;
4554 skb_put(skb
, pkt_size
);
4555 skb
->protocol
= eth_type_trans(skb
, dev
);
4557 if (rtl8169_rx_vlan_skb(tp
, desc
, skb
, polling
) < 0) {
4558 if (likely(polling
))
4559 netif_receive_skb(skb
);
4564 dev
->stats
.rx_bytes
+= pkt_size
;
4565 dev
->stats
.rx_packets
++;
4568 /* Work around for AMD plateform. */
4569 if ((desc
->opts2
& cpu_to_le32(0xfffe000)) &&
4570 (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)) {
4576 count
= cur_rx
- tp
->cur_rx
;
4577 tp
->cur_rx
= cur_rx
;
4579 delta
= rtl8169_rx_fill(tp
, dev
, tp
->dirty_rx
, tp
->cur_rx
);
4580 if (!delta
&& count
)
4581 netif_info(tp
, intr
, dev
, "no Rx buffer allocated\n");
4582 tp
->dirty_rx
+= delta
;
4585 * FIXME: until there is periodic timer to try and refill the ring,
4586 * a temporary shortage may definitely kill the Rx process.
4587 * - disable the asic to try and avoid an overflow and kick it again
4589 * - how do others driver handle this condition (Uh oh...).
4591 if (tp
->dirty_rx
+ NUM_RX_DESC
== tp
->cur_rx
)
4592 netif_emerg(tp
, intr
, dev
, "Rx buffers exhausted\n");
4597 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
)
4599 struct net_device
*dev
= dev_instance
;
4600 struct rtl8169_private
*tp
= netdev_priv(dev
);
4601 void __iomem
*ioaddr
= tp
->mmio_addr
;
4605 /* loop handling interrupts until we have no new ones or
4606 * we hit a invalid/hotplug case.
4608 status
= RTL_R16(IntrStatus
);
4609 while (status
&& status
!= 0xffff) {
4612 /* Handle all of the error cases first. These will reset
4613 * the chip, so just exit the loop.
4615 if (unlikely(!netif_running(dev
))) {
4616 rtl8169_asic_down(ioaddr
);
4620 /* Work around for rx fifo overflow */
4621 if (unlikely(status
& RxFIFOOver
) &&
4622 (tp
->mac_version
== RTL_GIGA_MAC_VER_11
)) {
4623 netif_stop_queue(dev
);
4624 rtl8169_tx_timeout(dev
);
4628 if (unlikely(status
& SYSErr
)) {
4629 rtl8169_pcierr_interrupt(dev
);
4633 if (status
& LinkChg
)
4634 rtl8169_check_link_status(dev
, tp
, ioaddr
);
4636 /* We need to see the lastest version of tp->intr_mask to
4637 * avoid ignoring an MSI interrupt and having to wait for
4638 * another event which may never come.
4641 if (status
& tp
->intr_mask
& tp
->napi_event
) {
4642 RTL_W16(IntrMask
, tp
->intr_event
& ~tp
->napi_event
);
4643 tp
->intr_mask
= ~tp
->napi_event
;
4645 if (likely(napi_schedule_prep(&tp
->napi
)))
4646 __napi_schedule(&tp
->napi
);
4648 netif_info(tp
, intr
, dev
,
4649 "interrupt %04x in poll\n", status
);
4652 /* We only get a new MSI interrupt when all active irq
4653 * sources on the chip have been acknowledged. So, ack
4654 * everything we've seen and check if new sources have become
4655 * active to avoid blocking all interrupts from the chip.
4658 (status
& RxFIFOOver
) ? (status
| RxOverflow
) : status
);
4659 status
= RTL_R16(IntrStatus
);
4662 return IRQ_RETVAL(handled
);
4665 static int rtl8169_poll(struct napi_struct
*napi
, int budget
)
4667 struct rtl8169_private
*tp
= container_of(napi
, struct rtl8169_private
, napi
);
4668 struct net_device
*dev
= tp
->dev
;
4669 void __iomem
*ioaddr
= tp
->mmio_addr
;
4672 work_done
= rtl8169_rx_interrupt(dev
, tp
, ioaddr
, (u32
) budget
);
4673 rtl8169_tx_interrupt(dev
, tp
, ioaddr
);
4675 if (work_done
< budget
) {
4676 napi_complete(napi
);
4678 /* We need for force the visibility of tp->intr_mask
4679 * for other CPUs, as we can loose an MSI interrupt
4680 * and potentially wait for a retransmit timeout if we don't.
4681 * The posted write to IntrMask is safe, as it will
4682 * eventually make it to the chip and we won't loose anything
4685 tp
->intr_mask
= 0xffff;
4687 RTL_W16(IntrMask
, tp
->intr_event
);
4693 static void rtl8169_rx_missed(struct net_device
*dev
, void __iomem
*ioaddr
)
4695 struct rtl8169_private
*tp
= netdev_priv(dev
);
4697 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
)
4700 dev
->stats
.rx_missed_errors
+= (RTL_R32(RxMissed
) & 0xffffff);
4701 RTL_W32(RxMissed
, 0);
4704 static void rtl8169_down(struct net_device
*dev
)
4706 struct rtl8169_private
*tp
= netdev_priv(dev
);
4707 void __iomem
*ioaddr
= tp
->mmio_addr
;
4708 unsigned int intrmask
;
4710 rtl8169_delete_timer(dev
);
4712 netif_stop_queue(dev
);
4714 napi_disable(&tp
->napi
);
4717 spin_lock_irq(&tp
->lock
);
4719 rtl8169_asic_down(ioaddr
);
4721 rtl8169_rx_missed(dev
, ioaddr
);
4723 spin_unlock_irq(&tp
->lock
);
4725 synchronize_irq(dev
->irq
);
4727 /* Give a racing hard_start_xmit a few cycles to complete. */
4728 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
4731 * And now for the 50k$ question: are IRQ disabled or not ?
4733 * Two paths lead here:
4735 * -> netif_running() is available to sync the current code and the
4736 * IRQ handler. See rtl8169_interrupt for details.
4737 * 2) dev->change_mtu
4738 * -> rtl8169_poll can not be issued again and re-enable the
4739 * interruptions. Let's simply issue the IRQ down sequence again.
4741 * No loop if hotpluged or major error (0xffff).
4743 intrmask
= RTL_R16(IntrMask
);
4744 if (intrmask
&& (intrmask
!= 0xffff))
4747 rtl8169_tx_clear(tp
);
4749 rtl8169_rx_clear(tp
);
4752 static int rtl8169_close(struct net_device
*dev
)
4754 struct rtl8169_private
*tp
= netdev_priv(dev
);
4755 struct pci_dev
*pdev
= tp
->pci_dev
;
4757 pm_runtime_get_sync(&pdev
->dev
);
4759 /* update counters before going down */
4760 rtl8169_update_counters(dev
);
4764 free_irq(dev
->irq
, dev
);
4766 pci_free_consistent(pdev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
4768 pci_free_consistent(pdev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
4770 tp
->TxDescArray
= NULL
;
4771 tp
->RxDescArray
= NULL
;
4773 pm_runtime_put_sync(&pdev
->dev
);
4778 static void rtl_set_rx_mode(struct net_device
*dev
)
4780 struct rtl8169_private
*tp
= netdev_priv(dev
);
4781 void __iomem
*ioaddr
= tp
->mmio_addr
;
4782 unsigned long flags
;
4783 u32 mc_filter
[2]; /* Multicast hash filter */
4787 if (dev
->flags
& IFF_PROMISC
) {
4788 /* Unconditionally log net taps. */
4789 netif_notice(tp
, link
, dev
, "Promiscuous mode enabled\n");
4791 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
|
4793 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
4794 } else if ((netdev_mc_count(dev
) > multicast_filter_limit
) ||
4795 (dev
->flags
& IFF_ALLMULTI
)) {
4796 /* Too many to filter perfectly -- accept all multicasts. */
4797 rx_mode
= AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
;
4798 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
4800 struct netdev_hw_addr
*ha
;
4802 rx_mode
= AcceptBroadcast
| AcceptMyPhys
;
4803 mc_filter
[1] = mc_filter
[0] = 0;
4804 netdev_for_each_mc_addr(ha
, dev
) {
4805 int bit_nr
= ether_crc(ETH_ALEN
, ha
->addr
) >> 26;
4806 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
4807 rx_mode
|= AcceptMulticast
;
4811 spin_lock_irqsave(&tp
->lock
, flags
);
4813 tmp
= rtl8169_rx_config
| rx_mode
|
4814 (RTL_R32(RxConfig
) & rtl_chip_info
[tp
->chipset
].RxConfigMask
);
4816 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
) {
4817 u32 data
= mc_filter
[0];
4819 mc_filter
[0] = swab32(mc_filter
[1]);
4820 mc_filter
[1] = swab32(data
);
4823 RTL_W32(MAR0
+ 4, mc_filter
[1]);
4824 RTL_W32(MAR0
+ 0, mc_filter
[0]);
4826 RTL_W32(RxConfig
, tmp
);
4828 spin_unlock_irqrestore(&tp
->lock
, flags
);
4832 * rtl8169_get_stats - Get rtl8169 read/write statistics
4833 * @dev: The Ethernet Device to get statistics for
4835 * Get TX/RX statistics for rtl8169
4837 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
)
4839 struct rtl8169_private
*tp
= netdev_priv(dev
);
4840 void __iomem
*ioaddr
= tp
->mmio_addr
;
4841 unsigned long flags
;
4843 if (netif_running(dev
)) {
4844 spin_lock_irqsave(&tp
->lock
, flags
);
4845 rtl8169_rx_missed(dev
, ioaddr
);
4846 spin_unlock_irqrestore(&tp
->lock
, flags
);
4852 static void rtl8169_net_suspend(struct net_device
*dev
)
4854 if (!netif_running(dev
))
4857 netif_device_detach(dev
);
4858 netif_stop_queue(dev
);
4863 static int rtl8169_suspend(struct device
*device
)
4865 struct pci_dev
*pdev
= to_pci_dev(device
);
4866 struct net_device
*dev
= pci_get_drvdata(pdev
);
4868 rtl8169_net_suspend(dev
);
4873 static void __rtl8169_resume(struct net_device
*dev
)
4875 netif_device_attach(dev
);
4876 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
4879 static int rtl8169_resume(struct device
*device
)
4881 struct pci_dev
*pdev
= to_pci_dev(device
);
4882 struct net_device
*dev
= pci_get_drvdata(pdev
);
4884 if (netif_running(dev
))
4885 __rtl8169_resume(dev
);
4890 static int rtl8169_runtime_suspend(struct device
*device
)
4892 struct pci_dev
*pdev
= to_pci_dev(device
);
4893 struct net_device
*dev
= pci_get_drvdata(pdev
);
4894 struct rtl8169_private
*tp
= netdev_priv(dev
);
4896 if (!tp
->TxDescArray
)
4899 spin_lock_irq(&tp
->lock
);
4900 tp
->saved_wolopts
= __rtl8169_get_wol(tp
);
4901 __rtl8169_set_wol(tp
, WAKE_ANY
);
4902 spin_unlock_irq(&tp
->lock
);
4904 rtl8169_net_suspend(dev
);
4909 static int rtl8169_runtime_resume(struct device
*device
)
4911 struct pci_dev
*pdev
= to_pci_dev(device
);
4912 struct net_device
*dev
= pci_get_drvdata(pdev
);
4913 struct rtl8169_private
*tp
= netdev_priv(dev
);
4915 if (!tp
->TxDescArray
)
4918 spin_lock_irq(&tp
->lock
);
4919 __rtl8169_set_wol(tp
, tp
->saved_wolopts
);
4920 tp
->saved_wolopts
= 0;
4921 spin_unlock_irq(&tp
->lock
);
4923 __rtl8169_resume(dev
);
4928 static int rtl8169_runtime_idle(struct device
*device
)
4930 struct pci_dev
*pdev
= to_pci_dev(device
);
4931 struct net_device
*dev
= pci_get_drvdata(pdev
);
4932 struct rtl8169_private
*tp
= netdev_priv(dev
);
4934 if (!tp
->TxDescArray
)
4937 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
4941 static const struct dev_pm_ops rtl8169_pm_ops
= {
4942 .suspend
= rtl8169_suspend
,
4943 .resume
= rtl8169_resume
,
4944 .freeze
= rtl8169_suspend
,
4945 .thaw
= rtl8169_resume
,
4946 .poweroff
= rtl8169_suspend
,
4947 .restore
= rtl8169_resume
,
4948 .runtime_suspend
= rtl8169_runtime_suspend
,
4949 .runtime_resume
= rtl8169_runtime_resume
,
4950 .runtime_idle
= rtl8169_runtime_idle
,
4953 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
4955 #else /* !CONFIG_PM */
4957 #define RTL8169_PM_OPS NULL
4959 #endif /* !CONFIG_PM */
4961 static void rtl_shutdown(struct pci_dev
*pdev
)
4963 struct net_device
*dev
= pci_get_drvdata(pdev
);
4964 struct rtl8169_private
*tp
= netdev_priv(dev
);
4965 void __iomem
*ioaddr
= tp
->mmio_addr
;
4967 rtl8169_net_suspend(dev
);
4969 /* restore original MAC address */
4970 rtl_rar_set(tp
, dev
->perm_addr
);
4972 spin_lock_irq(&tp
->lock
);
4974 rtl8169_asic_down(ioaddr
);
4976 spin_unlock_irq(&tp
->lock
);
4978 if (system_state
== SYSTEM_POWER_OFF
) {
4979 /* WoL fails with some 8168 when the receiver is disabled. */
4980 if (tp
->features
& RTL_FEATURE_WOL
) {
4981 pci_clear_master(pdev
);
4983 RTL_W8(ChipCmd
, CmdRxEnb
);
4988 pci_wake_from_d3(pdev
, true);
4989 pci_set_power_state(pdev
, PCI_D3hot
);
4993 static struct pci_driver rtl8169_pci_driver
= {
4995 .id_table
= rtl8169_pci_tbl
,
4996 .probe
= rtl8169_init_one
,
4997 .remove
= __devexit_p(rtl8169_remove_one
),
4998 .shutdown
= rtl_shutdown
,
4999 .driver
.pm
= RTL8169_PM_OPS
,
5002 static int __init
rtl8169_init_module(void)
5004 return pci_register_driver(&rtl8169_pci_driver
);
5007 static void __exit
rtl8169_cleanup_module(void)
5009 pci_unregister_driver(&rtl8169_pci_driver
);
5012 module_init(rtl8169_init_module
);
5013 module_exit(rtl8169_cleanup_module
);