1 /************************************************************************
2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3 * Copyright(c) 2002-2010 Exar Corp.
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
21 * Francois Romieu : For pointing out all code part that were
22 * deprecated and also styling related comments.
23 * Grant Grundler : For helping me get rid of some Architecture
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
27 * The module loadable parameters that are supported by the driver and a brief
28 * explanation of all the variables.
30 * rx_ring_num : This can be used to program the number of receive rings used
32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
38 * Tx descriptors that can be associated with each corresponding FIFO.
39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40 * 2(MSI_X). Default value is '2(MSI_X)'
41 * lro_max_pkts: This parameter defines maximum number of packets can be
42 * aggregated as a single large packet
43 * napi: This parameter used to enable/disable NAPI (polling Rx)
44 * Possible values '1' for enable and '0' for disable. Default is '1'
45 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
46 * Possible values '1' for enable and '0' for disable. Default is '0'
47 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
48 * Possible values '1' for enable , '0' for disable.
49 * Default is '2' - which means disable in promisc mode
50 * and enable in non-promiscuous mode.
51 * multiq: This parameter used to enable/disable MULTIQUEUE support.
52 * Possible values '1' for enable and '0' for disable. Default is '0'
53 ************************************************************************/
55 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
57 #include <linux/module.h>
58 #include <linux/types.h>
59 #include <linux/errno.h>
60 #include <linux/ioport.h>
61 #include <linux/pci.h>
62 #include <linux/dma-mapping.h>
63 #include <linux/kernel.h>
64 #include <linux/netdevice.h>
65 #include <linux/etherdevice.h>
66 #include <linux/mdio.h>
67 #include <linux/skbuff.h>
68 #include <linux/init.h>
69 #include <linux/delay.h>
70 #include <linux/stddef.h>
71 #include <linux/ioctl.h>
72 #include <linux/timex.h>
73 #include <linux/ethtool.h>
74 #include <linux/workqueue.h>
75 #include <linux/if_vlan.h>
77 #include <linux/tcp.h>
78 #include <linux/uaccess.h>
80 #include <linux/slab.h>
81 #include <linux/prefetch.h>
84 #include <asm/system.h>
85 #include <asm/div64.h>
90 #include "s2io-regs.h"
92 #define DRV_VERSION "2.0.26.28"
94 /* S2io Driver name & version. */
95 static const char s2io_driver_name
[] = "Neterion";
96 static const char s2io_driver_version
[] = DRV_VERSION
;
98 static const int rxd_size
[2] = {32, 48};
99 static const int rxd_count
[2] = {127, 85};
101 static inline int RXD_IS_UP2DT(struct RxD_t
*rxdp
)
105 ret
= ((!(rxdp
->Control_1
& RXD_OWN_XENA
)) &&
106 (GET_RXD_MARKER(rxdp
->Control_2
) != THE_RXD_MARK
));
112 * Cards with following subsystem_id have a link state indication
113 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
114 * macro below identifies these cards given the subsystem_id.
116 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
117 (dev_type == XFRAME_I_DEVICE) ? \
118 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
119 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
121 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
122 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
124 static inline int is_s2io_card_up(const struct s2io_nic
*sp
)
126 return test_bit(__S2IO_STATE_CARD_UP
, &sp
->state
);
129 /* Ethtool related variables and Macros. */
130 static const char s2io_gstrings
[][ETH_GSTRING_LEN
] = {
131 "Register test\t(offline)",
132 "Eeprom test\t(offline)",
133 "Link test\t(online)",
134 "RLDRAM test\t(offline)",
135 "BIST Test\t(offline)"
138 static const char ethtool_xena_stats_keys
[][ETH_GSTRING_LEN
] = {
140 {"tmac_data_octets"},
144 {"tmac_pause_ctrl_frms"},
148 {"tmac_any_err_frms"},
149 {"tmac_ttl_less_fb_octets"},
150 {"tmac_vld_ip_octets"},
158 {"rmac_data_octets"},
159 {"rmac_fcs_err_frms"},
161 {"rmac_vld_mcst_frms"},
162 {"rmac_vld_bcst_frms"},
163 {"rmac_in_rng_len_err_frms"},
164 {"rmac_out_rng_len_err_frms"},
166 {"rmac_pause_ctrl_frms"},
167 {"rmac_unsup_ctrl_frms"},
169 {"rmac_accepted_ucst_frms"},
170 {"rmac_accepted_nucst_frms"},
171 {"rmac_discarded_frms"},
172 {"rmac_drop_events"},
173 {"rmac_ttl_less_fb_octets"},
175 {"rmac_usized_frms"},
176 {"rmac_osized_frms"},
178 {"rmac_jabber_frms"},
179 {"rmac_ttl_64_frms"},
180 {"rmac_ttl_65_127_frms"},
181 {"rmac_ttl_128_255_frms"},
182 {"rmac_ttl_256_511_frms"},
183 {"rmac_ttl_512_1023_frms"},
184 {"rmac_ttl_1024_1518_frms"},
192 {"rmac_err_drp_udp"},
193 {"rmac_xgmii_err_sym"},
211 {"rmac_xgmii_data_err_cnt"},
212 {"rmac_xgmii_ctrl_err_cnt"},
213 {"rmac_accepted_ip"},
217 {"new_rd_req_rtry_cnt"},
219 {"wr_rtry_rd_ack_cnt"},
222 {"new_wr_req_rtry_cnt"},
225 {"rd_rtry_wr_ack_cnt"},
235 static const char ethtool_enhanced_stats_keys
[][ETH_GSTRING_LEN
] = {
236 {"rmac_ttl_1519_4095_frms"},
237 {"rmac_ttl_4096_8191_frms"},
238 {"rmac_ttl_8192_max_frms"},
239 {"rmac_ttl_gt_max_frms"},
240 {"rmac_osized_alt_frms"},
241 {"rmac_jabber_alt_frms"},
242 {"rmac_gt_max_alt_frms"},
244 {"rmac_len_discard"},
245 {"rmac_fcs_discard"},
248 {"rmac_red_discard"},
249 {"rmac_rts_discard"},
250 {"rmac_ingm_full_discard"},
254 static const char ethtool_driver_stats_keys
[][ETH_GSTRING_LEN
] = {
255 {"\n DRIVER STATISTICS"},
256 {"single_bit_ecc_errs"},
257 {"double_bit_ecc_errs"},
270 {"alarm_transceiver_temp_high"},
271 {"alarm_transceiver_temp_low"},
272 {"alarm_laser_bias_current_high"},
273 {"alarm_laser_bias_current_low"},
274 {"alarm_laser_output_power_high"},
275 {"alarm_laser_output_power_low"},
276 {"warn_transceiver_temp_high"},
277 {"warn_transceiver_temp_low"},
278 {"warn_laser_bias_current_high"},
279 {"warn_laser_bias_current_low"},
280 {"warn_laser_output_power_high"},
281 {"warn_laser_output_power_low"},
282 {"lro_aggregated_pkts"},
283 {"lro_flush_both_count"},
284 {"lro_out_of_sequence_pkts"},
285 {"lro_flush_due_to_max_pkts"},
286 {"lro_avg_aggr_pkts"},
287 {"mem_alloc_fail_cnt"},
288 {"pci_map_fail_cnt"},
289 {"watchdog_timer_cnt"},
296 {"tx_tcode_buf_abort_cnt"},
297 {"tx_tcode_desc_abort_cnt"},
298 {"tx_tcode_parity_err_cnt"},
299 {"tx_tcode_link_loss_cnt"},
300 {"tx_tcode_list_proc_err_cnt"},
301 {"rx_tcode_parity_err_cnt"},
302 {"rx_tcode_abort_cnt"},
303 {"rx_tcode_parity_abort_cnt"},
304 {"rx_tcode_rda_fail_cnt"},
305 {"rx_tcode_unkn_prot_cnt"},
306 {"rx_tcode_fcs_err_cnt"},
307 {"rx_tcode_buf_size_err_cnt"},
308 {"rx_tcode_rxd_corrupt_cnt"},
309 {"rx_tcode_unkn_err_cnt"},
317 {"mac_tmac_err_cnt"},
318 {"mac_rmac_err_cnt"},
319 {"xgxs_txgxs_err_cnt"},
320 {"xgxs_rxgxs_err_cnt"},
322 {"prc_pcix_err_cnt"},
329 #define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys)
330 #define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys)
331 #define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys)
333 #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN)
334 #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN)
336 #define XFRAME_I_STAT_STRINGS_LEN (XFRAME_I_STAT_LEN * ETH_GSTRING_LEN)
337 #define XFRAME_II_STAT_STRINGS_LEN (XFRAME_II_STAT_LEN * ETH_GSTRING_LEN)
339 #define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings)
340 #define S2IO_STRINGS_LEN (S2IO_TEST_LEN * ETH_GSTRING_LEN)
342 #define S2IO_TIMER_CONF(timer, handle, arg, exp) \
343 init_timer(&timer); \
344 timer.function = handle; \
345 timer.data = (unsigned long)arg; \
346 mod_timer(&timer, (jiffies + exp)) \
348 /* copy mac addr to def_mac_addr array */
349 static void do_s2io_copy_mac_addr(struct s2io_nic
*sp
, int offset
, u64 mac_addr
)
351 sp
->def_mac_addr
[offset
].mac_addr
[5] = (u8
) (mac_addr
);
352 sp
->def_mac_addr
[offset
].mac_addr
[4] = (u8
) (mac_addr
>> 8);
353 sp
->def_mac_addr
[offset
].mac_addr
[3] = (u8
) (mac_addr
>> 16);
354 sp
->def_mac_addr
[offset
].mac_addr
[2] = (u8
) (mac_addr
>> 24);
355 sp
->def_mac_addr
[offset
].mac_addr
[1] = (u8
) (mac_addr
>> 32);
356 sp
->def_mac_addr
[offset
].mac_addr
[0] = (u8
) (mac_addr
>> 40);
360 static void s2io_vlan_rx_register(struct net_device
*dev
,
361 struct vlan_group
*grp
)
364 struct s2io_nic
*nic
= netdev_priv(dev
);
365 unsigned long flags
[MAX_TX_FIFOS
];
366 struct config_param
*config
= &nic
->config
;
367 struct mac_info
*mac_control
= &nic
->mac_control
;
369 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
370 struct fifo_info
*fifo
= &mac_control
->fifos
[i
];
372 spin_lock_irqsave(&fifo
->tx_lock
, flags
[i
]);
377 for (i
= config
->tx_fifo_num
- 1; i
>= 0; i
--) {
378 struct fifo_info
*fifo
= &mac_control
->fifos
[i
];
380 spin_unlock_irqrestore(&fifo
->tx_lock
, flags
[i
]);
384 /* Unregister the vlan */
385 static void s2io_vlan_rx_kill_vid(struct net_device
*dev
, unsigned short vid
)
388 struct s2io_nic
*nic
= netdev_priv(dev
);
389 unsigned long flags
[MAX_TX_FIFOS
];
390 struct config_param
*config
= &nic
->config
;
391 struct mac_info
*mac_control
= &nic
->mac_control
;
393 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
394 struct fifo_info
*fifo
= &mac_control
->fifos
[i
];
396 spin_lock_irqsave(&fifo
->tx_lock
, flags
[i
]);
400 vlan_group_set_device(nic
->vlgrp
, vid
, NULL
);
402 for (i
= config
->tx_fifo_num
- 1; i
>= 0; i
--) {
403 struct fifo_info
*fifo
= &mac_control
->fifos
[i
];
405 spin_unlock_irqrestore(&fifo
->tx_lock
, flags
[i
]);
410 * Constants to be programmed into the Xena's registers, to configure
415 static const u64 herc_act_dtx_cfg
[] = {
417 0x8000051536750000ULL
, 0x80000515367500E0ULL
,
419 0x8000051536750004ULL
, 0x80000515367500E4ULL
,
421 0x80010515003F0000ULL
, 0x80010515003F00E0ULL
,
423 0x80010515003F0004ULL
, 0x80010515003F00E4ULL
,
425 0x801205150D440000ULL
, 0x801205150D4400E0ULL
,
427 0x801205150D440004ULL
, 0x801205150D4400E4ULL
,
429 0x80020515F2100000ULL
, 0x80020515F21000E0ULL
,
431 0x80020515F2100004ULL
, 0x80020515F21000E4ULL
,
436 static const u64 xena_dtx_cfg
[] = {
438 0x8000051500000000ULL
, 0x80000515000000E0ULL
,
440 0x80000515D9350004ULL
, 0x80000515D93500E4ULL
,
442 0x8001051500000000ULL
, 0x80010515000000E0ULL
,
444 0x80010515001E0004ULL
, 0x80010515001E00E4ULL
,
446 0x8002051500000000ULL
, 0x80020515000000E0ULL
,
448 0x80020515F2100004ULL
, 0x80020515F21000E4ULL
,
453 * Constants for Fixing the MacAddress problem seen mostly on
456 static const u64 fix_mac
[] = {
457 0x0060000000000000ULL
, 0x0060600000000000ULL
,
458 0x0040600000000000ULL
, 0x0000600000000000ULL
,
459 0x0020600000000000ULL
, 0x0060600000000000ULL
,
460 0x0020600000000000ULL
, 0x0060600000000000ULL
,
461 0x0020600000000000ULL
, 0x0060600000000000ULL
,
462 0x0020600000000000ULL
, 0x0060600000000000ULL
,
463 0x0020600000000000ULL
, 0x0060600000000000ULL
,
464 0x0020600000000000ULL
, 0x0060600000000000ULL
,
465 0x0020600000000000ULL
, 0x0060600000000000ULL
,
466 0x0020600000000000ULL
, 0x0060600000000000ULL
,
467 0x0020600000000000ULL
, 0x0060600000000000ULL
,
468 0x0020600000000000ULL
, 0x0060600000000000ULL
,
469 0x0020600000000000ULL
, 0x0000600000000000ULL
,
470 0x0040600000000000ULL
, 0x0060600000000000ULL
,
474 MODULE_LICENSE("GPL");
475 MODULE_VERSION(DRV_VERSION
);
478 /* Module Loadable parameters. */
479 S2IO_PARM_INT(tx_fifo_num
, FIFO_DEFAULT_NUM
);
480 S2IO_PARM_INT(rx_ring_num
, 1);
481 S2IO_PARM_INT(multiq
, 0);
482 S2IO_PARM_INT(rx_ring_mode
, 1);
483 S2IO_PARM_INT(use_continuous_tx_intrs
, 1);
484 S2IO_PARM_INT(rmac_pause_time
, 0x100);
485 S2IO_PARM_INT(mc_pause_threshold_q0q3
, 187);
486 S2IO_PARM_INT(mc_pause_threshold_q4q7
, 187);
487 S2IO_PARM_INT(shared_splits
, 0);
488 S2IO_PARM_INT(tmac_util_period
, 5);
489 S2IO_PARM_INT(rmac_util_period
, 5);
490 S2IO_PARM_INT(l3l4hdr_size
, 128);
491 /* 0 is no steering, 1 is Priority steering, 2 is Default steering */
492 S2IO_PARM_INT(tx_steering_type
, TX_DEFAULT_STEERING
);
493 /* Frequency of Rx desc syncs expressed as power of 2 */
494 S2IO_PARM_INT(rxsync_frequency
, 3);
495 /* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
496 S2IO_PARM_INT(intr_type
, 2);
497 /* Large receive offload feature */
499 /* Max pkts to be aggregated by LRO at one time. If not specified,
500 * aggregation happens until we hit max IP pkt size(64K)
502 S2IO_PARM_INT(lro_max_pkts
, 0xFFFF);
503 S2IO_PARM_INT(indicate_max_pkts
, 0);
505 S2IO_PARM_INT(napi
, 1);
506 S2IO_PARM_INT(ufo
, 0);
507 S2IO_PARM_INT(vlan_tag_strip
, NO_STRIP_IN_PROMISC
);
509 static unsigned int tx_fifo_len
[MAX_TX_FIFOS
] =
510 {DEFAULT_FIFO_0_LEN
, [1 ...(MAX_TX_FIFOS
- 1)] = DEFAULT_FIFO_1_7_LEN
};
511 static unsigned int rx_ring_sz
[MAX_RX_RINGS
] =
512 {[0 ...(MAX_RX_RINGS
- 1)] = SMALL_BLK_CNT
};
513 static unsigned int rts_frm_len
[MAX_RX_RINGS
] =
514 {[0 ...(MAX_RX_RINGS
- 1)] = 0 };
516 module_param_array(tx_fifo_len
, uint
, NULL
, 0);
517 module_param_array(rx_ring_sz
, uint
, NULL
, 0);
518 module_param_array(rts_frm_len
, uint
, NULL
, 0);
522 * This table lists all the devices that this driver supports.
524 static DEFINE_PCI_DEVICE_TABLE(s2io_tbl
) = {
525 {PCI_VENDOR_ID_S2IO
, PCI_DEVICE_ID_S2IO_WIN
,
526 PCI_ANY_ID
, PCI_ANY_ID
},
527 {PCI_VENDOR_ID_S2IO
, PCI_DEVICE_ID_S2IO_UNI
,
528 PCI_ANY_ID
, PCI_ANY_ID
},
529 {PCI_VENDOR_ID_S2IO
, PCI_DEVICE_ID_HERC_WIN
,
530 PCI_ANY_ID
, PCI_ANY_ID
},
531 {PCI_VENDOR_ID_S2IO
, PCI_DEVICE_ID_HERC_UNI
,
532 PCI_ANY_ID
, PCI_ANY_ID
},
536 MODULE_DEVICE_TABLE(pci
, s2io_tbl
);
538 static struct pci_error_handlers s2io_err_handler
= {
539 .error_detected
= s2io_io_error_detected
,
540 .slot_reset
= s2io_io_slot_reset
,
541 .resume
= s2io_io_resume
,
544 static struct pci_driver s2io_driver
= {
546 .id_table
= s2io_tbl
,
547 .probe
= s2io_init_nic
,
548 .remove
= __devexit_p(s2io_rem_nic
),
549 .err_handler
= &s2io_err_handler
,
552 /* A simplifier macro used both by init and free shared_mem Fns(). */
553 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
555 /* netqueue manipulation helper functions */
556 static inline void s2io_stop_all_tx_queue(struct s2io_nic
*sp
)
558 if (!sp
->config
.multiq
) {
561 for (i
= 0; i
< sp
->config
.tx_fifo_num
; i
++)
562 sp
->mac_control
.fifos
[i
].queue_state
= FIFO_QUEUE_STOP
;
564 netif_tx_stop_all_queues(sp
->dev
);
567 static inline void s2io_stop_tx_queue(struct s2io_nic
*sp
, int fifo_no
)
569 if (!sp
->config
.multiq
)
570 sp
->mac_control
.fifos
[fifo_no
].queue_state
=
573 netif_tx_stop_all_queues(sp
->dev
);
576 static inline void s2io_start_all_tx_queue(struct s2io_nic
*sp
)
578 if (!sp
->config
.multiq
) {
581 for (i
= 0; i
< sp
->config
.tx_fifo_num
; i
++)
582 sp
->mac_control
.fifos
[i
].queue_state
= FIFO_QUEUE_START
;
584 netif_tx_start_all_queues(sp
->dev
);
587 static inline void s2io_start_tx_queue(struct s2io_nic
*sp
, int fifo_no
)
589 if (!sp
->config
.multiq
)
590 sp
->mac_control
.fifos
[fifo_no
].queue_state
=
593 netif_tx_start_all_queues(sp
->dev
);
596 static inline void s2io_wake_all_tx_queue(struct s2io_nic
*sp
)
598 if (!sp
->config
.multiq
) {
601 for (i
= 0; i
< sp
->config
.tx_fifo_num
; i
++)
602 sp
->mac_control
.fifos
[i
].queue_state
= FIFO_QUEUE_START
;
604 netif_tx_wake_all_queues(sp
->dev
);
607 static inline void s2io_wake_tx_queue(
608 struct fifo_info
*fifo
, int cnt
, u8 multiq
)
612 if (cnt
&& __netif_subqueue_stopped(fifo
->dev
, fifo
->fifo_no
))
613 netif_wake_subqueue(fifo
->dev
, fifo
->fifo_no
);
614 } else if (cnt
&& (fifo
->queue_state
== FIFO_QUEUE_STOP
)) {
615 if (netif_queue_stopped(fifo
->dev
)) {
616 fifo
->queue_state
= FIFO_QUEUE_START
;
617 netif_wake_queue(fifo
->dev
);
623 * init_shared_mem - Allocation and Initialization of Memory
624 * @nic: Device private variable.
625 * Description: The function allocates all the memory areas shared
626 * between the NIC and the driver. This includes Tx descriptors,
627 * Rx descriptors and the statistics block.
630 static int init_shared_mem(struct s2io_nic
*nic
)
633 void *tmp_v_addr
, *tmp_v_addr_next
;
634 dma_addr_t tmp_p_addr
, tmp_p_addr_next
;
635 struct RxD_block
*pre_rxd_blk
= NULL
;
637 int lst_size
, lst_per_page
;
638 struct net_device
*dev
= nic
->dev
;
641 struct config_param
*config
= &nic
->config
;
642 struct mac_info
*mac_control
= &nic
->mac_control
;
643 unsigned long long mem_allocated
= 0;
645 /* Allocation and initialization of TXDLs in FIFOs */
647 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
648 struct tx_fifo_config
*tx_cfg
= &config
->tx_cfg
[i
];
650 size
+= tx_cfg
->fifo_len
;
652 if (size
> MAX_AVAILABLE_TXDS
) {
654 "Too many TxDs requested: %d, max supported: %d\n",
655 size
, MAX_AVAILABLE_TXDS
);
660 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
661 struct tx_fifo_config
*tx_cfg
= &config
->tx_cfg
[i
];
663 size
= tx_cfg
->fifo_len
;
665 * Legal values are from 2 to 8192
668 DBG_PRINT(ERR_DBG
, "Fifo %d: Invalid length (%d) - "
669 "Valid lengths are 2 through 8192\n",
675 lst_size
= (sizeof(struct TxD
) * config
->max_txds
);
676 lst_per_page
= PAGE_SIZE
/ lst_size
;
678 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
679 struct fifo_info
*fifo
= &mac_control
->fifos
[i
];
680 struct tx_fifo_config
*tx_cfg
= &config
->tx_cfg
[i
];
681 int fifo_len
= tx_cfg
->fifo_len
;
682 int list_holder_size
= fifo_len
* sizeof(struct list_info_hold
);
684 fifo
->list_info
= kzalloc(list_holder_size
, GFP_KERNEL
);
685 if (!fifo
->list_info
) {
686 DBG_PRINT(INFO_DBG
, "Malloc failed for list_info\n");
689 mem_allocated
+= list_holder_size
;
691 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
692 int page_num
= TXD_MEM_PAGE_CNT(config
->tx_cfg
[i
].fifo_len
,
694 struct fifo_info
*fifo
= &mac_control
->fifos
[i
];
695 struct tx_fifo_config
*tx_cfg
= &config
->tx_cfg
[i
];
697 fifo
->tx_curr_put_info
.offset
= 0;
698 fifo
->tx_curr_put_info
.fifo_len
= tx_cfg
->fifo_len
- 1;
699 fifo
->tx_curr_get_info
.offset
= 0;
700 fifo
->tx_curr_get_info
.fifo_len
= tx_cfg
->fifo_len
- 1;
703 fifo
->max_txds
= MAX_SKB_FRAGS
+ 2;
706 for (j
= 0; j
< page_num
; j
++) {
710 tmp_v
= pci_alloc_consistent(nic
->pdev
,
714 "pci_alloc_consistent failed for TxDL\n");
717 /* If we got a zero DMA address(can happen on
718 * certain platforms like PPC), reallocate.
719 * Store virtual address of page we don't want,
723 mac_control
->zerodma_virt_addr
= tmp_v
;
725 "%s: Zero DMA address for TxDL. "
726 "Virtual address %p\n",
728 tmp_v
= pci_alloc_consistent(nic
->pdev
,
732 "pci_alloc_consistent failed for TxDL\n");
735 mem_allocated
+= PAGE_SIZE
;
737 while (k
< lst_per_page
) {
738 int l
= (j
* lst_per_page
) + k
;
739 if (l
== tx_cfg
->fifo_len
)
741 fifo
->list_info
[l
].list_virt_addr
=
742 tmp_v
+ (k
* lst_size
);
743 fifo
->list_info
[l
].list_phy_addr
=
744 tmp_p
+ (k
* lst_size
);
750 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
751 struct fifo_info
*fifo
= &mac_control
->fifos
[i
];
752 struct tx_fifo_config
*tx_cfg
= &config
->tx_cfg
[i
];
754 size
= tx_cfg
->fifo_len
;
755 fifo
->ufo_in_band_v
= kcalloc(size
, sizeof(u64
), GFP_KERNEL
);
756 if (!fifo
->ufo_in_band_v
)
758 mem_allocated
+= (size
* sizeof(u64
));
761 /* Allocation and initialization of RXDs in Rings */
763 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
764 struct rx_ring_config
*rx_cfg
= &config
->rx_cfg
[i
];
765 struct ring_info
*ring
= &mac_control
->rings
[i
];
767 if (rx_cfg
->num_rxd
% (rxd_count
[nic
->rxd_mode
] + 1)) {
768 DBG_PRINT(ERR_DBG
, "%s: Ring%d RxD count is not a "
769 "multiple of RxDs per Block\n",
773 size
+= rx_cfg
->num_rxd
;
774 ring
->block_count
= rx_cfg
->num_rxd
/
775 (rxd_count
[nic
->rxd_mode
] + 1);
776 ring
->pkt_cnt
= rx_cfg
->num_rxd
- ring
->block_count
;
778 if (nic
->rxd_mode
== RXD_MODE_1
)
779 size
= (size
* (sizeof(struct RxD1
)));
781 size
= (size
* (sizeof(struct RxD3
)));
783 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
784 struct rx_ring_config
*rx_cfg
= &config
->rx_cfg
[i
];
785 struct ring_info
*ring
= &mac_control
->rings
[i
];
787 ring
->rx_curr_get_info
.block_index
= 0;
788 ring
->rx_curr_get_info
.offset
= 0;
789 ring
->rx_curr_get_info
.ring_len
= rx_cfg
->num_rxd
- 1;
790 ring
->rx_curr_put_info
.block_index
= 0;
791 ring
->rx_curr_put_info
.offset
= 0;
792 ring
->rx_curr_put_info
.ring_len
= rx_cfg
->num_rxd
- 1;
796 blk_cnt
= rx_cfg
->num_rxd
/ (rxd_count
[nic
->rxd_mode
] + 1);
797 /* Allocating all the Rx blocks */
798 for (j
= 0; j
< blk_cnt
; j
++) {
799 struct rx_block_info
*rx_blocks
;
802 rx_blocks
= &ring
->rx_blocks
[j
];
803 size
= SIZE_OF_BLOCK
; /* size is always page size */
804 tmp_v_addr
= pci_alloc_consistent(nic
->pdev
, size
,
806 if (tmp_v_addr
== NULL
) {
808 * In case of failure, free_shared_mem()
809 * is called, which should free any
810 * memory that was alloced till the
813 rx_blocks
->block_virt_addr
= tmp_v_addr
;
816 mem_allocated
+= size
;
817 memset(tmp_v_addr
, 0, size
);
819 size
= sizeof(struct rxd_info
) *
820 rxd_count
[nic
->rxd_mode
];
821 rx_blocks
->block_virt_addr
= tmp_v_addr
;
822 rx_blocks
->block_dma_addr
= tmp_p_addr
;
823 rx_blocks
->rxds
= kmalloc(size
, GFP_KERNEL
);
824 if (!rx_blocks
->rxds
)
826 mem_allocated
+= size
;
827 for (l
= 0; l
< rxd_count
[nic
->rxd_mode
]; l
++) {
828 rx_blocks
->rxds
[l
].virt_addr
=
829 rx_blocks
->block_virt_addr
+
830 (rxd_size
[nic
->rxd_mode
] * l
);
831 rx_blocks
->rxds
[l
].dma_addr
=
832 rx_blocks
->block_dma_addr
+
833 (rxd_size
[nic
->rxd_mode
] * l
);
836 /* Interlinking all Rx Blocks */
837 for (j
= 0; j
< blk_cnt
; j
++) {
838 int next
= (j
+ 1) % blk_cnt
;
839 tmp_v_addr
= ring
->rx_blocks
[j
].block_virt_addr
;
840 tmp_v_addr_next
= ring
->rx_blocks
[next
].block_virt_addr
;
841 tmp_p_addr
= ring
->rx_blocks
[j
].block_dma_addr
;
842 tmp_p_addr_next
= ring
->rx_blocks
[next
].block_dma_addr
;
844 pre_rxd_blk
= tmp_v_addr
;
845 pre_rxd_blk
->reserved_2_pNext_RxD_block
=
846 (unsigned long)tmp_v_addr_next
;
847 pre_rxd_blk
->pNext_RxD_Blk_physical
=
848 (u64
)tmp_p_addr_next
;
851 if (nic
->rxd_mode
== RXD_MODE_3B
) {
853 * Allocation of Storages for buffer addresses in 2BUFF mode
854 * and the buffers as well.
856 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
857 struct rx_ring_config
*rx_cfg
= &config
->rx_cfg
[i
];
858 struct ring_info
*ring
= &mac_control
->rings
[i
];
860 blk_cnt
= rx_cfg
->num_rxd
/
861 (rxd_count
[nic
->rxd_mode
] + 1);
862 size
= sizeof(struct buffAdd
*) * blk_cnt
;
863 ring
->ba
= kmalloc(size
, GFP_KERNEL
);
866 mem_allocated
+= size
;
867 for (j
= 0; j
< blk_cnt
; j
++) {
870 size
= sizeof(struct buffAdd
) *
871 (rxd_count
[nic
->rxd_mode
] + 1);
872 ring
->ba
[j
] = kmalloc(size
, GFP_KERNEL
);
875 mem_allocated
+= size
;
876 while (k
!= rxd_count
[nic
->rxd_mode
]) {
877 ba
= &ring
->ba
[j
][k
];
878 size
= BUF0_LEN
+ ALIGN_SIZE
;
879 ba
->ba_0_org
= kmalloc(size
, GFP_KERNEL
);
882 mem_allocated
+= size
;
883 tmp
= (unsigned long)ba
->ba_0_org
;
885 tmp
&= ~((unsigned long)ALIGN_SIZE
);
886 ba
->ba_0
= (void *)tmp
;
888 size
= BUF1_LEN
+ ALIGN_SIZE
;
889 ba
->ba_1_org
= kmalloc(size
, GFP_KERNEL
);
892 mem_allocated
+= size
;
893 tmp
= (unsigned long)ba
->ba_1_org
;
895 tmp
&= ~((unsigned long)ALIGN_SIZE
);
896 ba
->ba_1
= (void *)tmp
;
903 /* Allocation and initialization of Statistics block */
904 size
= sizeof(struct stat_block
);
905 mac_control
->stats_mem
=
906 pci_alloc_consistent(nic
->pdev
, size
,
907 &mac_control
->stats_mem_phy
);
909 if (!mac_control
->stats_mem
) {
911 * In case of failure, free_shared_mem() is called, which
912 * should free any memory that was alloced till the
917 mem_allocated
+= size
;
918 mac_control
->stats_mem_sz
= size
;
920 tmp_v_addr
= mac_control
->stats_mem
;
921 mac_control
->stats_info
= tmp_v_addr
;
922 memset(tmp_v_addr
, 0, size
);
923 DBG_PRINT(INIT_DBG
, "%s: Ring Mem PHY: 0x%llx\n",
924 dev_name(&nic
->pdev
->dev
), (unsigned long long)tmp_p_addr
);
925 mac_control
->stats_info
->sw_stat
.mem_allocated
+= mem_allocated
;
930 * free_shared_mem - Free the allocated Memory
931 * @nic: Device private variable.
932 * Description: This function is to free all memory locations allocated by
933 * the init_shared_mem() function and return it to the kernel.
936 static void free_shared_mem(struct s2io_nic
*nic
)
938 int i
, j
, blk_cnt
, size
;
940 dma_addr_t tmp_p_addr
;
941 int lst_size
, lst_per_page
;
942 struct net_device
*dev
;
944 struct config_param
*config
;
945 struct mac_info
*mac_control
;
946 struct stat_block
*stats
;
947 struct swStat
*swstats
;
954 config
= &nic
->config
;
955 mac_control
= &nic
->mac_control
;
956 stats
= mac_control
->stats_info
;
957 swstats
= &stats
->sw_stat
;
959 lst_size
= sizeof(struct TxD
) * config
->max_txds
;
960 lst_per_page
= PAGE_SIZE
/ lst_size
;
962 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
963 struct fifo_info
*fifo
= &mac_control
->fifos
[i
];
964 struct tx_fifo_config
*tx_cfg
= &config
->tx_cfg
[i
];
966 page_num
= TXD_MEM_PAGE_CNT(tx_cfg
->fifo_len
, lst_per_page
);
967 for (j
= 0; j
< page_num
; j
++) {
968 int mem_blks
= (j
* lst_per_page
);
969 struct list_info_hold
*fli
;
971 if (!fifo
->list_info
)
974 fli
= &fifo
->list_info
[mem_blks
];
975 if (!fli
->list_virt_addr
)
977 pci_free_consistent(nic
->pdev
, PAGE_SIZE
,
980 swstats
->mem_freed
+= PAGE_SIZE
;
982 /* If we got a zero DMA address during allocation,
985 if (mac_control
->zerodma_virt_addr
) {
986 pci_free_consistent(nic
->pdev
, PAGE_SIZE
,
987 mac_control
->zerodma_virt_addr
,
990 "%s: Freeing TxDL with zero DMA address. "
991 "Virtual address %p\n",
992 dev
->name
, mac_control
->zerodma_virt_addr
);
993 swstats
->mem_freed
+= PAGE_SIZE
;
995 kfree(fifo
->list_info
);
996 swstats
->mem_freed
+= tx_cfg
->fifo_len
*
997 sizeof(struct list_info_hold
);
1000 size
= SIZE_OF_BLOCK
;
1001 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
1002 struct ring_info
*ring
= &mac_control
->rings
[i
];
1004 blk_cnt
= ring
->block_count
;
1005 for (j
= 0; j
< blk_cnt
; j
++) {
1006 tmp_v_addr
= ring
->rx_blocks
[j
].block_virt_addr
;
1007 tmp_p_addr
= ring
->rx_blocks
[j
].block_dma_addr
;
1008 if (tmp_v_addr
== NULL
)
1010 pci_free_consistent(nic
->pdev
, size
,
1011 tmp_v_addr
, tmp_p_addr
);
1012 swstats
->mem_freed
+= size
;
1013 kfree(ring
->rx_blocks
[j
].rxds
);
1014 swstats
->mem_freed
+= sizeof(struct rxd_info
) *
1015 rxd_count
[nic
->rxd_mode
];
1019 if (nic
->rxd_mode
== RXD_MODE_3B
) {
1020 /* Freeing buffer storage addresses in 2BUFF mode. */
1021 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
1022 struct rx_ring_config
*rx_cfg
= &config
->rx_cfg
[i
];
1023 struct ring_info
*ring
= &mac_control
->rings
[i
];
1025 blk_cnt
= rx_cfg
->num_rxd
/
1026 (rxd_count
[nic
->rxd_mode
] + 1);
1027 for (j
= 0; j
< blk_cnt
; j
++) {
1031 while (k
!= rxd_count
[nic
->rxd_mode
]) {
1032 struct buffAdd
*ba
= &ring
->ba
[j
][k
];
1033 kfree(ba
->ba_0_org
);
1034 swstats
->mem_freed
+=
1035 BUF0_LEN
+ ALIGN_SIZE
;
1036 kfree(ba
->ba_1_org
);
1037 swstats
->mem_freed
+=
1038 BUF1_LEN
+ ALIGN_SIZE
;
1042 swstats
->mem_freed
+= sizeof(struct buffAdd
) *
1043 (rxd_count
[nic
->rxd_mode
] + 1);
1046 swstats
->mem_freed
+= sizeof(struct buffAdd
*) *
1051 for (i
= 0; i
< nic
->config
.tx_fifo_num
; i
++) {
1052 struct fifo_info
*fifo
= &mac_control
->fifos
[i
];
1053 struct tx_fifo_config
*tx_cfg
= &config
->tx_cfg
[i
];
1055 if (fifo
->ufo_in_band_v
) {
1056 swstats
->mem_freed
+= tx_cfg
->fifo_len
*
1058 kfree(fifo
->ufo_in_band_v
);
1062 if (mac_control
->stats_mem
) {
1063 swstats
->mem_freed
+= mac_control
->stats_mem_sz
;
1064 pci_free_consistent(nic
->pdev
,
1065 mac_control
->stats_mem_sz
,
1066 mac_control
->stats_mem
,
1067 mac_control
->stats_mem_phy
);
1072 * s2io_verify_pci_mode -
1075 static int s2io_verify_pci_mode(struct s2io_nic
*nic
)
1077 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
1078 register u64 val64
= 0;
1081 val64
= readq(&bar0
->pci_mode
);
1082 mode
= (u8
)GET_PCI_MODE(val64
);
1084 if (val64
& PCI_MODE_UNKNOWN_MODE
)
1085 return -1; /* Unknown PCI mode */
1089 #define NEC_VENID 0x1033
1090 #define NEC_DEVID 0x0125
1091 static int s2io_on_nec_bridge(struct pci_dev
*s2io_pdev
)
1093 struct pci_dev
*tdev
= NULL
;
1094 while ((tdev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, tdev
)) != NULL
) {
1095 if (tdev
->vendor
== NEC_VENID
&& tdev
->device
== NEC_DEVID
) {
1096 if (tdev
->bus
== s2io_pdev
->bus
->parent
) {
1105 static int bus_speed
[8] = {33, 133, 133, 200, 266, 133, 200, 266};
1107 * s2io_print_pci_mode -
1109 static int s2io_print_pci_mode(struct s2io_nic
*nic
)
1111 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
1112 register u64 val64
= 0;
1114 struct config_param
*config
= &nic
->config
;
1115 const char *pcimode
;
1117 val64
= readq(&bar0
->pci_mode
);
1118 mode
= (u8
)GET_PCI_MODE(val64
);
1120 if (val64
& PCI_MODE_UNKNOWN_MODE
)
1121 return -1; /* Unknown PCI mode */
1123 config
->bus_speed
= bus_speed
[mode
];
1125 if (s2io_on_nec_bridge(nic
->pdev
)) {
1126 DBG_PRINT(ERR_DBG
, "%s: Device is on PCI-E bus\n",
1132 case PCI_MODE_PCI_33
:
1133 pcimode
= "33MHz PCI bus";
1135 case PCI_MODE_PCI_66
:
1136 pcimode
= "66MHz PCI bus";
1138 case PCI_MODE_PCIX_M1_66
:
1139 pcimode
= "66MHz PCIX(M1) bus";
1141 case PCI_MODE_PCIX_M1_100
:
1142 pcimode
= "100MHz PCIX(M1) bus";
1144 case PCI_MODE_PCIX_M1_133
:
1145 pcimode
= "133MHz PCIX(M1) bus";
1147 case PCI_MODE_PCIX_M2_66
:
1148 pcimode
= "133MHz PCIX(M2) bus";
1150 case PCI_MODE_PCIX_M2_100
:
1151 pcimode
= "200MHz PCIX(M2) bus";
1153 case PCI_MODE_PCIX_M2_133
:
1154 pcimode
= "266MHz PCIX(M2) bus";
1157 pcimode
= "unsupported bus!";
1161 DBG_PRINT(ERR_DBG
, "%s: Device is on %d bit %s\n",
1162 nic
->dev
->name
, val64
& PCI_MODE_32_BITS
? 32 : 64, pcimode
);
1168 * init_tti - Initialization transmit traffic interrupt scheme
1169 * @nic: device private variable
1170 * @link: link status (UP/DOWN) used to enable/disable continuous
1171 * transmit interrupts
1172 * Description: The function configures transmit traffic interrupts
1173 * Return Value: SUCCESS on success and
1177 static int init_tti(struct s2io_nic
*nic
, int link
)
1179 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
1180 register u64 val64
= 0;
1182 struct config_param
*config
= &nic
->config
;
1184 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
1186 * TTI Initialization. Default Tx timer gets us about
1187 * 250 interrupts per sec. Continuous interrupts are enabled
1190 if (nic
->device_type
== XFRAME_II_DEVICE
) {
1191 int count
= (nic
->config
.bus_speed
* 125)/2;
1192 val64
= TTI_DATA1_MEM_TX_TIMER_VAL(count
);
1194 val64
= TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1196 val64
|= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1197 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1198 TTI_DATA1_MEM_TX_URNG_C(0x30) |
1199 TTI_DATA1_MEM_TX_TIMER_AC_EN
;
1201 if (use_continuous_tx_intrs
&& (link
== LINK_UP
))
1202 val64
|= TTI_DATA1_MEM_TX_TIMER_CI_EN
;
1203 writeq(val64
, &bar0
->tti_data1_mem
);
1205 if (nic
->config
.intr_type
== MSI_X
) {
1206 val64
= TTI_DATA2_MEM_TX_UFC_A(0x10) |
1207 TTI_DATA2_MEM_TX_UFC_B(0x100) |
1208 TTI_DATA2_MEM_TX_UFC_C(0x200) |
1209 TTI_DATA2_MEM_TX_UFC_D(0x300);
1211 if ((nic
->config
.tx_steering_type
==
1212 TX_DEFAULT_STEERING
) &&
1213 (config
->tx_fifo_num
> 1) &&
1214 (i
>= nic
->udp_fifo_idx
) &&
1215 (i
< (nic
->udp_fifo_idx
+
1216 nic
->total_udp_fifos
)))
1217 val64
= TTI_DATA2_MEM_TX_UFC_A(0x50) |
1218 TTI_DATA2_MEM_TX_UFC_B(0x80) |
1219 TTI_DATA2_MEM_TX_UFC_C(0x100) |
1220 TTI_DATA2_MEM_TX_UFC_D(0x120);
1222 val64
= TTI_DATA2_MEM_TX_UFC_A(0x10) |
1223 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1224 TTI_DATA2_MEM_TX_UFC_C(0x40) |
1225 TTI_DATA2_MEM_TX_UFC_D(0x80);
1228 writeq(val64
, &bar0
->tti_data2_mem
);
1230 val64
= TTI_CMD_MEM_WE
|
1231 TTI_CMD_MEM_STROBE_NEW_CMD
|
1232 TTI_CMD_MEM_OFFSET(i
);
1233 writeq(val64
, &bar0
->tti_command_mem
);
1235 if (wait_for_cmd_complete(&bar0
->tti_command_mem
,
1236 TTI_CMD_MEM_STROBE_NEW_CMD
,
1237 S2IO_BIT_RESET
) != SUCCESS
)
1245 * init_nic - Initialization of hardware
1246 * @nic: device private variable
1247 * Description: The function sequentially configures every block
1248 * of the H/W from their reset values.
1249 * Return Value: SUCCESS on success and
1250 * '-1' on failure (endian settings incorrect).
1253 static int init_nic(struct s2io_nic
*nic
)
1255 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
1256 struct net_device
*dev
= nic
->dev
;
1257 register u64 val64
= 0;
1262 unsigned long long mem_share
;
1264 struct config_param
*config
= &nic
->config
;
1265 struct mac_info
*mac_control
= &nic
->mac_control
;
1267 /* to set the swapper controle on the card */
1268 if (s2io_set_swapper(nic
)) {
1269 DBG_PRINT(ERR_DBG
, "ERROR: Setting Swapper failed\n");
1274 * Herc requires EOI to be removed from reset before XGXS, so..
1276 if (nic
->device_type
& XFRAME_II_DEVICE
) {
1277 val64
= 0xA500000000ULL
;
1278 writeq(val64
, &bar0
->sw_reset
);
1280 val64
= readq(&bar0
->sw_reset
);
1283 /* Remove XGXS from reset state */
1285 writeq(val64
, &bar0
->sw_reset
);
1287 val64
= readq(&bar0
->sw_reset
);
1289 /* Ensure that it's safe to access registers by checking
1290 * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1292 if (nic
->device_type
== XFRAME_II_DEVICE
) {
1293 for (i
= 0; i
< 50; i
++) {
1294 val64
= readq(&bar0
->adapter_status
);
1295 if (!(val64
& ADAPTER_STATUS_RIC_RUNNING
))
1303 /* Enable Receiving broadcasts */
1304 add
= &bar0
->mac_cfg
;
1305 val64
= readq(&bar0
->mac_cfg
);
1306 val64
|= MAC_RMAC_BCAST_ENABLE
;
1307 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1308 writel((u32
)val64
, add
);
1309 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1310 writel((u32
) (val64
>> 32), (add
+ 4));
1312 /* Read registers in all blocks */
1313 val64
= readq(&bar0
->mac_int_mask
);
1314 val64
= readq(&bar0
->mc_int_mask
);
1315 val64
= readq(&bar0
->xgxs_int_mask
);
1319 writeq(vBIT(val64
, 2, 14), &bar0
->rmac_max_pyld_len
);
1321 if (nic
->device_type
& XFRAME_II_DEVICE
) {
1322 while (herc_act_dtx_cfg
[dtx_cnt
] != END_SIGN
) {
1323 SPECIAL_REG_WRITE(herc_act_dtx_cfg
[dtx_cnt
],
1324 &bar0
->dtx_control
, UF
);
1326 msleep(1); /* Necessary!! */
1330 while (xena_dtx_cfg
[dtx_cnt
] != END_SIGN
) {
1331 SPECIAL_REG_WRITE(xena_dtx_cfg
[dtx_cnt
],
1332 &bar0
->dtx_control
, UF
);
1333 val64
= readq(&bar0
->dtx_control
);
1338 /* Tx DMA Initialization */
1340 writeq(val64
, &bar0
->tx_fifo_partition_0
);
1341 writeq(val64
, &bar0
->tx_fifo_partition_1
);
1342 writeq(val64
, &bar0
->tx_fifo_partition_2
);
1343 writeq(val64
, &bar0
->tx_fifo_partition_3
);
1345 for (i
= 0, j
= 0; i
< config
->tx_fifo_num
; i
++) {
1346 struct tx_fifo_config
*tx_cfg
= &config
->tx_cfg
[i
];
1348 val64
|= vBIT(tx_cfg
->fifo_len
- 1, ((j
* 32) + 19), 13) |
1349 vBIT(tx_cfg
->fifo_priority
, ((j
* 32) + 5), 3);
1351 if (i
== (config
->tx_fifo_num
- 1)) {
1358 writeq(val64
, &bar0
->tx_fifo_partition_0
);
1363 writeq(val64
, &bar0
->tx_fifo_partition_1
);
1368 writeq(val64
, &bar0
->tx_fifo_partition_2
);
1373 writeq(val64
, &bar0
->tx_fifo_partition_3
);
1384 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1385 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1387 if ((nic
->device_type
== XFRAME_I_DEVICE
) && (nic
->pdev
->revision
< 4))
1388 writeq(PCC_ENABLE_FOUR
, &bar0
->pcc_enable
);
1390 val64
= readq(&bar0
->tx_fifo_partition_0
);
1391 DBG_PRINT(INIT_DBG
, "Fifo partition at: 0x%p is: 0x%llx\n",
1392 &bar0
->tx_fifo_partition_0
, (unsigned long long)val64
);
1395 * Initialization of Tx_PA_CONFIG register to ignore packet
1396 * integrity checking.
1398 val64
= readq(&bar0
->tx_pa_cfg
);
1399 val64
|= TX_PA_CFG_IGNORE_FRM_ERR
|
1400 TX_PA_CFG_IGNORE_SNAP_OUI
|
1401 TX_PA_CFG_IGNORE_LLC_CTRL
|
1402 TX_PA_CFG_IGNORE_L2_ERR
;
1403 writeq(val64
, &bar0
->tx_pa_cfg
);
1405 /* Rx DMA intialization. */
1407 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
1408 struct rx_ring_config
*rx_cfg
= &config
->rx_cfg
[i
];
1410 val64
|= vBIT(rx_cfg
->ring_priority
, (5 + (i
* 8)), 3);
1412 writeq(val64
, &bar0
->rx_queue_priority
);
1415 * Allocating equal share of memory to all the
1419 if (nic
->device_type
& XFRAME_II_DEVICE
)
1424 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
1427 mem_share
= (mem_size
/ config
->rx_ring_num
+
1428 mem_size
% config
->rx_ring_num
);
1429 val64
|= RX_QUEUE_CFG_Q0_SZ(mem_share
);
1432 mem_share
= (mem_size
/ config
->rx_ring_num
);
1433 val64
|= RX_QUEUE_CFG_Q1_SZ(mem_share
);
1436 mem_share
= (mem_size
/ config
->rx_ring_num
);
1437 val64
|= RX_QUEUE_CFG_Q2_SZ(mem_share
);
1440 mem_share
= (mem_size
/ config
->rx_ring_num
);
1441 val64
|= RX_QUEUE_CFG_Q3_SZ(mem_share
);
1444 mem_share
= (mem_size
/ config
->rx_ring_num
);
1445 val64
|= RX_QUEUE_CFG_Q4_SZ(mem_share
);
1448 mem_share
= (mem_size
/ config
->rx_ring_num
);
1449 val64
|= RX_QUEUE_CFG_Q5_SZ(mem_share
);
1452 mem_share
= (mem_size
/ config
->rx_ring_num
);
1453 val64
|= RX_QUEUE_CFG_Q6_SZ(mem_share
);
1456 mem_share
= (mem_size
/ config
->rx_ring_num
);
1457 val64
|= RX_QUEUE_CFG_Q7_SZ(mem_share
);
1461 writeq(val64
, &bar0
->rx_queue_cfg
);
1464 * Filling Tx round robin registers
1465 * as per the number of FIFOs for equal scheduling priority
1467 switch (config
->tx_fifo_num
) {
1470 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1471 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1472 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1473 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1474 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1477 val64
= 0x0001000100010001ULL
;
1478 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1479 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1480 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1481 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1482 val64
= 0x0001000100000000ULL
;
1483 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1486 val64
= 0x0001020001020001ULL
;
1487 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1488 val64
= 0x0200010200010200ULL
;
1489 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1490 val64
= 0x0102000102000102ULL
;
1491 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1492 val64
= 0x0001020001020001ULL
;
1493 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1494 val64
= 0x0200010200000000ULL
;
1495 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1498 val64
= 0x0001020300010203ULL
;
1499 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1500 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1501 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1502 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1503 val64
= 0x0001020300000000ULL
;
1504 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1507 val64
= 0x0001020304000102ULL
;
1508 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1509 val64
= 0x0304000102030400ULL
;
1510 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1511 val64
= 0x0102030400010203ULL
;
1512 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1513 val64
= 0x0400010203040001ULL
;
1514 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1515 val64
= 0x0203040000000000ULL
;
1516 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1519 val64
= 0x0001020304050001ULL
;
1520 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1521 val64
= 0x0203040500010203ULL
;
1522 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1523 val64
= 0x0405000102030405ULL
;
1524 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1525 val64
= 0x0001020304050001ULL
;
1526 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1527 val64
= 0x0203040500000000ULL
;
1528 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1531 val64
= 0x0001020304050600ULL
;
1532 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1533 val64
= 0x0102030405060001ULL
;
1534 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1535 val64
= 0x0203040506000102ULL
;
1536 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1537 val64
= 0x0304050600010203ULL
;
1538 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1539 val64
= 0x0405060000000000ULL
;
1540 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1543 val64
= 0x0001020304050607ULL
;
1544 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1545 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1546 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1547 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1548 val64
= 0x0001020300000000ULL
;
1549 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1553 /* Enable all configured Tx FIFO partitions */
1554 val64
= readq(&bar0
->tx_fifo_partition_0
);
1555 val64
|= (TX_FIFO_PARTITION_EN
);
1556 writeq(val64
, &bar0
->tx_fifo_partition_0
);
1558 /* Filling the Rx round robin registers as per the
1559 * number of Rings and steering based on QoS with
1562 switch (config
->rx_ring_num
) {
1565 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1566 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1567 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1568 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1569 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1571 val64
= 0x8080808080808080ULL
;
1572 writeq(val64
, &bar0
->rts_qos_steering
);
1575 val64
= 0x0001000100010001ULL
;
1576 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1577 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1578 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1579 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1580 val64
= 0x0001000100000000ULL
;
1581 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1583 val64
= 0x8080808040404040ULL
;
1584 writeq(val64
, &bar0
->rts_qos_steering
);
1587 val64
= 0x0001020001020001ULL
;
1588 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1589 val64
= 0x0200010200010200ULL
;
1590 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1591 val64
= 0x0102000102000102ULL
;
1592 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1593 val64
= 0x0001020001020001ULL
;
1594 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1595 val64
= 0x0200010200000000ULL
;
1596 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1598 val64
= 0x8080804040402020ULL
;
1599 writeq(val64
, &bar0
->rts_qos_steering
);
1602 val64
= 0x0001020300010203ULL
;
1603 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1604 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1605 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1606 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1607 val64
= 0x0001020300000000ULL
;
1608 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1610 val64
= 0x8080404020201010ULL
;
1611 writeq(val64
, &bar0
->rts_qos_steering
);
1614 val64
= 0x0001020304000102ULL
;
1615 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1616 val64
= 0x0304000102030400ULL
;
1617 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1618 val64
= 0x0102030400010203ULL
;
1619 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1620 val64
= 0x0400010203040001ULL
;
1621 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1622 val64
= 0x0203040000000000ULL
;
1623 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1625 val64
= 0x8080404020201008ULL
;
1626 writeq(val64
, &bar0
->rts_qos_steering
);
1629 val64
= 0x0001020304050001ULL
;
1630 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1631 val64
= 0x0203040500010203ULL
;
1632 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1633 val64
= 0x0405000102030405ULL
;
1634 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1635 val64
= 0x0001020304050001ULL
;
1636 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1637 val64
= 0x0203040500000000ULL
;
1638 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1640 val64
= 0x8080404020100804ULL
;
1641 writeq(val64
, &bar0
->rts_qos_steering
);
1644 val64
= 0x0001020304050600ULL
;
1645 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1646 val64
= 0x0102030405060001ULL
;
1647 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1648 val64
= 0x0203040506000102ULL
;
1649 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1650 val64
= 0x0304050600010203ULL
;
1651 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1652 val64
= 0x0405060000000000ULL
;
1653 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1655 val64
= 0x8080402010080402ULL
;
1656 writeq(val64
, &bar0
->rts_qos_steering
);
1659 val64
= 0x0001020304050607ULL
;
1660 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1661 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1662 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1663 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1664 val64
= 0x0001020300000000ULL
;
1665 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1667 val64
= 0x8040201008040201ULL
;
1668 writeq(val64
, &bar0
->rts_qos_steering
);
1674 for (i
= 0; i
< 8; i
++)
1675 writeq(val64
, &bar0
->rts_frm_len_n
[i
]);
1677 /* Set the default rts frame length for the rings configured */
1678 val64
= MAC_RTS_FRM_LEN_SET(dev
->mtu
+22);
1679 for (i
= 0 ; i
< config
->rx_ring_num
; i
++)
1680 writeq(val64
, &bar0
->rts_frm_len_n
[i
]);
1682 /* Set the frame length for the configured rings
1683 * desired by the user
1685 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
1686 /* If rts_frm_len[i] == 0 then it is assumed that user not
1687 * specified frame length steering.
1688 * If the user provides the frame length then program
1689 * the rts_frm_len register for those values or else
1690 * leave it as it is.
1692 if (rts_frm_len
[i
] != 0) {
1693 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len
[i
]),
1694 &bar0
->rts_frm_len_n
[i
]);
1698 /* Disable differentiated services steering logic */
1699 for (i
= 0; i
< 64; i
++) {
1700 if (rts_ds_steer(nic
, i
, 0) == FAILURE
) {
1702 "%s: rts_ds_steer failed on codepoint %d\n",
1708 /* Program statistics memory */
1709 writeq(mac_control
->stats_mem_phy
, &bar0
->stat_addr
);
1711 if (nic
->device_type
== XFRAME_II_DEVICE
) {
1712 val64
= STAT_BC(0x320);
1713 writeq(val64
, &bar0
->stat_byte_cnt
);
1717 * Initializing the sampling rate for the device to calculate the
1718 * bandwidth utilization.
1720 val64
= MAC_TX_LINK_UTIL_VAL(tmac_util_period
) |
1721 MAC_RX_LINK_UTIL_VAL(rmac_util_period
);
1722 writeq(val64
, &bar0
->mac_link_util
);
1725 * Initializing the Transmit and Receive Traffic Interrupt
1729 /* Initialize TTI */
1730 if (SUCCESS
!= init_tti(nic
, nic
->last_link_state
))
1733 /* RTI Initialization */
1734 if (nic
->device_type
== XFRAME_II_DEVICE
) {
1736 * Programmed to generate Apprx 500 Intrs per
1739 int count
= (nic
->config
.bus_speed
* 125)/4;
1740 val64
= RTI_DATA1_MEM_RX_TIMER_VAL(count
);
1742 val64
= RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1743 val64
|= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1744 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1745 RTI_DATA1_MEM_RX_URNG_C(0x30) |
1746 RTI_DATA1_MEM_RX_TIMER_AC_EN
;
1748 writeq(val64
, &bar0
->rti_data1_mem
);
1750 val64
= RTI_DATA2_MEM_RX_UFC_A(0x1) |
1751 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1752 if (nic
->config
.intr_type
== MSI_X
)
1753 val64
|= (RTI_DATA2_MEM_RX_UFC_C(0x20) |
1754 RTI_DATA2_MEM_RX_UFC_D(0x40));
1756 val64
|= (RTI_DATA2_MEM_RX_UFC_C(0x40) |
1757 RTI_DATA2_MEM_RX_UFC_D(0x80));
1758 writeq(val64
, &bar0
->rti_data2_mem
);
1760 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
1761 val64
= RTI_CMD_MEM_WE
|
1762 RTI_CMD_MEM_STROBE_NEW_CMD
|
1763 RTI_CMD_MEM_OFFSET(i
);
1764 writeq(val64
, &bar0
->rti_command_mem
);
1767 * Once the operation completes, the Strobe bit of the
1768 * command register will be reset. We poll for this
1769 * particular condition. We wait for a maximum of 500ms
1770 * for the operation to complete, if it's not complete
1771 * by then we return error.
1775 val64
= readq(&bar0
->rti_command_mem
);
1776 if (!(val64
& RTI_CMD_MEM_STROBE_NEW_CMD
))
1780 DBG_PRINT(ERR_DBG
, "%s: RTI init failed\n",
1790 * Initializing proper values as Pause threshold into all
1791 * the 8 Queues on Rx side.
1793 writeq(0xffbbffbbffbbffbbULL
, &bar0
->mc_pause_thresh_q0q3
);
1794 writeq(0xffbbffbbffbbffbbULL
, &bar0
->mc_pause_thresh_q4q7
);
1796 /* Disable RMAC PAD STRIPPING */
1797 add
= &bar0
->mac_cfg
;
1798 val64
= readq(&bar0
->mac_cfg
);
1799 val64
&= ~(MAC_CFG_RMAC_STRIP_PAD
);
1800 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1801 writel((u32
) (val64
), add
);
1802 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1803 writel((u32
) (val64
>> 32), (add
+ 4));
1804 val64
= readq(&bar0
->mac_cfg
);
1806 /* Enable FCS stripping by adapter */
1807 add
= &bar0
->mac_cfg
;
1808 val64
= readq(&bar0
->mac_cfg
);
1809 val64
|= MAC_CFG_RMAC_STRIP_FCS
;
1810 if (nic
->device_type
== XFRAME_II_DEVICE
)
1811 writeq(val64
, &bar0
->mac_cfg
);
1813 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1814 writel((u32
) (val64
), add
);
1815 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1816 writel((u32
) (val64
>> 32), (add
+ 4));
1820 * Set the time value to be inserted in the pause frame
1821 * generated by xena.
1823 val64
= readq(&bar0
->rmac_pause_cfg
);
1824 val64
&= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1825 val64
|= RMAC_PAUSE_HG_PTIME(nic
->mac_control
.rmac_pause_time
);
1826 writeq(val64
, &bar0
->rmac_pause_cfg
);
1829 * Set the Threshold Limit for Generating the pause frame
1830 * If the amount of data in any Queue exceeds ratio of
1831 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1832 * pause frame is generated
1835 for (i
= 0; i
< 4; i
++) {
1836 val64
|= (((u64
)0xFF00 |
1837 nic
->mac_control
.mc_pause_threshold_q0q3
)
1840 writeq(val64
, &bar0
->mc_pause_thresh_q0q3
);
1843 for (i
= 0; i
< 4; i
++) {
1844 val64
|= (((u64
)0xFF00 |
1845 nic
->mac_control
.mc_pause_threshold_q4q7
)
1848 writeq(val64
, &bar0
->mc_pause_thresh_q4q7
);
1851 * TxDMA will stop Read request if the number of read split has
1852 * exceeded the limit pointed by shared_splits
1854 val64
= readq(&bar0
->pic_control
);
1855 val64
|= PIC_CNTL_SHARED_SPLITS(shared_splits
);
1856 writeq(val64
, &bar0
->pic_control
);
1858 if (nic
->config
.bus_speed
== 266) {
1859 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN
, &bar0
->txreqtimeout
);
1860 writeq(0x0, &bar0
->read_retry_delay
);
1861 writeq(0x0, &bar0
->write_retry_delay
);
1865 * Programming the Herc to split every write transaction
1866 * that does not start on an ADB to reduce disconnects.
1868 if (nic
->device_type
== XFRAME_II_DEVICE
) {
1869 val64
= FAULT_BEHAVIOUR
| EXT_REQ_EN
|
1870 MISC_LINK_STABILITY_PRD(3);
1871 writeq(val64
, &bar0
->misc_control
);
1872 val64
= readq(&bar0
->pic_control2
);
1873 val64
&= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
1874 writeq(val64
, &bar0
->pic_control2
);
1876 if (strstr(nic
->product_name
, "CX4")) {
1877 val64
= TMAC_AVG_IPG(0x17);
1878 writeq(val64
, &bar0
->tmac_avg_ipg
);
1883 #define LINK_UP_DOWN_INTERRUPT 1
1884 #define MAC_RMAC_ERR_TIMER 2
1886 static int s2io_link_fault_indication(struct s2io_nic
*nic
)
1888 if (nic
->device_type
== XFRAME_II_DEVICE
)
1889 return LINK_UP_DOWN_INTERRUPT
;
1891 return MAC_RMAC_ERR_TIMER
;
1895 * do_s2io_write_bits - update alarm bits in alarm register
1896 * @value: alarm bits
1897 * @flag: interrupt status
1898 * @addr: address value
1899 * Description: update alarm bits in alarm register
1903 static void do_s2io_write_bits(u64 value
, int flag
, void __iomem
*addr
)
1907 temp64
= readq(addr
);
1909 if (flag
== ENABLE_INTRS
)
1910 temp64
&= ~((u64
)value
);
1912 temp64
|= ((u64
)value
);
1913 writeq(temp64
, addr
);
1916 static void en_dis_err_alarms(struct s2io_nic
*nic
, u16 mask
, int flag
)
1918 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
1919 register u64 gen_int_mask
= 0;
1922 writeq(DISABLE_ALL_INTRS
, &bar0
->general_int_mask
);
1923 if (mask
& TX_DMA_INTR
) {
1924 gen_int_mask
|= TXDMA_INT_M
;
1926 do_s2io_write_bits(TXDMA_TDA_INT
| TXDMA_PFC_INT
|
1927 TXDMA_PCC_INT
| TXDMA_TTI_INT
|
1928 TXDMA_LSO_INT
| TXDMA_TPA_INT
|
1929 TXDMA_SM_INT
, flag
, &bar0
->txdma_int_mask
);
1931 do_s2io_write_bits(PFC_ECC_DB_ERR
| PFC_SM_ERR_ALARM
|
1932 PFC_MISC_0_ERR
| PFC_MISC_1_ERR
|
1933 PFC_PCIX_ERR
| PFC_ECC_SG_ERR
, flag
,
1934 &bar0
->pfc_err_mask
);
1936 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR
| TDA_SM0_ERR_ALARM
|
1937 TDA_SM1_ERR_ALARM
| TDA_Fn_ECC_SG_ERR
|
1938 TDA_PCIX_ERR
, flag
, &bar0
->tda_err_mask
);
1940 do_s2io_write_bits(PCC_FB_ECC_DB_ERR
| PCC_TXB_ECC_DB_ERR
|
1941 PCC_SM_ERR_ALARM
| PCC_WR_ERR_ALARM
|
1942 PCC_N_SERR
| PCC_6_COF_OV_ERR
|
1943 PCC_7_COF_OV_ERR
| PCC_6_LSO_OV_ERR
|
1944 PCC_7_LSO_OV_ERR
| PCC_FB_ECC_SG_ERR
|
1946 flag
, &bar0
->pcc_err_mask
);
1948 do_s2io_write_bits(TTI_SM_ERR_ALARM
| TTI_ECC_SG_ERR
|
1949 TTI_ECC_DB_ERR
, flag
, &bar0
->tti_err_mask
);
1951 do_s2io_write_bits(LSO6_ABORT
| LSO7_ABORT
|
1952 LSO6_SM_ERR_ALARM
| LSO7_SM_ERR_ALARM
|
1953 LSO6_SEND_OFLOW
| LSO7_SEND_OFLOW
,
1954 flag
, &bar0
->lso_err_mask
);
1956 do_s2io_write_bits(TPA_SM_ERR_ALARM
| TPA_TX_FRM_DROP
,
1957 flag
, &bar0
->tpa_err_mask
);
1959 do_s2io_write_bits(SM_SM_ERR_ALARM
, flag
, &bar0
->sm_err_mask
);
1962 if (mask
& TX_MAC_INTR
) {
1963 gen_int_mask
|= TXMAC_INT_M
;
1964 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT
, flag
,
1965 &bar0
->mac_int_mask
);
1966 do_s2io_write_bits(TMAC_TX_BUF_OVRN
| TMAC_TX_SM_ERR
|
1967 TMAC_ECC_SG_ERR
| TMAC_ECC_DB_ERR
|
1968 TMAC_DESC_ECC_SG_ERR
| TMAC_DESC_ECC_DB_ERR
,
1969 flag
, &bar0
->mac_tmac_err_mask
);
1972 if (mask
& TX_XGXS_INTR
) {
1973 gen_int_mask
|= TXXGXS_INT_M
;
1974 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS
, flag
,
1975 &bar0
->xgxs_int_mask
);
1976 do_s2io_write_bits(TXGXS_ESTORE_UFLOW
| TXGXS_TX_SM_ERR
|
1977 TXGXS_ECC_SG_ERR
| TXGXS_ECC_DB_ERR
,
1978 flag
, &bar0
->xgxs_txgxs_err_mask
);
1981 if (mask
& RX_DMA_INTR
) {
1982 gen_int_mask
|= RXDMA_INT_M
;
1983 do_s2io_write_bits(RXDMA_INT_RC_INT_M
| RXDMA_INT_RPA_INT_M
|
1984 RXDMA_INT_RDA_INT_M
| RXDMA_INT_RTI_INT_M
,
1985 flag
, &bar0
->rxdma_int_mask
);
1986 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR
| RC_FTC_ECC_DB_ERR
|
1987 RC_PRCn_SM_ERR_ALARM
| RC_FTC_SM_ERR_ALARM
|
1988 RC_PRCn_ECC_SG_ERR
| RC_FTC_ECC_SG_ERR
|
1989 RC_RDA_FAIL_WR_Rn
, flag
, &bar0
->rc_err_mask
);
1990 do_s2io_write_bits(PRC_PCI_AB_RD_Rn
| PRC_PCI_AB_WR_Rn
|
1991 PRC_PCI_AB_F_WR_Rn
| PRC_PCI_DP_RD_Rn
|
1992 PRC_PCI_DP_WR_Rn
| PRC_PCI_DP_F_WR_Rn
, flag
,
1993 &bar0
->prc_pcix_err_mask
);
1994 do_s2io_write_bits(RPA_SM_ERR_ALARM
| RPA_CREDIT_ERR
|
1995 RPA_ECC_SG_ERR
| RPA_ECC_DB_ERR
, flag
,
1996 &bar0
->rpa_err_mask
);
1997 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR
| RDA_FRM_ECC_DB_N_AERR
|
1998 RDA_SM1_ERR_ALARM
| RDA_SM0_ERR_ALARM
|
1999 RDA_RXD_ECC_DB_SERR
| RDA_RXDn_ECC_SG_ERR
|
2000 RDA_FRM_ECC_SG_ERR
|
2001 RDA_MISC_ERR
|RDA_PCIX_ERR
,
2002 flag
, &bar0
->rda_err_mask
);
2003 do_s2io_write_bits(RTI_SM_ERR_ALARM
|
2004 RTI_ECC_SG_ERR
| RTI_ECC_DB_ERR
,
2005 flag
, &bar0
->rti_err_mask
);
2008 if (mask
& RX_MAC_INTR
) {
2009 gen_int_mask
|= RXMAC_INT_M
;
2010 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT
, flag
,
2011 &bar0
->mac_int_mask
);
2012 interruptible
= (RMAC_RX_BUFF_OVRN
| RMAC_RX_SM_ERR
|
2013 RMAC_UNUSED_INT
| RMAC_SINGLE_ECC_ERR
|
2014 RMAC_DOUBLE_ECC_ERR
);
2015 if (s2io_link_fault_indication(nic
) == MAC_RMAC_ERR_TIMER
)
2016 interruptible
|= RMAC_LINK_STATE_CHANGE_INT
;
2017 do_s2io_write_bits(interruptible
,
2018 flag
, &bar0
->mac_rmac_err_mask
);
2021 if (mask
& RX_XGXS_INTR
) {
2022 gen_int_mask
|= RXXGXS_INT_M
;
2023 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS
, flag
,
2024 &bar0
->xgxs_int_mask
);
2025 do_s2io_write_bits(RXGXS_ESTORE_OFLOW
| RXGXS_RX_SM_ERR
, flag
,
2026 &bar0
->xgxs_rxgxs_err_mask
);
2029 if (mask
& MC_INTR
) {
2030 gen_int_mask
|= MC_INT_M
;
2031 do_s2io_write_bits(MC_INT_MASK_MC_INT
,
2032 flag
, &bar0
->mc_int_mask
);
2033 do_s2io_write_bits(MC_ERR_REG_SM_ERR
| MC_ERR_REG_ECC_ALL_SNG
|
2034 MC_ERR_REG_ECC_ALL_DBL
| PLL_LOCK_N
, flag
,
2035 &bar0
->mc_err_mask
);
2037 nic
->general_int_mask
= gen_int_mask
;
2039 /* Remove this line when alarm interrupts are enabled */
2040 nic
->general_int_mask
= 0;
2044 * en_dis_able_nic_intrs - Enable or Disable the interrupts
2045 * @nic: device private variable,
2046 * @mask: A mask indicating which Intr block must be modified and,
2047 * @flag: A flag indicating whether to enable or disable the Intrs.
2048 * Description: This function will either disable or enable the interrupts
2049 * depending on the flag argument. The mask argument can be used to
2050 * enable/disable any Intr block.
2051 * Return Value: NONE.
2054 static void en_dis_able_nic_intrs(struct s2io_nic
*nic
, u16 mask
, int flag
)
2056 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
2057 register u64 temp64
= 0, intr_mask
= 0;
2059 intr_mask
= nic
->general_int_mask
;
2061 /* Top level interrupt classification */
2062 /* PIC Interrupts */
2063 if (mask
& TX_PIC_INTR
) {
2064 /* Enable PIC Intrs in the general intr mask register */
2065 intr_mask
|= TXPIC_INT_M
;
2066 if (flag
== ENABLE_INTRS
) {
2068 * If Hercules adapter enable GPIO otherwise
2069 * disable all PCIX, Flash, MDIO, IIC and GPIO
2070 * interrupts for now.
2073 if (s2io_link_fault_indication(nic
) ==
2074 LINK_UP_DOWN_INTERRUPT
) {
2075 do_s2io_write_bits(PIC_INT_GPIO
, flag
,
2076 &bar0
->pic_int_mask
);
2077 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP
, flag
,
2078 &bar0
->gpio_int_mask
);
2080 writeq(DISABLE_ALL_INTRS
, &bar0
->pic_int_mask
);
2081 } else if (flag
== DISABLE_INTRS
) {
2083 * Disable PIC Intrs in the general
2084 * intr mask register
2086 writeq(DISABLE_ALL_INTRS
, &bar0
->pic_int_mask
);
2090 /* Tx traffic interrupts */
2091 if (mask
& TX_TRAFFIC_INTR
) {
2092 intr_mask
|= TXTRAFFIC_INT_M
;
2093 if (flag
== ENABLE_INTRS
) {
2095 * Enable all the Tx side interrupts
2096 * writing 0 Enables all 64 TX interrupt levels
2098 writeq(0x0, &bar0
->tx_traffic_mask
);
2099 } else if (flag
== DISABLE_INTRS
) {
2101 * Disable Tx Traffic Intrs in the general intr mask
2104 writeq(DISABLE_ALL_INTRS
, &bar0
->tx_traffic_mask
);
2108 /* Rx traffic interrupts */
2109 if (mask
& RX_TRAFFIC_INTR
) {
2110 intr_mask
|= RXTRAFFIC_INT_M
;
2111 if (flag
== ENABLE_INTRS
) {
2112 /* writing 0 Enables all 8 RX interrupt levels */
2113 writeq(0x0, &bar0
->rx_traffic_mask
);
2114 } else if (flag
== DISABLE_INTRS
) {
2116 * Disable Rx Traffic Intrs in the general intr mask
2119 writeq(DISABLE_ALL_INTRS
, &bar0
->rx_traffic_mask
);
2123 temp64
= readq(&bar0
->general_int_mask
);
2124 if (flag
== ENABLE_INTRS
)
2125 temp64
&= ~((u64
)intr_mask
);
2127 temp64
= DISABLE_ALL_INTRS
;
2128 writeq(temp64
, &bar0
->general_int_mask
);
2130 nic
->general_int_mask
= readq(&bar0
->general_int_mask
);
2134 * verify_pcc_quiescent- Checks for PCC quiescent state
2135 * Return: 1 If PCC is quiescence
2136 * 0 If PCC is not quiescence
2138 static int verify_pcc_quiescent(struct s2io_nic
*sp
, int flag
)
2141 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
2142 u64 val64
= readq(&bar0
->adapter_status
);
2144 herc
= (sp
->device_type
== XFRAME_II_DEVICE
);
2146 if (flag
== false) {
2147 if ((!herc
&& (sp
->pdev
->revision
>= 4)) || herc
) {
2148 if (!(val64
& ADAPTER_STATUS_RMAC_PCC_IDLE
))
2151 if (!(val64
& ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE
))
2155 if ((!herc
&& (sp
->pdev
->revision
>= 4)) || herc
) {
2156 if (((val64
& ADAPTER_STATUS_RMAC_PCC_IDLE
) ==
2157 ADAPTER_STATUS_RMAC_PCC_IDLE
))
2160 if (((val64
& ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE
) ==
2161 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE
))
2169 * verify_xena_quiescence - Checks whether the H/W is ready
2170 * Description: Returns whether the H/W is ready to go or not. Depending
2171 * on whether adapter enable bit was written or not the comparison
2172 * differs and the calling function passes the input argument flag to
2174 * Return: 1 If xena is quiescence
2175 * 0 If Xena is not quiescence
2178 static int verify_xena_quiescence(struct s2io_nic
*sp
)
2181 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
2182 u64 val64
= readq(&bar0
->adapter_status
);
2183 mode
= s2io_verify_pci_mode(sp
);
2185 if (!(val64
& ADAPTER_STATUS_TDMA_READY
)) {
2186 DBG_PRINT(ERR_DBG
, "TDMA is not ready!\n");
2189 if (!(val64
& ADAPTER_STATUS_RDMA_READY
)) {
2190 DBG_PRINT(ERR_DBG
, "RDMA is not ready!\n");
2193 if (!(val64
& ADAPTER_STATUS_PFC_READY
)) {
2194 DBG_PRINT(ERR_DBG
, "PFC is not ready!\n");
2197 if (!(val64
& ADAPTER_STATUS_TMAC_BUF_EMPTY
)) {
2198 DBG_PRINT(ERR_DBG
, "TMAC BUF is not empty!\n");
2201 if (!(val64
& ADAPTER_STATUS_PIC_QUIESCENT
)) {
2202 DBG_PRINT(ERR_DBG
, "PIC is not QUIESCENT!\n");
2205 if (!(val64
& ADAPTER_STATUS_MC_DRAM_READY
)) {
2206 DBG_PRINT(ERR_DBG
, "MC_DRAM is not ready!\n");
2209 if (!(val64
& ADAPTER_STATUS_MC_QUEUES_READY
)) {
2210 DBG_PRINT(ERR_DBG
, "MC_QUEUES is not ready!\n");
2213 if (!(val64
& ADAPTER_STATUS_M_PLL_LOCK
)) {
2214 DBG_PRINT(ERR_DBG
, "M_PLL is not locked!\n");
2219 * In PCI 33 mode, the P_PLL is not used, and therefore,
2220 * the the P_PLL_LOCK bit in the adapter_status register will
2223 if (!(val64
& ADAPTER_STATUS_P_PLL_LOCK
) &&
2224 sp
->device_type
== XFRAME_II_DEVICE
&&
2225 mode
!= PCI_MODE_PCI_33
) {
2226 DBG_PRINT(ERR_DBG
, "P_PLL is not locked!\n");
2229 if (!((val64
& ADAPTER_STATUS_RC_PRC_QUIESCENT
) ==
2230 ADAPTER_STATUS_RC_PRC_QUIESCENT
)) {
2231 DBG_PRINT(ERR_DBG
, "RC_PRC is not QUIESCENT!\n");
2238 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
2239 * @sp: Pointer to device specifc structure
2241 * New procedure to clear mac address reading problems on Alpha platforms
2245 static void fix_mac_address(struct s2io_nic
*sp
)
2247 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
2250 while (fix_mac
[i
] != END_SIGN
) {
2251 writeq(fix_mac
[i
++], &bar0
->gpio_control
);
2253 (void) readq(&bar0
->gpio_control
);
2258 * start_nic - Turns the device on
2259 * @nic : device private variable.
2261 * This function actually turns the device on. Before this function is
2262 * called,all Registers are configured from their reset states
2263 * and shared memory is allocated but the NIC is still quiescent. On
2264 * calling this function, the device interrupts are cleared and the NIC is
2265 * literally switched on by writing into the adapter control register.
2267 * SUCCESS on success and -1 on failure.
2270 static int start_nic(struct s2io_nic
*nic
)
2272 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
2273 struct net_device
*dev
= nic
->dev
;
2274 register u64 val64
= 0;
2276 struct config_param
*config
= &nic
->config
;
2277 struct mac_info
*mac_control
= &nic
->mac_control
;
2279 /* PRC Initialization and configuration */
2280 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2281 struct ring_info
*ring
= &mac_control
->rings
[i
];
2283 writeq((u64
)ring
->rx_blocks
[0].block_dma_addr
,
2284 &bar0
->prc_rxd0_n
[i
]);
2286 val64
= readq(&bar0
->prc_ctrl_n
[i
]);
2287 if (nic
->rxd_mode
== RXD_MODE_1
)
2288 val64
|= PRC_CTRL_RC_ENABLED
;
2290 val64
|= PRC_CTRL_RC_ENABLED
| PRC_CTRL_RING_MODE_3
;
2291 if (nic
->device_type
== XFRAME_II_DEVICE
)
2292 val64
|= PRC_CTRL_GROUP_READS
;
2293 val64
&= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2294 val64
|= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2295 writeq(val64
, &bar0
->prc_ctrl_n
[i
]);
2298 if (nic
->rxd_mode
== RXD_MODE_3B
) {
2299 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2300 val64
= readq(&bar0
->rx_pa_cfg
);
2301 val64
|= RX_PA_CFG_IGNORE_L2_ERR
;
2302 writeq(val64
, &bar0
->rx_pa_cfg
);
2305 if (vlan_tag_strip
== 0) {
2306 val64
= readq(&bar0
->rx_pa_cfg
);
2307 val64
&= ~RX_PA_CFG_STRIP_VLAN_TAG
;
2308 writeq(val64
, &bar0
->rx_pa_cfg
);
2309 nic
->vlan_strip_flag
= 0;
2313 * Enabling MC-RLDRAM. After enabling the device, we timeout
2314 * for around 100ms, which is approximately the time required
2315 * for the device to be ready for operation.
2317 val64
= readq(&bar0
->mc_rldram_mrs
);
2318 val64
|= MC_RLDRAM_QUEUE_SIZE_ENABLE
| MC_RLDRAM_MRS_ENABLE
;
2319 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_mrs
, UF
);
2320 val64
= readq(&bar0
->mc_rldram_mrs
);
2322 msleep(100); /* Delay by around 100 ms. */
2324 /* Enabling ECC Protection. */
2325 val64
= readq(&bar0
->adapter_control
);
2326 val64
&= ~ADAPTER_ECC_EN
;
2327 writeq(val64
, &bar0
->adapter_control
);
2330 * Verify if the device is ready to be enabled, if so enable
2333 val64
= readq(&bar0
->adapter_status
);
2334 if (!verify_xena_quiescence(nic
)) {
2335 DBG_PRINT(ERR_DBG
, "%s: device is not ready, "
2336 "Adapter status reads: 0x%llx\n",
2337 dev
->name
, (unsigned long long)val64
);
2342 * With some switches, link might be already up at this point.
2343 * Because of this weird behavior, when we enable laser,
2344 * we may not get link. We need to handle this. We cannot
2345 * figure out which switch is misbehaving. So we are forced to
2346 * make a global change.
2349 /* Enabling Laser. */
2350 val64
= readq(&bar0
->adapter_control
);
2351 val64
|= ADAPTER_EOI_TX_ON
;
2352 writeq(val64
, &bar0
->adapter_control
);
2354 if (s2io_link_fault_indication(nic
) == MAC_RMAC_ERR_TIMER
) {
2356 * Dont see link state interrupts initially on some switches,
2357 * so directly scheduling the link state task here.
2359 schedule_work(&nic
->set_link_task
);
2361 /* SXE-002: Initialize link and activity LED */
2362 subid
= nic
->pdev
->subsystem_device
;
2363 if (((subid
& 0xFF) >= 0x07) &&
2364 (nic
->device_type
== XFRAME_I_DEVICE
)) {
2365 val64
= readq(&bar0
->gpio_control
);
2366 val64
|= 0x0000800000000000ULL
;
2367 writeq(val64
, &bar0
->gpio_control
);
2368 val64
= 0x0411040400000000ULL
;
2369 writeq(val64
, (void __iomem
*)bar0
+ 0x2700);
2375 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2377 static struct sk_buff
*s2io_txdl_getskb(struct fifo_info
*fifo_data
,
2378 struct TxD
*txdlp
, int get_off
)
2380 struct s2io_nic
*nic
= fifo_data
->nic
;
2381 struct sk_buff
*skb
;
2386 if (txds
->Host_Control
== (u64
)(long)fifo_data
->ufo_in_band_v
) {
2387 pci_unmap_single(nic
->pdev
, (dma_addr_t
)txds
->Buffer_Pointer
,
2388 sizeof(u64
), PCI_DMA_TODEVICE
);
2392 skb
= (struct sk_buff
*)((unsigned long)txds
->Host_Control
);
2394 memset(txdlp
, 0, (sizeof(struct TxD
) * fifo_data
->max_txds
));
2397 pci_unmap_single(nic
->pdev
, (dma_addr_t
)txds
->Buffer_Pointer
,
2398 skb_headlen(skb
), PCI_DMA_TODEVICE
);
2399 frg_cnt
= skb_shinfo(skb
)->nr_frags
;
2402 for (j
= 0; j
< frg_cnt
; j
++, txds
++) {
2403 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[j
];
2404 if (!txds
->Buffer_Pointer
)
2406 pci_unmap_page(nic
->pdev
,
2407 (dma_addr_t
)txds
->Buffer_Pointer
,
2408 frag
->size
, PCI_DMA_TODEVICE
);
2411 memset(txdlp
, 0, (sizeof(struct TxD
) * fifo_data
->max_txds
));
2416 * free_tx_buffers - Free all queued Tx buffers
2417 * @nic : device private variable.
2419 * Free all queued Tx buffers.
2420 * Return Value: void
2423 static void free_tx_buffers(struct s2io_nic
*nic
)
2425 struct net_device
*dev
= nic
->dev
;
2426 struct sk_buff
*skb
;
2430 struct config_param
*config
= &nic
->config
;
2431 struct mac_info
*mac_control
= &nic
->mac_control
;
2432 struct stat_block
*stats
= mac_control
->stats_info
;
2433 struct swStat
*swstats
= &stats
->sw_stat
;
2435 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
2436 struct tx_fifo_config
*tx_cfg
= &config
->tx_cfg
[i
];
2437 struct fifo_info
*fifo
= &mac_control
->fifos
[i
];
2438 unsigned long flags
;
2440 spin_lock_irqsave(&fifo
->tx_lock
, flags
);
2441 for (j
= 0; j
< tx_cfg
->fifo_len
; j
++) {
2442 txdp
= fifo
->list_info
[j
].list_virt_addr
;
2443 skb
= s2io_txdl_getskb(&mac_control
->fifos
[i
], txdp
, j
);
2445 swstats
->mem_freed
+= skb
->truesize
;
2451 "%s: forcibly freeing %d skbs on FIFO%d\n",
2453 fifo
->tx_curr_get_info
.offset
= 0;
2454 fifo
->tx_curr_put_info
.offset
= 0;
2455 spin_unlock_irqrestore(&fifo
->tx_lock
, flags
);
2460 * stop_nic - To stop the nic
2461 * @nic ; device private variable.
2463 * This function does exactly the opposite of what the start_nic()
2464 * function does. This function is called to stop the device.
2469 static void stop_nic(struct s2io_nic
*nic
)
2471 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
2472 register u64 val64
= 0;
2475 /* Disable all interrupts */
2476 en_dis_err_alarms(nic
, ENA_ALL_INTRS
, DISABLE_INTRS
);
2477 interruptible
= TX_TRAFFIC_INTR
| RX_TRAFFIC_INTR
;
2478 interruptible
|= TX_PIC_INTR
;
2479 en_dis_able_nic_intrs(nic
, interruptible
, DISABLE_INTRS
);
2481 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2482 val64
= readq(&bar0
->adapter_control
);
2483 val64
&= ~(ADAPTER_CNTL_EN
);
2484 writeq(val64
, &bar0
->adapter_control
);
2488 * fill_rx_buffers - Allocates the Rx side skbs
2489 * @ring_info: per ring structure
2490 * @from_card_up: If this is true, we will map the buffer to get
2491 * the dma address for buf0 and buf1 to give it to the card.
2492 * Else we will sync the already mapped buffer to give it to the card.
2494 * The function allocates Rx side skbs and puts the physical
2495 * address of these buffers into the RxD buffer pointers, so that the NIC
2496 * can DMA the received frame into these locations.
2497 * The NIC supports 3 receive modes, viz
2499 * 2. three buffer and
2500 * 3. Five buffer modes.
2501 * Each mode defines how many fragments the received frame will be split
2502 * up into by the NIC. The frame is split into L3 header, L4 Header,
2503 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2504 * is split into 3 fragments. As of now only single buffer mode is
2507 * SUCCESS on success or an appropriate -ve value on failure.
2509 static int fill_rx_buffers(struct s2io_nic
*nic
, struct ring_info
*ring
,
2512 struct sk_buff
*skb
;
2514 int off
, size
, block_no
, block_no1
;
2519 struct RxD_t
*first_rxdp
= NULL
;
2520 u64 Buffer0_ptr
= 0, Buffer1_ptr
= 0;
2524 struct swStat
*swstats
= &ring
->nic
->mac_control
.stats_info
->sw_stat
;
2526 alloc_cnt
= ring
->pkt_cnt
- ring
->rx_bufs_left
;
2528 block_no1
= ring
->rx_curr_get_info
.block_index
;
2529 while (alloc_tab
< alloc_cnt
) {
2530 block_no
= ring
->rx_curr_put_info
.block_index
;
2532 off
= ring
->rx_curr_put_info
.offset
;
2534 rxdp
= ring
->rx_blocks
[block_no
].rxds
[off
].virt_addr
;
2536 rxd_index
= off
+ 1;
2538 rxd_index
+= (block_no
* ring
->rxd_count
);
2540 if ((block_no
== block_no1
) &&
2541 (off
== ring
->rx_curr_get_info
.offset
) &&
2542 (rxdp
->Host_Control
)) {
2543 DBG_PRINT(INTR_DBG
, "%s: Get and Put info equated\n",
2547 if (off
&& (off
== ring
->rxd_count
)) {
2548 ring
->rx_curr_put_info
.block_index
++;
2549 if (ring
->rx_curr_put_info
.block_index
==
2551 ring
->rx_curr_put_info
.block_index
= 0;
2552 block_no
= ring
->rx_curr_put_info
.block_index
;
2554 ring
->rx_curr_put_info
.offset
= off
;
2555 rxdp
= ring
->rx_blocks
[block_no
].block_virt_addr
;
2556 DBG_PRINT(INTR_DBG
, "%s: Next block at: %p\n",
2557 ring
->dev
->name
, rxdp
);
2561 if ((rxdp
->Control_1
& RXD_OWN_XENA
) &&
2562 ((ring
->rxd_mode
== RXD_MODE_3B
) &&
2563 (rxdp
->Control_2
& s2BIT(0)))) {
2564 ring
->rx_curr_put_info
.offset
= off
;
2567 /* calculate size of skb based on ring mode */
2569 HEADER_ETHERNET_II_802_3_SIZE
+
2570 HEADER_802_2_SIZE
+ HEADER_SNAP_SIZE
;
2571 if (ring
->rxd_mode
== RXD_MODE_1
)
2572 size
+= NET_IP_ALIGN
;
2574 size
= ring
->mtu
+ ALIGN_SIZE
+ BUF0_LEN
+ 4;
2577 skb
= dev_alloc_skb(size
);
2579 DBG_PRINT(INFO_DBG
, "%s: Could not allocate skb\n",
2583 first_rxdp
->Control_1
|= RXD_OWN_XENA
;
2585 swstats
->mem_alloc_fail_cnt
++;
2589 swstats
->mem_allocated
+= skb
->truesize
;
2591 if (ring
->rxd_mode
== RXD_MODE_1
) {
2592 /* 1 buffer mode - normal operation mode */
2593 rxdp1
= (struct RxD1
*)rxdp
;
2594 memset(rxdp
, 0, sizeof(struct RxD1
));
2595 skb_reserve(skb
, NET_IP_ALIGN
);
2596 rxdp1
->Buffer0_ptr
=
2597 pci_map_single(ring
->pdev
, skb
->data
,
2598 size
- NET_IP_ALIGN
,
2599 PCI_DMA_FROMDEVICE
);
2600 if (pci_dma_mapping_error(nic
->pdev
,
2601 rxdp1
->Buffer0_ptr
))
2602 goto pci_map_failed
;
2605 SET_BUFFER0_SIZE_1(size
- NET_IP_ALIGN
);
2606 rxdp
->Host_Control
= (unsigned long)skb
;
2607 } else if (ring
->rxd_mode
== RXD_MODE_3B
) {
2610 * 2 buffer mode provides 128
2611 * byte aligned receive buffers.
2614 rxdp3
= (struct RxD3
*)rxdp
;
2615 /* save buffer pointers to avoid frequent dma mapping */
2616 Buffer0_ptr
= rxdp3
->Buffer0_ptr
;
2617 Buffer1_ptr
= rxdp3
->Buffer1_ptr
;
2618 memset(rxdp
, 0, sizeof(struct RxD3
));
2619 /* restore the buffer pointers for dma sync*/
2620 rxdp3
->Buffer0_ptr
= Buffer0_ptr
;
2621 rxdp3
->Buffer1_ptr
= Buffer1_ptr
;
2623 ba
= &ring
->ba
[block_no
][off
];
2624 skb_reserve(skb
, BUF0_LEN
);
2625 tmp
= (u64
)(unsigned long)skb
->data
;
2628 skb
->data
= (void *) (unsigned long)tmp
;
2629 skb_reset_tail_pointer(skb
);
2632 rxdp3
->Buffer0_ptr
=
2633 pci_map_single(ring
->pdev
, ba
->ba_0
,
2635 PCI_DMA_FROMDEVICE
);
2636 if (pci_dma_mapping_error(nic
->pdev
,
2637 rxdp3
->Buffer0_ptr
))
2638 goto pci_map_failed
;
2640 pci_dma_sync_single_for_device(ring
->pdev
,
2641 (dma_addr_t
)rxdp3
->Buffer0_ptr
,
2643 PCI_DMA_FROMDEVICE
);
2645 rxdp
->Control_2
= SET_BUFFER0_SIZE_3(BUF0_LEN
);
2646 if (ring
->rxd_mode
== RXD_MODE_3B
) {
2647 /* Two buffer mode */
2650 * Buffer2 will have L3/L4 header plus
2653 rxdp3
->Buffer2_ptr
= pci_map_single(ring
->pdev
,
2656 PCI_DMA_FROMDEVICE
);
2658 if (pci_dma_mapping_error(nic
->pdev
,
2659 rxdp3
->Buffer2_ptr
))
2660 goto pci_map_failed
;
2663 rxdp3
->Buffer1_ptr
=
2664 pci_map_single(ring
->pdev
,
2667 PCI_DMA_FROMDEVICE
);
2669 if (pci_dma_mapping_error(nic
->pdev
,
2670 rxdp3
->Buffer1_ptr
)) {
2671 pci_unmap_single(ring
->pdev
,
2672 (dma_addr_t
)(unsigned long)
2675 PCI_DMA_FROMDEVICE
);
2676 goto pci_map_failed
;
2679 rxdp
->Control_2
|= SET_BUFFER1_SIZE_3(1);
2680 rxdp
->Control_2
|= SET_BUFFER2_SIZE_3
2683 rxdp
->Control_2
|= s2BIT(0);
2684 rxdp
->Host_Control
= (unsigned long) (skb
);
2686 if (alloc_tab
& ((1 << rxsync_frequency
) - 1))
2687 rxdp
->Control_1
|= RXD_OWN_XENA
;
2689 if (off
== (ring
->rxd_count
+ 1))
2691 ring
->rx_curr_put_info
.offset
= off
;
2693 rxdp
->Control_2
|= SET_RXD_MARKER
;
2694 if (!(alloc_tab
& ((1 << rxsync_frequency
) - 1))) {
2697 first_rxdp
->Control_1
|= RXD_OWN_XENA
;
2701 ring
->rx_bufs_left
+= 1;
2706 /* Transfer ownership of first descriptor to adapter just before
2707 * exiting. Before that, use memory barrier so that ownership
2708 * and other fields are seen by adapter correctly.
2712 first_rxdp
->Control_1
|= RXD_OWN_XENA
;
2718 swstats
->pci_map_fail_cnt
++;
2719 swstats
->mem_freed
+= skb
->truesize
;
2720 dev_kfree_skb_irq(skb
);
2724 static void free_rxd_blk(struct s2io_nic
*sp
, int ring_no
, int blk
)
2726 struct net_device
*dev
= sp
->dev
;
2728 struct sk_buff
*skb
;
2732 struct mac_info
*mac_control
= &sp
->mac_control
;
2733 struct stat_block
*stats
= mac_control
->stats_info
;
2734 struct swStat
*swstats
= &stats
->sw_stat
;
2736 for (j
= 0 ; j
< rxd_count
[sp
->rxd_mode
]; j
++) {
2737 rxdp
= mac_control
->rings
[ring_no
].
2738 rx_blocks
[blk
].rxds
[j
].virt_addr
;
2739 skb
= (struct sk_buff
*)((unsigned long)rxdp
->Host_Control
);
2742 if (sp
->rxd_mode
== RXD_MODE_1
) {
2743 rxdp1
= (struct RxD1
*)rxdp
;
2744 pci_unmap_single(sp
->pdev
,
2745 (dma_addr_t
)rxdp1
->Buffer0_ptr
,
2747 HEADER_ETHERNET_II_802_3_SIZE
+
2748 HEADER_802_2_SIZE
+ HEADER_SNAP_SIZE
,
2749 PCI_DMA_FROMDEVICE
);
2750 memset(rxdp
, 0, sizeof(struct RxD1
));
2751 } else if (sp
->rxd_mode
== RXD_MODE_3B
) {
2752 rxdp3
= (struct RxD3
*)rxdp
;
2753 pci_unmap_single(sp
->pdev
,
2754 (dma_addr_t
)rxdp3
->Buffer0_ptr
,
2756 PCI_DMA_FROMDEVICE
);
2757 pci_unmap_single(sp
->pdev
,
2758 (dma_addr_t
)rxdp3
->Buffer1_ptr
,
2760 PCI_DMA_FROMDEVICE
);
2761 pci_unmap_single(sp
->pdev
,
2762 (dma_addr_t
)rxdp3
->Buffer2_ptr
,
2764 PCI_DMA_FROMDEVICE
);
2765 memset(rxdp
, 0, sizeof(struct RxD3
));
2767 swstats
->mem_freed
+= skb
->truesize
;
2769 mac_control
->rings
[ring_no
].rx_bufs_left
-= 1;
2774 * free_rx_buffers - Frees all Rx buffers
2775 * @sp: device private variable.
2777 * This function will free all Rx buffers allocated by host.
2782 static void free_rx_buffers(struct s2io_nic
*sp
)
2784 struct net_device
*dev
= sp
->dev
;
2785 int i
, blk
= 0, buf_cnt
= 0;
2786 struct config_param
*config
= &sp
->config
;
2787 struct mac_info
*mac_control
= &sp
->mac_control
;
2789 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2790 struct ring_info
*ring
= &mac_control
->rings
[i
];
2792 for (blk
= 0; blk
< rx_ring_sz
[i
]; blk
++)
2793 free_rxd_blk(sp
, i
, blk
);
2795 ring
->rx_curr_put_info
.block_index
= 0;
2796 ring
->rx_curr_get_info
.block_index
= 0;
2797 ring
->rx_curr_put_info
.offset
= 0;
2798 ring
->rx_curr_get_info
.offset
= 0;
2799 ring
->rx_bufs_left
= 0;
2800 DBG_PRINT(INIT_DBG
, "%s: Freed 0x%x Rx Buffers on ring%d\n",
2801 dev
->name
, buf_cnt
, i
);
2805 static int s2io_chk_rx_buffers(struct s2io_nic
*nic
, struct ring_info
*ring
)
2807 if (fill_rx_buffers(nic
, ring
, 0) == -ENOMEM
) {
2808 DBG_PRINT(INFO_DBG
, "%s: Out of memory in Rx Intr!!\n",
2815 * s2io_poll - Rx interrupt handler for NAPI support
2816 * @napi : pointer to the napi structure.
2817 * @budget : The number of packets that were budgeted to be processed
2818 * during one pass through the 'Poll" function.
2820 * Comes into picture only if NAPI support has been incorporated. It does
2821 * the same thing that rx_intr_handler does, but not in a interrupt context
2822 * also It will process only a given number of packets.
2824 * 0 on success and 1 if there are No Rx packets to be processed.
2827 static int s2io_poll_msix(struct napi_struct
*napi
, int budget
)
2829 struct ring_info
*ring
= container_of(napi
, struct ring_info
, napi
);
2830 struct net_device
*dev
= ring
->dev
;
2831 int pkts_processed
= 0;
2832 u8 __iomem
*addr
= NULL
;
2834 struct s2io_nic
*nic
= netdev_priv(dev
);
2835 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
2836 int budget_org
= budget
;
2838 if (unlikely(!is_s2io_card_up(nic
)))
2841 pkts_processed
= rx_intr_handler(ring
, budget
);
2842 s2io_chk_rx_buffers(nic
, ring
);
2844 if (pkts_processed
< budget_org
) {
2845 napi_complete(napi
);
2846 /*Re Enable MSI-Rx Vector*/
2847 addr
= (u8 __iomem
*)&bar0
->xmsi_mask_reg
;
2848 addr
+= 7 - ring
->ring_no
;
2849 val8
= (ring
->ring_no
== 0) ? 0x3f : 0xbf;
2853 return pkts_processed
;
2856 static int s2io_poll_inta(struct napi_struct
*napi
, int budget
)
2858 struct s2io_nic
*nic
= container_of(napi
, struct s2io_nic
, napi
);
2859 int pkts_processed
= 0;
2860 int ring_pkts_processed
, i
;
2861 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
2862 int budget_org
= budget
;
2863 struct config_param
*config
= &nic
->config
;
2864 struct mac_info
*mac_control
= &nic
->mac_control
;
2866 if (unlikely(!is_s2io_card_up(nic
)))
2869 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2870 struct ring_info
*ring
= &mac_control
->rings
[i
];
2871 ring_pkts_processed
= rx_intr_handler(ring
, budget
);
2872 s2io_chk_rx_buffers(nic
, ring
);
2873 pkts_processed
+= ring_pkts_processed
;
2874 budget
-= ring_pkts_processed
;
2878 if (pkts_processed
< budget_org
) {
2879 napi_complete(napi
);
2880 /* Re enable the Rx interrupts for the ring */
2881 writeq(0, &bar0
->rx_traffic_mask
);
2882 readl(&bar0
->rx_traffic_mask
);
2884 return pkts_processed
;
2887 #ifdef CONFIG_NET_POLL_CONTROLLER
2889 * s2io_netpoll - netpoll event handler entry point
2890 * @dev : pointer to the device structure.
2892 * This function will be called by upper layer to check for events on the
2893 * interface in situations where interrupts are disabled. It is used for
2894 * specific in-kernel networking tasks, such as remote consoles and kernel
2895 * debugging over the network (example netdump in RedHat).
2897 static void s2io_netpoll(struct net_device
*dev
)
2899 struct s2io_nic
*nic
= netdev_priv(dev
);
2900 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
2901 u64 val64
= 0xFFFFFFFFFFFFFFFFULL
;
2903 struct config_param
*config
= &nic
->config
;
2904 struct mac_info
*mac_control
= &nic
->mac_control
;
2906 if (pci_channel_offline(nic
->pdev
))
2909 disable_irq(dev
->irq
);
2911 writeq(val64
, &bar0
->rx_traffic_int
);
2912 writeq(val64
, &bar0
->tx_traffic_int
);
2914 /* we need to free up the transmitted skbufs or else netpoll will
2915 * run out of skbs and will fail and eventually netpoll application such
2916 * as netdump will fail.
2918 for (i
= 0; i
< config
->tx_fifo_num
; i
++)
2919 tx_intr_handler(&mac_control
->fifos
[i
]);
2921 /* check for received packet and indicate up to network */
2922 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2923 struct ring_info
*ring
= &mac_control
->rings
[i
];
2925 rx_intr_handler(ring
, 0);
2928 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2929 struct ring_info
*ring
= &mac_control
->rings
[i
];
2931 if (fill_rx_buffers(nic
, ring
, 0) == -ENOMEM
) {
2933 "%s: Out of memory in Rx Netpoll!!\n",
2938 enable_irq(dev
->irq
);
2943 * rx_intr_handler - Rx interrupt handler
2944 * @ring_info: per ring structure.
2945 * @budget: budget for napi processing.
2947 * If the interrupt is because of a received frame or if the
2948 * receive ring contains fresh as yet un-processed frames,this function is
2949 * called. It picks out the RxD at which place the last Rx processing had
2950 * stopped and sends the skb to the OSM's Rx handler and then increments
2953 * No. of napi packets processed.
2955 static int rx_intr_handler(struct ring_info
*ring_data
, int budget
)
2957 int get_block
, put_block
;
2958 struct rx_curr_get_info get_info
, put_info
;
2960 struct sk_buff
*skb
;
2961 int pkt_cnt
= 0, napi_pkts
= 0;
2966 get_info
= ring_data
->rx_curr_get_info
;
2967 get_block
= get_info
.block_index
;
2968 memcpy(&put_info
, &ring_data
->rx_curr_put_info
, sizeof(put_info
));
2969 put_block
= put_info
.block_index
;
2970 rxdp
= ring_data
->rx_blocks
[get_block
].rxds
[get_info
.offset
].virt_addr
;
2972 while (RXD_IS_UP2DT(rxdp
)) {
2974 * If your are next to put index then it's
2975 * FIFO full condition
2977 if ((get_block
== put_block
) &&
2978 (get_info
.offset
+ 1) == put_info
.offset
) {
2979 DBG_PRINT(INTR_DBG
, "%s: Ring Full\n",
2980 ring_data
->dev
->name
);
2983 skb
= (struct sk_buff
*)((unsigned long)rxdp
->Host_Control
);
2985 DBG_PRINT(ERR_DBG
, "%s: NULL skb in Rx Intr\n",
2986 ring_data
->dev
->name
);
2989 if (ring_data
->rxd_mode
== RXD_MODE_1
) {
2990 rxdp1
= (struct RxD1
*)rxdp
;
2991 pci_unmap_single(ring_data
->pdev
, (dma_addr_t
)
2994 HEADER_ETHERNET_II_802_3_SIZE
+
2997 PCI_DMA_FROMDEVICE
);
2998 } else if (ring_data
->rxd_mode
== RXD_MODE_3B
) {
2999 rxdp3
= (struct RxD3
*)rxdp
;
3000 pci_dma_sync_single_for_cpu(ring_data
->pdev
,
3001 (dma_addr_t
)rxdp3
->Buffer0_ptr
,
3003 PCI_DMA_FROMDEVICE
);
3004 pci_unmap_single(ring_data
->pdev
,
3005 (dma_addr_t
)rxdp3
->Buffer2_ptr
,
3007 PCI_DMA_FROMDEVICE
);
3009 prefetch(skb
->data
);
3010 rx_osm_handler(ring_data
, rxdp
);
3012 ring_data
->rx_curr_get_info
.offset
= get_info
.offset
;
3013 rxdp
= ring_data
->rx_blocks
[get_block
].
3014 rxds
[get_info
.offset
].virt_addr
;
3015 if (get_info
.offset
== rxd_count
[ring_data
->rxd_mode
]) {
3016 get_info
.offset
= 0;
3017 ring_data
->rx_curr_get_info
.offset
= get_info
.offset
;
3019 if (get_block
== ring_data
->block_count
)
3021 ring_data
->rx_curr_get_info
.block_index
= get_block
;
3022 rxdp
= ring_data
->rx_blocks
[get_block
].block_virt_addr
;
3025 if (ring_data
->nic
->config
.napi
) {
3032 if ((indicate_max_pkts
) && (pkt_cnt
> indicate_max_pkts
))
3035 if (ring_data
->lro
) {
3036 /* Clear all LRO sessions before exiting */
3037 for (i
= 0; i
< MAX_LRO_SESSIONS
; i
++) {
3038 struct lro
*lro
= &ring_data
->lro0_n
[i
];
3040 update_L3L4_header(ring_data
->nic
, lro
);
3041 queue_rx_frame(lro
->parent
, lro
->vlan_tag
);
3042 clear_lro_session(lro
);
3050 * tx_intr_handler - Transmit interrupt handler
3051 * @nic : device private variable
3053 * If an interrupt was raised to indicate DMA complete of the
3054 * Tx packet, this function is called. It identifies the last TxD
3055 * whose buffer was freed and frees all skbs whose data have already
3056 * DMA'ed into the NICs internal memory.
3061 static void tx_intr_handler(struct fifo_info
*fifo_data
)
3063 struct s2io_nic
*nic
= fifo_data
->nic
;
3064 struct tx_curr_get_info get_info
, put_info
;
3065 struct sk_buff
*skb
= NULL
;
3068 unsigned long flags
= 0;
3070 struct stat_block
*stats
= nic
->mac_control
.stats_info
;
3071 struct swStat
*swstats
= &stats
->sw_stat
;
3073 if (!spin_trylock_irqsave(&fifo_data
->tx_lock
, flags
))
3076 get_info
= fifo_data
->tx_curr_get_info
;
3077 memcpy(&put_info
, &fifo_data
->tx_curr_put_info
, sizeof(put_info
));
3078 txdlp
= fifo_data
->list_info
[get_info
.offset
].list_virt_addr
;
3079 while ((!(txdlp
->Control_1
& TXD_LIST_OWN_XENA
)) &&
3080 (get_info
.offset
!= put_info
.offset
) &&
3081 (txdlp
->Host_Control
)) {
3082 /* Check for TxD errors */
3083 if (txdlp
->Control_1
& TXD_T_CODE
) {
3084 unsigned long long err
;
3085 err
= txdlp
->Control_1
& TXD_T_CODE
;
3087 swstats
->parity_err_cnt
++;
3090 /* update t_code statistics */
3091 err_mask
= err
>> 48;
3094 swstats
->tx_buf_abort_cnt
++;
3098 swstats
->tx_desc_abort_cnt
++;
3102 swstats
->tx_parity_err_cnt
++;
3106 swstats
->tx_link_loss_cnt
++;
3110 swstats
->tx_list_proc_err_cnt
++;
3115 skb
= s2io_txdl_getskb(fifo_data
, txdlp
, get_info
.offset
);
3117 spin_unlock_irqrestore(&fifo_data
->tx_lock
, flags
);
3118 DBG_PRINT(ERR_DBG
, "%s: NULL skb in Tx Free Intr\n",
3124 /* Updating the statistics block */
3125 swstats
->mem_freed
+= skb
->truesize
;
3126 dev_kfree_skb_irq(skb
);
3129 if (get_info
.offset
== get_info
.fifo_len
+ 1)
3130 get_info
.offset
= 0;
3131 txdlp
= fifo_data
->list_info
[get_info
.offset
].list_virt_addr
;
3132 fifo_data
->tx_curr_get_info
.offset
= get_info
.offset
;
3135 s2io_wake_tx_queue(fifo_data
, pkt_cnt
, nic
->config
.multiq
);
3137 spin_unlock_irqrestore(&fifo_data
->tx_lock
, flags
);
3141 * s2io_mdio_write - Function to write in to MDIO registers
3142 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3143 * @addr : address value
3144 * @value : data value
3145 * @dev : pointer to net_device structure
3147 * This function is used to write values to the MDIO registers
3150 static void s2io_mdio_write(u32 mmd_type
, u64 addr
, u16 value
,
3151 struct net_device
*dev
)
3154 struct s2io_nic
*sp
= netdev_priv(dev
);
3155 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
3157 /* address transaction */
3158 val64
= MDIO_MMD_INDX_ADDR(addr
) |
3159 MDIO_MMD_DEV_ADDR(mmd_type
) |
3160 MDIO_MMS_PRT_ADDR(0x0);
3161 writeq(val64
, &bar0
->mdio_control
);
3162 val64
= val64
| MDIO_CTRL_START_TRANS(0xE);
3163 writeq(val64
, &bar0
->mdio_control
);
3166 /* Data transaction */
3167 val64
= MDIO_MMD_INDX_ADDR(addr
) |
3168 MDIO_MMD_DEV_ADDR(mmd_type
) |
3169 MDIO_MMS_PRT_ADDR(0x0) |
3170 MDIO_MDIO_DATA(value
) |
3171 MDIO_OP(MDIO_OP_WRITE_TRANS
);
3172 writeq(val64
, &bar0
->mdio_control
);
3173 val64
= val64
| MDIO_CTRL_START_TRANS(0xE);
3174 writeq(val64
, &bar0
->mdio_control
);
3177 val64
= MDIO_MMD_INDX_ADDR(addr
) |
3178 MDIO_MMD_DEV_ADDR(mmd_type
) |
3179 MDIO_MMS_PRT_ADDR(0x0) |
3180 MDIO_OP(MDIO_OP_READ_TRANS
);
3181 writeq(val64
, &bar0
->mdio_control
);
3182 val64
= val64
| MDIO_CTRL_START_TRANS(0xE);
3183 writeq(val64
, &bar0
->mdio_control
);
3188 * s2io_mdio_read - Function to write in to MDIO registers
3189 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3190 * @addr : address value
3191 * @dev : pointer to net_device structure
3193 * This function is used to read values to the MDIO registers
3196 static u64
s2io_mdio_read(u32 mmd_type
, u64 addr
, struct net_device
*dev
)
3200 struct s2io_nic
*sp
= netdev_priv(dev
);
3201 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
3203 /* address transaction */
3204 val64
= val64
| (MDIO_MMD_INDX_ADDR(addr
)
3205 | MDIO_MMD_DEV_ADDR(mmd_type
)
3206 | MDIO_MMS_PRT_ADDR(0x0));
3207 writeq(val64
, &bar0
->mdio_control
);
3208 val64
= val64
| MDIO_CTRL_START_TRANS(0xE);
3209 writeq(val64
, &bar0
->mdio_control
);
3212 /* Data transaction */
3213 val64
= MDIO_MMD_INDX_ADDR(addr
) |
3214 MDIO_MMD_DEV_ADDR(mmd_type
) |
3215 MDIO_MMS_PRT_ADDR(0x0) |
3216 MDIO_OP(MDIO_OP_READ_TRANS
);
3217 writeq(val64
, &bar0
->mdio_control
);
3218 val64
= val64
| MDIO_CTRL_START_TRANS(0xE);
3219 writeq(val64
, &bar0
->mdio_control
);
3222 /* Read the value from regs */
3223 rval64
= readq(&bar0
->mdio_control
);
3224 rval64
= rval64
& 0xFFFF0000;
3225 rval64
= rval64
>> 16;
3230 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
3231 * @counter : counter value to be updated
3232 * @flag : flag to indicate the status
3233 * @type : counter type
3235 * This function is to check the status of the xpak counters value
3239 static void s2io_chk_xpak_counter(u64
*counter
, u64
* regs_stat
, u32 index
,
3245 for (i
= 0; i
< index
; i
++)
3249 *counter
= *counter
+ 1;
3250 val64
= *regs_stat
& mask
;
3251 val64
= val64
>> (index
* 0x2);
3257 "Take Xframe NIC out of service.\n");
3259 "Excessive temperatures may result in premature transceiver failure.\n");
3263 "Take Xframe NIC out of service.\n");
3265 "Excessive bias currents may indicate imminent laser diode failure.\n");
3269 "Take Xframe NIC out of service.\n");
3271 "Excessive laser output power may saturate far-end receiver.\n");
3275 "Incorrect XPAK Alarm type\n");
3279 val64
= val64
<< (index
* 0x2);
3280 *regs_stat
= (*regs_stat
& (~mask
)) | (val64
);
3283 *regs_stat
= *regs_stat
& (~mask
);
3288 * s2io_updt_xpak_counter - Function to update the xpak counters
3289 * @dev : pointer to net_device struct
3291 * This function is to upate the status of the xpak counters value
3294 static void s2io_updt_xpak_counter(struct net_device
*dev
)
3302 struct s2io_nic
*sp
= netdev_priv(dev
);
3303 struct stat_block
*stats
= sp
->mac_control
.stats_info
;
3304 struct xpakStat
*xstats
= &stats
->xpak_stat
;
3306 /* Check the communication with the MDIO slave */
3309 val64
= s2io_mdio_read(MDIO_MMD_PMAPMD
, addr
, dev
);
3310 if ((val64
== 0xFFFF) || (val64
== 0x0000)) {
3312 "ERR: MDIO slave access failed - Returned %llx\n",
3313 (unsigned long long)val64
);
3317 /* Check for the expected value of control reg 1 */
3318 if (val64
!= MDIO_CTRL1_SPEED10G
) {
3319 DBG_PRINT(ERR_DBG
, "Incorrect value at PMA address 0x0000 - "
3320 "Returned: %llx- Expected: 0x%x\n",
3321 (unsigned long long)val64
, MDIO_CTRL1_SPEED10G
);
3325 /* Loading the DOM register to MDIO register */
3327 s2io_mdio_write(MDIO_MMD_PMAPMD
, addr
, val16
, dev
);
3328 val64
= s2io_mdio_read(MDIO_MMD_PMAPMD
, addr
, dev
);
3330 /* Reading the Alarm flags */
3333 val64
= s2io_mdio_read(MDIO_MMD_PMAPMD
, addr
, dev
);
3335 flag
= CHECKBIT(val64
, 0x7);
3337 s2io_chk_xpak_counter(&xstats
->alarm_transceiver_temp_high
,
3338 &xstats
->xpak_regs_stat
,
3341 if (CHECKBIT(val64
, 0x6))
3342 xstats
->alarm_transceiver_temp_low
++;
3344 flag
= CHECKBIT(val64
, 0x3);
3346 s2io_chk_xpak_counter(&xstats
->alarm_laser_bias_current_high
,
3347 &xstats
->xpak_regs_stat
,
3350 if (CHECKBIT(val64
, 0x2))
3351 xstats
->alarm_laser_bias_current_low
++;
3353 flag
= CHECKBIT(val64
, 0x1);
3355 s2io_chk_xpak_counter(&xstats
->alarm_laser_output_power_high
,
3356 &xstats
->xpak_regs_stat
,
3359 if (CHECKBIT(val64
, 0x0))
3360 xstats
->alarm_laser_output_power_low
++;
3362 /* Reading the Warning flags */
3365 val64
= s2io_mdio_read(MDIO_MMD_PMAPMD
, addr
, dev
);
3367 if (CHECKBIT(val64
, 0x7))
3368 xstats
->warn_transceiver_temp_high
++;
3370 if (CHECKBIT(val64
, 0x6))
3371 xstats
->warn_transceiver_temp_low
++;
3373 if (CHECKBIT(val64
, 0x3))
3374 xstats
->warn_laser_bias_current_high
++;
3376 if (CHECKBIT(val64
, 0x2))
3377 xstats
->warn_laser_bias_current_low
++;
3379 if (CHECKBIT(val64
, 0x1))
3380 xstats
->warn_laser_output_power_high
++;
3382 if (CHECKBIT(val64
, 0x0))
3383 xstats
->warn_laser_output_power_low
++;
3387 * wait_for_cmd_complete - waits for a command to complete.
3388 * @sp : private member of the device structure, which is a pointer to the
3389 * s2io_nic structure.
3390 * Description: Function that waits for a command to Write into RMAC
3391 * ADDR DATA registers to be completed and returns either success or
3392 * error depending on whether the command was complete or not.
3394 * SUCCESS on success and FAILURE on failure.
3397 static int wait_for_cmd_complete(void __iomem
*addr
, u64 busy_bit
,
3400 int ret
= FAILURE
, cnt
= 0, delay
= 1;
3403 if ((bit_state
!= S2IO_BIT_RESET
) && (bit_state
!= S2IO_BIT_SET
))
3407 val64
= readq(addr
);
3408 if (bit_state
== S2IO_BIT_RESET
) {
3409 if (!(val64
& busy_bit
)) {
3414 if (val64
& busy_bit
) {
3431 * check_pci_device_id - Checks if the device id is supported
3433 * Description: Function to check if the pci device id is supported by driver.
3434 * Return value: Actual device id if supported else PCI_ANY_ID
3436 static u16
check_pci_device_id(u16 id
)
3439 case PCI_DEVICE_ID_HERC_WIN
:
3440 case PCI_DEVICE_ID_HERC_UNI
:
3441 return XFRAME_II_DEVICE
;
3442 case PCI_DEVICE_ID_S2IO_UNI
:
3443 case PCI_DEVICE_ID_S2IO_WIN
:
3444 return XFRAME_I_DEVICE
;
3451 * s2io_reset - Resets the card.
3452 * @sp : private member of the device structure.
3453 * Description: Function to Reset the card. This function then also
3454 * restores the previously saved PCI configuration space registers as
3455 * the card reset also resets the configuration space.
3460 static void s2io_reset(struct s2io_nic
*sp
)
3462 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
3467 unsigned long long up_cnt
, down_cnt
, up_time
, down_time
, reset_cnt
;
3468 unsigned long long mem_alloc_cnt
, mem_free_cnt
, watchdog_cnt
;
3469 struct stat_block
*stats
;
3470 struct swStat
*swstats
;
3472 DBG_PRINT(INIT_DBG
, "%s: Resetting XFrame card %s\n",
3473 __func__
, pci_name(sp
->pdev
));
3475 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3476 pci_read_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
, &(pci_cmd
));
3478 val64
= SW_RESET_ALL
;
3479 writeq(val64
, &bar0
->sw_reset
);
3480 if (strstr(sp
->product_name
, "CX4"))
3483 for (i
= 0; i
< S2IO_MAX_PCI_CONFIG_SPACE_REINIT
; i
++) {
3485 /* Restore the PCI state saved during initialization. */
3486 pci_restore_state(sp
->pdev
);
3487 pci_save_state(sp
->pdev
);
3488 pci_read_config_word(sp
->pdev
, 0x2, &val16
);
3489 if (check_pci_device_id(val16
) != (u16
)PCI_ANY_ID
)
3494 if (check_pci_device_id(val16
) == (u16
)PCI_ANY_ID
)
3495 DBG_PRINT(ERR_DBG
, "%s SW_Reset failed!\n", __func__
);
3497 pci_write_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
, pci_cmd
);
3501 /* Set swapper to enable I/O register access */
3502 s2io_set_swapper(sp
);
3504 /* restore mac_addr entries */
3505 do_s2io_restore_unicast_mc(sp
);
3507 /* Restore the MSIX table entries from local variables */
3508 restore_xmsi_data(sp
);
3510 /* Clear certain PCI/PCI-X fields after reset */
3511 if (sp
->device_type
== XFRAME_II_DEVICE
) {
3512 /* Clear "detected parity error" bit */
3513 pci_write_config_word(sp
->pdev
, PCI_STATUS
, 0x8000);
3515 /* Clearing PCIX Ecc status register */
3516 pci_write_config_dword(sp
->pdev
, 0x68, 0x7C);
3518 /* Clearing PCI_STATUS error reflected here */
3519 writeq(s2BIT(62), &bar0
->txpic_int_reg
);
3522 /* Reset device statistics maintained by OS */
3523 memset(&sp
->stats
, 0, sizeof(struct net_device_stats
));
3525 stats
= sp
->mac_control
.stats_info
;
3526 swstats
= &stats
->sw_stat
;
3528 /* save link up/down time/cnt, reset/memory/watchdog cnt */
3529 up_cnt
= swstats
->link_up_cnt
;
3530 down_cnt
= swstats
->link_down_cnt
;
3531 up_time
= swstats
->link_up_time
;
3532 down_time
= swstats
->link_down_time
;
3533 reset_cnt
= swstats
->soft_reset_cnt
;
3534 mem_alloc_cnt
= swstats
->mem_allocated
;
3535 mem_free_cnt
= swstats
->mem_freed
;
3536 watchdog_cnt
= swstats
->watchdog_timer_cnt
;
3538 memset(stats
, 0, sizeof(struct stat_block
));
3540 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3541 swstats
->link_up_cnt
= up_cnt
;
3542 swstats
->link_down_cnt
= down_cnt
;
3543 swstats
->link_up_time
= up_time
;
3544 swstats
->link_down_time
= down_time
;
3545 swstats
->soft_reset_cnt
= reset_cnt
;
3546 swstats
->mem_allocated
= mem_alloc_cnt
;
3547 swstats
->mem_freed
= mem_free_cnt
;
3548 swstats
->watchdog_timer_cnt
= watchdog_cnt
;
3550 /* SXE-002: Configure link and activity LED to turn it off */
3551 subid
= sp
->pdev
->subsystem_device
;
3552 if (((subid
& 0xFF) >= 0x07) &&
3553 (sp
->device_type
== XFRAME_I_DEVICE
)) {
3554 val64
= readq(&bar0
->gpio_control
);
3555 val64
|= 0x0000800000000000ULL
;
3556 writeq(val64
, &bar0
->gpio_control
);
3557 val64
= 0x0411040400000000ULL
;
3558 writeq(val64
, (void __iomem
*)bar0
+ 0x2700);
3562 * Clear spurious ECC interrupts that would have occurred on
3563 * XFRAME II cards after reset.
3565 if (sp
->device_type
== XFRAME_II_DEVICE
) {
3566 val64
= readq(&bar0
->pcc_err_reg
);
3567 writeq(val64
, &bar0
->pcc_err_reg
);
3570 sp
->device_enabled_once
= false;
3574 * s2io_set_swapper - to set the swapper controle on the card
3575 * @sp : private member of the device structure,
3576 * pointer to the s2io_nic structure.
3577 * Description: Function to set the swapper control on the card
3578 * correctly depending on the 'endianness' of the system.
3580 * SUCCESS on success and FAILURE on failure.
3583 static int s2io_set_swapper(struct s2io_nic
*sp
)
3585 struct net_device
*dev
= sp
->dev
;
3586 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
3587 u64 val64
, valt
, valr
;
3590 * Set proper endian settings and verify the same by reading
3591 * the PIF Feed-back register.
3594 val64
= readq(&bar0
->pif_rd_swapper_fb
);
3595 if (val64
!= 0x0123456789ABCDEFULL
) {
3597 static const u64 value
[] = {
3598 0xC30000C3C30000C3ULL
, /* FE=1, SE=1 */
3599 0x8100008181000081ULL
, /* FE=1, SE=0 */
3600 0x4200004242000042ULL
, /* FE=0, SE=1 */
3605 writeq(value
[i
], &bar0
->swapper_ctrl
);
3606 val64
= readq(&bar0
->pif_rd_swapper_fb
);
3607 if (val64
== 0x0123456789ABCDEFULL
)
3612 DBG_PRINT(ERR_DBG
, "%s: Endian settings are wrong, "
3613 "feedback read %llx\n",
3614 dev
->name
, (unsigned long long)val64
);
3619 valr
= readq(&bar0
->swapper_ctrl
);
3622 valt
= 0x0123456789ABCDEFULL
;
3623 writeq(valt
, &bar0
->xmsi_address
);
3624 val64
= readq(&bar0
->xmsi_address
);
3626 if (val64
!= valt
) {
3628 static const u64 value
[] = {
3629 0x00C3C30000C3C300ULL
, /* FE=1, SE=1 */
3630 0x0081810000818100ULL
, /* FE=1, SE=0 */
3631 0x0042420000424200ULL
, /* FE=0, SE=1 */
3636 writeq((value
[i
] | valr
), &bar0
->swapper_ctrl
);
3637 writeq(valt
, &bar0
->xmsi_address
);
3638 val64
= readq(&bar0
->xmsi_address
);
3644 unsigned long long x
= val64
;
3646 "Write failed, Xmsi_addr reads:0x%llx\n", x
);
3650 val64
= readq(&bar0
->swapper_ctrl
);
3651 val64
&= 0xFFFF000000000000ULL
;
3655 * The device by default set to a big endian format, so a
3656 * big endian driver need not set anything.
3658 val64
|= (SWAPPER_CTRL_TXP_FE
|
3659 SWAPPER_CTRL_TXP_SE
|
3660 SWAPPER_CTRL_TXD_R_FE
|
3661 SWAPPER_CTRL_TXD_W_FE
|
3662 SWAPPER_CTRL_TXF_R_FE
|
3663 SWAPPER_CTRL_RXD_R_FE
|
3664 SWAPPER_CTRL_RXD_W_FE
|
3665 SWAPPER_CTRL_RXF_W_FE
|
3666 SWAPPER_CTRL_XMSI_FE
|
3667 SWAPPER_CTRL_STATS_FE
|
3668 SWAPPER_CTRL_STATS_SE
);
3669 if (sp
->config
.intr_type
== INTA
)
3670 val64
|= SWAPPER_CTRL_XMSI_SE
;
3671 writeq(val64
, &bar0
->swapper_ctrl
);
3674 * Initially we enable all bits to make it accessible by the
3675 * driver, then we selectively enable only those bits that
3678 val64
|= (SWAPPER_CTRL_TXP_FE
|
3679 SWAPPER_CTRL_TXP_SE
|
3680 SWAPPER_CTRL_TXD_R_FE
|
3681 SWAPPER_CTRL_TXD_R_SE
|
3682 SWAPPER_CTRL_TXD_W_FE
|
3683 SWAPPER_CTRL_TXD_W_SE
|
3684 SWAPPER_CTRL_TXF_R_FE
|
3685 SWAPPER_CTRL_RXD_R_FE
|
3686 SWAPPER_CTRL_RXD_R_SE
|
3687 SWAPPER_CTRL_RXD_W_FE
|
3688 SWAPPER_CTRL_RXD_W_SE
|
3689 SWAPPER_CTRL_RXF_W_FE
|
3690 SWAPPER_CTRL_XMSI_FE
|
3691 SWAPPER_CTRL_STATS_FE
|
3692 SWAPPER_CTRL_STATS_SE
);
3693 if (sp
->config
.intr_type
== INTA
)
3694 val64
|= SWAPPER_CTRL_XMSI_SE
;
3695 writeq(val64
, &bar0
->swapper_ctrl
);
3697 val64
= readq(&bar0
->swapper_ctrl
);
3700 * Verifying if endian settings are accurate by reading a
3701 * feedback register.
3703 val64
= readq(&bar0
->pif_rd_swapper_fb
);
3704 if (val64
!= 0x0123456789ABCDEFULL
) {
3705 /* Endian settings are incorrect, calls for another dekko. */
3707 "%s: Endian settings are wrong, feedback read %llx\n",
3708 dev
->name
, (unsigned long long)val64
);
3715 static int wait_for_msix_trans(struct s2io_nic
*nic
, int i
)
3717 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
3719 int ret
= 0, cnt
= 0;
3722 val64
= readq(&bar0
->xmsi_access
);
3723 if (!(val64
& s2BIT(15)))
3729 DBG_PRINT(ERR_DBG
, "XMSI # %d Access failed\n", i
);
3736 static void restore_xmsi_data(struct s2io_nic
*nic
)
3738 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
3742 if (nic
->device_type
== XFRAME_I_DEVICE
)
3745 for (i
= 0; i
< MAX_REQUESTED_MSI_X
; i
++) {
3746 msix_index
= (i
) ? ((i
-1) * 8 + 1) : 0;
3747 writeq(nic
->msix_info
[i
].addr
, &bar0
->xmsi_address
);
3748 writeq(nic
->msix_info
[i
].data
, &bar0
->xmsi_data
);
3749 val64
= (s2BIT(7) | s2BIT(15) | vBIT(msix_index
, 26, 6));
3750 writeq(val64
, &bar0
->xmsi_access
);
3751 if (wait_for_msix_trans(nic
, msix_index
)) {
3752 DBG_PRINT(ERR_DBG
, "%s: index: %d failed\n",
3753 __func__
, msix_index
);
3759 static void store_xmsi_data(struct s2io_nic
*nic
)
3761 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
3762 u64 val64
, addr
, data
;
3765 if (nic
->device_type
== XFRAME_I_DEVICE
)
3768 /* Store and display */
3769 for (i
= 0; i
< MAX_REQUESTED_MSI_X
; i
++) {
3770 msix_index
= (i
) ? ((i
-1) * 8 + 1) : 0;
3771 val64
= (s2BIT(15) | vBIT(msix_index
, 26, 6));
3772 writeq(val64
, &bar0
->xmsi_access
);
3773 if (wait_for_msix_trans(nic
, msix_index
)) {
3774 DBG_PRINT(ERR_DBG
, "%s: index: %d failed\n",
3775 __func__
, msix_index
);
3778 addr
= readq(&bar0
->xmsi_address
);
3779 data
= readq(&bar0
->xmsi_data
);
3781 nic
->msix_info
[i
].addr
= addr
;
3782 nic
->msix_info
[i
].data
= data
;
3787 static int s2io_enable_msi_x(struct s2io_nic
*nic
)
3789 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
3791 u16 msi_control
; /* Temp variable */
3792 int ret
, i
, j
, msix_indx
= 1;
3794 struct stat_block
*stats
= nic
->mac_control
.stats_info
;
3795 struct swStat
*swstats
= &stats
->sw_stat
;
3797 size
= nic
->num_entries
* sizeof(struct msix_entry
);
3798 nic
->entries
= kzalloc(size
, GFP_KERNEL
);
3799 if (!nic
->entries
) {
3800 DBG_PRINT(INFO_DBG
, "%s: Memory allocation failed\n",
3802 swstats
->mem_alloc_fail_cnt
++;
3805 swstats
->mem_allocated
+= size
;
3807 size
= nic
->num_entries
* sizeof(struct s2io_msix_entry
);
3808 nic
->s2io_entries
= kzalloc(size
, GFP_KERNEL
);
3809 if (!nic
->s2io_entries
) {
3810 DBG_PRINT(INFO_DBG
, "%s: Memory allocation failed\n",
3812 swstats
->mem_alloc_fail_cnt
++;
3813 kfree(nic
->entries
);
3815 += (nic
->num_entries
* sizeof(struct msix_entry
));
3818 swstats
->mem_allocated
+= size
;
3820 nic
->entries
[0].entry
= 0;
3821 nic
->s2io_entries
[0].entry
= 0;
3822 nic
->s2io_entries
[0].in_use
= MSIX_FLG
;
3823 nic
->s2io_entries
[0].type
= MSIX_ALARM_TYPE
;
3824 nic
->s2io_entries
[0].arg
= &nic
->mac_control
.fifos
;
3826 for (i
= 1; i
< nic
->num_entries
; i
++) {
3827 nic
->entries
[i
].entry
= ((i
- 1) * 8) + 1;
3828 nic
->s2io_entries
[i
].entry
= ((i
- 1) * 8) + 1;
3829 nic
->s2io_entries
[i
].arg
= NULL
;
3830 nic
->s2io_entries
[i
].in_use
= 0;
3833 rx_mat
= readq(&bar0
->rx_mat
);
3834 for (j
= 0; j
< nic
->config
.rx_ring_num
; j
++) {
3835 rx_mat
|= RX_MAT_SET(j
, msix_indx
);
3836 nic
->s2io_entries
[j
+1].arg
= &nic
->mac_control
.rings
[j
];
3837 nic
->s2io_entries
[j
+1].type
= MSIX_RING_TYPE
;
3838 nic
->s2io_entries
[j
+1].in_use
= MSIX_FLG
;
3841 writeq(rx_mat
, &bar0
->rx_mat
);
3842 readq(&bar0
->rx_mat
);
3844 ret
= pci_enable_msix(nic
->pdev
, nic
->entries
, nic
->num_entries
);
3845 /* We fail init if error or we get less vectors than min required */
3847 DBG_PRINT(ERR_DBG
, "Enabling MSI-X failed\n");
3848 kfree(nic
->entries
);
3849 swstats
->mem_freed
+= nic
->num_entries
*
3850 sizeof(struct msix_entry
);
3851 kfree(nic
->s2io_entries
);
3852 swstats
->mem_freed
+= nic
->num_entries
*
3853 sizeof(struct s2io_msix_entry
);
3854 nic
->entries
= NULL
;
3855 nic
->s2io_entries
= NULL
;
3860 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3861 * in the herc NIC. (Temp change, needs to be removed later)
3863 pci_read_config_word(nic
->pdev
, 0x42, &msi_control
);
3864 msi_control
|= 0x1; /* Enable MSI */
3865 pci_write_config_word(nic
->pdev
, 0x42, msi_control
);
3870 /* Handle software interrupt used during MSI(X) test */
3871 static irqreturn_t
s2io_test_intr(int irq
, void *dev_id
)
3873 struct s2io_nic
*sp
= dev_id
;
3875 sp
->msi_detected
= 1;
3876 wake_up(&sp
->msi_wait
);
3881 /* Test interrupt path by forcing a a software IRQ */
3882 static int s2io_test_msi(struct s2io_nic
*sp
)
3884 struct pci_dev
*pdev
= sp
->pdev
;
3885 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
3889 err
= request_irq(sp
->entries
[1].vector
, s2io_test_intr
, 0,
3892 DBG_PRINT(ERR_DBG
, "%s: PCI %s: cannot assign irq %d\n",
3893 sp
->dev
->name
, pci_name(pdev
), pdev
->irq
);
3897 init_waitqueue_head(&sp
->msi_wait
);
3898 sp
->msi_detected
= 0;
3900 saved64
= val64
= readq(&bar0
->scheduled_int_ctrl
);
3901 val64
|= SCHED_INT_CTRL_ONE_SHOT
;
3902 val64
|= SCHED_INT_CTRL_TIMER_EN
;
3903 val64
|= SCHED_INT_CTRL_INT2MSI(1);
3904 writeq(val64
, &bar0
->scheduled_int_ctrl
);
3906 wait_event_timeout(sp
->msi_wait
, sp
->msi_detected
, HZ
/10);
3908 if (!sp
->msi_detected
) {
3909 /* MSI(X) test failed, go back to INTx mode */
3910 DBG_PRINT(ERR_DBG
, "%s: PCI %s: No interrupt was generated "
3911 "using MSI(X) during test\n",
3912 sp
->dev
->name
, pci_name(pdev
));
3917 free_irq(sp
->entries
[1].vector
, sp
);
3919 writeq(saved64
, &bar0
->scheduled_int_ctrl
);
3924 static void remove_msix_isr(struct s2io_nic
*sp
)
3929 for (i
= 0; i
< sp
->num_entries
; i
++) {
3930 if (sp
->s2io_entries
[i
].in_use
== MSIX_REGISTERED_SUCCESS
) {
3931 int vector
= sp
->entries
[i
].vector
;
3932 void *arg
= sp
->s2io_entries
[i
].arg
;
3933 free_irq(vector
, arg
);
3938 kfree(sp
->s2io_entries
);
3940 sp
->s2io_entries
= NULL
;
3942 pci_read_config_word(sp
->pdev
, 0x42, &msi_control
);
3943 msi_control
&= 0xFFFE; /* Disable MSI */
3944 pci_write_config_word(sp
->pdev
, 0x42, msi_control
);
3946 pci_disable_msix(sp
->pdev
);
3949 static void remove_inta_isr(struct s2io_nic
*sp
)
3951 struct net_device
*dev
= sp
->dev
;
3953 free_irq(sp
->pdev
->irq
, dev
);
3956 /* ********************************************************* *
3957 * Functions defined below concern the OS part of the driver *
3958 * ********************************************************* */
3961 * s2io_open - open entry point of the driver
3962 * @dev : pointer to the device structure.
3964 * This function is the open entry point of the driver. It mainly calls a
3965 * function to allocate Rx buffers and inserts them into the buffer
3966 * descriptors and then enables the Rx part of the NIC.
3968 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3972 static int s2io_open(struct net_device
*dev
)
3974 struct s2io_nic
*sp
= netdev_priv(dev
);
3975 struct swStat
*swstats
= &sp
->mac_control
.stats_info
->sw_stat
;
3979 * Make sure you have link off by default every time
3980 * Nic is initialized
3982 netif_carrier_off(dev
);
3983 sp
->last_link_state
= 0;
3985 /* Initialize H/W and enable interrupts */
3986 err
= s2io_card_up(sp
);
3988 DBG_PRINT(ERR_DBG
, "%s: H/W initialization failed\n",
3990 goto hw_init_failed
;
3993 if (do_s2io_prog_unicast(dev
, dev
->dev_addr
) == FAILURE
) {
3994 DBG_PRINT(ERR_DBG
, "Set Mac Address Failed\n");
3997 goto hw_init_failed
;
3999 s2io_start_all_tx_queue(sp
);
4003 if (sp
->config
.intr_type
== MSI_X
) {
4006 swstats
->mem_freed
+= sp
->num_entries
*
4007 sizeof(struct msix_entry
);
4009 if (sp
->s2io_entries
) {
4010 kfree(sp
->s2io_entries
);
4011 swstats
->mem_freed
+= sp
->num_entries
*
4012 sizeof(struct s2io_msix_entry
);
4019 * s2io_close -close entry point of the driver
4020 * @dev : device pointer.
4022 * This is the stop entry point of the driver. It needs to undo exactly
4023 * whatever was done by the open entry point,thus it's usually referred to
4024 * as the close function.Among other things this function mainly stops the
4025 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
4027 * 0 on success and an appropriate (-)ve integer as defined in errno.h
4031 static int s2io_close(struct net_device
*dev
)
4033 struct s2io_nic
*sp
= netdev_priv(dev
);
4034 struct config_param
*config
= &sp
->config
;
4038 /* Return if the device is already closed *
4039 * Can happen when s2io_card_up failed in change_mtu *
4041 if (!is_s2io_card_up(sp
))
4044 s2io_stop_all_tx_queue(sp
);
4045 /* delete all populated mac entries */
4046 for (offset
= 1; offset
< config
->max_mc_addr
; offset
++) {
4047 tmp64
= do_s2io_read_unicast_mc(sp
, offset
);
4048 if (tmp64
!= S2IO_DISABLE_MAC_ENTRY
)
4049 do_s2io_delete_unicast_mc(sp
, tmp64
);
4058 * s2io_xmit - Tx entry point of te driver
4059 * @skb : the socket buffer containing the Tx data.
4060 * @dev : device pointer.
4062 * This function is the Tx entry point of the driver. S2IO NIC supports
4063 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
4064 * NOTE: when device can't queue the pkt,just the trans_start variable will
4067 * 0 on success & 1 on failure.
4070 static netdev_tx_t
s2io_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
4072 struct s2io_nic
*sp
= netdev_priv(dev
);
4073 u16 frg_cnt
, frg_len
, i
, queue
, queue_len
, put_off
, get_off
;
4076 struct TxFIFO_element __iomem
*tx_fifo
;
4077 unsigned long flags
= 0;
4079 struct fifo_info
*fifo
= NULL
;
4080 int do_spin_lock
= 1;
4082 int enable_per_list_interrupt
= 0;
4083 struct config_param
*config
= &sp
->config
;
4084 struct mac_info
*mac_control
= &sp
->mac_control
;
4085 struct stat_block
*stats
= mac_control
->stats_info
;
4086 struct swStat
*swstats
= &stats
->sw_stat
;
4088 DBG_PRINT(TX_DBG
, "%s: In Neterion Tx routine\n", dev
->name
);
4090 if (unlikely(skb
->len
<= 0)) {
4091 DBG_PRINT(TX_DBG
, "%s: Buffer has no data..\n", dev
->name
);
4092 dev_kfree_skb_any(skb
);
4093 return NETDEV_TX_OK
;
4096 if (!is_s2io_card_up(sp
)) {
4097 DBG_PRINT(TX_DBG
, "%s: Card going down for reset\n",
4100 return NETDEV_TX_OK
;
4104 if (vlan_tx_tag_present(skb
))
4105 vlan_tag
= vlan_tx_tag_get(skb
);
4106 if (sp
->config
.tx_steering_type
== TX_DEFAULT_STEERING
) {
4107 if (skb
->protocol
== htons(ETH_P_IP
)) {
4112 if (!ip_is_fragment(ip
)) {
4113 th
= (struct tcphdr
*)(((unsigned char *)ip
) +
4116 if (ip
->protocol
== IPPROTO_TCP
) {
4117 queue_len
= sp
->total_tcp_fifos
;
4118 queue
= (ntohs(th
->source
) +
4120 sp
->fifo_selector
[queue_len
- 1];
4121 if (queue
>= queue_len
)
4122 queue
= queue_len
- 1;
4123 } else if (ip
->protocol
== IPPROTO_UDP
) {
4124 queue_len
= sp
->total_udp_fifos
;
4125 queue
= (ntohs(th
->source
) +
4127 sp
->fifo_selector
[queue_len
- 1];
4128 if (queue
>= queue_len
)
4129 queue
= queue_len
- 1;
4130 queue
+= sp
->udp_fifo_idx
;
4131 if (skb
->len
> 1024)
4132 enable_per_list_interrupt
= 1;
4137 } else if (sp
->config
.tx_steering_type
== TX_PRIORITY_STEERING
)
4138 /* get fifo number based on skb->priority value */
4139 queue
= config
->fifo_mapping
4140 [skb
->priority
& (MAX_TX_FIFOS
- 1)];
4141 fifo
= &mac_control
->fifos
[queue
];
4144 spin_lock_irqsave(&fifo
->tx_lock
, flags
);
4146 if (unlikely(!spin_trylock_irqsave(&fifo
->tx_lock
, flags
)))
4147 return NETDEV_TX_LOCKED
;
4150 if (sp
->config
.multiq
) {
4151 if (__netif_subqueue_stopped(dev
, fifo
->fifo_no
)) {
4152 spin_unlock_irqrestore(&fifo
->tx_lock
, flags
);
4153 return NETDEV_TX_BUSY
;
4155 } else if (unlikely(fifo
->queue_state
== FIFO_QUEUE_STOP
)) {
4156 if (netif_queue_stopped(dev
)) {
4157 spin_unlock_irqrestore(&fifo
->tx_lock
, flags
);
4158 return NETDEV_TX_BUSY
;
4162 put_off
= (u16
)fifo
->tx_curr_put_info
.offset
;
4163 get_off
= (u16
)fifo
->tx_curr_get_info
.offset
;
4164 txdp
= fifo
->list_info
[put_off
].list_virt_addr
;
4166 queue_len
= fifo
->tx_curr_put_info
.fifo_len
+ 1;
4167 /* Avoid "put" pointer going beyond "get" pointer */
4168 if (txdp
->Host_Control
||
4169 ((put_off
+1) == queue_len
? 0 : (put_off
+1)) == get_off
) {
4170 DBG_PRINT(TX_DBG
, "Error in xmit, No free TXDs.\n");
4171 s2io_stop_tx_queue(sp
, fifo
->fifo_no
);
4173 spin_unlock_irqrestore(&fifo
->tx_lock
, flags
);
4174 return NETDEV_TX_OK
;
4177 offload_type
= s2io_offload_type(skb
);
4178 if (offload_type
& (SKB_GSO_TCPV4
| SKB_GSO_TCPV6
)) {
4179 txdp
->Control_1
|= TXD_TCP_LSO_EN
;
4180 txdp
->Control_1
|= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb
));
4182 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
4183 txdp
->Control_2
|= (TXD_TX_CKO_IPV4_EN
|
4187 txdp
->Control_1
|= TXD_GATHER_CODE_FIRST
;
4188 txdp
->Control_1
|= TXD_LIST_OWN_XENA
;
4189 txdp
->Control_2
|= TXD_INT_NUMBER(fifo
->fifo_no
);
4190 if (enable_per_list_interrupt
)
4191 if (put_off
& (queue_len
>> 5))
4192 txdp
->Control_2
|= TXD_INT_TYPE_PER_LIST
;
4194 txdp
->Control_2
|= TXD_VLAN_ENABLE
;
4195 txdp
->Control_2
|= TXD_VLAN_TAG(vlan_tag
);
4198 frg_len
= skb_headlen(skb
);
4199 if (offload_type
== SKB_GSO_UDP
) {
4202 ufo_size
= s2io_udp_mss(skb
);
4204 txdp
->Control_1
|= TXD_UFO_EN
;
4205 txdp
->Control_1
|= TXD_UFO_MSS(ufo_size
);
4206 txdp
->Control_1
|= TXD_BUFFER0_SIZE(8);
4208 /* both variants do cpu_to_be64(be32_to_cpu(...)) */
4209 fifo
->ufo_in_band_v
[put_off
] =
4210 (__force u64
)skb_shinfo(skb
)->ip6_frag_id
;
4212 fifo
->ufo_in_band_v
[put_off
] =
4213 (__force u64
)skb_shinfo(skb
)->ip6_frag_id
<< 32;
4215 txdp
->Host_Control
= (unsigned long)fifo
->ufo_in_band_v
;
4216 txdp
->Buffer_Pointer
= pci_map_single(sp
->pdev
,
4217 fifo
->ufo_in_band_v
,
4220 if (pci_dma_mapping_error(sp
->pdev
, txdp
->Buffer_Pointer
))
4221 goto pci_map_failed
;
4225 txdp
->Buffer_Pointer
= pci_map_single(sp
->pdev
, skb
->data
,
4226 frg_len
, PCI_DMA_TODEVICE
);
4227 if (pci_dma_mapping_error(sp
->pdev
, txdp
->Buffer_Pointer
))
4228 goto pci_map_failed
;
4230 txdp
->Host_Control
= (unsigned long)skb
;
4231 txdp
->Control_1
|= TXD_BUFFER0_SIZE(frg_len
);
4232 if (offload_type
== SKB_GSO_UDP
)
4233 txdp
->Control_1
|= TXD_UFO_EN
;
4235 frg_cnt
= skb_shinfo(skb
)->nr_frags
;
4236 /* For fragmented SKB. */
4237 for (i
= 0; i
< frg_cnt
; i
++) {
4238 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
4239 /* A '0' length fragment will be ignored */
4243 txdp
->Buffer_Pointer
= (u64
)pci_map_page(sp
->pdev
, frag
->page
,
4247 txdp
->Control_1
= TXD_BUFFER0_SIZE(frag
->size
);
4248 if (offload_type
== SKB_GSO_UDP
)
4249 txdp
->Control_1
|= TXD_UFO_EN
;
4251 txdp
->Control_1
|= TXD_GATHER_CODE_LAST
;
4253 if (offload_type
== SKB_GSO_UDP
)
4254 frg_cnt
++; /* as Txd0 was used for inband header */
4256 tx_fifo
= mac_control
->tx_FIFO_start
[queue
];
4257 val64
= fifo
->list_info
[put_off
].list_phy_addr
;
4258 writeq(val64
, &tx_fifo
->TxDL_Pointer
);
4260 val64
= (TX_FIFO_LAST_TXD_NUM(frg_cnt
) | TX_FIFO_FIRST_LIST
|
4263 val64
|= TX_FIFO_SPECIAL_FUNC
;
4265 writeq(val64
, &tx_fifo
->List_Control
);
4270 if (put_off
== fifo
->tx_curr_put_info
.fifo_len
+ 1)
4272 fifo
->tx_curr_put_info
.offset
= put_off
;
4274 /* Avoid "put" pointer going beyond "get" pointer */
4275 if (((put_off
+1) == queue_len
? 0 : (put_off
+1)) == get_off
) {
4276 swstats
->fifo_full_cnt
++;
4278 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4280 s2io_stop_tx_queue(sp
, fifo
->fifo_no
);
4282 swstats
->mem_allocated
+= skb
->truesize
;
4283 spin_unlock_irqrestore(&fifo
->tx_lock
, flags
);
4285 if (sp
->config
.intr_type
== MSI_X
)
4286 tx_intr_handler(fifo
);
4288 return NETDEV_TX_OK
;
4291 swstats
->pci_map_fail_cnt
++;
4292 s2io_stop_tx_queue(sp
, fifo
->fifo_no
);
4293 swstats
->mem_freed
+= skb
->truesize
;
4295 spin_unlock_irqrestore(&fifo
->tx_lock
, flags
);
4296 return NETDEV_TX_OK
;
4300 s2io_alarm_handle(unsigned long data
)
4302 struct s2io_nic
*sp
= (struct s2io_nic
*)data
;
4303 struct net_device
*dev
= sp
->dev
;
4305 s2io_handle_errors(dev
);
4306 mod_timer(&sp
->alarm_timer
, jiffies
+ HZ
/ 2);
4309 static irqreturn_t
s2io_msix_ring_handle(int irq
, void *dev_id
)
4311 struct ring_info
*ring
= (struct ring_info
*)dev_id
;
4312 struct s2io_nic
*sp
= ring
->nic
;
4313 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4315 if (unlikely(!is_s2io_card_up(sp
)))
4318 if (sp
->config
.napi
) {
4319 u8 __iomem
*addr
= NULL
;
4322 addr
= (u8 __iomem
*)&bar0
->xmsi_mask_reg
;
4323 addr
+= (7 - ring
->ring_no
);
4324 val8
= (ring
->ring_no
== 0) ? 0x7f : 0xff;
4327 napi_schedule(&ring
->napi
);
4329 rx_intr_handler(ring
, 0);
4330 s2io_chk_rx_buffers(sp
, ring
);
4336 static irqreturn_t
s2io_msix_fifo_handle(int irq
, void *dev_id
)
4339 struct fifo_info
*fifos
= (struct fifo_info
*)dev_id
;
4340 struct s2io_nic
*sp
= fifos
->nic
;
4341 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4342 struct config_param
*config
= &sp
->config
;
4345 if (unlikely(!is_s2io_card_up(sp
)))
4348 reason
= readq(&bar0
->general_int_status
);
4349 if (unlikely(reason
== S2IO_MINUS_ONE
))
4350 /* Nothing much can be done. Get out */
4353 if (reason
& (GEN_INTR_TXPIC
| GEN_INTR_TXTRAFFIC
)) {
4354 writeq(S2IO_MINUS_ONE
, &bar0
->general_int_mask
);
4356 if (reason
& GEN_INTR_TXPIC
)
4357 s2io_txpic_intr_handle(sp
);
4359 if (reason
& GEN_INTR_TXTRAFFIC
)
4360 writeq(S2IO_MINUS_ONE
, &bar0
->tx_traffic_int
);
4362 for (i
= 0; i
< config
->tx_fifo_num
; i
++)
4363 tx_intr_handler(&fifos
[i
]);
4365 writeq(sp
->general_int_mask
, &bar0
->general_int_mask
);
4366 readl(&bar0
->general_int_status
);
4369 /* The interrupt was not raised by us */
4373 static void s2io_txpic_intr_handle(struct s2io_nic
*sp
)
4375 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4378 val64
= readq(&bar0
->pic_int_status
);
4379 if (val64
& PIC_INT_GPIO
) {
4380 val64
= readq(&bar0
->gpio_int_reg
);
4381 if ((val64
& GPIO_INT_REG_LINK_DOWN
) &&
4382 (val64
& GPIO_INT_REG_LINK_UP
)) {
4384 * This is unstable state so clear both up/down
4385 * interrupt and adapter to re-evaluate the link state.
4387 val64
|= GPIO_INT_REG_LINK_DOWN
;
4388 val64
|= GPIO_INT_REG_LINK_UP
;
4389 writeq(val64
, &bar0
->gpio_int_reg
);
4390 val64
= readq(&bar0
->gpio_int_mask
);
4391 val64
&= ~(GPIO_INT_MASK_LINK_UP
|
4392 GPIO_INT_MASK_LINK_DOWN
);
4393 writeq(val64
, &bar0
->gpio_int_mask
);
4394 } else if (val64
& GPIO_INT_REG_LINK_UP
) {
4395 val64
= readq(&bar0
->adapter_status
);
4396 /* Enable Adapter */
4397 val64
= readq(&bar0
->adapter_control
);
4398 val64
|= ADAPTER_CNTL_EN
;
4399 writeq(val64
, &bar0
->adapter_control
);
4400 val64
|= ADAPTER_LED_ON
;
4401 writeq(val64
, &bar0
->adapter_control
);
4402 if (!sp
->device_enabled_once
)
4403 sp
->device_enabled_once
= 1;
4405 s2io_link(sp
, LINK_UP
);
4407 * unmask link down interrupt and mask link-up
4410 val64
= readq(&bar0
->gpio_int_mask
);
4411 val64
&= ~GPIO_INT_MASK_LINK_DOWN
;
4412 val64
|= GPIO_INT_MASK_LINK_UP
;
4413 writeq(val64
, &bar0
->gpio_int_mask
);
4415 } else if (val64
& GPIO_INT_REG_LINK_DOWN
) {
4416 val64
= readq(&bar0
->adapter_status
);
4417 s2io_link(sp
, LINK_DOWN
);
4418 /* Link is down so unmaks link up interrupt */
4419 val64
= readq(&bar0
->gpio_int_mask
);
4420 val64
&= ~GPIO_INT_MASK_LINK_UP
;
4421 val64
|= GPIO_INT_MASK_LINK_DOWN
;
4422 writeq(val64
, &bar0
->gpio_int_mask
);
4425 val64
= readq(&bar0
->adapter_control
);
4426 val64
= val64
& (~ADAPTER_LED_ON
);
4427 writeq(val64
, &bar0
->adapter_control
);
4430 val64
= readq(&bar0
->gpio_int_mask
);
4434 * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4435 * @value: alarm bits
4436 * @addr: address value
4437 * @cnt: counter variable
4438 * Description: Check for alarm and increment the counter
4440 * 1 - if alarm bit set
4441 * 0 - if alarm bit is not set
4443 static int do_s2io_chk_alarm_bit(u64 value
, void __iomem
*addr
,
4444 unsigned long long *cnt
)
4447 val64
= readq(addr
);
4448 if (val64
& value
) {
4449 writeq(val64
, addr
);
4458 * s2io_handle_errors - Xframe error indication handler
4459 * @nic: device private variable
4460 * Description: Handle alarms such as loss of link, single or
4461 * double ECC errors, critical and serious errors.
4465 static void s2io_handle_errors(void *dev_id
)
4467 struct net_device
*dev
= (struct net_device
*)dev_id
;
4468 struct s2io_nic
*sp
= netdev_priv(dev
);
4469 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4470 u64 temp64
= 0, val64
= 0;
4473 struct swStat
*sw_stat
= &sp
->mac_control
.stats_info
->sw_stat
;
4474 struct xpakStat
*stats
= &sp
->mac_control
.stats_info
->xpak_stat
;
4476 if (!is_s2io_card_up(sp
))
4479 if (pci_channel_offline(sp
->pdev
))
4482 memset(&sw_stat
->ring_full_cnt
, 0,
4483 sizeof(sw_stat
->ring_full_cnt
));
4485 /* Handling the XPAK counters update */
4486 if (stats
->xpak_timer_count
< 72000) {
4487 /* waiting for an hour */
4488 stats
->xpak_timer_count
++;
4490 s2io_updt_xpak_counter(dev
);
4491 /* reset the count to zero */
4492 stats
->xpak_timer_count
= 0;
4495 /* Handling link status change error Intr */
4496 if (s2io_link_fault_indication(sp
) == MAC_RMAC_ERR_TIMER
) {
4497 val64
= readq(&bar0
->mac_rmac_err_reg
);
4498 writeq(val64
, &bar0
->mac_rmac_err_reg
);
4499 if (val64
& RMAC_LINK_STATE_CHANGE_INT
)
4500 schedule_work(&sp
->set_link_task
);
4503 /* In case of a serious error, the device will be Reset. */
4504 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY
, &bar0
->serr_source
,
4505 &sw_stat
->serious_err_cnt
))
4508 /* Check for data parity error */
4509 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT
, &bar0
->gpio_int_reg
,
4510 &sw_stat
->parity_err_cnt
))
4513 /* Check for ring full counter */
4514 if (sp
->device_type
== XFRAME_II_DEVICE
) {
4515 val64
= readq(&bar0
->ring_bump_counter1
);
4516 for (i
= 0; i
< 4; i
++) {
4517 temp64
= (val64
& vBIT(0xFFFF, (i
*16), 16));
4518 temp64
>>= 64 - ((i
+1)*16);
4519 sw_stat
->ring_full_cnt
[i
] += temp64
;
4522 val64
= readq(&bar0
->ring_bump_counter2
);
4523 for (i
= 0; i
< 4; i
++) {
4524 temp64
= (val64
& vBIT(0xFFFF, (i
*16), 16));
4525 temp64
>>= 64 - ((i
+1)*16);
4526 sw_stat
->ring_full_cnt
[i
+4] += temp64
;
4530 val64
= readq(&bar0
->txdma_int_status
);
4531 /*check for pfc_err*/
4532 if (val64
& TXDMA_PFC_INT
) {
4533 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR
| PFC_SM_ERR_ALARM
|
4534 PFC_MISC_0_ERR
| PFC_MISC_1_ERR
|
4537 &sw_stat
->pfc_err_cnt
))
4539 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR
,
4541 &sw_stat
->pfc_err_cnt
);
4544 /*check for tda_err*/
4545 if (val64
& TXDMA_TDA_INT
) {
4546 if (do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR
|
4550 &sw_stat
->tda_err_cnt
))
4552 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR
| TDA_PCIX_ERR
,
4554 &sw_stat
->tda_err_cnt
);
4556 /*check for pcc_err*/
4557 if (val64
& TXDMA_PCC_INT
) {
4558 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM
| PCC_WR_ERR_ALARM
|
4559 PCC_N_SERR
| PCC_6_COF_OV_ERR
|
4560 PCC_7_COF_OV_ERR
| PCC_6_LSO_OV_ERR
|
4561 PCC_7_LSO_OV_ERR
| PCC_FB_ECC_DB_ERR
|
4564 &sw_stat
->pcc_err_cnt
))
4566 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR
| PCC_TXB_ECC_SG_ERR
,
4568 &sw_stat
->pcc_err_cnt
);
4571 /*check for tti_err*/
4572 if (val64
& TXDMA_TTI_INT
) {
4573 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM
,
4575 &sw_stat
->tti_err_cnt
))
4577 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR
| TTI_ECC_DB_ERR
,
4579 &sw_stat
->tti_err_cnt
);
4582 /*check for lso_err*/
4583 if (val64
& TXDMA_LSO_INT
) {
4584 if (do_s2io_chk_alarm_bit(LSO6_ABORT
| LSO7_ABORT
|
4585 LSO6_SM_ERR_ALARM
| LSO7_SM_ERR_ALARM
,
4587 &sw_stat
->lso_err_cnt
))
4589 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW
| LSO7_SEND_OFLOW
,
4591 &sw_stat
->lso_err_cnt
);
4594 /*check for tpa_err*/
4595 if (val64
& TXDMA_TPA_INT
) {
4596 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM
,
4598 &sw_stat
->tpa_err_cnt
))
4600 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP
,
4602 &sw_stat
->tpa_err_cnt
);
4605 /*check for sm_err*/
4606 if (val64
& TXDMA_SM_INT
) {
4607 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM
,
4609 &sw_stat
->sm_err_cnt
))
4613 val64
= readq(&bar0
->mac_int_status
);
4614 if (val64
& MAC_INT_STATUS_TMAC_INT
) {
4615 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN
| TMAC_TX_SM_ERR
,
4616 &bar0
->mac_tmac_err_reg
,
4617 &sw_stat
->mac_tmac_err_cnt
))
4619 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR
| TMAC_ECC_DB_ERR
|
4620 TMAC_DESC_ECC_SG_ERR
|
4621 TMAC_DESC_ECC_DB_ERR
,
4622 &bar0
->mac_tmac_err_reg
,
4623 &sw_stat
->mac_tmac_err_cnt
);
4626 val64
= readq(&bar0
->xgxs_int_status
);
4627 if (val64
& XGXS_INT_STATUS_TXGXS
) {
4628 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW
| TXGXS_TX_SM_ERR
,
4629 &bar0
->xgxs_txgxs_err_reg
,
4630 &sw_stat
->xgxs_txgxs_err_cnt
))
4632 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR
| TXGXS_ECC_DB_ERR
,
4633 &bar0
->xgxs_txgxs_err_reg
,
4634 &sw_stat
->xgxs_txgxs_err_cnt
);
4637 val64
= readq(&bar0
->rxdma_int_status
);
4638 if (val64
& RXDMA_INT_RC_INT_M
) {
4639 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR
|
4641 RC_PRCn_SM_ERR_ALARM
|
4642 RC_FTC_SM_ERR_ALARM
,
4644 &sw_stat
->rc_err_cnt
))
4646 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR
|
4648 RC_RDA_FAIL_WR_Rn
, &bar0
->rc_err_reg
,
4649 &sw_stat
->rc_err_cnt
);
4650 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn
|
4653 &bar0
->prc_pcix_err_reg
,
4654 &sw_stat
->prc_pcix_err_cnt
))
4656 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn
|
4659 &bar0
->prc_pcix_err_reg
,
4660 &sw_stat
->prc_pcix_err_cnt
);
4663 if (val64
& RXDMA_INT_RPA_INT_M
) {
4664 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM
| RPA_CREDIT_ERR
,
4666 &sw_stat
->rpa_err_cnt
))
4668 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR
| RPA_ECC_DB_ERR
,
4670 &sw_stat
->rpa_err_cnt
);
4673 if (val64
& RXDMA_INT_RDA_INT_M
) {
4674 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR
|
4675 RDA_FRM_ECC_DB_N_AERR
|
4678 RDA_RXD_ECC_DB_SERR
,
4680 &sw_stat
->rda_err_cnt
))
4682 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR
|
4683 RDA_FRM_ECC_SG_ERR
|
4687 &sw_stat
->rda_err_cnt
);
4690 if (val64
& RXDMA_INT_RTI_INT_M
) {
4691 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM
,
4693 &sw_stat
->rti_err_cnt
))
4695 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR
| RTI_ECC_DB_ERR
,
4697 &sw_stat
->rti_err_cnt
);
4700 val64
= readq(&bar0
->mac_int_status
);
4701 if (val64
& MAC_INT_STATUS_RMAC_INT
) {
4702 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN
| RMAC_RX_SM_ERR
,
4703 &bar0
->mac_rmac_err_reg
,
4704 &sw_stat
->mac_rmac_err_cnt
))
4706 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT
|
4707 RMAC_SINGLE_ECC_ERR
|
4708 RMAC_DOUBLE_ECC_ERR
,
4709 &bar0
->mac_rmac_err_reg
,
4710 &sw_stat
->mac_rmac_err_cnt
);
4713 val64
= readq(&bar0
->xgxs_int_status
);
4714 if (val64
& XGXS_INT_STATUS_RXGXS
) {
4715 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW
| RXGXS_RX_SM_ERR
,
4716 &bar0
->xgxs_rxgxs_err_reg
,
4717 &sw_stat
->xgxs_rxgxs_err_cnt
))
4721 val64
= readq(&bar0
->mc_int_status
);
4722 if (val64
& MC_INT_STATUS_MC_INT
) {
4723 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR
,
4725 &sw_stat
->mc_err_cnt
))
4728 /* Handling Ecc errors */
4729 if (val64
& (MC_ERR_REG_ECC_ALL_SNG
| MC_ERR_REG_ECC_ALL_DBL
)) {
4730 writeq(val64
, &bar0
->mc_err_reg
);
4731 if (val64
& MC_ERR_REG_ECC_ALL_DBL
) {
4732 sw_stat
->double_ecc_errs
++;
4733 if (sp
->device_type
!= XFRAME_II_DEVICE
) {
4735 * Reset XframeI only if critical error
4738 (MC_ERR_REG_MIRI_ECC_DB_ERR_0
|
4739 MC_ERR_REG_MIRI_ECC_DB_ERR_1
))
4743 sw_stat
->single_ecc_errs
++;
4749 s2io_stop_all_tx_queue(sp
);
4750 schedule_work(&sp
->rst_timer_task
);
4751 sw_stat
->soft_reset_cnt
++;
4755 * s2io_isr - ISR handler of the device .
4756 * @irq: the irq of the device.
4757 * @dev_id: a void pointer to the dev structure of the NIC.
4758 * Description: This function is the ISR handler of the device. It
4759 * identifies the reason for the interrupt and calls the relevant
4760 * service routines. As a contongency measure, this ISR allocates the
4761 * recv buffers, if their numbers are below the panic value which is
4762 * presently set to 25% of the original number of rcv buffers allocated.
4764 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
4765 * IRQ_NONE: will be returned if interrupt is not from our device
4767 static irqreturn_t
s2io_isr(int irq
, void *dev_id
)
4769 struct net_device
*dev
= (struct net_device
*)dev_id
;
4770 struct s2io_nic
*sp
= netdev_priv(dev
);
4771 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4774 struct mac_info
*mac_control
;
4775 struct config_param
*config
;
4777 /* Pretend we handled any irq's from a disconnected card */
4778 if (pci_channel_offline(sp
->pdev
))
4781 if (!is_s2io_card_up(sp
))
4784 config
= &sp
->config
;
4785 mac_control
= &sp
->mac_control
;
4788 * Identify the cause for interrupt and call the appropriate
4789 * interrupt handler. Causes for the interrupt could be;
4794 reason
= readq(&bar0
->general_int_status
);
4796 if (unlikely(reason
== S2IO_MINUS_ONE
))
4797 return IRQ_HANDLED
; /* Nothing much can be done. Get out */
4800 (GEN_INTR_RXTRAFFIC
| GEN_INTR_TXTRAFFIC
| GEN_INTR_TXPIC
)) {
4801 writeq(S2IO_MINUS_ONE
, &bar0
->general_int_mask
);
4804 if (reason
& GEN_INTR_RXTRAFFIC
) {
4805 napi_schedule(&sp
->napi
);
4806 writeq(S2IO_MINUS_ONE
, &bar0
->rx_traffic_mask
);
4807 writeq(S2IO_MINUS_ONE
, &bar0
->rx_traffic_int
);
4808 readl(&bar0
->rx_traffic_int
);
4812 * rx_traffic_int reg is an R1 register, writing all 1's
4813 * will ensure that the actual interrupt causing bit
4814 * get's cleared and hence a read can be avoided.
4816 if (reason
& GEN_INTR_RXTRAFFIC
)
4817 writeq(S2IO_MINUS_ONE
, &bar0
->rx_traffic_int
);
4819 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
4820 struct ring_info
*ring
= &mac_control
->rings
[i
];
4822 rx_intr_handler(ring
, 0);
4827 * tx_traffic_int reg is an R1 register, writing all 1's
4828 * will ensure that the actual interrupt causing bit get's
4829 * cleared and hence a read can be avoided.
4831 if (reason
& GEN_INTR_TXTRAFFIC
)
4832 writeq(S2IO_MINUS_ONE
, &bar0
->tx_traffic_int
);
4834 for (i
= 0; i
< config
->tx_fifo_num
; i
++)
4835 tx_intr_handler(&mac_control
->fifos
[i
]);
4837 if (reason
& GEN_INTR_TXPIC
)
4838 s2io_txpic_intr_handle(sp
);
4841 * Reallocate the buffers from the interrupt handler itself.
4843 if (!config
->napi
) {
4844 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
4845 struct ring_info
*ring
= &mac_control
->rings
[i
];
4847 s2io_chk_rx_buffers(sp
, ring
);
4850 writeq(sp
->general_int_mask
, &bar0
->general_int_mask
);
4851 readl(&bar0
->general_int_status
);
4855 } else if (!reason
) {
4856 /* The interrupt was not raised by us */
4866 static void s2io_updt_stats(struct s2io_nic
*sp
)
4868 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4872 if (is_s2io_card_up(sp
)) {
4873 /* Apprx 30us on a 133 MHz bus */
4874 val64
= SET_UPDT_CLICKS(10) |
4875 STAT_CFG_ONE_SHOT_EN
| STAT_CFG_STAT_EN
;
4876 writeq(val64
, &bar0
->stat_cfg
);
4879 val64
= readq(&bar0
->stat_cfg
);
4880 if (!(val64
& s2BIT(0)))
4884 break; /* Updt failed */
4890 * s2io_get_stats - Updates the device statistics structure.
4891 * @dev : pointer to the device structure.
4893 * This function updates the device statistics structure in the s2io_nic
4894 * structure and returns a pointer to the same.
4896 * pointer to the updated net_device_stats structure.
4898 static struct net_device_stats
*s2io_get_stats(struct net_device
*dev
)
4900 struct s2io_nic
*sp
= netdev_priv(dev
);
4901 struct mac_info
*mac_control
= &sp
->mac_control
;
4902 struct stat_block
*stats
= mac_control
->stats_info
;
4905 /* Configure Stats for immediate updt */
4906 s2io_updt_stats(sp
);
4908 /* A device reset will cause the on-adapter statistics to be zero'ed.
4909 * This can be done while running by changing the MTU. To prevent the
4910 * system from having the stats zero'ed, the driver keeps a copy of the
4911 * last update to the system (which is also zero'ed on reset). This
4912 * enables the driver to accurately know the delta between the last
4913 * update and the current update.
4915 delta
= ((u64
) le32_to_cpu(stats
->rmac_vld_frms_oflow
) << 32 |
4916 le32_to_cpu(stats
->rmac_vld_frms
)) - sp
->stats
.rx_packets
;
4917 sp
->stats
.rx_packets
+= delta
;
4918 dev
->stats
.rx_packets
+= delta
;
4920 delta
= ((u64
) le32_to_cpu(stats
->tmac_frms_oflow
) << 32 |
4921 le32_to_cpu(stats
->tmac_frms
)) - sp
->stats
.tx_packets
;
4922 sp
->stats
.tx_packets
+= delta
;
4923 dev
->stats
.tx_packets
+= delta
;
4925 delta
= ((u64
) le32_to_cpu(stats
->rmac_data_octets_oflow
) << 32 |
4926 le32_to_cpu(stats
->rmac_data_octets
)) - sp
->stats
.rx_bytes
;
4927 sp
->stats
.rx_bytes
+= delta
;
4928 dev
->stats
.rx_bytes
+= delta
;
4930 delta
= ((u64
) le32_to_cpu(stats
->tmac_data_octets_oflow
) << 32 |
4931 le32_to_cpu(stats
->tmac_data_octets
)) - sp
->stats
.tx_bytes
;
4932 sp
->stats
.tx_bytes
+= delta
;
4933 dev
->stats
.tx_bytes
+= delta
;
4935 delta
= le64_to_cpu(stats
->rmac_drop_frms
) - sp
->stats
.rx_errors
;
4936 sp
->stats
.rx_errors
+= delta
;
4937 dev
->stats
.rx_errors
+= delta
;
4939 delta
= ((u64
) le32_to_cpu(stats
->tmac_any_err_frms_oflow
) << 32 |
4940 le32_to_cpu(stats
->tmac_any_err_frms
)) - sp
->stats
.tx_errors
;
4941 sp
->stats
.tx_errors
+= delta
;
4942 dev
->stats
.tx_errors
+= delta
;
4944 delta
= le64_to_cpu(stats
->rmac_drop_frms
) - sp
->stats
.rx_dropped
;
4945 sp
->stats
.rx_dropped
+= delta
;
4946 dev
->stats
.rx_dropped
+= delta
;
4948 delta
= le64_to_cpu(stats
->tmac_drop_frms
) - sp
->stats
.tx_dropped
;
4949 sp
->stats
.tx_dropped
+= delta
;
4950 dev
->stats
.tx_dropped
+= delta
;
4952 /* The adapter MAC interprets pause frames as multicast packets, but
4953 * does not pass them up. This erroneously increases the multicast
4954 * packet count and needs to be deducted when the multicast frame count
4957 delta
= (u64
) le32_to_cpu(stats
->rmac_vld_mcst_frms_oflow
) << 32 |
4958 le32_to_cpu(stats
->rmac_vld_mcst_frms
);
4959 delta
-= le64_to_cpu(stats
->rmac_pause_ctrl_frms
);
4960 delta
-= sp
->stats
.multicast
;
4961 sp
->stats
.multicast
+= delta
;
4962 dev
->stats
.multicast
+= delta
;
4964 delta
= ((u64
) le32_to_cpu(stats
->rmac_usized_frms_oflow
) << 32 |
4965 le32_to_cpu(stats
->rmac_usized_frms
)) +
4966 le64_to_cpu(stats
->rmac_long_frms
) - sp
->stats
.rx_length_errors
;
4967 sp
->stats
.rx_length_errors
+= delta
;
4968 dev
->stats
.rx_length_errors
+= delta
;
4970 delta
= le64_to_cpu(stats
->rmac_fcs_err_frms
) - sp
->stats
.rx_crc_errors
;
4971 sp
->stats
.rx_crc_errors
+= delta
;
4972 dev
->stats
.rx_crc_errors
+= delta
;
4978 * s2io_set_multicast - entry point for multicast address enable/disable.
4979 * @dev : pointer to the device structure
4981 * This function is a driver entry point which gets called by the kernel
4982 * whenever multicast addresses must be enabled/disabled. This also gets
4983 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4984 * determine, if multicast address must be enabled or if promiscuous mode
4985 * is to be disabled etc.
4990 static void s2io_set_multicast(struct net_device
*dev
)
4993 struct netdev_hw_addr
*ha
;
4994 struct s2io_nic
*sp
= netdev_priv(dev
);
4995 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4996 u64 val64
= 0, multi_mac
= 0x010203040506ULL
, mask
=
4998 u64 dis_addr
= S2IO_DISABLE_MAC_ENTRY
, mac_addr
= 0;
5000 struct config_param
*config
= &sp
->config
;
5002 if ((dev
->flags
& IFF_ALLMULTI
) && (!sp
->m_cast_flg
)) {
5003 /* Enable all Multicast addresses */
5004 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac
),
5005 &bar0
->rmac_addr_data0_mem
);
5006 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask
),
5007 &bar0
->rmac_addr_data1_mem
);
5008 val64
= RMAC_ADDR_CMD_MEM_WE
|
5009 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
5010 RMAC_ADDR_CMD_MEM_OFFSET(config
->max_mc_addr
- 1);
5011 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
5012 /* Wait till command completes */
5013 wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
5014 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
,
5018 sp
->all_multi_pos
= config
->max_mc_addr
- 1;
5019 } else if ((dev
->flags
& IFF_ALLMULTI
) && (sp
->m_cast_flg
)) {
5020 /* Disable all Multicast addresses */
5021 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr
),
5022 &bar0
->rmac_addr_data0_mem
);
5023 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
5024 &bar0
->rmac_addr_data1_mem
);
5025 val64
= RMAC_ADDR_CMD_MEM_WE
|
5026 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
5027 RMAC_ADDR_CMD_MEM_OFFSET(sp
->all_multi_pos
);
5028 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
5029 /* Wait till command completes */
5030 wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
5031 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
,
5035 sp
->all_multi_pos
= 0;
5038 if ((dev
->flags
& IFF_PROMISC
) && (!sp
->promisc_flg
)) {
5039 /* Put the NIC into promiscuous mode */
5040 add
= &bar0
->mac_cfg
;
5041 val64
= readq(&bar0
->mac_cfg
);
5042 val64
|= MAC_CFG_RMAC_PROM_ENABLE
;
5044 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
5045 writel((u32
)val64
, add
);
5046 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
5047 writel((u32
) (val64
>> 32), (add
+ 4));
5049 if (vlan_tag_strip
!= 1) {
5050 val64
= readq(&bar0
->rx_pa_cfg
);
5051 val64
&= ~RX_PA_CFG_STRIP_VLAN_TAG
;
5052 writeq(val64
, &bar0
->rx_pa_cfg
);
5053 sp
->vlan_strip_flag
= 0;
5056 val64
= readq(&bar0
->mac_cfg
);
5057 sp
->promisc_flg
= 1;
5058 DBG_PRINT(INFO_DBG
, "%s: entered promiscuous mode\n",
5060 } else if (!(dev
->flags
& IFF_PROMISC
) && (sp
->promisc_flg
)) {
5061 /* Remove the NIC from promiscuous mode */
5062 add
= &bar0
->mac_cfg
;
5063 val64
= readq(&bar0
->mac_cfg
);
5064 val64
&= ~MAC_CFG_RMAC_PROM_ENABLE
;
5066 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
5067 writel((u32
)val64
, add
);
5068 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
5069 writel((u32
) (val64
>> 32), (add
+ 4));
5071 if (vlan_tag_strip
!= 0) {
5072 val64
= readq(&bar0
->rx_pa_cfg
);
5073 val64
|= RX_PA_CFG_STRIP_VLAN_TAG
;
5074 writeq(val64
, &bar0
->rx_pa_cfg
);
5075 sp
->vlan_strip_flag
= 1;
5078 val64
= readq(&bar0
->mac_cfg
);
5079 sp
->promisc_flg
= 0;
5080 DBG_PRINT(INFO_DBG
, "%s: left promiscuous mode\n", dev
->name
);
5083 /* Update individual M_CAST address list */
5084 if ((!sp
->m_cast_flg
) && netdev_mc_count(dev
)) {
5085 if (netdev_mc_count(dev
) >
5086 (config
->max_mc_addr
- config
->max_mac_addr
)) {
5088 "%s: No more Rx filters can be added - "
5089 "please enable ALL_MULTI instead\n",
5094 prev_cnt
= sp
->mc_addr_count
;
5095 sp
->mc_addr_count
= netdev_mc_count(dev
);
5097 /* Clear out the previous list of Mc in the H/W. */
5098 for (i
= 0; i
< prev_cnt
; i
++) {
5099 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr
),
5100 &bar0
->rmac_addr_data0_mem
);
5101 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5102 &bar0
->rmac_addr_data1_mem
);
5103 val64
= RMAC_ADDR_CMD_MEM_WE
|
5104 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
5105 RMAC_ADDR_CMD_MEM_OFFSET
5106 (config
->mc_start_offset
+ i
);
5107 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
5109 /* Wait for command completes */
5110 if (wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
5111 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
,
5114 "%s: Adding Multicasts failed\n",
5120 /* Create the new Rx filter list and update the same in H/W. */
5122 netdev_for_each_mc_addr(ha
, dev
) {
5124 for (j
= 0; j
< ETH_ALEN
; j
++) {
5125 mac_addr
|= ha
->addr
[j
];
5129 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr
),
5130 &bar0
->rmac_addr_data0_mem
);
5131 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5132 &bar0
->rmac_addr_data1_mem
);
5133 val64
= RMAC_ADDR_CMD_MEM_WE
|
5134 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
5135 RMAC_ADDR_CMD_MEM_OFFSET
5136 (i
+ config
->mc_start_offset
);
5137 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
5139 /* Wait for command completes */
5140 if (wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
5141 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
,
5144 "%s: Adding Multicasts failed\n",
5153 /* read from CAM unicast & multicast addresses and store it in
5154 * def_mac_addr structure
5156 static void do_s2io_store_unicast_mc(struct s2io_nic
*sp
)
5160 struct config_param
*config
= &sp
->config
;
5162 /* store unicast & multicast mac addresses */
5163 for (offset
= 0; offset
< config
->max_mc_addr
; offset
++) {
5164 mac_addr
= do_s2io_read_unicast_mc(sp
, offset
);
5165 /* if read fails disable the entry */
5166 if (mac_addr
== FAILURE
)
5167 mac_addr
= S2IO_DISABLE_MAC_ENTRY
;
5168 do_s2io_copy_mac_addr(sp
, offset
, mac_addr
);
5172 /* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5173 static void do_s2io_restore_unicast_mc(struct s2io_nic
*sp
)
5176 struct config_param
*config
= &sp
->config
;
5177 /* restore unicast mac address */
5178 for (offset
= 0; offset
< config
->max_mac_addr
; offset
++)
5179 do_s2io_prog_unicast(sp
->dev
,
5180 sp
->def_mac_addr
[offset
].mac_addr
);
5182 /* restore multicast mac address */
5183 for (offset
= config
->mc_start_offset
;
5184 offset
< config
->max_mc_addr
; offset
++)
5185 do_s2io_add_mc(sp
, sp
->def_mac_addr
[offset
].mac_addr
);
5188 /* add a multicast MAC address to CAM */
5189 static int do_s2io_add_mc(struct s2io_nic
*sp
, u8
*addr
)
5193 struct config_param
*config
= &sp
->config
;
5195 for (i
= 0; i
< ETH_ALEN
; i
++) {
5197 mac_addr
|= addr
[i
];
5199 if ((0ULL == mac_addr
) || (mac_addr
== S2IO_DISABLE_MAC_ENTRY
))
5202 /* check if the multicast mac already preset in CAM */
5203 for (i
= config
->mc_start_offset
; i
< config
->max_mc_addr
; i
++) {
5205 tmp64
= do_s2io_read_unicast_mc(sp
, i
);
5206 if (tmp64
== S2IO_DISABLE_MAC_ENTRY
) /* CAM entry is empty */
5209 if (tmp64
== mac_addr
)
5212 if (i
== config
->max_mc_addr
) {
5214 "CAM full no space left for multicast MAC\n");
5217 /* Update the internal structure with this new mac address */
5218 do_s2io_copy_mac_addr(sp
, i
, mac_addr
);
5220 return do_s2io_add_mac(sp
, mac_addr
, i
);
5223 /* add MAC address to CAM */
5224 static int do_s2io_add_mac(struct s2io_nic
*sp
, u64 addr
, int off
)
5227 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5229 writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr
),
5230 &bar0
->rmac_addr_data0_mem
);
5232 val64
= RMAC_ADDR_CMD_MEM_WE
| RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
5233 RMAC_ADDR_CMD_MEM_OFFSET(off
);
5234 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
5236 /* Wait till command completes */
5237 if (wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
5238 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
,
5240 DBG_PRINT(INFO_DBG
, "do_s2io_add_mac failed\n");
5245 /* deletes a specified unicast/multicast mac entry from CAM */
5246 static int do_s2io_delete_unicast_mc(struct s2io_nic
*sp
, u64 addr
)
5249 u64 dis_addr
= S2IO_DISABLE_MAC_ENTRY
, tmp64
;
5250 struct config_param
*config
= &sp
->config
;
5253 offset
< config
->max_mc_addr
; offset
++) {
5254 tmp64
= do_s2io_read_unicast_mc(sp
, offset
);
5255 if (tmp64
== addr
) {
5256 /* disable the entry by writing 0xffffffffffffULL */
5257 if (do_s2io_add_mac(sp
, dis_addr
, offset
) == FAILURE
)
5259 /* store the new mac list from CAM */
5260 do_s2io_store_unicast_mc(sp
);
5264 DBG_PRINT(ERR_DBG
, "MAC address 0x%llx not found in CAM\n",
5265 (unsigned long long)addr
);
5269 /* read mac entries from CAM */
5270 static u64
do_s2io_read_unicast_mc(struct s2io_nic
*sp
, int offset
)
5272 u64 tmp64
= 0xffffffffffff0000ULL
, val64
;
5273 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5276 val64
= RMAC_ADDR_CMD_MEM_RD
| RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
5277 RMAC_ADDR_CMD_MEM_OFFSET(offset
);
5278 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
5280 /* Wait till command completes */
5281 if (wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
5282 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
,
5284 DBG_PRINT(INFO_DBG
, "do_s2io_read_unicast_mc failed\n");
5287 tmp64
= readq(&bar0
->rmac_addr_data0_mem
);
5293 * s2io_set_mac_addr driver entry point
5296 static int s2io_set_mac_addr(struct net_device
*dev
, void *p
)
5298 struct sockaddr
*addr
= p
;
5300 if (!is_valid_ether_addr(addr
->sa_data
))
5303 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
5305 /* store the MAC address in CAM */
5306 return do_s2io_prog_unicast(dev
, dev
->dev_addr
);
5309 * do_s2io_prog_unicast - Programs the Xframe mac address
5310 * @dev : pointer to the device structure.
5311 * @addr: a uchar pointer to the new mac address which is to be set.
5312 * Description : This procedure will program the Xframe to receive
5313 * frames with new Mac Address
5314 * Return value: SUCCESS on success and an appropriate (-)ve integer
5315 * as defined in errno.h file on failure.
5318 static int do_s2io_prog_unicast(struct net_device
*dev
, u8
*addr
)
5320 struct s2io_nic
*sp
= netdev_priv(dev
);
5321 register u64 mac_addr
= 0, perm_addr
= 0;
5324 struct config_param
*config
= &sp
->config
;
5327 * Set the new MAC address as the new unicast filter and reflect this
5328 * change on the device address registered with the OS. It will be
5331 for (i
= 0; i
< ETH_ALEN
; i
++) {
5333 mac_addr
|= addr
[i
];
5335 perm_addr
|= sp
->def_mac_addr
[0].mac_addr
[i
];
5338 /* check if the dev_addr is different than perm_addr */
5339 if (mac_addr
== perm_addr
)
5342 /* check if the mac already preset in CAM */
5343 for (i
= 1; i
< config
->max_mac_addr
; i
++) {
5344 tmp64
= do_s2io_read_unicast_mc(sp
, i
);
5345 if (tmp64
== S2IO_DISABLE_MAC_ENTRY
) /* CAM entry is empty */
5348 if (tmp64
== mac_addr
) {
5350 "MAC addr:0x%llx already present in CAM\n",
5351 (unsigned long long)mac_addr
);
5355 if (i
== config
->max_mac_addr
) {
5356 DBG_PRINT(ERR_DBG
, "CAM full no space left for Unicast MAC\n");
5359 /* Update the internal structure with this new mac address */
5360 do_s2io_copy_mac_addr(sp
, i
, mac_addr
);
5362 return do_s2io_add_mac(sp
, mac_addr
, i
);
5366 * s2io_ethtool_sset - Sets different link parameters.
5367 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5368 * @info: pointer to the structure with parameters given by ethtool to set
5371 * The function sets different link parameters provided by the user onto
5377 static int s2io_ethtool_sset(struct net_device
*dev
,
5378 struct ethtool_cmd
*info
)
5380 struct s2io_nic
*sp
= netdev_priv(dev
);
5381 if ((info
->autoneg
== AUTONEG_ENABLE
) ||
5382 (ethtool_cmd_speed(info
) != SPEED_10000
) ||
5383 (info
->duplex
!= DUPLEX_FULL
))
5386 s2io_close(sp
->dev
);
5394 * s2io_ethtol_gset - Return link specific information.
5395 * @sp : private member of the device structure, pointer to the
5396 * s2io_nic structure.
5397 * @info : pointer to the structure with parameters given by ethtool
5398 * to return link information.
5400 * Returns link specific information like speed, duplex etc.. to ethtool.
5402 * return 0 on success.
5405 static int s2io_ethtool_gset(struct net_device
*dev
, struct ethtool_cmd
*info
)
5407 struct s2io_nic
*sp
= netdev_priv(dev
);
5408 info
->supported
= (SUPPORTED_10000baseT_Full
| SUPPORTED_FIBRE
);
5409 info
->advertising
= (SUPPORTED_10000baseT_Full
| SUPPORTED_FIBRE
);
5410 info
->port
= PORT_FIBRE
;
5412 /* info->transceiver */
5413 info
->transceiver
= XCVR_EXTERNAL
;
5415 if (netif_carrier_ok(sp
->dev
)) {
5416 ethtool_cmd_speed_set(info
, SPEED_10000
);
5417 info
->duplex
= DUPLEX_FULL
;
5419 ethtool_cmd_speed_set(info
, -1);
5423 info
->autoneg
= AUTONEG_DISABLE
;
5428 * s2io_ethtool_gdrvinfo - Returns driver specific information.
5429 * @sp : private member of the device structure, which is a pointer to the
5430 * s2io_nic structure.
5431 * @info : pointer to the structure with parameters given by ethtool to
5432 * return driver information.
5434 * Returns driver specefic information like name, version etc.. to ethtool.
5439 static void s2io_ethtool_gdrvinfo(struct net_device
*dev
,
5440 struct ethtool_drvinfo
*info
)
5442 struct s2io_nic
*sp
= netdev_priv(dev
);
5444 strncpy(info
->driver
, s2io_driver_name
, sizeof(info
->driver
));
5445 strncpy(info
->version
, s2io_driver_version
, sizeof(info
->version
));
5446 strncpy(info
->fw_version
, "", sizeof(info
->fw_version
));
5447 strncpy(info
->bus_info
, pci_name(sp
->pdev
), sizeof(info
->bus_info
));
5448 info
->regdump_len
= XENA_REG_SPACE
;
5449 info
->eedump_len
= XENA_EEPROM_SPACE
;
5453 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
5454 * @sp: private member of the device structure, which is a pointer to the
5455 * s2io_nic structure.
5456 * @regs : pointer to the structure with parameters given by ethtool for
5457 * dumping the registers.
5458 * @reg_space: The input argumnet into which all the registers are dumped.
5460 * Dumps the entire register space of xFrame NIC into the user given
5466 static void s2io_ethtool_gregs(struct net_device
*dev
,
5467 struct ethtool_regs
*regs
, void *space
)
5471 u8
*reg_space
= (u8
*)space
;
5472 struct s2io_nic
*sp
= netdev_priv(dev
);
5474 regs
->len
= XENA_REG_SPACE
;
5475 regs
->version
= sp
->pdev
->subsystem_device
;
5477 for (i
= 0; i
< regs
->len
; i
+= 8) {
5478 reg
= readq(sp
->bar0
+ i
);
5479 memcpy((reg_space
+ i
), ®
, 8);
5484 * s2io_set_led - control NIC led
5486 static void s2io_set_led(struct s2io_nic
*sp
, bool on
)
5488 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5489 u16 subid
= sp
->pdev
->subsystem_device
;
5492 if ((sp
->device_type
== XFRAME_II_DEVICE
) ||
5493 ((subid
& 0xFF) >= 0x07)) {
5494 val64
= readq(&bar0
->gpio_control
);
5496 val64
|= GPIO_CTRL_GPIO_0
;
5498 val64
&= ~GPIO_CTRL_GPIO_0
;
5500 writeq(val64
, &bar0
->gpio_control
);
5502 val64
= readq(&bar0
->adapter_control
);
5504 val64
|= ADAPTER_LED_ON
;
5506 val64
&= ~ADAPTER_LED_ON
;
5508 writeq(val64
, &bar0
->adapter_control
);
5514 * s2io_ethtool_set_led - To physically identify the nic on the system.
5515 * @dev : network device
5516 * @state: led setting
5518 * Description: Used to physically identify the NIC on the system.
5519 * The Link LED will blink for a time specified by the user for
5521 * NOTE: The Link has to be Up to be able to blink the LED. Hence
5522 * identification is possible only if it's link is up.
5525 static int s2io_ethtool_set_led(struct net_device
*dev
,
5526 enum ethtool_phys_id_state state
)
5528 struct s2io_nic
*sp
= netdev_priv(dev
);
5529 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5530 u16 subid
= sp
->pdev
->subsystem_device
;
5532 if ((sp
->device_type
== XFRAME_I_DEVICE
) && ((subid
& 0xFF) < 0x07)) {
5533 u64 val64
= readq(&bar0
->adapter_control
);
5534 if (!(val64
& ADAPTER_CNTL_EN
)) {
5535 pr_err("Adapter Link down, cannot blink LED\n");
5541 case ETHTOOL_ID_ACTIVE
:
5542 sp
->adapt_ctrl_org
= readq(&bar0
->gpio_control
);
5543 return 1; /* cycle on/off once per second */
5546 s2io_set_led(sp
, true);
5549 case ETHTOOL_ID_OFF
:
5550 s2io_set_led(sp
, false);
5553 case ETHTOOL_ID_INACTIVE
:
5554 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp
->device_type
, subid
))
5555 writeq(sp
->adapt_ctrl_org
, &bar0
->gpio_control
);
5561 static void s2io_ethtool_gringparam(struct net_device
*dev
,
5562 struct ethtool_ringparam
*ering
)
5564 struct s2io_nic
*sp
= netdev_priv(dev
);
5565 int i
, tx_desc_count
= 0, rx_desc_count
= 0;
5567 if (sp
->rxd_mode
== RXD_MODE_1
) {
5568 ering
->rx_max_pending
= MAX_RX_DESC_1
;
5569 ering
->rx_jumbo_max_pending
= MAX_RX_DESC_1
;
5571 ering
->rx_max_pending
= MAX_RX_DESC_2
;
5572 ering
->rx_jumbo_max_pending
= MAX_RX_DESC_2
;
5575 ering
->rx_mini_max_pending
= 0;
5576 ering
->tx_max_pending
= MAX_TX_DESC
;
5578 for (i
= 0; i
< sp
->config
.rx_ring_num
; i
++)
5579 rx_desc_count
+= sp
->config
.rx_cfg
[i
].num_rxd
;
5580 ering
->rx_pending
= rx_desc_count
;
5581 ering
->rx_jumbo_pending
= rx_desc_count
;
5582 ering
->rx_mini_pending
= 0;
5584 for (i
= 0; i
< sp
->config
.tx_fifo_num
; i
++)
5585 tx_desc_count
+= sp
->config
.tx_cfg
[i
].fifo_len
;
5586 ering
->tx_pending
= tx_desc_count
;
5587 DBG_PRINT(INFO_DBG
, "max txds: %d\n", sp
->config
.max_txds
);
5591 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
5592 * @sp : private member of the device structure, which is a pointer to the
5593 * s2io_nic structure.
5594 * @ep : pointer to the structure with pause parameters given by ethtool.
5596 * Returns the Pause frame generation and reception capability of the NIC.
5600 static void s2io_ethtool_getpause_data(struct net_device
*dev
,
5601 struct ethtool_pauseparam
*ep
)
5604 struct s2io_nic
*sp
= netdev_priv(dev
);
5605 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5607 val64
= readq(&bar0
->rmac_pause_cfg
);
5608 if (val64
& RMAC_PAUSE_GEN_ENABLE
)
5609 ep
->tx_pause
= true;
5610 if (val64
& RMAC_PAUSE_RX_ENABLE
)
5611 ep
->rx_pause
= true;
5612 ep
->autoneg
= false;
5616 * s2io_ethtool_setpause_data - set/reset pause frame generation.
5617 * @sp : private member of the device structure, which is a pointer to the
5618 * s2io_nic structure.
5619 * @ep : pointer to the structure with pause parameters given by ethtool.
5621 * It can be used to set or reset Pause frame generation or reception
5622 * support of the NIC.
5624 * int, returns 0 on Success
5627 static int s2io_ethtool_setpause_data(struct net_device
*dev
,
5628 struct ethtool_pauseparam
*ep
)
5631 struct s2io_nic
*sp
= netdev_priv(dev
);
5632 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5634 val64
= readq(&bar0
->rmac_pause_cfg
);
5636 val64
|= RMAC_PAUSE_GEN_ENABLE
;
5638 val64
&= ~RMAC_PAUSE_GEN_ENABLE
;
5640 val64
|= RMAC_PAUSE_RX_ENABLE
;
5642 val64
&= ~RMAC_PAUSE_RX_ENABLE
;
5643 writeq(val64
, &bar0
->rmac_pause_cfg
);
5648 * read_eeprom - reads 4 bytes of data from user given offset.
5649 * @sp : private member of the device structure, which is a pointer to the
5650 * s2io_nic structure.
5651 * @off : offset at which the data must be written
5652 * @data : Its an output parameter where the data read at the given
5655 * Will read 4 bytes of data from the user given offset and return the
5657 * NOTE: Will allow to read only part of the EEPROM visible through the
5660 * -1 on failure and 0 on success.
5663 #define S2IO_DEV_ID 5
5664 static int read_eeprom(struct s2io_nic
*sp
, int off
, u64
*data
)
5669 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5671 if (sp
->device_type
== XFRAME_I_DEVICE
) {
5672 val64
= I2C_CONTROL_DEV_ID(S2IO_DEV_ID
) |
5673 I2C_CONTROL_ADDR(off
) |
5674 I2C_CONTROL_BYTE_CNT(0x3) |
5676 I2C_CONTROL_CNTL_START
;
5677 SPECIAL_REG_WRITE(val64
, &bar0
->i2c_control
, LF
);
5679 while (exit_cnt
< 5) {
5680 val64
= readq(&bar0
->i2c_control
);
5681 if (I2C_CONTROL_CNTL_END(val64
)) {
5682 *data
= I2C_CONTROL_GET_DATA(val64
);
5691 if (sp
->device_type
== XFRAME_II_DEVICE
) {
5692 val64
= SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1
|
5693 SPI_CONTROL_BYTECNT(0x3) |
5694 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off
);
5695 SPECIAL_REG_WRITE(val64
, &bar0
->spi_control
, LF
);
5696 val64
|= SPI_CONTROL_REQ
;
5697 SPECIAL_REG_WRITE(val64
, &bar0
->spi_control
, LF
);
5698 while (exit_cnt
< 5) {
5699 val64
= readq(&bar0
->spi_control
);
5700 if (val64
& SPI_CONTROL_NACK
) {
5703 } else if (val64
& SPI_CONTROL_DONE
) {
5704 *data
= readq(&bar0
->spi_data
);
5717 * write_eeprom - actually writes the relevant part of the data value.
5718 * @sp : private member of the device structure, which is a pointer to the
5719 * s2io_nic structure.
5720 * @off : offset at which the data must be written
5721 * @data : The data that is to be written
5722 * @cnt : Number of bytes of the data that are actually to be written into
5723 * the Eeprom. (max of 3)
5725 * Actually writes the relevant part of the data value into the Eeprom
5726 * through the I2C bus.
5728 * 0 on success, -1 on failure.
5731 static int write_eeprom(struct s2io_nic
*sp
, int off
, u64 data
, int cnt
)
5733 int exit_cnt
= 0, ret
= -1;
5735 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5737 if (sp
->device_type
== XFRAME_I_DEVICE
) {
5738 val64
= I2C_CONTROL_DEV_ID(S2IO_DEV_ID
) |
5739 I2C_CONTROL_ADDR(off
) |
5740 I2C_CONTROL_BYTE_CNT(cnt
) |
5741 I2C_CONTROL_SET_DATA((u32
)data
) |
5742 I2C_CONTROL_CNTL_START
;
5743 SPECIAL_REG_WRITE(val64
, &bar0
->i2c_control
, LF
);
5745 while (exit_cnt
< 5) {
5746 val64
= readq(&bar0
->i2c_control
);
5747 if (I2C_CONTROL_CNTL_END(val64
)) {
5748 if (!(val64
& I2C_CONTROL_NACK
))
5757 if (sp
->device_type
== XFRAME_II_DEVICE
) {
5758 int write_cnt
= (cnt
== 8) ? 0 : cnt
;
5759 writeq(SPI_DATA_WRITE(data
, (cnt
<< 3)), &bar0
->spi_data
);
5761 val64
= SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1
|
5762 SPI_CONTROL_BYTECNT(write_cnt
) |
5763 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off
);
5764 SPECIAL_REG_WRITE(val64
, &bar0
->spi_control
, LF
);
5765 val64
|= SPI_CONTROL_REQ
;
5766 SPECIAL_REG_WRITE(val64
, &bar0
->spi_control
, LF
);
5767 while (exit_cnt
< 5) {
5768 val64
= readq(&bar0
->spi_control
);
5769 if (val64
& SPI_CONTROL_NACK
) {
5772 } else if (val64
& SPI_CONTROL_DONE
) {
5782 static void s2io_vpd_read(struct s2io_nic
*nic
)
5786 int i
= 0, cnt
, len
, fail
= 0;
5787 int vpd_addr
= 0x80;
5788 struct swStat
*swstats
= &nic
->mac_control
.stats_info
->sw_stat
;
5790 if (nic
->device_type
== XFRAME_II_DEVICE
) {
5791 strcpy(nic
->product_name
, "Xframe II 10GbE network adapter");
5794 strcpy(nic
->product_name
, "Xframe I 10GbE network adapter");
5797 strcpy(nic
->serial_num
, "NOT AVAILABLE");
5799 vpd_data
= kmalloc(256, GFP_KERNEL
);
5801 swstats
->mem_alloc_fail_cnt
++;
5804 swstats
->mem_allocated
+= 256;
5806 for (i
= 0; i
< 256; i
+= 4) {
5807 pci_write_config_byte(nic
->pdev
, (vpd_addr
+ 2), i
);
5808 pci_read_config_byte(nic
->pdev
, (vpd_addr
+ 2), &data
);
5809 pci_write_config_byte(nic
->pdev
, (vpd_addr
+ 3), 0);
5810 for (cnt
= 0; cnt
< 5; cnt
++) {
5812 pci_read_config_byte(nic
->pdev
, (vpd_addr
+ 3), &data
);
5817 DBG_PRINT(ERR_DBG
, "Read of VPD data failed\n");
5821 pci_read_config_dword(nic
->pdev
, (vpd_addr
+ 4),
5822 (u32
*)&vpd_data
[i
]);
5826 /* read serial number of adapter */
5827 for (cnt
= 0; cnt
< 252; cnt
++) {
5828 if ((vpd_data
[cnt
] == 'S') &&
5829 (vpd_data
[cnt
+1] == 'N')) {
5830 len
= vpd_data
[cnt
+2];
5831 if (len
< min(VPD_STRING_LEN
, 256-cnt
-2)) {
5832 memcpy(nic
->serial_num
,
5835 memset(nic
->serial_num
+len
,
5837 VPD_STRING_LEN
-len
);
5844 if ((!fail
) && (vpd_data
[1] < VPD_STRING_LEN
)) {
5846 memcpy(nic
->product_name
, &vpd_data
[3], len
);
5847 nic
->product_name
[len
] = 0;
5850 swstats
->mem_freed
+= 256;
5854 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5855 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5856 * @eeprom : pointer to the user level structure provided by ethtool,
5857 * containing all relevant information.
5858 * @data_buf : user defined value to be written into Eeprom.
5859 * Description: Reads the values stored in the Eeprom at given offset
5860 * for a given length. Stores these values int the input argument data
5861 * buffer 'data_buf' and returns these to the caller (ethtool.)
5866 static int s2io_ethtool_geeprom(struct net_device
*dev
,
5867 struct ethtool_eeprom
*eeprom
, u8
* data_buf
)
5871 struct s2io_nic
*sp
= netdev_priv(dev
);
5873 eeprom
->magic
= sp
->pdev
->vendor
| (sp
->pdev
->device
<< 16);
5875 if ((eeprom
->offset
+ eeprom
->len
) > (XENA_EEPROM_SPACE
))
5876 eeprom
->len
= XENA_EEPROM_SPACE
- eeprom
->offset
;
5878 for (i
= 0; i
< eeprom
->len
; i
+= 4) {
5879 if (read_eeprom(sp
, (eeprom
->offset
+ i
), &data
)) {
5880 DBG_PRINT(ERR_DBG
, "Read of EEPROM failed\n");
5884 memcpy((data_buf
+ i
), &valid
, 4);
5890 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5891 * @sp : private member of the device structure, which is a pointer to the
5892 * s2io_nic structure.
5893 * @eeprom : pointer to the user level structure provided by ethtool,
5894 * containing all relevant information.
5895 * @data_buf ; user defined value to be written into Eeprom.
5897 * Tries to write the user provided value in the Eeprom, at the offset
5898 * given by the user.
5900 * 0 on success, -EFAULT on failure.
5903 static int s2io_ethtool_seeprom(struct net_device
*dev
,
5904 struct ethtool_eeprom
*eeprom
,
5907 int len
= eeprom
->len
, cnt
= 0;
5908 u64 valid
= 0, data
;
5909 struct s2io_nic
*sp
= netdev_priv(dev
);
5911 if (eeprom
->magic
!= (sp
->pdev
->vendor
| (sp
->pdev
->device
<< 16))) {
5913 "ETHTOOL_WRITE_EEPROM Err: "
5914 "Magic value is wrong, it is 0x%x should be 0x%x\n",
5915 (sp
->pdev
->vendor
| (sp
->pdev
->device
<< 16)),
5921 data
= (u32
)data_buf
[cnt
] & 0x000000FF;
5923 valid
= (u32
)(data
<< 24);
5927 if (write_eeprom(sp
, (eeprom
->offset
+ cnt
), valid
, 0)) {
5929 "ETHTOOL_WRITE_EEPROM Err: "
5930 "Cannot write into the specified offset\n");
5941 * s2io_register_test - reads and writes into all clock domains.
5942 * @sp : private member of the device structure, which is a pointer to the
5943 * s2io_nic structure.
5944 * @data : variable that returns the result of each of the test conducted b
5947 * Read and write into all clock domains. The NIC has 3 clock domains,
5948 * see that registers in all the three regions are accessible.
5953 static int s2io_register_test(struct s2io_nic
*sp
, uint64_t *data
)
5955 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5956 u64 val64
= 0, exp_val
;
5959 val64
= readq(&bar0
->pif_rd_swapper_fb
);
5960 if (val64
!= 0x123456789abcdefULL
) {
5962 DBG_PRINT(INFO_DBG
, "Read Test level %d fails\n", 1);
5965 val64
= readq(&bar0
->rmac_pause_cfg
);
5966 if (val64
!= 0xc000ffff00000000ULL
) {
5968 DBG_PRINT(INFO_DBG
, "Read Test level %d fails\n", 2);
5971 val64
= readq(&bar0
->rx_queue_cfg
);
5972 if (sp
->device_type
== XFRAME_II_DEVICE
)
5973 exp_val
= 0x0404040404040404ULL
;
5975 exp_val
= 0x0808080808080808ULL
;
5976 if (val64
!= exp_val
) {
5978 DBG_PRINT(INFO_DBG
, "Read Test level %d fails\n", 3);
5981 val64
= readq(&bar0
->xgxs_efifo_cfg
);
5982 if (val64
!= 0x000000001923141EULL
) {
5984 DBG_PRINT(INFO_DBG
, "Read Test level %d fails\n", 4);
5987 val64
= 0x5A5A5A5A5A5A5A5AULL
;
5988 writeq(val64
, &bar0
->xmsi_data
);
5989 val64
= readq(&bar0
->xmsi_data
);
5990 if (val64
!= 0x5A5A5A5A5A5A5A5AULL
) {
5992 DBG_PRINT(ERR_DBG
, "Write Test level %d fails\n", 1);
5995 val64
= 0xA5A5A5A5A5A5A5A5ULL
;
5996 writeq(val64
, &bar0
->xmsi_data
);
5997 val64
= readq(&bar0
->xmsi_data
);
5998 if (val64
!= 0xA5A5A5A5A5A5A5A5ULL
) {
6000 DBG_PRINT(ERR_DBG
, "Write Test level %d fails\n", 2);
6008 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
6009 * @sp : private member of the device structure, which is a pointer to the
6010 * s2io_nic structure.
6011 * @data:variable that returns the result of each of the test conducted by
6014 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
6020 static int s2io_eeprom_test(struct s2io_nic
*sp
, uint64_t *data
)
6023 u64 ret_data
, org_4F0
, org_7F0
;
6024 u8 saved_4F0
= 0, saved_7F0
= 0;
6025 struct net_device
*dev
= sp
->dev
;
6027 /* Test Write Error at offset 0 */
6028 /* Note that SPI interface allows write access to all areas
6029 * of EEPROM. Hence doing all negative testing only for Xframe I.
6031 if (sp
->device_type
== XFRAME_I_DEVICE
)
6032 if (!write_eeprom(sp
, 0, 0, 3))
6035 /* Save current values at offsets 0x4F0 and 0x7F0 */
6036 if (!read_eeprom(sp
, 0x4F0, &org_4F0
))
6038 if (!read_eeprom(sp
, 0x7F0, &org_7F0
))
6041 /* Test Write at offset 4f0 */
6042 if (write_eeprom(sp
, 0x4F0, 0x012345, 3))
6044 if (read_eeprom(sp
, 0x4F0, &ret_data
))
6047 if (ret_data
!= 0x012345) {
6048 DBG_PRINT(ERR_DBG
, "%s: eeprom test error at offset 0x4F0. "
6049 "Data written %llx Data read %llx\n",
6050 dev
->name
, (unsigned long long)0x12345,
6051 (unsigned long long)ret_data
);
6055 /* Reset the EEPROM data go FFFF */
6056 write_eeprom(sp
, 0x4F0, 0xFFFFFF, 3);
6058 /* Test Write Request Error at offset 0x7c */
6059 if (sp
->device_type
== XFRAME_I_DEVICE
)
6060 if (!write_eeprom(sp
, 0x07C, 0, 3))
6063 /* Test Write Request at offset 0x7f0 */
6064 if (write_eeprom(sp
, 0x7F0, 0x012345, 3))
6066 if (read_eeprom(sp
, 0x7F0, &ret_data
))
6069 if (ret_data
!= 0x012345) {
6070 DBG_PRINT(ERR_DBG
, "%s: eeprom test error at offset 0x7F0. "
6071 "Data written %llx Data read %llx\n",
6072 dev
->name
, (unsigned long long)0x12345,
6073 (unsigned long long)ret_data
);
6077 /* Reset the EEPROM data go FFFF */
6078 write_eeprom(sp
, 0x7F0, 0xFFFFFF, 3);
6080 if (sp
->device_type
== XFRAME_I_DEVICE
) {
6081 /* Test Write Error at offset 0x80 */
6082 if (!write_eeprom(sp
, 0x080, 0, 3))
6085 /* Test Write Error at offset 0xfc */
6086 if (!write_eeprom(sp
, 0x0FC, 0, 3))
6089 /* Test Write Error at offset 0x100 */
6090 if (!write_eeprom(sp
, 0x100, 0, 3))
6093 /* Test Write Error at offset 4ec */
6094 if (!write_eeprom(sp
, 0x4EC, 0, 3))
6098 /* Restore values at offsets 0x4F0 and 0x7F0 */
6100 write_eeprom(sp
, 0x4F0, org_4F0
, 3);
6102 write_eeprom(sp
, 0x7F0, org_7F0
, 3);
6109 * s2io_bist_test - invokes the MemBist test of the card .
6110 * @sp : private member of the device structure, which is a pointer to the
6111 * s2io_nic structure.
6112 * @data:variable that returns the result of each of the test conducted by
6115 * This invokes the MemBist test of the card. We give around
6116 * 2 secs time for the Test to complete. If it's still not complete
6117 * within this peiod, we consider that the test failed.
6119 * 0 on success and -1 on failure.
6122 static int s2io_bist_test(struct s2io_nic
*sp
, uint64_t *data
)
6125 int cnt
= 0, ret
= -1;
6127 pci_read_config_byte(sp
->pdev
, PCI_BIST
, &bist
);
6128 bist
|= PCI_BIST_START
;
6129 pci_write_config_word(sp
->pdev
, PCI_BIST
, bist
);
6132 pci_read_config_byte(sp
->pdev
, PCI_BIST
, &bist
);
6133 if (!(bist
& PCI_BIST_START
)) {
6134 *data
= (bist
& PCI_BIST_CODE_MASK
);
6146 * s2io-link_test - verifies the link state of the nic
6147 * @sp ; private member of the device structure, which is a pointer to the
6148 * s2io_nic structure.
6149 * @data: variable that returns the result of each of the test conducted by
6152 * The function verifies the link state of the NIC and updates the input
6153 * argument 'data' appropriately.
6158 static int s2io_link_test(struct s2io_nic
*sp
, uint64_t *data
)
6160 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
6163 val64
= readq(&bar0
->adapter_status
);
6164 if (!(LINK_IS_UP(val64
)))
6173 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
6174 * @sp - private member of the device structure, which is a pointer to the
6175 * s2io_nic structure.
6176 * @data - variable that returns the result of each of the test
6177 * conducted by the driver.
6179 * This is one of the offline test that tests the read and write
6180 * access to the RldRam chip on the NIC.
6185 static int s2io_rldram_test(struct s2io_nic
*sp
, uint64_t *data
)
6187 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
6189 int cnt
, iteration
= 0, test_fail
= 0;
6191 val64
= readq(&bar0
->adapter_control
);
6192 val64
&= ~ADAPTER_ECC_EN
;
6193 writeq(val64
, &bar0
->adapter_control
);
6195 val64
= readq(&bar0
->mc_rldram_test_ctrl
);
6196 val64
|= MC_RLDRAM_TEST_MODE
;
6197 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_test_ctrl
, LF
);
6199 val64
= readq(&bar0
->mc_rldram_mrs
);
6200 val64
|= MC_RLDRAM_QUEUE_SIZE_ENABLE
;
6201 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_mrs
, UF
);
6203 val64
|= MC_RLDRAM_MRS_ENABLE
;
6204 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_mrs
, UF
);
6206 while (iteration
< 2) {
6207 val64
= 0x55555555aaaa0000ULL
;
6209 val64
^= 0xFFFFFFFFFFFF0000ULL
;
6210 writeq(val64
, &bar0
->mc_rldram_test_d0
);
6212 val64
= 0xaaaa5a5555550000ULL
;
6214 val64
^= 0xFFFFFFFFFFFF0000ULL
;
6215 writeq(val64
, &bar0
->mc_rldram_test_d1
);
6217 val64
= 0x55aaaaaaaa5a0000ULL
;
6219 val64
^= 0xFFFFFFFFFFFF0000ULL
;
6220 writeq(val64
, &bar0
->mc_rldram_test_d2
);
6222 val64
= (u64
) (0x0000003ffffe0100ULL
);
6223 writeq(val64
, &bar0
->mc_rldram_test_add
);
6225 val64
= MC_RLDRAM_TEST_MODE
|
6226 MC_RLDRAM_TEST_WRITE
|
6228 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_test_ctrl
, LF
);
6230 for (cnt
= 0; cnt
< 5; cnt
++) {
6231 val64
= readq(&bar0
->mc_rldram_test_ctrl
);
6232 if (val64
& MC_RLDRAM_TEST_DONE
)
6240 val64
= MC_RLDRAM_TEST_MODE
| MC_RLDRAM_TEST_GO
;
6241 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_test_ctrl
, LF
);
6243 for (cnt
= 0; cnt
< 5; cnt
++) {
6244 val64
= readq(&bar0
->mc_rldram_test_ctrl
);
6245 if (val64
& MC_RLDRAM_TEST_DONE
)
6253 val64
= readq(&bar0
->mc_rldram_test_ctrl
);
6254 if (!(val64
& MC_RLDRAM_TEST_PASS
))
6262 /* Bring the adapter out of test mode */
6263 SPECIAL_REG_WRITE(0, &bar0
->mc_rldram_test_ctrl
, LF
);
6269 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6270 * @sp : private member of the device structure, which is a pointer to the
6271 * s2io_nic structure.
6272 * @ethtest : pointer to a ethtool command specific structure that will be
6273 * returned to the user.
6274 * @data : variable that returns the result of each of the test
6275 * conducted by the driver.
6277 * This function conducts 6 tests ( 4 offline and 2 online) to determine
6278 * the health of the card.
6283 static void s2io_ethtool_test(struct net_device
*dev
,
6284 struct ethtool_test
*ethtest
,
6287 struct s2io_nic
*sp
= netdev_priv(dev
);
6288 int orig_state
= netif_running(sp
->dev
);
6290 if (ethtest
->flags
== ETH_TEST_FL_OFFLINE
) {
6291 /* Offline Tests. */
6293 s2io_close(sp
->dev
);
6295 if (s2io_register_test(sp
, &data
[0]))
6296 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
6300 if (s2io_rldram_test(sp
, &data
[3]))
6301 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
6305 if (s2io_eeprom_test(sp
, &data
[1]))
6306 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
6308 if (s2io_bist_test(sp
, &data
[4]))
6309 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
6318 DBG_PRINT(ERR_DBG
, "%s: is not up, cannot run test\n",
6327 if (s2io_link_test(sp
, &data
[2]))
6328 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
6337 static void s2io_get_ethtool_stats(struct net_device
*dev
,
6338 struct ethtool_stats
*estats
,
6342 struct s2io_nic
*sp
= netdev_priv(dev
);
6343 struct stat_block
*stats
= sp
->mac_control
.stats_info
;
6344 struct swStat
*swstats
= &stats
->sw_stat
;
6345 struct xpakStat
*xstats
= &stats
->xpak_stat
;
6347 s2io_updt_stats(sp
);
6349 (u64
)le32_to_cpu(stats
->tmac_frms_oflow
) << 32 |
6350 le32_to_cpu(stats
->tmac_frms
);
6352 (u64
)le32_to_cpu(stats
->tmac_data_octets_oflow
) << 32 |
6353 le32_to_cpu(stats
->tmac_data_octets
);
6354 tmp_stats
[i
++] = le64_to_cpu(stats
->tmac_drop_frms
);
6356 (u64
)le32_to_cpu(stats
->tmac_mcst_frms_oflow
) << 32 |
6357 le32_to_cpu(stats
->tmac_mcst_frms
);
6359 (u64
)le32_to_cpu(stats
->tmac_bcst_frms_oflow
) << 32 |
6360 le32_to_cpu(stats
->tmac_bcst_frms
);
6361 tmp_stats
[i
++] = le64_to_cpu(stats
->tmac_pause_ctrl_frms
);
6363 (u64
)le32_to_cpu(stats
->tmac_ttl_octets_oflow
) << 32 |
6364 le32_to_cpu(stats
->tmac_ttl_octets
);
6366 (u64
)le32_to_cpu(stats
->tmac_ucst_frms_oflow
) << 32 |
6367 le32_to_cpu(stats
->tmac_ucst_frms
);
6369 (u64
)le32_to_cpu(stats
->tmac_nucst_frms_oflow
) << 32 |
6370 le32_to_cpu(stats
->tmac_nucst_frms
);
6372 (u64
)le32_to_cpu(stats
->tmac_any_err_frms_oflow
) << 32 |
6373 le32_to_cpu(stats
->tmac_any_err_frms
);
6374 tmp_stats
[i
++] = le64_to_cpu(stats
->tmac_ttl_less_fb_octets
);
6375 tmp_stats
[i
++] = le64_to_cpu(stats
->tmac_vld_ip_octets
);
6377 (u64
)le32_to_cpu(stats
->tmac_vld_ip_oflow
) << 32 |
6378 le32_to_cpu(stats
->tmac_vld_ip
);
6380 (u64
)le32_to_cpu(stats
->tmac_drop_ip_oflow
) << 32 |
6381 le32_to_cpu(stats
->tmac_drop_ip
);
6383 (u64
)le32_to_cpu(stats
->tmac_icmp_oflow
) << 32 |
6384 le32_to_cpu(stats
->tmac_icmp
);
6386 (u64
)le32_to_cpu(stats
->tmac_rst_tcp_oflow
) << 32 |
6387 le32_to_cpu(stats
->tmac_rst_tcp
);
6388 tmp_stats
[i
++] = le64_to_cpu(stats
->tmac_tcp
);
6389 tmp_stats
[i
++] = (u64
)le32_to_cpu(stats
->tmac_udp_oflow
) << 32 |
6390 le32_to_cpu(stats
->tmac_udp
);
6392 (u64
)le32_to_cpu(stats
->rmac_vld_frms_oflow
) << 32 |
6393 le32_to_cpu(stats
->rmac_vld_frms
);
6395 (u64
)le32_to_cpu(stats
->rmac_data_octets_oflow
) << 32 |
6396 le32_to_cpu(stats
->rmac_data_octets
);
6397 tmp_stats
[i
++] = le64_to_cpu(stats
->rmac_fcs_err_frms
);
6398 tmp_stats
[i
++] = le64_to_cpu(stats
->rmac_drop_frms
);
6400 (u64
)le32_to_cpu(stats
->rmac_vld_mcst_frms_oflow
) << 32 |
6401 le32_to_cpu(stats
->rmac_vld_mcst_frms
);
6403 (u64
)le32_to_cpu(stats
->rmac_vld_bcst_frms_oflow
) << 32 |
6404 le32_to_cpu(stats
->rmac_vld_bcst_frms
);
6405 tmp_stats
[i
++] = le32_to_cpu(stats
->rmac_in_rng_len_err_frms
);
6406 tmp_stats
[i
++] = le32_to_cpu(stats
->rmac_out_rng_len_err_frms
);
6407 tmp_stats
[i
++] = le64_to_cpu(stats
->rmac_long_frms
);
6408 tmp_stats
[i
++] = le64_to_cpu(stats
->rmac_pause_ctrl_frms
);
6409 tmp_stats
[i
++] = le64_to_cpu(stats
->rmac_unsup_ctrl_frms
);
6411 (u64
)le32_to_cpu(stats
->rmac_ttl_octets_oflow
) << 32 |
6412 le32_to_cpu(stats
->rmac_ttl_octets
);
6414 (u64
)le32_to_cpu(stats
->rmac_accepted_ucst_frms_oflow
) << 32
6415 | le32_to_cpu(stats
->rmac_accepted_ucst_frms
);
6417 (u64
)le32_to_cpu(stats
->rmac_accepted_nucst_frms_oflow
)
6418 << 32 | le32_to_cpu(stats
->rmac_accepted_nucst_frms
);
6420 (u64
)le32_to_cpu(stats
->rmac_discarded_frms_oflow
) << 32 |
6421 le32_to_cpu(stats
->rmac_discarded_frms
);
6423 (u64
)le32_to_cpu(stats
->rmac_drop_events_oflow
)
6424 << 32 | le32_to_cpu(stats
->rmac_drop_events
);
6425 tmp_stats
[i
++] = le64_to_cpu(stats
->rmac_ttl_less_fb_octets
);
6426 tmp_stats
[i
++] = le64_to_cpu(stats
->rmac_ttl_frms
);
6428 (u64
)le32_to_cpu(stats
->rmac_usized_frms_oflow
) << 32 |
6429 le32_to_cpu(stats
->rmac_usized_frms
);
6431 (u64
)le32_to_cpu(stats
->rmac_osized_frms_oflow
) << 32 |
6432 le32_to_cpu(stats
->rmac_osized_frms
);
6434 (u64
)le32_to_cpu(stats
->rmac_frag_frms_oflow
) << 32 |
6435 le32_to_cpu(stats
->rmac_frag_frms
);
6437 (u64
)le32_to_cpu(stats
->rmac_jabber_frms_oflow
) << 32 |
6438 le32_to_cpu(stats
->rmac_jabber_frms
);
6439 tmp_stats
[i
++] = le64_to_cpu(stats
->rmac_ttl_64_frms
);
6440 tmp_stats
[i
++] = le64_to_cpu(stats
->rmac_ttl_65_127_frms
);
6441 tmp_stats
[i
++] = le64_to_cpu(stats
->rmac_ttl_128_255_frms
);
6442 tmp_stats
[i
++] = le64_to_cpu(stats
->rmac_ttl_256_511_frms
);
6443 tmp_stats
[i
++] = le64_to_cpu(stats
->rmac_ttl_512_1023_frms
);
6444 tmp_stats
[i
++] = le64_to_cpu(stats
->rmac_ttl_1024_1518_frms
);
6446 (u64
)le32_to_cpu(stats
->rmac_ip_oflow
) << 32 |
6447 le32_to_cpu(stats
->rmac_ip
);
6448 tmp_stats
[i
++] = le64_to_cpu(stats
->rmac_ip_octets
);
6449 tmp_stats
[i
++] = le32_to_cpu(stats
->rmac_hdr_err_ip
);
6451 (u64
)le32_to_cpu(stats
->rmac_drop_ip_oflow
) << 32 |
6452 le32_to_cpu(stats
->rmac_drop_ip
);
6454 (u64
)le32_to_cpu(stats
->rmac_icmp_oflow
) << 32 |
6455 le32_to_cpu(stats
->rmac_icmp
);
6456 tmp_stats
[i
++] = le64_to_cpu(stats
->rmac_tcp
);
6458 (u64
)le32_to_cpu(stats
->rmac_udp_oflow
) << 32 |
6459 le32_to_cpu(stats
->rmac_udp
);
6461 (u64
)le32_to_cpu(stats
->rmac_err_drp_udp_oflow
) << 32 |
6462 le32_to_cpu(stats
->rmac_err_drp_udp
);
6463 tmp_stats
[i
++] = le64_to_cpu(stats
->rmac_xgmii_err_sym
);
6464 tmp_stats
[i
++] = le64_to_cpu(stats
->rmac_frms_q0
);
6465 tmp_stats
[i
++] = le64_to_cpu(stats
->rmac_frms_q1
);
6466 tmp_stats
[i
++] = le64_to_cpu(stats
->rmac_frms_q2
);
6467 tmp_stats
[i
++] = le64_to_cpu(stats
->rmac_frms_q3
);
6468 tmp_stats
[i
++] = le64_to_cpu(stats
->rmac_frms_q4
);
6469 tmp_stats
[i
++] = le64_to_cpu(stats
->rmac_frms_q5
);
6470 tmp_stats
[i
++] = le64_to_cpu(stats
->rmac_frms_q6
);
6471 tmp_stats
[i
++] = le64_to_cpu(stats
->rmac_frms_q7
);
6472 tmp_stats
[i
++] = le16_to_cpu(stats
->rmac_full_q0
);
6473 tmp_stats
[i
++] = le16_to_cpu(stats
->rmac_full_q1
);
6474 tmp_stats
[i
++] = le16_to_cpu(stats
->rmac_full_q2
);
6475 tmp_stats
[i
++] = le16_to_cpu(stats
->rmac_full_q3
);
6476 tmp_stats
[i
++] = le16_to_cpu(stats
->rmac_full_q4
);
6477 tmp_stats
[i
++] = le16_to_cpu(stats
->rmac_full_q5
);
6478 tmp_stats
[i
++] = le16_to_cpu(stats
->rmac_full_q6
);
6479 tmp_stats
[i
++] = le16_to_cpu(stats
->rmac_full_q7
);
6481 (u64
)le32_to_cpu(stats
->rmac_pause_cnt_oflow
) << 32 |
6482 le32_to_cpu(stats
->rmac_pause_cnt
);
6483 tmp_stats
[i
++] = le64_to_cpu(stats
->rmac_xgmii_data_err_cnt
);
6484 tmp_stats
[i
++] = le64_to_cpu(stats
->rmac_xgmii_ctrl_err_cnt
);
6486 (u64
)le32_to_cpu(stats
->rmac_accepted_ip_oflow
) << 32 |
6487 le32_to_cpu(stats
->rmac_accepted_ip
);
6488 tmp_stats
[i
++] = le32_to_cpu(stats
->rmac_err_tcp
);
6489 tmp_stats
[i
++] = le32_to_cpu(stats
->rd_req_cnt
);
6490 tmp_stats
[i
++] = le32_to_cpu(stats
->new_rd_req_cnt
);
6491 tmp_stats
[i
++] = le32_to_cpu(stats
->new_rd_req_rtry_cnt
);
6492 tmp_stats
[i
++] = le32_to_cpu(stats
->rd_rtry_cnt
);
6493 tmp_stats
[i
++] = le32_to_cpu(stats
->wr_rtry_rd_ack_cnt
);
6494 tmp_stats
[i
++] = le32_to_cpu(stats
->wr_req_cnt
);
6495 tmp_stats
[i
++] = le32_to_cpu(stats
->new_wr_req_cnt
);
6496 tmp_stats
[i
++] = le32_to_cpu(stats
->new_wr_req_rtry_cnt
);
6497 tmp_stats
[i
++] = le32_to_cpu(stats
->wr_rtry_cnt
);
6498 tmp_stats
[i
++] = le32_to_cpu(stats
->wr_disc_cnt
);
6499 tmp_stats
[i
++] = le32_to_cpu(stats
->rd_rtry_wr_ack_cnt
);
6500 tmp_stats
[i
++] = le32_to_cpu(stats
->txp_wr_cnt
);
6501 tmp_stats
[i
++] = le32_to_cpu(stats
->txd_rd_cnt
);
6502 tmp_stats
[i
++] = le32_to_cpu(stats
->txd_wr_cnt
);
6503 tmp_stats
[i
++] = le32_to_cpu(stats
->rxd_rd_cnt
);
6504 tmp_stats
[i
++] = le32_to_cpu(stats
->rxd_wr_cnt
);
6505 tmp_stats
[i
++] = le32_to_cpu(stats
->txf_rd_cnt
);
6506 tmp_stats
[i
++] = le32_to_cpu(stats
->rxf_wr_cnt
);
6508 /* Enhanced statistics exist only for Hercules */
6509 if (sp
->device_type
== XFRAME_II_DEVICE
) {
6511 le64_to_cpu(stats
->rmac_ttl_1519_4095_frms
);
6513 le64_to_cpu(stats
->rmac_ttl_4096_8191_frms
);
6515 le64_to_cpu(stats
->rmac_ttl_8192_max_frms
);
6516 tmp_stats
[i
++] = le64_to_cpu(stats
->rmac_ttl_gt_max_frms
);
6517 tmp_stats
[i
++] = le64_to_cpu(stats
->rmac_osized_alt_frms
);
6518 tmp_stats
[i
++] = le64_to_cpu(stats
->rmac_jabber_alt_frms
);
6519 tmp_stats
[i
++] = le64_to_cpu(stats
->rmac_gt_max_alt_frms
);
6520 tmp_stats
[i
++] = le64_to_cpu(stats
->rmac_vlan_frms
);
6521 tmp_stats
[i
++] = le32_to_cpu(stats
->rmac_len_discard
);
6522 tmp_stats
[i
++] = le32_to_cpu(stats
->rmac_fcs_discard
);
6523 tmp_stats
[i
++] = le32_to_cpu(stats
->rmac_pf_discard
);
6524 tmp_stats
[i
++] = le32_to_cpu(stats
->rmac_da_discard
);
6525 tmp_stats
[i
++] = le32_to_cpu(stats
->rmac_red_discard
);
6526 tmp_stats
[i
++] = le32_to_cpu(stats
->rmac_rts_discard
);
6527 tmp_stats
[i
++] = le32_to_cpu(stats
->rmac_ingm_full_discard
);
6528 tmp_stats
[i
++] = le32_to_cpu(stats
->link_fault_cnt
);
6532 tmp_stats
[i
++] = swstats
->single_ecc_errs
;
6533 tmp_stats
[i
++] = swstats
->double_ecc_errs
;
6534 tmp_stats
[i
++] = swstats
->parity_err_cnt
;
6535 tmp_stats
[i
++] = swstats
->serious_err_cnt
;
6536 tmp_stats
[i
++] = swstats
->soft_reset_cnt
;
6537 tmp_stats
[i
++] = swstats
->fifo_full_cnt
;
6538 for (k
= 0; k
< MAX_RX_RINGS
; k
++)
6539 tmp_stats
[i
++] = swstats
->ring_full_cnt
[k
];
6540 tmp_stats
[i
++] = xstats
->alarm_transceiver_temp_high
;
6541 tmp_stats
[i
++] = xstats
->alarm_transceiver_temp_low
;
6542 tmp_stats
[i
++] = xstats
->alarm_laser_bias_current_high
;
6543 tmp_stats
[i
++] = xstats
->alarm_laser_bias_current_low
;
6544 tmp_stats
[i
++] = xstats
->alarm_laser_output_power_high
;
6545 tmp_stats
[i
++] = xstats
->alarm_laser_output_power_low
;
6546 tmp_stats
[i
++] = xstats
->warn_transceiver_temp_high
;
6547 tmp_stats
[i
++] = xstats
->warn_transceiver_temp_low
;
6548 tmp_stats
[i
++] = xstats
->warn_laser_bias_current_high
;
6549 tmp_stats
[i
++] = xstats
->warn_laser_bias_current_low
;
6550 tmp_stats
[i
++] = xstats
->warn_laser_output_power_high
;
6551 tmp_stats
[i
++] = xstats
->warn_laser_output_power_low
;
6552 tmp_stats
[i
++] = swstats
->clubbed_frms_cnt
;
6553 tmp_stats
[i
++] = swstats
->sending_both
;
6554 tmp_stats
[i
++] = swstats
->outof_sequence_pkts
;
6555 tmp_stats
[i
++] = swstats
->flush_max_pkts
;
6556 if (swstats
->num_aggregations
) {
6557 u64 tmp
= swstats
->sum_avg_pkts_aggregated
;
6560 * Since 64-bit divide does not work on all platforms,
6561 * do repeated subtraction.
6563 while (tmp
>= swstats
->num_aggregations
) {
6564 tmp
-= swstats
->num_aggregations
;
6567 tmp_stats
[i
++] = count
;
6570 tmp_stats
[i
++] = swstats
->mem_alloc_fail_cnt
;
6571 tmp_stats
[i
++] = swstats
->pci_map_fail_cnt
;
6572 tmp_stats
[i
++] = swstats
->watchdog_timer_cnt
;
6573 tmp_stats
[i
++] = swstats
->mem_allocated
;
6574 tmp_stats
[i
++] = swstats
->mem_freed
;
6575 tmp_stats
[i
++] = swstats
->link_up_cnt
;
6576 tmp_stats
[i
++] = swstats
->link_down_cnt
;
6577 tmp_stats
[i
++] = swstats
->link_up_time
;
6578 tmp_stats
[i
++] = swstats
->link_down_time
;
6580 tmp_stats
[i
++] = swstats
->tx_buf_abort_cnt
;
6581 tmp_stats
[i
++] = swstats
->tx_desc_abort_cnt
;
6582 tmp_stats
[i
++] = swstats
->tx_parity_err_cnt
;
6583 tmp_stats
[i
++] = swstats
->tx_link_loss_cnt
;
6584 tmp_stats
[i
++] = swstats
->tx_list_proc_err_cnt
;
6586 tmp_stats
[i
++] = swstats
->rx_parity_err_cnt
;
6587 tmp_stats
[i
++] = swstats
->rx_abort_cnt
;
6588 tmp_stats
[i
++] = swstats
->rx_parity_abort_cnt
;
6589 tmp_stats
[i
++] = swstats
->rx_rda_fail_cnt
;
6590 tmp_stats
[i
++] = swstats
->rx_unkn_prot_cnt
;
6591 tmp_stats
[i
++] = swstats
->rx_fcs_err_cnt
;
6592 tmp_stats
[i
++] = swstats
->rx_buf_size_err_cnt
;
6593 tmp_stats
[i
++] = swstats
->rx_rxd_corrupt_cnt
;
6594 tmp_stats
[i
++] = swstats
->rx_unkn_err_cnt
;
6595 tmp_stats
[i
++] = swstats
->tda_err_cnt
;
6596 tmp_stats
[i
++] = swstats
->pfc_err_cnt
;
6597 tmp_stats
[i
++] = swstats
->pcc_err_cnt
;
6598 tmp_stats
[i
++] = swstats
->tti_err_cnt
;
6599 tmp_stats
[i
++] = swstats
->tpa_err_cnt
;
6600 tmp_stats
[i
++] = swstats
->sm_err_cnt
;
6601 tmp_stats
[i
++] = swstats
->lso_err_cnt
;
6602 tmp_stats
[i
++] = swstats
->mac_tmac_err_cnt
;
6603 tmp_stats
[i
++] = swstats
->mac_rmac_err_cnt
;
6604 tmp_stats
[i
++] = swstats
->xgxs_txgxs_err_cnt
;
6605 tmp_stats
[i
++] = swstats
->xgxs_rxgxs_err_cnt
;
6606 tmp_stats
[i
++] = swstats
->rc_err_cnt
;
6607 tmp_stats
[i
++] = swstats
->prc_pcix_err_cnt
;
6608 tmp_stats
[i
++] = swstats
->rpa_err_cnt
;
6609 tmp_stats
[i
++] = swstats
->rda_err_cnt
;
6610 tmp_stats
[i
++] = swstats
->rti_err_cnt
;
6611 tmp_stats
[i
++] = swstats
->mc_err_cnt
;
6614 static int s2io_ethtool_get_regs_len(struct net_device
*dev
)
6616 return XENA_REG_SPACE
;
6620 static int s2io_get_eeprom_len(struct net_device
*dev
)
6622 return XENA_EEPROM_SPACE
;
6625 static int s2io_get_sset_count(struct net_device
*dev
, int sset
)
6627 struct s2io_nic
*sp
= netdev_priv(dev
);
6631 return S2IO_TEST_LEN
;
6633 switch (sp
->device_type
) {
6634 case XFRAME_I_DEVICE
:
6635 return XFRAME_I_STAT_LEN
;
6636 case XFRAME_II_DEVICE
:
6637 return XFRAME_II_STAT_LEN
;
6646 static void s2io_ethtool_get_strings(struct net_device
*dev
,
6647 u32 stringset
, u8
*data
)
6650 struct s2io_nic
*sp
= netdev_priv(dev
);
6652 switch (stringset
) {
6654 memcpy(data
, s2io_gstrings
, S2IO_STRINGS_LEN
);
6657 stat_size
= sizeof(ethtool_xena_stats_keys
);
6658 memcpy(data
, ðtool_xena_stats_keys
, stat_size
);
6659 if (sp
->device_type
== XFRAME_II_DEVICE
) {
6660 memcpy(data
+ stat_size
,
6661 ðtool_enhanced_stats_keys
,
6662 sizeof(ethtool_enhanced_stats_keys
));
6663 stat_size
+= sizeof(ethtool_enhanced_stats_keys
);
6666 memcpy(data
+ stat_size
, ðtool_driver_stats_keys
,
6667 sizeof(ethtool_driver_stats_keys
));
6671 static int s2io_set_features(struct net_device
*dev
, u32 features
)
6673 struct s2io_nic
*sp
= netdev_priv(dev
);
6674 u32 changed
= (features
^ dev
->features
) & NETIF_F_LRO
;
6676 if (changed
&& netif_running(dev
)) {
6679 s2io_stop_all_tx_queue(sp
);
6681 dev
->features
= features
;
6682 rc
= s2io_card_up(sp
);
6686 s2io_start_all_tx_queue(sp
);
6694 static const struct ethtool_ops netdev_ethtool_ops
= {
6695 .get_settings
= s2io_ethtool_gset
,
6696 .set_settings
= s2io_ethtool_sset
,
6697 .get_drvinfo
= s2io_ethtool_gdrvinfo
,
6698 .get_regs_len
= s2io_ethtool_get_regs_len
,
6699 .get_regs
= s2io_ethtool_gregs
,
6700 .get_link
= ethtool_op_get_link
,
6701 .get_eeprom_len
= s2io_get_eeprom_len
,
6702 .get_eeprom
= s2io_ethtool_geeprom
,
6703 .set_eeprom
= s2io_ethtool_seeprom
,
6704 .get_ringparam
= s2io_ethtool_gringparam
,
6705 .get_pauseparam
= s2io_ethtool_getpause_data
,
6706 .set_pauseparam
= s2io_ethtool_setpause_data
,
6707 .self_test
= s2io_ethtool_test
,
6708 .get_strings
= s2io_ethtool_get_strings
,
6709 .set_phys_id
= s2io_ethtool_set_led
,
6710 .get_ethtool_stats
= s2io_get_ethtool_stats
,
6711 .get_sset_count
= s2io_get_sset_count
,
6715 * s2io_ioctl - Entry point for the Ioctl
6716 * @dev : Device pointer.
6717 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6718 * a proprietary structure used to pass information to the driver.
6719 * @cmd : This is used to distinguish between the different commands that
6720 * can be passed to the IOCTL functions.
6722 * Currently there are no special functionality supported in IOCTL, hence
6723 * function always return EOPNOTSUPPORTED
6726 static int s2io_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
6732 * s2io_change_mtu - entry point to change MTU size for the device.
6733 * @dev : device pointer.
6734 * @new_mtu : the new MTU size for the device.
6735 * Description: A driver entry point to change MTU size for the device.
6736 * Before changing the MTU the device must be stopped.
6738 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6742 static int s2io_change_mtu(struct net_device
*dev
, int new_mtu
)
6744 struct s2io_nic
*sp
= netdev_priv(dev
);
6747 if ((new_mtu
< MIN_MTU
) || (new_mtu
> S2IO_JUMBO_SIZE
)) {
6748 DBG_PRINT(ERR_DBG
, "%s: MTU size is invalid.\n", dev
->name
);
6753 if (netif_running(dev
)) {
6754 s2io_stop_all_tx_queue(sp
);
6756 ret
= s2io_card_up(sp
);
6758 DBG_PRINT(ERR_DBG
, "%s: Device bring up failed\n",
6762 s2io_wake_all_tx_queue(sp
);
6763 } else { /* Device is down */
6764 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
6765 u64 val64
= new_mtu
;
6767 writeq(vBIT(val64
, 2, 14), &bar0
->rmac_max_pyld_len
);
6774 * s2io_set_link - Set the LInk status
6775 * @data: long pointer to device private structue
6776 * Description: Sets the link status for the adapter
6779 static void s2io_set_link(struct work_struct
*work
)
6781 struct s2io_nic
*nic
= container_of(work
, struct s2io_nic
,
6783 struct net_device
*dev
= nic
->dev
;
6784 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
6790 if (!netif_running(dev
))
6793 if (test_and_set_bit(__S2IO_STATE_LINK_TASK
, &(nic
->state
))) {
6794 /* The card is being reset, no point doing anything */
6798 subid
= nic
->pdev
->subsystem_device
;
6799 if (s2io_link_fault_indication(nic
) == MAC_RMAC_ERR_TIMER
) {
6801 * Allow a small delay for the NICs self initiated
6802 * cleanup to complete.
6807 val64
= readq(&bar0
->adapter_status
);
6808 if (LINK_IS_UP(val64
)) {
6809 if (!(readq(&bar0
->adapter_control
) & ADAPTER_CNTL_EN
)) {
6810 if (verify_xena_quiescence(nic
)) {
6811 val64
= readq(&bar0
->adapter_control
);
6812 val64
|= ADAPTER_CNTL_EN
;
6813 writeq(val64
, &bar0
->adapter_control
);
6814 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6815 nic
->device_type
, subid
)) {
6816 val64
= readq(&bar0
->gpio_control
);
6817 val64
|= GPIO_CTRL_GPIO_0
;
6818 writeq(val64
, &bar0
->gpio_control
);
6819 val64
= readq(&bar0
->gpio_control
);
6821 val64
|= ADAPTER_LED_ON
;
6822 writeq(val64
, &bar0
->adapter_control
);
6824 nic
->device_enabled_once
= true;
6827 "%s: Error: device is not Quiescent\n",
6829 s2io_stop_all_tx_queue(nic
);
6832 val64
= readq(&bar0
->adapter_control
);
6833 val64
|= ADAPTER_LED_ON
;
6834 writeq(val64
, &bar0
->adapter_control
);
6835 s2io_link(nic
, LINK_UP
);
6837 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic
->device_type
,
6839 val64
= readq(&bar0
->gpio_control
);
6840 val64
&= ~GPIO_CTRL_GPIO_0
;
6841 writeq(val64
, &bar0
->gpio_control
);
6842 val64
= readq(&bar0
->gpio_control
);
6845 val64
= readq(&bar0
->adapter_control
);
6846 val64
= val64
& (~ADAPTER_LED_ON
);
6847 writeq(val64
, &bar0
->adapter_control
);
6848 s2io_link(nic
, LINK_DOWN
);
6850 clear_bit(__S2IO_STATE_LINK_TASK
, &(nic
->state
));
6856 static int set_rxd_buffer_pointer(struct s2io_nic
*sp
, struct RxD_t
*rxdp
,
6858 struct sk_buff
**skb
, u64
*temp0
, u64
*temp1
,
6859 u64
*temp2
, int size
)
6861 struct net_device
*dev
= sp
->dev
;
6862 struct swStat
*stats
= &sp
->mac_control
.stats_info
->sw_stat
;
6864 if ((sp
->rxd_mode
== RXD_MODE_1
) && (rxdp
->Host_Control
== 0)) {
6865 struct RxD1
*rxdp1
= (struct RxD1
*)rxdp
;
6868 DBG_PRINT(INFO_DBG
, "SKB is not NULL\n");
6870 * As Rx frame are not going to be processed,
6871 * using same mapped address for the Rxd
6874 rxdp1
->Buffer0_ptr
= *temp0
;
6876 *skb
= dev_alloc_skb(size
);
6879 "%s: Out of memory to allocate %s\n",
6880 dev
->name
, "1 buf mode SKBs");
6881 stats
->mem_alloc_fail_cnt
++;
6884 stats
->mem_allocated
+= (*skb
)->truesize
;
6885 /* storing the mapped addr in a temp variable
6886 * such it will be used for next rxd whose
6887 * Host Control is NULL
6889 rxdp1
->Buffer0_ptr
= *temp0
=
6890 pci_map_single(sp
->pdev
, (*skb
)->data
,
6891 size
- NET_IP_ALIGN
,
6892 PCI_DMA_FROMDEVICE
);
6893 if (pci_dma_mapping_error(sp
->pdev
, rxdp1
->Buffer0_ptr
))
6894 goto memalloc_failed
;
6895 rxdp
->Host_Control
= (unsigned long) (*skb
);
6897 } else if ((sp
->rxd_mode
== RXD_MODE_3B
) && (rxdp
->Host_Control
== 0)) {
6898 struct RxD3
*rxdp3
= (struct RxD3
*)rxdp
;
6899 /* Two buffer Mode */
6901 rxdp3
->Buffer2_ptr
= *temp2
;
6902 rxdp3
->Buffer0_ptr
= *temp0
;
6903 rxdp3
->Buffer1_ptr
= *temp1
;
6905 *skb
= dev_alloc_skb(size
);
6908 "%s: Out of memory to allocate %s\n",
6911 stats
->mem_alloc_fail_cnt
++;
6914 stats
->mem_allocated
+= (*skb
)->truesize
;
6915 rxdp3
->Buffer2_ptr
= *temp2
=
6916 pci_map_single(sp
->pdev
, (*skb
)->data
,
6918 PCI_DMA_FROMDEVICE
);
6919 if (pci_dma_mapping_error(sp
->pdev
, rxdp3
->Buffer2_ptr
))
6920 goto memalloc_failed
;
6921 rxdp3
->Buffer0_ptr
= *temp0
=
6922 pci_map_single(sp
->pdev
, ba
->ba_0
, BUF0_LEN
,
6923 PCI_DMA_FROMDEVICE
);
6924 if (pci_dma_mapping_error(sp
->pdev
,
6925 rxdp3
->Buffer0_ptr
)) {
6926 pci_unmap_single(sp
->pdev
,
6927 (dma_addr_t
)rxdp3
->Buffer2_ptr
,
6929 PCI_DMA_FROMDEVICE
);
6930 goto memalloc_failed
;
6932 rxdp
->Host_Control
= (unsigned long) (*skb
);
6934 /* Buffer-1 will be dummy buffer not used */
6935 rxdp3
->Buffer1_ptr
= *temp1
=
6936 pci_map_single(sp
->pdev
, ba
->ba_1
, BUF1_LEN
,
6937 PCI_DMA_FROMDEVICE
);
6938 if (pci_dma_mapping_error(sp
->pdev
,
6939 rxdp3
->Buffer1_ptr
)) {
6940 pci_unmap_single(sp
->pdev
,
6941 (dma_addr_t
)rxdp3
->Buffer0_ptr
,
6942 BUF0_LEN
, PCI_DMA_FROMDEVICE
);
6943 pci_unmap_single(sp
->pdev
,
6944 (dma_addr_t
)rxdp3
->Buffer2_ptr
,
6946 PCI_DMA_FROMDEVICE
);
6947 goto memalloc_failed
;
6954 stats
->pci_map_fail_cnt
++;
6955 stats
->mem_freed
+= (*skb
)->truesize
;
6956 dev_kfree_skb(*skb
);
6960 static void set_rxd_buffer_size(struct s2io_nic
*sp
, struct RxD_t
*rxdp
,
6963 struct net_device
*dev
= sp
->dev
;
6964 if (sp
->rxd_mode
== RXD_MODE_1
) {
6965 rxdp
->Control_2
= SET_BUFFER0_SIZE_1(size
- NET_IP_ALIGN
);
6966 } else if (sp
->rxd_mode
== RXD_MODE_3B
) {
6967 rxdp
->Control_2
= SET_BUFFER0_SIZE_3(BUF0_LEN
);
6968 rxdp
->Control_2
|= SET_BUFFER1_SIZE_3(1);
6969 rxdp
->Control_2
|= SET_BUFFER2_SIZE_3(dev
->mtu
+ 4);
6973 static int rxd_owner_bit_reset(struct s2io_nic
*sp
)
6975 int i
, j
, k
, blk_cnt
= 0, size
;
6976 struct config_param
*config
= &sp
->config
;
6977 struct mac_info
*mac_control
= &sp
->mac_control
;
6978 struct net_device
*dev
= sp
->dev
;
6979 struct RxD_t
*rxdp
= NULL
;
6980 struct sk_buff
*skb
= NULL
;
6981 struct buffAdd
*ba
= NULL
;
6982 u64 temp0_64
= 0, temp1_64
= 0, temp2_64
= 0;
6984 /* Calculate the size based on ring mode */
6985 size
= dev
->mtu
+ HEADER_ETHERNET_II_802_3_SIZE
+
6986 HEADER_802_2_SIZE
+ HEADER_SNAP_SIZE
;
6987 if (sp
->rxd_mode
== RXD_MODE_1
)
6988 size
+= NET_IP_ALIGN
;
6989 else if (sp
->rxd_mode
== RXD_MODE_3B
)
6990 size
= dev
->mtu
+ ALIGN_SIZE
+ BUF0_LEN
+ 4;
6992 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
6993 struct rx_ring_config
*rx_cfg
= &config
->rx_cfg
[i
];
6994 struct ring_info
*ring
= &mac_control
->rings
[i
];
6996 blk_cnt
= rx_cfg
->num_rxd
/ (rxd_count
[sp
->rxd_mode
] + 1);
6998 for (j
= 0; j
< blk_cnt
; j
++) {
6999 for (k
= 0; k
< rxd_count
[sp
->rxd_mode
]; k
++) {
7000 rxdp
= ring
->rx_blocks
[j
].rxds
[k
].virt_addr
;
7001 if (sp
->rxd_mode
== RXD_MODE_3B
)
7002 ba
= &ring
->ba
[j
][k
];
7003 if (set_rxd_buffer_pointer(sp
, rxdp
, ba
, &skb
,
7011 set_rxd_buffer_size(sp
, rxdp
, size
);
7013 /* flip the Ownership bit to Hardware */
7014 rxdp
->Control_1
|= RXD_OWN_XENA
;
7022 static int s2io_add_isr(struct s2io_nic
*sp
)
7025 struct net_device
*dev
= sp
->dev
;
7028 if (sp
->config
.intr_type
== MSI_X
)
7029 ret
= s2io_enable_msi_x(sp
);
7031 DBG_PRINT(ERR_DBG
, "%s: Defaulting to INTA\n", dev
->name
);
7032 sp
->config
.intr_type
= INTA
;
7036 * Store the values of the MSIX table in
7037 * the struct s2io_nic structure
7039 store_xmsi_data(sp
);
7041 /* After proper initialization of H/W, register ISR */
7042 if (sp
->config
.intr_type
== MSI_X
) {
7043 int i
, msix_rx_cnt
= 0;
7045 for (i
= 0; i
< sp
->num_entries
; i
++) {
7046 if (sp
->s2io_entries
[i
].in_use
== MSIX_FLG
) {
7047 if (sp
->s2io_entries
[i
].type
==
7049 sprintf(sp
->desc
[i
], "%s:MSI-X-%d-RX",
7051 err
= request_irq(sp
->entries
[i
].vector
,
7052 s2io_msix_ring_handle
,
7055 sp
->s2io_entries
[i
].arg
);
7056 } else if (sp
->s2io_entries
[i
].type
==
7058 sprintf(sp
->desc
[i
], "%s:MSI-X-%d-TX",
7060 err
= request_irq(sp
->entries
[i
].vector
,
7061 s2io_msix_fifo_handle
,
7064 sp
->s2io_entries
[i
].arg
);
7067 /* if either data or addr is zero print it. */
7068 if (!(sp
->msix_info
[i
].addr
&&
7069 sp
->msix_info
[i
].data
)) {
7071 "%s @Addr:0x%llx Data:0x%llx\n",
7073 (unsigned long long)
7074 sp
->msix_info
[i
].addr
,
7075 (unsigned long long)
7076 ntohl(sp
->msix_info
[i
].data
));
7080 remove_msix_isr(sp
);
7083 "%s:MSI-X-%d registration "
7084 "failed\n", dev
->name
, i
);
7087 "%s: Defaulting to INTA\n",
7089 sp
->config
.intr_type
= INTA
;
7092 sp
->s2io_entries
[i
].in_use
=
7093 MSIX_REGISTERED_SUCCESS
;
7097 pr_info("MSI-X-RX %d entries enabled\n", --msix_rx_cnt
);
7099 "MSI-X-TX entries enabled through alarm vector\n");
7102 if (sp
->config
.intr_type
== INTA
) {
7103 err
= request_irq((int)sp
->pdev
->irq
, s2io_isr
, IRQF_SHARED
,
7106 DBG_PRINT(ERR_DBG
, "%s: ISR registration failed\n",
7114 static void s2io_rem_isr(struct s2io_nic
*sp
)
7116 if (sp
->config
.intr_type
== MSI_X
)
7117 remove_msix_isr(sp
);
7119 remove_inta_isr(sp
);
7122 static void do_s2io_card_down(struct s2io_nic
*sp
, int do_io
)
7125 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
7126 register u64 val64
= 0;
7127 struct config_param
*config
;
7128 config
= &sp
->config
;
7130 if (!is_s2io_card_up(sp
))
7133 del_timer_sync(&sp
->alarm_timer
);
7134 /* If s2io_set_link task is executing, wait till it completes. */
7135 while (test_and_set_bit(__S2IO_STATE_LINK_TASK
, &(sp
->state
)))
7137 clear_bit(__S2IO_STATE_CARD_UP
, &sp
->state
);
7140 if (sp
->config
.napi
) {
7142 if (config
->intr_type
== MSI_X
) {
7143 for (; off
< sp
->config
.rx_ring_num
; off
++)
7144 napi_disable(&sp
->mac_control
.rings
[off
].napi
);
7147 napi_disable(&sp
->napi
);
7150 /* disable Tx and Rx traffic on the NIC */
7156 /* stop the tx queue, indicate link down */
7157 s2io_link(sp
, LINK_DOWN
);
7159 /* Check if the device is Quiescent and then Reset the NIC */
7161 /* As per the HW requirement we need to replenish the
7162 * receive buffer to avoid the ring bump. Since there is
7163 * no intention of processing the Rx frame at this pointwe are
7164 * just setting the ownership bit of rxd in Each Rx
7165 * ring to HW and set the appropriate buffer size
7166 * based on the ring mode
7168 rxd_owner_bit_reset(sp
);
7170 val64
= readq(&bar0
->adapter_status
);
7171 if (verify_xena_quiescence(sp
)) {
7172 if (verify_pcc_quiescent(sp
, sp
->device_enabled_once
))
7179 DBG_PRINT(ERR_DBG
, "Device not Quiescent - "
7180 "adapter status reads 0x%llx\n",
7181 (unsigned long long)val64
);
7188 /* Free all Tx buffers */
7189 free_tx_buffers(sp
);
7191 /* Free all Rx buffers */
7192 free_rx_buffers(sp
);
7194 clear_bit(__S2IO_STATE_LINK_TASK
, &(sp
->state
));
7197 static void s2io_card_down(struct s2io_nic
*sp
)
7199 do_s2io_card_down(sp
, 1);
7202 static int s2io_card_up(struct s2io_nic
*sp
)
7205 struct config_param
*config
;
7206 struct mac_info
*mac_control
;
7207 struct net_device
*dev
= (struct net_device
*)sp
->dev
;
7210 /* Initialize the H/W I/O registers */
7213 DBG_PRINT(ERR_DBG
, "%s: H/W initialization failed\n",
7221 * Initializing the Rx buffers. For now we are considering only 1
7222 * Rx ring and initializing buffers into 30 Rx blocks
7224 config
= &sp
->config
;
7225 mac_control
= &sp
->mac_control
;
7227 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
7228 struct ring_info
*ring
= &mac_control
->rings
[i
];
7230 ring
->mtu
= dev
->mtu
;
7231 ring
->lro
= !!(dev
->features
& NETIF_F_LRO
);
7232 ret
= fill_rx_buffers(sp
, ring
, 1);
7234 DBG_PRINT(ERR_DBG
, "%s: Out of memory in Open\n",
7237 free_rx_buffers(sp
);
7240 DBG_PRINT(INFO_DBG
, "Buf in ring:%d is %d:\n", i
,
7241 ring
->rx_bufs_left
);
7244 /* Initialise napi */
7246 if (config
->intr_type
== MSI_X
) {
7247 for (i
= 0; i
< sp
->config
.rx_ring_num
; i
++)
7248 napi_enable(&sp
->mac_control
.rings
[i
].napi
);
7250 napi_enable(&sp
->napi
);
7254 /* Maintain the state prior to the open */
7255 if (sp
->promisc_flg
)
7256 sp
->promisc_flg
= 0;
7257 if (sp
->m_cast_flg
) {
7259 sp
->all_multi_pos
= 0;
7262 /* Setting its receive mode */
7263 s2io_set_multicast(dev
);
7265 if (dev
->features
& NETIF_F_LRO
) {
7266 /* Initialize max aggregatable pkts per session based on MTU */
7267 sp
->lro_max_aggr_per_sess
= ((1<<16) - 1) / dev
->mtu
;
7268 /* Check if we can use (if specified) user provided value */
7269 if (lro_max_pkts
< sp
->lro_max_aggr_per_sess
)
7270 sp
->lro_max_aggr_per_sess
= lro_max_pkts
;
7273 /* Enable Rx Traffic and interrupts on the NIC */
7274 if (start_nic(sp
)) {
7275 DBG_PRINT(ERR_DBG
, "%s: Starting NIC failed\n", dev
->name
);
7277 free_rx_buffers(sp
);
7281 /* Add interrupt service routine */
7282 if (s2io_add_isr(sp
) != 0) {
7283 if (sp
->config
.intr_type
== MSI_X
)
7286 free_rx_buffers(sp
);
7290 S2IO_TIMER_CONF(sp
->alarm_timer
, s2io_alarm_handle
, sp
, (HZ
/2));
7292 set_bit(__S2IO_STATE_CARD_UP
, &sp
->state
);
7294 /* Enable select interrupts */
7295 en_dis_err_alarms(sp
, ENA_ALL_INTRS
, ENABLE_INTRS
);
7296 if (sp
->config
.intr_type
!= INTA
) {
7297 interruptible
= TX_TRAFFIC_INTR
| TX_PIC_INTR
;
7298 en_dis_able_nic_intrs(sp
, interruptible
, ENABLE_INTRS
);
7300 interruptible
= TX_TRAFFIC_INTR
| RX_TRAFFIC_INTR
;
7301 interruptible
|= TX_PIC_INTR
;
7302 en_dis_able_nic_intrs(sp
, interruptible
, ENABLE_INTRS
);
7309 * s2io_restart_nic - Resets the NIC.
7310 * @data : long pointer to the device private structure
7312 * This function is scheduled to be run by the s2io_tx_watchdog
7313 * function after 0.5 secs to reset the NIC. The idea is to reduce
7314 * the run time of the watch dog routine which is run holding a
7318 static void s2io_restart_nic(struct work_struct
*work
)
7320 struct s2io_nic
*sp
= container_of(work
, struct s2io_nic
, rst_timer_task
);
7321 struct net_device
*dev
= sp
->dev
;
7325 if (!netif_running(dev
))
7329 if (s2io_card_up(sp
)) {
7330 DBG_PRINT(ERR_DBG
, "%s: Device bring up failed\n", dev
->name
);
7332 s2io_wake_all_tx_queue(sp
);
7333 DBG_PRINT(ERR_DBG
, "%s: was reset by Tx watchdog timer\n", dev
->name
);
7339 * s2io_tx_watchdog - Watchdog for transmit side.
7340 * @dev : Pointer to net device structure
7342 * This function is triggered if the Tx Queue is stopped
7343 * for a pre-defined amount of time when the Interface is still up.
7344 * If the Interface is jammed in such a situation, the hardware is
7345 * reset (by s2io_close) and restarted again (by s2io_open) to
7346 * overcome any problem that might have been caused in the hardware.
7351 static void s2io_tx_watchdog(struct net_device
*dev
)
7353 struct s2io_nic
*sp
= netdev_priv(dev
);
7354 struct swStat
*swstats
= &sp
->mac_control
.stats_info
->sw_stat
;
7356 if (netif_carrier_ok(dev
)) {
7357 swstats
->watchdog_timer_cnt
++;
7358 schedule_work(&sp
->rst_timer_task
);
7359 swstats
->soft_reset_cnt
++;
7364 * rx_osm_handler - To perform some OS related operations on SKB.
7365 * @sp: private member of the device structure,pointer to s2io_nic structure.
7366 * @skb : the socket buffer pointer.
7367 * @len : length of the packet
7368 * @cksum : FCS checksum of the frame.
7369 * @ring_no : the ring from which this RxD was extracted.
7371 * This function is called by the Rx interrupt serivce routine to perform
7372 * some OS related operations on the SKB before passing it to the upper
7373 * layers. It mainly checks if the checksum is OK, if so adds it to the
7374 * SKBs cksum variable, increments the Rx packet count and passes the SKB
7375 * to the upper layer. If the checksum is wrong, it increments the Rx
7376 * packet error count, frees the SKB and returns error.
7378 * SUCCESS on success and -1 on failure.
7380 static int rx_osm_handler(struct ring_info
*ring_data
, struct RxD_t
* rxdp
)
7382 struct s2io_nic
*sp
= ring_data
->nic
;
7383 struct net_device
*dev
= (struct net_device
*)ring_data
->dev
;
7384 struct sk_buff
*skb
= (struct sk_buff
*)
7385 ((unsigned long)rxdp
->Host_Control
);
7386 int ring_no
= ring_data
->ring_no
;
7387 u16 l3_csum
, l4_csum
;
7388 unsigned long long err
= rxdp
->Control_1
& RXD_T_CODE
;
7389 struct lro
*uninitialized_var(lro
);
7391 struct swStat
*swstats
= &sp
->mac_control
.stats_info
->sw_stat
;
7396 /* Check for parity error */
7398 swstats
->parity_err_cnt
++;
7400 err_mask
= err
>> 48;
7403 swstats
->rx_parity_err_cnt
++;
7407 swstats
->rx_abort_cnt
++;
7411 swstats
->rx_parity_abort_cnt
++;
7415 swstats
->rx_rda_fail_cnt
++;
7419 swstats
->rx_unkn_prot_cnt
++;
7423 swstats
->rx_fcs_err_cnt
++;
7427 swstats
->rx_buf_size_err_cnt
++;
7431 swstats
->rx_rxd_corrupt_cnt
++;
7435 swstats
->rx_unkn_err_cnt
++;
7439 * Drop the packet if bad transfer code. Exception being
7440 * 0x5, which could be due to unsupported IPv6 extension header.
7441 * In this case, we let stack handle the packet.
7442 * Note that in this case, since checksum will be incorrect,
7443 * stack will validate the same.
7445 if (err_mask
!= 0x5) {
7446 DBG_PRINT(ERR_DBG
, "%s: Rx error Value: 0x%x\n",
7447 dev
->name
, err_mask
);
7448 dev
->stats
.rx_crc_errors
++;
7452 ring_data
->rx_bufs_left
-= 1;
7453 rxdp
->Host_Control
= 0;
7458 rxdp
->Host_Control
= 0;
7459 if (sp
->rxd_mode
== RXD_MODE_1
) {
7460 int len
= RXD_GET_BUFFER0_SIZE_1(rxdp
->Control_2
);
7463 } else if (sp
->rxd_mode
== RXD_MODE_3B
) {
7464 int get_block
= ring_data
->rx_curr_get_info
.block_index
;
7465 int get_off
= ring_data
->rx_curr_get_info
.offset
;
7466 int buf0_len
= RXD_GET_BUFFER0_SIZE_3(rxdp
->Control_2
);
7467 int buf2_len
= RXD_GET_BUFFER2_SIZE_3(rxdp
->Control_2
);
7468 unsigned char *buff
= skb_push(skb
, buf0_len
);
7470 struct buffAdd
*ba
= &ring_data
->ba
[get_block
][get_off
];
7471 memcpy(buff
, ba
->ba_0
, buf0_len
);
7472 skb_put(skb
, buf2_len
);
7475 if ((rxdp
->Control_1
& TCP_OR_UDP_FRAME
) &&
7476 ((!ring_data
->lro
) ||
7477 (ring_data
->lro
&& (!(rxdp
->Control_1
& RXD_FRAME_IP_FRAG
)))) &&
7478 (dev
->features
& NETIF_F_RXCSUM
)) {
7479 l3_csum
= RXD_GET_L3_CKSUM(rxdp
->Control_1
);
7480 l4_csum
= RXD_GET_L4_CKSUM(rxdp
->Control_1
);
7481 if ((l3_csum
== L3_CKSUM_OK
) && (l4_csum
== L4_CKSUM_OK
)) {
7483 * NIC verifies if the Checksum of the received
7484 * frame is Ok or not and accordingly returns
7485 * a flag in the RxD.
7487 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
7488 if (ring_data
->lro
) {
7493 ret
= s2io_club_tcp_session(ring_data
,
7498 case 3: /* Begin anew */
7501 case 1: /* Aggregate */
7502 lro_append_pkt(sp
, lro
, skb
, tcp_len
);
7504 case 4: /* Flush session */
7505 lro_append_pkt(sp
, lro
, skb
, tcp_len
);
7506 queue_rx_frame(lro
->parent
,
7508 clear_lro_session(lro
);
7509 swstats
->flush_max_pkts
++;
7511 case 2: /* Flush both */
7512 lro
->parent
->data_len
= lro
->frags_len
;
7513 swstats
->sending_both
++;
7514 queue_rx_frame(lro
->parent
,
7516 clear_lro_session(lro
);
7518 case 0: /* sessions exceeded */
7519 case -1: /* non-TCP or not L2 aggregatable */
7521 * First pkt in session not
7522 * L3/L4 aggregatable
7527 "%s: Samadhana!!\n",
7534 * Packet with erroneous checksum, let the
7535 * upper layers deal with it.
7537 skb_checksum_none_assert(skb
);
7540 skb_checksum_none_assert(skb
);
7542 swstats
->mem_freed
+= skb
->truesize
;
7544 skb_record_rx_queue(skb
, ring_no
);
7545 queue_rx_frame(skb
, RXD_GET_VLAN_TAG(rxdp
->Control_2
));
7547 sp
->mac_control
.rings
[ring_no
].rx_bufs_left
-= 1;
7552 * s2io_link - stops/starts the Tx queue.
7553 * @sp : private member of the device structure, which is a pointer to the
7554 * s2io_nic structure.
7555 * @link : inidicates whether link is UP/DOWN.
7557 * This function stops/starts the Tx queue depending on whether the link
7558 * status of the NIC is is down or up. This is called by the Alarm
7559 * interrupt handler whenever a link change interrupt comes up.
7564 static void s2io_link(struct s2io_nic
*sp
, int link
)
7566 struct net_device
*dev
= (struct net_device
*)sp
->dev
;
7567 struct swStat
*swstats
= &sp
->mac_control
.stats_info
->sw_stat
;
7569 if (link
!= sp
->last_link_state
) {
7571 if (link
== LINK_DOWN
) {
7572 DBG_PRINT(ERR_DBG
, "%s: Link down\n", dev
->name
);
7573 s2io_stop_all_tx_queue(sp
);
7574 netif_carrier_off(dev
);
7575 if (swstats
->link_up_cnt
)
7576 swstats
->link_up_time
=
7577 jiffies
- sp
->start_time
;
7578 swstats
->link_down_cnt
++;
7580 DBG_PRINT(ERR_DBG
, "%s: Link Up\n", dev
->name
);
7581 if (swstats
->link_down_cnt
)
7582 swstats
->link_down_time
=
7583 jiffies
- sp
->start_time
;
7584 swstats
->link_up_cnt
++;
7585 netif_carrier_on(dev
);
7586 s2io_wake_all_tx_queue(sp
);
7589 sp
->last_link_state
= link
;
7590 sp
->start_time
= jiffies
;
7594 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7595 * @sp : private member of the device structure, which is a pointer to the
7596 * s2io_nic structure.
7598 * This function initializes a few of the PCI and PCI-X configuration registers
7599 * with recommended values.
7604 static void s2io_init_pci(struct s2io_nic
*sp
)
7606 u16 pci_cmd
= 0, pcix_cmd
= 0;
7608 /* Enable Data Parity Error Recovery in PCI-X command register. */
7609 pci_read_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
,
7611 pci_write_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
,
7613 pci_read_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
,
7616 /* Set the PErr Response bit in PCI command register. */
7617 pci_read_config_word(sp
->pdev
, PCI_COMMAND
, &pci_cmd
);
7618 pci_write_config_word(sp
->pdev
, PCI_COMMAND
,
7619 (pci_cmd
| PCI_COMMAND_PARITY
));
7620 pci_read_config_word(sp
->pdev
, PCI_COMMAND
, &pci_cmd
);
7623 static int s2io_verify_parm(struct pci_dev
*pdev
, u8
*dev_intr_type
,
7628 if ((tx_fifo_num
> MAX_TX_FIFOS
) || (tx_fifo_num
< 1)) {
7629 DBG_PRINT(ERR_DBG
, "Requested number of tx fifos "
7630 "(%d) not supported\n", tx_fifo_num
);
7632 if (tx_fifo_num
< 1)
7635 tx_fifo_num
= MAX_TX_FIFOS
;
7637 DBG_PRINT(ERR_DBG
, "Default to %d tx fifos\n", tx_fifo_num
);
7641 *dev_multiq
= multiq
;
7643 if (tx_steering_type
&& (1 == tx_fifo_num
)) {
7644 if (tx_steering_type
!= TX_DEFAULT_STEERING
)
7646 "Tx steering is not supported with "
7647 "one fifo. Disabling Tx steering.\n");
7648 tx_steering_type
= NO_STEERING
;
7651 if ((tx_steering_type
< NO_STEERING
) ||
7652 (tx_steering_type
> TX_DEFAULT_STEERING
)) {
7654 "Requested transmit steering not supported\n");
7655 DBG_PRINT(ERR_DBG
, "Disabling transmit steering\n");
7656 tx_steering_type
= NO_STEERING
;
7659 if (rx_ring_num
> MAX_RX_RINGS
) {
7661 "Requested number of rx rings not supported\n");
7662 DBG_PRINT(ERR_DBG
, "Default to %d rx rings\n",
7664 rx_ring_num
= MAX_RX_RINGS
;
7667 if ((*dev_intr_type
!= INTA
) && (*dev_intr_type
!= MSI_X
)) {
7668 DBG_PRINT(ERR_DBG
, "Wrong intr_type requested. "
7669 "Defaulting to INTA\n");
7670 *dev_intr_type
= INTA
;
7673 if ((*dev_intr_type
== MSI_X
) &&
7674 ((pdev
->device
!= PCI_DEVICE_ID_HERC_WIN
) &&
7675 (pdev
->device
!= PCI_DEVICE_ID_HERC_UNI
))) {
7676 DBG_PRINT(ERR_DBG
, "Xframe I does not support MSI_X. "
7677 "Defaulting to INTA\n");
7678 *dev_intr_type
= INTA
;
7681 if ((rx_ring_mode
!= 1) && (rx_ring_mode
!= 2)) {
7682 DBG_PRINT(ERR_DBG
, "Requested ring mode not supported\n");
7683 DBG_PRINT(ERR_DBG
, "Defaulting to 1-buffer mode\n");
7687 for (i
= 0; i
< MAX_RX_RINGS
; i
++)
7688 if (rx_ring_sz
[i
] > MAX_RX_BLOCKS_PER_RING
) {
7689 DBG_PRINT(ERR_DBG
, "Requested rx ring size not "
7690 "supported\nDefaulting to %d\n",
7691 MAX_RX_BLOCKS_PER_RING
);
7692 rx_ring_sz
[i
] = MAX_RX_BLOCKS_PER_RING
;
7699 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7700 * or Traffic class respectively.
7701 * @nic: device private variable
7702 * Description: The function configures the receive steering to
7703 * desired receive ring.
7704 * Return Value: SUCCESS on success and
7705 * '-1' on failure (endian settings incorrect).
7707 static int rts_ds_steer(struct s2io_nic
*nic
, u8 ds_codepoint
, u8 ring
)
7709 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
7710 register u64 val64
= 0;
7712 if (ds_codepoint
> 63)
7715 val64
= RTS_DS_MEM_DATA(ring
);
7716 writeq(val64
, &bar0
->rts_ds_mem_data
);
7718 val64
= RTS_DS_MEM_CTRL_WE
|
7719 RTS_DS_MEM_CTRL_STROBE_NEW_CMD
|
7720 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint
);
7722 writeq(val64
, &bar0
->rts_ds_mem_ctrl
);
7724 return wait_for_cmd_complete(&bar0
->rts_ds_mem_ctrl
,
7725 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED
,
7729 static const struct net_device_ops s2io_netdev_ops
= {
7730 .ndo_open
= s2io_open
,
7731 .ndo_stop
= s2io_close
,
7732 .ndo_get_stats
= s2io_get_stats
,
7733 .ndo_start_xmit
= s2io_xmit
,
7734 .ndo_validate_addr
= eth_validate_addr
,
7735 .ndo_set_multicast_list
= s2io_set_multicast
,
7736 .ndo_do_ioctl
= s2io_ioctl
,
7737 .ndo_set_mac_address
= s2io_set_mac_addr
,
7738 .ndo_change_mtu
= s2io_change_mtu
,
7739 .ndo_set_features
= s2io_set_features
,
7740 .ndo_vlan_rx_register
= s2io_vlan_rx_register
,
7741 .ndo_vlan_rx_kill_vid
= s2io_vlan_rx_kill_vid
,
7742 .ndo_tx_timeout
= s2io_tx_watchdog
,
7743 #ifdef CONFIG_NET_POLL_CONTROLLER
7744 .ndo_poll_controller
= s2io_netpoll
,
7749 * s2io_init_nic - Initialization of the adapter .
7750 * @pdev : structure containing the PCI related information of the device.
7751 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7753 * The function initializes an adapter identified by the pci_dec structure.
7754 * All OS related initialization including memory and device structure and
7755 * initlaization of the device private variable is done. Also the swapper
7756 * control register is initialized to enable read and write into the I/O
7757 * registers of the device.
7759 * returns 0 on success and negative on failure.
7762 static int __devinit
7763 s2io_init_nic(struct pci_dev
*pdev
, const struct pci_device_id
*pre
)
7765 struct s2io_nic
*sp
;
7766 struct net_device
*dev
;
7768 int dma_flag
= false;
7769 u32 mac_up
, mac_down
;
7770 u64 val64
= 0, tmp64
= 0;
7771 struct XENA_dev_config __iomem
*bar0
= NULL
;
7773 struct config_param
*config
;
7774 struct mac_info
*mac_control
;
7776 u8 dev_intr_type
= intr_type
;
7779 ret
= s2io_verify_parm(pdev
, &dev_intr_type
, &dev_multiq
);
7783 ret
= pci_enable_device(pdev
);
7786 "%s: pci_enable_device failed\n", __func__
);
7790 if (!pci_set_dma_mask(pdev
, DMA_BIT_MASK(64))) {
7791 DBG_PRINT(INIT_DBG
, "%s: Using 64bit DMA\n", __func__
);
7793 if (pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64))) {
7795 "Unable to obtain 64bit DMA "
7796 "for consistent allocations\n");
7797 pci_disable_device(pdev
);
7800 } else if (!pci_set_dma_mask(pdev
, DMA_BIT_MASK(32))) {
7801 DBG_PRINT(INIT_DBG
, "%s: Using 32bit DMA\n", __func__
);
7803 pci_disable_device(pdev
);
7806 ret
= pci_request_regions(pdev
, s2io_driver_name
);
7808 DBG_PRINT(ERR_DBG
, "%s: Request Regions failed - %x\n",
7810 pci_disable_device(pdev
);
7814 dev
= alloc_etherdev_mq(sizeof(struct s2io_nic
), tx_fifo_num
);
7816 dev
= alloc_etherdev(sizeof(struct s2io_nic
));
7818 DBG_PRINT(ERR_DBG
, "Device allocation failed\n");
7819 pci_disable_device(pdev
);
7820 pci_release_regions(pdev
);
7824 pci_set_master(pdev
);
7825 pci_set_drvdata(pdev
, dev
);
7826 SET_NETDEV_DEV(dev
, &pdev
->dev
);
7828 /* Private member variable initialized to s2io NIC structure */
7829 sp
= netdev_priv(dev
);
7832 sp
->high_dma_flag
= dma_flag
;
7833 sp
->device_enabled_once
= false;
7834 if (rx_ring_mode
== 1)
7835 sp
->rxd_mode
= RXD_MODE_1
;
7836 if (rx_ring_mode
== 2)
7837 sp
->rxd_mode
= RXD_MODE_3B
;
7839 sp
->config
.intr_type
= dev_intr_type
;
7841 if ((pdev
->device
== PCI_DEVICE_ID_HERC_WIN
) ||
7842 (pdev
->device
== PCI_DEVICE_ID_HERC_UNI
))
7843 sp
->device_type
= XFRAME_II_DEVICE
;
7845 sp
->device_type
= XFRAME_I_DEVICE
;
7848 /* Initialize some PCI/PCI-X fields of the NIC. */
7852 * Setting the device configuration parameters.
7853 * Most of these parameters can be specified by the user during
7854 * module insertion as they are module loadable parameters. If
7855 * these parameters are not not specified during load time, they
7856 * are initialized with default values.
7858 config
= &sp
->config
;
7859 mac_control
= &sp
->mac_control
;
7861 config
->napi
= napi
;
7862 config
->tx_steering_type
= tx_steering_type
;
7864 /* Tx side parameters. */
7865 if (config
->tx_steering_type
== TX_PRIORITY_STEERING
)
7866 config
->tx_fifo_num
= MAX_TX_FIFOS
;
7868 config
->tx_fifo_num
= tx_fifo_num
;
7870 /* Initialize the fifos used for tx steering */
7871 if (config
->tx_fifo_num
< 5) {
7872 if (config
->tx_fifo_num
== 1)
7873 sp
->total_tcp_fifos
= 1;
7875 sp
->total_tcp_fifos
= config
->tx_fifo_num
- 1;
7876 sp
->udp_fifo_idx
= config
->tx_fifo_num
- 1;
7877 sp
->total_udp_fifos
= 1;
7878 sp
->other_fifo_idx
= sp
->total_tcp_fifos
- 1;
7880 sp
->total_tcp_fifos
= (tx_fifo_num
- FIFO_UDP_MAX_NUM
-
7881 FIFO_OTHER_MAX_NUM
);
7882 sp
->udp_fifo_idx
= sp
->total_tcp_fifos
;
7883 sp
->total_udp_fifos
= FIFO_UDP_MAX_NUM
;
7884 sp
->other_fifo_idx
= sp
->udp_fifo_idx
+ FIFO_UDP_MAX_NUM
;
7887 config
->multiq
= dev_multiq
;
7888 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
7889 struct tx_fifo_config
*tx_cfg
= &config
->tx_cfg
[i
];
7891 tx_cfg
->fifo_len
= tx_fifo_len
[i
];
7892 tx_cfg
->fifo_priority
= i
;
7895 /* mapping the QoS priority to the configured fifos */
7896 for (i
= 0; i
< MAX_TX_FIFOS
; i
++)
7897 config
->fifo_mapping
[i
] = fifo_map
[config
->tx_fifo_num
- 1][i
];
7899 /* map the hashing selector table to the configured fifos */
7900 for (i
= 0; i
< config
->tx_fifo_num
; i
++)
7901 sp
->fifo_selector
[i
] = fifo_selector
[i
];
7904 config
->tx_intr_type
= TXD_INT_TYPE_UTILZ
;
7905 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
7906 struct tx_fifo_config
*tx_cfg
= &config
->tx_cfg
[i
];
7908 tx_cfg
->f_no_snoop
= (NO_SNOOP_TXD
| NO_SNOOP_TXD_BUFFER
);
7909 if (tx_cfg
->fifo_len
< 65) {
7910 config
->tx_intr_type
= TXD_INT_TYPE_PER_LIST
;
7914 /* + 2 because one Txd for skb->data and one Txd for UFO */
7915 config
->max_txds
= MAX_SKB_FRAGS
+ 2;
7917 /* Rx side parameters. */
7918 config
->rx_ring_num
= rx_ring_num
;
7919 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
7920 struct rx_ring_config
*rx_cfg
= &config
->rx_cfg
[i
];
7921 struct ring_info
*ring
= &mac_control
->rings
[i
];
7923 rx_cfg
->num_rxd
= rx_ring_sz
[i
] * (rxd_count
[sp
->rxd_mode
] + 1);
7924 rx_cfg
->ring_priority
= i
;
7925 ring
->rx_bufs_left
= 0;
7926 ring
->rxd_mode
= sp
->rxd_mode
;
7927 ring
->rxd_count
= rxd_count
[sp
->rxd_mode
];
7928 ring
->pdev
= sp
->pdev
;
7929 ring
->dev
= sp
->dev
;
7932 for (i
= 0; i
< rx_ring_num
; i
++) {
7933 struct rx_ring_config
*rx_cfg
= &config
->rx_cfg
[i
];
7935 rx_cfg
->ring_org
= RING_ORG_BUFF1
;
7936 rx_cfg
->f_no_snoop
= (NO_SNOOP_RXD
| NO_SNOOP_RXD_BUFFER
);
7939 /* Setting Mac Control parameters */
7940 mac_control
->rmac_pause_time
= rmac_pause_time
;
7941 mac_control
->mc_pause_threshold_q0q3
= mc_pause_threshold_q0q3
;
7942 mac_control
->mc_pause_threshold_q4q7
= mc_pause_threshold_q4q7
;
7945 /* initialize the shared memory used by the NIC and the host */
7946 if (init_shared_mem(sp
)) {
7947 DBG_PRINT(ERR_DBG
, "%s: Memory allocation failed\n", dev
->name
);
7949 goto mem_alloc_failed
;
7952 sp
->bar0
= pci_ioremap_bar(pdev
, 0);
7954 DBG_PRINT(ERR_DBG
, "%s: Neterion: cannot remap io mem1\n",
7957 goto bar0_remap_failed
;
7960 sp
->bar1
= pci_ioremap_bar(pdev
, 2);
7962 DBG_PRINT(ERR_DBG
, "%s: Neterion: cannot remap io mem2\n",
7965 goto bar1_remap_failed
;
7968 dev
->irq
= pdev
->irq
;
7969 dev
->base_addr
= (unsigned long)sp
->bar0
;
7971 /* Initializing the BAR1 address as the start of the FIFO pointer. */
7972 for (j
= 0; j
< MAX_TX_FIFOS
; j
++) {
7973 mac_control
->tx_FIFO_start
[j
] = sp
->bar1
+ (j
* 0x00020000);
7976 /* Driver entry points */
7977 dev
->netdev_ops
= &s2io_netdev_ops
;
7978 SET_ETHTOOL_OPS(dev
, &netdev_ethtool_ops
);
7979 dev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
|
7980 NETIF_F_TSO
| NETIF_F_TSO6
|
7981 NETIF_F_RXCSUM
| NETIF_F_LRO
;
7982 dev
->features
|= dev
->hw_features
|
7983 NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
7984 if (sp
->device_type
& XFRAME_II_DEVICE
) {
7985 dev
->hw_features
|= NETIF_F_UFO
;
7987 dev
->features
|= NETIF_F_UFO
;
7989 if (sp
->high_dma_flag
== true)
7990 dev
->features
|= NETIF_F_HIGHDMA
;
7991 dev
->watchdog_timeo
= WATCH_DOG_TIMEOUT
;
7992 INIT_WORK(&sp
->rst_timer_task
, s2io_restart_nic
);
7993 INIT_WORK(&sp
->set_link_task
, s2io_set_link
);
7995 pci_save_state(sp
->pdev
);
7997 /* Setting swapper control on the NIC, for proper reset operation */
7998 if (s2io_set_swapper(sp
)) {
7999 DBG_PRINT(ERR_DBG
, "%s: swapper settings are wrong\n",
8002 goto set_swap_failed
;
8005 /* Verify if the Herc works on the slot its placed into */
8006 if (sp
->device_type
& XFRAME_II_DEVICE
) {
8007 mode
= s2io_verify_pci_mode(sp
);
8009 DBG_PRINT(ERR_DBG
, "%s: Unsupported PCI bus mode\n",
8012 goto set_swap_failed
;
8016 if (sp
->config
.intr_type
== MSI_X
) {
8017 sp
->num_entries
= config
->rx_ring_num
+ 1;
8018 ret
= s2io_enable_msi_x(sp
);
8021 ret
= s2io_test_msi(sp
);
8022 /* rollback MSI-X, will re-enable during add_isr() */
8023 remove_msix_isr(sp
);
8028 "MSI-X requested but failed to enable\n");
8029 sp
->config
.intr_type
= INTA
;
8033 if (config
->intr_type
== MSI_X
) {
8034 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
8035 struct ring_info
*ring
= &mac_control
->rings
[i
];
8037 netif_napi_add(dev
, &ring
->napi
, s2io_poll_msix
, 64);
8040 netif_napi_add(dev
, &sp
->napi
, s2io_poll_inta
, 64);
8043 /* Not needed for Herc */
8044 if (sp
->device_type
& XFRAME_I_DEVICE
) {
8046 * Fix for all "FFs" MAC address problems observed on
8049 fix_mac_address(sp
);
8054 * MAC address initialization.
8055 * For now only one mac address will be read and used.
8058 val64
= RMAC_ADDR_CMD_MEM_RD
| RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
8059 RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET
);
8060 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
8061 wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
8062 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
,
8064 tmp64
= readq(&bar0
->rmac_addr_data0_mem
);
8065 mac_down
= (u32
)tmp64
;
8066 mac_up
= (u32
) (tmp64
>> 32);
8068 sp
->def_mac_addr
[0].mac_addr
[3] = (u8
) (mac_up
);
8069 sp
->def_mac_addr
[0].mac_addr
[2] = (u8
) (mac_up
>> 8);
8070 sp
->def_mac_addr
[0].mac_addr
[1] = (u8
) (mac_up
>> 16);
8071 sp
->def_mac_addr
[0].mac_addr
[0] = (u8
) (mac_up
>> 24);
8072 sp
->def_mac_addr
[0].mac_addr
[5] = (u8
) (mac_down
>> 16);
8073 sp
->def_mac_addr
[0].mac_addr
[4] = (u8
) (mac_down
>> 24);
8075 /* Set the factory defined MAC address initially */
8076 dev
->addr_len
= ETH_ALEN
;
8077 memcpy(dev
->dev_addr
, sp
->def_mac_addr
, ETH_ALEN
);
8078 memcpy(dev
->perm_addr
, dev
->dev_addr
, ETH_ALEN
);
8080 /* initialize number of multicast & unicast MAC entries variables */
8081 if (sp
->device_type
== XFRAME_I_DEVICE
) {
8082 config
->max_mc_addr
= S2IO_XENA_MAX_MC_ADDRESSES
;
8083 config
->max_mac_addr
= S2IO_XENA_MAX_MAC_ADDRESSES
;
8084 config
->mc_start_offset
= S2IO_XENA_MC_ADDR_START_OFFSET
;
8085 } else if (sp
->device_type
== XFRAME_II_DEVICE
) {
8086 config
->max_mc_addr
= S2IO_HERC_MAX_MC_ADDRESSES
;
8087 config
->max_mac_addr
= S2IO_HERC_MAX_MAC_ADDRESSES
;
8088 config
->mc_start_offset
= S2IO_HERC_MC_ADDR_START_OFFSET
;
8091 /* store mac addresses from CAM to s2io_nic structure */
8092 do_s2io_store_unicast_mc(sp
);
8094 /* Configure MSIX vector for number of rings configured plus one */
8095 if ((sp
->device_type
== XFRAME_II_DEVICE
) &&
8096 (config
->intr_type
== MSI_X
))
8097 sp
->num_entries
= config
->rx_ring_num
+ 1;
8099 /* Store the values of the MSIX table in the s2io_nic structure */
8100 store_xmsi_data(sp
);
8101 /* reset Nic and bring it to known state */
8105 * Initialize link state flags
8106 * and the card state parameter
8110 /* Initialize spinlocks */
8111 for (i
= 0; i
< sp
->config
.tx_fifo_num
; i
++) {
8112 struct fifo_info
*fifo
= &mac_control
->fifos
[i
];
8114 spin_lock_init(&fifo
->tx_lock
);
8118 * SXE-002: Configure link and activity LED to init state
8121 subid
= sp
->pdev
->subsystem_device
;
8122 if ((subid
& 0xFF) >= 0x07) {
8123 val64
= readq(&bar0
->gpio_control
);
8124 val64
|= 0x0000800000000000ULL
;
8125 writeq(val64
, &bar0
->gpio_control
);
8126 val64
= 0x0411040400000000ULL
;
8127 writeq(val64
, (void __iomem
*)bar0
+ 0x2700);
8128 val64
= readq(&bar0
->gpio_control
);
8131 sp
->rx_csum
= 1; /* Rx chksum verify enabled by default */
8133 if (register_netdev(dev
)) {
8134 DBG_PRINT(ERR_DBG
, "Device registration failed\n");
8136 goto register_failed
;
8139 DBG_PRINT(ERR_DBG
, "Copyright(c) 2002-2010 Exar Corp.\n");
8140 DBG_PRINT(ERR_DBG
, "%s: Neterion %s (rev %d)\n", dev
->name
,
8141 sp
->product_name
, pdev
->revision
);
8142 DBG_PRINT(ERR_DBG
, "%s: Driver version %s\n", dev
->name
,
8143 s2io_driver_version
);
8144 DBG_PRINT(ERR_DBG
, "%s: MAC Address: %pM\n", dev
->name
, dev
->dev_addr
);
8145 DBG_PRINT(ERR_DBG
, "Serial number: %s\n", sp
->serial_num
);
8146 if (sp
->device_type
& XFRAME_II_DEVICE
) {
8147 mode
= s2io_print_pci_mode(sp
);
8150 unregister_netdev(dev
);
8151 goto set_swap_failed
;
8154 switch (sp
->rxd_mode
) {
8156 DBG_PRINT(ERR_DBG
, "%s: 1-Buffer receive mode enabled\n",
8160 DBG_PRINT(ERR_DBG
, "%s: 2-Buffer receive mode enabled\n",
8165 switch (sp
->config
.napi
) {
8167 DBG_PRINT(ERR_DBG
, "%s: NAPI disabled\n", dev
->name
);
8170 DBG_PRINT(ERR_DBG
, "%s: NAPI enabled\n", dev
->name
);
8174 DBG_PRINT(ERR_DBG
, "%s: Using %d Tx fifo(s)\n", dev
->name
,
8175 sp
->config
.tx_fifo_num
);
8177 DBG_PRINT(ERR_DBG
, "%s: Using %d Rx ring(s)\n", dev
->name
,
8178 sp
->config
.rx_ring_num
);
8180 switch (sp
->config
.intr_type
) {
8182 DBG_PRINT(ERR_DBG
, "%s: Interrupt type INTA\n", dev
->name
);
8185 DBG_PRINT(ERR_DBG
, "%s: Interrupt type MSI-X\n", dev
->name
);
8188 if (sp
->config
.multiq
) {
8189 for (i
= 0; i
< sp
->config
.tx_fifo_num
; i
++) {
8190 struct fifo_info
*fifo
= &mac_control
->fifos
[i
];
8192 fifo
->multiq
= config
->multiq
;
8194 DBG_PRINT(ERR_DBG
, "%s: Multiqueue support enabled\n",
8197 DBG_PRINT(ERR_DBG
, "%s: Multiqueue support disabled\n",
8200 switch (sp
->config
.tx_steering_type
) {
8202 DBG_PRINT(ERR_DBG
, "%s: No steering enabled for transmit\n",
8205 case TX_PRIORITY_STEERING
:
8207 "%s: Priority steering enabled for transmit\n",
8210 case TX_DEFAULT_STEERING
:
8212 "%s: Default steering enabled for transmit\n",
8216 DBG_PRINT(ERR_DBG
, "%s: Large receive offload enabled\n",
8220 "%s: UDP Fragmentation Offload(UFO) enabled\n",
8222 /* Initialize device name */
8223 sprintf(sp
->name
, "%s Neterion %s", dev
->name
, sp
->product_name
);
8226 sp
->vlan_strip_flag
= 1;
8228 sp
->vlan_strip_flag
= 0;
8231 * Make Link state as off at this point, when the Link change
8232 * interrupt comes the state will be automatically changed to
8235 netif_carrier_off(dev
);
8246 free_shared_mem(sp
);
8247 pci_disable_device(pdev
);
8248 pci_release_regions(pdev
);
8249 pci_set_drvdata(pdev
, NULL
);
8256 * s2io_rem_nic - Free the PCI device
8257 * @pdev: structure containing the PCI related information of the device.
8258 * Description: This function is called by the Pci subsystem to release a
8259 * PCI device and free up all resource held up by the device. This could
8260 * be in response to a Hot plug event or when the driver is to be removed
8264 static void __devexit
s2io_rem_nic(struct pci_dev
*pdev
)
8266 struct net_device
*dev
= pci_get_drvdata(pdev
);
8267 struct s2io_nic
*sp
;
8270 DBG_PRINT(ERR_DBG
, "Driver Data is NULL!!\n");
8274 sp
= netdev_priv(dev
);
8276 cancel_work_sync(&sp
->rst_timer_task
);
8277 cancel_work_sync(&sp
->set_link_task
);
8279 unregister_netdev(dev
);
8281 free_shared_mem(sp
);
8284 pci_release_regions(pdev
);
8285 pci_set_drvdata(pdev
, NULL
);
8287 pci_disable_device(pdev
);
8291 * s2io_starter - Entry point for the driver
8292 * Description: This function is the entry point for the driver. It verifies
8293 * the module loadable parameters and initializes PCI configuration space.
8296 static int __init
s2io_starter(void)
8298 return pci_register_driver(&s2io_driver
);
8302 * s2io_closer - Cleanup routine for the driver
8303 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
8306 static __exit
void s2io_closer(void)
8308 pci_unregister_driver(&s2io_driver
);
8309 DBG_PRINT(INIT_DBG
, "cleanup done\n");
8312 module_init(s2io_starter
);
8313 module_exit(s2io_closer
);
8315 static int check_L2_lro_capable(u8
*buffer
, struct iphdr
**ip
,
8316 struct tcphdr
**tcp
, struct RxD_t
*rxdp
,
8317 struct s2io_nic
*sp
)
8320 u8 l2_type
= (u8
)((rxdp
->Control_1
>> 37) & 0x7), ip_len
;
8322 if (!(rxdp
->Control_1
& RXD_FRAME_PROTO_TCP
)) {
8324 "%s: Non-TCP frames not supported for LRO\n",
8329 /* Checking for DIX type or DIX type with VLAN */
8330 if ((l2_type
== 0) || (l2_type
== 4)) {
8331 ip_off
= HEADER_ETHERNET_II_802_3_SIZE
;
8333 * If vlan stripping is disabled and the frame is VLAN tagged,
8334 * shift the offset by the VLAN header size bytes.
8336 if ((!sp
->vlan_strip_flag
) &&
8337 (rxdp
->Control_1
& RXD_FRAME_VLAN_TAG
))
8338 ip_off
+= HEADER_VLAN_SIZE
;
8340 /* LLC, SNAP etc are considered non-mergeable */
8344 *ip
= (struct iphdr
*)((u8
*)buffer
+ ip_off
);
8345 ip_len
= (u8
)((*ip
)->ihl
);
8347 *tcp
= (struct tcphdr
*)((unsigned long)*ip
+ ip_len
);
8352 static int check_for_socket_match(struct lro
*lro
, struct iphdr
*ip
,
8355 DBG_PRINT(INFO_DBG
, "%s: Been here...\n", __func__
);
8356 if ((lro
->iph
->saddr
!= ip
->saddr
) ||
8357 (lro
->iph
->daddr
!= ip
->daddr
) ||
8358 (lro
->tcph
->source
!= tcp
->source
) ||
8359 (lro
->tcph
->dest
!= tcp
->dest
))
8364 static inline int get_l4_pyld_length(struct iphdr
*ip
, struct tcphdr
*tcp
)
8366 return ntohs(ip
->tot_len
) - (ip
->ihl
<< 2) - (tcp
->doff
<< 2);
8369 static void initiate_new_session(struct lro
*lro
, u8
*l2h
,
8370 struct iphdr
*ip
, struct tcphdr
*tcp
,
8371 u32 tcp_pyld_len
, u16 vlan_tag
)
8373 DBG_PRINT(INFO_DBG
, "%s: Been here...\n", __func__
);
8377 lro
->tcp_next_seq
= tcp_pyld_len
+ ntohl(tcp
->seq
);
8378 lro
->tcp_ack
= tcp
->ack_seq
;
8380 lro
->total_len
= ntohs(ip
->tot_len
);
8382 lro
->vlan_tag
= vlan_tag
;
8384 * Check if we saw TCP timestamp.
8385 * Other consistency checks have already been done.
8387 if (tcp
->doff
== 8) {
8389 ptr
= (__be32
*)(tcp
+1);
8391 lro
->cur_tsval
= ntohl(*(ptr
+1));
8392 lro
->cur_tsecr
= *(ptr
+2);
8397 static void update_L3L4_header(struct s2io_nic
*sp
, struct lro
*lro
)
8399 struct iphdr
*ip
= lro
->iph
;
8400 struct tcphdr
*tcp
= lro
->tcph
;
8402 struct swStat
*swstats
= &sp
->mac_control
.stats_info
->sw_stat
;
8404 DBG_PRINT(INFO_DBG
, "%s: Been here...\n", __func__
);
8406 /* Update L3 header */
8407 ip
->tot_len
= htons(lro
->total_len
);
8409 nchk
= ip_fast_csum((u8
*)lro
->iph
, ip
->ihl
);
8412 /* Update L4 header */
8413 tcp
->ack_seq
= lro
->tcp_ack
;
8414 tcp
->window
= lro
->window
;
8416 /* Update tsecr field if this session has timestamps enabled */
8418 __be32
*ptr
= (__be32
*)(tcp
+ 1);
8419 *(ptr
+2) = lro
->cur_tsecr
;
8422 /* Update counters required for calculation of
8423 * average no. of packets aggregated.
8425 swstats
->sum_avg_pkts_aggregated
+= lro
->sg_num
;
8426 swstats
->num_aggregations
++;
8429 static void aggregate_new_rx(struct lro
*lro
, struct iphdr
*ip
,
8430 struct tcphdr
*tcp
, u32 l4_pyld
)
8432 DBG_PRINT(INFO_DBG
, "%s: Been here...\n", __func__
);
8433 lro
->total_len
+= l4_pyld
;
8434 lro
->frags_len
+= l4_pyld
;
8435 lro
->tcp_next_seq
+= l4_pyld
;
8438 /* Update ack seq no. and window ad(from this pkt) in LRO object */
8439 lro
->tcp_ack
= tcp
->ack_seq
;
8440 lro
->window
= tcp
->window
;
8444 /* Update tsecr and tsval from this packet */
8445 ptr
= (__be32
*)(tcp
+1);
8446 lro
->cur_tsval
= ntohl(*(ptr
+1));
8447 lro
->cur_tsecr
= *(ptr
+ 2);
8451 static int verify_l3_l4_lro_capable(struct lro
*l_lro
, struct iphdr
*ip
,
8452 struct tcphdr
*tcp
, u32 tcp_pyld_len
)
8456 DBG_PRINT(INFO_DBG
, "%s: Been here...\n", __func__
);
8458 if (!tcp_pyld_len
) {
8459 /* Runt frame or a pure ack */
8463 if (ip
->ihl
!= 5) /* IP has options */
8466 /* If we see CE codepoint in IP header, packet is not mergeable */
8467 if (INET_ECN_is_ce(ipv4_get_dsfield(ip
)))
8470 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
8471 if (tcp
->urg
|| tcp
->psh
|| tcp
->rst
||
8472 tcp
->syn
|| tcp
->fin
||
8473 tcp
->ece
|| tcp
->cwr
|| !tcp
->ack
) {
8475 * Currently recognize only the ack control word and
8476 * any other control field being set would result in
8477 * flushing the LRO session
8483 * Allow only one TCP timestamp option. Don't aggregate if
8484 * any other options are detected.
8486 if (tcp
->doff
!= 5 && tcp
->doff
!= 8)
8489 if (tcp
->doff
== 8) {
8490 ptr
= (u8
*)(tcp
+ 1);
8491 while (*ptr
== TCPOPT_NOP
)
8493 if (*ptr
!= TCPOPT_TIMESTAMP
|| *(ptr
+1) != TCPOLEN_TIMESTAMP
)
8496 /* Ensure timestamp value increases monotonically */
8498 if (l_lro
->cur_tsval
> ntohl(*((__be32
*)(ptr
+2))))
8501 /* timestamp echo reply should be non-zero */
8502 if (*((__be32
*)(ptr
+6)) == 0)
8509 static int s2io_club_tcp_session(struct ring_info
*ring_data
, u8
*buffer
,
8510 u8
**tcp
, u32
*tcp_len
, struct lro
**lro
,
8511 struct RxD_t
*rxdp
, struct s2io_nic
*sp
)
8514 struct tcphdr
*tcph
;
8517 struct swStat
*swstats
= &sp
->mac_control
.stats_info
->sw_stat
;
8519 ret
= check_L2_lro_capable(buffer
, &ip
, (struct tcphdr
**)tcp
,
8524 DBG_PRINT(INFO_DBG
, "IP Saddr: %x Daddr: %x\n", ip
->saddr
, ip
->daddr
);
8526 vlan_tag
= RXD_GET_VLAN_TAG(rxdp
->Control_2
);
8527 tcph
= (struct tcphdr
*)*tcp
;
8528 *tcp_len
= get_l4_pyld_length(ip
, tcph
);
8529 for (i
= 0; i
< MAX_LRO_SESSIONS
; i
++) {
8530 struct lro
*l_lro
= &ring_data
->lro0_n
[i
];
8531 if (l_lro
->in_use
) {
8532 if (check_for_socket_match(l_lro
, ip
, tcph
))
8534 /* Sock pair matched */
8537 if ((*lro
)->tcp_next_seq
!= ntohl(tcph
->seq
)) {
8538 DBG_PRINT(INFO_DBG
, "%s: Out of sequence. "
8539 "expected 0x%x, actual 0x%x\n",
8541 (*lro
)->tcp_next_seq
,
8544 swstats
->outof_sequence_pkts
++;
8549 if (!verify_l3_l4_lro_capable(l_lro
, ip
, tcph
,
8551 ret
= 1; /* Aggregate */
8553 ret
= 2; /* Flush both */
8559 /* Before searching for available LRO objects,
8560 * check if the pkt is L3/L4 aggregatable. If not
8561 * don't create new LRO session. Just send this
8564 if (verify_l3_l4_lro_capable(NULL
, ip
, tcph
, *tcp_len
))
8567 for (i
= 0; i
< MAX_LRO_SESSIONS
; i
++) {
8568 struct lro
*l_lro
= &ring_data
->lro0_n
[i
];
8569 if (!(l_lro
->in_use
)) {
8571 ret
= 3; /* Begin anew */
8577 if (ret
== 0) { /* sessions exceeded */
8578 DBG_PRINT(INFO_DBG
, "%s: All LRO sessions already in use\n",
8586 initiate_new_session(*lro
, buffer
, ip
, tcph
, *tcp_len
,
8590 update_L3L4_header(sp
, *lro
);
8593 aggregate_new_rx(*lro
, ip
, tcph
, *tcp_len
);
8594 if ((*lro
)->sg_num
== sp
->lro_max_aggr_per_sess
) {
8595 update_L3L4_header(sp
, *lro
);
8596 ret
= 4; /* Flush the LRO */
8600 DBG_PRINT(ERR_DBG
, "%s: Don't know, can't say!!\n", __func__
);
8607 static void clear_lro_session(struct lro
*lro
)
8609 static u16 lro_struct_size
= sizeof(struct lro
);
8611 memset(lro
, 0, lro_struct_size
);
8614 static void queue_rx_frame(struct sk_buff
*skb
, u16 vlan_tag
)
8616 struct net_device
*dev
= skb
->dev
;
8617 struct s2io_nic
*sp
= netdev_priv(dev
);
8619 skb
->protocol
= eth_type_trans(skb
, dev
);
8620 if (sp
->vlgrp
&& vlan_tag
&& (sp
->vlan_strip_flag
)) {
8621 /* Queueing the vlan frame to the upper layer */
8622 if (sp
->config
.napi
)
8623 vlan_hwaccel_receive_skb(skb
, sp
->vlgrp
, vlan_tag
);
8625 vlan_hwaccel_rx(skb
, sp
->vlgrp
, vlan_tag
);
8627 if (sp
->config
.napi
)
8628 netif_receive_skb(skb
);
8634 static void lro_append_pkt(struct s2io_nic
*sp
, struct lro
*lro
,
8635 struct sk_buff
*skb
, u32 tcp_len
)
8637 struct sk_buff
*first
= lro
->parent
;
8638 struct swStat
*swstats
= &sp
->mac_control
.stats_info
->sw_stat
;
8640 first
->len
+= tcp_len
;
8641 first
->data_len
= lro
->frags_len
;
8642 skb_pull(skb
, (skb
->len
- tcp_len
));
8643 if (skb_shinfo(first
)->frag_list
)
8644 lro
->last_frag
->next
= skb
;
8646 skb_shinfo(first
)->frag_list
= skb
;
8647 first
->truesize
+= skb
->truesize
;
8648 lro
->last_frag
= skb
;
8649 swstats
->clubbed_frms_cnt
++;
8653 * s2io_io_error_detected - called when PCI error is detected
8654 * @pdev: Pointer to PCI device
8655 * @state: The current pci connection state
8657 * This function is called after a PCI bus error affecting
8658 * this device has been detected.
8660 static pci_ers_result_t
s2io_io_error_detected(struct pci_dev
*pdev
,
8661 pci_channel_state_t state
)
8663 struct net_device
*netdev
= pci_get_drvdata(pdev
);
8664 struct s2io_nic
*sp
= netdev_priv(netdev
);
8666 netif_device_detach(netdev
);
8668 if (state
== pci_channel_io_perm_failure
)
8669 return PCI_ERS_RESULT_DISCONNECT
;
8671 if (netif_running(netdev
)) {
8672 /* Bring down the card, while avoiding PCI I/O */
8673 do_s2io_card_down(sp
, 0);
8675 pci_disable_device(pdev
);
8677 return PCI_ERS_RESULT_NEED_RESET
;
8681 * s2io_io_slot_reset - called after the pci bus has been reset.
8682 * @pdev: Pointer to PCI device
8684 * Restart the card from scratch, as if from a cold-boot.
8685 * At this point, the card has exprienced a hard reset,
8686 * followed by fixups by BIOS, and has its config space
8687 * set up identically to what it was at cold boot.
8689 static pci_ers_result_t
s2io_io_slot_reset(struct pci_dev
*pdev
)
8691 struct net_device
*netdev
= pci_get_drvdata(pdev
);
8692 struct s2io_nic
*sp
= netdev_priv(netdev
);
8694 if (pci_enable_device(pdev
)) {
8695 pr_err("Cannot re-enable PCI device after reset.\n");
8696 return PCI_ERS_RESULT_DISCONNECT
;
8699 pci_set_master(pdev
);
8702 return PCI_ERS_RESULT_RECOVERED
;
8706 * s2io_io_resume - called when traffic can start flowing again.
8707 * @pdev: Pointer to PCI device
8709 * This callback is called when the error recovery driver tells
8710 * us that its OK to resume normal operation.
8712 static void s2io_io_resume(struct pci_dev
*pdev
)
8714 struct net_device
*netdev
= pci_get_drvdata(pdev
);
8715 struct s2io_nic
*sp
= netdev_priv(netdev
);
8717 if (netif_running(netdev
)) {
8718 if (s2io_card_up(sp
)) {
8719 pr_err("Can't bring device back up after reset.\n");
8723 if (s2io_set_mac_addr(netdev
, netdev
->dev_addr
) == FAILURE
) {
8725 pr_err("Can't restore mac addr after reset.\n");
8730 netif_device_attach(netdev
);
8731 netif_tx_wake_all_queues(netdev
);