1 /************************************************************************
2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3 * Copyright(c) 2002-2007 Neterion Inc.
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
21 * Francois Romieu : For pointing out all code part that were
22 * deprecated and also styling related comments.
23 * Grant Grundler : For helping me get rid of some Architecture
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
27 * The module loadable parameters that are supported by the driver and a brief
28 * explaination of all the variables.
30 * rx_ring_num : This can be used to program the number of receive rings used
32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
38 * Tx descriptors that can be associated with each corresponding FIFO.
39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40 * 2(MSI_X). Default value is '2(MSI_X)'
41 * lro_enable: Specifies whether to enable Large Receive Offload (LRO) or not.
42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
45 * napi: This parameter used to enable/disable NAPI (polling Rx)
46 * Possible values '1' for enable and '0' for disable. Default is '1'
47 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48 * Possible values '1' for enable and '0' for disable. Default is '0'
49 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50 * Possible values '1' for enable , '0' for disable.
51 * Default is '2' - which means disable in promisc mode
52 * and enable in non-promiscuous mode.
53 * multiq: This parameter used to enable/disable MULTIQUEUE support.
54 * Possible values '1' for enable and '0' for disable. Default is '0'
55 ************************************************************************/
57 #include <linux/module.h>
58 #include <linux/types.h>
59 #include <linux/errno.h>
60 #include <linux/ioport.h>
61 #include <linux/pci.h>
62 #include <linux/dma-mapping.h>
63 #include <linux/kernel.h>
64 #include <linux/netdevice.h>
65 #include <linux/etherdevice.h>
66 #include <linux/mdio.h>
67 #include <linux/skbuff.h>
68 #include <linux/init.h>
69 #include <linux/delay.h>
70 #include <linux/stddef.h>
71 #include <linux/ioctl.h>
72 #include <linux/timex.h>
73 #include <linux/ethtool.h>
74 #include <linux/workqueue.h>
75 #include <linux/if_vlan.h>
77 #include <linux/tcp.h>
80 #include <asm/system.h>
81 #include <asm/uaccess.h>
83 #include <asm/div64.h>
88 #include "s2io-regs.h"
90 #define DRV_VERSION "2.0.26.25"
92 /* S2io Driver name & version. */
93 static char s2io_driver_name
[] = "Neterion";
94 static char s2io_driver_version
[] = DRV_VERSION
;
96 static int rxd_size
[2] = {32,48};
97 static int rxd_count
[2] = {127,85};
99 static inline int RXD_IS_UP2DT(struct RxD_t
*rxdp
)
103 ret
= ((!(rxdp
->Control_1
& RXD_OWN_XENA
)) &&
104 (GET_RXD_MARKER(rxdp
->Control_2
) != THE_RXD_MARK
));
110 * Cards with following subsystem_id have a link state indication
111 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
112 * macro below identifies these cards given the subsystem_id.
114 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
115 (dev_type == XFRAME_I_DEVICE) ? \
116 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
117 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
119 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
120 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
122 static inline int is_s2io_card_up(const struct s2io_nic
* sp
)
124 return test_bit(__S2IO_STATE_CARD_UP
, &sp
->state
);
127 /* Ethtool related variables and Macros. */
128 static char s2io_gstrings
[][ETH_GSTRING_LEN
] = {
129 "Register test\t(offline)",
130 "Eeprom test\t(offline)",
131 "Link test\t(online)",
132 "RLDRAM test\t(offline)",
133 "BIST Test\t(offline)"
136 static char ethtool_xena_stats_keys
[][ETH_GSTRING_LEN
] = {
138 {"tmac_data_octets"},
142 {"tmac_pause_ctrl_frms"},
146 {"tmac_any_err_frms"},
147 {"tmac_ttl_less_fb_octets"},
148 {"tmac_vld_ip_octets"},
156 {"rmac_data_octets"},
157 {"rmac_fcs_err_frms"},
159 {"rmac_vld_mcst_frms"},
160 {"rmac_vld_bcst_frms"},
161 {"rmac_in_rng_len_err_frms"},
162 {"rmac_out_rng_len_err_frms"},
164 {"rmac_pause_ctrl_frms"},
165 {"rmac_unsup_ctrl_frms"},
167 {"rmac_accepted_ucst_frms"},
168 {"rmac_accepted_nucst_frms"},
169 {"rmac_discarded_frms"},
170 {"rmac_drop_events"},
171 {"rmac_ttl_less_fb_octets"},
173 {"rmac_usized_frms"},
174 {"rmac_osized_frms"},
176 {"rmac_jabber_frms"},
177 {"rmac_ttl_64_frms"},
178 {"rmac_ttl_65_127_frms"},
179 {"rmac_ttl_128_255_frms"},
180 {"rmac_ttl_256_511_frms"},
181 {"rmac_ttl_512_1023_frms"},
182 {"rmac_ttl_1024_1518_frms"},
190 {"rmac_err_drp_udp"},
191 {"rmac_xgmii_err_sym"},
209 {"rmac_xgmii_data_err_cnt"},
210 {"rmac_xgmii_ctrl_err_cnt"},
211 {"rmac_accepted_ip"},
215 {"new_rd_req_rtry_cnt"},
217 {"wr_rtry_rd_ack_cnt"},
220 {"new_wr_req_rtry_cnt"},
223 {"rd_rtry_wr_ack_cnt"},
233 static char ethtool_enhanced_stats_keys
[][ETH_GSTRING_LEN
] = {
234 {"rmac_ttl_1519_4095_frms"},
235 {"rmac_ttl_4096_8191_frms"},
236 {"rmac_ttl_8192_max_frms"},
237 {"rmac_ttl_gt_max_frms"},
238 {"rmac_osized_alt_frms"},
239 {"rmac_jabber_alt_frms"},
240 {"rmac_gt_max_alt_frms"},
242 {"rmac_len_discard"},
243 {"rmac_fcs_discard"},
246 {"rmac_red_discard"},
247 {"rmac_rts_discard"},
248 {"rmac_ingm_full_discard"},
252 static char ethtool_driver_stats_keys
[][ETH_GSTRING_LEN
] = {
253 {"\n DRIVER STATISTICS"},
254 {"single_bit_ecc_errs"},
255 {"double_bit_ecc_errs"},
268 {"alarm_transceiver_temp_high"},
269 {"alarm_transceiver_temp_low"},
270 {"alarm_laser_bias_current_high"},
271 {"alarm_laser_bias_current_low"},
272 {"alarm_laser_output_power_high"},
273 {"alarm_laser_output_power_low"},
274 {"warn_transceiver_temp_high"},
275 {"warn_transceiver_temp_low"},
276 {"warn_laser_bias_current_high"},
277 {"warn_laser_bias_current_low"},
278 {"warn_laser_output_power_high"},
279 {"warn_laser_output_power_low"},
280 {"lro_aggregated_pkts"},
281 {"lro_flush_both_count"},
282 {"lro_out_of_sequence_pkts"},
283 {"lro_flush_due_to_max_pkts"},
284 {"lro_avg_aggr_pkts"},
285 {"mem_alloc_fail_cnt"},
286 {"pci_map_fail_cnt"},
287 {"watchdog_timer_cnt"},
294 {"tx_tcode_buf_abort_cnt"},
295 {"tx_tcode_desc_abort_cnt"},
296 {"tx_tcode_parity_err_cnt"},
297 {"tx_tcode_link_loss_cnt"},
298 {"tx_tcode_list_proc_err_cnt"},
299 {"rx_tcode_parity_err_cnt"},
300 {"rx_tcode_abort_cnt"},
301 {"rx_tcode_parity_abort_cnt"},
302 {"rx_tcode_rda_fail_cnt"},
303 {"rx_tcode_unkn_prot_cnt"},
304 {"rx_tcode_fcs_err_cnt"},
305 {"rx_tcode_buf_size_err_cnt"},
306 {"rx_tcode_rxd_corrupt_cnt"},
307 {"rx_tcode_unkn_err_cnt"},
315 {"mac_tmac_err_cnt"},
316 {"mac_rmac_err_cnt"},
317 {"xgxs_txgxs_err_cnt"},
318 {"xgxs_rxgxs_err_cnt"},
320 {"prc_pcix_err_cnt"},
327 #define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys)
328 #define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys)
329 #define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys)
331 #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN )
332 #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN )
334 #define XFRAME_I_STAT_STRINGS_LEN ( XFRAME_I_STAT_LEN * ETH_GSTRING_LEN )
335 #define XFRAME_II_STAT_STRINGS_LEN ( XFRAME_II_STAT_LEN * ETH_GSTRING_LEN )
337 #define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings)
338 #define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
340 #define S2IO_TIMER_CONF(timer, handle, arg, exp) \
341 init_timer(&timer); \
342 timer.function = handle; \
343 timer.data = (unsigned long) arg; \
344 mod_timer(&timer, (jiffies + exp)) \
346 /* copy mac addr to def_mac_addr array */
347 static void do_s2io_copy_mac_addr(struct s2io_nic
*sp
, int offset
, u64 mac_addr
)
349 sp
->def_mac_addr
[offset
].mac_addr
[5] = (u8
) (mac_addr
);
350 sp
->def_mac_addr
[offset
].mac_addr
[4] = (u8
) (mac_addr
>> 8);
351 sp
->def_mac_addr
[offset
].mac_addr
[3] = (u8
) (mac_addr
>> 16);
352 sp
->def_mac_addr
[offset
].mac_addr
[2] = (u8
) (mac_addr
>> 24);
353 sp
->def_mac_addr
[offset
].mac_addr
[1] = (u8
) (mac_addr
>> 32);
354 sp
->def_mac_addr
[offset
].mac_addr
[0] = (u8
) (mac_addr
>> 40);
358 static void s2io_vlan_rx_register(struct net_device
*dev
,
359 struct vlan_group
*grp
)
362 struct s2io_nic
*nic
= netdev_priv(dev
);
363 unsigned long flags
[MAX_TX_FIFOS
];
364 struct mac_info
*mac_control
= &nic
->mac_control
;
365 struct config_param
*config
= &nic
->config
;
367 for (i
= 0; i
< config
->tx_fifo_num
; i
++)
368 spin_lock_irqsave(&mac_control
->fifos
[i
].tx_lock
, flags
[i
]);
371 for (i
= config
->tx_fifo_num
- 1; i
>= 0; i
--)
372 spin_unlock_irqrestore(&mac_control
->fifos
[i
].tx_lock
,
376 /* Unregister the vlan */
377 static void s2io_vlan_rx_kill_vid(struct net_device
*dev
, unsigned short vid
)
380 struct s2io_nic
*nic
= netdev_priv(dev
);
381 unsigned long flags
[MAX_TX_FIFOS
];
382 struct mac_info
*mac_control
= &nic
->mac_control
;
383 struct config_param
*config
= &nic
->config
;
385 for (i
= 0; i
< config
->tx_fifo_num
; i
++)
386 spin_lock_irqsave(&mac_control
->fifos
[i
].tx_lock
, flags
[i
]);
389 vlan_group_set_device(nic
->vlgrp
, vid
, NULL
);
391 for (i
= config
->tx_fifo_num
- 1; i
>= 0; i
--)
392 spin_unlock_irqrestore(&mac_control
->fifos
[i
].tx_lock
,
397 * Constants to be programmed into the Xena's registers, to configure
402 static const u64 herc_act_dtx_cfg
[] = {
404 0x8000051536750000ULL
, 0x80000515367500E0ULL
,
406 0x8000051536750004ULL
, 0x80000515367500E4ULL
,
408 0x80010515003F0000ULL
, 0x80010515003F00E0ULL
,
410 0x80010515003F0004ULL
, 0x80010515003F00E4ULL
,
412 0x801205150D440000ULL
, 0x801205150D4400E0ULL
,
414 0x801205150D440004ULL
, 0x801205150D4400E4ULL
,
416 0x80020515F2100000ULL
, 0x80020515F21000E0ULL
,
418 0x80020515F2100004ULL
, 0x80020515F21000E4ULL
,
423 static const u64 xena_dtx_cfg
[] = {
425 0x8000051500000000ULL
, 0x80000515000000E0ULL
,
427 0x80000515D9350004ULL
, 0x80000515D93500E4ULL
,
429 0x8001051500000000ULL
, 0x80010515000000E0ULL
,
431 0x80010515001E0004ULL
, 0x80010515001E00E4ULL
,
433 0x8002051500000000ULL
, 0x80020515000000E0ULL
,
435 0x80020515F2100004ULL
, 0x80020515F21000E4ULL
,
440 * Constants for Fixing the MacAddress problem seen mostly on
443 static const u64 fix_mac
[] = {
444 0x0060000000000000ULL
, 0x0060600000000000ULL
,
445 0x0040600000000000ULL
, 0x0000600000000000ULL
,
446 0x0020600000000000ULL
, 0x0060600000000000ULL
,
447 0x0020600000000000ULL
, 0x0060600000000000ULL
,
448 0x0020600000000000ULL
, 0x0060600000000000ULL
,
449 0x0020600000000000ULL
, 0x0060600000000000ULL
,
450 0x0020600000000000ULL
, 0x0060600000000000ULL
,
451 0x0020600000000000ULL
, 0x0060600000000000ULL
,
452 0x0020600000000000ULL
, 0x0060600000000000ULL
,
453 0x0020600000000000ULL
, 0x0060600000000000ULL
,
454 0x0020600000000000ULL
, 0x0060600000000000ULL
,
455 0x0020600000000000ULL
, 0x0060600000000000ULL
,
456 0x0020600000000000ULL
, 0x0000600000000000ULL
,
457 0x0040600000000000ULL
, 0x0060600000000000ULL
,
461 MODULE_LICENSE("GPL");
462 MODULE_VERSION(DRV_VERSION
);
465 /* Module Loadable parameters. */
466 S2IO_PARM_INT(tx_fifo_num
, FIFO_DEFAULT_NUM
);
467 S2IO_PARM_INT(rx_ring_num
, 1);
468 S2IO_PARM_INT(multiq
, 0);
469 S2IO_PARM_INT(rx_ring_mode
, 1);
470 S2IO_PARM_INT(use_continuous_tx_intrs
, 1);
471 S2IO_PARM_INT(rmac_pause_time
, 0x100);
472 S2IO_PARM_INT(mc_pause_threshold_q0q3
, 187);
473 S2IO_PARM_INT(mc_pause_threshold_q4q7
, 187);
474 S2IO_PARM_INT(shared_splits
, 0);
475 S2IO_PARM_INT(tmac_util_period
, 5);
476 S2IO_PARM_INT(rmac_util_period
, 5);
477 S2IO_PARM_INT(l3l4hdr_size
, 128);
478 /* 0 is no steering, 1 is Priority steering, 2 is Default steering */
479 S2IO_PARM_INT(tx_steering_type
, TX_DEFAULT_STEERING
);
480 /* Frequency of Rx desc syncs expressed as power of 2 */
481 S2IO_PARM_INT(rxsync_frequency
, 3);
482 /* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
483 S2IO_PARM_INT(intr_type
, 2);
484 /* Large receive offload feature */
485 static unsigned int lro_enable
;
486 module_param_named(lro
, lro_enable
, uint
, 0);
488 /* Max pkts to be aggregated by LRO at one time. If not specified,
489 * aggregation happens until we hit max IP pkt size(64K)
491 S2IO_PARM_INT(lro_max_pkts
, 0xFFFF);
492 S2IO_PARM_INT(indicate_max_pkts
, 0);
494 S2IO_PARM_INT(napi
, 1);
495 S2IO_PARM_INT(ufo
, 0);
496 S2IO_PARM_INT(vlan_tag_strip
, NO_STRIP_IN_PROMISC
);
498 static unsigned int tx_fifo_len
[MAX_TX_FIFOS
] =
499 {DEFAULT_FIFO_0_LEN
, [1 ...(MAX_TX_FIFOS
- 1)] = DEFAULT_FIFO_1_7_LEN
};
500 static unsigned int rx_ring_sz
[MAX_RX_RINGS
] =
501 {[0 ...(MAX_RX_RINGS
- 1)] = SMALL_BLK_CNT
};
502 static unsigned int rts_frm_len
[MAX_RX_RINGS
] =
503 {[0 ...(MAX_RX_RINGS
- 1)] = 0 };
505 module_param_array(tx_fifo_len
, uint
, NULL
, 0);
506 module_param_array(rx_ring_sz
, uint
, NULL
, 0);
507 module_param_array(rts_frm_len
, uint
, NULL
, 0);
511 * This table lists all the devices that this driver supports.
513 static struct pci_device_id s2io_tbl
[] __devinitdata
= {
514 {PCI_VENDOR_ID_S2IO
, PCI_DEVICE_ID_S2IO_WIN
,
515 PCI_ANY_ID
, PCI_ANY_ID
},
516 {PCI_VENDOR_ID_S2IO
, PCI_DEVICE_ID_S2IO_UNI
,
517 PCI_ANY_ID
, PCI_ANY_ID
},
518 {PCI_VENDOR_ID_S2IO
, PCI_DEVICE_ID_HERC_WIN
,
519 PCI_ANY_ID
, PCI_ANY_ID
},
520 {PCI_VENDOR_ID_S2IO
, PCI_DEVICE_ID_HERC_UNI
,
521 PCI_ANY_ID
, PCI_ANY_ID
},
525 MODULE_DEVICE_TABLE(pci
, s2io_tbl
);
527 static struct pci_error_handlers s2io_err_handler
= {
528 .error_detected
= s2io_io_error_detected
,
529 .slot_reset
= s2io_io_slot_reset
,
530 .resume
= s2io_io_resume
,
533 static struct pci_driver s2io_driver
= {
535 .id_table
= s2io_tbl
,
536 .probe
= s2io_init_nic
,
537 .remove
= __devexit_p(s2io_rem_nic
),
538 .err_handler
= &s2io_err_handler
,
541 /* A simplifier macro used both by init and free shared_mem Fns(). */
542 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
544 /* netqueue manipulation helper functions */
545 static inline void s2io_stop_all_tx_queue(struct s2io_nic
*sp
)
547 if (!sp
->config
.multiq
) {
550 for (i
= 0; i
< sp
->config
.tx_fifo_num
; i
++)
551 sp
->mac_control
.fifos
[i
].queue_state
= FIFO_QUEUE_STOP
;
553 netif_tx_stop_all_queues(sp
->dev
);
556 static inline void s2io_stop_tx_queue(struct s2io_nic
*sp
, int fifo_no
)
558 if (!sp
->config
.multiq
)
559 sp
->mac_control
.fifos
[fifo_no
].queue_state
=
562 netif_tx_stop_all_queues(sp
->dev
);
565 static inline void s2io_start_all_tx_queue(struct s2io_nic
*sp
)
567 if (!sp
->config
.multiq
) {
570 for (i
= 0; i
< sp
->config
.tx_fifo_num
; i
++)
571 sp
->mac_control
.fifos
[i
].queue_state
= FIFO_QUEUE_START
;
573 netif_tx_start_all_queues(sp
->dev
);
576 static inline void s2io_start_tx_queue(struct s2io_nic
*sp
, int fifo_no
)
578 if (!sp
->config
.multiq
)
579 sp
->mac_control
.fifos
[fifo_no
].queue_state
=
582 netif_tx_start_all_queues(sp
->dev
);
585 static inline void s2io_wake_all_tx_queue(struct s2io_nic
*sp
)
587 if (!sp
->config
.multiq
) {
590 for (i
= 0; i
< sp
->config
.tx_fifo_num
; i
++)
591 sp
->mac_control
.fifos
[i
].queue_state
= FIFO_QUEUE_START
;
593 netif_tx_wake_all_queues(sp
->dev
);
596 static inline void s2io_wake_tx_queue(
597 struct fifo_info
*fifo
, int cnt
, u8 multiq
)
601 if (cnt
&& __netif_subqueue_stopped(fifo
->dev
, fifo
->fifo_no
))
602 netif_wake_subqueue(fifo
->dev
, fifo
->fifo_no
);
603 } else if (cnt
&& (fifo
->queue_state
== FIFO_QUEUE_STOP
)) {
604 if (netif_queue_stopped(fifo
->dev
)) {
605 fifo
->queue_state
= FIFO_QUEUE_START
;
606 netif_wake_queue(fifo
->dev
);
612 * init_shared_mem - Allocation and Initialization of Memory
613 * @nic: Device private variable.
614 * Description: The function allocates all the memory areas shared
615 * between the NIC and the driver. This includes Tx descriptors,
616 * Rx descriptors and the statistics block.
619 static int init_shared_mem(struct s2io_nic
*nic
)
622 void *tmp_v_addr
, *tmp_v_addr_next
;
623 dma_addr_t tmp_p_addr
, tmp_p_addr_next
;
624 struct RxD_block
*pre_rxd_blk
= NULL
;
626 int lst_size
, lst_per_page
;
627 struct net_device
*dev
= nic
->dev
;
631 struct mac_info
*mac_control
;
632 struct config_param
*config
;
633 unsigned long long mem_allocated
= 0;
635 mac_control
= &nic
->mac_control
;
636 config
= &nic
->config
;
639 /* Allocation and initialization of TXDLs in FIOFs */
641 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
642 size
+= config
->tx_cfg
[i
].fifo_len
;
644 if (size
> MAX_AVAILABLE_TXDS
) {
645 DBG_PRINT(ERR_DBG
, "s2io: Requested TxDs too high, ");
646 DBG_PRINT(ERR_DBG
, "Requested: %d, max supported: 8192\n", size
);
651 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
652 size
= config
->tx_cfg
[i
].fifo_len
;
654 * Legal values are from 2 to 8192
657 DBG_PRINT(ERR_DBG
, "s2io: Invalid fifo len (%d)", size
);
658 DBG_PRINT(ERR_DBG
, "for fifo %d\n", i
);
659 DBG_PRINT(ERR_DBG
, "s2io: Legal values for fifo len"
665 lst_size
= (sizeof(struct TxD
) * config
->max_txds
);
666 lst_per_page
= PAGE_SIZE
/ lst_size
;
668 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
669 int fifo_len
= config
->tx_cfg
[i
].fifo_len
;
670 int list_holder_size
= fifo_len
* sizeof(struct list_info_hold
);
671 mac_control
->fifos
[i
].list_info
= kzalloc(list_holder_size
,
673 if (!mac_control
->fifos
[i
].list_info
) {
675 "Malloc failed for list_info\n");
678 mem_allocated
+= list_holder_size
;
680 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
681 int page_num
= TXD_MEM_PAGE_CNT(config
->tx_cfg
[i
].fifo_len
,
683 mac_control
->fifos
[i
].tx_curr_put_info
.offset
= 0;
684 mac_control
->fifos
[i
].tx_curr_put_info
.fifo_len
=
685 config
->tx_cfg
[i
].fifo_len
- 1;
686 mac_control
->fifos
[i
].tx_curr_get_info
.offset
= 0;
687 mac_control
->fifos
[i
].tx_curr_get_info
.fifo_len
=
688 config
->tx_cfg
[i
].fifo_len
- 1;
689 mac_control
->fifos
[i
].fifo_no
= i
;
690 mac_control
->fifos
[i
].nic
= nic
;
691 mac_control
->fifos
[i
].max_txds
= MAX_SKB_FRAGS
+ 2;
692 mac_control
->fifos
[i
].dev
= dev
;
694 for (j
= 0; j
< page_num
; j
++) {
698 tmp_v
= pci_alloc_consistent(nic
->pdev
,
702 "pci_alloc_consistent ");
703 DBG_PRINT(INFO_DBG
, "failed for TxDL\n");
706 /* If we got a zero DMA address(can happen on
707 * certain platforms like PPC), reallocate.
708 * Store virtual address of page we don't want,
712 mac_control
->zerodma_virt_addr
= tmp_v
;
714 "%s: Zero DMA address for TxDL. ", dev
->name
);
716 "Virtual address %p\n", tmp_v
);
717 tmp_v
= pci_alloc_consistent(nic
->pdev
,
721 "pci_alloc_consistent ");
722 DBG_PRINT(INFO_DBG
, "failed for TxDL\n");
725 mem_allocated
+= PAGE_SIZE
;
727 while (k
< lst_per_page
) {
728 int l
= (j
* lst_per_page
) + k
;
729 if (l
== config
->tx_cfg
[i
].fifo_len
)
731 mac_control
->fifos
[i
].list_info
[l
].list_virt_addr
=
732 tmp_v
+ (k
* lst_size
);
733 mac_control
->fifos
[i
].list_info
[l
].list_phy_addr
=
734 tmp_p
+ (k
* lst_size
);
740 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
741 size
= config
->tx_cfg
[i
].fifo_len
;
742 mac_control
->fifos
[i
].ufo_in_band_v
743 = kcalloc(size
, sizeof(u64
), GFP_KERNEL
);
744 if (!mac_control
->fifos
[i
].ufo_in_band_v
)
746 mem_allocated
+= (size
* sizeof(u64
));
749 /* Allocation and initialization of RXDs in Rings */
751 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
752 if (config
->rx_cfg
[i
].num_rxd
%
753 (rxd_count
[nic
->rxd_mode
] + 1)) {
754 DBG_PRINT(ERR_DBG
, "%s: RxD count of ", dev
->name
);
755 DBG_PRINT(ERR_DBG
, "Ring%d is not a multiple of ",
757 DBG_PRINT(ERR_DBG
, "RxDs per Block");
760 size
+= config
->rx_cfg
[i
].num_rxd
;
761 mac_control
->rings
[i
].block_count
=
762 config
->rx_cfg
[i
].num_rxd
/
763 (rxd_count
[nic
->rxd_mode
] + 1 );
764 mac_control
->rings
[i
].pkt_cnt
= config
->rx_cfg
[i
].num_rxd
-
765 mac_control
->rings
[i
].block_count
;
767 if (nic
->rxd_mode
== RXD_MODE_1
)
768 size
= (size
* (sizeof(struct RxD1
)));
770 size
= (size
* (sizeof(struct RxD3
)));
772 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
773 mac_control
->rings
[i
].rx_curr_get_info
.block_index
= 0;
774 mac_control
->rings
[i
].rx_curr_get_info
.offset
= 0;
775 mac_control
->rings
[i
].rx_curr_get_info
.ring_len
=
776 config
->rx_cfg
[i
].num_rxd
- 1;
777 mac_control
->rings
[i
].rx_curr_put_info
.block_index
= 0;
778 mac_control
->rings
[i
].rx_curr_put_info
.offset
= 0;
779 mac_control
->rings
[i
].rx_curr_put_info
.ring_len
=
780 config
->rx_cfg
[i
].num_rxd
- 1;
781 mac_control
->rings
[i
].nic
= nic
;
782 mac_control
->rings
[i
].ring_no
= i
;
783 mac_control
->rings
[i
].lro
= lro_enable
;
785 blk_cnt
= config
->rx_cfg
[i
].num_rxd
/
786 (rxd_count
[nic
->rxd_mode
] + 1);
787 /* Allocating all the Rx blocks */
788 for (j
= 0; j
< blk_cnt
; j
++) {
789 struct rx_block_info
*rx_blocks
;
792 rx_blocks
= &mac_control
->rings
[i
].rx_blocks
[j
];
793 size
= SIZE_OF_BLOCK
; //size is always page size
794 tmp_v_addr
= pci_alloc_consistent(nic
->pdev
, size
,
796 if (tmp_v_addr
== NULL
) {
798 * In case of failure, free_shared_mem()
799 * is called, which should free any
800 * memory that was alloced till the
803 rx_blocks
->block_virt_addr
= tmp_v_addr
;
806 mem_allocated
+= size
;
807 memset(tmp_v_addr
, 0, size
);
808 rx_blocks
->block_virt_addr
= tmp_v_addr
;
809 rx_blocks
->block_dma_addr
= tmp_p_addr
;
810 rx_blocks
->rxds
= kmalloc(sizeof(struct rxd_info
)*
811 rxd_count
[nic
->rxd_mode
],
813 if (!rx_blocks
->rxds
)
816 (sizeof(struct rxd_info
)* rxd_count
[nic
->rxd_mode
]);
817 for (l
=0; l
<rxd_count
[nic
->rxd_mode
];l
++) {
818 rx_blocks
->rxds
[l
].virt_addr
=
819 rx_blocks
->block_virt_addr
+
820 (rxd_size
[nic
->rxd_mode
] * l
);
821 rx_blocks
->rxds
[l
].dma_addr
=
822 rx_blocks
->block_dma_addr
+
823 (rxd_size
[nic
->rxd_mode
] * l
);
826 /* Interlinking all Rx Blocks */
827 for (j
= 0; j
< blk_cnt
; j
++) {
829 mac_control
->rings
[i
].rx_blocks
[j
].block_virt_addr
;
831 mac_control
->rings
[i
].rx_blocks
[(j
+ 1) %
832 blk_cnt
].block_virt_addr
;
834 mac_control
->rings
[i
].rx_blocks
[j
].block_dma_addr
;
836 mac_control
->rings
[i
].rx_blocks
[(j
+ 1) %
837 blk_cnt
].block_dma_addr
;
839 pre_rxd_blk
= (struct RxD_block
*) tmp_v_addr
;
840 pre_rxd_blk
->reserved_2_pNext_RxD_block
=
841 (unsigned long) tmp_v_addr_next
;
842 pre_rxd_blk
->pNext_RxD_Blk_physical
=
843 (u64
) tmp_p_addr_next
;
846 if (nic
->rxd_mode
== RXD_MODE_3B
) {
848 * Allocation of Storages for buffer addresses in 2BUFF mode
849 * and the buffers as well.
851 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
852 blk_cnt
= config
->rx_cfg
[i
].num_rxd
/
853 (rxd_count
[nic
->rxd_mode
]+ 1);
854 mac_control
->rings
[i
].ba
=
855 kmalloc((sizeof(struct buffAdd
*) * blk_cnt
),
857 if (!mac_control
->rings
[i
].ba
)
859 mem_allocated
+=(sizeof(struct buffAdd
*) * blk_cnt
);
860 for (j
= 0; j
< blk_cnt
; j
++) {
862 mac_control
->rings
[i
].ba
[j
] =
863 kmalloc((sizeof(struct buffAdd
) *
864 (rxd_count
[nic
->rxd_mode
] + 1)),
866 if (!mac_control
->rings
[i
].ba
[j
])
868 mem_allocated
+= (sizeof(struct buffAdd
) * \
869 (rxd_count
[nic
->rxd_mode
] + 1));
870 while (k
!= rxd_count
[nic
->rxd_mode
]) {
871 ba
= &mac_control
->rings
[i
].ba
[j
][k
];
873 ba
->ba_0_org
= (void *) kmalloc
874 (BUF0_LEN
+ ALIGN_SIZE
, GFP_KERNEL
);
878 (BUF0_LEN
+ ALIGN_SIZE
);
879 tmp
= (unsigned long)ba
->ba_0_org
;
881 tmp
&= ~((unsigned long) ALIGN_SIZE
);
882 ba
->ba_0
= (void *) tmp
;
884 ba
->ba_1_org
= (void *) kmalloc
885 (BUF1_LEN
+ ALIGN_SIZE
, GFP_KERNEL
);
889 += (BUF1_LEN
+ ALIGN_SIZE
);
890 tmp
= (unsigned long) ba
->ba_1_org
;
892 tmp
&= ~((unsigned long) ALIGN_SIZE
);
893 ba
->ba_1
= (void *) tmp
;
900 /* Allocation and initialization of Statistics block */
901 size
= sizeof(struct stat_block
);
902 mac_control
->stats_mem
= pci_alloc_consistent
903 (nic
->pdev
, size
, &mac_control
->stats_mem_phy
);
905 if (!mac_control
->stats_mem
) {
907 * In case of failure, free_shared_mem() is called, which
908 * should free any memory that was alloced till the
913 mem_allocated
+= size
;
914 mac_control
->stats_mem_sz
= size
;
916 tmp_v_addr
= mac_control
->stats_mem
;
917 mac_control
->stats_info
= (struct stat_block
*) tmp_v_addr
;
918 memset(tmp_v_addr
, 0, size
);
919 DBG_PRINT(INIT_DBG
, "%s:Ring Mem PHY: 0x%llx\n", dev
->name
,
920 (unsigned long long) tmp_p_addr
);
921 mac_control
->stats_info
->sw_stat
.mem_allocated
+= mem_allocated
;
926 * free_shared_mem - Free the allocated Memory
927 * @nic: Device private variable.
928 * Description: This function is to free all memory locations allocated by
929 * the init_shared_mem() function and return it to the kernel.
932 static void free_shared_mem(struct s2io_nic
*nic
)
934 int i
, j
, blk_cnt
, size
;
936 dma_addr_t tmp_p_addr
;
937 struct mac_info
*mac_control
;
938 struct config_param
*config
;
939 int lst_size
, lst_per_page
;
940 struct net_device
*dev
;
948 mac_control
= &nic
->mac_control
;
949 config
= &nic
->config
;
951 lst_size
= (sizeof(struct TxD
) * config
->max_txds
);
952 lst_per_page
= PAGE_SIZE
/ lst_size
;
954 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
955 page_num
= TXD_MEM_PAGE_CNT(config
->tx_cfg
[i
].fifo_len
,
957 for (j
= 0; j
< page_num
; j
++) {
958 int mem_blks
= (j
* lst_per_page
);
959 if (!mac_control
->fifos
[i
].list_info
)
961 if (!mac_control
->fifos
[i
].list_info
[mem_blks
].
964 pci_free_consistent(nic
->pdev
, PAGE_SIZE
,
965 mac_control
->fifos
[i
].
968 mac_control
->fifos
[i
].
971 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
974 /* If we got a zero DMA address during allocation,
977 if (mac_control
->zerodma_virt_addr
) {
978 pci_free_consistent(nic
->pdev
, PAGE_SIZE
,
979 mac_control
->zerodma_virt_addr
,
982 "%s: Freeing TxDL with zero DMA addr. ",
984 DBG_PRINT(INIT_DBG
, "Virtual address %p\n",
985 mac_control
->zerodma_virt_addr
);
986 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
989 kfree(mac_control
->fifos
[i
].list_info
);
990 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+=
991 (nic
->config
.tx_cfg
[i
].fifo_len
*sizeof(struct list_info_hold
));
994 size
= SIZE_OF_BLOCK
;
995 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
996 blk_cnt
= mac_control
->rings
[i
].block_count
;
997 for (j
= 0; j
< blk_cnt
; j
++) {
998 tmp_v_addr
= mac_control
->rings
[i
].rx_blocks
[j
].
1000 tmp_p_addr
= mac_control
->rings
[i
].rx_blocks
[j
].
1002 if (tmp_v_addr
== NULL
)
1004 pci_free_consistent(nic
->pdev
, size
,
1005 tmp_v_addr
, tmp_p_addr
);
1006 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+= size
;
1007 kfree(mac_control
->rings
[i
].rx_blocks
[j
].rxds
);
1008 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+=
1009 ( sizeof(struct rxd_info
)* rxd_count
[nic
->rxd_mode
]);
1013 if (nic
->rxd_mode
== RXD_MODE_3B
) {
1014 /* Freeing buffer storage addresses in 2BUFF mode. */
1015 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
1016 blk_cnt
= config
->rx_cfg
[i
].num_rxd
/
1017 (rxd_count
[nic
->rxd_mode
] + 1);
1018 for (j
= 0; j
< blk_cnt
; j
++) {
1020 if (!mac_control
->rings
[i
].ba
[j
])
1022 while (k
!= rxd_count
[nic
->rxd_mode
]) {
1023 struct buffAdd
*ba
=
1024 &mac_control
->rings
[i
].ba
[j
][k
];
1025 kfree(ba
->ba_0_org
);
1026 nic
->mac_control
.stats_info
->sw_stat
.\
1027 mem_freed
+= (BUF0_LEN
+ ALIGN_SIZE
);
1028 kfree(ba
->ba_1_org
);
1029 nic
->mac_control
.stats_info
->sw_stat
.\
1030 mem_freed
+= (BUF1_LEN
+ ALIGN_SIZE
);
1033 kfree(mac_control
->rings
[i
].ba
[j
]);
1034 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+=
1035 (sizeof(struct buffAdd
) *
1036 (rxd_count
[nic
->rxd_mode
] + 1));
1038 kfree(mac_control
->rings
[i
].ba
);
1039 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+=
1040 (sizeof(struct buffAdd
*) * blk_cnt
);
1044 for (i
= 0; i
< nic
->config
.tx_fifo_num
; i
++) {
1045 if (mac_control
->fifos
[i
].ufo_in_band_v
) {
1046 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
1047 += (config
->tx_cfg
[i
].fifo_len
* sizeof(u64
));
1048 kfree(mac_control
->fifos
[i
].ufo_in_band_v
);
1052 if (mac_control
->stats_mem
) {
1053 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+=
1054 mac_control
->stats_mem_sz
;
1055 pci_free_consistent(nic
->pdev
,
1056 mac_control
->stats_mem_sz
,
1057 mac_control
->stats_mem
,
1058 mac_control
->stats_mem_phy
);
1063 * s2io_verify_pci_mode -
1066 static int s2io_verify_pci_mode(struct s2io_nic
*nic
)
1068 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
1069 register u64 val64
= 0;
1072 val64
= readq(&bar0
->pci_mode
);
1073 mode
= (u8
)GET_PCI_MODE(val64
);
1075 if ( val64
& PCI_MODE_UNKNOWN_MODE
)
1076 return -1; /* Unknown PCI mode */
1080 #define NEC_VENID 0x1033
1081 #define NEC_DEVID 0x0125
1082 static int s2io_on_nec_bridge(struct pci_dev
*s2io_pdev
)
1084 struct pci_dev
*tdev
= NULL
;
1085 while ((tdev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, tdev
)) != NULL
) {
1086 if (tdev
->vendor
== NEC_VENID
&& tdev
->device
== NEC_DEVID
) {
1087 if (tdev
->bus
== s2io_pdev
->bus
->parent
) {
1096 static int bus_speed
[8] = {33, 133, 133, 200, 266, 133, 200, 266};
1098 * s2io_print_pci_mode -
1100 static int s2io_print_pci_mode(struct s2io_nic
*nic
)
1102 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
1103 register u64 val64
= 0;
1105 struct config_param
*config
= &nic
->config
;
1107 val64
= readq(&bar0
->pci_mode
);
1108 mode
= (u8
)GET_PCI_MODE(val64
);
1110 if ( val64
& PCI_MODE_UNKNOWN_MODE
)
1111 return -1; /* Unknown PCI mode */
1113 config
->bus_speed
= bus_speed
[mode
];
1115 if (s2io_on_nec_bridge(nic
->pdev
)) {
1116 DBG_PRINT(ERR_DBG
, "%s: Device is on PCI-E bus\n",
1121 if (val64
& PCI_MODE_32_BITS
) {
1122 DBG_PRINT(ERR_DBG
, "%s: Device is on 32 bit ", nic
->dev
->name
);
1124 DBG_PRINT(ERR_DBG
, "%s: Device is on 64 bit ", nic
->dev
->name
);
1128 case PCI_MODE_PCI_33
:
1129 DBG_PRINT(ERR_DBG
, "33MHz PCI bus\n");
1131 case PCI_MODE_PCI_66
:
1132 DBG_PRINT(ERR_DBG
, "66MHz PCI bus\n");
1134 case PCI_MODE_PCIX_M1_66
:
1135 DBG_PRINT(ERR_DBG
, "66MHz PCIX(M1) bus\n");
1137 case PCI_MODE_PCIX_M1_100
:
1138 DBG_PRINT(ERR_DBG
, "100MHz PCIX(M1) bus\n");
1140 case PCI_MODE_PCIX_M1_133
:
1141 DBG_PRINT(ERR_DBG
, "133MHz PCIX(M1) bus\n");
1143 case PCI_MODE_PCIX_M2_66
:
1144 DBG_PRINT(ERR_DBG
, "133MHz PCIX(M2) bus\n");
1146 case PCI_MODE_PCIX_M2_100
:
1147 DBG_PRINT(ERR_DBG
, "200MHz PCIX(M2) bus\n");
1149 case PCI_MODE_PCIX_M2_133
:
1150 DBG_PRINT(ERR_DBG
, "266MHz PCIX(M2) bus\n");
1153 return -1; /* Unsupported bus speed */
1160 * init_tti - Initialization transmit traffic interrupt scheme
1161 * @nic: device private variable
1162 * @link: link status (UP/DOWN) used to enable/disable continuous
1163 * transmit interrupts
1164 * Description: The function configures transmit traffic interrupts
1165 * Return Value: SUCCESS on success and
1169 static int init_tti(struct s2io_nic
*nic
, int link
)
1171 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
1172 register u64 val64
= 0;
1174 struct config_param
*config
;
1176 config
= &nic
->config
;
1178 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
1180 * TTI Initialization. Default Tx timer gets us about
1181 * 250 interrupts per sec. Continuous interrupts are enabled
1184 if (nic
->device_type
== XFRAME_II_DEVICE
) {
1185 int count
= (nic
->config
.bus_speed
* 125)/2;
1186 val64
= TTI_DATA1_MEM_TX_TIMER_VAL(count
);
1188 val64
= TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1190 val64
|= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1191 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1192 TTI_DATA1_MEM_TX_URNG_C(0x30) |
1193 TTI_DATA1_MEM_TX_TIMER_AC_EN
;
1195 if (use_continuous_tx_intrs
&& (link
== LINK_UP
))
1196 val64
|= TTI_DATA1_MEM_TX_TIMER_CI_EN
;
1197 writeq(val64
, &bar0
->tti_data1_mem
);
1199 if (nic
->config
.intr_type
== MSI_X
) {
1200 val64
= TTI_DATA2_MEM_TX_UFC_A(0x10) |
1201 TTI_DATA2_MEM_TX_UFC_B(0x100) |
1202 TTI_DATA2_MEM_TX_UFC_C(0x200) |
1203 TTI_DATA2_MEM_TX_UFC_D(0x300);
1205 if ((nic
->config
.tx_steering_type
==
1206 TX_DEFAULT_STEERING
) &&
1207 (config
->tx_fifo_num
> 1) &&
1208 (i
>= nic
->udp_fifo_idx
) &&
1209 (i
< (nic
->udp_fifo_idx
+
1210 nic
->total_udp_fifos
)))
1211 val64
= TTI_DATA2_MEM_TX_UFC_A(0x50) |
1212 TTI_DATA2_MEM_TX_UFC_B(0x80) |
1213 TTI_DATA2_MEM_TX_UFC_C(0x100) |
1214 TTI_DATA2_MEM_TX_UFC_D(0x120);
1216 val64
= TTI_DATA2_MEM_TX_UFC_A(0x10) |
1217 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1218 TTI_DATA2_MEM_TX_UFC_C(0x40) |
1219 TTI_DATA2_MEM_TX_UFC_D(0x80);
1222 writeq(val64
, &bar0
->tti_data2_mem
);
1224 val64
= TTI_CMD_MEM_WE
| TTI_CMD_MEM_STROBE_NEW_CMD
|
1225 TTI_CMD_MEM_OFFSET(i
);
1226 writeq(val64
, &bar0
->tti_command_mem
);
1228 if (wait_for_cmd_complete(&bar0
->tti_command_mem
,
1229 TTI_CMD_MEM_STROBE_NEW_CMD
, S2IO_BIT_RESET
) != SUCCESS
)
1237 * init_nic - Initialization of hardware
1238 * @nic: device private variable
1239 * Description: The function sequentially configures every block
1240 * of the H/W from their reset values.
1241 * Return Value: SUCCESS on success and
1242 * '-1' on failure (endian settings incorrect).
1245 static int init_nic(struct s2io_nic
*nic
)
1247 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
1248 struct net_device
*dev
= nic
->dev
;
1249 register u64 val64
= 0;
1253 struct mac_info
*mac_control
;
1254 struct config_param
*config
;
1256 unsigned long long mem_share
;
1259 mac_control
= &nic
->mac_control
;
1260 config
= &nic
->config
;
1262 /* to set the swapper controle on the card */
1263 if(s2io_set_swapper(nic
)) {
1264 DBG_PRINT(ERR_DBG
,"ERROR: Setting Swapper failed\n");
1269 * Herc requires EOI to be removed from reset before XGXS, so..
1271 if (nic
->device_type
& XFRAME_II_DEVICE
) {
1272 val64
= 0xA500000000ULL
;
1273 writeq(val64
, &bar0
->sw_reset
);
1275 val64
= readq(&bar0
->sw_reset
);
1278 /* Remove XGXS from reset state */
1280 writeq(val64
, &bar0
->sw_reset
);
1282 val64
= readq(&bar0
->sw_reset
);
1284 /* Ensure that it's safe to access registers by checking
1285 * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1287 if (nic
->device_type
== XFRAME_II_DEVICE
) {
1288 for (i
= 0; i
< 50; i
++) {
1289 val64
= readq(&bar0
->adapter_status
);
1290 if (!(val64
& ADAPTER_STATUS_RIC_RUNNING
))
1298 /* Enable Receiving broadcasts */
1299 add
= &bar0
->mac_cfg
;
1300 val64
= readq(&bar0
->mac_cfg
);
1301 val64
|= MAC_RMAC_BCAST_ENABLE
;
1302 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1303 writel((u32
) val64
, add
);
1304 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1305 writel((u32
) (val64
>> 32), (add
+ 4));
1307 /* Read registers in all blocks */
1308 val64
= readq(&bar0
->mac_int_mask
);
1309 val64
= readq(&bar0
->mc_int_mask
);
1310 val64
= readq(&bar0
->xgxs_int_mask
);
1314 writeq(vBIT(val64
, 2, 14), &bar0
->rmac_max_pyld_len
);
1316 if (nic
->device_type
& XFRAME_II_DEVICE
) {
1317 while (herc_act_dtx_cfg
[dtx_cnt
] != END_SIGN
) {
1318 SPECIAL_REG_WRITE(herc_act_dtx_cfg
[dtx_cnt
],
1319 &bar0
->dtx_control
, UF
);
1321 msleep(1); /* Necessary!! */
1325 while (xena_dtx_cfg
[dtx_cnt
] != END_SIGN
) {
1326 SPECIAL_REG_WRITE(xena_dtx_cfg
[dtx_cnt
],
1327 &bar0
->dtx_control
, UF
);
1328 val64
= readq(&bar0
->dtx_control
);
1333 /* Tx DMA Initialization */
1335 writeq(val64
, &bar0
->tx_fifo_partition_0
);
1336 writeq(val64
, &bar0
->tx_fifo_partition_1
);
1337 writeq(val64
, &bar0
->tx_fifo_partition_2
);
1338 writeq(val64
, &bar0
->tx_fifo_partition_3
);
1341 for (i
= 0, j
= 0; i
< config
->tx_fifo_num
; i
++) {
1343 vBIT(config
->tx_cfg
[i
].fifo_len
- 1, ((j
* 32) + 19),
1344 13) | vBIT(config
->tx_cfg
[i
].fifo_priority
,
1347 if (i
== (config
->tx_fifo_num
- 1)) {
1354 writeq(val64
, &bar0
->tx_fifo_partition_0
);
1359 writeq(val64
, &bar0
->tx_fifo_partition_1
);
1364 writeq(val64
, &bar0
->tx_fifo_partition_2
);
1369 writeq(val64
, &bar0
->tx_fifo_partition_3
);
1380 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1381 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1383 if ((nic
->device_type
== XFRAME_I_DEVICE
) &&
1384 (nic
->pdev
->revision
< 4))
1385 writeq(PCC_ENABLE_FOUR
, &bar0
->pcc_enable
);
1387 val64
= readq(&bar0
->tx_fifo_partition_0
);
1388 DBG_PRINT(INIT_DBG
, "Fifo partition at: 0x%p is: 0x%llx\n",
1389 &bar0
->tx_fifo_partition_0
, (unsigned long long) val64
);
1392 * Initialization of Tx_PA_CONFIG register to ignore packet
1393 * integrity checking.
1395 val64
= readq(&bar0
->tx_pa_cfg
);
1396 val64
|= TX_PA_CFG_IGNORE_FRM_ERR
| TX_PA_CFG_IGNORE_SNAP_OUI
|
1397 TX_PA_CFG_IGNORE_LLC_CTRL
| TX_PA_CFG_IGNORE_L2_ERR
;
1398 writeq(val64
, &bar0
->tx_pa_cfg
);
1400 /* Rx DMA intialization. */
1402 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
1404 vBIT(config
->rx_cfg
[i
].ring_priority
, (5 + (i
* 8)),
1407 writeq(val64
, &bar0
->rx_queue_priority
);
1410 * Allocating equal share of memory to all the
1414 if (nic
->device_type
& XFRAME_II_DEVICE
)
1419 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
1422 mem_share
= (mem_size
/ config
->rx_ring_num
+
1423 mem_size
% config
->rx_ring_num
);
1424 val64
|= RX_QUEUE_CFG_Q0_SZ(mem_share
);
1427 mem_share
= (mem_size
/ config
->rx_ring_num
);
1428 val64
|= RX_QUEUE_CFG_Q1_SZ(mem_share
);
1431 mem_share
= (mem_size
/ config
->rx_ring_num
);
1432 val64
|= RX_QUEUE_CFG_Q2_SZ(mem_share
);
1435 mem_share
= (mem_size
/ config
->rx_ring_num
);
1436 val64
|= RX_QUEUE_CFG_Q3_SZ(mem_share
);
1439 mem_share
= (mem_size
/ config
->rx_ring_num
);
1440 val64
|= RX_QUEUE_CFG_Q4_SZ(mem_share
);
1443 mem_share
= (mem_size
/ config
->rx_ring_num
);
1444 val64
|= RX_QUEUE_CFG_Q5_SZ(mem_share
);
1447 mem_share
= (mem_size
/ config
->rx_ring_num
);
1448 val64
|= RX_QUEUE_CFG_Q6_SZ(mem_share
);
1451 mem_share
= (mem_size
/ config
->rx_ring_num
);
1452 val64
|= RX_QUEUE_CFG_Q7_SZ(mem_share
);
1456 writeq(val64
, &bar0
->rx_queue_cfg
);
1459 * Filling Tx round robin registers
1460 * as per the number of FIFOs for equal scheduling priority
1462 switch (config
->tx_fifo_num
) {
1465 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1466 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1467 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1468 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1469 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1472 val64
= 0x0001000100010001ULL
;
1473 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1474 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1475 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1476 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1477 val64
= 0x0001000100000000ULL
;
1478 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1481 val64
= 0x0001020001020001ULL
;
1482 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1483 val64
= 0x0200010200010200ULL
;
1484 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1485 val64
= 0x0102000102000102ULL
;
1486 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1487 val64
= 0x0001020001020001ULL
;
1488 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1489 val64
= 0x0200010200000000ULL
;
1490 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1493 val64
= 0x0001020300010203ULL
;
1494 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1495 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1496 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1497 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1498 val64
= 0x0001020300000000ULL
;
1499 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1502 val64
= 0x0001020304000102ULL
;
1503 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1504 val64
= 0x0304000102030400ULL
;
1505 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1506 val64
= 0x0102030400010203ULL
;
1507 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1508 val64
= 0x0400010203040001ULL
;
1509 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1510 val64
= 0x0203040000000000ULL
;
1511 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1514 val64
= 0x0001020304050001ULL
;
1515 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1516 val64
= 0x0203040500010203ULL
;
1517 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1518 val64
= 0x0405000102030405ULL
;
1519 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1520 val64
= 0x0001020304050001ULL
;
1521 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1522 val64
= 0x0203040500000000ULL
;
1523 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1526 val64
= 0x0001020304050600ULL
;
1527 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1528 val64
= 0x0102030405060001ULL
;
1529 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1530 val64
= 0x0203040506000102ULL
;
1531 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1532 val64
= 0x0304050600010203ULL
;
1533 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1534 val64
= 0x0405060000000000ULL
;
1535 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1538 val64
= 0x0001020304050607ULL
;
1539 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1540 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1541 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1542 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1543 val64
= 0x0001020300000000ULL
;
1544 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1548 /* Enable all configured Tx FIFO partitions */
1549 val64
= readq(&bar0
->tx_fifo_partition_0
);
1550 val64
|= (TX_FIFO_PARTITION_EN
);
1551 writeq(val64
, &bar0
->tx_fifo_partition_0
);
1553 /* Filling the Rx round robin registers as per the
1554 * number of Rings and steering based on QoS with
1557 switch (config
->rx_ring_num
) {
1560 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1561 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1562 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1563 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1564 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1566 val64
= 0x8080808080808080ULL
;
1567 writeq(val64
, &bar0
->rts_qos_steering
);
1570 val64
= 0x0001000100010001ULL
;
1571 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1572 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1573 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1574 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1575 val64
= 0x0001000100000000ULL
;
1576 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1578 val64
= 0x8080808040404040ULL
;
1579 writeq(val64
, &bar0
->rts_qos_steering
);
1582 val64
= 0x0001020001020001ULL
;
1583 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1584 val64
= 0x0200010200010200ULL
;
1585 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1586 val64
= 0x0102000102000102ULL
;
1587 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1588 val64
= 0x0001020001020001ULL
;
1589 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1590 val64
= 0x0200010200000000ULL
;
1591 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1593 val64
= 0x8080804040402020ULL
;
1594 writeq(val64
, &bar0
->rts_qos_steering
);
1597 val64
= 0x0001020300010203ULL
;
1598 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1599 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1600 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1601 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1602 val64
= 0x0001020300000000ULL
;
1603 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1605 val64
= 0x8080404020201010ULL
;
1606 writeq(val64
, &bar0
->rts_qos_steering
);
1609 val64
= 0x0001020304000102ULL
;
1610 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1611 val64
= 0x0304000102030400ULL
;
1612 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1613 val64
= 0x0102030400010203ULL
;
1614 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1615 val64
= 0x0400010203040001ULL
;
1616 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1617 val64
= 0x0203040000000000ULL
;
1618 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1620 val64
= 0x8080404020201008ULL
;
1621 writeq(val64
, &bar0
->rts_qos_steering
);
1624 val64
= 0x0001020304050001ULL
;
1625 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1626 val64
= 0x0203040500010203ULL
;
1627 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1628 val64
= 0x0405000102030405ULL
;
1629 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1630 val64
= 0x0001020304050001ULL
;
1631 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1632 val64
= 0x0203040500000000ULL
;
1633 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1635 val64
= 0x8080404020100804ULL
;
1636 writeq(val64
, &bar0
->rts_qos_steering
);
1639 val64
= 0x0001020304050600ULL
;
1640 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1641 val64
= 0x0102030405060001ULL
;
1642 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1643 val64
= 0x0203040506000102ULL
;
1644 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1645 val64
= 0x0304050600010203ULL
;
1646 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1647 val64
= 0x0405060000000000ULL
;
1648 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1650 val64
= 0x8080402010080402ULL
;
1651 writeq(val64
, &bar0
->rts_qos_steering
);
1654 val64
= 0x0001020304050607ULL
;
1655 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1656 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1657 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1658 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1659 val64
= 0x0001020300000000ULL
;
1660 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1662 val64
= 0x8040201008040201ULL
;
1663 writeq(val64
, &bar0
->rts_qos_steering
);
1669 for (i
= 0; i
< 8; i
++)
1670 writeq(val64
, &bar0
->rts_frm_len_n
[i
]);
1672 /* Set the default rts frame length for the rings configured */
1673 val64
= MAC_RTS_FRM_LEN_SET(dev
->mtu
+22);
1674 for (i
= 0 ; i
< config
->rx_ring_num
; i
++)
1675 writeq(val64
, &bar0
->rts_frm_len_n
[i
]);
1677 /* Set the frame length for the configured rings
1678 * desired by the user
1680 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
1681 /* If rts_frm_len[i] == 0 then it is assumed that user not
1682 * specified frame length steering.
1683 * If the user provides the frame length then program
1684 * the rts_frm_len register for those values or else
1685 * leave it as it is.
1687 if (rts_frm_len
[i
] != 0) {
1688 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len
[i
]),
1689 &bar0
->rts_frm_len_n
[i
]);
1693 /* Disable differentiated services steering logic */
1694 for (i
= 0; i
< 64; i
++) {
1695 if (rts_ds_steer(nic
, i
, 0) == FAILURE
) {
1696 DBG_PRINT(ERR_DBG
, "%s: failed rts ds steering",
1698 DBG_PRINT(ERR_DBG
, "set on codepoint %d\n", i
);
1703 /* Program statistics memory */
1704 writeq(mac_control
->stats_mem_phy
, &bar0
->stat_addr
);
1706 if (nic
->device_type
== XFRAME_II_DEVICE
) {
1707 val64
= STAT_BC(0x320);
1708 writeq(val64
, &bar0
->stat_byte_cnt
);
1712 * Initializing the sampling rate for the device to calculate the
1713 * bandwidth utilization.
1715 val64
= MAC_TX_LINK_UTIL_VAL(tmac_util_period
) |
1716 MAC_RX_LINK_UTIL_VAL(rmac_util_period
);
1717 writeq(val64
, &bar0
->mac_link_util
);
1720 * Initializing the Transmit and Receive Traffic Interrupt
1724 /* Initialize TTI */
1725 if (SUCCESS
!= init_tti(nic
, nic
->last_link_state
))
1728 /* RTI Initialization */
1729 if (nic
->device_type
== XFRAME_II_DEVICE
) {
1731 * Programmed to generate Apprx 500 Intrs per
1734 int count
= (nic
->config
.bus_speed
* 125)/4;
1735 val64
= RTI_DATA1_MEM_RX_TIMER_VAL(count
);
1737 val64
= RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1738 val64
|= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1739 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1740 RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN
;
1742 writeq(val64
, &bar0
->rti_data1_mem
);
1744 val64
= RTI_DATA2_MEM_RX_UFC_A(0x1) |
1745 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1746 if (nic
->config
.intr_type
== MSI_X
)
1747 val64
|= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1748 RTI_DATA2_MEM_RX_UFC_D(0x40));
1750 val64
|= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1751 RTI_DATA2_MEM_RX_UFC_D(0x80));
1752 writeq(val64
, &bar0
->rti_data2_mem
);
1754 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
1755 val64
= RTI_CMD_MEM_WE
| RTI_CMD_MEM_STROBE_NEW_CMD
1756 | RTI_CMD_MEM_OFFSET(i
);
1757 writeq(val64
, &bar0
->rti_command_mem
);
1760 * Once the operation completes, the Strobe bit of the
1761 * command register will be reset. We poll for this
1762 * particular condition. We wait for a maximum of 500ms
1763 * for the operation to complete, if it's not complete
1764 * by then we return error.
1768 val64
= readq(&bar0
->rti_command_mem
);
1769 if (!(val64
& RTI_CMD_MEM_STROBE_NEW_CMD
))
1773 DBG_PRINT(ERR_DBG
, "%s: RTI init Failed\n",
1783 * Initializing proper values as Pause threshold into all
1784 * the 8 Queues on Rx side.
1786 writeq(0xffbbffbbffbbffbbULL
, &bar0
->mc_pause_thresh_q0q3
);
1787 writeq(0xffbbffbbffbbffbbULL
, &bar0
->mc_pause_thresh_q4q7
);
1789 /* Disable RMAC PAD STRIPPING */
1790 add
= &bar0
->mac_cfg
;
1791 val64
= readq(&bar0
->mac_cfg
);
1792 val64
&= ~(MAC_CFG_RMAC_STRIP_PAD
);
1793 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1794 writel((u32
) (val64
), add
);
1795 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1796 writel((u32
) (val64
>> 32), (add
+ 4));
1797 val64
= readq(&bar0
->mac_cfg
);
1799 /* Enable FCS stripping by adapter */
1800 add
= &bar0
->mac_cfg
;
1801 val64
= readq(&bar0
->mac_cfg
);
1802 val64
|= MAC_CFG_RMAC_STRIP_FCS
;
1803 if (nic
->device_type
== XFRAME_II_DEVICE
)
1804 writeq(val64
, &bar0
->mac_cfg
);
1806 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1807 writel((u32
) (val64
), add
);
1808 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1809 writel((u32
) (val64
>> 32), (add
+ 4));
1813 * Set the time value to be inserted in the pause frame
1814 * generated by xena.
1816 val64
= readq(&bar0
->rmac_pause_cfg
);
1817 val64
&= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1818 val64
|= RMAC_PAUSE_HG_PTIME(nic
->mac_control
.rmac_pause_time
);
1819 writeq(val64
, &bar0
->rmac_pause_cfg
);
1822 * Set the Threshold Limit for Generating the pause frame
1823 * If the amount of data in any Queue exceeds ratio of
1824 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1825 * pause frame is generated
1828 for (i
= 0; i
< 4; i
++) {
1830 (((u64
) 0xFF00 | nic
->mac_control
.
1831 mc_pause_threshold_q0q3
)
1834 writeq(val64
, &bar0
->mc_pause_thresh_q0q3
);
1837 for (i
= 0; i
< 4; i
++) {
1839 (((u64
) 0xFF00 | nic
->mac_control
.
1840 mc_pause_threshold_q4q7
)
1843 writeq(val64
, &bar0
->mc_pause_thresh_q4q7
);
1846 * TxDMA will stop Read request if the number of read split has
1847 * exceeded the limit pointed by shared_splits
1849 val64
= readq(&bar0
->pic_control
);
1850 val64
|= PIC_CNTL_SHARED_SPLITS(shared_splits
);
1851 writeq(val64
, &bar0
->pic_control
);
1853 if (nic
->config
.bus_speed
== 266) {
1854 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN
, &bar0
->txreqtimeout
);
1855 writeq(0x0, &bar0
->read_retry_delay
);
1856 writeq(0x0, &bar0
->write_retry_delay
);
1860 * Programming the Herc to split every write transaction
1861 * that does not start on an ADB to reduce disconnects.
1863 if (nic
->device_type
== XFRAME_II_DEVICE
) {
1864 val64
= FAULT_BEHAVIOUR
| EXT_REQ_EN
|
1865 MISC_LINK_STABILITY_PRD(3);
1866 writeq(val64
, &bar0
->misc_control
);
1867 val64
= readq(&bar0
->pic_control2
);
1868 val64
&= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
1869 writeq(val64
, &bar0
->pic_control2
);
1871 if (strstr(nic
->product_name
, "CX4")) {
1872 val64
= TMAC_AVG_IPG(0x17);
1873 writeq(val64
, &bar0
->tmac_avg_ipg
);
1878 #define LINK_UP_DOWN_INTERRUPT 1
1879 #define MAC_RMAC_ERR_TIMER 2
1881 static int s2io_link_fault_indication(struct s2io_nic
*nic
)
1883 if (nic
->device_type
== XFRAME_II_DEVICE
)
1884 return LINK_UP_DOWN_INTERRUPT
;
1886 return MAC_RMAC_ERR_TIMER
;
1890 * do_s2io_write_bits - update alarm bits in alarm register
1891 * @value: alarm bits
1892 * @flag: interrupt status
1893 * @addr: address value
1894 * Description: update alarm bits in alarm register
1898 static void do_s2io_write_bits(u64 value
, int flag
, void __iomem
*addr
)
1902 temp64
= readq(addr
);
1904 if(flag
== ENABLE_INTRS
)
1905 temp64
&= ~((u64
) value
);
1907 temp64
|= ((u64
) value
);
1908 writeq(temp64
, addr
);
1911 static void en_dis_err_alarms(struct s2io_nic
*nic
, u16 mask
, int flag
)
1913 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
1914 register u64 gen_int_mask
= 0;
1917 writeq(DISABLE_ALL_INTRS
, &bar0
->general_int_mask
);
1918 if (mask
& TX_DMA_INTR
) {
1920 gen_int_mask
|= TXDMA_INT_M
;
1922 do_s2io_write_bits(TXDMA_TDA_INT
| TXDMA_PFC_INT
|
1923 TXDMA_PCC_INT
| TXDMA_TTI_INT
|
1924 TXDMA_LSO_INT
| TXDMA_TPA_INT
|
1925 TXDMA_SM_INT
, flag
, &bar0
->txdma_int_mask
);
1927 do_s2io_write_bits(PFC_ECC_DB_ERR
| PFC_SM_ERR_ALARM
|
1928 PFC_MISC_0_ERR
| PFC_MISC_1_ERR
|
1929 PFC_PCIX_ERR
| PFC_ECC_SG_ERR
, flag
,
1930 &bar0
->pfc_err_mask
);
1932 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR
| TDA_SM0_ERR_ALARM
|
1933 TDA_SM1_ERR_ALARM
| TDA_Fn_ECC_SG_ERR
|
1934 TDA_PCIX_ERR
, flag
, &bar0
->tda_err_mask
);
1936 do_s2io_write_bits(PCC_FB_ECC_DB_ERR
| PCC_TXB_ECC_DB_ERR
|
1937 PCC_SM_ERR_ALARM
| PCC_WR_ERR_ALARM
|
1938 PCC_N_SERR
| PCC_6_COF_OV_ERR
|
1939 PCC_7_COF_OV_ERR
| PCC_6_LSO_OV_ERR
|
1940 PCC_7_LSO_OV_ERR
| PCC_FB_ECC_SG_ERR
|
1941 PCC_TXB_ECC_SG_ERR
, flag
, &bar0
->pcc_err_mask
);
1943 do_s2io_write_bits(TTI_SM_ERR_ALARM
| TTI_ECC_SG_ERR
|
1944 TTI_ECC_DB_ERR
, flag
, &bar0
->tti_err_mask
);
1946 do_s2io_write_bits(LSO6_ABORT
| LSO7_ABORT
|
1947 LSO6_SM_ERR_ALARM
| LSO7_SM_ERR_ALARM
|
1948 LSO6_SEND_OFLOW
| LSO7_SEND_OFLOW
,
1949 flag
, &bar0
->lso_err_mask
);
1951 do_s2io_write_bits(TPA_SM_ERR_ALARM
| TPA_TX_FRM_DROP
,
1952 flag
, &bar0
->tpa_err_mask
);
1954 do_s2io_write_bits(SM_SM_ERR_ALARM
, flag
, &bar0
->sm_err_mask
);
1958 if (mask
& TX_MAC_INTR
) {
1959 gen_int_mask
|= TXMAC_INT_M
;
1960 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT
, flag
,
1961 &bar0
->mac_int_mask
);
1962 do_s2io_write_bits(TMAC_TX_BUF_OVRN
| TMAC_TX_SM_ERR
|
1963 TMAC_ECC_SG_ERR
| TMAC_ECC_DB_ERR
|
1964 TMAC_DESC_ECC_SG_ERR
| TMAC_DESC_ECC_DB_ERR
,
1965 flag
, &bar0
->mac_tmac_err_mask
);
1968 if (mask
& TX_XGXS_INTR
) {
1969 gen_int_mask
|= TXXGXS_INT_M
;
1970 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS
, flag
,
1971 &bar0
->xgxs_int_mask
);
1972 do_s2io_write_bits(TXGXS_ESTORE_UFLOW
| TXGXS_TX_SM_ERR
|
1973 TXGXS_ECC_SG_ERR
| TXGXS_ECC_DB_ERR
,
1974 flag
, &bar0
->xgxs_txgxs_err_mask
);
1977 if (mask
& RX_DMA_INTR
) {
1978 gen_int_mask
|= RXDMA_INT_M
;
1979 do_s2io_write_bits(RXDMA_INT_RC_INT_M
| RXDMA_INT_RPA_INT_M
|
1980 RXDMA_INT_RDA_INT_M
| RXDMA_INT_RTI_INT_M
,
1981 flag
, &bar0
->rxdma_int_mask
);
1982 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR
| RC_FTC_ECC_DB_ERR
|
1983 RC_PRCn_SM_ERR_ALARM
| RC_FTC_SM_ERR_ALARM
|
1984 RC_PRCn_ECC_SG_ERR
| RC_FTC_ECC_SG_ERR
|
1985 RC_RDA_FAIL_WR_Rn
, flag
, &bar0
->rc_err_mask
);
1986 do_s2io_write_bits(PRC_PCI_AB_RD_Rn
| PRC_PCI_AB_WR_Rn
|
1987 PRC_PCI_AB_F_WR_Rn
| PRC_PCI_DP_RD_Rn
|
1988 PRC_PCI_DP_WR_Rn
| PRC_PCI_DP_F_WR_Rn
, flag
,
1989 &bar0
->prc_pcix_err_mask
);
1990 do_s2io_write_bits(RPA_SM_ERR_ALARM
| RPA_CREDIT_ERR
|
1991 RPA_ECC_SG_ERR
| RPA_ECC_DB_ERR
, flag
,
1992 &bar0
->rpa_err_mask
);
1993 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR
| RDA_FRM_ECC_DB_N_AERR
|
1994 RDA_SM1_ERR_ALARM
| RDA_SM0_ERR_ALARM
|
1995 RDA_RXD_ECC_DB_SERR
| RDA_RXDn_ECC_SG_ERR
|
1996 RDA_FRM_ECC_SG_ERR
| RDA_MISC_ERR
|RDA_PCIX_ERR
,
1997 flag
, &bar0
->rda_err_mask
);
1998 do_s2io_write_bits(RTI_SM_ERR_ALARM
|
1999 RTI_ECC_SG_ERR
| RTI_ECC_DB_ERR
,
2000 flag
, &bar0
->rti_err_mask
);
2003 if (mask
& RX_MAC_INTR
) {
2004 gen_int_mask
|= RXMAC_INT_M
;
2005 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT
, flag
,
2006 &bar0
->mac_int_mask
);
2007 interruptible
= RMAC_RX_BUFF_OVRN
| RMAC_RX_SM_ERR
|
2008 RMAC_UNUSED_INT
| RMAC_SINGLE_ECC_ERR
|
2009 RMAC_DOUBLE_ECC_ERR
;
2010 if (s2io_link_fault_indication(nic
) == MAC_RMAC_ERR_TIMER
)
2011 interruptible
|= RMAC_LINK_STATE_CHANGE_INT
;
2012 do_s2io_write_bits(interruptible
,
2013 flag
, &bar0
->mac_rmac_err_mask
);
2016 if (mask
& RX_XGXS_INTR
)
2018 gen_int_mask
|= RXXGXS_INT_M
;
2019 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS
, flag
,
2020 &bar0
->xgxs_int_mask
);
2021 do_s2io_write_bits(RXGXS_ESTORE_OFLOW
| RXGXS_RX_SM_ERR
, flag
,
2022 &bar0
->xgxs_rxgxs_err_mask
);
2025 if (mask
& MC_INTR
) {
2026 gen_int_mask
|= MC_INT_M
;
2027 do_s2io_write_bits(MC_INT_MASK_MC_INT
, flag
, &bar0
->mc_int_mask
);
2028 do_s2io_write_bits(MC_ERR_REG_SM_ERR
| MC_ERR_REG_ECC_ALL_SNG
|
2029 MC_ERR_REG_ECC_ALL_DBL
| PLL_LOCK_N
, flag
,
2030 &bar0
->mc_err_mask
);
2032 nic
->general_int_mask
= gen_int_mask
;
2034 /* Remove this line when alarm interrupts are enabled */
2035 nic
->general_int_mask
= 0;
2038 * en_dis_able_nic_intrs - Enable or Disable the interrupts
2039 * @nic: device private variable,
2040 * @mask: A mask indicating which Intr block must be modified and,
2041 * @flag: A flag indicating whether to enable or disable the Intrs.
2042 * Description: This function will either disable or enable the interrupts
2043 * depending on the flag argument. The mask argument can be used to
2044 * enable/disable any Intr block.
2045 * Return Value: NONE.
2048 static void en_dis_able_nic_intrs(struct s2io_nic
*nic
, u16 mask
, int flag
)
2050 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
2051 register u64 temp64
= 0, intr_mask
= 0;
2053 intr_mask
= nic
->general_int_mask
;
2055 /* Top level interrupt classification */
2056 /* PIC Interrupts */
2057 if (mask
& TX_PIC_INTR
) {
2058 /* Enable PIC Intrs in the general intr mask register */
2059 intr_mask
|= TXPIC_INT_M
;
2060 if (flag
== ENABLE_INTRS
) {
2062 * If Hercules adapter enable GPIO otherwise
2063 * disable all PCIX, Flash, MDIO, IIC and GPIO
2064 * interrupts for now.
2067 if (s2io_link_fault_indication(nic
) ==
2068 LINK_UP_DOWN_INTERRUPT
) {
2069 do_s2io_write_bits(PIC_INT_GPIO
, flag
,
2070 &bar0
->pic_int_mask
);
2071 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP
, flag
,
2072 &bar0
->gpio_int_mask
);
2074 writeq(DISABLE_ALL_INTRS
, &bar0
->pic_int_mask
);
2075 } else if (flag
== DISABLE_INTRS
) {
2077 * Disable PIC Intrs in the general
2078 * intr mask register
2080 writeq(DISABLE_ALL_INTRS
, &bar0
->pic_int_mask
);
2084 /* Tx traffic interrupts */
2085 if (mask
& TX_TRAFFIC_INTR
) {
2086 intr_mask
|= TXTRAFFIC_INT_M
;
2087 if (flag
== ENABLE_INTRS
) {
2089 * Enable all the Tx side interrupts
2090 * writing 0 Enables all 64 TX interrupt levels
2092 writeq(0x0, &bar0
->tx_traffic_mask
);
2093 } else if (flag
== DISABLE_INTRS
) {
2095 * Disable Tx Traffic Intrs in the general intr mask
2098 writeq(DISABLE_ALL_INTRS
, &bar0
->tx_traffic_mask
);
2102 /* Rx traffic interrupts */
2103 if (mask
& RX_TRAFFIC_INTR
) {
2104 intr_mask
|= RXTRAFFIC_INT_M
;
2105 if (flag
== ENABLE_INTRS
) {
2106 /* writing 0 Enables all 8 RX interrupt levels */
2107 writeq(0x0, &bar0
->rx_traffic_mask
);
2108 } else if (flag
== DISABLE_INTRS
) {
2110 * Disable Rx Traffic Intrs in the general intr mask
2113 writeq(DISABLE_ALL_INTRS
, &bar0
->rx_traffic_mask
);
2117 temp64
= readq(&bar0
->general_int_mask
);
2118 if (flag
== ENABLE_INTRS
)
2119 temp64
&= ~((u64
) intr_mask
);
2121 temp64
= DISABLE_ALL_INTRS
;
2122 writeq(temp64
, &bar0
->general_int_mask
);
2124 nic
->general_int_mask
= readq(&bar0
->general_int_mask
);
2128 * verify_pcc_quiescent- Checks for PCC quiescent state
2129 * Return: 1 If PCC is quiescence
2130 * 0 If PCC is not quiescence
2132 static int verify_pcc_quiescent(struct s2io_nic
*sp
, int flag
)
2135 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
2136 u64 val64
= readq(&bar0
->adapter_status
);
2138 herc
= (sp
->device_type
== XFRAME_II_DEVICE
);
2140 if (flag
== FALSE
) {
2141 if ((!herc
&& (sp
->pdev
->revision
>= 4)) || herc
) {
2142 if (!(val64
& ADAPTER_STATUS_RMAC_PCC_IDLE
))
2145 if (!(val64
& ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE
))
2149 if ((!herc
&& (sp
->pdev
->revision
>= 4)) || herc
) {
2150 if (((val64
& ADAPTER_STATUS_RMAC_PCC_IDLE
) ==
2151 ADAPTER_STATUS_RMAC_PCC_IDLE
))
2154 if (((val64
& ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE
) ==
2155 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE
))
2163 * verify_xena_quiescence - Checks whether the H/W is ready
2164 * Description: Returns whether the H/W is ready to go or not. Depending
2165 * on whether adapter enable bit was written or not the comparison
2166 * differs and the calling function passes the input argument flag to
2168 * Return: 1 If xena is quiescence
2169 * 0 If Xena is not quiescence
2172 static int verify_xena_quiescence(struct s2io_nic
*sp
)
2175 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
2176 u64 val64
= readq(&bar0
->adapter_status
);
2177 mode
= s2io_verify_pci_mode(sp
);
2179 if (!(val64
& ADAPTER_STATUS_TDMA_READY
)) {
2180 DBG_PRINT(ERR_DBG
, "%s", "TDMA is not ready!");
2183 if (!(val64
& ADAPTER_STATUS_RDMA_READY
)) {
2184 DBG_PRINT(ERR_DBG
, "%s", "RDMA is not ready!");
2187 if (!(val64
& ADAPTER_STATUS_PFC_READY
)) {
2188 DBG_PRINT(ERR_DBG
, "%s", "PFC is not ready!");
2191 if (!(val64
& ADAPTER_STATUS_TMAC_BUF_EMPTY
)) {
2192 DBG_PRINT(ERR_DBG
, "%s", "TMAC BUF is not empty!");
2195 if (!(val64
& ADAPTER_STATUS_PIC_QUIESCENT
)) {
2196 DBG_PRINT(ERR_DBG
, "%s", "PIC is not QUIESCENT!");
2199 if (!(val64
& ADAPTER_STATUS_MC_DRAM_READY
)) {
2200 DBG_PRINT(ERR_DBG
, "%s", "MC_DRAM is not ready!");
2203 if (!(val64
& ADAPTER_STATUS_MC_QUEUES_READY
)) {
2204 DBG_PRINT(ERR_DBG
, "%s", "MC_QUEUES is not ready!");
2207 if (!(val64
& ADAPTER_STATUS_M_PLL_LOCK
)) {
2208 DBG_PRINT(ERR_DBG
, "%s", "M_PLL is not locked!");
2213 * In PCI 33 mode, the P_PLL is not used, and therefore,
2214 * the the P_PLL_LOCK bit in the adapter_status register will
2217 if (!(val64
& ADAPTER_STATUS_P_PLL_LOCK
) &&
2218 sp
->device_type
== XFRAME_II_DEVICE
&& mode
!=
2220 DBG_PRINT(ERR_DBG
, "%s", "P_PLL is not locked!");
2223 if (!((val64
& ADAPTER_STATUS_RC_PRC_QUIESCENT
) ==
2224 ADAPTER_STATUS_RC_PRC_QUIESCENT
)) {
2225 DBG_PRINT(ERR_DBG
, "%s", "RC_PRC is not QUIESCENT!");
2232 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
2233 * @sp: Pointer to device specifc structure
2235 * New procedure to clear mac address reading problems on Alpha platforms
2239 static void fix_mac_address(struct s2io_nic
* sp
)
2241 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
2245 while (fix_mac
[i
] != END_SIGN
) {
2246 writeq(fix_mac
[i
++], &bar0
->gpio_control
);
2248 val64
= readq(&bar0
->gpio_control
);
2253 * start_nic - Turns the device on
2254 * @nic : device private variable.
2256 * This function actually turns the device on. Before this function is
2257 * called,all Registers are configured from their reset states
2258 * and shared memory is allocated but the NIC is still quiescent. On
2259 * calling this function, the device interrupts are cleared and the NIC is
2260 * literally switched on by writing into the adapter control register.
2262 * SUCCESS on success and -1 on failure.
2265 static int start_nic(struct s2io_nic
*nic
)
2267 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
2268 struct net_device
*dev
= nic
->dev
;
2269 register u64 val64
= 0;
2271 struct mac_info
*mac_control
;
2272 struct config_param
*config
;
2274 mac_control
= &nic
->mac_control
;
2275 config
= &nic
->config
;
2277 /* PRC Initialization and configuration */
2278 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2279 writeq((u64
) mac_control
->rings
[i
].rx_blocks
[0].block_dma_addr
,
2280 &bar0
->prc_rxd0_n
[i
]);
2282 val64
= readq(&bar0
->prc_ctrl_n
[i
]);
2283 if (nic
->rxd_mode
== RXD_MODE_1
)
2284 val64
|= PRC_CTRL_RC_ENABLED
;
2286 val64
|= PRC_CTRL_RC_ENABLED
| PRC_CTRL_RING_MODE_3
;
2287 if (nic
->device_type
== XFRAME_II_DEVICE
)
2288 val64
|= PRC_CTRL_GROUP_READS
;
2289 val64
&= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2290 val64
|= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2291 writeq(val64
, &bar0
->prc_ctrl_n
[i
]);
2294 if (nic
->rxd_mode
== RXD_MODE_3B
) {
2295 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2296 val64
= readq(&bar0
->rx_pa_cfg
);
2297 val64
|= RX_PA_CFG_IGNORE_L2_ERR
;
2298 writeq(val64
, &bar0
->rx_pa_cfg
);
2301 if (vlan_tag_strip
== 0) {
2302 val64
= readq(&bar0
->rx_pa_cfg
);
2303 val64
&= ~RX_PA_CFG_STRIP_VLAN_TAG
;
2304 writeq(val64
, &bar0
->rx_pa_cfg
);
2305 nic
->vlan_strip_flag
= 0;
2309 * Enabling MC-RLDRAM. After enabling the device, we timeout
2310 * for around 100ms, which is approximately the time required
2311 * for the device to be ready for operation.
2313 val64
= readq(&bar0
->mc_rldram_mrs
);
2314 val64
|= MC_RLDRAM_QUEUE_SIZE_ENABLE
| MC_RLDRAM_MRS_ENABLE
;
2315 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_mrs
, UF
);
2316 val64
= readq(&bar0
->mc_rldram_mrs
);
2318 msleep(100); /* Delay by around 100 ms. */
2320 /* Enabling ECC Protection. */
2321 val64
= readq(&bar0
->adapter_control
);
2322 val64
&= ~ADAPTER_ECC_EN
;
2323 writeq(val64
, &bar0
->adapter_control
);
2326 * Verify if the device is ready to be enabled, if so enable
2329 val64
= readq(&bar0
->adapter_status
);
2330 if (!verify_xena_quiescence(nic
)) {
2331 DBG_PRINT(ERR_DBG
, "%s: device is not ready, ", dev
->name
);
2332 DBG_PRINT(ERR_DBG
, "Adapter status reads: 0x%llx\n",
2333 (unsigned long long) val64
);
2338 * With some switches, link might be already up at this point.
2339 * Because of this weird behavior, when we enable laser,
2340 * we may not get link. We need to handle this. We cannot
2341 * figure out which switch is misbehaving. So we are forced to
2342 * make a global change.
2345 /* Enabling Laser. */
2346 val64
= readq(&bar0
->adapter_control
);
2347 val64
|= ADAPTER_EOI_TX_ON
;
2348 writeq(val64
, &bar0
->adapter_control
);
2350 if (s2io_link_fault_indication(nic
) == MAC_RMAC_ERR_TIMER
) {
2352 * Dont see link state interrupts initally on some switches,
2353 * so directly scheduling the link state task here.
2355 schedule_work(&nic
->set_link_task
);
2357 /* SXE-002: Initialize link and activity LED */
2358 subid
= nic
->pdev
->subsystem_device
;
2359 if (((subid
& 0xFF) >= 0x07) &&
2360 (nic
->device_type
== XFRAME_I_DEVICE
)) {
2361 val64
= readq(&bar0
->gpio_control
);
2362 val64
|= 0x0000800000000000ULL
;
2363 writeq(val64
, &bar0
->gpio_control
);
2364 val64
= 0x0411040400000000ULL
;
2365 writeq(val64
, (void __iomem
*)bar0
+ 0x2700);
2371 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2373 static struct sk_buff
*s2io_txdl_getskb(struct fifo_info
*fifo_data
, struct \
2374 TxD
*txdlp
, int get_off
)
2376 struct s2io_nic
*nic
= fifo_data
->nic
;
2377 struct sk_buff
*skb
;
2382 if (txds
->Host_Control
== (u64
)(long)fifo_data
->ufo_in_band_v
) {
2383 pci_unmap_single(nic
->pdev
, (dma_addr_t
)
2384 txds
->Buffer_Pointer
, sizeof(u64
),
2389 skb
= (struct sk_buff
*) ((unsigned long)
2390 txds
->Host_Control
);
2392 memset(txdlp
, 0, (sizeof(struct TxD
) * fifo_data
->max_txds
));
2395 pci_unmap_single(nic
->pdev
, (dma_addr_t
)
2396 txds
->Buffer_Pointer
,
2397 skb
->len
- skb
->data_len
,
2399 frg_cnt
= skb_shinfo(skb
)->nr_frags
;
2402 for (j
= 0; j
< frg_cnt
; j
++, txds
++) {
2403 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[j
];
2404 if (!txds
->Buffer_Pointer
)
2406 pci_unmap_page(nic
->pdev
, (dma_addr_t
)
2407 txds
->Buffer_Pointer
,
2408 frag
->size
, PCI_DMA_TODEVICE
);
2411 memset(txdlp
,0, (sizeof(struct TxD
) * fifo_data
->max_txds
));
2416 * free_tx_buffers - Free all queued Tx buffers
2417 * @nic : device private variable.
2419 * Free all queued Tx buffers.
2420 * Return Value: void
2423 static void free_tx_buffers(struct s2io_nic
*nic
)
2425 struct net_device
*dev
= nic
->dev
;
2426 struct sk_buff
*skb
;
2429 struct mac_info
*mac_control
;
2430 struct config_param
*config
;
2433 mac_control
= &nic
->mac_control
;
2434 config
= &nic
->config
;
2436 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
2437 unsigned long flags
;
2438 spin_lock_irqsave(&mac_control
->fifos
[i
].tx_lock
, flags
);
2439 for (j
= 0; j
< config
->tx_cfg
[i
].fifo_len
; j
++) {
2440 txdp
= (struct TxD
*) \
2441 mac_control
->fifos
[i
].list_info
[j
].list_virt_addr
;
2442 skb
= s2io_txdl_getskb(&mac_control
->fifos
[i
], txdp
, j
);
2444 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
2451 "%s:forcibly freeing %d skbs on FIFO%d\n",
2453 mac_control
->fifos
[i
].tx_curr_get_info
.offset
= 0;
2454 mac_control
->fifos
[i
].tx_curr_put_info
.offset
= 0;
2455 spin_unlock_irqrestore(&mac_control
->fifos
[i
].tx_lock
, flags
);
2460 * stop_nic - To stop the nic
2461 * @nic ; device private variable.
2463 * This function does exactly the opposite of what the start_nic()
2464 * function does. This function is called to stop the device.
2469 static void stop_nic(struct s2io_nic
*nic
)
2471 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
2472 register u64 val64
= 0;
2474 struct mac_info
*mac_control
;
2475 struct config_param
*config
;
2477 mac_control
= &nic
->mac_control
;
2478 config
= &nic
->config
;
2480 /* Disable all interrupts */
2481 en_dis_err_alarms(nic
, ENA_ALL_INTRS
, DISABLE_INTRS
);
2482 interruptible
= TX_TRAFFIC_INTR
| RX_TRAFFIC_INTR
;
2483 interruptible
|= TX_PIC_INTR
;
2484 en_dis_able_nic_intrs(nic
, interruptible
, DISABLE_INTRS
);
2486 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2487 val64
= readq(&bar0
->adapter_control
);
2488 val64
&= ~(ADAPTER_CNTL_EN
);
2489 writeq(val64
, &bar0
->adapter_control
);
2493 * fill_rx_buffers - Allocates the Rx side skbs
2494 * @ring_info: per ring structure
2495 * @from_card_up: If this is true, we will map the buffer to get
2496 * the dma address for buf0 and buf1 to give it to the card.
2497 * Else we will sync the already mapped buffer to give it to the card.
2499 * The function allocates Rx side skbs and puts the physical
2500 * address of these buffers into the RxD buffer pointers, so that the NIC
2501 * can DMA the received frame into these locations.
2502 * The NIC supports 3 receive modes, viz
2504 * 2. three buffer and
2505 * 3. Five buffer modes.
2506 * Each mode defines how many fragments the received frame will be split
2507 * up into by the NIC. The frame is split into L3 header, L4 Header,
2508 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2509 * is split into 3 fragments. As of now only single buffer mode is
2512 * SUCCESS on success or an appropriate -ve value on failure.
2514 static int fill_rx_buffers(struct s2io_nic
*nic
, struct ring_info
*ring
,
2517 struct sk_buff
*skb
;
2519 int off
, size
, block_no
, block_no1
;
2524 struct RxD_t
*first_rxdp
= NULL
;
2525 u64 Buffer0_ptr
= 0, Buffer1_ptr
= 0;
2529 struct swStat
*stats
= &ring
->nic
->mac_control
.stats_info
->sw_stat
;
2531 alloc_cnt
= ring
->pkt_cnt
- ring
->rx_bufs_left
;
2533 block_no1
= ring
->rx_curr_get_info
.block_index
;
2534 while (alloc_tab
< alloc_cnt
) {
2535 block_no
= ring
->rx_curr_put_info
.block_index
;
2537 off
= ring
->rx_curr_put_info
.offset
;
2539 rxdp
= ring
->rx_blocks
[block_no
].rxds
[off
].virt_addr
;
2541 rxd_index
= off
+ 1;
2543 rxd_index
+= (block_no
* ring
->rxd_count
);
2545 if ((block_no
== block_no1
) &&
2546 (off
== ring
->rx_curr_get_info
.offset
) &&
2547 (rxdp
->Host_Control
)) {
2548 DBG_PRINT(INTR_DBG
, "%s: Get and Put",
2550 DBG_PRINT(INTR_DBG
, " info equated\n");
2553 if (off
&& (off
== ring
->rxd_count
)) {
2554 ring
->rx_curr_put_info
.block_index
++;
2555 if (ring
->rx_curr_put_info
.block_index
==
2557 ring
->rx_curr_put_info
.block_index
= 0;
2558 block_no
= ring
->rx_curr_put_info
.block_index
;
2560 ring
->rx_curr_put_info
.offset
= off
;
2561 rxdp
= ring
->rx_blocks
[block_no
].block_virt_addr
;
2562 DBG_PRINT(INTR_DBG
, "%s: Next block at: %p\n",
2563 ring
->dev
->name
, rxdp
);
2567 if ((rxdp
->Control_1
& RXD_OWN_XENA
) &&
2568 ((ring
->rxd_mode
== RXD_MODE_3B
) &&
2569 (rxdp
->Control_2
& s2BIT(0)))) {
2570 ring
->rx_curr_put_info
.offset
= off
;
2573 /* calculate size of skb based on ring mode */
2574 size
= ring
->mtu
+ HEADER_ETHERNET_II_802_3_SIZE
+
2575 HEADER_802_2_SIZE
+ HEADER_SNAP_SIZE
;
2576 if (ring
->rxd_mode
== RXD_MODE_1
)
2577 size
+= NET_IP_ALIGN
;
2579 size
= ring
->mtu
+ ALIGN_SIZE
+ BUF0_LEN
+ 4;
2582 skb
= dev_alloc_skb(size
);
2584 DBG_PRINT(INFO_DBG
, "%s: Out of ", ring
->dev
->name
);
2585 DBG_PRINT(INFO_DBG
, "memory to allocate SKBs\n");
2588 first_rxdp
->Control_1
|= RXD_OWN_XENA
;
2590 stats
->mem_alloc_fail_cnt
++;
2594 stats
->mem_allocated
+= skb
->truesize
;
2596 if (ring
->rxd_mode
== RXD_MODE_1
) {
2597 /* 1 buffer mode - normal operation mode */
2598 rxdp1
= (struct RxD1
*)rxdp
;
2599 memset(rxdp
, 0, sizeof(struct RxD1
));
2600 skb_reserve(skb
, NET_IP_ALIGN
);
2601 rxdp1
->Buffer0_ptr
= pci_map_single
2602 (ring
->pdev
, skb
->data
, size
- NET_IP_ALIGN
,
2603 PCI_DMA_FROMDEVICE
);
2604 if (pci_dma_mapping_error(nic
->pdev
,
2605 rxdp1
->Buffer0_ptr
))
2606 goto pci_map_failed
;
2609 SET_BUFFER0_SIZE_1(size
- NET_IP_ALIGN
);
2610 rxdp
->Host_Control
= (unsigned long) (skb
);
2611 } else if (ring
->rxd_mode
== RXD_MODE_3B
) {
2614 * 2 buffer mode provides 128
2615 * byte aligned receive buffers.
2618 rxdp3
= (struct RxD3
*)rxdp
;
2619 /* save buffer pointers to avoid frequent dma mapping */
2620 Buffer0_ptr
= rxdp3
->Buffer0_ptr
;
2621 Buffer1_ptr
= rxdp3
->Buffer1_ptr
;
2622 memset(rxdp
, 0, sizeof(struct RxD3
));
2623 /* restore the buffer pointers for dma sync*/
2624 rxdp3
->Buffer0_ptr
= Buffer0_ptr
;
2625 rxdp3
->Buffer1_ptr
= Buffer1_ptr
;
2627 ba
= &ring
->ba
[block_no
][off
];
2628 skb_reserve(skb
, BUF0_LEN
);
2629 tmp
= (u64
)(unsigned long) skb
->data
;
2632 skb
->data
= (void *) (unsigned long)tmp
;
2633 skb_reset_tail_pointer(skb
);
2636 rxdp3
->Buffer0_ptr
=
2637 pci_map_single(ring
->pdev
, ba
->ba_0
,
2638 BUF0_LEN
, PCI_DMA_FROMDEVICE
);
2639 if (pci_dma_mapping_error(nic
->pdev
,
2640 rxdp3
->Buffer0_ptr
))
2641 goto pci_map_failed
;
2643 pci_dma_sync_single_for_device(ring
->pdev
,
2644 (dma_addr_t
) rxdp3
->Buffer0_ptr
,
2645 BUF0_LEN
, PCI_DMA_FROMDEVICE
);
2647 rxdp
->Control_2
= SET_BUFFER0_SIZE_3(BUF0_LEN
);
2648 if (ring
->rxd_mode
== RXD_MODE_3B
) {
2649 /* Two buffer mode */
2652 * Buffer2 will have L3/L4 header plus
2655 rxdp3
->Buffer2_ptr
= pci_map_single
2656 (ring
->pdev
, skb
->data
, ring
->mtu
+ 4,
2657 PCI_DMA_FROMDEVICE
);
2659 if (pci_dma_mapping_error(nic
->pdev
,
2660 rxdp3
->Buffer2_ptr
))
2661 goto pci_map_failed
;
2664 rxdp3
->Buffer1_ptr
=
2665 pci_map_single(ring
->pdev
,
2667 PCI_DMA_FROMDEVICE
);
2669 if (pci_dma_mapping_error(nic
->pdev
,
2670 rxdp3
->Buffer1_ptr
)) {
2673 (dma_addr_t
)(unsigned long)
2676 PCI_DMA_FROMDEVICE
);
2677 goto pci_map_failed
;
2680 rxdp
->Control_2
|= SET_BUFFER1_SIZE_3(1);
2681 rxdp
->Control_2
|= SET_BUFFER2_SIZE_3
2684 rxdp
->Control_2
|= s2BIT(0);
2685 rxdp
->Host_Control
= (unsigned long) (skb
);
2687 if (alloc_tab
& ((1 << rxsync_frequency
) - 1))
2688 rxdp
->Control_1
|= RXD_OWN_XENA
;
2690 if (off
== (ring
->rxd_count
+ 1))
2692 ring
->rx_curr_put_info
.offset
= off
;
2694 rxdp
->Control_2
|= SET_RXD_MARKER
;
2695 if (!(alloc_tab
& ((1 << rxsync_frequency
) - 1))) {
2698 first_rxdp
->Control_1
|= RXD_OWN_XENA
;
2702 ring
->rx_bufs_left
+= 1;
2707 /* Transfer ownership of first descriptor to adapter just before
2708 * exiting. Before that, use memory barrier so that ownership
2709 * and other fields are seen by adapter correctly.
2713 first_rxdp
->Control_1
|= RXD_OWN_XENA
;
2718 stats
->pci_map_fail_cnt
++;
2719 stats
->mem_freed
+= skb
->truesize
;
2720 dev_kfree_skb_irq(skb
);
2724 static void free_rxd_blk(struct s2io_nic
*sp
, int ring_no
, int blk
)
2726 struct net_device
*dev
= sp
->dev
;
2728 struct sk_buff
*skb
;
2730 struct mac_info
*mac_control
;
2735 mac_control
= &sp
->mac_control
;
2736 for (j
= 0 ; j
< rxd_count
[sp
->rxd_mode
]; j
++) {
2737 rxdp
= mac_control
->rings
[ring_no
].
2738 rx_blocks
[blk
].rxds
[j
].virt_addr
;
2739 skb
= (struct sk_buff
*)
2740 ((unsigned long) rxdp
->Host_Control
);
2744 if (sp
->rxd_mode
== RXD_MODE_1
) {
2745 rxdp1
= (struct RxD1
*)rxdp
;
2746 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2749 HEADER_ETHERNET_II_802_3_SIZE
2750 + HEADER_802_2_SIZE
+
2752 PCI_DMA_FROMDEVICE
);
2753 memset(rxdp
, 0, sizeof(struct RxD1
));
2754 } else if(sp
->rxd_mode
== RXD_MODE_3B
) {
2755 rxdp3
= (struct RxD3
*)rxdp
;
2756 ba
= &mac_control
->rings
[ring_no
].
2758 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2761 PCI_DMA_FROMDEVICE
);
2762 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2765 PCI_DMA_FROMDEVICE
);
2766 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2769 PCI_DMA_FROMDEVICE
);
2770 memset(rxdp
, 0, sizeof(struct RxD3
));
2772 sp
->mac_control
.stats_info
->sw_stat
.mem_freed
+= skb
->truesize
;
2774 mac_control
->rings
[ring_no
].rx_bufs_left
-= 1;
2779 * free_rx_buffers - Frees all Rx buffers
2780 * @sp: device private variable.
2782 * This function will free all Rx buffers allocated by host.
2787 static void free_rx_buffers(struct s2io_nic
*sp
)
2789 struct net_device
*dev
= sp
->dev
;
2790 int i
, blk
= 0, buf_cnt
= 0;
2791 struct mac_info
*mac_control
;
2792 struct config_param
*config
;
2794 mac_control
= &sp
->mac_control
;
2795 config
= &sp
->config
;
2797 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2798 for (blk
= 0; blk
< rx_ring_sz
[i
]; blk
++)
2799 free_rxd_blk(sp
,i
,blk
);
2801 mac_control
->rings
[i
].rx_curr_put_info
.block_index
= 0;
2802 mac_control
->rings
[i
].rx_curr_get_info
.block_index
= 0;
2803 mac_control
->rings
[i
].rx_curr_put_info
.offset
= 0;
2804 mac_control
->rings
[i
].rx_curr_get_info
.offset
= 0;
2805 mac_control
->rings
[i
].rx_bufs_left
= 0;
2806 DBG_PRINT(INIT_DBG
, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2807 dev
->name
, buf_cnt
, i
);
2811 static int s2io_chk_rx_buffers(struct s2io_nic
*nic
, struct ring_info
*ring
)
2813 if (fill_rx_buffers(nic
, ring
, 0) == -ENOMEM
) {
2814 DBG_PRINT(INFO_DBG
, "%s:Out of memory", ring
->dev
->name
);
2815 DBG_PRINT(INFO_DBG
, " in Rx Intr!!\n");
2821 * s2io_poll - Rx interrupt handler for NAPI support
2822 * @napi : pointer to the napi structure.
2823 * @budget : The number of packets that were budgeted to be processed
2824 * during one pass through the 'Poll" function.
2826 * Comes into picture only if NAPI support has been incorporated. It does
2827 * the same thing that rx_intr_handler does, but not in a interrupt context
2828 * also It will process only a given number of packets.
2830 * 0 on success and 1 if there are No Rx packets to be processed.
2833 static int s2io_poll_msix(struct napi_struct
*napi
, int budget
)
2835 struct ring_info
*ring
= container_of(napi
, struct ring_info
, napi
);
2836 struct net_device
*dev
= ring
->dev
;
2837 struct config_param
*config
;
2838 struct mac_info
*mac_control
;
2839 int pkts_processed
= 0;
2840 u8 __iomem
*addr
= NULL
;
2842 struct s2io_nic
*nic
= netdev_priv(dev
);
2843 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
2844 int budget_org
= budget
;
2846 config
= &nic
->config
;
2847 mac_control
= &nic
->mac_control
;
2849 if (unlikely(!is_s2io_card_up(nic
)))
2852 pkts_processed
= rx_intr_handler(ring
, budget
);
2853 s2io_chk_rx_buffers(nic
, ring
);
2855 if (pkts_processed
< budget_org
) {
2856 napi_complete(napi
);
2857 /*Re Enable MSI-Rx Vector*/
2858 addr
= (u8 __iomem
*)&bar0
->xmsi_mask_reg
;
2859 addr
+= 7 - ring
->ring_no
;
2860 val8
= (ring
->ring_no
== 0) ? 0x3f : 0xbf;
2864 return pkts_processed
;
2866 static int s2io_poll_inta(struct napi_struct
*napi
, int budget
)
2868 struct s2io_nic
*nic
= container_of(napi
, struct s2io_nic
, napi
);
2869 struct ring_info
*ring
;
2870 struct config_param
*config
;
2871 struct mac_info
*mac_control
;
2872 int pkts_processed
= 0;
2873 int ring_pkts_processed
, i
;
2874 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
2875 int budget_org
= budget
;
2877 config
= &nic
->config
;
2878 mac_control
= &nic
->mac_control
;
2880 if (unlikely(!is_s2io_card_up(nic
)))
2883 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2884 ring
= &mac_control
->rings
[i
];
2885 ring_pkts_processed
= rx_intr_handler(ring
, budget
);
2886 s2io_chk_rx_buffers(nic
, ring
);
2887 pkts_processed
+= ring_pkts_processed
;
2888 budget
-= ring_pkts_processed
;
2892 if (pkts_processed
< budget_org
) {
2893 napi_complete(napi
);
2894 /* Re enable the Rx interrupts for the ring */
2895 writeq(0, &bar0
->rx_traffic_mask
);
2896 readl(&bar0
->rx_traffic_mask
);
2898 return pkts_processed
;
2901 #ifdef CONFIG_NET_POLL_CONTROLLER
2903 * s2io_netpoll - netpoll event handler entry point
2904 * @dev : pointer to the device structure.
2906 * This function will be called by upper layer to check for events on the
2907 * interface in situations where interrupts are disabled. It is used for
2908 * specific in-kernel networking tasks, such as remote consoles and kernel
2909 * debugging over the network (example netdump in RedHat).
2911 static void s2io_netpoll(struct net_device
*dev
)
2913 struct s2io_nic
*nic
= netdev_priv(dev
);
2914 struct mac_info
*mac_control
;
2915 struct config_param
*config
;
2916 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
2917 u64 val64
= 0xFFFFFFFFFFFFFFFFULL
;
2920 if (pci_channel_offline(nic
->pdev
))
2923 disable_irq(dev
->irq
);
2925 mac_control
= &nic
->mac_control
;
2926 config
= &nic
->config
;
2928 writeq(val64
, &bar0
->rx_traffic_int
);
2929 writeq(val64
, &bar0
->tx_traffic_int
);
2931 /* we need to free up the transmitted skbufs or else netpoll will
2932 * run out of skbs and will fail and eventually netpoll application such
2933 * as netdump will fail.
2935 for (i
= 0; i
< config
->tx_fifo_num
; i
++)
2936 tx_intr_handler(&mac_control
->fifos
[i
]);
2938 /* check for received packet and indicate up to network */
2939 for (i
= 0; i
< config
->rx_ring_num
; i
++)
2940 rx_intr_handler(&mac_control
->rings
[i
], 0);
2942 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2943 if (fill_rx_buffers(nic
, &mac_control
->rings
[i
], 0) ==
2945 DBG_PRINT(INFO_DBG
, "%s:Out of memory", dev
->name
);
2946 DBG_PRINT(INFO_DBG
, " in Rx Netpoll!!\n");
2950 enable_irq(dev
->irq
);
2956 * rx_intr_handler - Rx interrupt handler
2957 * @ring_info: per ring structure.
2958 * @budget: budget for napi processing.
2960 * If the interrupt is because of a received frame or if the
2961 * receive ring contains fresh as yet un-processed frames,this function is
2962 * called. It picks out the RxD at which place the last Rx processing had
2963 * stopped and sends the skb to the OSM's Rx handler and then increments
2966 * No. of napi packets processed.
2968 static int rx_intr_handler(struct ring_info
*ring_data
, int budget
)
2970 int get_block
, put_block
;
2971 struct rx_curr_get_info get_info
, put_info
;
2973 struct sk_buff
*skb
;
2974 int pkt_cnt
= 0, napi_pkts
= 0;
2979 get_info
= ring_data
->rx_curr_get_info
;
2980 get_block
= get_info
.block_index
;
2981 memcpy(&put_info
, &ring_data
->rx_curr_put_info
, sizeof(put_info
));
2982 put_block
= put_info
.block_index
;
2983 rxdp
= ring_data
->rx_blocks
[get_block
].rxds
[get_info
.offset
].virt_addr
;
2985 while (RXD_IS_UP2DT(rxdp
)) {
2987 * If your are next to put index then it's
2988 * FIFO full condition
2990 if ((get_block
== put_block
) &&
2991 (get_info
.offset
+ 1) == put_info
.offset
) {
2992 DBG_PRINT(INTR_DBG
, "%s: Ring Full\n",
2993 ring_data
->dev
->name
);
2996 skb
= (struct sk_buff
*) ((unsigned long)rxdp
->Host_Control
);
2998 DBG_PRINT(ERR_DBG
, "%s: The skb is ",
2999 ring_data
->dev
->name
);
3000 DBG_PRINT(ERR_DBG
, "Null in Rx Intr\n");
3003 if (ring_data
->rxd_mode
== RXD_MODE_1
) {
3004 rxdp1
= (struct RxD1
*)rxdp
;
3005 pci_unmap_single(ring_data
->pdev
, (dma_addr_t
)
3008 HEADER_ETHERNET_II_802_3_SIZE
+
3011 PCI_DMA_FROMDEVICE
);
3012 } else if (ring_data
->rxd_mode
== RXD_MODE_3B
) {
3013 rxdp3
= (struct RxD3
*)rxdp
;
3014 pci_dma_sync_single_for_cpu(ring_data
->pdev
, (dma_addr_t
)
3016 BUF0_LEN
, PCI_DMA_FROMDEVICE
);
3017 pci_unmap_single(ring_data
->pdev
, (dma_addr_t
)
3020 PCI_DMA_FROMDEVICE
);
3022 prefetch(skb
->data
);
3023 rx_osm_handler(ring_data
, rxdp
);
3025 ring_data
->rx_curr_get_info
.offset
= get_info
.offset
;
3026 rxdp
= ring_data
->rx_blocks
[get_block
].
3027 rxds
[get_info
.offset
].virt_addr
;
3028 if (get_info
.offset
== rxd_count
[ring_data
->rxd_mode
]) {
3029 get_info
.offset
= 0;
3030 ring_data
->rx_curr_get_info
.offset
= get_info
.offset
;
3032 if (get_block
== ring_data
->block_count
)
3034 ring_data
->rx_curr_get_info
.block_index
= get_block
;
3035 rxdp
= ring_data
->rx_blocks
[get_block
].block_virt_addr
;
3038 if (ring_data
->nic
->config
.napi
) {
3045 if ((indicate_max_pkts
) && (pkt_cnt
> indicate_max_pkts
))
3048 if (ring_data
->lro
) {
3049 /* Clear all LRO sessions before exiting */
3050 for (i
=0; i
<MAX_LRO_SESSIONS
; i
++) {
3051 struct lro
*lro
= &ring_data
->lro0_n
[i
];
3053 update_L3L4_header(ring_data
->nic
, lro
);
3054 queue_rx_frame(lro
->parent
, lro
->vlan_tag
);
3055 clear_lro_session(lro
);
3063 * tx_intr_handler - Transmit interrupt handler
3064 * @nic : device private variable
3066 * If an interrupt was raised to indicate DMA complete of the
3067 * Tx packet, this function is called. It identifies the last TxD
3068 * whose buffer was freed and frees all skbs whose data have already
3069 * DMA'ed into the NICs internal memory.
3074 static void tx_intr_handler(struct fifo_info
*fifo_data
)
3076 struct s2io_nic
*nic
= fifo_data
->nic
;
3077 struct tx_curr_get_info get_info
, put_info
;
3078 struct sk_buff
*skb
= NULL
;
3081 unsigned long flags
= 0;
3084 if (!spin_trylock_irqsave(&fifo_data
->tx_lock
, flags
))
3087 get_info
= fifo_data
->tx_curr_get_info
;
3088 memcpy(&put_info
, &fifo_data
->tx_curr_put_info
, sizeof(put_info
));
3089 txdlp
= (struct TxD
*) fifo_data
->list_info
[get_info
.offset
].
3091 while ((!(txdlp
->Control_1
& TXD_LIST_OWN_XENA
)) &&
3092 (get_info
.offset
!= put_info
.offset
) &&
3093 (txdlp
->Host_Control
)) {
3094 /* Check for TxD errors */
3095 if (txdlp
->Control_1
& TXD_T_CODE
) {
3096 unsigned long long err
;
3097 err
= txdlp
->Control_1
& TXD_T_CODE
;
3099 nic
->mac_control
.stats_info
->sw_stat
.
3103 /* update t_code statistics */
3104 err_mask
= err
>> 48;
3107 nic
->mac_control
.stats_info
->sw_stat
.
3112 nic
->mac_control
.stats_info
->sw_stat
.
3113 tx_desc_abort_cnt
++;
3117 nic
->mac_control
.stats_info
->sw_stat
.
3118 tx_parity_err_cnt
++;
3122 nic
->mac_control
.stats_info
->sw_stat
.
3127 nic
->mac_control
.stats_info
->sw_stat
.
3128 tx_list_proc_err_cnt
++;
3133 skb
= s2io_txdl_getskb(fifo_data
, txdlp
, get_info
.offset
);
3135 spin_unlock_irqrestore(&fifo_data
->tx_lock
, flags
);
3136 DBG_PRINT(ERR_DBG
, "%s: Null skb ",
3138 DBG_PRINT(ERR_DBG
, "in Tx Free Intr\n");
3143 /* Updating the statistics block */
3144 nic
->dev
->stats
.tx_bytes
+= skb
->len
;
3145 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+= skb
->truesize
;
3146 dev_kfree_skb_irq(skb
);
3149 if (get_info
.offset
== get_info
.fifo_len
+ 1)
3150 get_info
.offset
= 0;
3151 txdlp
= (struct TxD
*) fifo_data
->list_info
3152 [get_info
.offset
].list_virt_addr
;
3153 fifo_data
->tx_curr_get_info
.offset
=
3157 s2io_wake_tx_queue(fifo_data
, pkt_cnt
, nic
->config
.multiq
);
3159 spin_unlock_irqrestore(&fifo_data
->tx_lock
, flags
);
3163 * s2io_mdio_write - Function to write in to MDIO registers
3164 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3165 * @addr : address value
3166 * @value : data value
3167 * @dev : pointer to net_device structure
3169 * This function is used to write values to the MDIO registers
3172 static void s2io_mdio_write(u32 mmd_type
, u64 addr
, u16 value
, struct net_device
*dev
)
3175 struct s2io_nic
*sp
= netdev_priv(dev
);
3176 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
3178 //address transaction
3179 val64
= val64
| MDIO_MMD_INDX_ADDR(addr
)
3180 | MDIO_MMD_DEV_ADDR(mmd_type
)
3181 | MDIO_MMS_PRT_ADDR(0x0);
3182 writeq(val64
, &bar0
->mdio_control
);
3183 val64
= val64
| MDIO_CTRL_START_TRANS(0xE);
3184 writeq(val64
, &bar0
->mdio_control
);
3189 val64
= val64
| MDIO_MMD_INDX_ADDR(addr
)
3190 | MDIO_MMD_DEV_ADDR(mmd_type
)
3191 | MDIO_MMS_PRT_ADDR(0x0)
3192 | MDIO_MDIO_DATA(value
)
3193 | MDIO_OP(MDIO_OP_WRITE_TRANS
);
3194 writeq(val64
, &bar0
->mdio_control
);
3195 val64
= val64
| MDIO_CTRL_START_TRANS(0xE);
3196 writeq(val64
, &bar0
->mdio_control
);
3200 val64
= val64
| MDIO_MMD_INDX_ADDR(addr
)
3201 | MDIO_MMD_DEV_ADDR(mmd_type
)
3202 | MDIO_MMS_PRT_ADDR(0x0)
3203 | MDIO_OP(MDIO_OP_READ_TRANS
);
3204 writeq(val64
, &bar0
->mdio_control
);
3205 val64
= val64
| MDIO_CTRL_START_TRANS(0xE);
3206 writeq(val64
, &bar0
->mdio_control
);
3212 * s2io_mdio_read - Function to write in to MDIO registers
3213 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3214 * @addr : address value
3215 * @dev : pointer to net_device structure
3217 * This function is used to read values to the MDIO registers
3220 static u64
s2io_mdio_read(u32 mmd_type
, u64 addr
, struct net_device
*dev
)
3224 struct s2io_nic
*sp
= netdev_priv(dev
);
3225 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
3227 /* address transaction */
3228 val64
= val64
| MDIO_MMD_INDX_ADDR(addr
)
3229 | MDIO_MMD_DEV_ADDR(mmd_type
)
3230 | MDIO_MMS_PRT_ADDR(0x0);
3231 writeq(val64
, &bar0
->mdio_control
);
3232 val64
= val64
| MDIO_CTRL_START_TRANS(0xE);
3233 writeq(val64
, &bar0
->mdio_control
);
3236 /* Data transaction */
3238 val64
= val64
| MDIO_MMD_INDX_ADDR(addr
)
3239 | MDIO_MMD_DEV_ADDR(mmd_type
)
3240 | MDIO_MMS_PRT_ADDR(0x0)
3241 | MDIO_OP(MDIO_OP_READ_TRANS
);
3242 writeq(val64
, &bar0
->mdio_control
);
3243 val64
= val64
| MDIO_CTRL_START_TRANS(0xE);
3244 writeq(val64
, &bar0
->mdio_control
);
3247 /* Read the value from regs */
3248 rval64
= readq(&bar0
->mdio_control
);
3249 rval64
= rval64
& 0xFFFF0000;
3250 rval64
= rval64
>> 16;
3254 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
3255 * @counter : couter value to be updated
3256 * @flag : flag to indicate the status
3257 * @type : counter type
3259 * This function is to check the status of the xpak counters value
3263 static void s2io_chk_xpak_counter(u64
*counter
, u64
* regs_stat
, u32 index
, u16 flag
, u16 type
)
3268 for(i
= 0; i
<index
; i
++)
3273 *counter
= *counter
+ 1;
3274 val64
= *regs_stat
& mask
;
3275 val64
= val64
>> (index
* 0x2);
3282 DBG_PRINT(ERR_DBG
, "Take Xframe NIC out of "
3283 "service. Excessive temperatures may "
3284 "result in premature transceiver "
3288 DBG_PRINT(ERR_DBG
, "Take Xframe NIC out of "
3289 "service Excessive bias currents may "
3290 "indicate imminent laser diode "
3294 DBG_PRINT(ERR_DBG
, "Take Xframe NIC out of "
3295 "service Excessive laser output "
3296 "power may saturate far-end "
3300 DBG_PRINT(ERR_DBG
, "Incorrect XPAK Alarm "
3305 val64
= val64
<< (index
* 0x2);
3306 *regs_stat
= (*regs_stat
& (~mask
)) | (val64
);
3309 *regs_stat
= *regs_stat
& (~mask
);
3314 * s2io_updt_xpak_counter - Function to update the xpak counters
3315 * @dev : pointer to net_device struct
3317 * This function is to upate the status of the xpak counters value
3320 static void s2io_updt_xpak_counter(struct net_device
*dev
)
3328 struct s2io_nic
*sp
= netdev_priv(dev
);
3329 struct stat_block
*stat_info
= sp
->mac_control
.stats_info
;
3331 /* Check the communication with the MDIO slave */
3334 val64
= s2io_mdio_read(MDIO_MMD_PMAPMD
, addr
, dev
);
3335 if((val64
== 0xFFFF) || (val64
== 0x0000))
3337 DBG_PRINT(ERR_DBG
, "ERR: MDIO slave access failed - "
3338 "Returned %llx\n", (unsigned long long)val64
);
3342 /* Check for the expected value of control reg 1 */
3343 if(val64
!= MDIO_CTRL1_SPEED10G
)
3345 DBG_PRINT(ERR_DBG
, "Incorrect value at PMA address 0x0000 - ");
3346 DBG_PRINT(ERR_DBG
, "Returned: %llx- Expected: 0x%x\n",
3347 (unsigned long long)val64
, MDIO_CTRL1_SPEED10G
);
3351 /* Loading the DOM register to MDIO register */
3353 s2io_mdio_write(MDIO_MMD_PMAPMD
, addr
, val16
, dev
);
3354 val64
= s2io_mdio_read(MDIO_MMD_PMAPMD
, addr
, dev
);
3356 /* Reading the Alarm flags */
3359 val64
= s2io_mdio_read(MDIO_MMD_PMAPMD
, addr
, dev
);
3361 flag
= CHECKBIT(val64
, 0x7);
3363 s2io_chk_xpak_counter(&stat_info
->xpak_stat
.alarm_transceiver_temp_high
,
3364 &stat_info
->xpak_stat
.xpak_regs_stat
,
3367 if(CHECKBIT(val64
, 0x6))
3368 stat_info
->xpak_stat
.alarm_transceiver_temp_low
++;
3370 flag
= CHECKBIT(val64
, 0x3);
3372 s2io_chk_xpak_counter(&stat_info
->xpak_stat
.alarm_laser_bias_current_high
,
3373 &stat_info
->xpak_stat
.xpak_regs_stat
,
3376 if(CHECKBIT(val64
, 0x2))
3377 stat_info
->xpak_stat
.alarm_laser_bias_current_low
++;
3379 flag
= CHECKBIT(val64
, 0x1);
3381 s2io_chk_xpak_counter(&stat_info
->xpak_stat
.alarm_laser_output_power_high
,
3382 &stat_info
->xpak_stat
.xpak_regs_stat
,
3385 if(CHECKBIT(val64
, 0x0))
3386 stat_info
->xpak_stat
.alarm_laser_output_power_low
++;
3388 /* Reading the Warning flags */
3391 val64
= s2io_mdio_read(MDIO_MMD_PMAPMD
, addr
, dev
);
3393 if(CHECKBIT(val64
, 0x7))
3394 stat_info
->xpak_stat
.warn_transceiver_temp_high
++;
3396 if(CHECKBIT(val64
, 0x6))
3397 stat_info
->xpak_stat
.warn_transceiver_temp_low
++;
3399 if(CHECKBIT(val64
, 0x3))
3400 stat_info
->xpak_stat
.warn_laser_bias_current_high
++;
3402 if(CHECKBIT(val64
, 0x2))
3403 stat_info
->xpak_stat
.warn_laser_bias_current_low
++;
3405 if(CHECKBIT(val64
, 0x1))
3406 stat_info
->xpak_stat
.warn_laser_output_power_high
++;
3408 if(CHECKBIT(val64
, 0x0))
3409 stat_info
->xpak_stat
.warn_laser_output_power_low
++;
3413 * wait_for_cmd_complete - waits for a command to complete.
3414 * @sp : private member of the device structure, which is a pointer to the
3415 * s2io_nic structure.
3416 * Description: Function that waits for a command to Write into RMAC
3417 * ADDR DATA registers to be completed and returns either success or
3418 * error depending on whether the command was complete or not.
3420 * SUCCESS on success and FAILURE on failure.
3423 static int wait_for_cmd_complete(void __iomem
*addr
, u64 busy_bit
,
3426 int ret
= FAILURE
, cnt
= 0, delay
= 1;
3429 if ((bit_state
!= S2IO_BIT_RESET
) && (bit_state
!= S2IO_BIT_SET
))
3433 val64
= readq(addr
);
3434 if (bit_state
== S2IO_BIT_RESET
) {
3435 if (!(val64
& busy_bit
)) {
3440 if (!(val64
& busy_bit
)) {
3457 * check_pci_device_id - Checks if the device id is supported
3459 * Description: Function to check if the pci device id is supported by driver.
3460 * Return value: Actual device id if supported else PCI_ANY_ID
3462 static u16
check_pci_device_id(u16 id
)
3465 case PCI_DEVICE_ID_HERC_WIN
:
3466 case PCI_DEVICE_ID_HERC_UNI
:
3467 return XFRAME_II_DEVICE
;
3468 case PCI_DEVICE_ID_S2IO_UNI
:
3469 case PCI_DEVICE_ID_S2IO_WIN
:
3470 return XFRAME_I_DEVICE
;
3477 * s2io_reset - Resets the card.
3478 * @sp : private member of the device structure.
3479 * Description: Function to Reset the card. This function then also
3480 * restores the previously saved PCI configuration space registers as
3481 * the card reset also resets the configuration space.
3486 static void s2io_reset(struct s2io_nic
* sp
)
3488 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
3493 unsigned long long up_cnt
, down_cnt
, up_time
, down_time
, reset_cnt
;
3494 unsigned long long mem_alloc_cnt
, mem_free_cnt
, watchdog_cnt
;
3496 DBG_PRINT(INIT_DBG
,"%s - Resetting XFrame card %s\n",
3497 __func__
, sp
->dev
->name
);
3499 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3500 pci_read_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
, &(pci_cmd
));
3502 val64
= SW_RESET_ALL
;
3503 writeq(val64
, &bar0
->sw_reset
);
3504 if (strstr(sp
->product_name
, "CX4")) {
3508 for (i
= 0; i
< S2IO_MAX_PCI_CONFIG_SPACE_REINIT
; i
++) {
3510 /* Restore the PCI state saved during initialization. */
3511 pci_restore_state(sp
->pdev
);
3512 pci_read_config_word(sp
->pdev
, 0x2, &val16
);
3513 if (check_pci_device_id(val16
) != (u16
)PCI_ANY_ID
)
3518 if (check_pci_device_id(val16
) == (u16
)PCI_ANY_ID
) {
3519 DBG_PRINT(ERR_DBG
,"%s SW_Reset failed!\n", __func__
);
3522 pci_write_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
, pci_cmd
);
3526 /* Set swapper to enable I/O register access */
3527 s2io_set_swapper(sp
);
3529 /* restore mac_addr entries */
3530 do_s2io_restore_unicast_mc(sp
);
3532 /* Restore the MSIX table entries from local variables */
3533 restore_xmsi_data(sp
);
3535 /* Clear certain PCI/PCI-X fields after reset */
3536 if (sp
->device_type
== XFRAME_II_DEVICE
) {
3537 /* Clear "detected parity error" bit */
3538 pci_write_config_word(sp
->pdev
, PCI_STATUS
, 0x8000);
3540 /* Clearing PCIX Ecc status register */
3541 pci_write_config_dword(sp
->pdev
, 0x68, 0x7C);
3543 /* Clearing PCI_STATUS error reflected here */
3544 writeq(s2BIT(62), &bar0
->txpic_int_reg
);
3547 /* Reset device statistics maintained by OS */
3548 memset(&sp
->stats
, 0, sizeof (struct net_device_stats
));
3550 up_cnt
= sp
->mac_control
.stats_info
->sw_stat
.link_up_cnt
;
3551 down_cnt
= sp
->mac_control
.stats_info
->sw_stat
.link_down_cnt
;
3552 up_time
= sp
->mac_control
.stats_info
->sw_stat
.link_up_time
;
3553 down_time
= sp
->mac_control
.stats_info
->sw_stat
.link_down_time
;
3554 reset_cnt
= sp
->mac_control
.stats_info
->sw_stat
.soft_reset_cnt
;
3555 mem_alloc_cnt
= sp
->mac_control
.stats_info
->sw_stat
.mem_allocated
;
3556 mem_free_cnt
= sp
->mac_control
.stats_info
->sw_stat
.mem_freed
;
3557 watchdog_cnt
= sp
->mac_control
.stats_info
->sw_stat
.watchdog_timer_cnt
;
3558 /* save link up/down time/cnt, reset/memory/watchdog cnt */
3559 memset(sp
->mac_control
.stats_info
, 0, sizeof(struct stat_block
));
3560 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3561 sp
->mac_control
.stats_info
->sw_stat
.link_up_cnt
= up_cnt
;
3562 sp
->mac_control
.stats_info
->sw_stat
.link_down_cnt
= down_cnt
;
3563 sp
->mac_control
.stats_info
->sw_stat
.link_up_time
= up_time
;
3564 sp
->mac_control
.stats_info
->sw_stat
.link_down_time
= down_time
;
3565 sp
->mac_control
.stats_info
->sw_stat
.soft_reset_cnt
= reset_cnt
;
3566 sp
->mac_control
.stats_info
->sw_stat
.mem_allocated
= mem_alloc_cnt
;
3567 sp
->mac_control
.stats_info
->sw_stat
.mem_freed
= mem_free_cnt
;
3568 sp
->mac_control
.stats_info
->sw_stat
.watchdog_timer_cnt
= watchdog_cnt
;
3570 /* SXE-002: Configure link and activity LED to turn it off */
3571 subid
= sp
->pdev
->subsystem_device
;
3572 if (((subid
& 0xFF) >= 0x07) &&
3573 (sp
->device_type
== XFRAME_I_DEVICE
)) {
3574 val64
= readq(&bar0
->gpio_control
);
3575 val64
|= 0x0000800000000000ULL
;
3576 writeq(val64
, &bar0
->gpio_control
);
3577 val64
= 0x0411040400000000ULL
;
3578 writeq(val64
, (void __iomem
*)bar0
+ 0x2700);
3582 * Clear spurious ECC interrupts that would have occured on
3583 * XFRAME II cards after reset.
3585 if (sp
->device_type
== XFRAME_II_DEVICE
) {
3586 val64
= readq(&bar0
->pcc_err_reg
);
3587 writeq(val64
, &bar0
->pcc_err_reg
);
3590 sp
->device_enabled_once
= FALSE
;
3594 * s2io_set_swapper - to set the swapper controle on the card
3595 * @sp : private member of the device structure,
3596 * pointer to the s2io_nic structure.
3597 * Description: Function to set the swapper control on the card
3598 * correctly depending on the 'endianness' of the system.
3600 * SUCCESS on success and FAILURE on failure.
3603 static int s2io_set_swapper(struct s2io_nic
* sp
)
3605 struct net_device
*dev
= sp
->dev
;
3606 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
3607 u64 val64
, valt
, valr
;
3610 * Set proper endian settings and verify the same by reading
3611 * the PIF Feed-back register.
3614 val64
= readq(&bar0
->pif_rd_swapper_fb
);
3615 if (val64
!= 0x0123456789ABCDEFULL
) {
3617 u64 value
[] = { 0xC30000C3C30000C3ULL
, /* FE=1, SE=1 */
3618 0x8100008181000081ULL
, /* FE=1, SE=0 */
3619 0x4200004242000042ULL
, /* FE=0, SE=1 */
3620 0}; /* FE=0, SE=0 */
3623 writeq(value
[i
], &bar0
->swapper_ctrl
);
3624 val64
= readq(&bar0
->pif_rd_swapper_fb
);
3625 if (val64
== 0x0123456789ABCDEFULL
)
3630 DBG_PRINT(ERR_DBG
, "%s: Endian settings are wrong, ",
3632 DBG_PRINT(ERR_DBG
, "feedback read %llx\n",
3633 (unsigned long long) val64
);
3638 valr
= readq(&bar0
->swapper_ctrl
);
3641 valt
= 0x0123456789ABCDEFULL
;
3642 writeq(valt
, &bar0
->xmsi_address
);
3643 val64
= readq(&bar0
->xmsi_address
);
3647 u64 value
[] = { 0x00C3C30000C3C300ULL
, /* FE=1, SE=1 */
3648 0x0081810000818100ULL
, /* FE=1, SE=0 */
3649 0x0042420000424200ULL
, /* FE=0, SE=1 */
3650 0}; /* FE=0, SE=0 */
3653 writeq((value
[i
] | valr
), &bar0
->swapper_ctrl
);
3654 writeq(valt
, &bar0
->xmsi_address
);
3655 val64
= readq(&bar0
->xmsi_address
);
3661 unsigned long long x
= val64
;
3662 DBG_PRINT(ERR_DBG
, "Write failed, Xmsi_addr ");
3663 DBG_PRINT(ERR_DBG
, "reads:0x%llx\n", x
);
3667 val64
= readq(&bar0
->swapper_ctrl
);
3668 val64
&= 0xFFFF000000000000ULL
;
3672 * The device by default set to a big endian format, so a
3673 * big endian driver need not set anything.
3675 val64
|= (SWAPPER_CTRL_TXP_FE
|
3676 SWAPPER_CTRL_TXP_SE
|
3677 SWAPPER_CTRL_TXD_R_FE
|
3678 SWAPPER_CTRL_TXD_W_FE
|
3679 SWAPPER_CTRL_TXF_R_FE
|
3680 SWAPPER_CTRL_RXD_R_FE
|
3681 SWAPPER_CTRL_RXD_W_FE
|
3682 SWAPPER_CTRL_RXF_W_FE
|
3683 SWAPPER_CTRL_XMSI_FE
|
3684 SWAPPER_CTRL_STATS_FE
| SWAPPER_CTRL_STATS_SE
);
3685 if (sp
->config
.intr_type
== INTA
)
3686 val64
|= SWAPPER_CTRL_XMSI_SE
;
3687 writeq(val64
, &bar0
->swapper_ctrl
);
3690 * Initially we enable all bits to make it accessible by the
3691 * driver, then we selectively enable only those bits that
3694 val64
|= (SWAPPER_CTRL_TXP_FE
|
3695 SWAPPER_CTRL_TXP_SE
|
3696 SWAPPER_CTRL_TXD_R_FE
|
3697 SWAPPER_CTRL_TXD_R_SE
|
3698 SWAPPER_CTRL_TXD_W_FE
|
3699 SWAPPER_CTRL_TXD_W_SE
|
3700 SWAPPER_CTRL_TXF_R_FE
|
3701 SWAPPER_CTRL_RXD_R_FE
|
3702 SWAPPER_CTRL_RXD_R_SE
|
3703 SWAPPER_CTRL_RXD_W_FE
|
3704 SWAPPER_CTRL_RXD_W_SE
|
3705 SWAPPER_CTRL_RXF_W_FE
|
3706 SWAPPER_CTRL_XMSI_FE
|
3707 SWAPPER_CTRL_STATS_FE
| SWAPPER_CTRL_STATS_SE
);
3708 if (sp
->config
.intr_type
== INTA
)
3709 val64
|= SWAPPER_CTRL_XMSI_SE
;
3710 writeq(val64
, &bar0
->swapper_ctrl
);
3712 val64
= readq(&bar0
->swapper_ctrl
);
3715 * Verifying if endian settings are accurate by reading a
3716 * feedback register.
3718 val64
= readq(&bar0
->pif_rd_swapper_fb
);
3719 if (val64
!= 0x0123456789ABCDEFULL
) {
3720 /* Endian settings are incorrect, calls for another dekko. */
3721 DBG_PRINT(ERR_DBG
, "%s: Endian settings are wrong, ",
3723 DBG_PRINT(ERR_DBG
, "feedback read %llx\n",
3724 (unsigned long long) val64
);
3731 static int wait_for_msix_trans(struct s2io_nic
*nic
, int i
)
3733 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
3735 int ret
= 0, cnt
= 0;
3738 val64
= readq(&bar0
->xmsi_access
);
3739 if (!(val64
& s2BIT(15)))
3745 DBG_PRINT(ERR_DBG
, "XMSI # %d Access failed\n", i
);
3752 static void restore_xmsi_data(struct s2io_nic
*nic
)
3754 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
3759 if (nic
->device_type
== XFRAME_I_DEVICE
)
3762 for (i
=0; i
< MAX_REQUESTED_MSI_X
; i
++) {
3763 msix_index
= (i
) ? ((i
-1) * 8 + 1): 0;
3764 writeq(nic
->msix_info
[i
].addr
, &bar0
->xmsi_address
);
3765 writeq(nic
->msix_info
[i
].data
, &bar0
->xmsi_data
);
3766 val64
= (s2BIT(7) | s2BIT(15) | vBIT(msix_index
, 26, 6));
3767 writeq(val64
, &bar0
->xmsi_access
);
3768 if (wait_for_msix_trans(nic
, msix_index
)) {
3769 DBG_PRINT(ERR_DBG
, "failed in %s\n", __func__
);
3775 static void store_xmsi_data(struct s2io_nic
*nic
)
3777 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
3778 u64 val64
, addr
, data
;
3781 if (nic
->device_type
== XFRAME_I_DEVICE
)
3784 /* Store and display */
3785 for (i
=0; i
< MAX_REQUESTED_MSI_X
; i
++) {
3786 msix_index
= (i
) ? ((i
-1) * 8 + 1): 0;
3787 val64
= (s2BIT(15) | vBIT(msix_index
, 26, 6));
3788 writeq(val64
, &bar0
->xmsi_access
);
3789 if (wait_for_msix_trans(nic
, msix_index
)) {
3790 DBG_PRINT(ERR_DBG
, "failed in %s\n", __func__
);
3793 addr
= readq(&bar0
->xmsi_address
);
3794 data
= readq(&bar0
->xmsi_data
);
3796 nic
->msix_info
[i
].addr
= addr
;
3797 nic
->msix_info
[i
].data
= data
;
3802 static int s2io_enable_msi_x(struct s2io_nic
*nic
)
3804 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
3806 u16 msi_control
; /* Temp variable */
3807 int ret
, i
, j
, msix_indx
= 1;
3809 nic
->entries
= kmalloc(nic
->num_entries
* sizeof(struct msix_entry
),
3811 if (!nic
->entries
) {
3812 DBG_PRINT(INFO_DBG
, "%s: Memory allocation failed\n", \
3814 nic
->mac_control
.stats_info
->sw_stat
.mem_alloc_fail_cnt
++;
3817 nic
->mac_control
.stats_info
->sw_stat
.mem_allocated
3818 += (nic
->num_entries
* sizeof(struct msix_entry
));
3820 memset(nic
->entries
, 0, nic
->num_entries
* sizeof(struct msix_entry
));
3823 kmalloc(nic
->num_entries
* sizeof(struct s2io_msix_entry
),
3825 if (!nic
->s2io_entries
) {
3826 DBG_PRINT(INFO_DBG
, "%s: Memory allocation failed\n",
3828 nic
->mac_control
.stats_info
->sw_stat
.mem_alloc_fail_cnt
++;
3829 kfree(nic
->entries
);
3830 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
3831 += (nic
->num_entries
* sizeof(struct msix_entry
));
3834 nic
->mac_control
.stats_info
->sw_stat
.mem_allocated
3835 += (nic
->num_entries
* sizeof(struct s2io_msix_entry
));
3836 memset(nic
->s2io_entries
, 0,
3837 nic
->num_entries
* sizeof(struct s2io_msix_entry
));
3839 nic
->entries
[0].entry
= 0;
3840 nic
->s2io_entries
[0].entry
= 0;
3841 nic
->s2io_entries
[0].in_use
= MSIX_FLG
;
3842 nic
->s2io_entries
[0].type
= MSIX_ALARM_TYPE
;
3843 nic
->s2io_entries
[0].arg
= &nic
->mac_control
.fifos
;
3845 for (i
= 1; i
< nic
->num_entries
; i
++) {
3846 nic
->entries
[i
].entry
= ((i
- 1) * 8) + 1;
3847 nic
->s2io_entries
[i
].entry
= ((i
- 1) * 8) + 1;
3848 nic
->s2io_entries
[i
].arg
= NULL
;
3849 nic
->s2io_entries
[i
].in_use
= 0;
3852 rx_mat
= readq(&bar0
->rx_mat
);
3853 for (j
= 0; j
< nic
->config
.rx_ring_num
; j
++) {
3854 rx_mat
|= RX_MAT_SET(j
, msix_indx
);
3855 nic
->s2io_entries
[j
+1].arg
= &nic
->mac_control
.rings
[j
];
3856 nic
->s2io_entries
[j
+1].type
= MSIX_RING_TYPE
;
3857 nic
->s2io_entries
[j
+1].in_use
= MSIX_FLG
;
3860 writeq(rx_mat
, &bar0
->rx_mat
);
3861 readq(&bar0
->rx_mat
);
3863 ret
= pci_enable_msix(nic
->pdev
, nic
->entries
, nic
->num_entries
);
3864 /* We fail init if error or we get less vectors than min required */
3866 DBG_PRINT(ERR_DBG
, "s2io: Enabling MSI-X failed\n");
3867 kfree(nic
->entries
);
3868 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
3869 += (nic
->num_entries
* sizeof(struct msix_entry
));
3870 kfree(nic
->s2io_entries
);
3871 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
3872 += (nic
->num_entries
* sizeof(struct s2io_msix_entry
));
3873 nic
->entries
= NULL
;
3874 nic
->s2io_entries
= NULL
;
3879 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3880 * in the herc NIC. (Temp change, needs to be removed later)
3882 pci_read_config_word(nic
->pdev
, 0x42, &msi_control
);
3883 msi_control
|= 0x1; /* Enable MSI */
3884 pci_write_config_word(nic
->pdev
, 0x42, msi_control
);
3889 /* Handle software interrupt used during MSI(X) test */
3890 static irqreturn_t
s2io_test_intr(int irq
, void *dev_id
)
3892 struct s2io_nic
*sp
= dev_id
;
3894 sp
->msi_detected
= 1;
3895 wake_up(&sp
->msi_wait
);
3900 /* Test interrupt path by forcing a a software IRQ */
3901 static int s2io_test_msi(struct s2io_nic
*sp
)
3903 struct pci_dev
*pdev
= sp
->pdev
;
3904 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
3908 err
= request_irq(sp
->entries
[1].vector
, s2io_test_intr
, 0,
3911 DBG_PRINT(ERR_DBG
, "%s: PCI %s: cannot assign irq %d\n",
3912 sp
->dev
->name
, pci_name(pdev
), pdev
->irq
);
3916 init_waitqueue_head (&sp
->msi_wait
);
3917 sp
->msi_detected
= 0;
3919 saved64
= val64
= readq(&bar0
->scheduled_int_ctrl
);
3920 val64
|= SCHED_INT_CTRL_ONE_SHOT
;
3921 val64
|= SCHED_INT_CTRL_TIMER_EN
;
3922 val64
|= SCHED_INT_CTRL_INT2MSI(1);
3923 writeq(val64
, &bar0
->scheduled_int_ctrl
);
3925 wait_event_timeout(sp
->msi_wait
, sp
->msi_detected
, HZ
/10);
3927 if (!sp
->msi_detected
) {
3928 /* MSI(X) test failed, go back to INTx mode */
3929 DBG_PRINT(ERR_DBG
, "%s: PCI %s: No interrupt was generated "
3930 "using MSI(X) during test\n", sp
->dev
->name
,
3936 free_irq(sp
->entries
[1].vector
, sp
);
3938 writeq(saved64
, &bar0
->scheduled_int_ctrl
);
3943 static void remove_msix_isr(struct s2io_nic
*sp
)
3948 for (i
= 0; i
< sp
->num_entries
; i
++) {
3949 if (sp
->s2io_entries
[i
].in_use
==
3950 MSIX_REGISTERED_SUCCESS
) {
3951 int vector
= sp
->entries
[i
].vector
;
3952 void *arg
= sp
->s2io_entries
[i
].arg
;
3953 free_irq(vector
, arg
);
3958 kfree(sp
->s2io_entries
);
3960 sp
->s2io_entries
= NULL
;
3962 pci_read_config_word(sp
->pdev
, 0x42, &msi_control
);
3963 msi_control
&= 0xFFFE; /* Disable MSI */
3964 pci_write_config_word(sp
->pdev
, 0x42, msi_control
);
3966 pci_disable_msix(sp
->pdev
);
3969 static void remove_inta_isr(struct s2io_nic
*sp
)
3971 struct net_device
*dev
= sp
->dev
;
3973 free_irq(sp
->pdev
->irq
, dev
);
3976 /* ********************************************************* *
3977 * Functions defined below concern the OS part of the driver *
3978 * ********************************************************* */
3981 * s2io_open - open entry point of the driver
3982 * @dev : pointer to the device structure.
3984 * This function is the open entry point of the driver. It mainly calls a
3985 * function to allocate Rx buffers and inserts them into the buffer
3986 * descriptors and then enables the Rx part of the NIC.
3988 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3992 static int s2io_open(struct net_device
*dev
)
3994 struct s2io_nic
*sp
= netdev_priv(dev
);
3998 * Make sure you have link off by default every time
3999 * Nic is initialized
4001 netif_carrier_off(dev
);
4002 sp
->last_link_state
= 0;
4004 /* Initialize H/W and enable interrupts */
4005 err
= s2io_card_up(sp
);
4007 DBG_PRINT(ERR_DBG
, "%s: H/W initialization failed\n",
4009 goto hw_init_failed
;
4012 if (do_s2io_prog_unicast(dev
, dev
->dev_addr
) == FAILURE
) {
4013 DBG_PRINT(ERR_DBG
, "Set Mac Address Failed\n");
4016 goto hw_init_failed
;
4018 s2io_start_all_tx_queue(sp
);
4022 if (sp
->config
.intr_type
== MSI_X
) {
4025 sp
->mac_control
.stats_info
->sw_stat
.mem_freed
4026 += (sp
->num_entries
* sizeof(struct msix_entry
));
4028 if (sp
->s2io_entries
) {
4029 kfree(sp
->s2io_entries
);
4030 sp
->mac_control
.stats_info
->sw_stat
.mem_freed
4031 += (sp
->num_entries
* sizeof(struct s2io_msix_entry
));
4038 * s2io_close -close entry point of the driver
4039 * @dev : device pointer.
4041 * This is the stop entry point of the driver. It needs to undo exactly
4042 * whatever was done by the open entry point,thus it's usually referred to
4043 * as the close function.Among other things this function mainly stops the
4044 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
4046 * 0 on success and an appropriate (-)ve integer as defined in errno.h
4050 static int s2io_close(struct net_device
*dev
)
4052 struct s2io_nic
*sp
= netdev_priv(dev
);
4053 struct config_param
*config
= &sp
->config
;
4057 /* Return if the device is already closed *
4058 * Can happen when s2io_card_up failed in change_mtu *
4060 if (!is_s2io_card_up(sp
))
4063 s2io_stop_all_tx_queue(sp
);
4064 /* delete all populated mac entries */
4065 for (offset
= 1; offset
< config
->max_mc_addr
; offset
++) {
4066 tmp64
= do_s2io_read_unicast_mc(sp
, offset
);
4067 if (tmp64
!= S2IO_DISABLE_MAC_ENTRY
)
4068 do_s2io_delete_unicast_mc(sp
, tmp64
);
4077 * s2io_xmit - Tx entry point of te driver
4078 * @skb : the socket buffer containing the Tx data.
4079 * @dev : device pointer.
4081 * This function is the Tx entry point of the driver. S2IO NIC supports
4082 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
4083 * NOTE: when device cant queue the pkt,just the trans_start variable will
4086 * 0 on success & 1 on failure.
4089 static int s2io_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
4091 struct s2io_nic
*sp
= netdev_priv(dev
);
4092 u16 frg_cnt
, frg_len
, i
, queue
, queue_len
, put_off
, get_off
;
4095 struct TxFIFO_element __iomem
*tx_fifo
;
4096 unsigned long flags
= 0;
4098 struct fifo_info
*fifo
= NULL
;
4099 struct mac_info
*mac_control
;
4100 struct config_param
*config
;
4101 int do_spin_lock
= 1;
4103 int enable_per_list_interrupt
= 0;
4104 struct swStat
*stats
= &sp
->mac_control
.stats_info
->sw_stat
;
4106 mac_control
= &sp
->mac_control
;
4107 config
= &sp
->config
;
4109 DBG_PRINT(TX_DBG
, "%s: In Neterion Tx routine\n", dev
->name
);
4111 if (unlikely(skb
->len
<= 0)) {
4112 DBG_PRINT(TX_DBG
, "%s:Buffer has no data..\n", dev
->name
);
4113 dev_kfree_skb_any(skb
);
4117 if (!is_s2io_card_up(sp
)) {
4118 DBG_PRINT(TX_DBG
, "%s: Card going down for reset\n",
4125 if (sp
->vlgrp
&& vlan_tx_tag_present(skb
))
4126 vlan_tag
= vlan_tx_tag_get(skb
);
4127 if (sp
->config
.tx_steering_type
== TX_DEFAULT_STEERING
) {
4128 if (skb
->protocol
== htons(ETH_P_IP
)) {
4133 if ((ip
->frag_off
& htons(IP_OFFSET
|IP_MF
)) == 0) {
4134 th
= (struct tcphdr
*)(((unsigned char *)ip
) +
4137 if (ip
->protocol
== IPPROTO_TCP
) {
4138 queue_len
= sp
->total_tcp_fifos
;
4139 queue
= (ntohs(th
->source
) +
4141 sp
->fifo_selector
[queue_len
- 1];
4142 if (queue
>= queue_len
)
4143 queue
= queue_len
- 1;
4144 } else if (ip
->protocol
== IPPROTO_UDP
) {
4145 queue_len
= sp
->total_udp_fifos
;
4146 queue
= (ntohs(th
->source
) +
4148 sp
->fifo_selector
[queue_len
- 1];
4149 if (queue
>= queue_len
)
4150 queue
= queue_len
- 1;
4151 queue
+= sp
->udp_fifo_idx
;
4152 if (skb
->len
> 1024)
4153 enable_per_list_interrupt
= 1;
4158 } else if (sp
->config
.tx_steering_type
== TX_PRIORITY_STEERING
)
4159 /* get fifo number based on skb->priority value */
4160 queue
= config
->fifo_mapping
4161 [skb
->priority
& (MAX_TX_FIFOS
- 1)];
4162 fifo
= &mac_control
->fifos
[queue
];
4165 spin_lock_irqsave(&fifo
->tx_lock
, flags
);
4167 if (unlikely(!spin_trylock_irqsave(&fifo
->tx_lock
, flags
)))
4168 return NETDEV_TX_LOCKED
;
4171 if (sp
->config
.multiq
) {
4172 if (__netif_subqueue_stopped(dev
, fifo
->fifo_no
)) {
4173 spin_unlock_irqrestore(&fifo
->tx_lock
, flags
);
4174 return NETDEV_TX_BUSY
;
4176 } else if (unlikely(fifo
->queue_state
== FIFO_QUEUE_STOP
)) {
4177 if (netif_queue_stopped(dev
)) {
4178 spin_unlock_irqrestore(&fifo
->tx_lock
, flags
);
4179 return NETDEV_TX_BUSY
;
4183 put_off
= (u16
) fifo
->tx_curr_put_info
.offset
;
4184 get_off
= (u16
) fifo
->tx_curr_get_info
.offset
;
4185 txdp
= (struct TxD
*) fifo
->list_info
[put_off
].list_virt_addr
;
4187 queue_len
= fifo
->tx_curr_put_info
.fifo_len
+ 1;
4188 /* Avoid "put" pointer going beyond "get" pointer */
4189 if (txdp
->Host_Control
||
4190 ((put_off
+1) == queue_len
? 0 : (put_off
+1)) == get_off
) {
4191 DBG_PRINT(TX_DBG
, "Error in xmit, No free TXDs.\n");
4192 s2io_stop_tx_queue(sp
, fifo
->fifo_no
);
4194 spin_unlock_irqrestore(&fifo
->tx_lock
, flags
);
4198 offload_type
= s2io_offload_type(skb
);
4199 if (offload_type
& (SKB_GSO_TCPV4
| SKB_GSO_TCPV6
)) {
4200 txdp
->Control_1
|= TXD_TCP_LSO_EN
;
4201 txdp
->Control_1
|= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb
));
4203 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
4205 (TXD_TX_CKO_IPV4_EN
| TXD_TX_CKO_TCP_EN
|
4208 txdp
->Control_1
|= TXD_GATHER_CODE_FIRST
;
4209 txdp
->Control_1
|= TXD_LIST_OWN_XENA
;
4210 txdp
->Control_2
|= TXD_INT_NUMBER(fifo
->fifo_no
);
4211 if (enable_per_list_interrupt
)
4212 if (put_off
& (queue_len
>> 5))
4213 txdp
->Control_2
|= TXD_INT_TYPE_PER_LIST
;
4215 txdp
->Control_2
|= TXD_VLAN_ENABLE
;
4216 txdp
->Control_2
|= TXD_VLAN_TAG(vlan_tag
);
4219 frg_len
= skb
->len
- skb
->data_len
;
4220 if (offload_type
== SKB_GSO_UDP
) {
4223 ufo_size
= s2io_udp_mss(skb
);
4225 txdp
->Control_1
|= TXD_UFO_EN
;
4226 txdp
->Control_1
|= TXD_UFO_MSS(ufo_size
);
4227 txdp
->Control_1
|= TXD_BUFFER0_SIZE(8);
4229 /* both variants do cpu_to_be64(be32_to_cpu(...)) */
4230 fifo
->ufo_in_band_v
[put_off
] =
4231 (__force u64
)skb_shinfo(skb
)->ip6_frag_id
;
4233 fifo
->ufo_in_band_v
[put_off
] =
4234 (__force u64
)skb_shinfo(skb
)->ip6_frag_id
<< 32;
4236 txdp
->Host_Control
= (unsigned long)fifo
->ufo_in_band_v
;
4237 txdp
->Buffer_Pointer
= pci_map_single(sp
->pdev
,
4238 fifo
->ufo_in_band_v
,
4239 sizeof(u64
), PCI_DMA_TODEVICE
);
4240 if (pci_dma_mapping_error(sp
->pdev
, txdp
->Buffer_Pointer
))
4241 goto pci_map_failed
;
4245 txdp
->Buffer_Pointer
= pci_map_single
4246 (sp
->pdev
, skb
->data
, frg_len
, PCI_DMA_TODEVICE
);
4247 if (pci_dma_mapping_error(sp
->pdev
, txdp
->Buffer_Pointer
))
4248 goto pci_map_failed
;
4250 txdp
->Host_Control
= (unsigned long) skb
;
4251 txdp
->Control_1
|= TXD_BUFFER0_SIZE(frg_len
);
4252 if (offload_type
== SKB_GSO_UDP
)
4253 txdp
->Control_1
|= TXD_UFO_EN
;
4255 frg_cnt
= skb_shinfo(skb
)->nr_frags
;
4256 /* For fragmented SKB. */
4257 for (i
= 0; i
< frg_cnt
; i
++) {
4258 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
4259 /* A '0' length fragment will be ignored */
4263 txdp
->Buffer_Pointer
= (u64
) pci_map_page
4264 (sp
->pdev
, frag
->page
, frag
->page_offset
,
4265 frag
->size
, PCI_DMA_TODEVICE
);
4266 txdp
->Control_1
= TXD_BUFFER0_SIZE(frag
->size
);
4267 if (offload_type
== SKB_GSO_UDP
)
4268 txdp
->Control_1
|= TXD_UFO_EN
;
4270 txdp
->Control_1
|= TXD_GATHER_CODE_LAST
;
4272 if (offload_type
== SKB_GSO_UDP
)
4273 frg_cnt
++; /* as Txd0 was used for inband header */
4275 tx_fifo
= mac_control
->tx_FIFO_start
[queue
];
4276 val64
= fifo
->list_info
[put_off
].list_phy_addr
;
4277 writeq(val64
, &tx_fifo
->TxDL_Pointer
);
4279 val64
= (TX_FIFO_LAST_TXD_NUM(frg_cnt
) | TX_FIFO_FIRST_LIST
|
4282 val64
|= TX_FIFO_SPECIAL_FUNC
;
4284 writeq(val64
, &tx_fifo
->List_Control
);
4289 if (put_off
== fifo
->tx_curr_put_info
.fifo_len
+ 1)
4291 fifo
->tx_curr_put_info
.offset
= put_off
;
4293 /* Avoid "put" pointer going beyond "get" pointer */
4294 if (((put_off
+1) == queue_len
? 0 : (put_off
+1)) == get_off
) {
4295 sp
->mac_control
.stats_info
->sw_stat
.fifo_full_cnt
++;
4297 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4299 s2io_stop_tx_queue(sp
, fifo
->fifo_no
);
4301 mac_control
->stats_info
->sw_stat
.mem_allocated
+= skb
->truesize
;
4302 dev
->trans_start
= jiffies
;
4303 spin_unlock_irqrestore(&fifo
->tx_lock
, flags
);
4305 if (sp
->config
.intr_type
== MSI_X
)
4306 tx_intr_handler(fifo
);
4310 stats
->pci_map_fail_cnt
++;
4311 s2io_stop_tx_queue(sp
, fifo
->fifo_no
);
4312 stats
->mem_freed
+= skb
->truesize
;
4314 spin_unlock_irqrestore(&fifo
->tx_lock
, flags
);
4319 s2io_alarm_handle(unsigned long data
)
4321 struct s2io_nic
*sp
= (struct s2io_nic
*)data
;
4322 struct net_device
*dev
= sp
->dev
;
4324 s2io_handle_errors(dev
);
4325 mod_timer(&sp
->alarm_timer
, jiffies
+ HZ
/ 2);
4328 static irqreturn_t
s2io_msix_ring_handle(int irq
, void *dev_id
)
4330 struct ring_info
*ring
= (struct ring_info
*)dev_id
;
4331 struct s2io_nic
*sp
= ring
->nic
;
4332 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4334 if (unlikely(!is_s2io_card_up(sp
)))
4337 if (sp
->config
.napi
) {
4338 u8 __iomem
*addr
= NULL
;
4341 addr
= (u8 __iomem
*)&bar0
->xmsi_mask_reg
;
4342 addr
+= (7 - ring
->ring_no
);
4343 val8
= (ring
->ring_no
== 0) ? 0x7f : 0xff;
4346 napi_schedule(&ring
->napi
);
4348 rx_intr_handler(ring
, 0);
4349 s2io_chk_rx_buffers(sp
, ring
);
4355 static irqreturn_t
s2io_msix_fifo_handle(int irq
, void *dev_id
)
4358 struct fifo_info
*fifos
= (struct fifo_info
*)dev_id
;
4359 struct s2io_nic
*sp
= fifos
->nic
;
4360 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4361 struct config_param
*config
= &sp
->config
;
4364 if (unlikely(!is_s2io_card_up(sp
)))
4367 reason
= readq(&bar0
->general_int_status
);
4368 if (unlikely(reason
== S2IO_MINUS_ONE
))
4369 /* Nothing much can be done. Get out */
4372 if (reason
& (GEN_INTR_TXPIC
| GEN_INTR_TXTRAFFIC
)) {
4373 writeq(S2IO_MINUS_ONE
, &bar0
->general_int_mask
);
4375 if (reason
& GEN_INTR_TXPIC
)
4376 s2io_txpic_intr_handle(sp
);
4378 if (reason
& GEN_INTR_TXTRAFFIC
)
4379 writeq(S2IO_MINUS_ONE
, &bar0
->tx_traffic_int
);
4381 for (i
= 0; i
< config
->tx_fifo_num
; i
++)
4382 tx_intr_handler(&fifos
[i
]);
4384 writeq(sp
->general_int_mask
, &bar0
->general_int_mask
);
4385 readl(&bar0
->general_int_status
);
4388 /* The interrupt was not raised by us */
4392 static void s2io_txpic_intr_handle(struct s2io_nic
*sp
)
4394 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4397 val64
= readq(&bar0
->pic_int_status
);
4398 if (val64
& PIC_INT_GPIO
) {
4399 val64
= readq(&bar0
->gpio_int_reg
);
4400 if ((val64
& GPIO_INT_REG_LINK_DOWN
) &&
4401 (val64
& GPIO_INT_REG_LINK_UP
)) {
4403 * This is unstable state so clear both up/down
4404 * interrupt and adapter to re-evaluate the link state.
4406 val64
|= GPIO_INT_REG_LINK_DOWN
;
4407 val64
|= GPIO_INT_REG_LINK_UP
;
4408 writeq(val64
, &bar0
->gpio_int_reg
);
4409 val64
= readq(&bar0
->gpio_int_mask
);
4410 val64
&= ~(GPIO_INT_MASK_LINK_UP
|
4411 GPIO_INT_MASK_LINK_DOWN
);
4412 writeq(val64
, &bar0
->gpio_int_mask
);
4414 else if (val64
& GPIO_INT_REG_LINK_UP
) {
4415 val64
= readq(&bar0
->adapter_status
);
4416 /* Enable Adapter */
4417 val64
= readq(&bar0
->adapter_control
);
4418 val64
|= ADAPTER_CNTL_EN
;
4419 writeq(val64
, &bar0
->adapter_control
);
4420 val64
|= ADAPTER_LED_ON
;
4421 writeq(val64
, &bar0
->adapter_control
);
4422 if (!sp
->device_enabled_once
)
4423 sp
->device_enabled_once
= 1;
4425 s2io_link(sp
, LINK_UP
);
4427 * unmask link down interrupt and mask link-up
4430 val64
= readq(&bar0
->gpio_int_mask
);
4431 val64
&= ~GPIO_INT_MASK_LINK_DOWN
;
4432 val64
|= GPIO_INT_MASK_LINK_UP
;
4433 writeq(val64
, &bar0
->gpio_int_mask
);
4435 }else if (val64
& GPIO_INT_REG_LINK_DOWN
) {
4436 val64
= readq(&bar0
->adapter_status
);
4437 s2io_link(sp
, LINK_DOWN
);
4438 /* Link is down so unmaks link up interrupt */
4439 val64
= readq(&bar0
->gpio_int_mask
);
4440 val64
&= ~GPIO_INT_MASK_LINK_UP
;
4441 val64
|= GPIO_INT_MASK_LINK_DOWN
;
4442 writeq(val64
, &bar0
->gpio_int_mask
);
4445 val64
= readq(&bar0
->adapter_control
);
4446 val64
= val64
&(~ADAPTER_LED_ON
);
4447 writeq(val64
, &bar0
->adapter_control
);
4450 val64
= readq(&bar0
->gpio_int_mask
);
4454 * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4455 * @value: alarm bits
4456 * @addr: address value
4457 * @cnt: counter variable
4458 * Description: Check for alarm and increment the counter
4460 * 1 - if alarm bit set
4461 * 0 - if alarm bit is not set
4463 static int do_s2io_chk_alarm_bit(u64 value
, void __iomem
* addr
,
4464 unsigned long long *cnt
)
4467 val64
= readq(addr
);
4468 if ( val64
& value
) {
4469 writeq(val64
, addr
);
4478 * s2io_handle_errors - Xframe error indication handler
4479 * @nic: device private variable
4480 * Description: Handle alarms such as loss of link, single or
4481 * double ECC errors, critical and serious errors.
4485 static void s2io_handle_errors(void * dev_id
)
4487 struct net_device
*dev
= (struct net_device
*) dev_id
;
4488 struct s2io_nic
*sp
= netdev_priv(dev
);
4489 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4490 u64 temp64
= 0,val64
=0;
4493 struct swStat
*sw_stat
= &sp
->mac_control
.stats_info
->sw_stat
;
4494 struct xpakStat
*stats
= &sp
->mac_control
.stats_info
->xpak_stat
;
4496 if (!is_s2io_card_up(sp
))
4499 if (pci_channel_offline(sp
->pdev
))
4502 memset(&sw_stat
->ring_full_cnt
, 0,
4503 sizeof(sw_stat
->ring_full_cnt
));
4505 /* Handling the XPAK counters update */
4506 if(stats
->xpak_timer_count
< 72000) {
4507 /* waiting for an hour */
4508 stats
->xpak_timer_count
++;
4510 s2io_updt_xpak_counter(dev
);
4511 /* reset the count to zero */
4512 stats
->xpak_timer_count
= 0;
4515 /* Handling link status change error Intr */
4516 if (s2io_link_fault_indication(sp
) == MAC_RMAC_ERR_TIMER
) {
4517 val64
= readq(&bar0
->mac_rmac_err_reg
);
4518 writeq(val64
, &bar0
->mac_rmac_err_reg
);
4519 if (val64
& RMAC_LINK_STATE_CHANGE_INT
)
4520 schedule_work(&sp
->set_link_task
);
4523 /* In case of a serious error, the device will be Reset. */
4524 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY
, &bar0
->serr_source
,
4525 &sw_stat
->serious_err_cnt
))
4528 /* Check for data parity error */
4529 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT
, &bar0
->gpio_int_reg
,
4530 &sw_stat
->parity_err_cnt
))
4533 /* Check for ring full counter */
4534 if (sp
->device_type
== XFRAME_II_DEVICE
) {
4535 val64
= readq(&bar0
->ring_bump_counter1
);
4536 for (i
=0; i
<4; i
++) {
4537 temp64
= ( val64
& vBIT(0xFFFF,(i
*16),16));
4538 temp64
>>= 64 - ((i
+1)*16);
4539 sw_stat
->ring_full_cnt
[i
] += temp64
;
4542 val64
= readq(&bar0
->ring_bump_counter2
);
4543 for (i
=0; i
<4; i
++) {
4544 temp64
= ( val64
& vBIT(0xFFFF,(i
*16),16));
4545 temp64
>>= 64 - ((i
+1)*16);
4546 sw_stat
->ring_full_cnt
[i
+4] += temp64
;
4550 val64
= readq(&bar0
->txdma_int_status
);
4551 /*check for pfc_err*/
4552 if (val64
& TXDMA_PFC_INT
) {
4553 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR
| PFC_SM_ERR_ALARM
|
4554 PFC_MISC_0_ERR
| PFC_MISC_1_ERR
|
4555 PFC_PCIX_ERR
, &bar0
->pfc_err_reg
,
4556 &sw_stat
->pfc_err_cnt
))
4558 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR
, &bar0
->pfc_err_reg
,
4559 &sw_stat
->pfc_err_cnt
);
4562 /*check for tda_err*/
4563 if (val64
& TXDMA_TDA_INT
) {
4564 if(do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR
| TDA_SM0_ERR_ALARM
|
4565 TDA_SM1_ERR_ALARM
, &bar0
->tda_err_reg
,
4566 &sw_stat
->tda_err_cnt
))
4568 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR
| TDA_PCIX_ERR
,
4569 &bar0
->tda_err_reg
, &sw_stat
->tda_err_cnt
);
4571 /*check for pcc_err*/
4572 if (val64
& TXDMA_PCC_INT
) {
4573 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM
| PCC_WR_ERR_ALARM
4574 | PCC_N_SERR
| PCC_6_COF_OV_ERR
4575 | PCC_7_COF_OV_ERR
| PCC_6_LSO_OV_ERR
4576 | PCC_7_LSO_OV_ERR
| PCC_FB_ECC_DB_ERR
4577 | PCC_TXB_ECC_DB_ERR
, &bar0
->pcc_err_reg
,
4578 &sw_stat
->pcc_err_cnt
))
4580 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR
| PCC_TXB_ECC_SG_ERR
,
4581 &bar0
->pcc_err_reg
, &sw_stat
->pcc_err_cnt
);
4584 /*check for tti_err*/
4585 if (val64
& TXDMA_TTI_INT
) {
4586 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM
, &bar0
->tti_err_reg
,
4587 &sw_stat
->tti_err_cnt
))
4589 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR
| TTI_ECC_DB_ERR
,
4590 &bar0
->tti_err_reg
, &sw_stat
->tti_err_cnt
);
4593 /*check for lso_err*/
4594 if (val64
& TXDMA_LSO_INT
) {
4595 if (do_s2io_chk_alarm_bit(LSO6_ABORT
| LSO7_ABORT
4596 | LSO6_SM_ERR_ALARM
| LSO7_SM_ERR_ALARM
,
4597 &bar0
->lso_err_reg
, &sw_stat
->lso_err_cnt
))
4599 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW
| LSO7_SEND_OFLOW
,
4600 &bar0
->lso_err_reg
, &sw_stat
->lso_err_cnt
);
4603 /*check for tpa_err*/
4604 if (val64
& TXDMA_TPA_INT
) {
4605 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM
, &bar0
->tpa_err_reg
,
4606 &sw_stat
->tpa_err_cnt
))
4608 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP
, &bar0
->tpa_err_reg
,
4609 &sw_stat
->tpa_err_cnt
);
4612 /*check for sm_err*/
4613 if (val64
& TXDMA_SM_INT
) {
4614 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM
, &bar0
->sm_err_reg
,
4615 &sw_stat
->sm_err_cnt
))
4619 val64
= readq(&bar0
->mac_int_status
);
4620 if (val64
& MAC_INT_STATUS_TMAC_INT
) {
4621 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN
| TMAC_TX_SM_ERR
,
4622 &bar0
->mac_tmac_err_reg
,
4623 &sw_stat
->mac_tmac_err_cnt
))
4625 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR
| TMAC_ECC_DB_ERR
4626 | TMAC_DESC_ECC_SG_ERR
| TMAC_DESC_ECC_DB_ERR
,
4627 &bar0
->mac_tmac_err_reg
,
4628 &sw_stat
->mac_tmac_err_cnt
);
4631 val64
= readq(&bar0
->xgxs_int_status
);
4632 if (val64
& XGXS_INT_STATUS_TXGXS
) {
4633 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW
| TXGXS_TX_SM_ERR
,
4634 &bar0
->xgxs_txgxs_err_reg
,
4635 &sw_stat
->xgxs_txgxs_err_cnt
))
4637 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR
| TXGXS_ECC_DB_ERR
,
4638 &bar0
->xgxs_txgxs_err_reg
,
4639 &sw_stat
->xgxs_txgxs_err_cnt
);
4642 val64
= readq(&bar0
->rxdma_int_status
);
4643 if (val64
& RXDMA_INT_RC_INT_M
) {
4644 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR
| RC_FTC_ECC_DB_ERR
4645 | RC_PRCn_SM_ERR_ALARM
|RC_FTC_SM_ERR_ALARM
,
4646 &bar0
->rc_err_reg
, &sw_stat
->rc_err_cnt
))
4648 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR
| RC_FTC_ECC_SG_ERR
4649 | RC_RDA_FAIL_WR_Rn
, &bar0
->rc_err_reg
,
4650 &sw_stat
->rc_err_cnt
);
4651 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn
| PRC_PCI_AB_WR_Rn
4652 | PRC_PCI_AB_F_WR_Rn
, &bar0
->prc_pcix_err_reg
,
4653 &sw_stat
->prc_pcix_err_cnt
))
4655 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn
| PRC_PCI_DP_WR_Rn
4656 | PRC_PCI_DP_F_WR_Rn
, &bar0
->prc_pcix_err_reg
,
4657 &sw_stat
->prc_pcix_err_cnt
);
4660 if (val64
& RXDMA_INT_RPA_INT_M
) {
4661 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM
| RPA_CREDIT_ERR
,
4662 &bar0
->rpa_err_reg
, &sw_stat
->rpa_err_cnt
))
4664 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR
| RPA_ECC_DB_ERR
,
4665 &bar0
->rpa_err_reg
, &sw_stat
->rpa_err_cnt
);
4668 if (val64
& RXDMA_INT_RDA_INT_M
) {
4669 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR
4670 | RDA_FRM_ECC_DB_N_AERR
| RDA_SM1_ERR_ALARM
4671 | RDA_SM0_ERR_ALARM
| RDA_RXD_ECC_DB_SERR
,
4672 &bar0
->rda_err_reg
, &sw_stat
->rda_err_cnt
))
4674 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR
| RDA_FRM_ECC_SG_ERR
4675 | RDA_MISC_ERR
| RDA_PCIX_ERR
,
4676 &bar0
->rda_err_reg
, &sw_stat
->rda_err_cnt
);
4679 if (val64
& RXDMA_INT_RTI_INT_M
) {
4680 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM
, &bar0
->rti_err_reg
,
4681 &sw_stat
->rti_err_cnt
))
4683 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR
| RTI_ECC_DB_ERR
,
4684 &bar0
->rti_err_reg
, &sw_stat
->rti_err_cnt
);
4687 val64
= readq(&bar0
->mac_int_status
);
4688 if (val64
& MAC_INT_STATUS_RMAC_INT
) {
4689 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN
| RMAC_RX_SM_ERR
,
4690 &bar0
->mac_rmac_err_reg
,
4691 &sw_stat
->mac_rmac_err_cnt
))
4693 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT
|RMAC_SINGLE_ECC_ERR
|
4694 RMAC_DOUBLE_ECC_ERR
, &bar0
->mac_rmac_err_reg
,
4695 &sw_stat
->mac_rmac_err_cnt
);
4698 val64
= readq(&bar0
->xgxs_int_status
);
4699 if (val64
& XGXS_INT_STATUS_RXGXS
) {
4700 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW
| RXGXS_RX_SM_ERR
,
4701 &bar0
->xgxs_rxgxs_err_reg
,
4702 &sw_stat
->xgxs_rxgxs_err_cnt
))
4706 val64
= readq(&bar0
->mc_int_status
);
4707 if(val64
& MC_INT_STATUS_MC_INT
) {
4708 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR
, &bar0
->mc_err_reg
,
4709 &sw_stat
->mc_err_cnt
))
4712 /* Handling Ecc errors */
4713 if (val64
& (MC_ERR_REG_ECC_ALL_SNG
| MC_ERR_REG_ECC_ALL_DBL
)) {
4714 writeq(val64
, &bar0
->mc_err_reg
);
4715 if (val64
& MC_ERR_REG_ECC_ALL_DBL
) {
4716 sw_stat
->double_ecc_errs
++;
4717 if (sp
->device_type
!= XFRAME_II_DEVICE
) {
4719 * Reset XframeI only if critical error
4722 (MC_ERR_REG_MIRI_ECC_DB_ERR_0
|
4723 MC_ERR_REG_MIRI_ECC_DB_ERR_1
))
4727 sw_stat
->single_ecc_errs
++;
4733 s2io_stop_all_tx_queue(sp
);
4734 schedule_work(&sp
->rst_timer_task
);
4735 sw_stat
->soft_reset_cnt
++;
4740 * s2io_isr - ISR handler of the device .
4741 * @irq: the irq of the device.
4742 * @dev_id: a void pointer to the dev structure of the NIC.
4743 * Description: This function is the ISR handler of the device. It
4744 * identifies the reason for the interrupt and calls the relevant
4745 * service routines. As a contongency measure, this ISR allocates the
4746 * recv buffers, if their numbers are below the panic value which is
4747 * presently set to 25% of the original number of rcv buffers allocated.
4749 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
4750 * IRQ_NONE: will be returned if interrupt is not from our device
4752 static irqreturn_t
s2io_isr(int irq
, void *dev_id
)
4754 struct net_device
*dev
= (struct net_device
*) dev_id
;
4755 struct s2io_nic
*sp
= netdev_priv(dev
);
4756 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4759 struct mac_info
*mac_control
;
4760 struct config_param
*config
;
4762 /* Pretend we handled any irq's from a disconnected card */
4763 if (pci_channel_offline(sp
->pdev
))
4766 if (!is_s2io_card_up(sp
))
4769 mac_control
= &sp
->mac_control
;
4770 config
= &sp
->config
;
4773 * Identify the cause for interrupt and call the appropriate
4774 * interrupt handler. Causes for the interrupt could be;
4779 reason
= readq(&bar0
->general_int_status
);
4781 if (unlikely(reason
== S2IO_MINUS_ONE
) ) {
4782 /* Nothing much can be done. Get out */
4786 if (reason
& (GEN_INTR_RXTRAFFIC
|
4787 GEN_INTR_TXTRAFFIC
| GEN_INTR_TXPIC
))
4789 writeq(S2IO_MINUS_ONE
, &bar0
->general_int_mask
);
4792 if (reason
& GEN_INTR_RXTRAFFIC
) {
4793 napi_schedule(&sp
->napi
);
4794 writeq(S2IO_MINUS_ONE
, &bar0
->rx_traffic_mask
);
4795 writeq(S2IO_MINUS_ONE
, &bar0
->rx_traffic_int
);
4796 readl(&bar0
->rx_traffic_int
);
4800 * rx_traffic_int reg is an R1 register, writing all 1's
4801 * will ensure that the actual interrupt causing bit
4802 * get's cleared and hence a read can be avoided.
4804 if (reason
& GEN_INTR_RXTRAFFIC
)
4805 writeq(S2IO_MINUS_ONE
, &bar0
->rx_traffic_int
);
4807 for (i
= 0; i
< config
->rx_ring_num
; i
++)
4808 rx_intr_handler(&mac_control
->rings
[i
], 0);
4812 * tx_traffic_int reg is an R1 register, writing all 1's
4813 * will ensure that the actual interrupt causing bit get's
4814 * cleared and hence a read can be avoided.
4816 if (reason
& GEN_INTR_TXTRAFFIC
)
4817 writeq(S2IO_MINUS_ONE
, &bar0
->tx_traffic_int
);
4819 for (i
= 0; i
< config
->tx_fifo_num
; i
++)
4820 tx_intr_handler(&mac_control
->fifos
[i
]);
4822 if (reason
& GEN_INTR_TXPIC
)
4823 s2io_txpic_intr_handle(sp
);
4826 * Reallocate the buffers from the interrupt handler itself.
4828 if (!config
->napi
) {
4829 for (i
= 0; i
< config
->rx_ring_num
; i
++)
4830 s2io_chk_rx_buffers(sp
, &mac_control
->rings
[i
]);
4832 writeq(sp
->general_int_mask
, &bar0
->general_int_mask
);
4833 readl(&bar0
->general_int_status
);
4839 /* The interrupt was not raised by us */
4849 static void s2io_updt_stats(struct s2io_nic
*sp
)
4851 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4855 if (is_s2io_card_up(sp
)) {
4856 /* Apprx 30us on a 133 MHz bus */
4857 val64
= SET_UPDT_CLICKS(10) |
4858 STAT_CFG_ONE_SHOT_EN
| STAT_CFG_STAT_EN
;
4859 writeq(val64
, &bar0
->stat_cfg
);
4862 val64
= readq(&bar0
->stat_cfg
);
4863 if (!(val64
& s2BIT(0)))
4867 break; /* Updt failed */
4873 * s2io_get_stats - Updates the device statistics structure.
4874 * @dev : pointer to the device structure.
4876 * This function updates the device statistics structure in the s2io_nic
4877 * structure and returns a pointer to the same.
4879 * pointer to the updated net_device_stats structure.
4882 static struct net_device_stats
*s2io_get_stats(struct net_device
*dev
)
4884 struct s2io_nic
*sp
= netdev_priv(dev
);
4885 struct mac_info
*mac_control
;
4886 struct config_param
*config
;
4890 mac_control
= &sp
->mac_control
;
4891 config
= &sp
->config
;
4893 /* Configure Stats for immediate updt */
4894 s2io_updt_stats(sp
);
4896 /* Using sp->stats as a staging area, because reset (due to mtu
4897 change, for example) will clear some hardware counters */
4898 dev
->stats
.tx_packets
+=
4899 le32_to_cpu(mac_control
->stats_info
->tmac_frms
) -
4900 sp
->stats
.tx_packets
;
4901 sp
->stats
.tx_packets
=
4902 le32_to_cpu(mac_control
->stats_info
->tmac_frms
);
4903 dev
->stats
.tx_errors
+=
4904 le32_to_cpu(mac_control
->stats_info
->tmac_any_err_frms
) -
4905 sp
->stats
.tx_errors
;
4906 sp
->stats
.tx_errors
=
4907 le32_to_cpu(mac_control
->stats_info
->tmac_any_err_frms
);
4908 dev
->stats
.rx_errors
+=
4909 le64_to_cpu(mac_control
->stats_info
->rmac_drop_frms
) -
4910 sp
->stats
.rx_errors
;
4911 sp
->stats
.rx_errors
=
4912 le64_to_cpu(mac_control
->stats_info
->rmac_drop_frms
);
4913 dev
->stats
.multicast
=
4914 le32_to_cpu(mac_control
->stats_info
->rmac_vld_mcst_frms
) -
4915 sp
->stats
.multicast
;
4916 sp
->stats
.multicast
=
4917 le32_to_cpu(mac_control
->stats_info
->rmac_vld_mcst_frms
);
4918 dev
->stats
.rx_length_errors
=
4919 le64_to_cpu(mac_control
->stats_info
->rmac_long_frms
) -
4920 sp
->stats
.rx_length_errors
;
4921 sp
->stats
.rx_length_errors
=
4922 le64_to_cpu(mac_control
->stats_info
->rmac_long_frms
);
4924 /* collect per-ring rx_packets and rx_bytes */
4925 dev
->stats
.rx_packets
= dev
->stats
.rx_bytes
= 0;
4926 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
4927 dev
->stats
.rx_packets
+= mac_control
->rings
[i
].rx_packets
;
4928 dev
->stats
.rx_bytes
+= mac_control
->rings
[i
].rx_bytes
;
4931 return (&dev
->stats
);
4935 * s2io_set_multicast - entry point for multicast address enable/disable.
4936 * @dev : pointer to the device structure
4938 * This function is a driver entry point which gets called by the kernel
4939 * whenever multicast addresses must be enabled/disabled. This also gets
4940 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4941 * determine, if multicast address must be enabled or if promiscuous mode
4942 * is to be disabled etc.
4947 static void s2io_set_multicast(struct net_device
*dev
)
4950 struct dev_mc_list
*mclist
;
4951 struct s2io_nic
*sp
= netdev_priv(dev
);
4952 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4953 u64 val64
= 0, multi_mac
= 0x010203040506ULL
, mask
=
4955 u64 dis_addr
= S2IO_DISABLE_MAC_ENTRY
, mac_addr
= 0;
4957 struct config_param
*config
= &sp
->config
;
4959 if ((dev
->flags
& IFF_ALLMULTI
) && (!sp
->m_cast_flg
)) {
4960 /* Enable all Multicast addresses */
4961 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac
),
4962 &bar0
->rmac_addr_data0_mem
);
4963 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask
),
4964 &bar0
->rmac_addr_data1_mem
);
4965 val64
= RMAC_ADDR_CMD_MEM_WE
|
4966 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
4967 RMAC_ADDR_CMD_MEM_OFFSET(config
->max_mc_addr
- 1);
4968 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
4969 /* Wait till command completes */
4970 wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
4971 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
,
4975 sp
->all_multi_pos
= config
->max_mc_addr
- 1;
4976 } else if ((dev
->flags
& IFF_ALLMULTI
) && (sp
->m_cast_flg
)) {
4977 /* Disable all Multicast addresses */
4978 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr
),
4979 &bar0
->rmac_addr_data0_mem
);
4980 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4981 &bar0
->rmac_addr_data1_mem
);
4982 val64
= RMAC_ADDR_CMD_MEM_WE
|
4983 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
4984 RMAC_ADDR_CMD_MEM_OFFSET(sp
->all_multi_pos
);
4985 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
4986 /* Wait till command completes */
4987 wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
4988 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
,
4992 sp
->all_multi_pos
= 0;
4995 if ((dev
->flags
& IFF_PROMISC
) && (!sp
->promisc_flg
)) {
4996 /* Put the NIC into promiscuous mode */
4997 add
= &bar0
->mac_cfg
;
4998 val64
= readq(&bar0
->mac_cfg
);
4999 val64
|= MAC_CFG_RMAC_PROM_ENABLE
;
5001 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
5002 writel((u32
) val64
, add
);
5003 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
5004 writel((u32
) (val64
>> 32), (add
+ 4));
5006 if (vlan_tag_strip
!= 1) {
5007 val64
= readq(&bar0
->rx_pa_cfg
);
5008 val64
&= ~RX_PA_CFG_STRIP_VLAN_TAG
;
5009 writeq(val64
, &bar0
->rx_pa_cfg
);
5010 sp
->vlan_strip_flag
= 0;
5013 val64
= readq(&bar0
->mac_cfg
);
5014 sp
->promisc_flg
= 1;
5015 DBG_PRINT(INFO_DBG
, "%s: entered promiscuous mode\n",
5017 } else if (!(dev
->flags
& IFF_PROMISC
) && (sp
->promisc_flg
)) {
5018 /* Remove the NIC from promiscuous mode */
5019 add
= &bar0
->mac_cfg
;
5020 val64
= readq(&bar0
->mac_cfg
);
5021 val64
&= ~MAC_CFG_RMAC_PROM_ENABLE
;
5023 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
5024 writel((u32
) val64
, add
);
5025 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
5026 writel((u32
) (val64
>> 32), (add
+ 4));
5028 if (vlan_tag_strip
!= 0) {
5029 val64
= readq(&bar0
->rx_pa_cfg
);
5030 val64
|= RX_PA_CFG_STRIP_VLAN_TAG
;
5031 writeq(val64
, &bar0
->rx_pa_cfg
);
5032 sp
->vlan_strip_flag
= 1;
5035 val64
= readq(&bar0
->mac_cfg
);
5036 sp
->promisc_flg
= 0;
5037 DBG_PRINT(INFO_DBG
, "%s: left promiscuous mode\n",
5041 /* Update individual M_CAST address list */
5042 if ((!sp
->m_cast_flg
) && dev
->mc_count
) {
5044 (config
->max_mc_addr
- config
->max_mac_addr
)) {
5045 DBG_PRINT(ERR_DBG
, "%s: No more Rx filters ",
5047 DBG_PRINT(ERR_DBG
, "can be added, please enable ");
5048 DBG_PRINT(ERR_DBG
, "ALL_MULTI instead\n");
5052 prev_cnt
= sp
->mc_addr_count
;
5053 sp
->mc_addr_count
= dev
->mc_count
;
5055 /* Clear out the previous list of Mc in the H/W. */
5056 for (i
= 0; i
< prev_cnt
; i
++) {
5057 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr
),
5058 &bar0
->rmac_addr_data0_mem
);
5059 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5060 &bar0
->rmac_addr_data1_mem
);
5061 val64
= RMAC_ADDR_CMD_MEM_WE
|
5062 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
5063 RMAC_ADDR_CMD_MEM_OFFSET
5064 (config
->mc_start_offset
+ i
);
5065 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
5067 /* Wait for command completes */
5068 if (wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
5069 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
,
5071 DBG_PRINT(ERR_DBG
, "%s: Adding ",
5073 DBG_PRINT(ERR_DBG
, "Multicasts failed\n");
5078 /* Create the new Rx filter list and update the same in H/W. */
5079 for (i
= 0, mclist
= dev
->mc_list
; i
< dev
->mc_count
;
5080 i
++, mclist
= mclist
->next
) {
5081 memcpy(sp
->usr_addrs
[i
].addr
, mclist
->dmi_addr
,
5084 for (j
= 0; j
< ETH_ALEN
; j
++) {
5085 mac_addr
|= mclist
->dmi_addr
[j
];
5089 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr
),
5090 &bar0
->rmac_addr_data0_mem
);
5091 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5092 &bar0
->rmac_addr_data1_mem
);
5093 val64
= RMAC_ADDR_CMD_MEM_WE
|
5094 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
5095 RMAC_ADDR_CMD_MEM_OFFSET
5096 (i
+ config
->mc_start_offset
);
5097 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
5099 /* Wait for command completes */
5100 if (wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
5101 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
,
5103 DBG_PRINT(ERR_DBG
, "%s: Adding ",
5105 DBG_PRINT(ERR_DBG
, "Multicasts failed\n");
5112 /* read from CAM unicast & multicast addresses and store it in
5113 * def_mac_addr structure
5115 static void do_s2io_store_unicast_mc(struct s2io_nic
*sp
)
5119 struct config_param
*config
= &sp
->config
;
5121 /* store unicast & multicast mac addresses */
5122 for (offset
= 0; offset
< config
->max_mc_addr
; offset
++) {
5123 mac_addr
= do_s2io_read_unicast_mc(sp
, offset
);
5124 /* if read fails disable the entry */
5125 if (mac_addr
== FAILURE
)
5126 mac_addr
= S2IO_DISABLE_MAC_ENTRY
;
5127 do_s2io_copy_mac_addr(sp
, offset
, mac_addr
);
5131 /* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5132 static void do_s2io_restore_unicast_mc(struct s2io_nic
*sp
)
5135 struct config_param
*config
= &sp
->config
;
5136 /* restore unicast mac address */
5137 for (offset
= 0; offset
< config
->max_mac_addr
; offset
++)
5138 do_s2io_prog_unicast(sp
->dev
,
5139 sp
->def_mac_addr
[offset
].mac_addr
);
5141 /* restore multicast mac address */
5142 for (offset
= config
->mc_start_offset
;
5143 offset
< config
->max_mc_addr
; offset
++)
5144 do_s2io_add_mc(sp
, sp
->def_mac_addr
[offset
].mac_addr
);
5147 /* add a multicast MAC address to CAM */
5148 static int do_s2io_add_mc(struct s2io_nic
*sp
, u8
*addr
)
5152 struct config_param
*config
= &sp
->config
;
5154 for (i
= 0; i
< ETH_ALEN
; i
++) {
5156 mac_addr
|= addr
[i
];
5158 if ((0ULL == mac_addr
) || (mac_addr
== S2IO_DISABLE_MAC_ENTRY
))
5161 /* check if the multicast mac already preset in CAM */
5162 for (i
= config
->mc_start_offset
; i
< config
->max_mc_addr
; i
++) {
5164 tmp64
= do_s2io_read_unicast_mc(sp
, i
);
5165 if (tmp64
== S2IO_DISABLE_MAC_ENTRY
) /* CAM entry is empty */
5168 if (tmp64
== mac_addr
)
5171 if (i
== config
->max_mc_addr
) {
5173 "CAM full no space left for multicast MAC\n");
5176 /* Update the internal structure with this new mac address */
5177 do_s2io_copy_mac_addr(sp
, i
, mac_addr
);
5179 return (do_s2io_add_mac(sp
, mac_addr
, i
));
5182 /* add MAC address to CAM */
5183 static int do_s2io_add_mac(struct s2io_nic
*sp
, u64 addr
, int off
)
5186 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5188 writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr
),
5189 &bar0
->rmac_addr_data0_mem
);
5192 RMAC_ADDR_CMD_MEM_WE
| RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
5193 RMAC_ADDR_CMD_MEM_OFFSET(off
);
5194 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
5196 /* Wait till command completes */
5197 if (wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
5198 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
,
5200 DBG_PRINT(INFO_DBG
, "do_s2io_add_mac failed\n");
5205 /* deletes a specified unicast/multicast mac entry from CAM */
5206 static int do_s2io_delete_unicast_mc(struct s2io_nic
*sp
, u64 addr
)
5209 u64 dis_addr
= S2IO_DISABLE_MAC_ENTRY
, tmp64
;
5210 struct config_param
*config
= &sp
->config
;
5213 offset
< config
->max_mc_addr
; offset
++) {
5214 tmp64
= do_s2io_read_unicast_mc(sp
, offset
);
5215 if (tmp64
== addr
) {
5216 /* disable the entry by writing 0xffffffffffffULL */
5217 if (do_s2io_add_mac(sp
, dis_addr
, offset
) == FAILURE
)
5219 /* store the new mac list from CAM */
5220 do_s2io_store_unicast_mc(sp
);
5224 DBG_PRINT(ERR_DBG
, "MAC address 0x%llx not found in CAM\n",
5225 (unsigned long long)addr
);
5229 /* read mac entries from CAM */
5230 static u64
do_s2io_read_unicast_mc(struct s2io_nic
*sp
, int offset
)
5232 u64 tmp64
= 0xffffffffffff0000ULL
, val64
;
5233 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5237 RMAC_ADDR_CMD_MEM_RD
| RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
5238 RMAC_ADDR_CMD_MEM_OFFSET(offset
);
5239 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
5241 /* Wait till command completes */
5242 if (wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
5243 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
,
5245 DBG_PRINT(INFO_DBG
, "do_s2io_read_unicast_mc failed\n");
5248 tmp64
= readq(&bar0
->rmac_addr_data0_mem
);
5249 return (tmp64
>> 16);
5253 * s2io_set_mac_addr driver entry point
5256 static int s2io_set_mac_addr(struct net_device
*dev
, void *p
)
5258 struct sockaddr
*addr
= p
;
5260 if (!is_valid_ether_addr(addr
->sa_data
))
5263 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
5265 /* store the MAC address in CAM */
5266 return (do_s2io_prog_unicast(dev
, dev
->dev_addr
));
5269 * do_s2io_prog_unicast - Programs the Xframe mac address
5270 * @dev : pointer to the device structure.
5271 * @addr: a uchar pointer to the new mac address which is to be set.
5272 * Description : This procedure will program the Xframe to receive
5273 * frames with new Mac Address
5274 * Return value: SUCCESS on success and an appropriate (-)ve integer
5275 * as defined in errno.h file on failure.
5278 static int do_s2io_prog_unicast(struct net_device
*dev
, u8
*addr
)
5280 struct s2io_nic
*sp
= netdev_priv(dev
);
5281 register u64 mac_addr
= 0, perm_addr
= 0;
5284 struct config_param
*config
= &sp
->config
;
5287 * Set the new MAC address as the new unicast filter and reflect this
5288 * change on the device address registered with the OS. It will be
5291 for (i
= 0; i
< ETH_ALEN
; i
++) {
5293 mac_addr
|= addr
[i
];
5295 perm_addr
|= sp
->def_mac_addr
[0].mac_addr
[i
];
5298 /* check if the dev_addr is different than perm_addr */
5299 if (mac_addr
== perm_addr
)
5302 /* check if the mac already preset in CAM */
5303 for (i
= 1; i
< config
->max_mac_addr
; i
++) {
5304 tmp64
= do_s2io_read_unicast_mc(sp
, i
);
5305 if (tmp64
== S2IO_DISABLE_MAC_ENTRY
) /* CAM entry is empty */
5308 if (tmp64
== mac_addr
) {
5310 "MAC addr:0x%llx already present in CAM\n",
5311 (unsigned long long)mac_addr
);
5315 if (i
== config
->max_mac_addr
) {
5316 DBG_PRINT(ERR_DBG
, "CAM full no space left for Unicast MAC\n");
5319 /* Update the internal structure with this new mac address */
5320 do_s2io_copy_mac_addr(sp
, i
, mac_addr
);
5321 return (do_s2io_add_mac(sp
, mac_addr
, i
));
5325 * s2io_ethtool_sset - Sets different link parameters.
5326 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5327 * @info: pointer to the structure with parameters given by ethtool to set
5330 * The function sets different link parameters provided by the user onto
5336 static int s2io_ethtool_sset(struct net_device
*dev
,
5337 struct ethtool_cmd
*info
)
5339 struct s2io_nic
*sp
= netdev_priv(dev
);
5340 if ((info
->autoneg
== AUTONEG_ENABLE
) ||
5341 (info
->speed
!= SPEED_10000
) || (info
->duplex
!= DUPLEX_FULL
))
5344 s2io_close(sp
->dev
);
5352 * s2io_ethtol_gset - Return link specific information.
5353 * @sp : private member of the device structure, pointer to the
5354 * s2io_nic structure.
5355 * @info : pointer to the structure with parameters given by ethtool
5356 * to return link information.
5358 * Returns link specific information like speed, duplex etc.. to ethtool.
5360 * return 0 on success.
5363 static int s2io_ethtool_gset(struct net_device
*dev
, struct ethtool_cmd
*info
)
5365 struct s2io_nic
*sp
= netdev_priv(dev
);
5366 info
->supported
= (SUPPORTED_10000baseT_Full
| SUPPORTED_FIBRE
);
5367 info
->advertising
= (SUPPORTED_10000baseT_Full
| SUPPORTED_FIBRE
);
5368 info
->port
= PORT_FIBRE
;
5370 /* info->transceiver */
5371 info
->transceiver
= XCVR_EXTERNAL
;
5373 if (netif_carrier_ok(sp
->dev
)) {
5374 info
->speed
= 10000;
5375 info
->duplex
= DUPLEX_FULL
;
5381 info
->autoneg
= AUTONEG_DISABLE
;
5386 * s2io_ethtool_gdrvinfo - Returns driver specific information.
5387 * @sp : private member of the device structure, which is a pointer to the
5388 * s2io_nic structure.
5389 * @info : pointer to the structure with parameters given by ethtool to
5390 * return driver information.
5392 * Returns driver specefic information like name, version etc.. to ethtool.
5397 static void s2io_ethtool_gdrvinfo(struct net_device
*dev
,
5398 struct ethtool_drvinfo
*info
)
5400 struct s2io_nic
*sp
= netdev_priv(dev
);
5402 strncpy(info
->driver
, s2io_driver_name
, sizeof(info
->driver
));
5403 strncpy(info
->version
, s2io_driver_version
, sizeof(info
->version
));
5404 strncpy(info
->fw_version
, "", sizeof(info
->fw_version
));
5405 strncpy(info
->bus_info
, pci_name(sp
->pdev
), sizeof(info
->bus_info
));
5406 info
->regdump_len
= XENA_REG_SPACE
;
5407 info
->eedump_len
= XENA_EEPROM_SPACE
;
5411 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
5412 * @sp: private member of the device structure, which is a pointer to the
5413 * s2io_nic structure.
5414 * @regs : pointer to the structure with parameters given by ethtool for
5415 * dumping the registers.
5416 * @reg_space: The input argumnet into which all the registers are dumped.
5418 * Dumps the entire register space of xFrame NIC into the user given
5424 static void s2io_ethtool_gregs(struct net_device
*dev
,
5425 struct ethtool_regs
*regs
, void *space
)
5429 u8
*reg_space
= (u8
*) space
;
5430 struct s2io_nic
*sp
= netdev_priv(dev
);
5432 regs
->len
= XENA_REG_SPACE
;
5433 regs
->version
= sp
->pdev
->subsystem_device
;
5435 for (i
= 0; i
< regs
->len
; i
+= 8) {
5436 reg
= readq(sp
->bar0
+ i
);
5437 memcpy((reg_space
+ i
), ®
, 8);
5442 * s2io_phy_id - timer function that alternates adapter LED.
5443 * @data : address of the private member of the device structure, which
5444 * is a pointer to the s2io_nic structure, provided as an u32.
5445 * Description: This is actually the timer function that alternates the
5446 * adapter LED bit of the adapter control bit to set/reset every time on
5447 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
5448 * once every second.
5450 static void s2io_phy_id(unsigned long data
)
5452 struct s2io_nic
*sp
= (struct s2io_nic
*) data
;
5453 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5457 subid
= sp
->pdev
->subsystem_device
;
5458 if ((sp
->device_type
== XFRAME_II_DEVICE
) ||
5459 ((subid
& 0xFF) >= 0x07)) {
5460 val64
= readq(&bar0
->gpio_control
);
5461 val64
^= GPIO_CTRL_GPIO_0
;
5462 writeq(val64
, &bar0
->gpio_control
);
5464 val64
= readq(&bar0
->adapter_control
);
5465 val64
^= ADAPTER_LED_ON
;
5466 writeq(val64
, &bar0
->adapter_control
);
5469 mod_timer(&sp
->id_timer
, jiffies
+ HZ
/ 2);
5473 * s2io_ethtool_idnic - To physically identify the nic on the system.
5474 * @sp : private member of the device structure, which is a pointer to the
5475 * s2io_nic structure.
5476 * @id : pointer to the structure with identification parameters given by
5478 * Description: Used to physically identify the NIC on the system.
5479 * The Link LED will blink for a time specified by the user for
5481 * NOTE: The Link has to be Up to be able to blink the LED. Hence
5482 * identification is possible only if it's link is up.
5484 * int , returns 0 on success
5487 static int s2io_ethtool_idnic(struct net_device
*dev
, u32 data
)
5489 u64 val64
= 0, last_gpio_ctrl_val
;
5490 struct s2io_nic
*sp
= netdev_priv(dev
);
5491 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5494 subid
= sp
->pdev
->subsystem_device
;
5495 last_gpio_ctrl_val
= readq(&bar0
->gpio_control
);
5496 if ((sp
->device_type
== XFRAME_I_DEVICE
) &&
5497 ((subid
& 0xFF) < 0x07)) {
5498 val64
= readq(&bar0
->adapter_control
);
5499 if (!(val64
& ADAPTER_CNTL_EN
)) {
5501 "Adapter Link down, cannot blink LED\n");
5505 if (sp
->id_timer
.function
== NULL
) {
5506 init_timer(&sp
->id_timer
);
5507 sp
->id_timer
.function
= s2io_phy_id
;
5508 sp
->id_timer
.data
= (unsigned long) sp
;
5510 mod_timer(&sp
->id_timer
, jiffies
);
5512 msleep_interruptible(data
* HZ
);
5514 msleep_interruptible(MAX_FLICKER_TIME
);
5515 del_timer_sync(&sp
->id_timer
);
5517 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp
->device_type
, subid
)) {
5518 writeq(last_gpio_ctrl_val
, &bar0
->gpio_control
);
5519 last_gpio_ctrl_val
= readq(&bar0
->gpio_control
);
5525 static void s2io_ethtool_gringparam(struct net_device
*dev
,
5526 struct ethtool_ringparam
*ering
)
5528 struct s2io_nic
*sp
= netdev_priv(dev
);
5529 int i
,tx_desc_count
=0,rx_desc_count
=0;
5531 if (sp
->rxd_mode
== RXD_MODE_1
)
5532 ering
->rx_max_pending
= MAX_RX_DESC_1
;
5533 else if (sp
->rxd_mode
== RXD_MODE_3B
)
5534 ering
->rx_max_pending
= MAX_RX_DESC_2
;
5536 ering
->tx_max_pending
= MAX_TX_DESC
;
5537 for (i
= 0 ; i
< sp
->config
.tx_fifo_num
; i
++)
5538 tx_desc_count
+= sp
->config
.tx_cfg
[i
].fifo_len
;
5540 DBG_PRINT(INFO_DBG
,"\nmax txds : %d\n",sp
->config
.max_txds
);
5541 ering
->tx_pending
= tx_desc_count
;
5543 for (i
= 0 ; i
< sp
->config
.rx_ring_num
; i
++)
5544 rx_desc_count
+= sp
->config
.rx_cfg
[i
].num_rxd
;
5546 ering
->rx_pending
= rx_desc_count
;
5548 ering
->rx_mini_max_pending
= 0;
5549 ering
->rx_mini_pending
= 0;
5550 if(sp
->rxd_mode
== RXD_MODE_1
)
5551 ering
->rx_jumbo_max_pending
= MAX_RX_DESC_1
;
5552 else if (sp
->rxd_mode
== RXD_MODE_3B
)
5553 ering
->rx_jumbo_max_pending
= MAX_RX_DESC_2
;
5554 ering
->rx_jumbo_pending
= rx_desc_count
;
5558 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
5559 * @sp : private member of the device structure, which is a pointer to the
5560 * s2io_nic structure.
5561 * @ep : pointer to the structure with pause parameters given by ethtool.
5563 * Returns the Pause frame generation and reception capability of the NIC.
5567 static void s2io_ethtool_getpause_data(struct net_device
*dev
,
5568 struct ethtool_pauseparam
*ep
)
5571 struct s2io_nic
*sp
= netdev_priv(dev
);
5572 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5574 val64
= readq(&bar0
->rmac_pause_cfg
);
5575 if (val64
& RMAC_PAUSE_GEN_ENABLE
)
5576 ep
->tx_pause
= TRUE
;
5577 if (val64
& RMAC_PAUSE_RX_ENABLE
)
5578 ep
->rx_pause
= TRUE
;
5579 ep
->autoneg
= FALSE
;
5583 * s2io_ethtool_setpause_data - set/reset pause frame generation.
5584 * @sp : private member of the device structure, which is a pointer to the
5585 * s2io_nic structure.
5586 * @ep : pointer to the structure with pause parameters given by ethtool.
5588 * It can be used to set or reset Pause frame generation or reception
5589 * support of the NIC.
5591 * int, returns 0 on Success
5594 static int s2io_ethtool_setpause_data(struct net_device
*dev
,
5595 struct ethtool_pauseparam
*ep
)
5598 struct s2io_nic
*sp
= netdev_priv(dev
);
5599 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5601 val64
= readq(&bar0
->rmac_pause_cfg
);
5603 val64
|= RMAC_PAUSE_GEN_ENABLE
;
5605 val64
&= ~RMAC_PAUSE_GEN_ENABLE
;
5607 val64
|= RMAC_PAUSE_RX_ENABLE
;
5609 val64
&= ~RMAC_PAUSE_RX_ENABLE
;
5610 writeq(val64
, &bar0
->rmac_pause_cfg
);
5615 * read_eeprom - reads 4 bytes of data from user given offset.
5616 * @sp : private member of the device structure, which is a pointer to the
5617 * s2io_nic structure.
5618 * @off : offset at which the data must be written
5619 * @data : Its an output parameter where the data read at the given
5622 * Will read 4 bytes of data from the user given offset and return the
5624 * NOTE: Will allow to read only part of the EEPROM visible through the
5627 * -1 on failure and 0 on success.
5630 #define S2IO_DEV_ID 5
5631 static int read_eeprom(struct s2io_nic
* sp
, int off
, u64
* data
)
5636 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5638 if (sp
->device_type
== XFRAME_I_DEVICE
) {
5639 val64
= I2C_CONTROL_DEV_ID(S2IO_DEV_ID
) | I2C_CONTROL_ADDR(off
) |
5640 I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ
|
5641 I2C_CONTROL_CNTL_START
;
5642 SPECIAL_REG_WRITE(val64
, &bar0
->i2c_control
, LF
);
5644 while (exit_cnt
< 5) {
5645 val64
= readq(&bar0
->i2c_control
);
5646 if (I2C_CONTROL_CNTL_END(val64
)) {
5647 *data
= I2C_CONTROL_GET_DATA(val64
);
5656 if (sp
->device_type
== XFRAME_II_DEVICE
) {
5657 val64
= SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1
|
5658 SPI_CONTROL_BYTECNT(0x3) |
5659 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off
);
5660 SPECIAL_REG_WRITE(val64
, &bar0
->spi_control
, LF
);
5661 val64
|= SPI_CONTROL_REQ
;
5662 SPECIAL_REG_WRITE(val64
, &bar0
->spi_control
, LF
);
5663 while (exit_cnt
< 5) {
5664 val64
= readq(&bar0
->spi_control
);
5665 if (val64
& SPI_CONTROL_NACK
) {
5668 } else if (val64
& SPI_CONTROL_DONE
) {
5669 *data
= readq(&bar0
->spi_data
);
5682 * write_eeprom - actually writes the relevant part of the data value.
5683 * @sp : private member of the device structure, which is a pointer to the
5684 * s2io_nic structure.
5685 * @off : offset at which the data must be written
5686 * @data : The data that is to be written
5687 * @cnt : Number of bytes of the data that are actually to be written into
5688 * the Eeprom. (max of 3)
5690 * Actually writes the relevant part of the data value into the Eeprom
5691 * through the I2C bus.
5693 * 0 on success, -1 on failure.
5696 static int write_eeprom(struct s2io_nic
* sp
, int off
, u64 data
, int cnt
)
5698 int exit_cnt
= 0, ret
= -1;
5700 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5702 if (sp
->device_type
== XFRAME_I_DEVICE
) {
5703 val64
= I2C_CONTROL_DEV_ID(S2IO_DEV_ID
) | I2C_CONTROL_ADDR(off
) |
5704 I2C_CONTROL_BYTE_CNT(cnt
) | I2C_CONTROL_SET_DATA((u32
)data
) |
5705 I2C_CONTROL_CNTL_START
;
5706 SPECIAL_REG_WRITE(val64
, &bar0
->i2c_control
, LF
);
5708 while (exit_cnt
< 5) {
5709 val64
= readq(&bar0
->i2c_control
);
5710 if (I2C_CONTROL_CNTL_END(val64
)) {
5711 if (!(val64
& I2C_CONTROL_NACK
))
5720 if (sp
->device_type
== XFRAME_II_DEVICE
) {
5721 int write_cnt
= (cnt
== 8) ? 0 : cnt
;
5722 writeq(SPI_DATA_WRITE(data
,(cnt
<<3)), &bar0
->spi_data
);
5724 val64
= SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1
|
5725 SPI_CONTROL_BYTECNT(write_cnt
) |
5726 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off
);
5727 SPECIAL_REG_WRITE(val64
, &bar0
->spi_control
, LF
);
5728 val64
|= SPI_CONTROL_REQ
;
5729 SPECIAL_REG_WRITE(val64
, &bar0
->spi_control
, LF
);
5730 while (exit_cnt
< 5) {
5731 val64
= readq(&bar0
->spi_control
);
5732 if (val64
& SPI_CONTROL_NACK
) {
5735 } else if (val64
& SPI_CONTROL_DONE
) {
5745 static void s2io_vpd_read(struct s2io_nic
*nic
)
5749 int i
=0, cnt
, fail
= 0;
5750 int vpd_addr
= 0x80;
5752 if (nic
->device_type
== XFRAME_II_DEVICE
) {
5753 strcpy(nic
->product_name
, "Xframe II 10GbE network adapter");
5757 strcpy(nic
->product_name
, "Xframe I 10GbE network adapter");
5760 strcpy(nic
->serial_num
, "NOT AVAILABLE");
5762 vpd_data
= kmalloc(256, GFP_KERNEL
);
5764 nic
->mac_control
.stats_info
->sw_stat
.mem_alloc_fail_cnt
++;
5767 nic
->mac_control
.stats_info
->sw_stat
.mem_allocated
+= 256;
5769 for (i
= 0; i
< 256; i
+=4 ) {
5770 pci_write_config_byte(nic
->pdev
, (vpd_addr
+ 2), i
);
5771 pci_read_config_byte(nic
->pdev
, (vpd_addr
+ 2), &data
);
5772 pci_write_config_byte(nic
->pdev
, (vpd_addr
+ 3), 0);
5773 for (cnt
= 0; cnt
<5; cnt
++) {
5775 pci_read_config_byte(nic
->pdev
, (vpd_addr
+ 3), &data
);
5780 DBG_PRINT(ERR_DBG
, "Read of VPD data failed\n");
5784 pci_read_config_dword(nic
->pdev
, (vpd_addr
+ 4),
5785 (u32
*)&vpd_data
[i
]);
5789 /* read serial number of adapter */
5790 for (cnt
= 0; cnt
< 256; cnt
++) {
5791 if ((vpd_data
[cnt
] == 'S') &&
5792 (vpd_data
[cnt
+1] == 'N') &&
5793 (vpd_data
[cnt
+2] < VPD_STRING_LEN
)) {
5794 memset(nic
->serial_num
, 0, VPD_STRING_LEN
);
5795 memcpy(nic
->serial_num
, &vpd_data
[cnt
+ 3],
5802 if ((!fail
) && (vpd_data
[1] < VPD_STRING_LEN
)) {
5803 memset(nic
->product_name
, 0, vpd_data
[1]);
5804 memcpy(nic
->product_name
, &vpd_data
[3], vpd_data
[1]);
5807 nic
->mac_control
.stats_info
->sw_stat
.mem_freed
+= 256;
5811 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5812 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5813 * @eeprom : pointer to the user level structure provided by ethtool,
5814 * containing all relevant information.
5815 * @data_buf : user defined value to be written into Eeprom.
5816 * Description: Reads the values stored in the Eeprom at given offset
5817 * for a given length. Stores these values int the input argument data
5818 * buffer 'data_buf' and returns these to the caller (ethtool.)
5823 static int s2io_ethtool_geeprom(struct net_device
*dev
,
5824 struct ethtool_eeprom
*eeprom
, u8
* data_buf
)
5828 struct s2io_nic
*sp
= netdev_priv(dev
);
5830 eeprom
->magic
= sp
->pdev
->vendor
| (sp
->pdev
->device
<< 16);
5832 if ((eeprom
->offset
+ eeprom
->len
) > (XENA_EEPROM_SPACE
))
5833 eeprom
->len
= XENA_EEPROM_SPACE
- eeprom
->offset
;
5835 for (i
= 0; i
< eeprom
->len
; i
+= 4) {
5836 if (read_eeprom(sp
, (eeprom
->offset
+ i
), &data
)) {
5837 DBG_PRINT(ERR_DBG
, "Read of EEPROM failed\n");
5841 memcpy((data_buf
+ i
), &valid
, 4);
5847 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5848 * @sp : private member of the device structure, which is a pointer to the
5849 * s2io_nic structure.
5850 * @eeprom : pointer to the user level structure provided by ethtool,
5851 * containing all relevant information.
5852 * @data_buf ; user defined value to be written into Eeprom.
5854 * Tries to write the user provided value in the Eeprom, at the offset
5855 * given by the user.
5857 * 0 on success, -EFAULT on failure.
5860 static int s2io_ethtool_seeprom(struct net_device
*dev
,
5861 struct ethtool_eeprom
*eeprom
,
5864 int len
= eeprom
->len
, cnt
= 0;
5865 u64 valid
= 0, data
;
5866 struct s2io_nic
*sp
= netdev_priv(dev
);
5868 if (eeprom
->magic
!= (sp
->pdev
->vendor
| (sp
->pdev
->device
<< 16))) {
5870 "ETHTOOL_WRITE_EEPROM Err: Magic value ");
5871 DBG_PRINT(ERR_DBG
, "is wrong, Its not 0x%x\n",
5877 data
= (u32
) data_buf
[cnt
] & 0x000000FF;
5879 valid
= (u32
) (data
<< 24);
5883 if (write_eeprom(sp
, (eeprom
->offset
+ cnt
), valid
, 0)) {
5885 "ETHTOOL_WRITE_EEPROM Err: Cannot ");
5887 "write into the specified offset\n");
5898 * s2io_register_test - reads and writes into all clock domains.
5899 * @sp : private member of the device structure, which is a pointer to the
5900 * s2io_nic structure.
5901 * @data : variable that returns the result of each of the test conducted b
5904 * Read and write into all clock domains. The NIC has 3 clock domains,
5905 * see that registers in all the three regions are accessible.
5910 static int s2io_register_test(struct s2io_nic
* sp
, uint64_t * data
)
5912 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5913 u64 val64
= 0, exp_val
;
5916 val64
= readq(&bar0
->pif_rd_swapper_fb
);
5917 if (val64
!= 0x123456789abcdefULL
) {
5919 DBG_PRINT(INFO_DBG
, "Read Test level 1 fails\n");
5922 val64
= readq(&bar0
->rmac_pause_cfg
);
5923 if (val64
!= 0xc000ffff00000000ULL
) {
5925 DBG_PRINT(INFO_DBG
, "Read Test level 2 fails\n");
5928 val64
= readq(&bar0
->rx_queue_cfg
);
5929 if (sp
->device_type
== XFRAME_II_DEVICE
)
5930 exp_val
= 0x0404040404040404ULL
;
5932 exp_val
= 0x0808080808080808ULL
;
5933 if (val64
!= exp_val
) {
5935 DBG_PRINT(INFO_DBG
, "Read Test level 3 fails\n");
5938 val64
= readq(&bar0
->xgxs_efifo_cfg
);
5939 if (val64
!= 0x000000001923141EULL
) {
5941 DBG_PRINT(INFO_DBG
, "Read Test level 4 fails\n");
5944 val64
= 0x5A5A5A5A5A5A5A5AULL
;
5945 writeq(val64
, &bar0
->xmsi_data
);
5946 val64
= readq(&bar0
->xmsi_data
);
5947 if (val64
!= 0x5A5A5A5A5A5A5A5AULL
) {
5949 DBG_PRINT(ERR_DBG
, "Write Test level 1 fails\n");
5952 val64
= 0xA5A5A5A5A5A5A5A5ULL
;
5953 writeq(val64
, &bar0
->xmsi_data
);
5954 val64
= readq(&bar0
->xmsi_data
);
5955 if (val64
!= 0xA5A5A5A5A5A5A5A5ULL
) {
5957 DBG_PRINT(ERR_DBG
, "Write Test level 2 fails\n");
5965 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
5966 * @sp : private member of the device structure, which is a pointer to the
5967 * s2io_nic structure.
5968 * @data:variable that returns the result of each of the test conducted by
5971 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
5977 static int s2io_eeprom_test(struct s2io_nic
* sp
, uint64_t * data
)
5980 u64 ret_data
, org_4F0
, org_7F0
;
5981 u8 saved_4F0
= 0, saved_7F0
= 0;
5982 struct net_device
*dev
= sp
->dev
;
5984 /* Test Write Error at offset 0 */
5985 /* Note that SPI interface allows write access to all areas
5986 * of EEPROM. Hence doing all negative testing only for Xframe I.
5988 if (sp
->device_type
== XFRAME_I_DEVICE
)
5989 if (!write_eeprom(sp
, 0, 0, 3))
5992 /* Save current values at offsets 0x4F0 and 0x7F0 */
5993 if (!read_eeprom(sp
, 0x4F0, &org_4F0
))
5995 if (!read_eeprom(sp
, 0x7F0, &org_7F0
))
5998 /* Test Write at offset 4f0 */
5999 if (write_eeprom(sp
, 0x4F0, 0x012345, 3))
6001 if (read_eeprom(sp
, 0x4F0, &ret_data
))
6004 if (ret_data
!= 0x012345) {
6005 DBG_PRINT(ERR_DBG
, "%s: eeprom test error at offset 0x4F0. "
6006 "Data written %llx Data read %llx\n",
6007 dev
->name
, (unsigned long long)0x12345,
6008 (unsigned long long)ret_data
);
6012 /* Reset the EEPROM data go FFFF */
6013 write_eeprom(sp
, 0x4F0, 0xFFFFFF, 3);
6015 /* Test Write Request Error at offset 0x7c */
6016 if (sp
->device_type
== XFRAME_I_DEVICE
)
6017 if (!write_eeprom(sp
, 0x07C, 0, 3))
6020 /* Test Write Request at offset 0x7f0 */
6021 if (write_eeprom(sp
, 0x7F0, 0x012345, 3))
6023 if (read_eeprom(sp
, 0x7F0, &ret_data
))
6026 if (ret_data
!= 0x012345) {
6027 DBG_PRINT(ERR_DBG
, "%s: eeprom test error at offset 0x7F0. "
6028 "Data written %llx Data read %llx\n",
6029 dev
->name
, (unsigned long long)0x12345,
6030 (unsigned long long)ret_data
);
6034 /* Reset the EEPROM data go FFFF */
6035 write_eeprom(sp
, 0x7F0, 0xFFFFFF, 3);
6037 if (sp
->device_type
== XFRAME_I_DEVICE
) {
6038 /* Test Write Error at offset 0x80 */
6039 if (!write_eeprom(sp
, 0x080, 0, 3))
6042 /* Test Write Error at offset 0xfc */
6043 if (!write_eeprom(sp
, 0x0FC, 0, 3))
6046 /* Test Write Error at offset 0x100 */
6047 if (!write_eeprom(sp
, 0x100, 0, 3))
6050 /* Test Write Error at offset 4ec */
6051 if (!write_eeprom(sp
, 0x4EC, 0, 3))
6055 /* Restore values at offsets 0x4F0 and 0x7F0 */
6057 write_eeprom(sp
, 0x4F0, org_4F0
, 3);
6059 write_eeprom(sp
, 0x7F0, org_7F0
, 3);
6066 * s2io_bist_test - invokes the MemBist test of the card .
6067 * @sp : private member of the device structure, which is a pointer to the
6068 * s2io_nic structure.
6069 * @data:variable that returns the result of each of the test conducted by
6072 * This invokes the MemBist test of the card. We give around
6073 * 2 secs time for the Test to complete. If it's still not complete
6074 * within this peiod, we consider that the test failed.
6076 * 0 on success and -1 on failure.
6079 static int s2io_bist_test(struct s2io_nic
* sp
, uint64_t * data
)
6082 int cnt
= 0, ret
= -1;
6084 pci_read_config_byte(sp
->pdev
, PCI_BIST
, &bist
);
6085 bist
|= PCI_BIST_START
;
6086 pci_write_config_word(sp
->pdev
, PCI_BIST
, bist
);
6089 pci_read_config_byte(sp
->pdev
, PCI_BIST
, &bist
);
6090 if (!(bist
& PCI_BIST_START
)) {
6091 *data
= (bist
& PCI_BIST_CODE_MASK
);
6103 * s2io-link_test - verifies the link state of the nic
6104 * @sp ; private member of the device structure, which is a pointer to the
6105 * s2io_nic structure.
6106 * @data: variable that returns the result of each of the test conducted by
6109 * The function verifies the link state of the NIC and updates the input
6110 * argument 'data' appropriately.
6115 static int s2io_link_test(struct s2io_nic
* sp
, uint64_t * data
)
6117 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
6120 val64
= readq(&bar0
->adapter_status
);
6121 if(!(LINK_IS_UP(val64
)))
6130 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
6131 * @sp - private member of the device structure, which is a pointer to the
6132 * s2io_nic structure.
6133 * @data - variable that returns the result of each of the test
6134 * conducted by the driver.
6136 * This is one of the offline test that tests the read and write
6137 * access to the RldRam chip on the NIC.
6142 static int s2io_rldram_test(struct s2io_nic
* sp
, uint64_t * data
)
6144 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
6146 int cnt
, iteration
= 0, test_fail
= 0;
6148 val64
= readq(&bar0
->adapter_control
);
6149 val64
&= ~ADAPTER_ECC_EN
;
6150 writeq(val64
, &bar0
->adapter_control
);
6152 val64
= readq(&bar0
->mc_rldram_test_ctrl
);
6153 val64
|= MC_RLDRAM_TEST_MODE
;
6154 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_test_ctrl
, LF
);
6156 val64
= readq(&bar0
->mc_rldram_mrs
);
6157 val64
|= MC_RLDRAM_QUEUE_SIZE_ENABLE
;
6158 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_mrs
, UF
);
6160 val64
|= MC_RLDRAM_MRS_ENABLE
;
6161 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_mrs
, UF
);
6163 while (iteration
< 2) {
6164 val64
= 0x55555555aaaa0000ULL
;
6165 if (iteration
== 1) {
6166 val64
^= 0xFFFFFFFFFFFF0000ULL
;
6168 writeq(val64
, &bar0
->mc_rldram_test_d0
);
6170 val64
= 0xaaaa5a5555550000ULL
;
6171 if (iteration
== 1) {
6172 val64
^= 0xFFFFFFFFFFFF0000ULL
;
6174 writeq(val64
, &bar0
->mc_rldram_test_d1
);
6176 val64
= 0x55aaaaaaaa5a0000ULL
;
6177 if (iteration
== 1) {
6178 val64
^= 0xFFFFFFFFFFFF0000ULL
;
6180 writeq(val64
, &bar0
->mc_rldram_test_d2
);
6182 val64
= (u64
) (0x0000003ffffe0100ULL
);
6183 writeq(val64
, &bar0
->mc_rldram_test_add
);
6185 val64
= MC_RLDRAM_TEST_MODE
| MC_RLDRAM_TEST_WRITE
|
6187 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_test_ctrl
, LF
);
6189 for (cnt
= 0; cnt
< 5; cnt
++) {
6190 val64
= readq(&bar0
->mc_rldram_test_ctrl
);
6191 if (val64
& MC_RLDRAM_TEST_DONE
)
6199 val64
= MC_RLDRAM_TEST_MODE
| MC_RLDRAM_TEST_GO
;
6200 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_test_ctrl
, LF
);
6202 for (cnt
= 0; cnt
< 5; cnt
++) {
6203 val64
= readq(&bar0
->mc_rldram_test_ctrl
);
6204 if (val64
& MC_RLDRAM_TEST_DONE
)
6212 val64
= readq(&bar0
->mc_rldram_test_ctrl
);
6213 if (!(val64
& MC_RLDRAM_TEST_PASS
))
6221 /* Bring the adapter out of test mode */
6222 SPECIAL_REG_WRITE(0, &bar0
->mc_rldram_test_ctrl
, LF
);
6228 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6229 * @sp : private member of the device structure, which is a pointer to the
6230 * s2io_nic structure.
6231 * @ethtest : pointer to a ethtool command specific structure that will be
6232 * returned to the user.
6233 * @data : variable that returns the result of each of the test
6234 * conducted by the driver.
6236 * This function conducts 6 tests ( 4 offline and 2 online) to determine
6237 * the health of the card.
6242 static void s2io_ethtool_test(struct net_device
*dev
,
6243 struct ethtool_test
*ethtest
,
6246 struct s2io_nic
*sp
= netdev_priv(dev
);
6247 int orig_state
= netif_running(sp
->dev
);
6249 if (ethtest
->flags
== ETH_TEST_FL_OFFLINE
) {
6250 /* Offline Tests. */
6252 s2io_close(sp
->dev
);
6254 if (s2io_register_test(sp
, &data
[0]))
6255 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
6259 if (s2io_rldram_test(sp
, &data
[3]))
6260 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
6264 if (s2io_eeprom_test(sp
, &data
[1]))
6265 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
6267 if (s2io_bist_test(sp
, &data
[4]))
6268 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
6278 "%s: is not up, cannot run test\n",
6287 if (s2io_link_test(sp
, &data
[2]))
6288 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
6297 static void s2io_get_ethtool_stats(struct net_device
*dev
,
6298 struct ethtool_stats
*estats
,
6302 struct s2io_nic
*sp
= netdev_priv(dev
);
6303 struct stat_block
*stat_info
= sp
->mac_control
.stats_info
;
6305 s2io_updt_stats(sp
);
6307 (u64
)le32_to_cpu(stat_info
->tmac_frms_oflow
) << 32 |
6308 le32_to_cpu(stat_info
->tmac_frms
);
6310 (u64
)le32_to_cpu(stat_info
->tmac_data_octets_oflow
) << 32 |
6311 le32_to_cpu(stat_info
->tmac_data_octets
);
6312 tmp_stats
[i
++] = le64_to_cpu(stat_info
->tmac_drop_frms
);
6314 (u64
)le32_to_cpu(stat_info
->tmac_mcst_frms_oflow
) << 32 |
6315 le32_to_cpu(stat_info
->tmac_mcst_frms
);
6317 (u64
)le32_to_cpu(stat_info
->tmac_bcst_frms_oflow
) << 32 |
6318 le32_to_cpu(stat_info
->tmac_bcst_frms
);
6319 tmp_stats
[i
++] = le64_to_cpu(stat_info
->tmac_pause_ctrl_frms
);
6321 (u64
)le32_to_cpu(stat_info
->tmac_ttl_octets_oflow
) << 32 |
6322 le32_to_cpu(stat_info
->tmac_ttl_octets
);
6324 (u64
)le32_to_cpu(stat_info
->tmac_ucst_frms_oflow
) << 32 |
6325 le32_to_cpu(stat_info
->tmac_ucst_frms
);
6327 (u64
)le32_to_cpu(stat_info
->tmac_nucst_frms_oflow
) << 32 |
6328 le32_to_cpu(stat_info
->tmac_nucst_frms
);
6330 (u64
)le32_to_cpu(stat_info
->tmac_any_err_frms_oflow
) << 32 |
6331 le32_to_cpu(stat_info
->tmac_any_err_frms
);
6332 tmp_stats
[i
++] = le64_to_cpu(stat_info
->tmac_ttl_less_fb_octets
);
6333 tmp_stats
[i
++] = le64_to_cpu(stat_info
->tmac_vld_ip_octets
);
6335 (u64
)le32_to_cpu(stat_info
->tmac_vld_ip_oflow
) << 32 |
6336 le32_to_cpu(stat_info
->tmac_vld_ip
);
6338 (u64
)le32_to_cpu(stat_info
->tmac_drop_ip_oflow
) << 32 |
6339 le32_to_cpu(stat_info
->tmac_drop_ip
);
6341 (u64
)le32_to_cpu(stat_info
->tmac_icmp_oflow
) << 32 |
6342 le32_to_cpu(stat_info
->tmac_icmp
);
6344 (u64
)le32_to_cpu(stat_info
->tmac_rst_tcp_oflow
) << 32 |
6345 le32_to_cpu(stat_info
->tmac_rst_tcp
);
6346 tmp_stats
[i
++] = le64_to_cpu(stat_info
->tmac_tcp
);
6347 tmp_stats
[i
++] = (u64
)le32_to_cpu(stat_info
->tmac_udp_oflow
) << 32 |
6348 le32_to_cpu(stat_info
->tmac_udp
);
6350 (u64
)le32_to_cpu(stat_info
->rmac_vld_frms_oflow
) << 32 |
6351 le32_to_cpu(stat_info
->rmac_vld_frms
);
6353 (u64
)le32_to_cpu(stat_info
->rmac_data_octets_oflow
) << 32 |
6354 le32_to_cpu(stat_info
->rmac_data_octets
);
6355 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_fcs_err_frms
);
6356 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_drop_frms
);
6358 (u64
)le32_to_cpu(stat_info
->rmac_vld_mcst_frms_oflow
) << 32 |
6359 le32_to_cpu(stat_info
->rmac_vld_mcst_frms
);
6361 (u64
)le32_to_cpu(stat_info
->rmac_vld_bcst_frms_oflow
) << 32 |
6362 le32_to_cpu(stat_info
->rmac_vld_bcst_frms
);
6363 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_in_rng_len_err_frms
);
6364 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_out_rng_len_err_frms
);
6365 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_long_frms
);
6366 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_pause_ctrl_frms
);
6367 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_unsup_ctrl_frms
);
6369 (u64
)le32_to_cpu(stat_info
->rmac_ttl_octets_oflow
) << 32 |
6370 le32_to_cpu(stat_info
->rmac_ttl_octets
);
6372 (u64
)le32_to_cpu(stat_info
->rmac_accepted_ucst_frms_oflow
)
6373 << 32 | le32_to_cpu(stat_info
->rmac_accepted_ucst_frms
);
6375 (u64
)le32_to_cpu(stat_info
->rmac_accepted_nucst_frms_oflow
)
6376 << 32 | le32_to_cpu(stat_info
->rmac_accepted_nucst_frms
);
6378 (u64
)le32_to_cpu(stat_info
->rmac_discarded_frms_oflow
) << 32 |
6379 le32_to_cpu(stat_info
->rmac_discarded_frms
);
6381 (u64
)le32_to_cpu(stat_info
->rmac_drop_events_oflow
)
6382 << 32 | le32_to_cpu(stat_info
->rmac_drop_events
);
6383 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_less_fb_octets
);
6384 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_frms
);
6386 (u64
)le32_to_cpu(stat_info
->rmac_usized_frms_oflow
) << 32 |
6387 le32_to_cpu(stat_info
->rmac_usized_frms
);
6389 (u64
)le32_to_cpu(stat_info
->rmac_osized_frms_oflow
) << 32 |
6390 le32_to_cpu(stat_info
->rmac_osized_frms
);
6392 (u64
)le32_to_cpu(stat_info
->rmac_frag_frms_oflow
) << 32 |
6393 le32_to_cpu(stat_info
->rmac_frag_frms
);
6395 (u64
)le32_to_cpu(stat_info
->rmac_jabber_frms_oflow
) << 32 |
6396 le32_to_cpu(stat_info
->rmac_jabber_frms
);
6397 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_64_frms
);
6398 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_65_127_frms
);
6399 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_128_255_frms
);
6400 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_256_511_frms
);
6401 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_512_1023_frms
);
6402 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_1024_1518_frms
);
6404 (u64
)le32_to_cpu(stat_info
->rmac_ip_oflow
) << 32 |
6405 le32_to_cpu(stat_info
->rmac_ip
);
6406 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ip_octets
);
6407 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_hdr_err_ip
);
6409 (u64
)le32_to_cpu(stat_info
->rmac_drop_ip_oflow
) << 32 |
6410 le32_to_cpu(stat_info
->rmac_drop_ip
);
6412 (u64
)le32_to_cpu(stat_info
->rmac_icmp_oflow
) << 32 |
6413 le32_to_cpu(stat_info
->rmac_icmp
);
6414 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_tcp
);
6416 (u64
)le32_to_cpu(stat_info
->rmac_udp_oflow
) << 32 |
6417 le32_to_cpu(stat_info
->rmac_udp
);
6419 (u64
)le32_to_cpu(stat_info
->rmac_err_drp_udp_oflow
) << 32 |
6420 le32_to_cpu(stat_info
->rmac_err_drp_udp
);
6421 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_xgmii_err_sym
);
6422 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q0
);
6423 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q1
);
6424 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q2
);
6425 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q3
);
6426 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q4
);
6427 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q5
);
6428 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q6
);
6429 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q7
);
6430 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q0
);
6431 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q1
);
6432 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q2
);
6433 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q3
);
6434 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q4
);
6435 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q5
);
6436 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q6
);
6437 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q7
);
6439 (u64
)le32_to_cpu(stat_info
->rmac_pause_cnt_oflow
) << 32 |
6440 le32_to_cpu(stat_info
->rmac_pause_cnt
);
6441 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_xgmii_data_err_cnt
);
6442 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_xgmii_ctrl_err_cnt
);
6444 (u64
)le32_to_cpu(stat_info
->rmac_accepted_ip_oflow
) << 32 |
6445 le32_to_cpu(stat_info
->rmac_accepted_ip
);
6446 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_err_tcp
);
6447 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rd_req_cnt
);
6448 tmp_stats
[i
++] = le32_to_cpu(stat_info
->new_rd_req_cnt
);
6449 tmp_stats
[i
++] = le32_to_cpu(stat_info
->new_rd_req_rtry_cnt
);
6450 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rd_rtry_cnt
);
6451 tmp_stats
[i
++] = le32_to_cpu(stat_info
->wr_rtry_rd_ack_cnt
);
6452 tmp_stats
[i
++] = le32_to_cpu(stat_info
->wr_req_cnt
);
6453 tmp_stats
[i
++] = le32_to_cpu(stat_info
->new_wr_req_cnt
);
6454 tmp_stats
[i
++] = le32_to_cpu(stat_info
->new_wr_req_rtry_cnt
);
6455 tmp_stats
[i
++] = le32_to_cpu(stat_info
->wr_rtry_cnt
);
6456 tmp_stats
[i
++] = le32_to_cpu(stat_info
->wr_disc_cnt
);
6457 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rd_rtry_wr_ack_cnt
);
6458 tmp_stats
[i
++] = le32_to_cpu(stat_info
->txp_wr_cnt
);
6459 tmp_stats
[i
++] = le32_to_cpu(stat_info
->txd_rd_cnt
);
6460 tmp_stats
[i
++] = le32_to_cpu(stat_info
->txd_wr_cnt
);
6461 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rxd_rd_cnt
);
6462 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rxd_wr_cnt
);
6463 tmp_stats
[i
++] = le32_to_cpu(stat_info
->txf_rd_cnt
);
6464 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rxf_wr_cnt
);
6466 /* Enhanced statistics exist only for Hercules */
6467 if(sp
->device_type
== XFRAME_II_DEVICE
) {
6469 le64_to_cpu(stat_info
->rmac_ttl_1519_4095_frms
);
6471 le64_to_cpu(stat_info
->rmac_ttl_4096_8191_frms
);
6473 le64_to_cpu(stat_info
->rmac_ttl_8192_max_frms
);
6474 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_gt_max_frms
);
6475 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_osized_alt_frms
);
6476 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_jabber_alt_frms
);
6477 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_gt_max_alt_frms
);
6478 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_vlan_frms
);
6479 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_len_discard
);
6480 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_fcs_discard
);
6481 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_pf_discard
);
6482 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_da_discard
);
6483 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_red_discard
);
6484 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_rts_discard
);
6485 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_ingm_full_discard
);
6486 tmp_stats
[i
++] = le32_to_cpu(stat_info
->link_fault_cnt
);
6490 tmp_stats
[i
++] = stat_info
->sw_stat
.single_ecc_errs
;
6491 tmp_stats
[i
++] = stat_info
->sw_stat
.double_ecc_errs
;
6492 tmp_stats
[i
++] = stat_info
->sw_stat
.parity_err_cnt
;
6493 tmp_stats
[i
++] = stat_info
->sw_stat
.serious_err_cnt
;
6494 tmp_stats
[i
++] = stat_info
->sw_stat
.soft_reset_cnt
;
6495 tmp_stats
[i
++] = stat_info
->sw_stat
.fifo_full_cnt
;
6496 for (k
= 0; k
< MAX_RX_RINGS
; k
++)
6497 tmp_stats
[i
++] = stat_info
->sw_stat
.ring_full_cnt
[k
];
6498 tmp_stats
[i
++] = stat_info
->xpak_stat
.alarm_transceiver_temp_high
;
6499 tmp_stats
[i
++] = stat_info
->xpak_stat
.alarm_transceiver_temp_low
;
6500 tmp_stats
[i
++] = stat_info
->xpak_stat
.alarm_laser_bias_current_high
;
6501 tmp_stats
[i
++] = stat_info
->xpak_stat
.alarm_laser_bias_current_low
;
6502 tmp_stats
[i
++] = stat_info
->xpak_stat
.alarm_laser_output_power_high
;
6503 tmp_stats
[i
++] = stat_info
->xpak_stat
.alarm_laser_output_power_low
;
6504 tmp_stats
[i
++] = stat_info
->xpak_stat
.warn_transceiver_temp_high
;
6505 tmp_stats
[i
++] = stat_info
->xpak_stat
.warn_transceiver_temp_low
;
6506 tmp_stats
[i
++] = stat_info
->xpak_stat
.warn_laser_bias_current_high
;
6507 tmp_stats
[i
++] = stat_info
->xpak_stat
.warn_laser_bias_current_low
;
6508 tmp_stats
[i
++] = stat_info
->xpak_stat
.warn_laser_output_power_high
;
6509 tmp_stats
[i
++] = stat_info
->xpak_stat
.warn_laser_output_power_low
;
6510 tmp_stats
[i
++] = stat_info
->sw_stat
.clubbed_frms_cnt
;
6511 tmp_stats
[i
++] = stat_info
->sw_stat
.sending_both
;
6512 tmp_stats
[i
++] = stat_info
->sw_stat
.outof_sequence_pkts
;
6513 tmp_stats
[i
++] = stat_info
->sw_stat
.flush_max_pkts
;
6514 if (stat_info
->sw_stat
.num_aggregations
) {
6515 u64 tmp
= stat_info
->sw_stat
.sum_avg_pkts_aggregated
;
6518 * Since 64-bit divide does not work on all platforms,
6519 * do repeated subtraction.
6521 while (tmp
>= stat_info
->sw_stat
.num_aggregations
) {
6522 tmp
-= stat_info
->sw_stat
.num_aggregations
;
6525 tmp_stats
[i
++] = count
;
6529 tmp_stats
[i
++] = stat_info
->sw_stat
.mem_alloc_fail_cnt
;
6530 tmp_stats
[i
++] = stat_info
->sw_stat
.pci_map_fail_cnt
;
6531 tmp_stats
[i
++] = stat_info
->sw_stat
.watchdog_timer_cnt
;
6532 tmp_stats
[i
++] = stat_info
->sw_stat
.mem_allocated
;
6533 tmp_stats
[i
++] = stat_info
->sw_stat
.mem_freed
;
6534 tmp_stats
[i
++] = stat_info
->sw_stat
.link_up_cnt
;
6535 tmp_stats
[i
++] = stat_info
->sw_stat
.link_down_cnt
;
6536 tmp_stats
[i
++] = stat_info
->sw_stat
.link_up_time
;
6537 tmp_stats
[i
++] = stat_info
->sw_stat
.link_down_time
;
6539 tmp_stats
[i
++] = stat_info
->sw_stat
.tx_buf_abort_cnt
;
6540 tmp_stats
[i
++] = stat_info
->sw_stat
.tx_desc_abort_cnt
;
6541 tmp_stats
[i
++] = stat_info
->sw_stat
.tx_parity_err_cnt
;
6542 tmp_stats
[i
++] = stat_info
->sw_stat
.tx_link_loss_cnt
;
6543 tmp_stats
[i
++] = stat_info
->sw_stat
.tx_list_proc_err_cnt
;
6545 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_parity_err_cnt
;
6546 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_abort_cnt
;
6547 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_parity_abort_cnt
;
6548 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_rda_fail_cnt
;
6549 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_unkn_prot_cnt
;
6550 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_fcs_err_cnt
;
6551 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_buf_size_err_cnt
;
6552 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_rxd_corrupt_cnt
;
6553 tmp_stats
[i
++] = stat_info
->sw_stat
.rx_unkn_err_cnt
;
6554 tmp_stats
[i
++] = stat_info
->sw_stat
.tda_err_cnt
;
6555 tmp_stats
[i
++] = stat_info
->sw_stat
.pfc_err_cnt
;
6556 tmp_stats
[i
++] = stat_info
->sw_stat
.pcc_err_cnt
;
6557 tmp_stats
[i
++] = stat_info
->sw_stat
.tti_err_cnt
;
6558 tmp_stats
[i
++] = stat_info
->sw_stat
.tpa_err_cnt
;
6559 tmp_stats
[i
++] = stat_info
->sw_stat
.sm_err_cnt
;
6560 tmp_stats
[i
++] = stat_info
->sw_stat
.lso_err_cnt
;
6561 tmp_stats
[i
++] = stat_info
->sw_stat
.mac_tmac_err_cnt
;
6562 tmp_stats
[i
++] = stat_info
->sw_stat
.mac_rmac_err_cnt
;
6563 tmp_stats
[i
++] = stat_info
->sw_stat
.xgxs_txgxs_err_cnt
;
6564 tmp_stats
[i
++] = stat_info
->sw_stat
.xgxs_rxgxs_err_cnt
;
6565 tmp_stats
[i
++] = stat_info
->sw_stat
.rc_err_cnt
;
6566 tmp_stats
[i
++] = stat_info
->sw_stat
.prc_pcix_err_cnt
;
6567 tmp_stats
[i
++] = stat_info
->sw_stat
.rpa_err_cnt
;
6568 tmp_stats
[i
++] = stat_info
->sw_stat
.rda_err_cnt
;
6569 tmp_stats
[i
++] = stat_info
->sw_stat
.rti_err_cnt
;
6570 tmp_stats
[i
++] = stat_info
->sw_stat
.mc_err_cnt
;
6573 static int s2io_ethtool_get_regs_len(struct net_device
*dev
)
6575 return (XENA_REG_SPACE
);
6579 static u32
s2io_ethtool_get_rx_csum(struct net_device
* dev
)
6581 struct s2io_nic
*sp
= netdev_priv(dev
);
6583 return (sp
->rx_csum
);
6586 static int s2io_ethtool_set_rx_csum(struct net_device
*dev
, u32 data
)
6588 struct s2io_nic
*sp
= netdev_priv(dev
);
6598 static int s2io_get_eeprom_len(struct net_device
*dev
)
6600 return (XENA_EEPROM_SPACE
);
6603 static int s2io_get_sset_count(struct net_device
*dev
, int sset
)
6605 struct s2io_nic
*sp
= netdev_priv(dev
);
6609 return S2IO_TEST_LEN
;
6611 switch(sp
->device_type
) {
6612 case XFRAME_I_DEVICE
:
6613 return XFRAME_I_STAT_LEN
;
6614 case XFRAME_II_DEVICE
:
6615 return XFRAME_II_STAT_LEN
;
6624 static void s2io_ethtool_get_strings(struct net_device
*dev
,
6625 u32 stringset
, u8
* data
)
6628 struct s2io_nic
*sp
= netdev_priv(dev
);
6630 switch (stringset
) {
6632 memcpy(data
, s2io_gstrings
, S2IO_STRINGS_LEN
);
6635 stat_size
= sizeof(ethtool_xena_stats_keys
);
6636 memcpy(data
, ðtool_xena_stats_keys
,stat_size
);
6637 if(sp
->device_type
== XFRAME_II_DEVICE
) {
6638 memcpy(data
+ stat_size
,
6639 ðtool_enhanced_stats_keys
,
6640 sizeof(ethtool_enhanced_stats_keys
));
6641 stat_size
+= sizeof(ethtool_enhanced_stats_keys
);
6644 memcpy(data
+ stat_size
, ðtool_driver_stats_keys
,
6645 sizeof(ethtool_driver_stats_keys
));
6649 static int s2io_ethtool_op_set_tx_csum(struct net_device
*dev
, u32 data
)
6652 dev
->features
|= NETIF_F_IP_CSUM
;
6654 dev
->features
&= ~NETIF_F_IP_CSUM
;
6659 static u32
s2io_ethtool_op_get_tso(struct net_device
*dev
)
6661 return (dev
->features
& NETIF_F_TSO
) != 0;
6663 static int s2io_ethtool_op_set_tso(struct net_device
*dev
, u32 data
)
6666 dev
->features
|= (NETIF_F_TSO
| NETIF_F_TSO6
);
6668 dev
->features
&= ~(NETIF_F_TSO
| NETIF_F_TSO6
);
6673 static const struct ethtool_ops netdev_ethtool_ops
= {
6674 .get_settings
= s2io_ethtool_gset
,
6675 .set_settings
= s2io_ethtool_sset
,
6676 .get_drvinfo
= s2io_ethtool_gdrvinfo
,
6677 .get_regs_len
= s2io_ethtool_get_regs_len
,
6678 .get_regs
= s2io_ethtool_gregs
,
6679 .get_link
= ethtool_op_get_link
,
6680 .get_eeprom_len
= s2io_get_eeprom_len
,
6681 .get_eeprom
= s2io_ethtool_geeprom
,
6682 .set_eeprom
= s2io_ethtool_seeprom
,
6683 .get_ringparam
= s2io_ethtool_gringparam
,
6684 .get_pauseparam
= s2io_ethtool_getpause_data
,
6685 .set_pauseparam
= s2io_ethtool_setpause_data
,
6686 .get_rx_csum
= s2io_ethtool_get_rx_csum
,
6687 .set_rx_csum
= s2io_ethtool_set_rx_csum
,
6688 .set_tx_csum
= s2io_ethtool_op_set_tx_csum
,
6689 .set_sg
= ethtool_op_set_sg
,
6690 .get_tso
= s2io_ethtool_op_get_tso
,
6691 .set_tso
= s2io_ethtool_op_set_tso
,
6692 .set_ufo
= ethtool_op_set_ufo
,
6693 .self_test
= s2io_ethtool_test
,
6694 .get_strings
= s2io_ethtool_get_strings
,
6695 .phys_id
= s2io_ethtool_idnic
,
6696 .get_ethtool_stats
= s2io_get_ethtool_stats
,
6697 .get_sset_count
= s2io_get_sset_count
,
6701 * s2io_ioctl - Entry point for the Ioctl
6702 * @dev : Device pointer.
6703 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6704 * a proprietary structure used to pass information to the driver.
6705 * @cmd : This is used to distinguish between the different commands that
6706 * can be passed to the IOCTL functions.
6708 * Currently there are no special functionality supported in IOCTL, hence
6709 * function always return EOPNOTSUPPORTED
6712 static int s2io_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
6718 * s2io_change_mtu - entry point to change MTU size for the device.
6719 * @dev : device pointer.
6720 * @new_mtu : the new MTU size for the device.
6721 * Description: A driver entry point to change MTU size for the device.
6722 * Before changing the MTU the device must be stopped.
6724 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6728 static int s2io_change_mtu(struct net_device
*dev
, int new_mtu
)
6730 struct s2io_nic
*sp
= netdev_priv(dev
);
6733 if ((new_mtu
< MIN_MTU
) || (new_mtu
> S2IO_JUMBO_SIZE
)) {
6734 DBG_PRINT(ERR_DBG
, "%s: MTU size is invalid.\n",
6740 if (netif_running(dev
)) {
6741 s2io_stop_all_tx_queue(sp
);
6743 ret
= s2io_card_up(sp
);
6745 DBG_PRINT(ERR_DBG
, "%s: Device bring up failed\n",
6749 s2io_wake_all_tx_queue(sp
);
6750 } else { /* Device is down */
6751 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
6752 u64 val64
= new_mtu
;
6754 writeq(vBIT(val64
, 2, 14), &bar0
->rmac_max_pyld_len
);
6761 * s2io_set_link - Set the LInk status
6762 * @data: long pointer to device private structue
6763 * Description: Sets the link status for the adapter
6766 static void s2io_set_link(struct work_struct
*work
)
6768 struct s2io_nic
*nic
= container_of(work
, struct s2io_nic
, set_link_task
);
6769 struct net_device
*dev
= nic
->dev
;
6770 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
6776 if (!netif_running(dev
))
6779 if (test_and_set_bit(__S2IO_STATE_LINK_TASK
, &(nic
->state
))) {
6780 /* The card is being reset, no point doing anything */
6784 subid
= nic
->pdev
->subsystem_device
;
6785 if (s2io_link_fault_indication(nic
) == MAC_RMAC_ERR_TIMER
) {
6787 * Allow a small delay for the NICs self initiated
6788 * cleanup to complete.
6793 val64
= readq(&bar0
->adapter_status
);
6794 if (LINK_IS_UP(val64
)) {
6795 if (!(readq(&bar0
->adapter_control
) & ADAPTER_CNTL_EN
)) {
6796 if (verify_xena_quiescence(nic
)) {
6797 val64
= readq(&bar0
->adapter_control
);
6798 val64
|= ADAPTER_CNTL_EN
;
6799 writeq(val64
, &bar0
->adapter_control
);
6800 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6801 nic
->device_type
, subid
)) {
6802 val64
= readq(&bar0
->gpio_control
);
6803 val64
|= GPIO_CTRL_GPIO_0
;
6804 writeq(val64
, &bar0
->gpio_control
);
6805 val64
= readq(&bar0
->gpio_control
);
6807 val64
|= ADAPTER_LED_ON
;
6808 writeq(val64
, &bar0
->adapter_control
);
6810 nic
->device_enabled_once
= TRUE
;
6812 DBG_PRINT(ERR_DBG
, "%s: Error: ", dev
->name
);
6813 DBG_PRINT(ERR_DBG
, "device is not Quiescent\n");
6814 s2io_stop_all_tx_queue(nic
);
6817 val64
= readq(&bar0
->adapter_control
);
6818 val64
|= ADAPTER_LED_ON
;
6819 writeq(val64
, &bar0
->adapter_control
);
6820 s2io_link(nic
, LINK_UP
);
6822 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic
->device_type
,
6824 val64
= readq(&bar0
->gpio_control
);
6825 val64
&= ~GPIO_CTRL_GPIO_0
;
6826 writeq(val64
, &bar0
->gpio_control
);
6827 val64
= readq(&bar0
->gpio_control
);
6830 val64
= readq(&bar0
->adapter_control
);
6831 val64
= val64
&(~ADAPTER_LED_ON
);
6832 writeq(val64
, &bar0
->adapter_control
);
6833 s2io_link(nic
, LINK_DOWN
);
6835 clear_bit(__S2IO_STATE_LINK_TASK
, &(nic
->state
));
6841 static int set_rxd_buffer_pointer(struct s2io_nic
*sp
, struct RxD_t
*rxdp
,
6843 struct sk_buff
**skb
, u64
*temp0
, u64
*temp1
,
6844 u64
*temp2
, int size
)
6846 struct net_device
*dev
= sp
->dev
;
6847 struct swStat
*stats
= &sp
->mac_control
.stats_info
->sw_stat
;
6849 if ((sp
->rxd_mode
== RXD_MODE_1
) && (rxdp
->Host_Control
== 0)) {
6850 struct RxD1
*rxdp1
= (struct RxD1
*)rxdp
;
6853 DBG_PRINT(INFO_DBG
, "SKB is not NULL\n");
6855 * As Rx frame are not going to be processed,
6856 * using same mapped address for the Rxd
6859 rxdp1
->Buffer0_ptr
= *temp0
;
6861 *skb
= dev_alloc_skb(size
);
6863 DBG_PRINT(INFO_DBG
, "%s: Out of ", dev
->name
);
6864 DBG_PRINT(INFO_DBG
, "memory to allocate ");
6865 DBG_PRINT(INFO_DBG
, "1 buf mode SKBs\n");
6866 sp
->mac_control
.stats_info
->sw_stat
. \
6867 mem_alloc_fail_cnt
++;
6870 sp
->mac_control
.stats_info
->sw_stat
.mem_allocated
6871 += (*skb
)->truesize
;
6872 /* storing the mapped addr in a temp variable
6873 * such it will be used for next rxd whose
6874 * Host Control is NULL
6876 rxdp1
->Buffer0_ptr
= *temp0
=
6877 pci_map_single( sp
->pdev
, (*skb
)->data
,
6878 size
- NET_IP_ALIGN
,
6879 PCI_DMA_FROMDEVICE
);
6880 if (pci_dma_mapping_error(sp
->pdev
, rxdp1
->Buffer0_ptr
))
6881 goto memalloc_failed
;
6882 rxdp
->Host_Control
= (unsigned long) (*skb
);
6884 } else if ((sp
->rxd_mode
== RXD_MODE_3B
) && (rxdp
->Host_Control
== 0)) {
6885 struct RxD3
*rxdp3
= (struct RxD3
*)rxdp
;
6886 /* Two buffer Mode */
6888 rxdp3
->Buffer2_ptr
= *temp2
;
6889 rxdp3
->Buffer0_ptr
= *temp0
;
6890 rxdp3
->Buffer1_ptr
= *temp1
;
6892 *skb
= dev_alloc_skb(size
);
6894 DBG_PRINT(INFO_DBG
, "%s: Out of ", dev
->name
);
6895 DBG_PRINT(INFO_DBG
, "memory to allocate ");
6896 DBG_PRINT(INFO_DBG
, "2 buf mode SKBs\n");
6897 sp
->mac_control
.stats_info
->sw_stat
. \
6898 mem_alloc_fail_cnt
++;
6901 sp
->mac_control
.stats_info
->sw_stat
.mem_allocated
6902 += (*skb
)->truesize
;
6903 rxdp3
->Buffer2_ptr
= *temp2
=
6904 pci_map_single(sp
->pdev
, (*skb
)->data
,
6906 PCI_DMA_FROMDEVICE
);
6907 if (pci_dma_mapping_error(sp
->pdev
, rxdp3
->Buffer2_ptr
))
6908 goto memalloc_failed
;
6909 rxdp3
->Buffer0_ptr
= *temp0
=
6910 pci_map_single( sp
->pdev
, ba
->ba_0
, BUF0_LEN
,
6911 PCI_DMA_FROMDEVICE
);
6912 if (pci_dma_mapping_error(sp
->pdev
,
6913 rxdp3
->Buffer0_ptr
)) {
6914 pci_unmap_single (sp
->pdev
,
6915 (dma_addr_t
)rxdp3
->Buffer2_ptr
,
6916 dev
->mtu
+ 4, PCI_DMA_FROMDEVICE
);
6917 goto memalloc_failed
;
6919 rxdp
->Host_Control
= (unsigned long) (*skb
);
6921 /* Buffer-1 will be dummy buffer not used */
6922 rxdp3
->Buffer1_ptr
= *temp1
=
6923 pci_map_single(sp
->pdev
, ba
->ba_1
, BUF1_LEN
,
6924 PCI_DMA_FROMDEVICE
);
6925 if (pci_dma_mapping_error(sp
->pdev
,
6926 rxdp3
->Buffer1_ptr
)) {
6927 pci_unmap_single (sp
->pdev
,
6928 (dma_addr_t
)rxdp3
->Buffer0_ptr
,
6929 BUF0_LEN
, PCI_DMA_FROMDEVICE
);
6930 pci_unmap_single (sp
->pdev
,
6931 (dma_addr_t
)rxdp3
->Buffer2_ptr
,
6932 dev
->mtu
+ 4, PCI_DMA_FROMDEVICE
);
6933 goto memalloc_failed
;
6939 stats
->pci_map_fail_cnt
++;
6940 stats
->mem_freed
+= (*skb
)->truesize
;
6941 dev_kfree_skb(*skb
);
6945 static void set_rxd_buffer_size(struct s2io_nic
*sp
, struct RxD_t
*rxdp
,
6948 struct net_device
*dev
= sp
->dev
;
6949 if (sp
->rxd_mode
== RXD_MODE_1
) {
6950 rxdp
->Control_2
= SET_BUFFER0_SIZE_1( size
- NET_IP_ALIGN
);
6951 } else if (sp
->rxd_mode
== RXD_MODE_3B
) {
6952 rxdp
->Control_2
= SET_BUFFER0_SIZE_3(BUF0_LEN
);
6953 rxdp
->Control_2
|= SET_BUFFER1_SIZE_3(1);
6954 rxdp
->Control_2
|= SET_BUFFER2_SIZE_3( dev
->mtu
+ 4);
6958 static int rxd_owner_bit_reset(struct s2io_nic
*sp
)
6960 int i
, j
, k
, blk_cnt
= 0, size
;
6961 struct mac_info
* mac_control
= &sp
->mac_control
;
6962 struct config_param
*config
= &sp
->config
;
6963 struct net_device
*dev
= sp
->dev
;
6964 struct RxD_t
*rxdp
= NULL
;
6965 struct sk_buff
*skb
= NULL
;
6966 struct buffAdd
*ba
= NULL
;
6967 u64 temp0_64
= 0, temp1_64
= 0, temp2_64
= 0;
6969 /* Calculate the size based on ring mode */
6970 size
= dev
->mtu
+ HEADER_ETHERNET_II_802_3_SIZE
+
6971 HEADER_802_2_SIZE
+ HEADER_SNAP_SIZE
;
6972 if (sp
->rxd_mode
== RXD_MODE_1
)
6973 size
+= NET_IP_ALIGN
;
6974 else if (sp
->rxd_mode
== RXD_MODE_3B
)
6975 size
= dev
->mtu
+ ALIGN_SIZE
+ BUF0_LEN
+ 4;
6977 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
6978 blk_cnt
= config
->rx_cfg
[i
].num_rxd
/
6979 (rxd_count
[sp
->rxd_mode
] +1);
6981 for (j
= 0; j
< blk_cnt
; j
++) {
6982 for (k
= 0; k
< rxd_count
[sp
->rxd_mode
]; k
++) {
6983 rxdp
= mac_control
->rings
[i
].
6984 rx_blocks
[j
].rxds
[k
].virt_addr
;
6985 if(sp
->rxd_mode
== RXD_MODE_3B
)
6986 ba
= &mac_control
->rings
[i
].ba
[j
][k
];
6987 if (set_rxd_buffer_pointer(sp
, rxdp
, ba
,
6988 &skb
,(u64
*)&temp0_64
,
6995 set_rxd_buffer_size(sp
, rxdp
, size
);
6997 /* flip the Ownership bit to Hardware */
6998 rxdp
->Control_1
|= RXD_OWN_XENA
;
7006 static int s2io_add_isr(struct s2io_nic
* sp
)
7009 struct net_device
*dev
= sp
->dev
;
7012 if (sp
->config
.intr_type
== MSI_X
)
7013 ret
= s2io_enable_msi_x(sp
);
7015 DBG_PRINT(ERR_DBG
, "%s: Defaulting to INTA\n", dev
->name
);
7016 sp
->config
.intr_type
= INTA
;
7019 /* Store the values of the MSIX table in the struct s2io_nic structure */
7020 store_xmsi_data(sp
);
7022 /* After proper initialization of H/W, register ISR */
7023 if (sp
->config
.intr_type
== MSI_X
) {
7024 int i
, msix_rx_cnt
= 0;
7026 for (i
= 0; i
< sp
->num_entries
; i
++) {
7027 if (sp
->s2io_entries
[i
].in_use
== MSIX_FLG
) {
7028 if (sp
->s2io_entries
[i
].type
==
7030 sprintf(sp
->desc
[i
], "%s:MSI-X-%d-RX",
7032 err
= request_irq(sp
->entries
[i
].vector
,
7033 s2io_msix_ring_handle
, 0,
7035 sp
->s2io_entries
[i
].arg
);
7036 } else if (sp
->s2io_entries
[i
].type
==
7038 sprintf(sp
->desc
[i
], "%s:MSI-X-%d-TX",
7040 err
= request_irq(sp
->entries
[i
].vector
,
7041 s2io_msix_fifo_handle
, 0,
7043 sp
->s2io_entries
[i
].arg
);
7046 /* if either data or addr is zero print it. */
7047 if (!(sp
->msix_info
[i
].addr
&&
7048 sp
->msix_info
[i
].data
)) {
7050 "%s @Addr:0x%llx Data:0x%llx\n",
7052 (unsigned long long)
7053 sp
->msix_info
[i
].addr
,
7054 (unsigned long long)
7055 ntohl(sp
->msix_info
[i
].data
));
7059 remove_msix_isr(sp
);
7062 "%s:MSI-X-%d registration "
7063 "failed\n", dev
->name
, i
);
7066 "%s: Defaulting to INTA\n",
7068 sp
->config
.intr_type
= INTA
;
7071 sp
->s2io_entries
[i
].in_use
=
7072 MSIX_REGISTERED_SUCCESS
;
7076 printk(KERN_INFO
"MSI-X-RX %d entries enabled\n",
7078 DBG_PRINT(INFO_DBG
, "MSI-X-TX entries enabled"
7079 " through alarm vector\n");
7082 if (sp
->config
.intr_type
== INTA
) {
7083 err
= request_irq((int) sp
->pdev
->irq
, s2io_isr
, IRQF_SHARED
,
7086 DBG_PRINT(ERR_DBG
, "%s: ISR registration failed\n",
7093 static void s2io_rem_isr(struct s2io_nic
* sp
)
7095 if (sp
->config
.intr_type
== MSI_X
)
7096 remove_msix_isr(sp
);
7098 remove_inta_isr(sp
);
7101 static void do_s2io_card_down(struct s2io_nic
* sp
, int do_io
)
7104 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
7105 register u64 val64
= 0;
7106 struct config_param
*config
;
7107 config
= &sp
->config
;
7109 if (!is_s2io_card_up(sp
))
7112 del_timer_sync(&sp
->alarm_timer
);
7113 /* If s2io_set_link task is executing, wait till it completes. */
7114 while (test_and_set_bit(__S2IO_STATE_LINK_TASK
, &(sp
->state
))) {
7117 clear_bit(__S2IO_STATE_CARD_UP
, &sp
->state
);
7120 if (sp
->config
.napi
) {
7122 if (config
->intr_type
== MSI_X
) {
7123 for (; off
< sp
->config
.rx_ring_num
; off
++)
7124 napi_disable(&sp
->mac_control
.rings
[off
].napi
);
7127 napi_disable(&sp
->napi
);
7130 /* disable Tx and Rx traffic on the NIC */
7136 /* stop the tx queue, indicate link down */
7137 s2io_link(sp
, LINK_DOWN
);
7139 /* Check if the device is Quiescent and then Reset the NIC */
7141 /* As per the HW requirement we need to replenish the
7142 * receive buffer to avoid the ring bump. Since there is
7143 * no intention of processing the Rx frame at this pointwe are
7144 * just settting the ownership bit of rxd in Each Rx
7145 * ring to HW and set the appropriate buffer size
7146 * based on the ring mode
7148 rxd_owner_bit_reset(sp
);
7150 val64
= readq(&bar0
->adapter_status
);
7151 if (verify_xena_quiescence(sp
)) {
7152 if(verify_pcc_quiescent(sp
, sp
->device_enabled_once
))
7160 "s2io_close:Device not Quiescent ");
7161 DBG_PRINT(ERR_DBG
, "adaper status reads 0x%llx\n",
7162 (unsigned long long) val64
);
7169 /* Free all Tx buffers */
7170 free_tx_buffers(sp
);
7172 /* Free all Rx buffers */
7173 free_rx_buffers(sp
);
7175 clear_bit(__S2IO_STATE_LINK_TASK
, &(sp
->state
));
7178 static void s2io_card_down(struct s2io_nic
* sp
)
7180 do_s2io_card_down(sp
, 1);
7183 static int s2io_card_up(struct s2io_nic
* sp
)
7186 struct mac_info
*mac_control
;
7187 struct config_param
*config
;
7188 struct net_device
*dev
= (struct net_device
*) sp
->dev
;
7191 /* Initialize the H/W I/O registers */
7194 DBG_PRINT(ERR_DBG
, "%s: H/W initialization failed\n",
7202 * Initializing the Rx buffers. For now we are considering only 1
7203 * Rx ring and initializing buffers into 30 Rx blocks
7205 mac_control
= &sp
->mac_control
;
7206 config
= &sp
->config
;
7208 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
7209 mac_control
->rings
[i
].mtu
= dev
->mtu
;
7210 ret
= fill_rx_buffers(sp
, &mac_control
->rings
[i
], 1);
7212 DBG_PRINT(ERR_DBG
, "%s: Out of memory in Open\n",
7215 free_rx_buffers(sp
);
7218 DBG_PRINT(INFO_DBG
, "Buf in ring:%d is %d:\n", i
,
7219 mac_control
->rings
[i
].rx_bufs_left
);
7222 /* Initialise napi */
7224 if (config
->intr_type
== MSI_X
) {
7225 for (i
= 0; i
< sp
->config
.rx_ring_num
; i
++)
7226 napi_enable(&sp
->mac_control
.rings
[i
].napi
);
7228 napi_enable(&sp
->napi
);
7232 /* Maintain the state prior to the open */
7233 if (sp
->promisc_flg
)
7234 sp
->promisc_flg
= 0;
7235 if (sp
->m_cast_flg
) {
7237 sp
->all_multi_pos
= 0;
7240 /* Setting its receive mode */
7241 s2io_set_multicast(dev
);
7244 /* Initialize max aggregatable pkts per session based on MTU */
7245 sp
->lro_max_aggr_per_sess
= ((1<<16) - 1) / dev
->mtu
;
7246 /* Check if we can use(if specified) user provided value */
7247 if (lro_max_pkts
< sp
->lro_max_aggr_per_sess
)
7248 sp
->lro_max_aggr_per_sess
= lro_max_pkts
;
7251 /* Enable Rx Traffic and interrupts on the NIC */
7252 if (start_nic(sp
)) {
7253 DBG_PRINT(ERR_DBG
, "%s: Starting NIC failed\n", dev
->name
);
7255 free_rx_buffers(sp
);
7259 /* Add interrupt service routine */
7260 if (s2io_add_isr(sp
) != 0) {
7261 if (sp
->config
.intr_type
== MSI_X
)
7264 free_rx_buffers(sp
);
7268 S2IO_TIMER_CONF(sp
->alarm_timer
, s2io_alarm_handle
, sp
, (HZ
/2));
7270 set_bit(__S2IO_STATE_CARD_UP
, &sp
->state
);
7272 /* Enable select interrupts */
7273 en_dis_err_alarms(sp
, ENA_ALL_INTRS
, ENABLE_INTRS
);
7274 if (sp
->config
.intr_type
!= INTA
) {
7275 interruptible
= TX_TRAFFIC_INTR
| TX_PIC_INTR
;
7276 en_dis_able_nic_intrs(sp
, interruptible
, ENABLE_INTRS
);
7278 interruptible
= TX_TRAFFIC_INTR
| RX_TRAFFIC_INTR
;
7279 interruptible
|= TX_PIC_INTR
;
7280 en_dis_able_nic_intrs(sp
, interruptible
, ENABLE_INTRS
);
7287 * s2io_restart_nic - Resets the NIC.
7288 * @data : long pointer to the device private structure
7290 * This function is scheduled to be run by the s2io_tx_watchdog
7291 * function after 0.5 secs to reset the NIC. The idea is to reduce
7292 * the run time of the watch dog routine which is run holding a
7296 static void s2io_restart_nic(struct work_struct
*work
)
7298 struct s2io_nic
*sp
= container_of(work
, struct s2io_nic
, rst_timer_task
);
7299 struct net_device
*dev
= sp
->dev
;
7303 if (!netif_running(dev
))
7307 if (s2io_card_up(sp
)) {
7308 DBG_PRINT(ERR_DBG
, "%s: Device bring up failed\n",
7311 s2io_wake_all_tx_queue(sp
);
7312 DBG_PRINT(ERR_DBG
, "%s: was reset by Tx watchdog timer\n",
7319 * s2io_tx_watchdog - Watchdog for transmit side.
7320 * @dev : Pointer to net device structure
7322 * This function is triggered if the Tx Queue is stopped
7323 * for a pre-defined amount of time when the Interface is still up.
7324 * If the Interface is jammed in such a situation, the hardware is
7325 * reset (by s2io_close) and restarted again (by s2io_open) to
7326 * overcome any problem that might have been caused in the hardware.
7331 static void s2io_tx_watchdog(struct net_device
*dev
)
7333 struct s2io_nic
*sp
= netdev_priv(dev
);
7335 if (netif_carrier_ok(dev
)) {
7336 sp
->mac_control
.stats_info
->sw_stat
.watchdog_timer_cnt
++;
7337 schedule_work(&sp
->rst_timer_task
);
7338 sp
->mac_control
.stats_info
->sw_stat
.soft_reset_cnt
++;
7343 * rx_osm_handler - To perform some OS related operations on SKB.
7344 * @sp: private member of the device structure,pointer to s2io_nic structure.
7345 * @skb : the socket buffer pointer.
7346 * @len : length of the packet
7347 * @cksum : FCS checksum of the frame.
7348 * @ring_no : the ring from which this RxD was extracted.
7350 * This function is called by the Rx interrupt serivce routine to perform
7351 * some OS related operations on the SKB before passing it to the upper
7352 * layers. It mainly checks if the checksum is OK, if so adds it to the
7353 * SKBs cksum variable, increments the Rx packet count and passes the SKB
7354 * to the upper layer. If the checksum is wrong, it increments the Rx
7355 * packet error count, frees the SKB and returns error.
7357 * SUCCESS on success and -1 on failure.
7359 static int rx_osm_handler(struct ring_info
*ring_data
, struct RxD_t
* rxdp
)
7361 struct s2io_nic
*sp
= ring_data
->nic
;
7362 struct net_device
*dev
= (struct net_device
*) ring_data
->dev
;
7363 struct sk_buff
*skb
= (struct sk_buff
*)
7364 ((unsigned long) rxdp
->Host_Control
);
7365 int ring_no
= ring_data
->ring_no
;
7366 u16 l3_csum
, l4_csum
;
7367 unsigned long long err
= rxdp
->Control_1
& RXD_T_CODE
;
7368 struct lro
*uninitialized_var(lro
);
7374 /* Check for parity error */
7376 sp
->mac_control
.stats_info
->sw_stat
.parity_err_cnt
++;
7378 err_mask
= err
>> 48;
7381 sp
->mac_control
.stats_info
->sw_stat
.
7382 rx_parity_err_cnt
++;
7386 sp
->mac_control
.stats_info
->sw_stat
.
7391 sp
->mac_control
.stats_info
->sw_stat
.
7392 rx_parity_abort_cnt
++;
7396 sp
->mac_control
.stats_info
->sw_stat
.
7401 sp
->mac_control
.stats_info
->sw_stat
.
7406 sp
->mac_control
.stats_info
->sw_stat
.
7411 sp
->mac_control
.stats_info
->sw_stat
.
7412 rx_buf_size_err_cnt
++;
7416 sp
->mac_control
.stats_info
->sw_stat
.
7417 rx_rxd_corrupt_cnt
++;
7421 sp
->mac_control
.stats_info
->sw_stat
.
7426 * Drop the packet if bad transfer code. Exception being
7427 * 0x5, which could be due to unsupported IPv6 extension header.
7428 * In this case, we let stack handle the packet.
7429 * Note that in this case, since checksum will be incorrect,
7430 * stack will validate the same.
7432 if (err_mask
!= 0x5) {
7433 DBG_PRINT(ERR_DBG
, "%s: Rx error Value: 0x%x\n",
7434 dev
->name
, err_mask
);
7435 dev
->stats
.rx_crc_errors
++;
7436 sp
->mac_control
.stats_info
->sw_stat
.mem_freed
7439 ring_data
->rx_bufs_left
-= 1;
7440 rxdp
->Host_Control
= 0;
7445 /* Updating statistics */
7446 ring_data
->rx_packets
++;
7447 rxdp
->Host_Control
= 0;
7448 if (sp
->rxd_mode
== RXD_MODE_1
) {
7449 int len
= RXD_GET_BUFFER0_SIZE_1(rxdp
->Control_2
);
7451 ring_data
->rx_bytes
+= len
;
7454 } else if (sp
->rxd_mode
== RXD_MODE_3B
) {
7455 int get_block
= ring_data
->rx_curr_get_info
.block_index
;
7456 int get_off
= ring_data
->rx_curr_get_info
.offset
;
7457 int buf0_len
= RXD_GET_BUFFER0_SIZE_3(rxdp
->Control_2
);
7458 int buf2_len
= RXD_GET_BUFFER2_SIZE_3(rxdp
->Control_2
);
7459 unsigned char *buff
= skb_push(skb
, buf0_len
);
7461 struct buffAdd
*ba
= &ring_data
->ba
[get_block
][get_off
];
7462 ring_data
->rx_bytes
+= buf0_len
+ buf2_len
;
7463 memcpy(buff
, ba
->ba_0
, buf0_len
);
7464 skb_put(skb
, buf2_len
);
7467 if ((rxdp
->Control_1
& TCP_OR_UDP_FRAME
) && ((!ring_data
->lro
) ||
7468 (ring_data
->lro
&& (!(rxdp
->Control_1
& RXD_FRAME_IP_FRAG
)))) &&
7470 l3_csum
= RXD_GET_L3_CKSUM(rxdp
->Control_1
);
7471 l4_csum
= RXD_GET_L4_CKSUM(rxdp
->Control_1
);
7472 if ((l3_csum
== L3_CKSUM_OK
) && (l4_csum
== L4_CKSUM_OK
)) {
7474 * NIC verifies if the Checksum of the received
7475 * frame is Ok or not and accordingly returns
7476 * a flag in the RxD.
7478 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
7479 if (ring_data
->lro
) {
7484 ret
= s2io_club_tcp_session(ring_data
,
7485 skb
->data
, &tcp
, &tcp_len
, &lro
,
7488 case 3: /* Begin anew */
7491 case 1: /* Aggregate */
7493 lro_append_pkt(sp
, lro
,
7497 case 4: /* Flush session */
7499 lro_append_pkt(sp
, lro
,
7501 queue_rx_frame(lro
->parent
,
7503 clear_lro_session(lro
);
7504 sp
->mac_control
.stats_info
->
7505 sw_stat
.flush_max_pkts
++;
7508 case 2: /* Flush both */
7509 lro
->parent
->data_len
=
7511 sp
->mac_control
.stats_info
->
7512 sw_stat
.sending_both
++;
7513 queue_rx_frame(lro
->parent
,
7515 clear_lro_session(lro
);
7517 case 0: /* sessions exceeded */
7518 case -1: /* non-TCP or not
7522 * First pkt in session not
7523 * L3/L4 aggregatable
7528 "%s: Samadhana!!\n",
7535 * Packet with erroneous checksum, let the
7536 * upper layers deal with it.
7538 skb
->ip_summed
= CHECKSUM_NONE
;
7541 skb
->ip_summed
= CHECKSUM_NONE
;
7543 sp
->mac_control
.stats_info
->sw_stat
.mem_freed
+= skb
->truesize
;
7545 skb_record_rx_queue(skb
, ring_no
);
7546 queue_rx_frame(skb
, RXD_GET_VLAN_TAG(rxdp
->Control_2
));
7548 sp
->mac_control
.rings
[ring_no
].rx_bufs_left
-= 1;
7553 * s2io_link - stops/starts the Tx queue.
7554 * @sp : private member of the device structure, which is a pointer to the
7555 * s2io_nic structure.
7556 * @link : inidicates whether link is UP/DOWN.
7558 * This function stops/starts the Tx queue depending on whether the link
7559 * status of the NIC is is down or up. This is called by the Alarm
7560 * interrupt handler whenever a link change interrupt comes up.
7565 static void s2io_link(struct s2io_nic
* sp
, int link
)
7567 struct net_device
*dev
= (struct net_device
*) sp
->dev
;
7569 if (link
!= sp
->last_link_state
) {
7571 if (link
== LINK_DOWN
) {
7572 DBG_PRINT(ERR_DBG
, "%s: Link down\n", dev
->name
);
7573 s2io_stop_all_tx_queue(sp
);
7574 netif_carrier_off(dev
);
7575 if(sp
->mac_control
.stats_info
->sw_stat
.link_up_cnt
)
7576 sp
->mac_control
.stats_info
->sw_stat
.link_up_time
=
7577 jiffies
- sp
->start_time
;
7578 sp
->mac_control
.stats_info
->sw_stat
.link_down_cnt
++;
7580 DBG_PRINT(ERR_DBG
, "%s: Link Up\n", dev
->name
);
7581 if (sp
->mac_control
.stats_info
->sw_stat
.link_down_cnt
)
7582 sp
->mac_control
.stats_info
->sw_stat
.link_down_time
=
7583 jiffies
- sp
->start_time
;
7584 sp
->mac_control
.stats_info
->sw_stat
.link_up_cnt
++;
7585 netif_carrier_on(dev
);
7586 s2io_wake_all_tx_queue(sp
);
7589 sp
->last_link_state
= link
;
7590 sp
->start_time
= jiffies
;
7594 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7595 * @sp : private member of the device structure, which is a pointer to the
7596 * s2io_nic structure.
7598 * This function initializes a few of the PCI and PCI-X configuration registers
7599 * with recommended values.
7604 static void s2io_init_pci(struct s2io_nic
* sp
)
7606 u16 pci_cmd
= 0, pcix_cmd
= 0;
7608 /* Enable Data Parity Error Recovery in PCI-X command register. */
7609 pci_read_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
,
7611 pci_write_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
,
7613 pci_read_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
,
7616 /* Set the PErr Response bit in PCI command register. */
7617 pci_read_config_word(sp
->pdev
, PCI_COMMAND
, &pci_cmd
);
7618 pci_write_config_word(sp
->pdev
, PCI_COMMAND
,
7619 (pci_cmd
| PCI_COMMAND_PARITY
));
7620 pci_read_config_word(sp
->pdev
, PCI_COMMAND
, &pci_cmd
);
7623 static int s2io_verify_parm(struct pci_dev
*pdev
, u8
*dev_intr_type
,
7626 if ((tx_fifo_num
> MAX_TX_FIFOS
) ||
7627 (tx_fifo_num
< 1)) {
7628 DBG_PRINT(ERR_DBG
, "s2io: Requested number of tx fifos "
7629 "(%d) not supported\n", tx_fifo_num
);
7631 if (tx_fifo_num
< 1)
7634 tx_fifo_num
= MAX_TX_FIFOS
;
7636 DBG_PRINT(ERR_DBG
, "s2io: Default to %d ", tx_fifo_num
);
7637 DBG_PRINT(ERR_DBG
, "tx fifos\n");
7641 *dev_multiq
= multiq
;
7643 if (tx_steering_type
&& (1 == tx_fifo_num
)) {
7644 if (tx_steering_type
!= TX_DEFAULT_STEERING
)
7646 "s2io: Tx steering is not supported with "
7647 "one fifo. Disabling Tx steering.\n");
7648 tx_steering_type
= NO_STEERING
;
7651 if ((tx_steering_type
< NO_STEERING
) ||
7652 (tx_steering_type
> TX_DEFAULT_STEERING
)) {
7653 DBG_PRINT(ERR_DBG
, "s2io: Requested transmit steering not "
7655 DBG_PRINT(ERR_DBG
, "s2io: Disabling transmit steering\n");
7656 tx_steering_type
= NO_STEERING
;
7659 if (rx_ring_num
> MAX_RX_RINGS
) {
7660 DBG_PRINT(ERR_DBG
, "s2io: Requested number of rx rings not "
7662 DBG_PRINT(ERR_DBG
, "s2io: Default to %d rx rings\n",
7664 rx_ring_num
= MAX_RX_RINGS
;
7667 if ((*dev_intr_type
!= INTA
) && (*dev_intr_type
!= MSI_X
)) {
7668 DBG_PRINT(ERR_DBG
, "s2io: Wrong intr_type requested. "
7669 "Defaulting to INTA\n");
7670 *dev_intr_type
= INTA
;
7673 if ((*dev_intr_type
== MSI_X
) &&
7674 ((pdev
->device
!= PCI_DEVICE_ID_HERC_WIN
) &&
7675 (pdev
->device
!= PCI_DEVICE_ID_HERC_UNI
))) {
7676 DBG_PRINT(ERR_DBG
, "s2io: Xframe I does not support MSI_X. "
7677 "Defaulting to INTA\n");
7678 *dev_intr_type
= INTA
;
7681 if ((rx_ring_mode
!= 1) && (rx_ring_mode
!= 2)) {
7682 DBG_PRINT(ERR_DBG
, "s2io: Requested ring mode not supported\n");
7683 DBG_PRINT(ERR_DBG
, "s2io: Defaulting to 1-buffer mode\n");
7690 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7691 * or Traffic class respectively.
7692 * @nic: device private variable
7693 * Description: The function configures the receive steering to
7694 * desired receive ring.
7695 * Return Value: SUCCESS on success and
7696 * '-1' on failure (endian settings incorrect).
7698 static int rts_ds_steer(struct s2io_nic
*nic
, u8 ds_codepoint
, u8 ring
)
7700 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
7701 register u64 val64
= 0;
7703 if (ds_codepoint
> 63)
7706 val64
= RTS_DS_MEM_DATA(ring
);
7707 writeq(val64
, &bar0
->rts_ds_mem_data
);
7709 val64
= RTS_DS_MEM_CTRL_WE
|
7710 RTS_DS_MEM_CTRL_STROBE_NEW_CMD
|
7711 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint
);
7713 writeq(val64
, &bar0
->rts_ds_mem_ctrl
);
7715 return wait_for_cmd_complete(&bar0
->rts_ds_mem_ctrl
,
7716 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED
,
7720 static const struct net_device_ops s2io_netdev_ops
= {
7721 .ndo_open
= s2io_open
,
7722 .ndo_stop
= s2io_close
,
7723 .ndo_get_stats
= s2io_get_stats
,
7724 .ndo_start_xmit
= s2io_xmit
,
7725 .ndo_validate_addr
= eth_validate_addr
,
7726 .ndo_set_multicast_list
= s2io_set_multicast
,
7727 .ndo_do_ioctl
= s2io_ioctl
,
7728 .ndo_set_mac_address
= s2io_set_mac_addr
,
7729 .ndo_change_mtu
= s2io_change_mtu
,
7730 .ndo_vlan_rx_register
= s2io_vlan_rx_register
,
7731 .ndo_vlan_rx_kill_vid
= s2io_vlan_rx_kill_vid
,
7732 .ndo_tx_timeout
= s2io_tx_watchdog
,
7733 #ifdef CONFIG_NET_POLL_CONTROLLER
7734 .ndo_poll_controller
= s2io_netpoll
,
7739 * s2io_init_nic - Initialization of the adapter .
7740 * @pdev : structure containing the PCI related information of the device.
7741 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7743 * The function initializes an adapter identified by the pci_dec structure.
7744 * All OS related initialization including memory and device structure and
7745 * initlaization of the device private variable is done. Also the swapper
7746 * control register is initialized to enable read and write into the I/O
7747 * registers of the device.
7749 * returns 0 on success and negative on failure.
7752 static int __devinit
7753 s2io_init_nic(struct pci_dev
*pdev
, const struct pci_device_id
*pre
)
7755 struct s2io_nic
*sp
;
7756 struct net_device
*dev
;
7758 int dma_flag
= FALSE
;
7759 u32 mac_up
, mac_down
;
7760 u64 val64
= 0, tmp64
= 0;
7761 struct XENA_dev_config __iomem
*bar0
= NULL
;
7763 struct mac_info
*mac_control
;
7764 struct config_param
*config
;
7766 u8 dev_intr_type
= intr_type
;
7769 ret
= s2io_verify_parm(pdev
, &dev_intr_type
, &dev_multiq
);
7773 if ((ret
= pci_enable_device(pdev
))) {
7775 "s2io_init_nic: pci_enable_device failed\n");
7779 if (!pci_set_dma_mask(pdev
, DMA_BIT_MASK(64))) {
7780 DBG_PRINT(INIT_DBG
, "s2io_init_nic: Using 64bit DMA\n");
7782 if (pci_set_consistent_dma_mask
7783 (pdev
, DMA_BIT_MASK(64))) {
7785 "Unable to obtain 64bit DMA for \
7786 consistent allocations\n");
7787 pci_disable_device(pdev
);
7790 } else if (!pci_set_dma_mask(pdev
, DMA_BIT_MASK(32))) {
7791 DBG_PRINT(INIT_DBG
, "s2io_init_nic: Using 32bit DMA\n");
7793 pci_disable_device(pdev
);
7796 if ((ret
= pci_request_regions(pdev
, s2io_driver_name
))) {
7797 DBG_PRINT(ERR_DBG
, "%s: Request Regions failed - %x \n", __func__
, ret
);
7798 pci_disable_device(pdev
);
7802 dev
= alloc_etherdev_mq(sizeof(struct s2io_nic
), tx_fifo_num
);
7804 dev
= alloc_etherdev(sizeof(struct s2io_nic
));
7806 DBG_PRINT(ERR_DBG
, "Device allocation failed\n");
7807 pci_disable_device(pdev
);
7808 pci_release_regions(pdev
);
7812 pci_set_master(pdev
);
7813 pci_set_drvdata(pdev
, dev
);
7814 SET_NETDEV_DEV(dev
, &pdev
->dev
);
7816 /* Private member variable initialized to s2io NIC structure */
7817 sp
= netdev_priv(dev
);
7818 memset(sp
, 0, sizeof(struct s2io_nic
));
7821 sp
->high_dma_flag
= dma_flag
;
7822 sp
->device_enabled_once
= FALSE
;
7823 if (rx_ring_mode
== 1)
7824 sp
->rxd_mode
= RXD_MODE_1
;
7825 if (rx_ring_mode
== 2)
7826 sp
->rxd_mode
= RXD_MODE_3B
;
7828 sp
->config
.intr_type
= dev_intr_type
;
7830 if ((pdev
->device
== PCI_DEVICE_ID_HERC_WIN
) ||
7831 (pdev
->device
== PCI_DEVICE_ID_HERC_UNI
))
7832 sp
->device_type
= XFRAME_II_DEVICE
;
7834 sp
->device_type
= XFRAME_I_DEVICE
;
7836 sp
->lro
= lro_enable
;
7838 /* Initialize some PCI/PCI-X fields of the NIC. */
7842 * Setting the device configuration parameters.
7843 * Most of these parameters can be specified by the user during
7844 * module insertion as they are module loadable parameters. If
7845 * these parameters are not not specified during load time, they
7846 * are initialized with default values.
7848 mac_control
= &sp
->mac_control
;
7849 config
= &sp
->config
;
7851 config
->napi
= napi
;
7852 config
->tx_steering_type
= tx_steering_type
;
7854 /* Tx side parameters. */
7855 if (config
->tx_steering_type
== TX_PRIORITY_STEERING
)
7856 config
->tx_fifo_num
= MAX_TX_FIFOS
;
7858 config
->tx_fifo_num
= tx_fifo_num
;
7860 /* Initialize the fifos used for tx steering */
7861 if (config
->tx_fifo_num
< 5) {
7862 if (config
->tx_fifo_num
== 1)
7863 sp
->total_tcp_fifos
= 1;
7865 sp
->total_tcp_fifos
= config
->tx_fifo_num
- 1;
7866 sp
->udp_fifo_idx
= config
->tx_fifo_num
- 1;
7867 sp
->total_udp_fifos
= 1;
7868 sp
->other_fifo_idx
= sp
->total_tcp_fifos
- 1;
7870 sp
->total_tcp_fifos
= (tx_fifo_num
- FIFO_UDP_MAX_NUM
-
7871 FIFO_OTHER_MAX_NUM
);
7872 sp
->udp_fifo_idx
= sp
->total_tcp_fifos
;
7873 sp
->total_udp_fifos
= FIFO_UDP_MAX_NUM
;
7874 sp
->other_fifo_idx
= sp
->udp_fifo_idx
+ FIFO_UDP_MAX_NUM
;
7877 config
->multiq
= dev_multiq
;
7878 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
7879 config
->tx_cfg
[i
].fifo_len
= tx_fifo_len
[i
];
7880 config
->tx_cfg
[i
].fifo_priority
= i
;
7883 /* mapping the QoS priority to the configured fifos */
7884 for (i
= 0; i
< MAX_TX_FIFOS
; i
++)
7885 config
->fifo_mapping
[i
] = fifo_map
[config
->tx_fifo_num
- 1][i
];
7887 /* map the hashing selector table to the configured fifos */
7888 for (i
= 0; i
< config
->tx_fifo_num
; i
++)
7889 sp
->fifo_selector
[i
] = fifo_selector
[i
];
7892 config
->tx_intr_type
= TXD_INT_TYPE_UTILZ
;
7893 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
7894 config
->tx_cfg
[i
].f_no_snoop
=
7895 (NO_SNOOP_TXD
| NO_SNOOP_TXD_BUFFER
);
7896 if (config
->tx_cfg
[i
].fifo_len
< 65) {
7897 config
->tx_intr_type
= TXD_INT_TYPE_PER_LIST
;
7901 /* + 2 because one Txd for skb->data and one Txd for UFO */
7902 config
->max_txds
= MAX_SKB_FRAGS
+ 2;
7904 /* Rx side parameters. */
7905 config
->rx_ring_num
= rx_ring_num
;
7906 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
7907 config
->rx_cfg
[i
].num_rxd
= rx_ring_sz
[i
] *
7908 (rxd_count
[sp
->rxd_mode
] + 1);
7909 config
->rx_cfg
[i
].ring_priority
= i
;
7910 mac_control
->rings
[i
].rx_bufs_left
= 0;
7911 mac_control
->rings
[i
].rxd_mode
= sp
->rxd_mode
;
7912 mac_control
->rings
[i
].rxd_count
= rxd_count
[sp
->rxd_mode
];
7913 mac_control
->rings
[i
].pdev
= sp
->pdev
;
7914 mac_control
->rings
[i
].dev
= sp
->dev
;
7917 for (i
= 0; i
< rx_ring_num
; i
++) {
7918 config
->rx_cfg
[i
].ring_org
= RING_ORG_BUFF1
;
7919 config
->rx_cfg
[i
].f_no_snoop
=
7920 (NO_SNOOP_RXD
| NO_SNOOP_RXD_BUFFER
);
7923 /* Setting Mac Control parameters */
7924 mac_control
->rmac_pause_time
= rmac_pause_time
;
7925 mac_control
->mc_pause_threshold_q0q3
= mc_pause_threshold_q0q3
;
7926 mac_control
->mc_pause_threshold_q4q7
= mc_pause_threshold_q4q7
;
7929 /* initialize the shared memory used by the NIC and the host */
7930 if (init_shared_mem(sp
)) {
7931 DBG_PRINT(ERR_DBG
, "%s: Memory allocation failed\n",
7934 goto mem_alloc_failed
;
7937 sp
->bar0
= pci_ioremap_bar(pdev
, 0);
7939 DBG_PRINT(ERR_DBG
, "%s: Neterion: cannot remap io mem1\n",
7942 goto bar0_remap_failed
;
7945 sp
->bar1
= pci_ioremap_bar(pdev
, 2);
7947 DBG_PRINT(ERR_DBG
, "%s: Neterion: cannot remap io mem2\n",
7950 goto bar1_remap_failed
;
7953 dev
->irq
= pdev
->irq
;
7954 dev
->base_addr
= (unsigned long) sp
->bar0
;
7956 /* Initializing the BAR1 address as the start of the FIFO pointer. */
7957 for (j
= 0; j
< MAX_TX_FIFOS
; j
++) {
7958 mac_control
->tx_FIFO_start
[j
] = (struct TxFIFO_element __iomem
*)
7959 (sp
->bar1
+ (j
* 0x00020000));
7962 /* Driver entry points */
7963 dev
->netdev_ops
= &s2io_netdev_ops
;
7964 SET_ETHTOOL_OPS(dev
, &netdev_ethtool_ops
);
7965 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
7967 dev
->features
|= NETIF_F_SG
| NETIF_F_IP_CSUM
;
7968 if (sp
->high_dma_flag
== TRUE
)
7969 dev
->features
|= NETIF_F_HIGHDMA
;
7970 dev
->features
|= NETIF_F_TSO
;
7971 dev
->features
|= NETIF_F_TSO6
;
7972 if ((sp
->device_type
& XFRAME_II_DEVICE
) && (ufo
)) {
7973 dev
->features
|= NETIF_F_UFO
;
7974 dev
->features
|= NETIF_F_HW_CSUM
;
7976 dev
->watchdog_timeo
= WATCH_DOG_TIMEOUT
;
7977 INIT_WORK(&sp
->rst_timer_task
, s2io_restart_nic
);
7978 INIT_WORK(&sp
->set_link_task
, s2io_set_link
);
7980 pci_save_state(sp
->pdev
);
7982 /* Setting swapper control on the NIC, for proper reset operation */
7983 if (s2io_set_swapper(sp
)) {
7984 DBG_PRINT(ERR_DBG
, "%s:swapper settings are wrong\n",
7987 goto set_swap_failed
;
7990 /* Verify if the Herc works on the slot its placed into */
7991 if (sp
->device_type
& XFRAME_II_DEVICE
) {
7992 mode
= s2io_verify_pci_mode(sp
);
7994 DBG_PRINT(ERR_DBG
, "%s: ", __func__
);
7995 DBG_PRINT(ERR_DBG
, " Unsupported PCI bus mode\n");
7997 goto set_swap_failed
;
8001 if (sp
->config
.intr_type
== MSI_X
) {
8002 sp
->num_entries
= config
->rx_ring_num
+ 1;
8003 ret
= s2io_enable_msi_x(sp
);
8006 ret
= s2io_test_msi(sp
);
8007 /* rollback MSI-X, will re-enable during add_isr() */
8008 remove_msix_isr(sp
);
8013 "s2io: MSI-X requested but failed to enable\n");
8014 sp
->config
.intr_type
= INTA
;
8018 if (config
->intr_type
== MSI_X
) {
8019 for (i
= 0; i
< config
->rx_ring_num
; i
++)
8020 netif_napi_add(dev
, &mac_control
->rings
[i
].napi
,
8021 s2io_poll_msix
, 64);
8023 netif_napi_add(dev
, &sp
->napi
, s2io_poll_inta
, 64);
8026 /* Not needed for Herc */
8027 if (sp
->device_type
& XFRAME_I_DEVICE
) {
8029 * Fix for all "FFs" MAC address problems observed on
8032 fix_mac_address(sp
);
8037 * MAC address initialization.
8038 * For now only one mac address will be read and used.
8041 val64
= RMAC_ADDR_CMD_MEM_RD
| RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
8042 RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET
);
8043 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
8044 wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
8045 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
, S2IO_BIT_RESET
);
8046 tmp64
= readq(&bar0
->rmac_addr_data0_mem
);
8047 mac_down
= (u32
) tmp64
;
8048 mac_up
= (u32
) (tmp64
>> 32);
8050 sp
->def_mac_addr
[0].mac_addr
[3] = (u8
) (mac_up
);
8051 sp
->def_mac_addr
[0].mac_addr
[2] = (u8
) (mac_up
>> 8);
8052 sp
->def_mac_addr
[0].mac_addr
[1] = (u8
) (mac_up
>> 16);
8053 sp
->def_mac_addr
[0].mac_addr
[0] = (u8
) (mac_up
>> 24);
8054 sp
->def_mac_addr
[0].mac_addr
[5] = (u8
) (mac_down
>> 16);
8055 sp
->def_mac_addr
[0].mac_addr
[4] = (u8
) (mac_down
>> 24);
8057 /* Set the factory defined MAC address initially */
8058 dev
->addr_len
= ETH_ALEN
;
8059 memcpy(dev
->dev_addr
, sp
->def_mac_addr
, ETH_ALEN
);
8060 memcpy(dev
->perm_addr
, dev
->dev_addr
, ETH_ALEN
);
8062 /* initialize number of multicast & unicast MAC entries variables */
8063 if (sp
->device_type
== XFRAME_I_DEVICE
) {
8064 config
->max_mc_addr
= S2IO_XENA_MAX_MC_ADDRESSES
;
8065 config
->max_mac_addr
= S2IO_XENA_MAX_MAC_ADDRESSES
;
8066 config
->mc_start_offset
= S2IO_XENA_MC_ADDR_START_OFFSET
;
8067 } else if (sp
->device_type
== XFRAME_II_DEVICE
) {
8068 config
->max_mc_addr
= S2IO_HERC_MAX_MC_ADDRESSES
;
8069 config
->max_mac_addr
= S2IO_HERC_MAX_MAC_ADDRESSES
;
8070 config
->mc_start_offset
= S2IO_HERC_MC_ADDR_START_OFFSET
;
8073 /* store mac addresses from CAM to s2io_nic structure */
8074 do_s2io_store_unicast_mc(sp
);
8076 /* Configure MSIX vector for number of rings configured plus one */
8077 if ((sp
->device_type
== XFRAME_II_DEVICE
) &&
8078 (config
->intr_type
== MSI_X
))
8079 sp
->num_entries
= config
->rx_ring_num
+ 1;
8081 /* Store the values of the MSIX table in the s2io_nic structure */
8082 store_xmsi_data(sp
);
8083 /* reset Nic and bring it to known state */
8087 * Initialize link state flags
8088 * and the card state parameter
8092 /* Initialize spinlocks */
8093 for (i
= 0; i
< sp
->config
.tx_fifo_num
; i
++)
8094 spin_lock_init(&mac_control
->fifos
[i
].tx_lock
);
8097 * SXE-002: Configure link and activity LED to init state
8100 subid
= sp
->pdev
->subsystem_device
;
8101 if ((subid
& 0xFF) >= 0x07) {
8102 val64
= readq(&bar0
->gpio_control
);
8103 val64
|= 0x0000800000000000ULL
;
8104 writeq(val64
, &bar0
->gpio_control
);
8105 val64
= 0x0411040400000000ULL
;
8106 writeq(val64
, (void __iomem
*) bar0
+ 0x2700);
8107 val64
= readq(&bar0
->gpio_control
);
8110 sp
->rx_csum
= 1; /* Rx chksum verify enabled by default */
8112 if (register_netdev(dev
)) {
8113 DBG_PRINT(ERR_DBG
, "Device registration failed\n");
8115 goto register_failed
;
8118 DBG_PRINT(ERR_DBG
, "Copyright(c) 2002-2007 Neterion Inc.\n");
8119 DBG_PRINT(ERR_DBG
, "%s: Neterion %s (rev %d)\n",dev
->name
,
8120 sp
->product_name
, pdev
->revision
);
8121 DBG_PRINT(ERR_DBG
, "%s: Driver version %s\n", dev
->name
,
8122 s2io_driver_version
);
8123 DBG_PRINT(ERR_DBG
, "%s: MAC ADDR: %pM\n", dev
->name
, dev
->dev_addr
);
8124 DBG_PRINT(ERR_DBG
, "SERIAL NUMBER: %s\n", sp
->serial_num
);
8125 if (sp
->device_type
& XFRAME_II_DEVICE
) {
8126 mode
= s2io_print_pci_mode(sp
);
8128 DBG_PRINT(ERR_DBG
, " Unsupported PCI bus mode\n");
8130 unregister_netdev(dev
);
8131 goto set_swap_failed
;
8134 switch(sp
->rxd_mode
) {
8136 DBG_PRINT(ERR_DBG
, "%s: 1-Buffer receive mode enabled\n",
8140 DBG_PRINT(ERR_DBG
, "%s: 2-Buffer receive mode enabled\n",
8145 switch (sp
->config
.napi
) {
8147 DBG_PRINT(ERR_DBG
, "%s: NAPI disabled\n", dev
->name
);
8150 DBG_PRINT(ERR_DBG
, "%s: NAPI enabled\n", dev
->name
);
8154 DBG_PRINT(ERR_DBG
, "%s: Using %d Tx fifo(s)\n", dev
->name
,
8155 sp
->config
.tx_fifo_num
);
8157 DBG_PRINT(ERR_DBG
, "%s: Using %d Rx ring(s)\n", dev
->name
,
8158 sp
->config
.rx_ring_num
);
8160 switch(sp
->config
.intr_type
) {
8162 DBG_PRINT(ERR_DBG
, "%s: Interrupt type INTA\n", dev
->name
);
8165 DBG_PRINT(ERR_DBG
, "%s: Interrupt type MSI-X\n", dev
->name
);
8168 if (sp
->config
.multiq
) {
8169 for (i
= 0; i
< sp
->config
.tx_fifo_num
; i
++)
8170 mac_control
->fifos
[i
].multiq
= config
->multiq
;
8171 DBG_PRINT(ERR_DBG
, "%s: Multiqueue support enabled\n",
8174 DBG_PRINT(ERR_DBG
, "%s: Multiqueue support disabled\n",
8177 switch (sp
->config
.tx_steering_type
) {
8179 DBG_PRINT(ERR_DBG
, "%s: No steering enabled for"
8180 " transmit\n", dev
->name
);
8182 case TX_PRIORITY_STEERING
:
8183 DBG_PRINT(ERR_DBG
, "%s: Priority steering enabled for"
8184 " transmit\n", dev
->name
);
8186 case TX_DEFAULT_STEERING
:
8187 DBG_PRINT(ERR_DBG
, "%s: Default steering enabled for"
8188 " transmit\n", dev
->name
);
8192 DBG_PRINT(ERR_DBG
, "%s: Large receive offload enabled\n",
8195 DBG_PRINT(ERR_DBG
, "%s: UDP Fragmentation Offload(UFO)"
8196 " enabled\n", dev
->name
);
8197 /* Initialize device name */
8198 sprintf(sp
->name
, "%s Neterion %s", dev
->name
, sp
->product_name
);
8201 sp
->vlan_strip_flag
= 1;
8203 sp
->vlan_strip_flag
= 0;
8206 * Make Link state as off at this point, when the Link change
8207 * interrupt comes the state will be automatically changed to
8210 netif_carrier_off(dev
);
8221 free_shared_mem(sp
);
8222 pci_disable_device(pdev
);
8223 pci_release_regions(pdev
);
8224 pci_set_drvdata(pdev
, NULL
);
8231 * s2io_rem_nic - Free the PCI device
8232 * @pdev: structure containing the PCI related information of the device.
8233 * Description: This function is called by the Pci subsystem to release a
8234 * PCI device and free up all resource held up by the device. This could
8235 * be in response to a Hot plug event or when the driver is to be removed
8239 static void __devexit
s2io_rem_nic(struct pci_dev
*pdev
)
8241 struct net_device
*dev
=
8242 (struct net_device
*) pci_get_drvdata(pdev
);
8243 struct s2io_nic
*sp
;
8246 DBG_PRINT(ERR_DBG
, "Driver Data is NULL!!\n");
8250 flush_scheduled_work();
8252 sp
= netdev_priv(dev
);
8253 unregister_netdev(dev
);
8255 free_shared_mem(sp
);
8258 pci_release_regions(pdev
);
8259 pci_set_drvdata(pdev
, NULL
);
8261 pci_disable_device(pdev
);
8265 * s2io_starter - Entry point for the driver
8266 * Description: This function is the entry point for the driver. It verifies
8267 * the module loadable parameters and initializes PCI configuration space.
8270 static int __init
s2io_starter(void)
8272 return pci_register_driver(&s2io_driver
);
8276 * s2io_closer - Cleanup routine for the driver
8277 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
8280 static __exit
void s2io_closer(void)
8282 pci_unregister_driver(&s2io_driver
);
8283 DBG_PRINT(INIT_DBG
, "cleanup done\n");
8286 module_init(s2io_starter
);
8287 module_exit(s2io_closer
);
8289 static int check_L2_lro_capable(u8
*buffer
, struct iphdr
**ip
,
8290 struct tcphdr
**tcp
, struct RxD_t
*rxdp
,
8291 struct s2io_nic
*sp
)
8294 u8 l2_type
= (u8
)((rxdp
->Control_1
>> 37) & 0x7), ip_len
;
8296 if (!(rxdp
->Control_1
& RXD_FRAME_PROTO_TCP
)) {
8297 DBG_PRINT(INIT_DBG
,"%s: Non-TCP frames not supported for LRO\n",
8302 /* Checking for DIX type or DIX type with VLAN */
8304 || (l2_type
== 4)) {
8305 ip_off
= HEADER_ETHERNET_II_802_3_SIZE
;
8307 * If vlan stripping is disabled and the frame is VLAN tagged,
8308 * shift the offset by the VLAN header size bytes.
8310 if ((!sp
->vlan_strip_flag
) &&
8311 (rxdp
->Control_1
& RXD_FRAME_VLAN_TAG
))
8312 ip_off
+= HEADER_VLAN_SIZE
;
8314 /* LLC, SNAP etc are considered non-mergeable */
8318 *ip
= (struct iphdr
*)((u8
*)buffer
+ ip_off
);
8319 ip_len
= (u8
)((*ip
)->ihl
);
8321 *tcp
= (struct tcphdr
*)((unsigned long)*ip
+ ip_len
);
8326 static int check_for_socket_match(struct lro
*lro
, struct iphdr
*ip
,
8329 DBG_PRINT(INFO_DBG
,"%s: Been here...\n", __func__
);
8330 if ((lro
->iph
->saddr
!= ip
->saddr
) || (lro
->iph
->daddr
!= ip
->daddr
) ||
8331 (lro
->tcph
->source
!= tcp
->source
) || (lro
->tcph
->dest
!= tcp
->dest
))
8336 static inline int get_l4_pyld_length(struct iphdr
*ip
, struct tcphdr
*tcp
)
8338 return(ntohs(ip
->tot_len
) - (ip
->ihl
<< 2) - (tcp
->doff
<< 2));
8341 static void initiate_new_session(struct lro
*lro
, u8
*l2h
,
8342 struct iphdr
*ip
, struct tcphdr
*tcp
, u32 tcp_pyld_len
, u16 vlan_tag
)
8344 DBG_PRINT(INFO_DBG
,"%s: Been here...\n", __func__
);
8348 lro
->tcp_next_seq
= tcp_pyld_len
+ ntohl(tcp
->seq
);
8349 lro
->tcp_ack
= tcp
->ack_seq
;
8351 lro
->total_len
= ntohs(ip
->tot_len
);
8353 lro
->vlan_tag
= vlan_tag
;
8355 * check if we saw TCP timestamp. Other consistency checks have
8356 * already been done.
8358 if (tcp
->doff
== 8) {
8360 ptr
= (__be32
*)(tcp
+1);
8362 lro
->cur_tsval
= ntohl(*(ptr
+1));
8363 lro
->cur_tsecr
= *(ptr
+2);
8368 static void update_L3L4_header(struct s2io_nic
*sp
, struct lro
*lro
)
8370 struct iphdr
*ip
= lro
->iph
;
8371 struct tcphdr
*tcp
= lro
->tcph
;
8373 struct stat_block
*statinfo
= sp
->mac_control
.stats_info
;
8374 DBG_PRINT(INFO_DBG
,"%s: Been here...\n", __func__
);
8376 /* Update L3 header */
8377 ip
->tot_len
= htons(lro
->total_len
);
8379 nchk
= ip_fast_csum((u8
*)lro
->iph
, ip
->ihl
);
8382 /* Update L4 header */
8383 tcp
->ack_seq
= lro
->tcp_ack
;
8384 tcp
->window
= lro
->window
;
8386 /* Update tsecr field if this session has timestamps enabled */
8388 __be32
*ptr
= (__be32
*)(tcp
+ 1);
8389 *(ptr
+2) = lro
->cur_tsecr
;
8392 /* Update counters required for calculation of
8393 * average no. of packets aggregated.
8395 statinfo
->sw_stat
.sum_avg_pkts_aggregated
+= lro
->sg_num
;
8396 statinfo
->sw_stat
.num_aggregations
++;
8399 static void aggregate_new_rx(struct lro
*lro
, struct iphdr
*ip
,
8400 struct tcphdr
*tcp
, u32 l4_pyld
)
8402 DBG_PRINT(INFO_DBG
,"%s: Been here...\n", __func__
);
8403 lro
->total_len
+= l4_pyld
;
8404 lro
->frags_len
+= l4_pyld
;
8405 lro
->tcp_next_seq
+= l4_pyld
;
8408 /* Update ack seq no. and window ad(from this pkt) in LRO object */
8409 lro
->tcp_ack
= tcp
->ack_seq
;
8410 lro
->window
= tcp
->window
;
8414 /* Update tsecr and tsval from this packet */
8415 ptr
= (__be32
*)(tcp
+1);
8416 lro
->cur_tsval
= ntohl(*(ptr
+1));
8417 lro
->cur_tsecr
= *(ptr
+ 2);
8421 static int verify_l3_l4_lro_capable(struct lro
*l_lro
, struct iphdr
*ip
,
8422 struct tcphdr
*tcp
, u32 tcp_pyld_len
)
8426 DBG_PRINT(INFO_DBG
,"%s: Been here...\n", __func__
);
8428 if (!tcp_pyld_len
) {
8429 /* Runt frame or a pure ack */
8433 if (ip
->ihl
!= 5) /* IP has options */
8436 /* If we see CE codepoint in IP header, packet is not mergeable */
8437 if (INET_ECN_is_ce(ipv4_get_dsfield(ip
)))
8440 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
8441 if (tcp
->urg
|| tcp
->psh
|| tcp
->rst
|| tcp
->syn
|| tcp
->fin
||
8442 tcp
->ece
|| tcp
->cwr
|| !tcp
->ack
) {
8444 * Currently recognize only the ack control word and
8445 * any other control field being set would result in
8446 * flushing the LRO session
8452 * Allow only one TCP timestamp option. Don't aggregate if
8453 * any other options are detected.
8455 if (tcp
->doff
!= 5 && tcp
->doff
!= 8)
8458 if (tcp
->doff
== 8) {
8459 ptr
= (u8
*)(tcp
+ 1);
8460 while (*ptr
== TCPOPT_NOP
)
8462 if (*ptr
!= TCPOPT_TIMESTAMP
|| *(ptr
+1) != TCPOLEN_TIMESTAMP
)
8465 /* Ensure timestamp value increases monotonically */
8467 if (l_lro
->cur_tsval
> ntohl(*((__be32
*)(ptr
+2))))
8470 /* timestamp echo reply should be non-zero */
8471 if (*((__be32
*)(ptr
+6)) == 0)
8479 s2io_club_tcp_session(struct ring_info
*ring_data
, u8
*buffer
, u8
**tcp
,
8480 u32
*tcp_len
, struct lro
**lro
, struct RxD_t
*rxdp
,
8481 struct s2io_nic
*sp
)
8484 struct tcphdr
*tcph
;
8488 if (!(ret
= check_L2_lro_capable(buffer
, &ip
, (struct tcphdr
**)tcp
,
8490 DBG_PRINT(INFO_DBG
,"IP Saddr: %x Daddr: %x\n",
8491 ip
->saddr
, ip
->daddr
);
8495 vlan_tag
= RXD_GET_VLAN_TAG(rxdp
->Control_2
);
8496 tcph
= (struct tcphdr
*)*tcp
;
8497 *tcp_len
= get_l4_pyld_length(ip
, tcph
);
8498 for (i
=0; i
<MAX_LRO_SESSIONS
; i
++) {
8499 struct lro
*l_lro
= &ring_data
->lro0_n
[i
];
8500 if (l_lro
->in_use
) {
8501 if (check_for_socket_match(l_lro
, ip
, tcph
))
8503 /* Sock pair matched */
8506 if ((*lro
)->tcp_next_seq
!= ntohl(tcph
->seq
)) {
8507 DBG_PRINT(INFO_DBG
, "%s:Out of order. expected "
8508 "0x%x, actual 0x%x\n", __func__
,
8509 (*lro
)->tcp_next_seq
,
8512 sp
->mac_control
.stats_info
->
8513 sw_stat
.outof_sequence_pkts
++;
8518 if (!verify_l3_l4_lro_capable(l_lro
, ip
, tcph
,*tcp_len
))
8519 ret
= 1; /* Aggregate */
8521 ret
= 2; /* Flush both */
8527 /* Before searching for available LRO objects,
8528 * check if the pkt is L3/L4 aggregatable. If not
8529 * don't create new LRO session. Just send this
8532 if (verify_l3_l4_lro_capable(NULL
, ip
, tcph
, *tcp_len
)) {
8536 for (i
=0; i
<MAX_LRO_SESSIONS
; i
++) {
8537 struct lro
*l_lro
= &ring_data
->lro0_n
[i
];
8538 if (!(l_lro
->in_use
)) {
8540 ret
= 3; /* Begin anew */
8546 if (ret
== 0) { /* sessions exceeded */
8547 DBG_PRINT(INFO_DBG
,"%s:All LRO sessions already in use\n",
8555 initiate_new_session(*lro
, buffer
, ip
, tcph
, *tcp_len
,
8559 update_L3L4_header(sp
, *lro
);
8562 aggregate_new_rx(*lro
, ip
, tcph
, *tcp_len
);
8563 if ((*lro
)->sg_num
== sp
->lro_max_aggr_per_sess
) {
8564 update_L3L4_header(sp
, *lro
);
8565 ret
= 4; /* Flush the LRO */
8569 DBG_PRINT(ERR_DBG
,"%s:Dont know, can't say!!\n",
8577 static void clear_lro_session(struct lro
*lro
)
8579 static u16 lro_struct_size
= sizeof(struct lro
);
8581 memset(lro
, 0, lro_struct_size
);
8584 static void queue_rx_frame(struct sk_buff
*skb
, u16 vlan_tag
)
8586 struct net_device
*dev
= skb
->dev
;
8587 struct s2io_nic
*sp
= netdev_priv(dev
);
8589 skb
->protocol
= eth_type_trans(skb
, dev
);
8590 if (sp
->vlgrp
&& vlan_tag
8591 && (sp
->vlan_strip_flag
)) {
8592 /* Queueing the vlan frame to the upper layer */
8593 if (sp
->config
.napi
)
8594 vlan_hwaccel_receive_skb(skb
, sp
->vlgrp
, vlan_tag
);
8596 vlan_hwaccel_rx(skb
, sp
->vlgrp
, vlan_tag
);
8598 if (sp
->config
.napi
)
8599 netif_receive_skb(skb
);
8605 static void lro_append_pkt(struct s2io_nic
*sp
, struct lro
*lro
,
8606 struct sk_buff
*skb
,
8609 struct sk_buff
*first
= lro
->parent
;
8611 first
->len
+= tcp_len
;
8612 first
->data_len
= lro
->frags_len
;
8613 skb_pull(skb
, (skb
->len
- tcp_len
));
8614 if (skb_shinfo(first
)->frag_list
)
8615 lro
->last_frag
->next
= skb
;
8617 skb_shinfo(first
)->frag_list
= skb
;
8618 first
->truesize
+= skb
->truesize
;
8619 lro
->last_frag
= skb
;
8620 sp
->mac_control
.stats_info
->sw_stat
.clubbed_frms_cnt
++;
8625 * s2io_io_error_detected - called when PCI error is detected
8626 * @pdev: Pointer to PCI device
8627 * @state: The current pci connection state
8629 * This function is called after a PCI bus error affecting
8630 * this device has been detected.
8632 static pci_ers_result_t
s2io_io_error_detected(struct pci_dev
*pdev
,
8633 pci_channel_state_t state
)
8635 struct net_device
*netdev
= pci_get_drvdata(pdev
);
8636 struct s2io_nic
*sp
= netdev_priv(netdev
);
8638 netif_device_detach(netdev
);
8640 if (netif_running(netdev
)) {
8641 /* Bring down the card, while avoiding PCI I/O */
8642 do_s2io_card_down(sp
, 0);
8644 pci_disable_device(pdev
);
8646 return PCI_ERS_RESULT_NEED_RESET
;
8650 * s2io_io_slot_reset - called after the pci bus has been reset.
8651 * @pdev: Pointer to PCI device
8653 * Restart the card from scratch, as if from a cold-boot.
8654 * At this point, the card has exprienced a hard reset,
8655 * followed by fixups by BIOS, and has its config space
8656 * set up identically to what it was at cold boot.
8658 static pci_ers_result_t
s2io_io_slot_reset(struct pci_dev
*pdev
)
8660 struct net_device
*netdev
= pci_get_drvdata(pdev
);
8661 struct s2io_nic
*sp
= netdev_priv(netdev
);
8663 if (pci_enable_device(pdev
)) {
8664 printk(KERN_ERR
"s2io: "
8665 "Cannot re-enable PCI device after reset.\n");
8666 return PCI_ERS_RESULT_DISCONNECT
;
8669 pci_set_master(pdev
);
8672 return PCI_ERS_RESULT_RECOVERED
;
8676 * s2io_io_resume - called when traffic can start flowing again.
8677 * @pdev: Pointer to PCI device
8679 * This callback is called when the error recovery driver tells
8680 * us that its OK to resume normal operation.
8682 static void s2io_io_resume(struct pci_dev
*pdev
)
8684 struct net_device
*netdev
= pci_get_drvdata(pdev
);
8685 struct s2io_nic
*sp
= netdev_priv(netdev
);
8687 if (netif_running(netdev
)) {
8688 if (s2io_card_up(sp
)) {
8689 printk(KERN_ERR
"s2io: "
8690 "Can't bring device back up after reset.\n");
8694 if (s2io_set_mac_addr(netdev
, netdev
->dev_addr
) == FAILURE
) {
8696 printk(KERN_ERR
"s2io: "
8697 "Can't resetore mac addr after reset.\n");
8702 netif_device_attach(netdev
);
8703 netif_tx_wake_all_queues(netdev
);