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e1000e: remove e1000_queue_stats
[deliverable/linux.git] / drivers / net / sh_eth.c
1 /*
2 * SuperH Ethernet device driver
3 *
4 * Copyright (C) 2006-2008 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2009 Renesas Solutions Corp.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 */
22
23 #include <linux/init.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/etherdevice.h>
26 #include <linux/delay.h>
27 #include <linux/platform_device.h>
28 #include <linux/mdio-bitbang.h>
29 #include <linux/netdevice.h>
30 #include <linux/phy.h>
31 #include <linux/cache.h>
32 #include <linux/io.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/slab.h>
35 #include <linux/ethtool.h>
36
37 #include "sh_eth.h"
38
39 #define SH_ETH_DEF_MSG_ENABLE \
40 (NETIF_MSG_LINK | \
41 NETIF_MSG_TIMER | \
42 NETIF_MSG_RX_ERR| \
43 NETIF_MSG_TX_ERR)
44
45 /* There is CPU dependent code */
46 #if defined(CONFIG_CPU_SUBTYPE_SH7724)
47 #define SH_ETH_RESET_DEFAULT 1
48 static void sh_eth_set_duplex(struct net_device *ndev)
49 {
50 struct sh_eth_private *mdp = netdev_priv(ndev);
51
52 if (mdp->duplex) /* Full */
53 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
54 else /* Half */
55 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
56 }
57
58 static void sh_eth_set_rate(struct net_device *ndev)
59 {
60 struct sh_eth_private *mdp = netdev_priv(ndev);
61
62 switch (mdp->speed) {
63 case 10: /* 10BASE */
64 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
65 break;
66 case 100:/* 100BASE */
67 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
68 break;
69 default:
70 break;
71 }
72 }
73
74 /* SH7724 */
75 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
76 .set_duplex = sh_eth_set_duplex,
77 .set_rate = sh_eth_set_rate,
78
79 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
80 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
81 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f,
82
83 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
84 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
85 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
86 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
87
88 .apr = 1,
89 .mpr = 1,
90 .tpauser = 1,
91 .hw_swap = 1,
92 .rpadir = 1,
93 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
94 };
95 #elif defined(CONFIG_CPU_SUBTYPE_SH7757)
96 #define SH_ETH_HAS_BOTH_MODULES 1
97 #define SH_ETH_HAS_TSU 1
98 static void sh_eth_set_duplex(struct net_device *ndev)
99 {
100 struct sh_eth_private *mdp = netdev_priv(ndev);
101
102 if (mdp->duplex) /* Full */
103 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
104 else /* Half */
105 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
106 }
107
108 static void sh_eth_set_rate(struct net_device *ndev)
109 {
110 struct sh_eth_private *mdp = netdev_priv(ndev);
111
112 switch (mdp->speed) {
113 case 10: /* 10BASE */
114 sh_eth_write(ndev, 0, RTRATE);
115 break;
116 case 100:/* 100BASE */
117 sh_eth_write(ndev, 1, RTRATE);
118 break;
119 default:
120 break;
121 }
122 }
123
124 /* SH7757 */
125 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
126 .set_duplex = sh_eth_set_duplex,
127 .set_rate = sh_eth_set_rate,
128
129 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
130 .rmcr_value = 0x00000001,
131
132 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
133 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
134 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
135 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
136
137 .apr = 1,
138 .mpr = 1,
139 .tpauser = 1,
140 .hw_swap = 1,
141 .no_ade = 1,
142 };
143
144 #define SH_GIGA_ETH_BASE 0xfee00000
145 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
146 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
147 static void sh_eth_chip_reset_giga(struct net_device *ndev)
148 {
149 int i;
150 unsigned long mahr[2], malr[2];
151
152 /* save MAHR and MALR */
153 for (i = 0; i < 2; i++) {
154 malr[i] = readl(GIGA_MALR(i));
155 mahr[i] = readl(GIGA_MAHR(i));
156 }
157
158 /* reset device */
159 writel(ARSTR_ARSTR, SH_GIGA_ETH_BASE + 0x1800);
160 mdelay(1);
161
162 /* restore MAHR and MALR */
163 for (i = 0; i < 2; i++) {
164 writel(malr[i], GIGA_MALR(i));
165 writel(mahr[i], GIGA_MAHR(i));
166 }
167 }
168
169 static int sh_eth_is_gether(struct sh_eth_private *mdp);
170 static void sh_eth_reset(struct net_device *ndev)
171 {
172 struct sh_eth_private *mdp = netdev_priv(ndev);
173 int cnt = 100;
174
175 if (sh_eth_is_gether(mdp)) {
176 sh_eth_write(ndev, 0x03, EDSR);
177 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
178 EDMR);
179 while (cnt > 0) {
180 if (!(sh_eth_read(ndev, EDMR) & 0x3))
181 break;
182 mdelay(1);
183 cnt--;
184 }
185 if (cnt < 0)
186 printk(KERN_ERR "Device reset fail\n");
187
188 /* Table Init */
189 sh_eth_write(ndev, 0x0, TDLAR);
190 sh_eth_write(ndev, 0x0, TDFAR);
191 sh_eth_write(ndev, 0x0, TDFXR);
192 sh_eth_write(ndev, 0x0, TDFFR);
193 sh_eth_write(ndev, 0x0, RDLAR);
194 sh_eth_write(ndev, 0x0, RDFAR);
195 sh_eth_write(ndev, 0x0, RDFXR);
196 sh_eth_write(ndev, 0x0, RDFFR);
197 } else {
198 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
199 EDMR);
200 mdelay(3);
201 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
202 EDMR);
203 }
204 }
205
206 static void sh_eth_set_duplex_giga(struct net_device *ndev)
207 {
208 struct sh_eth_private *mdp = netdev_priv(ndev);
209
210 if (mdp->duplex) /* Full */
211 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
212 else /* Half */
213 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
214 }
215
216 static void sh_eth_set_rate_giga(struct net_device *ndev)
217 {
218 struct sh_eth_private *mdp = netdev_priv(ndev);
219
220 switch (mdp->speed) {
221 case 10: /* 10BASE */
222 sh_eth_write(ndev, 0x00000000, GECMR);
223 break;
224 case 100:/* 100BASE */
225 sh_eth_write(ndev, 0x00000010, GECMR);
226 break;
227 case 1000: /* 1000BASE */
228 sh_eth_write(ndev, 0x00000020, GECMR);
229 break;
230 default:
231 break;
232 }
233 }
234
235 /* SH7757(GETHERC) */
236 static struct sh_eth_cpu_data sh_eth_my_cpu_data_giga = {
237 .chip_reset = sh_eth_chip_reset_giga,
238 .set_duplex = sh_eth_set_duplex_giga,
239 .set_rate = sh_eth_set_rate_giga,
240
241 .ecsr_value = ECSR_ICD | ECSR_MPD,
242 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
243 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
244
245 .tx_check = EESR_TC1 | EESR_FTC,
246 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
247 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
248 EESR_ECI,
249 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
250 EESR_TFE,
251 .fdr_value = 0x0000072f,
252 .rmcr_value = 0x00000001,
253
254 .apr = 1,
255 .mpr = 1,
256 .tpauser = 1,
257 .bculr = 1,
258 .hw_swap = 1,
259 .rpadir = 1,
260 .rpadir_value = 2 << 16,
261 .no_trimd = 1,
262 .no_ade = 1,
263 };
264
265 static struct sh_eth_cpu_data *sh_eth_get_cpu_data(struct sh_eth_private *mdp)
266 {
267 if (sh_eth_is_gether(mdp))
268 return &sh_eth_my_cpu_data_giga;
269 else
270 return &sh_eth_my_cpu_data;
271 }
272
273 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
274 #define SH_ETH_HAS_TSU 1
275 static void sh_eth_chip_reset(struct net_device *ndev)
276 {
277 struct sh_eth_private *mdp = netdev_priv(ndev);
278
279 /* reset device */
280 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
281 mdelay(1);
282 }
283
284 static void sh_eth_reset(struct net_device *ndev)
285 {
286 int cnt = 100;
287
288 sh_eth_write(ndev, EDSR_ENALL, EDSR);
289 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR);
290 while (cnt > 0) {
291 if (!(sh_eth_read(ndev, EDMR) & 0x3))
292 break;
293 mdelay(1);
294 cnt--;
295 }
296 if (cnt == 0)
297 printk(KERN_ERR "Device reset fail\n");
298
299 /* Table Init */
300 sh_eth_write(ndev, 0x0, TDLAR);
301 sh_eth_write(ndev, 0x0, TDFAR);
302 sh_eth_write(ndev, 0x0, TDFXR);
303 sh_eth_write(ndev, 0x0, TDFFR);
304 sh_eth_write(ndev, 0x0, RDLAR);
305 sh_eth_write(ndev, 0x0, RDFAR);
306 sh_eth_write(ndev, 0x0, RDFXR);
307 sh_eth_write(ndev, 0x0, RDFFR);
308 }
309
310 static void sh_eth_set_duplex(struct net_device *ndev)
311 {
312 struct sh_eth_private *mdp = netdev_priv(ndev);
313
314 if (mdp->duplex) /* Full */
315 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
316 else /* Half */
317 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
318 }
319
320 static void sh_eth_set_rate(struct net_device *ndev)
321 {
322 struct sh_eth_private *mdp = netdev_priv(ndev);
323
324 switch (mdp->speed) {
325 case 10: /* 10BASE */
326 sh_eth_write(ndev, GECMR_10, GECMR);
327 break;
328 case 100:/* 100BASE */
329 sh_eth_write(ndev, GECMR_100, GECMR);
330 break;
331 case 1000: /* 1000BASE */
332 sh_eth_write(ndev, GECMR_1000, GECMR);
333 break;
334 default:
335 break;
336 }
337 }
338
339 /* sh7763 */
340 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
341 .chip_reset = sh_eth_chip_reset,
342 .set_duplex = sh_eth_set_duplex,
343 .set_rate = sh_eth_set_rate,
344
345 .ecsr_value = ECSR_ICD | ECSR_MPD,
346 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
347 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
348
349 .tx_check = EESR_TC1 | EESR_FTC,
350 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
351 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
352 EESR_ECI,
353 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
354 EESR_TFE,
355
356 .apr = 1,
357 .mpr = 1,
358 .tpauser = 1,
359 .bculr = 1,
360 .hw_swap = 1,
361 .no_trimd = 1,
362 .no_ade = 1,
363 .tsu = 1,
364 };
365
366 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
367 #define SH_ETH_RESET_DEFAULT 1
368 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
369 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
370
371 .apr = 1,
372 .mpr = 1,
373 .tpauser = 1,
374 .hw_swap = 1,
375 };
376 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
377 #define SH_ETH_RESET_DEFAULT 1
378 #define SH_ETH_HAS_TSU 1
379 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
380 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
381 .tsu = 1,
382 };
383 #endif
384
385 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
386 {
387 if (!cd->ecsr_value)
388 cd->ecsr_value = DEFAULT_ECSR_INIT;
389
390 if (!cd->ecsipr_value)
391 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
392
393 if (!cd->fcftr_value)
394 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
395 DEFAULT_FIFO_F_D_RFD;
396
397 if (!cd->fdr_value)
398 cd->fdr_value = DEFAULT_FDR_INIT;
399
400 if (!cd->rmcr_value)
401 cd->rmcr_value = DEFAULT_RMCR_VALUE;
402
403 if (!cd->tx_check)
404 cd->tx_check = DEFAULT_TX_CHECK;
405
406 if (!cd->eesr_err_check)
407 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
408
409 if (!cd->tx_error_check)
410 cd->tx_error_check = DEFAULT_TX_ERROR_CHECK;
411 }
412
413 #if defined(SH_ETH_RESET_DEFAULT)
414 /* Chip Reset */
415 static void sh_eth_reset(struct net_device *ndev)
416 {
417 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, EDMR);
418 mdelay(3);
419 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, EDMR);
420 }
421 #endif
422
423 #if defined(CONFIG_CPU_SH4)
424 static void sh_eth_set_receive_align(struct sk_buff *skb)
425 {
426 int reserve;
427
428 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
429 if (reserve)
430 skb_reserve(skb, reserve);
431 }
432 #else
433 static void sh_eth_set_receive_align(struct sk_buff *skb)
434 {
435 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
436 }
437 #endif
438
439
440 /* CPU <-> EDMAC endian convert */
441 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
442 {
443 switch (mdp->edmac_endian) {
444 case EDMAC_LITTLE_ENDIAN:
445 return cpu_to_le32(x);
446 case EDMAC_BIG_ENDIAN:
447 return cpu_to_be32(x);
448 }
449 return x;
450 }
451
452 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
453 {
454 switch (mdp->edmac_endian) {
455 case EDMAC_LITTLE_ENDIAN:
456 return le32_to_cpu(x);
457 case EDMAC_BIG_ENDIAN:
458 return be32_to_cpu(x);
459 }
460 return x;
461 }
462
463 /*
464 * Program the hardware MAC address from dev->dev_addr.
465 */
466 static void update_mac_address(struct net_device *ndev)
467 {
468 sh_eth_write(ndev,
469 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
470 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
471 sh_eth_write(ndev,
472 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
473 }
474
475 /*
476 * Get MAC address from SuperH MAC address register
477 *
478 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
479 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
480 * When you want use this device, you must set MAC address in bootloader.
481 *
482 */
483 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
484 {
485 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
486 memcpy(ndev->dev_addr, mac, 6);
487 } else {
488 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
489 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
490 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
491 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
492 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
493 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
494 }
495 }
496
497 static int sh_eth_is_gether(struct sh_eth_private *mdp)
498 {
499 if (mdp->reg_offset == sh_eth_offset_gigabit)
500 return 1;
501 else
502 return 0;
503 }
504
505 static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
506 {
507 if (sh_eth_is_gether(mdp))
508 return EDTRR_TRNS_GETHER;
509 else
510 return EDTRR_TRNS_ETHER;
511 }
512
513 struct bb_info {
514 void (*set_gate)(unsigned long addr);
515 struct mdiobb_ctrl ctrl;
516 u32 addr;
517 u32 mmd_msk;/* MMD */
518 u32 mdo_msk;
519 u32 mdi_msk;
520 u32 mdc_msk;
521 };
522
523 /* PHY bit set */
524 static void bb_set(u32 addr, u32 msk)
525 {
526 writel(readl(addr) | msk, addr);
527 }
528
529 /* PHY bit clear */
530 static void bb_clr(u32 addr, u32 msk)
531 {
532 writel((readl(addr) & ~msk), addr);
533 }
534
535 /* PHY bit read */
536 static int bb_read(u32 addr, u32 msk)
537 {
538 return (readl(addr) & msk) != 0;
539 }
540
541 /* Data I/O pin control */
542 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
543 {
544 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
545
546 if (bitbang->set_gate)
547 bitbang->set_gate(bitbang->addr);
548
549 if (bit)
550 bb_set(bitbang->addr, bitbang->mmd_msk);
551 else
552 bb_clr(bitbang->addr, bitbang->mmd_msk);
553 }
554
555 /* Set bit data*/
556 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
557 {
558 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
559
560 if (bitbang->set_gate)
561 bitbang->set_gate(bitbang->addr);
562
563 if (bit)
564 bb_set(bitbang->addr, bitbang->mdo_msk);
565 else
566 bb_clr(bitbang->addr, bitbang->mdo_msk);
567 }
568
569 /* Get bit data*/
570 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
571 {
572 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
573
574 if (bitbang->set_gate)
575 bitbang->set_gate(bitbang->addr);
576
577 return bb_read(bitbang->addr, bitbang->mdi_msk);
578 }
579
580 /* MDC pin control */
581 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
582 {
583 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
584
585 if (bitbang->set_gate)
586 bitbang->set_gate(bitbang->addr);
587
588 if (bit)
589 bb_set(bitbang->addr, bitbang->mdc_msk);
590 else
591 bb_clr(bitbang->addr, bitbang->mdc_msk);
592 }
593
594 /* mdio bus control struct */
595 static struct mdiobb_ops bb_ops = {
596 .owner = THIS_MODULE,
597 .set_mdc = sh_mdc_ctrl,
598 .set_mdio_dir = sh_mmd_ctrl,
599 .set_mdio_data = sh_set_mdio,
600 .get_mdio_data = sh_get_mdio,
601 };
602
603 /* free skb and descriptor buffer */
604 static void sh_eth_ring_free(struct net_device *ndev)
605 {
606 struct sh_eth_private *mdp = netdev_priv(ndev);
607 int i;
608
609 /* Free Rx skb ringbuffer */
610 if (mdp->rx_skbuff) {
611 for (i = 0; i < RX_RING_SIZE; i++) {
612 if (mdp->rx_skbuff[i])
613 dev_kfree_skb(mdp->rx_skbuff[i]);
614 }
615 }
616 kfree(mdp->rx_skbuff);
617
618 /* Free Tx skb ringbuffer */
619 if (mdp->tx_skbuff) {
620 for (i = 0; i < TX_RING_SIZE; i++) {
621 if (mdp->tx_skbuff[i])
622 dev_kfree_skb(mdp->tx_skbuff[i]);
623 }
624 }
625 kfree(mdp->tx_skbuff);
626 }
627
628 /* format skb and descriptor buffer */
629 static void sh_eth_ring_format(struct net_device *ndev)
630 {
631 struct sh_eth_private *mdp = netdev_priv(ndev);
632 int i;
633 struct sk_buff *skb;
634 struct sh_eth_rxdesc *rxdesc = NULL;
635 struct sh_eth_txdesc *txdesc = NULL;
636 int rx_ringsize = sizeof(*rxdesc) * RX_RING_SIZE;
637 int tx_ringsize = sizeof(*txdesc) * TX_RING_SIZE;
638
639 mdp->cur_rx = mdp->cur_tx = 0;
640 mdp->dirty_rx = mdp->dirty_tx = 0;
641
642 memset(mdp->rx_ring, 0, rx_ringsize);
643
644 /* build Rx ring buffer */
645 for (i = 0; i < RX_RING_SIZE; i++) {
646 /* skb */
647 mdp->rx_skbuff[i] = NULL;
648 skb = dev_alloc_skb(mdp->rx_buf_sz);
649 mdp->rx_skbuff[i] = skb;
650 if (skb == NULL)
651 break;
652 dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz,
653 DMA_FROM_DEVICE);
654 skb->dev = ndev; /* Mark as being used by this device. */
655 sh_eth_set_receive_align(skb);
656
657 /* RX descriptor */
658 rxdesc = &mdp->rx_ring[i];
659 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
660 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
661
662 /* The size of the buffer is 16 byte boundary. */
663 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
664 /* Rx descriptor address set */
665 if (i == 0) {
666 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
667 if (sh_eth_is_gether(mdp))
668 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
669 }
670 }
671
672 mdp->dirty_rx = (u32) (i - RX_RING_SIZE);
673
674 /* Mark the last entry as wrapping the ring. */
675 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
676
677 memset(mdp->tx_ring, 0, tx_ringsize);
678
679 /* build Tx ring buffer */
680 for (i = 0; i < TX_RING_SIZE; i++) {
681 mdp->tx_skbuff[i] = NULL;
682 txdesc = &mdp->tx_ring[i];
683 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
684 txdesc->buffer_length = 0;
685 if (i == 0) {
686 /* Tx descriptor address set */
687 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
688 if (sh_eth_is_gether(mdp))
689 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
690 }
691 }
692
693 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
694 }
695
696 /* Get skb and descriptor buffer */
697 static int sh_eth_ring_init(struct net_device *ndev)
698 {
699 struct sh_eth_private *mdp = netdev_priv(ndev);
700 int rx_ringsize, tx_ringsize, ret = 0;
701
702 /*
703 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
704 * card needs room to do 8 byte alignment, +2 so we can reserve
705 * the first 2 bytes, and +16 gets room for the status word from the
706 * card.
707 */
708 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
709 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
710 if (mdp->cd->rpadir)
711 mdp->rx_buf_sz += NET_IP_ALIGN;
712
713 /* Allocate RX and TX skb rings */
714 mdp->rx_skbuff = kmalloc(sizeof(*mdp->rx_skbuff) * RX_RING_SIZE,
715 GFP_KERNEL);
716 if (!mdp->rx_skbuff) {
717 dev_err(&ndev->dev, "Cannot allocate Rx skb\n");
718 ret = -ENOMEM;
719 return ret;
720 }
721
722 mdp->tx_skbuff = kmalloc(sizeof(*mdp->tx_skbuff) * TX_RING_SIZE,
723 GFP_KERNEL);
724 if (!mdp->tx_skbuff) {
725 dev_err(&ndev->dev, "Cannot allocate Tx skb\n");
726 ret = -ENOMEM;
727 goto skb_ring_free;
728 }
729
730 /* Allocate all Rx descriptors. */
731 rx_ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
732 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
733 GFP_KERNEL);
734
735 if (!mdp->rx_ring) {
736 dev_err(&ndev->dev, "Cannot allocate Rx Ring (size %d bytes)\n",
737 rx_ringsize);
738 ret = -ENOMEM;
739 goto desc_ring_free;
740 }
741
742 mdp->dirty_rx = 0;
743
744 /* Allocate all Tx descriptors. */
745 tx_ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
746 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
747 GFP_KERNEL);
748 if (!mdp->tx_ring) {
749 dev_err(&ndev->dev, "Cannot allocate Tx Ring (size %d bytes)\n",
750 tx_ringsize);
751 ret = -ENOMEM;
752 goto desc_ring_free;
753 }
754 return ret;
755
756 desc_ring_free:
757 /* free DMA buffer */
758 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
759
760 skb_ring_free:
761 /* Free Rx and Tx skb ring buffer */
762 sh_eth_ring_free(ndev);
763
764 return ret;
765 }
766
767 static int sh_eth_dev_init(struct net_device *ndev)
768 {
769 int ret = 0;
770 struct sh_eth_private *mdp = netdev_priv(ndev);
771 u_int32_t rx_int_var, tx_int_var;
772 u32 val;
773
774 /* Soft Reset */
775 sh_eth_reset(ndev);
776
777 /* Descriptor format */
778 sh_eth_ring_format(ndev);
779 if (mdp->cd->rpadir)
780 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
781
782 /* all sh_eth int mask */
783 sh_eth_write(ndev, 0, EESIPR);
784
785 #if defined(__LITTLE_ENDIAN__)
786 if (mdp->cd->hw_swap)
787 sh_eth_write(ndev, EDMR_EL, EDMR);
788 else
789 #endif
790 sh_eth_write(ndev, 0, EDMR);
791
792 /* FIFO size set */
793 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
794 sh_eth_write(ndev, 0, TFTR);
795
796 /* Frame recv control */
797 sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR);
798
799 rx_int_var = mdp->rx_int_var = DESC_I_RINT8 | DESC_I_RINT5;
800 tx_int_var = mdp->tx_int_var = DESC_I_TINT2;
801 sh_eth_write(ndev, rx_int_var | tx_int_var, TRSCER);
802
803 if (mdp->cd->bculr)
804 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
805
806 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
807
808 if (!mdp->cd->no_trimd)
809 sh_eth_write(ndev, 0, TRIMD);
810
811 /* Recv frame limit set register */
812 sh_eth_write(ndev, RFLR_VALUE, RFLR);
813
814 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
815 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
816
817 /* PAUSE Prohibition */
818 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
819 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
820
821 sh_eth_write(ndev, val, ECMR);
822
823 if (mdp->cd->set_rate)
824 mdp->cd->set_rate(ndev);
825
826 /* E-MAC Status Register clear */
827 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
828
829 /* E-MAC Interrupt Enable register */
830 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
831
832 /* Set MAC address */
833 update_mac_address(ndev);
834
835 /* mask reset */
836 if (mdp->cd->apr)
837 sh_eth_write(ndev, APR_AP, APR);
838 if (mdp->cd->mpr)
839 sh_eth_write(ndev, MPR_MP, MPR);
840 if (mdp->cd->tpauser)
841 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
842
843 /* Setting the Rx mode will start the Rx process. */
844 sh_eth_write(ndev, EDRRR_R, EDRRR);
845
846 netif_start_queue(ndev);
847
848 return ret;
849 }
850
851 /* free Tx skb function */
852 static int sh_eth_txfree(struct net_device *ndev)
853 {
854 struct sh_eth_private *mdp = netdev_priv(ndev);
855 struct sh_eth_txdesc *txdesc;
856 int freeNum = 0;
857 int entry = 0;
858
859 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
860 entry = mdp->dirty_tx % TX_RING_SIZE;
861 txdesc = &mdp->tx_ring[entry];
862 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
863 break;
864 /* Free the original skb. */
865 if (mdp->tx_skbuff[entry]) {
866 dma_unmap_single(&ndev->dev, txdesc->addr,
867 txdesc->buffer_length, DMA_TO_DEVICE);
868 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
869 mdp->tx_skbuff[entry] = NULL;
870 freeNum++;
871 }
872 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
873 if (entry >= TX_RING_SIZE - 1)
874 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
875
876 mdp->stats.tx_packets++;
877 mdp->stats.tx_bytes += txdesc->buffer_length;
878 }
879 return freeNum;
880 }
881
882 /* Packet receive function */
883 static int sh_eth_rx(struct net_device *ndev)
884 {
885 struct sh_eth_private *mdp = netdev_priv(ndev);
886 struct sh_eth_rxdesc *rxdesc;
887
888 int entry = mdp->cur_rx % RX_RING_SIZE;
889 int boguscnt = (mdp->dirty_rx + RX_RING_SIZE) - mdp->cur_rx;
890 struct sk_buff *skb;
891 u16 pkt_len = 0;
892 u32 desc_status;
893
894 rxdesc = &mdp->rx_ring[entry];
895 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
896 desc_status = edmac_to_cpu(mdp, rxdesc->status);
897 pkt_len = rxdesc->frame_length;
898
899 if (--boguscnt < 0)
900 break;
901
902 if (!(desc_status & RDFEND))
903 mdp->stats.rx_length_errors++;
904
905 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
906 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
907 mdp->stats.rx_errors++;
908 if (desc_status & RD_RFS1)
909 mdp->stats.rx_crc_errors++;
910 if (desc_status & RD_RFS2)
911 mdp->stats.rx_frame_errors++;
912 if (desc_status & RD_RFS3)
913 mdp->stats.rx_length_errors++;
914 if (desc_status & RD_RFS4)
915 mdp->stats.rx_length_errors++;
916 if (desc_status & RD_RFS6)
917 mdp->stats.rx_missed_errors++;
918 if (desc_status & RD_RFS10)
919 mdp->stats.rx_over_errors++;
920 } else {
921 if (!mdp->cd->hw_swap)
922 sh_eth_soft_swap(
923 phys_to_virt(ALIGN(rxdesc->addr, 4)),
924 pkt_len + 2);
925 skb = mdp->rx_skbuff[entry];
926 mdp->rx_skbuff[entry] = NULL;
927 if (mdp->cd->rpadir)
928 skb_reserve(skb, NET_IP_ALIGN);
929 skb_put(skb, pkt_len);
930 skb->protocol = eth_type_trans(skb, ndev);
931 netif_rx(skb);
932 mdp->stats.rx_packets++;
933 mdp->stats.rx_bytes += pkt_len;
934 }
935 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
936 entry = (++mdp->cur_rx) % RX_RING_SIZE;
937 rxdesc = &mdp->rx_ring[entry];
938 }
939
940 /* Refill the Rx ring buffers. */
941 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
942 entry = mdp->dirty_rx % RX_RING_SIZE;
943 rxdesc = &mdp->rx_ring[entry];
944 /* The size of the buffer is 16 byte boundary. */
945 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
946
947 if (mdp->rx_skbuff[entry] == NULL) {
948 skb = dev_alloc_skb(mdp->rx_buf_sz);
949 mdp->rx_skbuff[entry] = skb;
950 if (skb == NULL)
951 break; /* Better luck next round. */
952 dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz,
953 DMA_FROM_DEVICE);
954 skb->dev = ndev;
955 sh_eth_set_receive_align(skb);
956
957 skb_checksum_none_assert(skb);
958 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
959 }
960 if (entry >= RX_RING_SIZE - 1)
961 rxdesc->status |=
962 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
963 else
964 rxdesc->status |=
965 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
966 }
967
968 /* Restart Rx engine if stopped. */
969 /* If we don't need to check status, don't. -KDU */
970 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R))
971 sh_eth_write(ndev, EDRRR_R, EDRRR);
972
973 return 0;
974 }
975
976 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
977 {
978 /* disable tx and rx */
979 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
980 ~(ECMR_RE | ECMR_TE), ECMR);
981 }
982
983 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
984 {
985 /* enable tx and rx */
986 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
987 (ECMR_RE | ECMR_TE), ECMR);
988 }
989
990 /* error control function */
991 static void sh_eth_error(struct net_device *ndev, int intr_status)
992 {
993 struct sh_eth_private *mdp = netdev_priv(ndev);
994 u32 felic_stat;
995 u32 link_stat;
996 u32 mask;
997
998 if (intr_status & EESR_ECI) {
999 felic_stat = sh_eth_read(ndev, ECSR);
1000 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1001 if (felic_stat & ECSR_ICD)
1002 mdp->stats.tx_carrier_errors++;
1003 if (felic_stat & ECSR_LCHNG) {
1004 /* Link Changed */
1005 if (mdp->cd->no_psr || mdp->no_ether_link) {
1006 if (mdp->link == PHY_DOWN)
1007 link_stat = 0;
1008 else
1009 link_stat = PHY_ST_LINK;
1010 } else {
1011 link_stat = (sh_eth_read(ndev, PSR));
1012 if (mdp->ether_link_active_low)
1013 link_stat = ~link_stat;
1014 }
1015 if (!(link_stat & PHY_ST_LINK))
1016 sh_eth_rcv_snd_disable(ndev);
1017 else {
1018 /* Link Up */
1019 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1020 ~DMAC_M_ECI, EESIPR);
1021 /*clear int */
1022 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1023 ECSR);
1024 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1025 DMAC_M_ECI, EESIPR);
1026 /* enable tx and rx */
1027 sh_eth_rcv_snd_enable(ndev);
1028 }
1029 }
1030 }
1031
1032 if (intr_status & EESR_TWB) {
1033 /* Write buck end. unused write back interrupt */
1034 if (intr_status & EESR_TABT) /* Transmit Abort int */
1035 mdp->stats.tx_aborted_errors++;
1036 if (netif_msg_tx_err(mdp))
1037 dev_err(&ndev->dev, "Transmit Abort\n");
1038 }
1039
1040 if (intr_status & EESR_RABT) {
1041 /* Receive Abort int */
1042 if (intr_status & EESR_RFRMER) {
1043 /* Receive Frame Overflow int */
1044 mdp->stats.rx_frame_errors++;
1045 if (netif_msg_rx_err(mdp))
1046 dev_err(&ndev->dev, "Receive Abort\n");
1047 }
1048 }
1049
1050 if (intr_status & EESR_TDE) {
1051 /* Transmit Descriptor Empty int */
1052 mdp->stats.tx_fifo_errors++;
1053 if (netif_msg_tx_err(mdp))
1054 dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
1055 }
1056
1057 if (intr_status & EESR_TFE) {
1058 /* FIFO under flow */
1059 mdp->stats.tx_fifo_errors++;
1060 if (netif_msg_tx_err(mdp))
1061 dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
1062 }
1063
1064 if (intr_status & EESR_RDE) {
1065 /* Receive Descriptor Empty int */
1066 mdp->stats.rx_over_errors++;
1067
1068 if (sh_eth_read(ndev, EDRRR) ^ EDRRR_R)
1069 sh_eth_write(ndev, EDRRR_R, EDRRR);
1070 if (netif_msg_rx_err(mdp))
1071 dev_err(&ndev->dev, "Receive Descriptor Empty\n");
1072 }
1073
1074 if (intr_status & EESR_RFE) {
1075 /* Receive FIFO Overflow int */
1076 mdp->stats.rx_fifo_errors++;
1077 if (netif_msg_rx_err(mdp))
1078 dev_err(&ndev->dev, "Receive FIFO Overflow\n");
1079 }
1080
1081 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1082 /* Address Error */
1083 mdp->stats.tx_fifo_errors++;
1084 if (netif_msg_tx_err(mdp))
1085 dev_err(&ndev->dev, "Address Error\n");
1086 }
1087
1088 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1089 if (mdp->cd->no_ade)
1090 mask &= ~EESR_ADE;
1091 if (intr_status & mask) {
1092 /* Tx error */
1093 u32 edtrr = sh_eth_read(ndev, EDTRR);
1094 /* dmesg */
1095 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
1096 intr_status, mdp->cur_tx);
1097 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1098 mdp->dirty_tx, (u32) ndev->state, edtrr);
1099 /* dirty buffer free */
1100 sh_eth_txfree(ndev);
1101
1102 /* SH7712 BUG */
1103 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1104 /* tx dma start */
1105 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1106 }
1107 /* wakeup */
1108 netif_wake_queue(ndev);
1109 }
1110 }
1111
1112 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1113 {
1114 struct net_device *ndev = netdev;
1115 struct sh_eth_private *mdp = netdev_priv(ndev);
1116 struct sh_eth_cpu_data *cd = mdp->cd;
1117 irqreturn_t ret = IRQ_NONE;
1118 u32 intr_status = 0;
1119
1120 spin_lock(&mdp->lock);
1121
1122 /* Get interrpt stat */
1123 intr_status = sh_eth_read(ndev, EESR);
1124 /* Clear interrupt */
1125 if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF |
1126 EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF |
1127 cd->tx_check | cd->eesr_err_check)) {
1128 sh_eth_write(ndev, intr_status, EESR);
1129 ret = IRQ_HANDLED;
1130 } else
1131 goto other_irq;
1132
1133 if (intr_status & (EESR_FRC | /* Frame recv*/
1134 EESR_RMAF | /* Multi cast address recv*/
1135 EESR_RRF | /* Bit frame recv */
1136 EESR_RTLF | /* Long frame recv*/
1137 EESR_RTSF | /* short frame recv */
1138 EESR_PRE | /* PHY-LSI recv error */
1139 EESR_CERF)){ /* recv frame CRC error */
1140 sh_eth_rx(ndev);
1141 }
1142
1143 /* Tx Check */
1144 if (intr_status & cd->tx_check) {
1145 sh_eth_txfree(ndev);
1146 netif_wake_queue(ndev);
1147 }
1148
1149 if (intr_status & cd->eesr_err_check)
1150 sh_eth_error(ndev, intr_status);
1151
1152 other_irq:
1153 spin_unlock(&mdp->lock);
1154
1155 return ret;
1156 }
1157
1158 static void sh_eth_timer(unsigned long data)
1159 {
1160 struct net_device *ndev = (struct net_device *)data;
1161 struct sh_eth_private *mdp = netdev_priv(ndev);
1162
1163 mod_timer(&mdp->timer, jiffies + (10 * HZ));
1164 }
1165
1166 /* PHY state control function */
1167 static void sh_eth_adjust_link(struct net_device *ndev)
1168 {
1169 struct sh_eth_private *mdp = netdev_priv(ndev);
1170 struct phy_device *phydev = mdp->phydev;
1171 int new_state = 0;
1172
1173 if (phydev->link != PHY_DOWN) {
1174 if (phydev->duplex != mdp->duplex) {
1175 new_state = 1;
1176 mdp->duplex = phydev->duplex;
1177 if (mdp->cd->set_duplex)
1178 mdp->cd->set_duplex(ndev);
1179 }
1180
1181 if (phydev->speed != mdp->speed) {
1182 new_state = 1;
1183 mdp->speed = phydev->speed;
1184 if (mdp->cd->set_rate)
1185 mdp->cd->set_rate(ndev);
1186 }
1187 if (mdp->link == PHY_DOWN) {
1188 sh_eth_write(ndev, (sh_eth_read(ndev, ECMR) & ~ECMR_TXF)
1189 | ECMR_DM, ECMR);
1190 new_state = 1;
1191 mdp->link = phydev->link;
1192 }
1193 } else if (mdp->link) {
1194 new_state = 1;
1195 mdp->link = PHY_DOWN;
1196 mdp->speed = 0;
1197 mdp->duplex = -1;
1198 }
1199
1200 if (new_state && netif_msg_link(mdp))
1201 phy_print_status(phydev);
1202 }
1203
1204 /* PHY init function */
1205 static int sh_eth_phy_init(struct net_device *ndev)
1206 {
1207 struct sh_eth_private *mdp = netdev_priv(ndev);
1208 char phy_id[MII_BUS_ID_SIZE + 3];
1209 struct phy_device *phydev = NULL;
1210
1211 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1212 mdp->mii_bus->id , mdp->phy_id);
1213
1214 mdp->link = PHY_DOWN;
1215 mdp->speed = 0;
1216 mdp->duplex = -1;
1217
1218 /* Try connect to PHY */
1219 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1220 0, mdp->phy_interface);
1221 if (IS_ERR(phydev)) {
1222 dev_err(&ndev->dev, "phy_connect failed\n");
1223 return PTR_ERR(phydev);
1224 }
1225
1226 dev_info(&ndev->dev, "attached phy %i to driver %s\n",
1227 phydev->addr, phydev->drv->name);
1228
1229 mdp->phydev = phydev;
1230
1231 return 0;
1232 }
1233
1234 /* PHY control start function */
1235 static int sh_eth_phy_start(struct net_device *ndev)
1236 {
1237 struct sh_eth_private *mdp = netdev_priv(ndev);
1238 int ret;
1239
1240 ret = sh_eth_phy_init(ndev);
1241 if (ret)
1242 return ret;
1243
1244 /* reset phy - this also wakes it from PDOWN */
1245 phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
1246 phy_start(mdp->phydev);
1247
1248 return 0;
1249 }
1250
1251 static int sh_eth_get_settings(struct net_device *ndev,
1252 struct ethtool_cmd *ecmd)
1253 {
1254 struct sh_eth_private *mdp = netdev_priv(ndev);
1255 unsigned long flags;
1256 int ret;
1257
1258 spin_lock_irqsave(&mdp->lock, flags);
1259 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1260 spin_unlock_irqrestore(&mdp->lock, flags);
1261
1262 return ret;
1263 }
1264
1265 static int sh_eth_set_settings(struct net_device *ndev,
1266 struct ethtool_cmd *ecmd)
1267 {
1268 struct sh_eth_private *mdp = netdev_priv(ndev);
1269 unsigned long flags;
1270 int ret;
1271
1272 spin_lock_irqsave(&mdp->lock, flags);
1273
1274 /* disable tx and rx */
1275 sh_eth_rcv_snd_disable(ndev);
1276
1277 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1278 if (ret)
1279 goto error_exit;
1280
1281 if (ecmd->duplex == DUPLEX_FULL)
1282 mdp->duplex = 1;
1283 else
1284 mdp->duplex = 0;
1285
1286 if (mdp->cd->set_duplex)
1287 mdp->cd->set_duplex(ndev);
1288
1289 error_exit:
1290 mdelay(1);
1291
1292 /* enable tx and rx */
1293 sh_eth_rcv_snd_enable(ndev);
1294
1295 spin_unlock_irqrestore(&mdp->lock, flags);
1296
1297 return ret;
1298 }
1299
1300 static int sh_eth_nway_reset(struct net_device *ndev)
1301 {
1302 struct sh_eth_private *mdp = netdev_priv(ndev);
1303 unsigned long flags;
1304 int ret;
1305
1306 spin_lock_irqsave(&mdp->lock, flags);
1307 ret = phy_start_aneg(mdp->phydev);
1308 spin_unlock_irqrestore(&mdp->lock, flags);
1309
1310 return ret;
1311 }
1312
1313 static u32 sh_eth_get_msglevel(struct net_device *ndev)
1314 {
1315 struct sh_eth_private *mdp = netdev_priv(ndev);
1316 return mdp->msg_enable;
1317 }
1318
1319 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1320 {
1321 struct sh_eth_private *mdp = netdev_priv(ndev);
1322 mdp->msg_enable = value;
1323 }
1324
1325 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1326 "rx_current", "tx_current",
1327 "rx_dirty", "tx_dirty",
1328 };
1329 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1330
1331 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1332 {
1333 switch (sset) {
1334 case ETH_SS_STATS:
1335 return SH_ETH_STATS_LEN;
1336 default:
1337 return -EOPNOTSUPP;
1338 }
1339 }
1340
1341 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1342 struct ethtool_stats *stats, u64 *data)
1343 {
1344 struct sh_eth_private *mdp = netdev_priv(ndev);
1345 int i = 0;
1346
1347 /* device-specific stats */
1348 data[i++] = mdp->cur_rx;
1349 data[i++] = mdp->cur_tx;
1350 data[i++] = mdp->dirty_rx;
1351 data[i++] = mdp->dirty_tx;
1352 }
1353
1354 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1355 {
1356 switch (stringset) {
1357 case ETH_SS_STATS:
1358 memcpy(data, *sh_eth_gstrings_stats,
1359 sizeof(sh_eth_gstrings_stats));
1360 break;
1361 }
1362 }
1363
1364 static struct ethtool_ops sh_eth_ethtool_ops = {
1365 .get_settings = sh_eth_get_settings,
1366 .set_settings = sh_eth_set_settings,
1367 .nway_reset = sh_eth_nway_reset,
1368 .get_msglevel = sh_eth_get_msglevel,
1369 .set_msglevel = sh_eth_set_msglevel,
1370 .get_link = ethtool_op_get_link,
1371 .get_strings = sh_eth_get_strings,
1372 .get_ethtool_stats = sh_eth_get_ethtool_stats,
1373 .get_sset_count = sh_eth_get_sset_count,
1374 };
1375
1376 /* network device open function */
1377 static int sh_eth_open(struct net_device *ndev)
1378 {
1379 int ret = 0;
1380 struct sh_eth_private *mdp = netdev_priv(ndev);
1381
1382 pm_runtime_get_sync(&mdp->pdev->dev);
1383
1384 ret = request_irq(ndev->irq, sh_eth_interrupt,
1385 #if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
1386 defined(CONFIG_CPU_SUBTYPE_SH7764) || \
1387 defined(CONFIG_CPU_SUBTYPE_SH7757)
1388 IRQF_SHARED,
1389 #else
1390 0,
1391 #endif
1392 ndev->name, ndev);
1393 if (ret) {
1394 dev_err(&ndev->dev, "Can not assign IRQ number\n");
1395 return ret;
1396 }
1397
1398 /* Descriptor set */
1399 ret = sh_eth_ring_init(ndev);
1400 if (ret)
1401 goto out_free_irq;
1402
1403 /* device init */
1404 ret = sh_eth_dev_init(ndev);
1405 if (ret)
1406 goto out_free_irq;
1407
1408 /* PHY control start*/
1409 ret = sh_eth_phy_start(ndev);
1410 if (ret)
1411 goto out_free_irq;
1412
1413 /* Set the timer to check for link beat. */
1414 init_timer(&mdp->timer);
1415 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
1416 setup_timer(&mdp->timer, sh_eth_timer, (unsigned long)ndev);
1417
1418 return ret;
1419
1420 out_free_irq:
1421 free_irq(ndev->irq, ndev);
1422 pm_runtime_put_sync(&mdp->pdev->dev);
1423 return ret;
1424 }
1425
1426 /* Timeout function */
1427 static void sh_eth_tx_timeout(struct net_device *ndev)
1428 {
1429 struct sh_eth_private *mdp = netdev_priv(ndev);
1430 struct sh_eth_rxdesc *rxdesc;
1431 int i;
1432
1433 netif_stop_queue(ndev);
1434
1435 if (netif_msg_timer(mdp))
1436 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x,"
1437 " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR));
1438
1439 /* tx_errors count up */
1440 mdp->stats.tx_errors++;
1441
1442 /* timer off */
1443 del_timer_sync(&mdp->timer);
1444
1445 /* Free all the skbuffs in the Rx queue. */
1446 for (i = 0; i < RX_RING_SIZE; i++) {
1447 rxdesc = &mdp->rx_ring[i];
1448 rxdesc->status = 0;
1449 rxdesc->addr = 0xBADF00D0;
1450 if (mdp->rx_skbuff[i])
1451 dev_kfree_skb(mdp->rx_skbuff[i]);
1452 mdp->rx_skbuff[i] = NULL;
1453 }
1454 for (i = 0; i < TX_RING_SIZE; i++) {
1455 if (mdp->tx_skbuff[i])
1456 dev_kfree_skb(mdp->tx_skbuff[i]);
1457 mdp->tx_skbuff[i] = NULL;
1458 }
1459
1460 /* device init */
1461 sh_eth_dev_init(ndev);
1462
1463 /* timer on */
1464 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
1465 add_timer(&mdp->timer);
1466 }
1467
1468 /* Packet transmit function */
1469 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1470 {
1471 struct sh_eth_private *mdp = netdev_priv(ndev);
1472 struct sh_eth_txdesc *txdesc;
1473 u32 entry;
1474 unsigned long flags;
1475
1476 spin_lock_irqsave(&mdp->lock, flags);
1477 if ((mdp->cur_tx - mdp->dirty_tx) >= (TX_RING_SIZE - 4)) {
1478 if (!sh_eth_txfree(ndev)) {
1479 if (netif_msg_tx_queued(mdp))
1480 dev_warn(&ndev->dev, "TxFD exhausted.\n");
1481 netif_stop_queue(ndev);
1482 spin_unlock_irqrestore(&mdp->lock, flags);
1483 return NETDEV_TX_BUSY;
1484 }
1485 }
1486 spin_unlock_irqrestore(&mdp->lock, flags);
1487
1488 entry = mdp->cur_tx % TX_RING_SIZE;
1489 mdp->tx_skbuff[entry] = skb;
1490 txdesc = &mdp->tx_ring[entry];
1491 /* soft swap. */
1492 if (!mdp->cd->hw_swap)
1493 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
1494 skb->len + 2);
1495 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
1496 DMA_TO_DEVICE);
1497 if (skb->len < ETHERSMALL)
1498 txdesc->buffer_length = ETHERSMALL;
1499 else
1500 txdesc->buffer_length = skb->len;
1501
1502 if (entry >= TX_RING_SIZE - 1)
1503 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
1504 else
1505 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
1506
1507 mdp->cur_tx++;
1508
1509 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
1510 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1511
1512 return NETDEV_TX_OK;
1513 }
1514
1515 /* device close function */
1516 static int sh_eth_close(struct net_device *ndev)
1517 {
1518 struct sh_eth_private *mdp = netdev_priv(ndev);
1519 int ringsize;
1520
1521 netif_stop_queue(ndev);
1522
1523 /* Disable interrupts by clearing the interrupt mask. */
1524 sh_eth_write(ndev, 0x0000, EESIPR);
1525
1526 /* Stop the chip's Tx and Rx processes. */
1527 sh_eth_write(ndev, 0, EDTRR);
1528 sh_eth_write(ndev, 0, EDRRR);
1529
1530 /* PHY Disconnect */
1531 if (mdp->phydev) {
1532 phy_stop(mdp->phydev);
1533 phy_disconnect(mdp->phydev);
1534 }
1535
1536 free_irq(ndev->irq, ndev);
1537
1538 del_timer_sync(&mdp->timer);
1539
1540 /* Free all the skbuffs in the Rx queue. */
1541 sh_eth_ring_free(ndev);
1542
1543 /* free DMA buffer */
1544 ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
1545 dma_free_coherent(NULL, ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1546
1547 /* free DMA buffer */
1548 ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
1549 dma_free_coherent(NULL, ringsize, mdp->tx_ring, mdp->tx_desc_dma);
1550
1551 pm_runtime_put_sync(&mdp->pdev->dev);
1552
1553 return 0;
1554 }
1555
1556 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
1557 {
1558 struct sh_eth_private *mdp = netdev_priv(ndev);
1559
1560 pm_runtime_get_sync(&mdp->pdev->dev);
1561
1562 mdp->stats.tx_dropped += sh_eth_read(ndev, TROCR);
1563 sh_eth_write(ndev, 0, TROCR); /* (write clear) */
1564 mdp->stats.collisions += sh_eth_read(ndev, CDCR);
1565 sh_eth_write(ndev, 0, CDCR); /* (write clear) */
1566 mdp->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
1567 sh_eth_write(ndev, 0, LCCR); /* (write clear) */
1568 if (sh_eth_is_gether(mdp)) {
1569 mdp->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
1570 sh_eth_write(ndev, 0, CERCR); /* (write clear) */
1571 mdp->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
1572 sh_eth_write(ndev, 0, CEECR); /* (write clear) */
1573 } else {
1574 mdp->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
1575 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */
1576 }
1577 pm_runtime_put_sync(&mdp->pdev->dev);
1578
1579 return &mdp->stats;
1580 }
1581
1582 /* ioctl to device funciotn*/
1583 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
1584 int cmd)
1585 {
1586 struct sh_eth_private *mdp = netdev_priv(ndev);
1587 struct phy_device *phydev = mdp->phydev;
1588
1589 if (!netif_running(ndev))
1590 return -EINVAL;
1591
1592 if (!phydev)
1593 return -ENODEV;
1594
1595 return phy_mii_ioctl(phydev, rq, cmd);
1596 }
1597
1598 #if defined(SH_ETH_HAS_TSU)
1599 /* Multicast reception directions set */
1600 static void sh_eth_set_multicast_list(struct net_device *ndev)
1601 {
1602 if (ndev->flags & IFF_PROMISC) {
1603 /* Set promiscuous. */
1604 sh_eth_write(ndev, (sh_eth_read(ndev, ECMR) & ~ECMR_MCT) |
1605 ECMR_PRM, ECMR);
1606 } else {
1607 /* Normal, unicast/broadcast-only mode. */
1608 sh_eth_write(ndev, (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) |
1609 ECMR_MCT, ECMR);
1610 }
1611 }
1612 #endif /* SH_ETH_HAS_TSU */
1613
1614 /* SuperH's TSU register init function */
1615 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
1616 {
1617 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
1618 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
1619 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
1620 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
1621 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
1622 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
1623 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
1624 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
1625 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
1626 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
1627 if (sh_eth_is_gether(mdp)) {
1628 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
1629 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
1630 } else {
1631 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
1632 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
1633 }
1634 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
1635 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
1636 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
1637 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
1638 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
1639 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
1640 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
1641 }
1642
1643 /* MDIO bus release function */
1644 static int sh_mdio_release(struct net_device *ndev)
1645 {
1646 struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
1647
1648 /* unregister mdio bus */
1649 mdiobus_unregister(bus);
1650
1651 /* remove mdio bus info from net_device */
1652 dev_set_drvdata(&ndev->dev, NULL);
1653
1654 /* free interrupts memory */
1655 kfree(bus->irq);
1656
1657 /* free bitbang info */
1658 free_mdio_bitbang(bus);
1659
1660 return 0;
1661 }
1662
1663 /* MDIO bus init function */
1664 static int sh_mdio_init(struct net_device *ndev, int id,
1665 struct sh_eth_plat_data *pd)
1666 {
1667 int ret, i;
1668 struct bb_info *bitbang;
1669 struct sh_eth_private *mdp = netdev_priv(ndev);
1670
1671 /* create bit control struct for PHY */
1672 bitbang = kzalloc(sizeof(struct bb_info), GFP_KERNEL);
1673 if (!bitbang) {
1674 ret = -ENOMEM;
1675 goto out;
1676 }
1677
1678 /* bitbang init */
1679 bitbang->addr = ndev->base_addr + mdp->reg_offset[PIR];
1680 bitbang->set_gate = pd->set_mdio_gate;
1681 bitbang->mdi_msk = 0x08;
1682 bitbang->mdo_msk = 0x04;
1683 bitbang->mmd_msk = 0x02;/* MMD */
1684 bitbang->mdc_msk = 0x01;
1685 bitbang->ctrl.ops = &bb_ops;
1686
1687 /* MII controller setting */
1688 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
1689 if (!mdp->mii_bus) {
1690 ret = -ENOMEM;
1691 goto out_free_bitbang;
1692 }
1693
1694 /* Hook up MII support for ethtool */
1695 mdp->mii_bus->name = "sh_mii";
1696 mdp->mii_bus->parent = &ndev->dev;
1697 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%x", id);
1698
1699 /* PHY IRQ */
1700 mdp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
1701 if (!mdp->mii_bus->irq) {
1702 ret = -ENOMEM;
1703 goto out_free_bus;
1704 }
1705
1706 for (i = 0; i < PHY_MAX_ADDR; i++)
1707 mdp->mii_bus->irq[i] = PHY_POLL;
1708
1709 /* regist mdio bus */
1710 ret = mdiobus_register(mdp->mii_bus);
1711 if (ret)
1712 goto out_free_irq;
1713
1714 dev_set_drvdata(&ndev->dev, mdp->mii_bus);
1715
1716 return 0;
1717
1718 out_free_irq:
1719 kfree(mdp->mii_bus->irq);
1720
1721 out_free_bus:
1722 free_mdio_bitbang(mdp->mii_bus);
1723
1724 out_free_bitbang:
1725 kfree(bitbang);
1726
1727 out:
1728 return ret;
1729 }
1730
1731 static const u16 *sh_eth_get_register_offset(int register_type)
1732 {
1733 const u16 *reg_offset = NULL;
1734
1735 switch (register_type) {
1736 case SH_ETH_REG_GIGABIT:
1737 reg_offset = sh_eth_offset_gigabit;
1738 break;
1739 case SH_ETH_REG_FAST_SH4:
1740 reg_offset = sh_eth_offset_fast_sh4;
1741 break;
1742 case SH_ETH_REG_FAST_SH3_SH2:
1743 reg_offset = sh_eth_offset_fast_sh3_sh2;
1744 break;
1745 default:
1746 printk(KERN_ERR "Unknown register type (%d)\n", register_type);
1747 break;
1748 }
1749
1750 return reg_offset;
1751 }
1752
1753 static const struct net_device_ops sh_eth_netdev_ops = {
1754 .ndo_open = sh_eth_open,
1755 .ndo_stop = sh_eth_close,
1756 .ndo_start_xmit = sh_eth_start_xmit,
1757 .ndo_get_stats = sh_eth_get_stats,
1758 #if defined(SH_ETH_HAS_TSU)
1759 .ndo_set_multicast_list = sh_eth_set_multicast_list,
1760 #endif
1761 .ndo_tx_timeout = sh_eth_tx_timeout,
1762 .ndo_do_ioctl = sh_eth_do_ioctl,
1763 .ndo_validate_addr = eth_validate_addr,
1764 .ndo_set_mac_address = eth_mac_addr,
1765 .ndo_change_mtu = eth_change_mtu,
1766 };
1767
1768 static int sh_eth_drv_probe(struct platform_device *pdev)
1769 {
1770 int ret, devno = 0;
1771 struct resource *res;
1772 struct net_device *ndev = NULL;
1773 struct sh_eth_private *mdp = NULL;
1774 struct sh_eth_plat_data *pd;
1775
1776 /* get base addr */
1777 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1778 if (unlikely(res == NULL)) {
1779 dev_err(&pdev->dev, "invalid resource\n");
1780 ret = -EINVAL;
1781 goto out;
1782 }
1783
1784 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
1785 if (!ndev) {
1786 dev_err(&pdev->dev, "Could not allocate device.\n");
1787 ret = -ENOMEM;
1788 goto out;
1789 }
1790
1791 /* The sh Ether-specific entries in the device structure. */
1792 ndev->base_addr = res->start;
1793 devno = pdev->id;
1794 if (devno < 0)
1795 devno = 0;
1796
1797 ndev->dma = -1;
1798 ret = platform_get_irq(pdev, 0);
1799 if (ret < 0) {
1800 ret = -ENODEV;
1801 goto out_release;
1802 }
1803 ndev->irq = ret;
1804
1805 SET_NETDEV_DEV(ndev, &pdev->dev);
1806
1807 /* Fill in the fields of the device structure with ethernet values. */
1808 ether_setup(ndev);
1809
1810 mdp = netdev_priv(ndev);
1811 spin_lock_init(&mdp->lock);
1812 mdp->pdev = pdev;
1813 pm_runtime_enable(&pdev->dev);
1814 pm_runtime_resume(&pdev->dev);
1815
1816 pd = (struct sh_eth_plat_data *)(pdev->dev.platform_data);
1817 /* get PHY ID */
1818 mdp->phy_id = pd->phy;
1819 mdp->phy_interface = pd->phy_interface;
1820 /* EDMAC endian */
1821 mdp->edmac_endian = pd->edmac_endian;
1822 mdp->no_ether_link = pd->no_ether_link;
1823 mdp->ether_link_active_low = pd->ether_link_active_low;
1824 mdp->reg_offset = sh_eth_get_register_offset(pd->register_type);
1825
1826 /* set cpu data */
1827 #if defined(SH_ETH_HAS_BOTH_MODULES)
1828 mdp->cd = sh_eth_get_cpu_data(mdp);
1829 #else
1830 mdp->cd = &sh_eth_my_cpu_data;
1831 #endif
1832 sh_eth_set_default_cpu_data(mdp->cd);
1833
1834 /* set function */
1835 ndev->netdev_ops = &sh_eth_netdev_ops;
1836 SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
1837 ndev->watchdog_timeo = TX_TIMEOUT;
1838
1839 /* debug message level */
1840 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
1841 mdp->post_rx = POST_RX >> (devno << 1);
1842 mdp->post_fw = POST_FW >> (devno << 1);
1843
1844 /* read and set MAC address */
1845 read_mac_address(ndev, pd->mac_addr);
1846
1847 /* First device only init */
1848 if (!devno) {
1849 if (mdp->cd->tsu) {
1850 struct resource *rtsu;
1851 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1852 if (!rtsu) {
1853 dev_err(&pdev->dev, "Not found TSU resource\n");
1854 goto out_release;
1855 }
1856 mdp->tsu_addr = ioremap(rtsu->start,
1857 resource_size(rtsu));
1858 }
1859 if (mdp->cd->chip_reset)
1860 mdp->cd->chip_reset(ndev);
1861
1862 if (mdp->cd->tsu) {
1863 /* TSU init (Init only)*/
1864 sh_eth_tsu_init(mdp);
1865 }
1866 }
1867
1868 /* network device register */
1869 ret = register_netdev(ndev);
1870 if (ret)
1871 goto out_release;
1872
1873 /* mdio bus init */
1874 ret = sh_mdio_init(ndev, pdev->id, pd);
1875 if (ret)
1876 goto out_unregister;
1877
1878 /* print device information */
1879 pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
1880 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
1881
1882 platform_set_drvdata(pdev, ndev);
1883
1884 return ret;
1885
1886 out_unregister:
1887 unregister_netdev(ndev);
1888
1889 out_release:
1890 /* net_dev free */
1891 if (mdp && mdp->tsu_addr)
1892 iounmap(mdp->tsu_addr);
1893 if (ndev)
1894 free_netdev(ndev);
1895
1896 out:
1897 return ret;
1898 }
1899
1900 static int sh_eth_drv_remove(struct platform_device *pdev)
1901 {
1902 struct net_device *ndev = platform_get_drvdata(pdev);
1903 struct sh_eth_private *mdp = netdev_priv(ndev);
1904
1905 iounmap(mdp->tsu_addr);
1906 sh_mdio_release(ndev);
1907 unregister_netdev(ndev);
1908 pm_runtime_disable(&pdev->dev);
1909 free_netdev(ndev);
1910 platform_set_drvdata(pdev, NULL);
1911
1912 return 0;
1913 }
1914
1915 static int sh_eth_runtime_nop(struct device *dev)
1916 {
1917 /*
1918 * Runtime PM callback shared between ->runtime_suspend()
1919 * and ->runtime_resume(). Simply returns success.
1920 *
1921 * This driver re-initializes all registers after
1922 * pm_runtime_get_sync() anyway so there is no need
1923 * to save and restore registers here.
1924 */
1925 return 0;
1926 }
1927
1928 static struct dev_pm_ops sh_eth_dev_pm_ops = {
1929 .runtime_suspend = sh_eth_runtime_nop,
1930 .runtime_resume = sh_eth_runtime_nop,
1931 };
1932
1933 static struct platform_driver sh_eth_driver = {
1934 .probe = sh_eth_drv_probe,
1935 .remove = sh_eth_drv_remove,
1936 .driver = {
1937 .name = CARDNAME,
1938 .pm = &sh_eth_dev_pm_ops,
1939 },
1940 };
1941
1942 static int __init sh_eth_init(void)
1943 {
1944 return platform_driver_register(&sh_eth_driver);
1945 }
1946
1947 static void __exit sh_eth_cleanup(void)
1948 {
1949 platform_driver_unregister(&sh_eth_driver);
1950 }
1951
1952 module_init(sh_eth_init);
1953 module_exit(sh_eth_cleanup);
1954
1955 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
1956 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
1957 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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