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Merge branch 'forcedeth'
[deliverable/linux.git] / drivers / net / skge.c
1 /*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27 #include <linux/config.h>
28 #include <linux/in.h>
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/moduleparam.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/ethtool.h>
35 #include <linux/pci.h>
36 #include <linux/if_vlan.h>
37 #include <linux/ip.h>
38 #include <linux/delay.h>
39 #include <linux/crc32.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/mii.h>
42 #include <asm/irq.h>
43
44 #include "skge.h"
45
46 #define DRV_NAME "skge"
47 #define DRV_VERSION "1.3"
48 #define PFX DRV_NAME " "
49
50 #define DEFAULT_TX_RING_SIZE 128
51 #define DEFAULT_RX_RING_SIZE 512
52 #define MAX_TX_RING_SIZE 1024
53 #define MAX_RX_RING_SIZE 4096
54 #define RX_COPY_THRESHOLD 128
55 #define RX_BUF_SIZE 1536
56 #define PHY_RETRIES 1000
57 #define ETH_JUMBO_MTU 9000
58 #define TX_WATCHDOG (5 * HZ)
59 #define NAPI_WEIGHT 64
60 #define BLINK_MS 250
61
62 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
63 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
64 MODULE_LICENSE("GPL");
65 MODULE_VERSION(DRV_VERSION);
66
67 static const u32 default_msg
68 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
69 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
70
71 static int debug = -1; /* defaults above */
72 module_param(debug, int, 0);
73 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
74
75 static const struct pci_device_id skge_id_table[] = {
76 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
77 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
78 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
79 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
80 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
81 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
82 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
83 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
84 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
85 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },
86 { 0 }
87 };
88 MODULE_DEVICE_TABLE(pci, skge_id_table);
89
90 static int skge_up(struct net_device *dev);
91 static int skge_down(struct net_device *dev);
92 static void skge_phy_reset(struct skge_port *skge);
93 static void skge_tx_clean(struct skge_port *skge);
94 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
95 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
96 static void genesis_get_stats(struct skge_port *skge, u64 *data);
97 static void yukon_get_stats(struct skge_port *skge, u64 *data);
98 static void yukon_init(struct skge_hw *hw, int port);
99 static void genesis_mac_init(struct skge_hw *hw, int port);
100 static void genesis_link_up(struct skge_port *skge);
101
102 /* Avoid conditionals by using array */
103 static const int txqaddr[] = { Q_XA1, Q_XA2 };
104 static const int rxqaddr[] = { Q_R1, Q_R2 };
105 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
106 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
107 static const u32 portirqmask[] = { IS_PORT_1, IS_PORT_2 };
108
109 static int skge_get_regs_len(struct net_device *dev)
110 {
111 return 0x4000;
112 }
113
114 /*
115 * Returns copy of whole control register region
116 * Note: skip RAM address register because accessing it will
117 * cause bus hangs!
118 */
119 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
120 void *p)
121 {
122 const struct skge_port *skge = netdev_priv(dev);
123 const void __iomem *io = skge->hw->regs;
124
125 regs->version = 1;
126 memset(p, 0, regs->len);
127 memcpy_fromio(p, io, B3_RAM_ADDR);
128
129 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
130 regs->len - B3_RI_WTO_R1);
131 }
132
133 /* Wake on Lan only supported on Yukon chips with rev 1 or above */
134 static int wol_supported(const struct skge_hw *hw)
135 {
136 return !((hw->chip_id == CHIP_ID_GENESIS ||
137 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
138 }
139
140 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
141 {
142 struct skge_port *skge = netdev_priv(dev);
143
144 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
145 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
146 }
147
148 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
149 {
150 struct skge_port *skge = netdev_priv(dev);
151 struct skge_hw *hw = skge->hw;
152
153 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
154 return -EOPNOTSUPP;
155
156 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
157 return -EOPNOTSUPP;
158
159 skge->wol = wol->wolopts == WAKE_MAGIC;
160
161 if (skge->wol) {
162 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
163
164 skge_write16(hw, WOL_CTRL_STAT,
165 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
166 WOL_CTL_ENA_MAGIC_PKT_UNIT);
167 } else
168 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
169
170 return 0;
171 }
172
173 /* Determine supported/advertised modes based on hardware.
174 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
175 */
176 static u32 skge_supported_modes(const struct skge_hw *hw)
177 {
178 u32 supported;
179
180 if (hw->copper) {
181 supported = SUPPORTED_10baseT_Half
182 | SUPPORTED_10baseT_Full
183 | SUPPORTED_100baseT_Half
184 | SUPPORTED_100baseT_Full
185 | SUPPORTED_1000baseT_Half
186 | SUPPORTED_1000baseT_Full
187 | SUPPORTED_Autoneg| SUPPORTED_TP;
188
189 if (hw->chip_id == CHIP_ID_GENESIS)
190 supported &= ~(SUPPORTED_10baseT_Half
191 | SUPPORTED_10baseT_Full
192 | SUPPORTED_100baseT_Half
193 | SUPPORTED_100baseT_Full);
194
195 else if (hw->chip_id == CHIP_ID_YUKON)
196 supported &= ~SUPPORTED_1000baseT_Half;
197 } else
198 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
199 | SUPPORTED_Autoneg;
200
201 return supported;
202 }
203
204 static int skge_get_settings(struct net_device *dev,
205 struct ethtool_cmd *ecmd)
206 {
207 struct skge_port *skge = netdev_priv(dev);
208 struct skge_hw *hw = skge->hw;
209
210 ecmd->transceiver = XCVR_INTERNAL;
211 ecmd->supported = skge_supported_modes(hw);
212
213 if (hw->copper) {
214 ecmd->port = PORT_TP;
215 ecmd->phy_address = hw->phy_addr;
216 } else
217 ecmd->port = PORT_FIBRE;
218
219 ecmd->advertising = skge->advertising;
220 ecmd->autoneg = skge->autoneg;
221 ecmd->speed = skge->speed;
222 ecmd->duplex = skge->duplex;
223 return 0;
224 }
225
226 static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
227 {
228 struct skge_port *skge = netdev_priv(dev);
229 const struct skge_hw *hw = skge->hw;
230 u32 supported = skge_supported_modes(hw);
231
232 if (ecmd->autoneg == AUTONEG_ENABLE) {
233 ecmd->advertising = supported;
234 skge->duplex = -1;
235 skge->speed = -1;
236 } else {
237 u32 setting;
238
239 switch (ecmd->speed) {
240 case SPEED_1000:
241 if (ecmd->duplex == DUPLEX_FULL)
242 setting = SUPPORTED_1000baseT_Full;
243 else if (ecmd->duplex == DUPLEX_HALF)
244 setting = SUPPORTED_1000baseT_Half;
245 else
246 return -EINVAL;
247 break;
248 case SPEED_100:
249 if (ecmd->duplex == DUPLEX_FULL)
250 setting = SUPPORTED_100baseT_Full;
251 else if (ecmd->duplex == DUPLEX_HALF)
252 setting = SUPPORTED_100baseT_Half;
253 else
254 return -EINVAL;
255 break;
256
257 case SPEED_10:
258 if (ecmd->duplex == DUPLEX_FULL)
259 setting = SUPPORTED_10baseT_Full;
260 else if (ecmd->duplex == DUPLEX_HALF)
261 setting = SUPPORTED_10baseT_Half;
262 else
263 return -EINVAL;
264 break;
265 default:
266 return -EINVAL;
267 }
268
269 if ((setting & supported) == 0)
270 return -EINVAL;
271
272 skge->speed = ecmd->speed;
273 skge->duplex = ecmd->duplex;
274 }
275
276 skge->autoneg = ecmd->autoneg;
277 skge->advertising = ecmd->advertising;
278
279 if (netif_running(dev))
280 skge_phy_reset(skge);
281
282 return (0);
283 }
284
285 static void skge_get_drvinfo(struct net_device *dev,
286 struct ethtool_drvinfo *info)
287 {
288 struct skge_port *skge = netdev_priv(dev);
289
290 strcpy(info->driver, DRV_NAME);
291 strcpy(info->version, DRV_VERSION);
292 strcpy(info->fw_version, "N/A");
293 strcpy(info->bus_info, pci_name(skge->hw->pdev));
294 }
295
296 static const struct skge_stat {
297 char name[ETH_GSTRING_LEN];
298 u16 xmac_offset;
299 u16 gma_offset;
300 } skge_stats[] = {
301 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
302 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
303
304 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
305 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
306 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
307 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
308 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
309 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
310 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
311 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
312
313 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
314 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
315 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
316 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
317 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
318 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
319
320 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
321 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
322 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
323 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
324 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
325 };
326
327 static int skge_get_stats_count(struct net_device *dev)
328 {
329 return ARRAY_SIZE(skge_stats);
330 }
331
332 static void skge_get_ethtool_stats(struct net_device *dev,
333 struct ethtool_stats *stats, u64 *data)
334 {
335 struct skge_port *skge = netdev_priv(dev);
336
337 if (skge->hw->chip_id == CHIP_ID_GENESIS)
338 genesis_get_stats(skge, data);
339 else
340 yukon_get_stats(skge, data);
341 }
342
343 /* Use hardware MIB variables for critical path statistics and
344 * transmit feedback not reported at interrupt.
345 * Other errors are accounted for in interrupt handler.
346 */
347 static struct net_device_stats *skge_get_stats(struct net_device *dev)
348 {
349 struct skge_port *skge = netdev_priv(dev);
350 u64 data[ARRAY_SIZE(skge_stats)];
351
352 if (skge->hw->chip_id == CHIP_ID_GENESIS)
353 genesis_get_stats(skge, data);
354 else
355 yukon_get_stats(skge, data);
356
357 skge->net_stats.tx_bytes = data[0];
358 skge->net_stats.rx_bytes = data[1];
359 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
360 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
361 skge->net_stats.multicast = data[5] + data[7];
362 skge->net_stats.collisions = data[10];
363 skge->net_stats.tx_aborted_errors = data[12];
364
365 return &skge->net_stats;
366 }
367
368 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
369 {
370 int i;
371
372 switch (stringset) {
373 case ETH_SS_STATS:
374 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
375 memcpy(data + i * ETH_GSTRING_LEN,
376 skge_stats[i].name, ETH_GSTRING_LEN);
377 break;
378 }
379 }
380
381 static void skge_get_ring_param(struct net_device *dev,
382 struct ethtool_ringparam *p)
383 {
384 struct skge_port *skge = netdev_priv(dev);
385
386 p->rx_max_pending = MAX_RX_RING_SIZE;
387 p->tx_max_pending = MAX_TX_RING_SIZE;
388 p->rx_mini_max_pending = 0;
389 p->rx_jumbo_max_pending = 0;
390
391 p->rx_pending = skge->rx_ring.count;
392 p->tx_pending = skge->tx_ring.count;
393 p->rx_mini_pending = 0;
394 p->rx_jumbo_pending = 0;
395 }
396
397 static int skge_set_ring_param(struct net_device *dev,
398 struct ethtool_ringparam *p)
399 {
400 struct skge_port *skge = netdev_priv(dev);
401 int err;
402
403 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
404 p->tx_pending == 0 || p->tx_pending > MAX_TX_RING_SIZE)
405 return -EINVAL;
406
407 skge->rx_ring.count = p->rx_pending;
408 skge->tx_ring.count = p->tx_pending;
409
410 if (netif_running(dev)) {
411 skge_down(dev);
412 err = skge_up(dev);
413 if (err)
414 dev_close(dev);
415 }
416
417 return 0;
418 }
419
420 static u32 skge_get_msglevel(struct net_device *netdev)
421 {
422 struct skge_port *skge = netdev_priv(netdev);
423 return skge->msg_enable;
424 }
425
426 static void skge_set_msglevel(struct net_device *netdev, u32 value)
427 {
428 struct skge_port *skge = netdev_priv(netdev);
429 skge->msg_enable = value;
430 }
431
432 static int skge_nway_reset(struct net_device *dev)
433 {
434 struct skge_port *skge = netdev_priv(dev);
435
436 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
437 return -EINVAL;
438
439 skge_phy_reset(skge);
440 return 0;
441 }
442
443 static int skge_set_sg(struct net_device *dev, u32 data)
444 {
445 struct skge_port *skge = netdev_priv(dev);
446 struct skge_hw *hw = skge->hw;
447
448 if (hw->chip_id == CHIP_ID_GENESIS && data)
449 return -EOPNOTSUPP;
450 return ethtool_op_set_sg(dev, data);
451 }
452
453 static int skge_set_tx_csum(struct net_device *dev, u32 data)
454 {
455 struct skge_port *skge = netdev_priv(dev);
456 struct skge_hw *hw = skge->hw;
457
458 if (hw->chip_id == CHIP_ID_GENESIS && data)
459 return -EOPNOTSUPP;
460
461 return ethtool_op_set_tx_csum(dev, data);
462 }
463
464 static u32 skge_get_rx_csum(struct net_device *dev)
465 {
466 struct skge_port *skge = netdev_priv(dev);
467
468 return skge->rx_csum;
469 }
470
471 /* Only Yukon supports checksum offload. */
472 static int skge_set_rx_csum(struct net_device *dev, u32 data)
473 {
474 struct skge_port *skge = netdev_priv(dev);
475
476 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
477 return -EOPNOTSUPP;
478
479 skge->rx_csum = data;
480 return 0;
481 }
482
483 static void skge_get_pauseparam(struct net_device *dev,
484 struct ethtool_pauseparam *ecmd)
485 {
486 struct skge_port *skge = netdev_priv(dev);
487
488 ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
489 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
490 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
491 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
492
493 ecmd->autoneg = skge->autoneg;
494 }
495
496 static int skge_set_pauseparam(struct net_device *dev,
497 struct ethtool_pauseparam *ecmd)
498 {
499 struct skge_port *skge = netdev_priv(dev);
500
501 skge->autoneg = ecmd->autoneg;
502 if (ecmd->rx_pause && ecmd->tx_pause)
503 skge->flow_control = FLOW_MODE_SYMMETRIC;
504 else if (ecmd->rx_pause && !ecmd->tx_pause)
505 skge->flow_control = FLOW_MODE_REM_SEND;
506 else if (!ecmd->rx_pause && ecmd->tx_pause)
507 skge->flow_control = FLOW_MODE_LOC_SEND;
508 else
509 skge->flow_control = FLOW_MODE_NONE;
510
511 if (netif_running(dev))
512 skge_phy_reset(skge);
513 return 0;
514 }
515
516 /* Chip internal frequency for clock calculations */
517 static inline u32 hwkhz(const struct skge_hw *hw)
518 {
519 if (hw->chip_id == CHIP_ID_GENESIS)
520 return 53215; /* or: 53.125 MHz */
521 else
522 return 78215; /* or: 78.125 MHz */
523 }
524
525 /* Chip HZ to microseconds */
526 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
527 {
528 return (ticks * 1000) / hwkhz(hw);
529 }
530
531 /* Microseconds to chip HZ */
532 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
533 {
534 return hwkhz(hw) * usec / 1000;
535 }
536
537 static int skge_get_coalesce(struct net_device *dev,
538 struct ethtool_coalesce *ecmd)
539 {
540 struct skge_port *skge = netdev_priv(dev);
541 struct skge_hw *hw = skge->hw;
542 int port = skge->port;
543
544 ecmd->rx_coalesce_usecs = 0;
545 ecmd->tx_coalesce_usecs = 0;
546
547 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
548 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
549 u32 msk = skge_read32(hw, B2_IRQM_MSK);
550
551 if (msk & rxirqmask[port])
552 ecmd->rx_coalesce_usecs = delay;
553 if (msk & txirqmask[port])
554 ecmd->tx_coalesce_usecs = delay;
555 }
556
557 return 0;
558 }
559
560 /* Note: interrupt timer is per board, but can turn on/off per port */
561 static int skge_set_coalesce(struct net_device *dev,
562 struct ethtool_coalesce *ecmd)
563 {
564 struct skge_port *skge = netdev_priv(dev);
565 struct skge_hw *hw = skge->hw;
566 int port = skge->port;
567 u32 msk = skge_read32(hw, B2_IRQM_MSK);
568 u32 delay = 25;
569
570 if (ecmd->rx_coalesce_usecs == 0)
571 msk &= ~rxirqmask[port];
572 else if (ecmd->rx_coalesce_usecs < 25 ||
573 ecmd->rx_coalesce_usecs > 33333)
574 return -EINVAL;
575 else {
576 msk |= rxirqmask[port];
577 delay = ecmd->rx_coalesce_usecs;
578 }
579
580 if (ecmd->tx_coalesce_usecs == 0)
581 msk &= ~txirqmask[port];
582 else if (ecmd->tx_coalesce_usecs < 25 ||
583 ecmd->tx_coalesce_usecs > 33333)
584 return -EINVAL;
585 else {
586 msk |= txirqmask[port];
587 delay = min(delay, ecmd->rx_coalesce_usecs);
588 }
589
590 skge_write32(hw, B2_IRQM_MSK, msk);
591 if (msk == 0)
592 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
593 else {
594 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
595 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
596 }
597 return 0;
598 }
599
600 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
601 static void skge_led(struct skge_port *skge, enum led_mode mode)
602 {
603 struct skge_hw *hw = skge->hw;
604 int port = skge->port;
605
606 spin_lock_bh(&hw->phy_lock);
607 if (hw->chip_id == CHIP_ID_GENESIS) {
608 switch (mode) {
609 case LED_MODE_OFF:
610 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
611 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
612 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
613 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
614 break;
615
616 case LED_MODE_ON:
617 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
618 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
619
620 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
621 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
622
623 break;
624
625 case LED_MODE_TST:
626 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
627 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
628 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
629
630 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
631 break;
632 }
633 } else {
634 switch (mode) {
635 case LED_MODE_OFF:
636 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
637 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
638 PHY_M_LED_MO_DUP(MO_LED_OFF) |
639 PHY_M_LED_MO_10(MO_LED_OFF) |
640 PHY_M_LED_MO_100(MO_LED_OFF) |
641 PHY_M_LED_MO_1000(MO_LED_OFF) |
642 PHY_M_LED_MO_RX(MO_LED_OFF));
643 break;
644 case LED_MODE_ON:
645 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
646 PHY_M_LED_PULS_DUR(PULS_170MS) |
647 PHY_M_LED_BLINK_RT(BLINK_84MS) |
648 PHY_M_LEDC_TX_CTRL |
649 PHY_M_LEDC_DP_CTRL);
650
651 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
652 PHY_M_LED_MO_RX(MO_LED_OFF) |
653 (skge->speed == SPEED_100 ?
654 PHY_M_LED_MO_100(MO_LED_ON) : 0));
655 break;
656 case LED_MODE_TST:
657 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
658 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
659 PHY_M_LED_MO_DUP(MO_LED_ON) |
660 PHY_M_LED_MO_10(MO_LED_ON) |
661 PHY_M_LED_MO_100(MO_LED_ON) |
662 PHY_M_LED_MO_1000(MO_LED_ON) |
663 PHY_M_LED_MO_RX(MO_LED_ON));
664 }
665 }
666 spin_unlock_bh(&hw->phy_lock);
667 }
668
669 /* blink LED's for finding board */
670 static int skge_phys_id(struct net_device *dev, u32 data)
671 {
672 struct skge_port *skge = netdev_priv(dev);
673 unsigned long ms;
674 enum led_mode mode = LED_MODE_TST;
675
676 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
677 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
678 else
679 ms = data * 1000;
680
681 while (ms > 0) {
682 skge_led(skge, mode);
683 mode ^= LED_MODE_TST;
684
685 if (msleep_interruptible(BLINK_MS))
686 break;
687 ms -= BLINK_MS;
688 }
689
690 /* back to regular LED state */
691 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
692
693 return 0;
694 }
695
696 static struct ethtool_ops skge_ethtool_ops = {
697 .get_settings = skge_get_settings,
698 .set_settings = skge_set_settings,
699 .get_drvinfo = skge_get_drvinfo,
700 .get_regs_len = skge_get_regs_len,
701 .get_regs = skge_get_regs,
702 .get_wol = skge_get_wol,
703 .set_wol = skge_set_wol,
704 .get_msglevel = skge_get_msglevel,
705 .set_msglevel = skge_set_msglevel,
706 .nway_reset = skge_nway_reset,
707 .get_link = ethtool_op_get_link,
708 .get_ringparam = skge_get_ring_param,
709 .set_ringparam = skge_set_ring_param,
710 .get_pauseparam = skge_get_pauseparam,
711 .set_pauseparam = skge_set_pauseparam,
712 .get_coalesce = skge_get_coalesce,
713 .set_coalesce = skge_set_coalesce,
714 .get_sg = ethtool_op_get_sg,
715 .set_sg = skge_set_sg,
716 .get_tx_csum = ethtool_op_get_tx_csum,
717 .set_tx_csum = skge_set_tx_csum,
718 .get_rx_csum = skge_get_rx_csum,
719 .set_rx_csum = skge_set_rx_csum,
720 .get_strings = skge_get_strings,
721 .phys_id = skge_phys_id,
722 .get_stats_count = skge_get_stats_count,
723 .get_ethtool_stats = skge_get_ethtool_stats,
724 .get_perm_addr = ethtool_op_get_perm_addr,
725 };
726
727 /*
728 * Allocate ring elements and chain them together
729 * One-to-one association of board descriptors with ring elements
730 */
731 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u64 base)
732 {
733 struct skge_tx_desc *d;
734 struct skge_element *e;
735 int i;
736
737 ring->start = kmalloc(sizeof(*e)*ring->count, GFP_KERNEL);
738 if (!ring->start)
739 return -ENOMEM;
740
741 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
742 e->desc = d;
743 e->skb = NULL;
744 if (i == ring->count - 1) {
745 e->next = ring->start;
746 d->next_offset = base;
747 } else {
748 e->next = e + 1;
749 d->next_offset = base + (i+1) * sizeof(*d);
750 }
751 }
752 ring->to_use = ring->to_clean = ring->start;
753
754 return 0;
755 }
756
757 /* Allocate and setup a new buffer for receiving */
758 static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
759 struct sk_buff *skb, unsigned int bufsize)
760 {
761 struct skge_rx_desc *rd = e->desc;
762 u64 map;
763
764 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
765 PCI_DMA_FROMDEVICE);
766
767 rd->dma_lo = map;
768 rd->dma_hi = map >> 32;
769 e->skb = skb;
770 rd->csum1_start = ETH_HLEN;
771 rd->csum2_start = ETH_HLEN;
772 rd->csum1 = 0;
773 rd->csum2 = 0;
774
775 wmb();
776
777 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
778 pci_unmap_addr_set(e, mapaddr, map);
779 pci_unmap_len_set(e, maplen, bufsize);
780 }
781
782 /* Resume receiving using existing skb,
783 * Note: DMA address is not changed by chip.
784 * MTU not changed while receiver active.
785 */
786 static void skge_rx_reuse(struct skge_element *e, unsigned int size)
787 {
788 struct skge_rx_desc *rd = e->desc;
789
790 rd->csum2 = 0;
791 rd->csum2_start = ETH_HLEN;
792
793 wmb();
794
795 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
796 }
797
798
799 /* Free all buffers in receive ring, assumes receiver stopped */
800 static void skge_rx_clean(struct skge_port *skge)
801 {
802 struct skge_hw *hw = skge->hw;
803 struct skge_ring *ring = &skge->rx_ring;
804 struct skge_element *e;
805
806 e = ring->start;
807 do {
808 struct skge_rx_desc *rd = e->desc;
809 rd->control = 0;
810 if (e->skb) {
811 pci_unmap_single(hw->pdev,
812 pci_unmap_addr(e, mapaddr),
813 pci_unmap_len(e, maplen),
814 PCI_DMA_FROMDEVICE);
815 dev_kfree_skb(e->skb);
816 e->skb = NULL;
817 }
818 } while ((e = e->next) != ring->start);
819 }
820
821
822 /* Allocate buffers for receive ring
823 * For receive: to_clean is next received frame.
824 */
825 static int skge_rx_fill(struct skge_port *skge)
826 {
827 struct skge_ring *ring = &skge->rx_ring;
828 struct skge_element *e;
829
830 e = ring->start;
831 do {
832 struct sk_buff *skb;
833
834 skb = dev_alloc_skb(skge->rx_buf_size + NET_IP_ALIGN);
835 if (!skb)
836 return -ENOMEM;
837
838 skb_reserve(skb, NET_IP_ALIGN);
839 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
840 } while ( (e = e->next) != ring->start);
841
842 ring->to_clean = ring->start;
843 return 0;
844 }
845
846 static void skge_link_up(struct skge_port *skge)
847 {
848 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
849 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
850
851 netif_carrier_on(skge->netdev);
852 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
853 netif_wake_queue(skge->netdev);
854
855 if (netif_msg_link(skge))
856 printk(KERN_INFO PFX
857 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
858 skge->netdev->name, skge->speed,
859 skge->duplex == DUPLEX_FULL ? "full" : "half",
860 (skge->flow_control == FLOW_MODE_NONE) ? "none" :
861 (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
862 (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
863 (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
864 "unknown");
865 }
866
867 static void skge_link_down(struct skge_port *skge)
868 {
869 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
870 netif_carrier_off(skge->netdev);
871 netif_stop_queue(skge->netdev);
872
873 if (netif_msg_link(skge))
874 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
875 }
876
877 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
878 {
879 int i;
880
881 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
882 xm_read16(hw, port, XM_PHY_DATA);
883
884 /* Need to wait for external PHY */
885 for (i = 0; i < PHY_RETRIES; i++) {
886 udelay(1);
887 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
888 goto ready;
889 }
890
891 return -ETIMEDOUT;
892 ready:
893 *val = xm_read16(hw, port, XM_PHY_DATA);
894
895 return 0;
896 }
897
898 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
899 {
900 u16 v = 0;
901 if (__xm_phy_read(hw, port, reg, &v))
902 printk(KERN_WARNING PFX "%s: phy read timed out\n",
903 hw->dev[port]->name);
904 return v;
905 }
906
907 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
908 {
909 int i;
910
911 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
912 for (i = 0; i < PHY_RETRIES; i++) {
913 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
914 goto ready;
915 udelay(1);
916 }
917 return -EIO;
918
919 ready:
920 xm_write16(hw, port, XM_PHY_DATA, val);
921 return 0;
922 }
923
924 static void genesis_init(struct skge_hw *hw)
925 {
926 /* set blink source counter */
927 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
928 skge_write8(hw, B2_BSC_CTRL, BSC_START);
929
930 /* configure mac arbiter */
931 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
932
933 /* configure mac arbiter timeout values */
934 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
935 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
936 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
937 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
938
939 skge_write8(hw, B3_MA_RCINI_RX1, 0);
940 skge_write8(hw, B3_MA_RCINI_RX2, 0);
941 skge_write8(hw, B3_MA_RCINI_TX1, 0);
942 skge_write8(hw, B3_MA_RCINI_TX2, 0);
943
944 /* configure packet arbiter timeout */
945 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
946 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
947 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
948 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
949 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
950 }
951
952 static void genesis_reset(struct skge_hw *hw, int port)
953 {
954 const u8 zero[8] = { 0 };
955
956 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
957
958 /* reset the statistics module */
959 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
960 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
961 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
962 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
963 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
964
965 /* disable Broadcom PHY IRQ */
966 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
967
968 xm_outhash(hw, port, XM_HSM, zero);
969 }
970
971
972 /* Convert mode to MII values */
973 static const u16 phy_pause_map[] = {
974 [FLOW_MODE_NONE] = 0,
975 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
976 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
977 [FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
978 };
979
980
981 /* Check status of Broadcom phy link */
982 static void bcom_check_link(struct skge_hw *hw, int port)
983 {
984 struct net_device *dev = hw->dev[port];
985 struct skge_port *skge = netdev_priv(dev);
986 u16 status;
987
988 /* read twice because of latch */
989 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
990 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
991
992 if ((status & PHY_ST_LSYNC) == 0) {
993 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
994 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
995 xm_write16(hw, port, XM_MMU_CMD, cmd);
996 /* dummy read to ensure writing */
997 (void) xm_read16(hw, port, XM_MMU_CMD);
998
999 if (netif_carrier_ok(dev))
1000 skge_link_down(skge);
1001 } else {
1002 if (skge->autoneg == AUTONEG_ENABLE &&
1003 (status & PHY_ST_AN_OVER)) {
1004 u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);
1005 u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1006
1007 if (lpa & PHY_B_AN_RF) {
1008 printk(KERN_NOTICE PFX "%s: remote fault\n",
1009 dev->name);
1010 return;
1011 }
1012
1013 /* Check Duplex mismatch */
1014 switch (aux & PHY_B_AS_AN_RES_MSK) {
1015 case PHY_B_RES_1000FD:
1016 skge->duplex = DUPLEX_FULL;
1017 break;
1018 case PHY_B_RES_1000HD:
1019 skge->duplex = DUPLEX_HALF;
1020 break;
1021 default:
1022 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1023 dev->name);
1024 return;
1025 }
1026
1027
1028 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1029 switch (aux & PHY_B_AS_PAUSE_MSK) {
1030 case PHY_B_AS_PAUSE_MSK:
1031 skge->flow_control = FLOW_MODE_SYMMETRIC;
1032 break;
1033 case PHY_B_AS_PRR:
1034 skge->flow_control = FLOW_MODE_REM_SEND;
1035 break;
1036 case PHY_B_AS_PRT:
1037 skge->flow_control = FLOW_MODE_LOC_SEND;
1038 break;
1039 default:
1040 skge->flow_control = FLOW_MODE_NONE;
1041 }
1042
1043 skge->speed = SPEED_1000;
1044 }
1045
1046 if (!netif_carrier_ok(dev))
1047 genesis_link_up(skge);
1048 }
1049 }
1050
1051 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1052 * Phy on for 100 or 10Mbit operation
1053 */
1054 static void bcom_phy_init(struct skge_port *skge, int jumbo)
1055 {
1056 struct skge_hw *hw = skge->hw;
1057 int port = skge->port;
1058 int i;
1059 u16 id1, r, ext, ctl;
1060
1061 /* magic workaround patterns for Broadcom */
1062 static const struct {
1063 u16 reg;
1064 u16 val;
1065 } A1hack[] = {
1066 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1067 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1068 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1069 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1070 }, C0hack[] = {
1071 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1072 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1073 };
1074
1075 /* read Id from external PHY (all have the same address) */
1076 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1077
1078 /* Optimize MDIO transfer by suppressing preamble. */
1079 r = xm_read16(hw, port, XM_MMU_CMD);
1080 r |= XM_MMU_NO_PRE;
1081 xm_write16(hw, port, XM_MMU_CMD,r);
1082
1083 switch (id1) {
1084 case PHY_BCOM_ID1_C0:
1085 /*
1086 * Workaround BCOM Errata for the C0 type.
1087 * Write magic patterns to reserved registers.
1088 */
1089 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1090 xm_phy_write(hw, port,
1091 C0hack[i].reg, C0hack[i].val);
1092
1093 break;
1094 case PHY_BCOM_ID1_A1:
1095 /*
1096 * Workaround BCOM Errata for the A1 type.
1097 * Write magic patterns to reserved registers.
1098 */
1099 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1100 xm_phy_write(hw, port,
1101 A1hack[i].reg, A1hack[i].val);
1102 break;
1103 }
1104
1105 /*
1106 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1107 * Disable Power Management after reset.
1108 */
1109 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1110 r |= PHY_B_AC_DIS_PM;
1111 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1112
1113 /* Dummy read */
1114 xm_read16(hw, port, XM_ISRC);
1115
1116 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1117 ctl = PHY_CT_SP1000; /* always 1000mbit */
1118
1119 if (skge->autoneg == AUTONEG_ENABLE) {
1120 /*
1121 * Workaround BCOM Errata #1 for the C5 type.
1122 * 1000Base-T Link Acquisition Failure in Slave Mode
1123 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1124 */
1125 u16 adv = PHY_B_1000C_RD;
1126 if (skge->advertising & ADVERTISED_1000baseT_Half)
1127 adv |= PHY_B_1000C_AHD;
1128 if (skge->advertising & ADVERTISED_1000baseT_Full)
1129 adv |= PHY_B_1000C_AFD;
1130 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1131
1132 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1133 } else {
1134 if (skge->duplex == DUPLEX_FULL)
1135 ctl |= PHY_CT_DUP_MD;
1136 /* Force to slave */
1137 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1138 }
1139
1140 /* Set autonegotiation pause parameters */
1141 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1142 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1143
1144 /* Handle Jumbo frames */
1145 if (jumbo) {
1146 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1147 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1148
1149 ext |= PHY_B_PEC_HIGH_LA;
1150
1151 }
1152
1153 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1154 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1155
1156 /* Use link status change interrupt */
1157 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1158
1159 bcom_check_link(hw, port);
1160 }
1161
1162 static void genesis_mac_init(struct skge_hw *hw, int port)
1163 {
1164 struct net_device *dev = hw->dev[port];
1165 struct skge_port *skge = netdev_priv(dev);
1166 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1167 int i;
1168 u32 r;
1169 const u8 zero[6] = { 0 };
1170
1171 /* Clear MIB counters */
1172 xm_write16(hw, port, XM_STAT_CMD,
1173 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1174 /* Clear two times according to Errata #3 */
1175 xm_write16(hw, port, XM_STAT_CMD,
1176 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1177
1178 /* Unreset the XMAC. */
1179 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1180
1181 /*
1182 * Perform additional initialization for external PHYs,
1183 * namely for the 1000baseTX cards that use the XMAC's
1184 * GMII mode.
1185 */
1186 /* Take external Phy out of reset */
1187 r = skge_read32(hw, B2_GP_IO);
1188 if (port == 0)
1189 r |= GP_DIR_0|GP_IO_0;
1190 else
1191 r |= GP_DIR_2|GP_IO_2;
1192
1193 skge_write32(hw, B2_GP_IO, r);
1194 skge_read32(hw, B2_GP_IO);
1195
1196 /* Enable GMII interface */
1197 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1198
1199 bcom_phy_init(skge, jumbo);
1200
1201 /* Set Station Address */
1202 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1203
1204 /* We don't use match addresses so clear */
1205 for (i = 1; i < 16; i++)
1206 xm_outaddr(hw, port, XM_EXM(i), zero);
1207
1208 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1209 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1210
1211 /* We don't need the FCS appended to the packet. */
1212 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1213 if (jumbo)
1214 r |= XM_RX_BIG_PK_OK;
1215
1216 if (skge->duplex == DUPLEX_HALF) {
1217 /*
1218 * If in manual half duplex mode the other side might be in
1219 * full duplex mode, so ignore if a carrier extension is not seen
1220 * on frames received
1221 */
1222 r |= XM_RX_DIS_CEXT;
1223 }
1224 xm_write16(hw, port, XM_RX_CMD, r);
1225
1226
1227 /* We want short frames padded to 60 bytes. */
1228 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1229
1230 /*
1231 * Bump up the transmit threshold. This helps hold off transmit
1232 * underruns when we're blasting traffic from both ports at once.
1233 */
1234 xm_write16(hw, port, XM_TX_THR, 512);
1235
1236 /*
1237 * Enable the reception of all error frames. This is is
1238 * a necessary evil due to the design of the XMAC. The
1239 * XMAC's receive FIFO is only 8K in size, however jumbo
1240 * frames can be up to 9000 bytes in length. When bad
1241 * frame filtering is enabled, the XMAC's RX FIFO operates
1242 * in 'store and forward' mode. For this to work, the
1243 * entire frame has to fit into the FIFO, but that means
1244 * that jumbo frames larger than 8192 bytes will be
1245 * truncated. Disabling all bad frame filtering causes
1246 * the RX FIFO to operate in streaming mode, in which
1247 * case the XMAC will start transferring frames out of the
1248 * RX FIFO as soon as the FIFO threshold is reached.
1249 */
1250 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1251
1252
1253 /*
1254 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1255 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1256 * and 'Octets Rx OK Hi Cnt Ov'.
1257 */
1258 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1259
1260 /*
1261 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1262 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1263 * and 'Octets Tx OK Hi Cnt Ov'.
1264 */
1265 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1266
1267 /* Configure MAC arbiter */
1268 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1269
1270 /* configure timeout values */
1271 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1272 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1273 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1274 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1275
1276 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1277 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1278 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1279 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1280
1281 /* Configure Rx MAC FIFO */
1282 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1283 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1284 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1285
1286 /* Configure Tx MAC FIFO */
1287 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1288 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1289 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1290
1291 if (jumbo) {
1292 /* Enable frame flushing if jumbo frames used */
1293 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
1294 } else {
1295 /* enable timeout timers if normal frames */
1296 skge_write16(hw, B3_PA_CTRL,
1297 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1298 }
1299 }
1300
1301 static void genesis_stop(struct skge_port *skge)
1302 {
1303 struct skge_hw *hw = skge->hw;
1304 int port = skge->port;
1305 u32 reg;
1306
1307 genesis_reset(hw, port);
1308
1309 /* Clear Tx packet arbiter timeout IRQ */
1310 skge_write16(hw, B3_PA_CTRL,
1311 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1312
1313 /*
1314 * If the transfer sticks at the MAC the STOP command will not
1315 * terminate if we don't flush the XMAC's transmit FIFO !
1316 */
1317 xm_write32(hw, port, XM_MODE,
1318 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
1319
1320
1321 /* Reset the MAC */
1322 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1323
1324 /* For external PHYs there must be special handling */
1325 reg = skge_read32(hw, B2_GP_IO);
1326 if (port == 0) {
1327 reg |= GP_DIR_0;
1328 reg &= ~GP_IO_0;
1329 } else {
1330 reg |= GP_DIR_2;
1331 reg &= ~GP_IO_2;
1332 }
1333 skge_write32(hw, B2_GP_IO, reg);
1334 skge_read32(hw, B2_GP_IO);
1335
1336 xm_write16(hw, port, XM_MMU_CMD,
1337 xm_read16(hw, port, XM_MMU_CMD)
1338 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1339
1340 xm_read16(hw, port, XM_MMU_CMD);
1341 }
1342
1343
1344 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1345 {
1346 struct skge_hw *hw = skge->hw;
1347 int port = skge->port;
1348 int i;
1349 unsigned long timeout = jiffies + HZ;
1350
1351 xm_write16(hw, port,
1352 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1353
1354 /* wait for update to complete */
1355 while (xm_read16(hw, port, XM_STAT_CMD)
1356 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1357 if (time_after(jiffies, timeout))
1358 break;
1359 udelay(10);
1360 }
1361
1362 /* special case for 64 bit octet counter */
1363 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1364 | xm_read32(hw, port, XM_TXO_OK_LO);
1365 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1366 | xm_read32(hw, port, XM_RXO_OK_LO);
1367
1368 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1369 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1370 }
1371
1372 static void genesis_mac_intr(struct skge_hw *hw, int port)
1373 {
1374 struct skge_port *skge = netdev_priv(hw->dev[port]);
1375 u16 status = xm_read16(hw, port, XM_ISRC);
1376
1377 if (netif_msg_intr(skge))
1378 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1379 skge->netdev->name, status);
1380
1381 if (status & XM_IS_TXF_UR) {
1382 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1383 ++skge->net_stats.tx_fifo_errors;
1384 }
1385 if (status & XM_IS_RXF_OV) {
1386 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
1387 ++skge->net_stats.rx_fifo_errors;
1388 }
1389 }
1390
1391 static void genesis_link_up(struct skge_port *skge)
1392 {
1393 struct skge_hw *hw = skge->hw;
1394 int port = skge->port;
1395 u16 cmd;
1396 u32 mode, msk;
1397
1398 cmd = xm_read16(hw, port, XM_MMU_CMD);
1399
1400 /*
1401 * enabling pause frame reception is required for 1000BT
1402 * because the XMAC is not reset if the link is going down
1403 */
1404 if (skge->flow_control == FLOW_MODE_NONE ||
1405 skge->flow_control == FLOW_MODE_LOC_SEND)
1406 /* Disable Pause Frame Reception */
1407 cmd |= XM_MMU_IGN_PF;
1408 else
1409 /* Enable Pause Frame Reception */
1410 cmd &= ~XM_MMU_IGN_PF;
1411
1412 xm_write16(hw, port, XM_MMU_CMD, cmd);
1413
1414 mode = xm_read32(hw, port, XM_MODE);
1415 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1416 skge->flow_control == FLOW_MODE_LOC_SEND) {
1417 /*
1418 * Configure Pause Frame Generation
1419 * Use internal and external Pause Frame Generation.
1420 * Sending pause frames is edge triggered.
1421 * Send a Pause frame with the maximum pause time if
1422 * internal oder external FIFO full condition occurs.
1423 * Send a zero pause time frame to re-start transmission.
1424 */
1425 /* XM_PAUSE_DA = '010000C28001' (default) */
1426 /* XM_MAC_PTIME = 0xffff (maximum) */
1427 /* remember this value is defined in big endian (!) */
1428 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1429
1430 mode |= XM_PAUSE_MODE;
1431 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1432 } else {
1433 /*
1434 * disable pause frame generation is required for 1000BT
1435 * because the XMAC is not reset if the link is going down
1436 */
1437 /* Disable Pause Mode in Mode Register */
1438 mode &= ~XM_PAUSE_MODE;
1439
1440 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1441 }
1442
1443 xm_write32(hw, port, XM_MODE, mode);
1444
1445 msk = XM_DEF_MSK;
1446 /* disable GP0 interrupt bit for external Phy */
1447 msk |= XM_IS_INP_ASS;
1448
1449 xm_write16(hw, port, XM_IMSK, msk);
1450 xm_read16(hw, port, XM_ISRC);
1451
1452 /* get MMU Command Reg. */
1453 cmd = xm_read16(hw, port, XM_MMU_CMD);
1454 if (skge->duplex == DUPLEX_FULL)
1455 cmd |= XM_MMU_GMII_FD;
1456
1457 /*
1458 * Workaround BCOM Errata (#10523) for all BCom Phys
1459 * Enable Power Management after link up
1460 */
1461 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1462 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1463 & ~PHY_B_AC_DIS_PM);
1464 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1465
1466 /* enable Rx/Tx */
1467 xm_write16(hw, port, XM_MMU_CMD,
1468 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1469 skge_link_up(skge);
1470 }
1471
1472
1473 static inline void bcom_phy_intr(struct skge_port *skge)
1474 {
1475 struct skge_hw *hw = skge->hw;
1476 int port = skge->port;
1477 u16 isrc;
1478
1479 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1480 if (netif_msg_intr(skge))
1481 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1482 skge->netdev->name, isrc);
1483
1484 if (isrc & PHY_B_IS_PSE)
1485 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1486 hw->dev[port]->name);
1487
1488 /* Workaround BCom Errata:
1489 * enable and disable loopback mode if "NO HCD" occurs.
1490 */
1491 if (isrc & PHY_B_IS_NO_HDCL) {
1492 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1493 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1494 ctrl | PHY_CT_LOOP);
1495 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1496 ctrl & ~PHY_CT_LOOP);
1497 }
1498
1499 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1500 bcom_check_link(hw, port);
1501
1502 }
1503
1504 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1505 {
1506 int i;
1507
1508 gma_write16(hw, port, GM_SMI_DATA, val);
1509 gma_write16(hw, port, GM_SMI_CTRL,
1510 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1511 for (i = 0; i < PHY_RETRIES; i++) {
1512 udelay(1);
1513
1514 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1515 return 0;
1516 }
1517
1518 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1519 hw->dev[port]->name);
1520 return -EIO;
1521 }
1522
1523 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1524 {
1525 int i;
1526
1527 gma_write16(hw, port, GM_SMI_CTRL,
1528 GM_SMI_CT_PHY_AD(hw->phy_addr)
1529 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1530
1531 for (i = 0; i < PHY_RETRIES; i++) {
1532 udelay(1);
1533 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1534 goto ready;
1535 }
1536
1537 return -ETIMEDOUT;
1538 ready:
1539 *val = gma_read16(hw, port, GM_SMI_DATA);
1540 return 0;
1541 }
1542
1543 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1544 {
1545 u16 v = 0;
1546 if (__gm_phy_read(hw, port, reg, &v))
1547 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1548 hw->dev[port]->name);
1549 return v;
1550 }
1551
1552 /* Marvell Phy Initialization */
1553 static void yukon_init(struct skge_hw *hw, int port)
1554 {
1555 struct skge_port *skge = netdev_priv(hw->dev[port]);
1556 u16 ctrl, ct1000, adv;
1557
1558 if (skge->autoneg == AUTONEG_ENABLE) {
1559 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1560
1561 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1562 PHY_M_EC_MAC_S_MSK);
1563 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1564
1565 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1566
1567 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1568 }
1569
1570 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1571 if (skge->autoneg == AUTONEG_DISABLE)
1572 ctrl &= ~PHY_CT_ANE;
1573
1574 ctrl |= PHY_CT_RESET;
1575 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1576
1577 ctrl = 0;
1578 ct1000 = 0;
1579 adv = PHY_AN_CSMA;
1580
1581 if (skge->autoneg == AUTONEG_ENABLE) {
1582 if (hw->copper) {
1583 if (skge->advertising & ADVERTISED_1000baseT_Full)
1584 ct1000 |= PHY_M_1000C_AFD;
1585 if (skge->advertising & ADVERTISED_1000baseT_Half)
1586 ct1000 |= PHY_M_1000C_AHD;
1587 if (skge->advertising & ADVERTISED_100baseT_Full)
1588 adv |= PHY_M_AN_100_FD;
1589 if (skge->advertising & ADVERTISED_100baseT_Half)
1590 adv |= PHY_M_AN_100_HD;
1591 if (skge->advertising & ADVERTISED_10baseT_Full)
1592 adv |= PHY_M_AN_10_FD;
1593 if (skge->advertising & ADVERTISED_10baseT_Half)
1594 adv |= PHY_M_AN_10_HD;
1595 } else /* special defines for FIBER (88E1011S only) */
1596 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
1597
1598 /* Set Flow-control capabilities */
1599 adv |= phy_pause_map[skge->flow_control];
1600
1601 /* Restart Auto-negotiation */
1602 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1603 } else {
1604 /* forced speed/duplex settings */
1605 ct1000 = PHY_M_1000C_MSE;
1606
1607 if (skge->duplex == DUPLEX_FULL)
1608 ctrl |= PHY_CT_DUP_MD;
1609
1610 switch (skge->speed) {
1611 case SPEED_1000:
1612 ctrl |= PHY_CT_SP1000;
1613 break;
1614 case SPEED_100:
1615 ctrl |= PHY_CT_SP100;
1616 break;
1617 }
1618
1619 ctrl |= PHY_CT_RESET;
1620 }
1621
1622 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
1623
1624 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1625 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1626
1627 /* Enable phy interrupt on autonegotiation complete (or link up) */
1628 if (skge->autoneg == AUTONEG_ENABLE)
1629 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
1630 else
1631 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1632 }
1633
1634 static void yukon_reset(struct skge_hw *hw, int port)
1635 {
1636 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1637 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1638 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1639 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1640 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
1641
1642 gma_write16(hw, port, GM_RX_CTRL,
1643 gma_read16(hw, port, GM_RX_CTRL)
1644 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1645 }
1646
1647 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
1648 static int is_yukon_lite_a0(struct skge_hw *hw)
1649 {
1650 u32 reg;
1651 int ret;
1652
1653 if (hw->chip_id != CHIP_ID_YUKON)
1654 return 0;
1655
1656 reg = skge_read32(hw, B2_FAR);
1657 skge_write8(hw, B2_FAR + 3, 0xff);
1658 ret = (skge_read8(hw, B2_FAR + 3) != 0);
1659 skge_write32(hw, B2_FAR, reg);
1660 return ret;
1661 }
1662
1663 static void yukon_mac_init(struct skge_hw *hw, int port)
1664 {
1665 struct skge_port *skge = netdev_priv(hw->dev[port]);
1666 int i;
1667 u32 reg;
1668 const u8 *addr = hw->dev[port]->dev_addr;
1669
1670 /* WA code for COMA mode -- set PHY reset */
1671 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1672 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1673 reg = skge_read32(hw, B2_GP_IO);
1674 reg |= GP_DIR_9 | GP_IO_9;
1675 skge_write32(hw, B2_GP_IO, reg);
1676 }
1677
1678 /* hard reset */
1679 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1680 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1681
1682 /* WA code for COMA mode -- clear PHY reset */
1683 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1684 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1685 reg = skge_read32(hw, B2_GP_IO);
1686 reg |= GP_DIR_9;
1687 reg &= ~GP_IO_9;
1688 skge_write32(hw, B2_GP_IO, reg);
1689 }
1690
1691 /* Set hardware config mode */
1692 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1693 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
1694 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
1695
1696 /* Clear GMC reset */
1697 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1698 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1699 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
1700
1701 if (skge->autoneg == AUTONEG_DISABLE) {
1702 reg = GM_GPCR_AU_ALL_DIS;
1703 gma_write16(hw, port, GM_GP_CTRL,
1704 gma_read16(hw, port, GM_GP_CTRL) | reg);
1705
1706 switch (skge->speed) {
1707 case SPEED_1000:
1708 reg &= ~GM_GPCR_SPEED_100;
1709 reg |= GM_GPCR_SPEED_1000;
1710 break;
1711 case SPEED_100:
1712 reg &= ~GM_GPCR_SPEED_1000;
1713 reg |= GM_GPCR_SPEED_100;
1714 break;
1715 case SPEED_10:
1716 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1717 break;
1718 }
1719
1720 if (skge->duplex == DUPLEX_FULL)
1721 reg |= GM_GPCR_DUP_FULL;
1722 } else
1723 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
1724
1725 switch (skge->flow_control) {
1726 case FLOW_MODE_NONE:
1727 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1728 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1729 break;
1730 case FLOW_MODE_LOC_SEND:
1731 /* disable Rx flow-control */
1732 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1733 }
1734
1735 gma_write16(hw, port, GM_GP_CTRL, reg);
1736 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
1737
1738 yukon_init(hw, port);
1739
1740 /* MIB clear */
1741 reg = gma_read16(hw, port, GM_PHY_ADDR);
1742 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
1743
1744 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
1745 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1746 gma_write16(hw, port, GM_PHY_ADDR, reg);
1747
1748 /* transmit control */
1749 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
1750
1751 /* receive control reg: unicast + multicast + no FCS */
1752 gma_write16(hw, port, GM_RX_CTRL,
1753 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1754
1755 /* transmit flow control */
1756 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
1757
1758 /* transmit parameter */
1759 gma_write16(hw, port, GM_TX_PARAM,
1760 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1761 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1762 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1763
1764 /* serial mode register */
1765 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1766 if (hw->dev[port]->mtu > 1500)
1767 reg |= GM_SMOD_JUMBO_ENA;
1768
1769 gma_write16(hw, port, GM_SERIAL_MODE, reg);
1770
1771 /* physical address: used for pause frames */
1772 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
1773 /* virtual address for data */
1774 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
1775
1776 /* enable interrupt mask for counter overflows */
1777 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1778 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1779 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
1780
1781 /* Initialize Mac Fifo */
1782
1783 /* Configure Rx MAC FIFO */
1784 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
1785 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
1786
1787 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
1788 if (is_yukon_lite_a0(hw))
1789 reg &= ~GMF_RX_F_FL_ON;
1790
1791 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1792 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
1793 /*
1794 * because Pause Packet Truncation in GMAC is not working
1795 * we have to increase the Flush Threshold to 64 bytes
1796 * in order to flush pause packets in Rx FIFO on Yukon-1
1797 */
1798 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
1799
1800 /* Configure Tx MAC FIFO */
1801 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1802 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1803 }
1804
1805 /* Go into power down mode */
1806 static void yukon_suspend(struct skge_hw *hw, int port)
1807 {
1808 u16 ctrl;
1809
1810 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
1811 ctrl |= PHY_M_PC_POL_R_DIS;
1812 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
1813
1814 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1815 ctrl |= PHY_CT_RESET;
1816 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1817
1818 /* switch IEEE compatible power down mode on */
1819 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1820 ctrl |= PHY_CT_PDOWN;
1821 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1822 }
1823
1824 static void yukon_stop(struct skge_port *skge)
1825 {
1826 struct skge_hw *hw = skge->hw;
1827 int port = skge->port;
1828
1829 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1830 yukon_reset(hw, port);
1831
1832 gma_write16(hw, port, GM_GP_CTRL,
1833 gma_read16(hw, port, GM_GP_CTRL)
1834 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
1835 gma_read16(hw, port, GM_GP_CTRL);
1836
1837 yukon_suspend(hw, port);
1838
1839 /* set GPHY Control reset */
1840 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1841 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1842 }
1843
1844 static void yukon_get_stats(struct skge_port *skge, u64 *data)
1845 {
1846 struct skge_hw *hw = skge->hw;
1847 int port = skge->port;
1848 int i;
1849
1850 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
1851 | gma_read32(hw, port, GM_TXO_OK_LO);
1852 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
1853 | gma_read32(hw, port, GM_RXO_OK_LO);
1854
1855 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1856 data[i] = gma_read32(hw, port,
1857 skge_stats[i].gma_offset);
1858 }
1859
1860 static void yukon_mac_intr(struct skge_hw *hw, int port)
1861 {
1862 struct net_device *dev = hw->dev[port];
1863 struct skge_port *skge = netdev_priv(dev);
1864 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1865
1866 if (netif_msg_intr(skge))
1867 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1868 dev->name, status);
1869
1870 if (status & GM_IS_RX_FF_OR) {
1871 ++skge->net_stats.rx_fifo_errors;
1872 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
1873 }
1874
1875 if (status & GM_IS_TX_FF_UR) {
1876 ++skge->net_stats.tx_fifo_errors;
1877 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
1878 }
1879
1880 }
1881
1882 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
1883 {
1884 switch (aux & PHY_M_PS_SPEED_MSK) {
1885 case PHY_M_PS_SPEED_1000:
1886 return SPEED_1000;
1887 case PHY_M_PS_SPEED_100:
1888 return SPEED_100;
1889 default:
1890 return SPEED_10;
1891 }
1892 }
1893
1894 static void yukon_link_up(struct skge_port *skge)
1895 {
1896 struct skge_hw *hw = skge->hw;
1897 int port = skge->port;
1898 u16 reg;
1899
1900 /* Enable Transmit FIFO Underrun */
1901 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1902
1903 reg = gma_read16(hw, port, GM_GP_CTRL);
1904 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
1905 reg |= GM_GPCR_DUP_FULL;
1906
1907 /* enable Rx/Tx */
1908 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1909 gma_write16(hw, port, GM_GP_CTRL, reg);
1910
1911 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1912 skge_link_up(skge);
1913 }
1914
1915 static void yukon_link_down(struct skge_port *skge)
1916 {
1917 struct skge_hw *hw = skge->hw;
1918 int port = skge->port;
1919 u16 ctrl;
1920
1921 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1922
1923 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1924 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1925 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1926
1927 if (skge->flow_control == FLOW_MODE_REM_SEND) {
1928 /* restore Asymmetric Pause bit */
1929 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1930 gm_phy_read(hw, port,
1931 PHY_MARV_AUNE_ADV)
1932 | PHY_M_AN_ASP);
1933
1934 }
1935
1936 yukon_reset(hw, port);
1937 skge_link_down(skge);
1938
1939 yukon_init(hw, port);
1940 }
1941
1942 static void yukon_phy_intr(struct skge_port *skge)
1943 {
1944 struct skge_hw *hw = skge->hw;
1945 int port = skge->port;
1946 const char *reason = NULL;
1947 u16 istatus, phystat;
1948
1949 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1950 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1951
1952 if (netif_msg_intr(skge))
1953 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
1954 skge->netdev->name, istatus, phystat);
1955
1956 if (istatus & PHY_M_IS_AN_COMPL) {
1957 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
1958 & PHY_M_AN_RF) {
1959 reason = "remote fault";
1960 goto failed;
1961 }
1962
1963 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1964 reason = "master/slave fault";
1965 goto failed;
1966 }
1967
1968 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
1969 reason = "speed/duplex";
1970 goto failed;
1971 }
1972
1973 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
1974 ? DUPLEX_FULL : DUPLEX_HALF;
1975 skge->speed = yukon_speed(hw, phystat);
1976
1977 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1978 switch (phystat & PHY_M_PS_PAUSE_MSK) {
1979 case PHY_M_PS_PAUSE_MSK:
1980 skge->flow_control = FLOW_MODE_SYMMETRIC;
1981 break;
1982 case PHY_M_PS_RX_P_EN:
1983 skge->flow_control = FLOW_MODE_REM_SEND;
1984 break;
1985 case PHY_M_PS_TX_P_EN:
1986 skge->flow_control = FLOW_MODE_LOC_SEND;
1987 break;
1988 default:
1989 skge->flow_control = FLOW_MODE_NONE;
1990 }
1991
1992 if (skge->flow_control == FLOW_MODE_NONE ||
1993 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
1994 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1995 else
1996 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1997 yukon_link_up(skge);
1998 return;
1999 }
2000
2001 if (istatus & PHY_M_IS_LSP_CHANGE)
2002 skge->speed = yukon_speed(hw, phystat);
2003
2004 if (istatus & PHY_M_IS_DUP_CHANGE)
2005 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2006 if (istatus & PHY_M_IS_LST_CHANGE) {
2007 if (phystat & PHY_M_PS_LINK_UP)
2008 yukon_link_up(skge);
2009 else
2010 yukon_link_down(skge);
2011 }
2012 return;
2013 failed:
2014 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2015 skge->netdev->name, reason);
2016
2017 /* XXX restart autonegotiation? */
2018 }
2019
2020 static void skge_phy_reset(struct skge_port *skge)
2021 {
2022 struct skge_hw *hw = skge->hw;
2023 int port = skge->port;
2024
2025 netif_stop_queue(skge->netdev);
2026 netif_carrier_off(skge->netdev);
2027
2028 spin_lock_bh(&hw->phy_lock);
2029 if (hw->chip_id == CHIP_ID_GENESIS) {
2030 genesis_reset(hw, port);
2031 genesis_mac_init(hw, port);
2032 } else {
2033 yukon_reset(hw, port);
2034 yukon_init(hw, port);
2035 }
2036 spin_unlock_bh(&hw->phy_lock);
2037 }
2038
2039 /* Basic MII support */
2040 static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2041 {
2042 struct mii_ioctl_data *data = if_mii(ifr);
2043 struct skge_port *skge = netdev_priv(dev);
2044 struct skge_hw *hw = skge->hw;
2045 int err = -EOPNOTSUPP;
2046
2047 if (!netif_running(dev))
2048 return -ENODEV; /* Phy still in reset */
2049
2050 switch(cmd) {
2051 case SIOCGMIIPHY:
2052 data->phy_id = hw->phy_addr;
2053
2054 /* fallthru */
2055 case SIOCGMIIREG: {
2056 u16 val = 0;
2057 spin_lock_bh(&hw->phy_lock);
2058 if (hw->chip_id == CHIP_ID_GENESIS)
2059 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2060 else
2061 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2062 spin_unlock_bh(&hw->phy_lock);
2063 data->val_out = val;
2064 break;
2065 }
2066
2067 case SIOCSMIIREG:
2068 if (!capable(CAP_NET_ADMIN))
2069 return -EPERM;
2070
2071 spin_lock_bh(&hw->phy_lock);
2072 if (hw->chip_id == CHIP_ID_GENESIS)
2073 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2074 data->val_in);
2075 else
2076 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2077 data->val_in);
2078 spin_unlock_bh(&hw->phy_lock);
2079 break;
2080 }
2081 return err;
2082 }
2083
2084 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2085 {
2086 u32 end;
2087
2088 start /= 8;
2089 len /= 8;
2090 end = start + len - 1;
2091
2092 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2093 skge_write32(hw, RB_ADDR(q, RB_START), start);
2094 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2095 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2096 skge_write32(hw, RB_ADDR(q, RB_END), end);
2097
2098 if (q == Q_R1 || q == Q_R2) {
2099 /* Set thresholds on receive queue's */
2100 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2101 start + (2*len)/3);
2102 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2103 start + (len/3));
2104 } else {
2105 /* Enable store & forward on Tx queue's because
2106 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2107 */
2108 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2109 }
2110
2111 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2112 }
2113
2114 /* Setup Bus Memory Interface */
2115 static void skge_qset(struct skge_port *skge, u16 q,
2116 const struct skge_element *e)
2117 {
2118 struct skge_hw *hw = skge->hw;
2119 u32 watermark = 0x600;
2120 u64 base = skge->dma + (e->desc - skge->mem);
2121
2122 /* optimization to reduce window on 32bit/33mhz */
2123 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2124 watermark /= 2;
2125
2126 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2127 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2128 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2129 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2130 }
2131
2132 static int skge_up(struct net_device *dev)
2133 {
2134 struct skge_port *skge = netdev_priv(dev);
2135 struct skge_hw *hw = skge->hw;
2136 int port = skge->port;
2137 u32 chunk, ram_addr;
2138 size_t rx_size, tx_size;
2139 int err;
2140
2141 if (netif_msg_ifup(skge))
2142 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2143
2144 if (dev->mtu > RX_BUF_SIZE)
2145 skge->rx_buf_size = dev->mtu + ETH_HLEN + NET_IP_ALIGN;
2146 else
2147 skge->rx_buf_size = RX_BUF_SIZE;
2148
2149
2150 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2151 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2152 skge->mem_size = tx_size + rx_size;
2153 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2154 if (!skge->mem)
2155 return -ENOMEM;
2156
2157 memset(skge->mem, 0, skge->mem_size);
2158
2159 if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma)))
2160 goto free_pci_mem;
2161
2162 err = skge_rx_fill(skge);
2163 if (err)
2164 goto free_rx_ring;
2165
2166 if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2167 skge->dma + rx_size)))
2168 goto free_rx_ring;
2169
2170 skge->tx_avail = skge->tx_ring.count - 1;
2171
2172 /* Enable IRQ from port */
2173 hw->intr_mask |= portirqmask[port];
2174 skge_write32(hw, B0_IMSK, hw->intr_mask);
2175
2176 /* Initialize MAC */
2177 spin_lock_bh(&hw->phy_lock);
2178 if (hw->chip_id == CHIP_ID_GENESIS)
2179 genesis_mac_init(hw, port);
2180 else
2181 yukon_mac_init(hw, port);
2182 spin_unlock_bh(&hw->phy_lock);
2183
2184 /* Configure RAMbuffers */
2185 chunk = hw->ram_size / ((hw->ports + 1)*2);
2186 ram_addr = hw->ram_offset + 2 * chunk * port;
2187
2188 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2189 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2190
2191 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2192 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2193 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2194
2195 /* Start receiver BMU */
2196 wmb();
2197 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2198 skge_led(skge, LED_MODE_ON);
2199
2200 return 0;
2201
2202 free_rx_ring:
2203 skge_rx_clean(skge);
2204 kfree(skge->rx_ring.start);
2205 free_pci_mem:
2206 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2207 skge->mem = NULL;
2208
2209 return err;
2210 }
2211
2212 static int skge_down(struct net_device *dev)
2213 {
2214 struct skge_port *skge = netdev_priv(dev);
2215 struct skge_hw *hw = skge->hw;
2216 int port = skge->port;
2217
2218 if (skge->mem == NULL)
2219 return 0;
2220
2221 if (netif_msg_ifdown(skge))
2222 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2223
2224 netif_stop_queue(dev);
2225
2226 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2227 if (hw->chip_id == CHIP_ID_GENESIS)
2228 genesis_stop(skge);
2229 else
2230 yukon_stop(skge);
2231
2232 hw->intr_mask &= ~portirqmask[skge->port];
2233 skge_write32(hw, B0_IMSK, hw->intr_mask);
2234
2235 /* Stop transmitter */
2236 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2237 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2238 RB_RST_SET|RB_DIS_OP_MD);
2239
2240
2241 /* Disable Force Sync bit and Enable Alloc bit */
2242 skge_write8(hw, SK_REG(port, TXA_CTRL),
2243 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2244
2245 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2246 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2247 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2248
2249 /* Reset PCI FIFO */
2250 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2251 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2252
2253 /* Reset the RAM Buffer async Tx queue */
2254 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2255 /* stop receiver */
2256 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2257 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2258 RB_RST_SET|RB_DIS_OP_MD);
2259 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2260
2261 if (hw->chip_id == CHIP_ID_GENESIS) {
2262 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2263 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2264 } else {
2265 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2266 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2267 }
2268
2269 skge_led(skge, LED_MODE_OFF);
2270
2271 skge_tx_clean(skge);
2272 skge_rx_clean(skge);
2273
2274 kfree(skge->rx_ring.start);
2275 kfree(skge->tx_ring.start);
2276 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2277 skge->mem = NULL;
2278 return 0;
2279 }
2280
2281 static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2282 {
2283 struct skge_port *skge = netdev_priv(dev);
2284 struct skge_hw *hw = skge->hw;
2285 struct skge_ring *ring = &skge->tx_ring;
2286 struct skge_element *e;
2287 struct skge_tx_desc *td;
2288 int i;
2289 u32 control, len;
2290 u64 map;
2291 unsigned long flags;
2292
2293 skb = skb_padto(skb, ETH_ZLEN);
2294 if (!skb)
2295 return NETDEV_TX_OK;
2296
2297 local_irq_save(flags);
2298 if (!spin_trylock(&skge->tx_lock)) {
2299 /* Collision - tell upper layer to requeue */
2300 local_irq_restore(flags);
2301 return NETDEV_TX_LOCKED;
2302 }
2303
2304 if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {
2305 if (!netif_queue_stopped(dev)) {
2306 netif_stop_queue(dev);
2307
2308 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2309 dev->name);
2310 }
2311 spin_unlock_irqrestore(&skge->tx_lock, flags);
2312 return NETDEV_TX_BUSY;
2313 }
2314
2315 e = ring->to_use;
2316 td = e->desc;
2317 e->skb = skb;
2318 len = skb_headlen(skb);
2319 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2320 pci_unmap_addr_set(e, mapaddr, map);
2321 pci_unmap_len_set(e, maplen, len);
2322
2323 td->dma_lo = map;
2324 td->dma_hi = map >> 32;
2325
2326 if (skb->ip_summed == CHECKSUM_HW) {
2327 int offset = skb->h.raw - skb->data;
2328
2329 /* This seems backwards, but it is what the sk98lin
2330 * does. Looks like hardware is wrong?
2331 */
2332 if (skb->h.ipiph->protocol == IPPROTO_UDP
2333 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2334 control = BMU_TCP_CHECK;
2335 else
2336 control = BMU_UDP_CHECK;
2337
2338 td->csum_offs = 0;
2339 td->csum_start = offset;
2340 td->csum_write = offset + skb->csum;
2341 } else
2342 control = BMU_CHECK;
2343
2344 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2345 control |= BMU_EOF| BMU_IRQ_EOF;
2346 else {
2347 struct skge_tx_desc *tf = td;
2348
2349 control |= BMU_STFWD;
2350 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2351 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2352
2353 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2354 frag->size, PCI_DMA_TODEVICE);
2355
2356 e = e->next;
2357 e->skb = NULL;
2358 tf = e->desc;
2359 tf->dma_lo = map;
2360 tf->dma_hi = (u64) map >> 32;
2361 pci_unmap_addr_set(e, mapaddr, map);
2362 pci_unmap_len_set(e, maplen, frag->size);
2363
2364 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2365 }
2366 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2367 }
2368 /* Make sure all the descriptors written */
2369 wmb();
2370 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2371 wmb();
2372
2373 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2374
2375 if (netif_msg_tx_queued(skge))
2376 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
2377 dev->name, e - ring->start, skb->len);
2378
2379 ring->to_use = e->next;
2380 skge->tx_avail -= skb_shinfo(skb)->nr_frags + 1;
2381 if (skge->tx_avail <= MAX_SKB_FRAGS + 1) {
2382 pr_debug("%s: transmit queue full\n", dev->name);
2383 netif_stop_queue(dev);
2384 }
2385
2386 dev->trans_start = jiffies;
2387 spin_unlock_irqrestore(&skge->tx_lock, flags);
2388
2389 return NETDEV_TX_OK;
2390 }
2391
2392 static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)
2393 {
2394 /* This ring element can be skb or fragment */
2395 if (e->skb) {
2396 pci_unmap_single(hw->pdev,
2397 pci_unmap_addr(e, mapaddr),
2398 pci_unmap_len(e, maplen),
2399 PCI_DMA_TODEVICE);
2400 dev_kfree_skb_any(e->skb);
2401 e->skb = NULL;
2402 } else {
2403 pci_unmap_page(hw->pdev,
2404 pci_unmap_addr(e, mapaddr),
2405 pci_unmap_len(e, maplen),
2406 PCI_DMA_TODEVICE);
2407 }
2408 }
2409
2410 static void skge_tx_clean(struct skge_port *skge)
2411 {
2412 struct skge_ring *ring = &skge->tx_ring;
2413 struct skge_element *e;
2414 unsigned long flags;
2415
2416 spin_lock_irqsave(&skge->tx_lock, flags);
2417 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2418 ++skge->tx_avail;
2419 skge_tx_free(skge->hw, e);
2420 }
2421 ring->to_clean = e;
2422 spin_unlock_irqrestore(&skge->tx_lock, flags);
2423 }
2424
2425 static void skge_tx_timeout(struct net_device *dev)
2426 {
2427 struct skge_port *skge = netdev_priv(dev);
2428
2429 if (netif_msg_timer(skge))
2430 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2431
2432 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2433 skge_tx_clean(skge);
2434 }
2435
2436 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2437 {
2438 int err;
2439
2440 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2441 return -EINVAL;
2442
2443 if (!netif_running(dev)) {
2444 dev->mtu = new_mtu;
2445 return 0;
2446 }
2447
2448 skge_down(dev);
2449
2450 dev->mtu = new_mtu;
2451
2452 err = skge_up(dev);
2453 if (err)
2454 dev_close(dev);
2455
2456 return err;
2457 }
2458
2459 static void genesis_set_multicast(struct net_device *dev)
2460 {
2461 struct skge_port *skge = netdev_priv(dev);
2462 struct skge_hw *hw = skge->hw;
2463 int port = skge->port;
2464 int i, count = dev->mc_count;
2465 struct dev_mc_list *list = dev->mc_list;
2466 u32 mode;
2467 u8 filter[8];
2468
2469 mode = xm_read32(hw, port, XM_MODE);
2470 mode |= XM_MD_ENA_HASH;
2471 if (dev->flags & IFF_PROMISC)
2472 mode |= XM_MD_ENA_PROM;
2473 else
2474 mode &= ~XM_MD_ENA_PROM;
2475
2476 if (dev->flags & IFF_ALLMULTI)
2477 memset(filter, 0xff, sizeof(filter));
2478 else {
2479 memset(filter, 0, sizeof(filter));
2480 for (i = 0; list && i < count; i++, list = list->next) {
2481 u32 crc, bit;
2482 crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
2483 bit = ~crc & 0x3f;
2484 filter[bit/8] |= 1 << (bit%8);
2485 }
2486 }
2487
2488 xm_write32(hw, port, XM_MODE, mode);
2489 xm_outhash(hw, port, XM_HSM, filter);
2490 }
2491
2492 static void yukon_set_multicast(struct net_device *dev)
2493 {
2494 struct skge_port *skge = netdev_priv(dev);
2495 struct skge_hw *hw = skge->hw;
2496 int port = skge->port;
2497 struct dev_mc_list *list = dev->mc_list;
2498 u16 reg;
2499 u8 filter[8];
2500
2501 memset(filter, 0, sizeof(filter));
2502
2503 reg = gma_read16(hw, port, GM_RX_CTRL);
2504 reg |= GM_RXCR_UCF_ENA;
2505
2506 if (dev->flags & IFF_PROMISC) /* promiscuous */
2507 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2508 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2509 memset(filter, 0xff, sizeof(filter));
2510 else if (dev->mc_count == 0) /* no multicast */
2511 reg &= ~GM_RXCR_MCF_ENA;
2512 else {
2513 int i;
2514 reg |= GM_RXCR_MCF_ENA;
2515
2516 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2517 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2518 filter[bit/8] |= 1 << (bit%8);
2519 }
2520 }
2521
2522
2523 gma_write16(hw, port, GM_MC_ADDR_H1,
2524 (u16)filter[0] | ((u16)filter[1] << 8));
2525 gma_write16(hw, port, GM_MC_ADDR_H2,
2526 (u16)filter[2] | ((u16)filter[3] << 8));
2527 gma_write16(hw, port, GM_MC_ADDR_H3,
2528 (u16)filter[4] | ((u16)filter[5] << 8));
2529 gma_write16(hw, port, GM_MC_ADDR_H4,
2530 (u16)filter[6] | ((u16)filter[7] << 8));
2531
2532 gma_write16(hw, port, GM_RX_CTRL, reg);
2533 }
2534
2535 static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2536 {
2537 if (hw->chip_id == CHIP_ID_GENESIS)
2538 return status >> XMR_FS_LEN_SHIFT;
2539 else
2540 return status >> GMR_FS_LEN_SHIFT;
2541 }
2542
2543 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2544 {
2545 if (hw->chip_id == CHIP_ID_GENESIS)
2546 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2547 else
2548 return (status & GMR_FS_ANY_ERR) ||
2549 (status & GMR_FS_RX_OK) == 0;
2550 }
2551
2552
2553 /* Get receive buffer from descriptor.
2554 * Handles copy of small buffers and reallocation failures
2555 */
2556 static inline struct sk_buff *skge_rx_get(struct skge_port *skge,
2557 struct skge_element *e,
2558 u32 control, u32 status, u16 csum)
2559 {
2560 struct sk_buff *skb;
2561 u16 len = control & BMU_BBC;
2562
2563 if (unlikely(netif_msg_rx_status(skge)))
2564 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
2565 skge->netdev->name, e - skge->rx_ring.start,
2566 status, len);
2567
2568 if (len > skge->rx_buf_size)
2569 goto error;
2570
2571 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
2572 goto error;
2573
2574 if (bad_phy_status(skge->hw, status))
2575 goto error;
2576
2577 if (phy_length(skge->hw, status) != len)
2578 goto error;
2579
2580 if (len < RX_COPY_THRESHOLD) {
2581 skb = dev_alloc_skb(len + 2);
2582 if (!skb)
2583 goto resubmit;
2584
2585 skb_reserve(skb, 2);
2586 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2587 pci_unmap_addr(e, mapaddr),
2588 len, PCI_DMA_FROMDEVICE);
2589 memcpy(skb->data, e->skb->data, len);
2590 pci_dma_sync_single_for_device(skge->hw->pdev,
2591 pci_unmap_addr(e, mapaddr),
2592 len, PCI_DMA_FROMDEVICE);
2593 skge_rx_reuse(e, skge->rx_buf_size);
2594 } else {
2595 struct sk_buff *nskb;
2596 nskb = dev_alloc_skb(skge->rx_buf_size + NET_IP_ALIGN);
2597 if (!nskb)
2598 goto resubmit;
2599
2600 pci_unmap_single(skge->hw->pdev,
2601 pci_unmap_addr(e, mapaddr),
2602 pci_unmap_len(e, maplen),
2603 PCI_DMA_FROMDEVICE);
2604 skb = e->skb;
2605 prefetch(skb->data);
2606 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
2607 }
2608
2609 skb_put(skb, len);
2610 skb->dev = skge->netdev;
2611 if (skge->rx_csum) {
2612 skb->csum = csum;
2613 skb->ip_summed = CHECKSUM_HW;
2614 }
2615
2616 skb->protocol = eth_type_trans(skb, skge->netdev);
2617
2618 return skb;
2619 error:
2620
2621 if (netif_msg_rx_err(skge))
2622 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
2623 skge->netdev->name, e - skge->rx_ring.start,
2624 control, status);
2625
2626 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2627 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2628 skge->net_stats.rx_length_errors++;
2629 if (status & XMR_FS_FRA_ERR)
2630 skge->net_stats.rx_frame_errors++;
2631 if (status & XMR_FS_FCS_ERR)
2632 skge->net_stats.rx_crc_errors++;
2633 } else {
2634 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2635 skge->net_stats.rx_length_errors++;
2636 if (status & GMR_FS_FRAGMENT)
2637 skge->net_stats.rx_frame_errors++;
2638 if (status & GMR_FS_CRC_ERR)
2639 skge->net_stats.rx_crc_errors++;
2640 }
2641
2642 resubmit:
2643 skge_rx_reuse(e, skge->rx_buf_size);
2644 return NULL;
2645 }
2646
2647
2648 static int skge_poll(struct net_device *dev, int *budget)
2649 {
2650 struct skge_port *skge = netdev_priv(dev);
2651 struct skge_hw *hw = skge->hw;
2652 struct skge_ring *ring = &skge->rx_ring;
2653 struct skge_element *e;
2654 unsigned int to_do = min(dev->quota, *budget);
2655 unsigned int work_done = 0;
2656
2657 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
2658 struct skge_rx_desc *rd = e->desc;
2659 struct sk_buff *skb;
2660 u32 control;
2661
2662 rmb();
2663 control = rd->control;
2664 if (control & BMU_OWN)
2665 break;
2666
2667 skb = skge_rx_get(skge, e, control, rd->status,
2668 le16_to_cpu(rd->csum2));
2669 if (likely(skb)) {
2670 dev->last_rx = jiffies;
2671 netif_receive_skb(skb);
2672
2673 ++work_done;
2674 } else
2675 skge_rx_reuse(e, skge->rx_buf_size);
2676 }
2677 ring->to_clean = e;
2678
2679 /* restart receiver */
2680 wmb();
2681 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR),
2682 CSR_START | CSR_IRQ_CL_F);
2683
2684 *budget -= work_done;
2685 dev->quota -= work_done;
2686
2687 if (work_done >= to_do)
2688 return 1; /* not done */
2689
2690 netif_rx_complete(dev);
2691 hw->intr_mask |= portirqmask[skge->port];
2692 skge_write32(hw, B0_IMSK, hw->intr_mask);
2693 skge_read32(hw, B0_IMSK);
2694
2695 return 0;
2696 }
2697
2698 static inline void skge_tx_intr(struct net_device *dev)
2699 {
2700 struct skge_port *skge = netdev_priv(dev);
2701 struct skge_hw *hw = skge->hw;
2702 struct skge_ring *ring = &skge->tx_ring;
2703 struct skge_element *e;
2704
2705 spin_lock(&skge->tx_lock);
2706 for (e = ring->to_clean; prefetch(e->next), e != ring->to_use; e = e->next) {
2707 struct skge_tx_desc *td = e->desc;
2708 u32 control;
2709
2710 rmb();
2711 control = td->control;
2712 if (control & BMU_OWN)
2713 break;
2714
2715 if (unlikely(netif_msg_tx_done(skge)))
2716 printk(KERN_DEBUG PFX "%s: tx done slot %td status 0x%x\n",
2717 dev->name, e - ring->start, td->status);
2718
2719 skge_tx_free(hw, e);
2720 e->skb = NULL;
2721 ++skge->tx_avail;
2722 }
2723 ring->to_clean = e;
2724 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2725
2726 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
2727 netif_wake_queue(dev);
2728
2729 spin_unlock(&skge->tx_lock);
2730 }
2731
2732 /* Parity errors seem to happen when Genesis is connected to a switch
2733 * with no other ports present. Heartbeat error??
2734 */
2735 static void skge_mac_parity(struct skge_hw *hw, int port)
2736 {
2737 struct net_device *dev = hw->dev[port];
2738
2739 if (dev) {
2740 struct skge_port *skge = netdev_priv(dev);
2741 ++skge->net_stats.tx_heartbeat_errors;
2742 }
2743
2744 if (hw->chip_id == CHIP_ID_GENESIS)
2745 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
2746 MFF_CLR_PERR);
2747 else
2748 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
2749 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
2750 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
2751 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2752 }
2753
2754 static void skge_pci_clear(struct skge_hw *hw)
2755 {
2756 u16 status;
2757
2758 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
2759 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2760 pci_write_config_word(hw->pdev, PCI_STATUS,
2761 status | PCI_STATUS_ERROR_BITS);
2762 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2763 }
2764
2765 static void skge_mac_intr(struct skge_hw *hw, int port)
2766 {
2767 if (hw->chip_id == CHIP_ID_GENESIS)
2768 genesis_mac_intr(hw, port);
2769 else
2770 yukon_mac_intr(hw, port);
2771 }
2772
2773 /* Handle device specific framing and timeout interrupts */
2774 static void skge_error_irq(struct skge_hw *hw)
2775 {
2776 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2777
2778 if (hw->chip_id == CHIP_ID_GENESIS) {
2779 /* clear xmac errors */
2780 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
2781 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
2782 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
2783 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
2784 } else {
2785 /* Timestamp (unused) overflow */
2786 if (hwstatus & IS_IRQ_TIST_OV)
2787 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2788 }
2789
2790 if (hwstatus & IS_RAM_RD_PAR) {
2791 printk(KERN_ERR PFX "Ram read data parity error\n");
2792 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2793 }
2794
2795 if (hwstatus & IS_RAM_WR_PAR) {
2796 printk(KERN_ERR PFX "Ram write data parity error\n");
2797 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
2798 }
2799
2800 if (hwstatus & IS_M1_PAR_ERR)
2801 skge_mac_parity(hw, 0);
2802
2803 if (hwstatus & IS_M2_PAR_ERR)
2804 skge_mac_parity(hw, 1);
2805
2806 if (hwstatus & IS_R1_PAR_ERR)
2807 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
2808
2809 if (hwstatus & IS_R2_PAR_ERR)
2810 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
2811
2812 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
2813 printk(KERN_ERR PFX "hardware error detected (status 0x%x)\n",
2814 hwstatus);
2815
2816 skge_pci_clear(hw);
2817
2818 /* if error still set then just ignore it */
2819 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2820 if (hwstatus & IS_IRQ_STAT) {
2821 pr_debug("IRQ status %x: still set ignoring hardware errors\n",
2822 hwstatus);
2823 hw->intr_mask &= ~IS_HW_ERR;
2824 }
2825 }
2826 }
2827
2828 /*
2829 * Interrupt from PHY are handled in tasklet (soft irq)
2830 * because accessing phy registers requires spin wait which might
2831 * cause excess interrupt latency.
2832 */
2833 static void skge_extirq(unsigned long data)
2834 {
2835 struct skge_hw *hw = (struct skge_hw *) data;
2836 int port;
2837
2838 spin_lock(&hw->phy_lock);
2839 for (port = 0; port < 2; port++) {
2840 struct net_device *dev = hw->dev[port];
2841
2842 if (dev && netif_running(dev)) {
2843 struct skge_port *skge = netdev_priv(dev);
2844
2845 if (hw->chip_id != CHIP_ID_GENESIS)
2846 yukon_phy_intr(skge);
2847 else
2848 bcom_phy_intr(skge);
2849 }
2850 }
2851 spin_unlock(&hw->phy_lock);
2852
2853 local_irq_disable();
2854 hw->intr_mask |= IS_EXT_REG;
2855 skge_write32(hw, B0_IMSK, hw->intr_mask);
2856 local_irq_enable();
2857 }
2858
2859 static inline void skge_wakeup(struct net_device *dev)
2860 {
2861 struct skge_port *skge = netdev_priv(dev);
2862
2863 prefetch(skge->rx_ring.to_clean);
2864 netif_rx_schedule(dev);
2865 }
2866
2867 static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2868 {
2869 struct skge_hw *hw = dev_id;
2870 u32 status = skge_read32(hw, B0_SP_ISRC);
2871
2872 if (status == 0 || status == ~0) /* hotplug or shared irq */
2873 return IRQ_NONE;
2874
2875 status &= hw->intr_mask;
2876 if (status & IS_R1_F) {
2877 hw->intr_mask &= ~IS_R1_F;
2878 skge_wakeup(hw->dev[0]);
2879 }
2880
2881 if (status & IS_R2_F) {
2882 hw->intr_mask &= ~IS_R2_F;
2883 skge_wakeup(hw->dev[1]);
2884 }
2885
2886 if (status & IS_XA1_F)
2887 skge_tx_intr(hw->dev[0]);
2888
2889 if (status & IS_XA2_F)
2890 skge_tx_intr(hw->dev[1]);
2891
2892 if (status & IS_PA_TO_RX1) {
2893 struct skge_port *skge = netdev_priv(hw->dev[0]);
2894 ++skge->net_stats.rx_over_errors;
2895 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
2896 }
2897
2898 if (status & IS_PA_TO_RX2) {
2899 struct skge_port *skge = netdev_priv(hw->dev[1]);
2900 ++skge->net_stats.rx_over_errors;
2901 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
2902 }
2903
2904 if (status & IS_PA_TO_TX1)
2905 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
2906
2907 if (status & IS_PA_TO_TX2)
2908 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
2909
2910 if (status & IS_MAC1)
2911 skge_mac_intr(hw, 0);
2912
2913 if (status & IS_MAC2)
2914 skge_mac_intr(hw, 1);
2915
2916 if (status & IS_HW_ERR)
2917 skge_error_irq(hw);
2918
2919 if (status & IS_EXT_REG) {
2920 hw->intr_mask &= ~IS_EXT_REG;
2921 tasklet_schedule(&hw->ext_tasklet);
2922 }
2923
2924 skge_write32(hw, B0_IMSK, hw->intr_mask);
2925
2926 return IRQ_HANDLED;
2927 }
2928
2929 #ifdef CONFIG_NET_POLL_CONTROLLER
2930 static void skge_netpoll(struct net_device *dev)
2931 {
2932 struct skge_port *skge = netdev_priv(dev);
2933
2934 disable_irq(dev->irq);
2935 skge_intr(dev->irq, skge->hw, NULL);
2936 enable_irq(dev->irq);
2937 }
2938 #endif
2939
2940 static int skge_set_mac_address(struct net_device *dev, void *p)
2941 {
2942 struct skge_port *skge = netdev_priv(dev);
2943 struct skge_hw *hw = skge->hw;
2944 unsigned port = skge->port;
2945 const struct sockaddr *addr = p;
2946
2947 if (!is_valid_ether_addr(addr->sa_data))
2948 return -EADDRNOTAVAIL;
2949
2950 spin_lock_bh(&hw->phy_lock);
2951 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2952 memcpy_toio(hw->regs + B2_MAC_1 + port*8,
2953 dev->dev_addr, ETH_ALEN);
2954 memcpy_toio(hw->regs + B2_MAC_2 + port*8,
2955 dev->dev_addr, ETH_ALEN);
2956
2957 if (hw->chip_id == CHIP_ID_GENESIS)
2958 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
2959 else {
2960 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2961 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2962 }
2963 spin_unlock_bh(&hw->phy_lock);
2964
2965 return 0;
2966 }
2967
2968 static const struct {
2969 u8 id;
2970 const char *name;
2971 } skge_chips[] = {
2972 { CHIP_ID_GENESIS, "Genesis" },
2973 { CHIP_ID_YUKON, "Yukon" },
2974 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
2975 { CHIP_ID_YUKON_LP, "Yukon-LP"},
2976 };
2977
2978 static const char *skge_board_name(const struct skge_hw *hw)
2979 {
2980 int i;
2981 static char buf[16];
2982
2983 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
2984 if (skge_chips[i].id == hw->chip_id)
2985 return skge_chips[i].name;
2986
2987 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
2988 return buf;
2989 }
2990
2991
2992 /*
2993 * Setup the board data structure, but don't bring up
2994 * the port(s)
2995 */
2996 static int skge_reset(struct skge_hw *hw)
2997 {
2998 u32 reg;
2999 u16 ctst;
3000 u8 t8, mac_cfg, pmd_type, phy_type;
3001 int i;
3002
3003 ctst = skge_read16(hw, B0_CTST);
3004
3005 /* do a SW reset */
3006 skge_write8(hw, B0_CTST, CS_RST_SET);
3007 skge_write8(hw, B0_CTST, CS_RST_CLR);
3008
3009 /* clear PCI errors, if any */
3010 skge_pci_clear(hw);
3011
3012 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3013
3014 /* restore CLK_RUN bits (for Yukon-Lite) */
3015 skge_write16(hw, B0_CTST,
3016 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3017
3018 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
3019 phy_type = skge_read8(hw, B2_E_1) & 0xf;
3020 pmd_type = skge_read8(hw, B2_PMD_TYP);
3021 hw->copper = (pmd_type == 'T' || pmd_type == '1');
3022
3023 switch (hw->chip_id) {
3024 case CHIP_ID_GENESIS:
3025 switch (phy_type) {
3026 case SK_PHY_BCOM:
3027 hw->phy_addr = PHY_ADDR_BCOM;
3028 break;
3029 default:
3030 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
3031 pci_name(hw->pdev), phy_type);
3032 return -EOPNOTSUPP;
3033 }
3034 break;
3035
3036 case CHIP_ID_YUKON:
3037 case CHIP_ID_YUKON_LITE:
3038 case CHIP_ID_YUKON_LP:
3039 if (phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3040 hw->copper = 1;
3041
3042 hw->phy_addr = PHY_ADDR_MARV;
3043 break;
3044
3045 default:
3046 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
3047 pci_name(hw->pdev), hw->chip_id);
3048 return -EOPNOTSUPP;
3049 }
3050
3051 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3052 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3053 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
3054
3055 /* read the adapters RAM size */
3056 t8 = skge_read8(hw, B2_E_0);
3057 if (hw->chip_id == CHIP_ID_GENESIS) {
3058 if (t8 == 3) {
3059 /* special case: 4 x 64k x 36, offset = 0x80000 */
3060 hw->ram_size = 0x100000;
3061 hw->ram_offset = 0x80000;
3062 } else
3063 hw->ram_size = t8 * 512;
3064 }
3065 else if (t8 == 0)
3066 hw->ram_size = 0x20000;
3067 else
3068 hw->ram_size = t8 * 4096;
3069
3070 hw->intr_mask = IS_HW_ERR | IS_EXT_REG;
3071 if (hw->chip_id == CHIP_ID_GENESIS)
3072 genesis_init(hw);
3073 else {
3074 /* switch power to VCC (WA for VAUX problem) */
3075 skge_write8(hw, B0_POWER_CTRL,
3076 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3077
3078 /* avoid boards with stuck Hardware error bits */
3079 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3080 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3081 printk(KERN_WARNING PFX "stuck hardware sensor bit\n");
3082 hw->intr_mask &= ~IS_HW_ERR;
3083 }
3084
3085 /* Clear PHY COMA */
3086 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3087 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3088 reg &= ~PCI_PHY_COMA;
3089 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3090 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3091
3092
3093 for (i = 0; i < hw->ports; i++) {
3094 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3095 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3096 }
3097 }
3098
3099 /* turn off hardware timer (unused) */
3100 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3101 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3102 skge_write8(hw, B0_LED, LED_STAT_ON);
3103
3104 /* enable the Tx Arbiters */
3105 for (i = 0; i < hw->ports; i++)
3106 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3107
3108 /* Initialize ram interface */
3109 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3110
3111 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3112 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3113 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3114 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3115 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3116 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3117 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3118 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3119 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3120 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3121 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3122 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3123
3124 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3125
3126 /* Set interrupt moderation for Transmit only
3127 * Receive interrupts avoided by NAPI
3128 */
3129 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3130 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3131 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3132
3133 skge_write32(hw, B0_IMSK, hw->intr_mask);
3134
3135 spin_lock_bh(&hw->phy_lock);
3136 for (i = 0; i < hw->ports; i++) {
3137 if (hw->chip_id == CHIP_ID_GENESIS)
3138 genesis_reset(hw, i);
3139 else
3140 yukon_reset(hw, i);
3141 }
3142 spin_unlock_bh(&hw->phy_lock);
3143
3144 return 0;
3145 }
3146
3147 /* Initialize network device */
3148 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3149 int highmem)
3150 {
3151 struct skge_port *skge;
3152 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3153
3154 if (!dev) {
3155 printk(KERN_ERR "skge etherdev alloc failed");
3156 return NULL;
3157 }
3158
3159 SET_MODULE_OWNER(dev);
3160 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3161 dev->open = skge_up;
3162 dev->stop = skge_down;
3163 dev->do_ioctl = skge_ioctl;
3164 dev->hard_start_xmit = skge_xmit_frame;
3165 dev->get_stats = skge_get_stats;
3166 if (hw->chip_id == CHIP_ID_GENESIS)
3167 dev->set_multicast_list = genesis_set_multicast;
3168 else
3169 dev->set_multicast_list = yukon_set_multicast;
3170
3171 dev->set_mac_address = skge_set_mac_address;
3172 dev->change_mtu = skge_change_mtu;
3173 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3174 dev->tx_timeout = skge_tx_timeout;
3175 dev->watchdog_timeo = TX_WATCHDOG;
3176 dev->poll = skge_poll;
3177 dev->weight = NAPI_WEIGHT;
3178 #ifdef CONFIG_NET_POLL_CONTROLLER
3179 dev->poll_controller = skge_netpoll;
3180 #endif
3181 dev->irq = hw->pdev->irq;
3182 dev->features = NETIF_F_LLTX;
3183 if (highmem)
3184 dev->features |= NETIF_F_HIGHDMA;
3185
3186 skge = netdev_priv(dev);
3187 skge->netdev = dev;
3188 skge->hw = hw;
3189 skge->msg_enable = netif_msg_init(debug, default_msg);
3190 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3191 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3192
3193 /* Auto speed and flow control */
3194 skge->autoneg = AUTONEG_ENABLE;
3195 skge->flow_control = FLOW_MODE_SYMMETRIC;
3196 skge->duplex = -1;
3197 skge->speed = -1;
3198 skge->advertising = skge_supported_modes(hw);
3199
3200 hw->dev[port] = dev;
3201
3202 skge->port = port;
3203
3204 spin_lock_init(&skge->tx_lock);
3205
3206 if (hw->chip_id != CHIP_ID_GENESIS) {
3207 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3208 skge->rx_csum = 1;
3209 }
3210
3211 /* read the mac address */
3212 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3213 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3214
3215 /* device is off until link detection */
3216 netif_carrier_off(dev);
3217 netif_stop_queue(dev);
3218
3219 return dev;
3220 }
3221
3222 static void __devinit skge_show_addr(struct net_device *dev)
3223 {
3224 const struct skge_port *skge = netdev_priv(dev);
3225
3226 if (netif_msg_probe(skge))
3227 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3228 dev->name,
3229 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3230 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3231 }
3232
3233 static int __devinit skge_probe(struct pci_dev *pdev,
3234 const struct pci_device_id *ent)
3235 {
3236 struct net_device *dev, *dev1;
3237 struct skge_hw *hw;
3238 int err, using_dac = 0;
3239
3240 if ((err = pci_enable_device(pdev))) {
3241 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3242 pci_name(pdev));
3243 goto err_out;
3244 }
3245
3246 if ((err = pci_request_regions(pdev, DRV_NAME))) {
3247 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3248 pci_name(pdev));
3249 goto err_out_disable_pdev;
3250 }
3251
3252 pci_set_master(pdev);
3253
3254 if (sizeof(dma_addr_t) > sizeof(u32) &&
3255 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3256 using_dac = 1;
3257 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3258 if (err < 0) {
3259 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3260 "for consistent allocations\n", pci_name(pdev));
3261 goto err_out_free_regions;
3262 }
3263 } else {
3264 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3265 if (err) {
3266 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3267 pci_name(pdev));
3268 goto err_out_free_regions;
3269 }
3270 }
3271
3272 #ifdef __BIG_ENDIAN
3273 /* byte swap descriptors in hardware */
3274 {
3275 u32 reg;
3276
3277 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3278 reg |= PCI_REV_DESC;
3279 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3280 }
3281 #endif
3282
3283 err = -ENOMEM;
3284 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3285 if (!hw) {
3286 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3287 pci_name(pdev));
3288 goto err_out_free_regions;
3289 }
3290
3291 hw->pdev = pdev;
3292 spin_lock_init(&hw->phy_lock);
3293 tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);
3294
3295 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3296 if (!hw->regs) {
3297 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3298 pci_name(pdev));
3299 goto err_out_free_hw;
3300 }
3301
3302 if ((err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw))) {
3303 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3304 pci_name(pdev), pdev->irq);
3305 goto err_out_iounmap;
3306 }
3307 pci_set_drvdata(pdev, hw);
3308
3309 err = skge_reset(hw);
3310 if (err)
3311 goto err_out_free_irq;
3312
3313 printk(KERN_INFO PFX DRV_VERSION " addr 0x%lx irq %d chip %s rev %d\n",
3314 pci_resource_start(pdev, 0), pdev->irq,
3315 skge_board_name(hw), hw->chip_rev);
3316
3317 if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)
3318 goto err_out_led_off;
3319
3320 if ((err = register_netdev(dev))) {
3321 printk(KERN_ERR PFX "%s: cannot register net device\n",
3322 pci_name(pdev));
3323 goto err_out_free_netdev;
3324 }
3325
3326 skge_show_addr(dev);
3327
3328 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
3329 if (register_netdev(dev1) == 0)
3330 skge_show_addr(dev1);
3331 else {
3332 /* Failure to register second port need not be fatal */
3333 printk(KERN_WARNING PFX "register of second port failed\n");
3334 hw->dev[1] = NULL;
3335 free_netdev(dev1);
3336 }
3337 }
3338
3339 return 0;
3340
3341 err_out_free_netdev:
3342 free_netdev(dev);
3343 err_out_led_off:
3344 skge_write16(hw, B0_LED, LED_STAT_OFF);
3345 err_out_free_irq:
3346 free_irq(pdev->irq, hw);
3347 err_out_iounmap:
3348 iounmap(hw->regs);
3349 err_out_free_hw:
3350 kfree(hw);
3351 err_out_free_regions:
3352 pci_release_regions(pdev);
3353 err_out_disable_pdev:
3354 pci_disable_device(pdev);
3355 pci_set_drvdata(pdev, NULL);
3356 err_out:
3357 return err;
3358 }
3359
3360 static void __devexit skge_remove(struct pci_dev *pdev)
3361 {
3362 struct skge_hw *hw = pci_get_drvdata(pdev);
3363 struct net_device *dev0, *dev1;
3364
3365 if (!hw)
3366 return;
3367
3368 if ((dev1 = hw->dev[1]))
3369 unregister_netdev(dev1);
3370 dev0 = hw->dev[0];
3371 unregister_netdev(dev0);
3372
3373 skge_write32(hw, B0_IMSK, 0);
3374 skge_write16(hw, B0_LED, LED_STAT_OFF);
3375 skge_pci_clear(hw);
3376 skge_write8(hw, B0_CTST, CS_RST_SET);
3377
3378 tasklet_kill(&hw->ext_tasklet);
3379
3380 free_irq(pdev->irq, hw);
3381 pci_release_regions(pdev);
3382 pci_disable_device(pdev);
3383 if (dev1)
3384 free_netdev(dev1);
3385 free_netdev(dev0);
3386
3387 iounmap(hw->regs);
3388 kfree(hw);
3389 pci_set_drvdata(pdev, NULL);
3390 }
3391
3392 #ifdef CONFIG_PM
3393 static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
3394 {
3395 struct skge_hw *hw = pci_get_drvdata(pdev);
3396 int i, wol = 0;
3397
3398 for (i = 0; i < 2; i++) {
3399 struct net_device *dev = hw->dev[i];
3400
3401 if (dev) {
3402 struct skge_port *skge = netdev_priv(dev);
3403 if (netif_running(dev)) {
3404 netif_carrier_off(dev);
3405 if (skge->wol)
3406 netif_stop_queue(dev);
3407 else
3408 skge_down(dev);
3409 }
3410 netif_device_detach(dev);
3411 wol |= skge->wol;
3412 }
3413 }
3414
3415 pci_save_state(pdev);
3416 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
3417 pci_disable_device(pdev);
3418 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3419
3420 return 0;
3421 }
3422
3423 static int skge_resume(struct pci_dev *pdev)
3424 {
3425 struct skge_hw *hw = pci_get_drvdata(pdev);
3426 int i;
3427
3428 pci_set_power_state(pdev, PCI_D0);
3429 pci_restore_state(pdev);
3430 pci_enable_wake(pdev, PCI_D0, 0);
3431
3432 skge_reset(hw);
3433
3434 for (i = 0; i < 2; i++) {
3435 struct net_device *dev = hw->dev[i];
3436 if (dev) {
3437 netif_device_attach(dev);
3438 if (netif_running(dev) && skge_up(dev))
3439 dev_close(dev);
3440 }
3441 }
3442 return 0;
3443 }
3444 #endif
3445
3446 static struct pci_driver skge_driver = {
3447 .name = DRV_NAME,
3448 .id_table = skge_id_table,
3449 .probe = skge_probe,
3450 .remove = __devexit_p(skge_remove),
3451 #ifdef CONFIG_PM
3452 .suspend = skge_suspend,
3453 .resume = skge_resume,
3454 #endif
3455 };
3456
3457 static int __init skge_init_module(void)
3458 {
3459 return pci_module_init(&skge_driver);
3460 }
3461
3462 static void __exit skge_cleanup_module(void)
3463 {
3464 pci_unregister_driver(&skge_driver);
3465 }
3466
3467 module_init(skge_init_module);
3468 module_exit(skge_cleanup_module);
Linux kernel - Deliverables
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