2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/moduleparam.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
34 #include <linux/if_vlan.h>
36 #include <linux/delay.h>
37 #include <linux/crc32.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/mii.h>
44 #define DRV_NAME "skge"
45 #define DRV_VERSION "1.9"
46 #define PFX DRV_NAME " "
48 #define DEFAULT_TX_RING_SIZE 128
49 #define DEFAULT_RX_RING_SIZE 512
50 #define MAX_TX_RING_SIZE 1024
51 #define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
52 #define MAX_RX_RING_SIZE 4096
53 #define RX_COPY_THRESHOLD 128
54 #define RX_BUF_SIZE 1536
55 #define PHY_RETRIES 1000
56 #define ETH_JUMBO_MTU 9000
57 #define TX_WATCHDOG (5 * HZ)
58 #define NAPI_WEIGHT 64
60 #define LINK_HZ (HZ/2)
62 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
63 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
64 MODULE_LICENSE("GPL");
65 MODULE_VERSION(DRV_VERSION
);
67 static const u32 default_msg
68 = NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
69 | NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
;
71 static int debug
= -1; /* defaults above */
72 module_param(debug
, int, 0);
73 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
75 static const struct pci_device_id skge_id_table
[] = {
76 { PCI_DEVICE(PCI_VENDOR_ID_3COM
, PCI_DEVICE_ID_3COM_3C940
) },
77 { PCI_DEVICE(PCI_VENDOR_ID_3COM
, PCI_DEVICE_ID_3COM_3C940B
) },
78 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_GE
) },
79 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_YU
) },
80 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, PCI_DEVICE_ID_DLINK_DGE510T
), },
81 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4b01) }, /* DGE-530T */
82 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4320) },
83 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x5005) }, /* Belkin */
84 { PCI_DEVICE(PCI_VENDOR_ID_CNET
, PCI_DEVICE_ID_CNET_GIGACARD
) },
85 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS
, PCI_DEVICE_ID_LINKSYS_EG1064
) },
86 { PCI_VENDOR_ID_LINKSYS
, 0x1032, PCI_ANY_ID
, 0x0015, },
89 MODULE_DEVICE_TABLE(pci
, skge_id_table
);
91 static int skge_up(struct net_device
*dev
);
92 static int skge_down(struct net_device
*dev
);
93 static void skge_phy_reset(struct skge_port
*skge
);
94 static void skge_tx_clean(struct net_device
*dev
);
95 static int xm_phy_write(struct skge_hw
*hw
, int port
, u16 reg
, u16 val
);
96 static int gm_phy_write(struct skge_hw
*hw
, int port
, u16 reg
, u16 val
);
97 static void genesis_get_stats(struct skge_port
*skge
, u64
*data
);
98 static void yukon_get_stats(struct skge_port
*skge
, u64
*data
);
99 static void yukon_init(struct skge_hw
*hw
, int port
);
100 static void genesis_mac_init(struct skge_hw
*hw
, int port
);
101 static void genesis_link_up(struct skge_port
*skge
);
103 /* Avoid conditionals by using array */
104 static const int txqaddr
[] = { Q_XA1
, Q_XA2
};
105 static const int rxqaddr
[] = { Q_R1
, Q_R2
};
106 static const u32 rxirqmask
[] = { IS_R1_F
, IS_R2_F
};
107 static const u32 txirqmask
[] = { IS_XA1_F
, IS_XA2_F
};
108 static const u32 irqmask
[] = { IS_R1_F
|IS_XA1_F
, IS_R2_F
|IS_XA2_F
};
110 static int skge_get_regs_len(struct net_device
*dev
)
116 * Returns copy of whole control register region
117 * Note: skip RAM address register because accessing it will
120 static void skge_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
123 const struct skge_port
*skge
= netdev_priv(dev
);
124 const void __iomem
*io
= skge
->hw
->regs
;
127 memset(p
, 0, regs
->len
);
128 memcpy_fromio(p
, io
, B3_RAM_ADDR
);
130 memcpy_fromio(p
+ B3_RI_WTO_R1
, io
+ B3_RI_WTO_R1
,
131 regs
->len
- B3_RI_WTO_R1
);
134 /* Wake on Lan only supported on Yukon chips with rev 1 or above */
135 static int wol_supported(const struct skge_hw
*hw
)
137 return !((hw
->chip_id
== CHIP_ID_GENESIS
||
138 (hw
->chip_id
== CHIP_ID_YUKON
&& hw
->chip_rev
== 0)));
141 static void skge_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
143 struct skge_port
*skge
= netdev_priv(dev
);
145 wol
->supported
= wol_supported(skge
->hw
) ? WAKE_MAGIC
: 0;
146 wol
->wolopts
= skge
->wol
? WAKE_MAGIC
: 0;
149 static int skge_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
151 struct skge_port
*skge
= netdev_priv(dev
);
152 struct skge_hw
*hw
= skge
->hw
;
154 if (wol
->wolopts
!= WAKE_MAGIC
&& wol
->wolopts
!= 0)
157 if (wol
->wolopts
== WAKE_MAGIC
&& !wol_supported(hw
))
160 skge
->wol
= wol
->wolopts
== WAKE_MAGIC
;
163 memcpy_toio(hw
->regs
+ WOL_MAC_ADDR
, dev
->dev_addr
, ETH_ALEN
);
165 skge_write16(hw
, WOL_CTRL_STAT
,
166 WOL_CTL_ENA_PME_ON_MAGIC_PKT
|
167 WOL_CTL_ENA_MAGIC_PKT_UNIT
);
169 skge_write16(hw
, WOL_CTRL_STAT
, WOL_CTL_DEFAULT
);
174 /* Determine supported/advertised modes based on hardware.
175 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
177 static u32
skge_supported_modes(const struct skge_hw
*hw
)
182 supported
= SUPPORTED_10baseT_Half
183 | SUPPORTED_10baseT_Full
184 | SUPPORTED_100baseT_Half
185 | SUPPORTED_100baseT_Full
186 | SUPPORTED_1000baseT_Half
187 | SUPPORTED_1000baseT_Full
188 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
190 if (hw
->chip_id
== CHIP_ID_GENESIS
)
191 supported
&= ~(SUPPORTED_10baseT_Half
192 | SUPPORTED_10baseT_Full
193 | SUPPORTED_100baseT_Half
194 | SUPPORTED_100baseT_Full
);
196 else if (hw
->chip_id
== CHIP_ID_YUKON
)
197 supported
&= ~SUPPORTED_1000baseT_Half
;
199 supported
= SUPPORTED_1000baseT_Full
| SUPPORTED_1000baseT_Half
200 | SUPPORTED_FIBRE
| SUPPORTED_Autoneg
;
205 static int skge_get_settings(struct net_device
*dev
,
206 struct ethtool_cmd
*ecmd
)
208 struct skge_port
*skge
= netdev_priv(dev
);
209 struct skge_hw
*hw
= skge
->hw
;
211 ecmd
->transceiver
= XCVR_INTERNAL
;
212 ecmd
->supported
= skge_supported_modes(hw
);
215 ecmd
->port
= PORT_TP
;
216 ecmd
->phy_address
= hw
->phy_addr
;
218 ecmd
->port
= PORT_FIBRE
;
220 ecmd
->advertising
= skge
->advertising
;
221 ecmd
->autoneg
= skge
->autoneg
;
222 ecmd
->speed
= skge
->speed
;
223 ecmd
->duplex
= skge
->duplex
;
227 static int skge_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
229 struct skge_port
*skge
= netdev_priv(dev
);
230 const struct skge_hw
*hw
= skge
->hw
;
231 u32 supported
= skge_supported_modes(hw
);
233 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
234 ecmd
->advertising
= supported
;
240 switch (ecmd
->speed
) {
242 if (ecmd
->duplex
== DUPLEX_FULL
)
243 setting
= SUPPORTED_1000baseT_Full
;
244 else if (ecmd
->duplex
== DUPLEX_HALF
)
245 setting
= SUPPORTED_1000baseT_Half
;
250 if (ecmd
->duplex
== DUPLEX_FULL
)
251 setting
= SUPPORTED_100baseT_Full
;
252 else if (ecmd
->duplex
== DUPLEX_HALF
)
253 setting
= SUPPORTED_100baseT_Half
;
259 if (ecmd
->duplex
== DUPLEX_FULL
)
260 setting
= SUPPORTED_10baseT_Full
;
261 else if (ecmd
->duplex
== DUPLEX_HALF
)
262 setting
= SUPPORTED_10baseT_Half
;
270 if ((setting
& supported
) == 0)
273 skge
->speed
= ecmd
->speed
;
274 skge
->duplex
= ecmd
->duplex
;
277 skge
->autoneg
= ecmd
->autoneg
;
278 skge
->advertising
= ecmd
->advertising
;
280 if (netif_running(dev
))
281 skge_phy_reset(skge
);
286 static void skge_get_drvinfo(struct net_device
*dev
,
287 struct ethtool_drvinfo
*info
)
289 struct skge_port
*skge
= netdev_priv(dev
);
291 strcpy(info
->driver
, DRV_NAME
);
292 strcpy(info
->version
, DRV_VERSION
);
293 strcpy(info
->fw_version
, "N/A");
294 strcpy(info
->bus_info
, pci_name(skge
->hw
->pdev
));
297 static const struct skge_stat
{
298 char name
[ETH_GSTRING_LEN
];
302 { "tx_bytes", XM_TXO_OK_HI
, GM_TXO_OK_HI
},
303 { "rx_bytes", XM_RXO_OK_HI
, GM_RXO_OK_HI
},
305 { "tx_broadcast", XM_TXF_BC_OK
, GM_TXF_BC_OK
},
306 { "rx_broadcast", XM_RXF_BC_OK
, GM_RXF_BC_OK
},
307 { "tx_multicast", XM_TXF_MC_OK
, GM_TXF_MC_OK
},
308 { "rx_multicast", XM_RXF_MC_OK
, GM_RXF_MC_OK
},
309 { "tx_unicast", XM_TXF_UC_OK
, GM_TXF_UC_OK
},
310 { "rx_unicast", XM_RXF_UC_OK
, GM_RXF_UC_OK
},
311 { "tx_mac_pause", XM_TXF_MPAUSE
, GM_TXF_MPAUSE
},
312 { "rx_mac_pause", XM_RXF_MPAUSE
, GM_RXF_MPAUSE
},
314 { "collisions", XM_TXF_SNG_COL
, GM_TXF_SNG_COL
},
315 { "multi_collisions", XM_TXF_MUL_COL
, GM_TXF_MUL_COL
},
316 { "aborted", XM_TXF_ABO_COL
, GM_TXF_ABO_COL
},
317 { "late_collision", XM_TXF_LAT_COL
, GM_TXF_LAT_COL
},
318 { "fifo_underrun", XM_TXE_FIFO_UR
, GM_TXE_FIFO_UR
},
319 { "fifo_overflow", XM_RXE_FIFO_OV
, GM_RXE_FIFO_OV
},
321 { "rx_toolong", XM_RXF_LNG_ERR
, GM_RXF_LNG_ERR
},
322 { "rx_jabber", XM_RXF_JAB_PKT
, GM_RXF_JAB_PKT
},
323 { "rx_runt", XM_RXE_RUNT
, GM_RXE_FRAG
},
324 { "rx_too_long", XM_RXF_LNG_ERR
, GM_RXF_LNG_ERR
},
325 { "rx_fcs_error", XM_RXF_FCS_ERR
, GM_RXF_FCS_ERR
},
328 static int skge_get_stats_count(struct net_device
*dev
)
330 return ARRAY_SIZE(skge_stats
);
333 static void skge_get_ethtool_stats(struct net_device
*dev
,
334 struct ethtool_stats
*stats
, u64
*data
)
336 struct skge_port
*skge
= netdev_priv(dev
);
338 if (skge
->hw
->chip_id
== CHIP_ID_GENESIS
)
339 genesis_get_stats(skge
, data
);
341 yukon_get_stats(skge
, data
);
344 /* Use hardware MIB variables for critical path statistics and
345 * transmit feedback not reported at interrupt.
346 * Other errors are accounted for in interrupt handler.
348 static struct net_device_stats
*skge_get_stats(struct net_device
*dev
)
350 struct skge_port
*skge
= netdev_priv(dev
);
351 u64 data
[ARRAY_SIZE(skge_stats
)];
353 if (skge
->hw
->chip_id
== CHIP_ID_GENESIS
)
354 genesis_get_stats(skge
, data
);
356 yukon_get_stats(skge
, data
);
358 skge
->net_stats
.tx_bytes
= data
[0];
359 skge
->net_stats
.rx_bytes
= data
[1];
360 skge
->net_stats
.tx_packets
= data
[2] + data
[4] + data
[6];
361 skge
->net_stats
.rx_packets
= data
[3] + data
[5] + data
[7];
362 skge
->net_stats
.multicast
= data
[3] + data
[5];
363 skge
->net_stats
.collisions
= data
[10];
364 skge
->net_stats
.tx_aborted_errors
= data
[12];
366 return &skge
->net_stats
;
369 static void skge_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
375 for (i
= 0; i
< ARRAY_SIZE(skge_stats
); i
++)
376 memcpy(data
+ i
* ETH_GSTRING_LEN
,
377 skge_stats
[i
].name
, ETH_GSTRING_LEN
);
382 static void skge_get_ring_param(struct net_device
*dev
,
383 struct ethtool_ringparam
*p
)
385 struct skge_port
*skge
= netdev_priv(dev
);
387 p
->rx_max_pending
= MAX_RX_RING_SIZE
;
388 p
->tx_max_pending
= MAX_TX_RING_SIZE
;
389 p
->rx_mini_max_pending
= 0;
390 p
->rx_jumbo_max_pending
= 0;
392 p
->rx_pending
= skge
->rx_ring
.count
;
393 p
->tx_pending
= skge
->tx_ring
.count
;
394 p
->rx_mini_pending
= 0;
395 p
->rx_jumbo_pending
= 0;
398 static int skge_set_ring_param(struct net_device
*dev
,
399 struct ethtool_ringparam
*p
)
401 struct skge_port
*skge
= netdev_priv(dev
);
404 if (p
->rx_pending
== 0 || p
->rx_pending
> MAX_RX_RING_SIZE
||
405 p
->tx_pending
< TX_LOW_WATER
|| p
->tx_pending
> MAX_TX_RING_SIZE
)
408 skge
->rx_ring
.count
= p
->rx_pending
;
409 skge
->tx_ring
.count
= p
->tx_pending
;
411 if (netif_running(dev
)) {
421 static u32
skge_get_msglevel(struct net_device
*netdev
)
423 struct skge_port
*skge
= netdev_priv(netdev
);
424 return skge
->msg_enable
;
427 static void skge_set_msglevel(struct net_device
*netdev
, u32 value
)
429 struct skge_port
*skge
= netdev_priv(netdev
);
430 skge
->msg_enable
= value
;
433 static int skge_nway_reset(struct net_device
*dev
)
435 struct skge_port
*skge
= netdev_priv(dev
);
437 if (skge
->autoneg
!= AUTONEG_ENABLE
|| !netif_running(dev
))
440 skge_phy_reset(skge
);
444 static int skge_set_sg(struct net_device
*dev
, u32 data
)
446 struct skge_port
*skge
= netdev_priv(dev
);
447 struct skge_hw
*hw
= skge
->hw
;
449 if (hw
->chip_id
== CHIP_ID_GENESIS
&& data
)
451 return ethtool_op_set_sg(dev
, data
);
454 static int skge_set_tx_csum(struct net_device
*dev
, u32 data
)
456 struct skge_port
*skge
= netdev_priv(dev
);
457 struct skge_hw
*hw
= skge
->hw
;
459 if (hw
->chip_id
== CHIP_ID_GENESIS
&& data
)
462 return ethtool_op_set_tx_csum(dev
, data
);
465 static u32
skge_get_rx_csum(struct net_device
*dev
)
467 struct skge_port
*skge
= netdev_priv(dev
);
469 return skge
->rx_csum
;
472 /* Only Yukon supports checksum offload. */
473 static int skge_set_rx_csum(struct net_device
*dev
, u32 data
)
475 struct skge_port
*skge
= netdev_priv(dev
);
477 if (skge
->hw
->chip_id
== CHIP_ID_GENESIS
&& data
)
480 skge
->rx_csum
= data
;
484 static void skge_get_pauseparam(struct net_device
*dev
,
485 struct ethtool_pauseparam
*ecmd
)
487 struct skge_port
*skge
= netdev_priv(dev
);
489 ecmd
->rx_pause
= (skge
->flow_control
== FLOW_MODE_SYMMETRIC
)
490 || (skge
->flow_control
== FLOW_MODE_SYM_OR_REM
);
491 ecmd
->tx_pause
= ecmd
->rx_pause
|| (skge
->flow_control
== FLOW_MODE_LOC_SEND
);
493 ecmd
->autoneg
= ecmd
->rx_pause
|| ecmd
->tx_pause
;
496 static int skge_set_pauseparam(struct net_device
*dev
,
497 struct ethtool_pauseparam
*ecmd
)
499 struct skge_port
*skge
= netdev_priv(dev
);
500 struct ethtool_pauseparam old
;
502 skge_get_pauseparam(dev
, &old
);
504 if (ecmd
->autoneg
!= old
.autoneg
)
505 skge
->flow_control
= ecmd
->autoneg
? FLOW_MODE_NONE
: FLOW_MODE_SYMMETRIC
;
507 if (ecmd
->rx_pause
&& ecmd
->tx_pause
)
508 skge
->flow_control
= FLOW_MODE_SYMMETRIC
;
509 else if (ecmd
->rx_pause
&& !ecmd
->tx_pause
)
510 skge
->flow_control
= FLOW_MODE_SYM_OR_REM
;
511 else if (!ecmd
->rx_pause
&& ecmd
->tx_pause
)
512 skge
->flow_control
= FLOW_MODE_LOC_SEND
;
514 skge
->flow_control
= FLOW_MODE_NONE
;
517 if (netif_running(dev
))
518 skge_phy_reset(skge
);
523 /* Chip internal frequency for clock calculations */
524 static inline u32
hwkhz(const struct skge_hw
*hw
)
526 return (hw
->chip_id
== CHIP_ID_GENESIS
) ? 53125 : 78125;
529 /* Chip HZ to microseconds */
530 static inline u32
skge_clk2usec(const struct skge_hw
*hw
, u32 ticks
)
532 return (ticks
* 1000) / hwkhz(hw
);
535 /* Microseconds to chip HZ */
536 static inline u32
skge_usecs2clk(const struct skge_hw
*hw
, u32 usec
)
538 return hwkhz(hw
) * usec
/ 1000;
541 static int skge_get_coalesce(struct net_device
*dev
,
542 struct ethtool_coalesce
*ecmd
)
544 struct skge_port
*skge
= netdev_priv(dev
);
545 struct skge_hw
*hw
= skge
->hw
;
546 int port
= skge
->port
;
548 ecmd
->rx_coalesce_usecs
= 0;
549 ecmd
->tx_coalesce_usecs
= 0;
551 if (skge_read32(hw
, B2_IRQM_CTRL
) & TIM_START
) {
552 u32 delay
= skge_clk2usec(hw
, skge_read32(hw
, B2_IRQM_INI
));
553 u32 msk
= skge_read32(hw
, B2_IRQM_MSK
);
555 if (msk
& rxirqmask
[port
])
556 ecmd
->rx_coalesce_usecs
= delay
;
557 if (msk
& txirqmask
[port
])
558 ecmd
->tx_coalesce_usecs
= delay
;
564 /* Note: interrupt timer is per board, but can turn on/off per port */
565 static int skge_set_coalesce(struct net_device
*dev
,
566 struct ethtool_coalesce
*ecmd
)
568 struct skge_port
*skge
= netdev_priv(dev
);
569 struct skge_hw
*hw
= skge
->hw
;
570 int port
= skge
->port
;
571 u32 msk
= skge_read32(hw
, B2_IRQM_MSK
);
574 if (ecmd
->rx_coalesce_usecs
== 0)
575 msk
&= ~rxirqmask
[port
];
576 else if (ecmd
->rx_coalesce_usecs
< 25 ||
577 ecmd
->rx_coalesce_usecs
> 33333)
580 msk
|= rxirqmask
[port
];
581 delay
= ecmd
->rx_coalesce_usecs
;
584 if (ecmd
->tx_coalesce_usecs
== 0)
585 msk
&= ~txirqmask
[port
];
586 else if (ecmd
->tx_coalesce_usecs
< 25 ||
587 ecmd
->tx_coalesce_usecs
> 33333)
590 msk
|= txirqmask
[port
];
591 delay
= min(delay
, ecmd
->rx_coalesce_usecs
);
594 skge_write32(hw
, B2_IRQM_MSK
, msk
);
596 skge_write32(hw
, B2_IRQM_CTRL
, TIM_STOP
);
598 skge_write32(hw
, B2_IRQM_INI
, skge_usecs2clk(hw
, delay
));
599 skge_write32(hw
, B2_IRQM_CTRL
, TIM_START
);
604 enum led_mode
{ LED_MODE_OFF
, LED_MODE_ON
, LED_MODE_TST
};
605 static void skge_led(struct skge_port
*skge
, enum led_mode mode
)
607 struct skge_hw
*hw
= skge
->hw
;
608 int port
= skge
->port
;
610 mutex_lock(&hw
->phy_mutex
);
611 if (hw
->chip_id
== CHIP_ID_GENESIS
) {
614 if (hw
->phy_type
== SK_PHY_BCOM
)
615 xm_phy_write(hw
, port
, PHY_BCOM_P_EXT_CTRL
, PHY_B_PEC_LED_OFF
);
617 skge_write32(hw
, SK_REG(port
, TX_LED_VAL
), 0);
618 skge_write8(hw
, SK_REG(port
, TX_LED_CTRL
), LED_T_OFF
);
620 skge_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_OFF
);
621 skge_write32(hw
, SK_REG(port
, RX_LED_VAL
), 0);
622 skge_write8(hw
, SK_REG(port
, RX_LED_CTRL
), LED_T_OFF
);
626 skge_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_ON
);
627 skge_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_LINKSYNC_ON
);
629 skge_write8(hw
, SK_REG(port
, RX_LED_CTRL
), LED_START
);
630 skge_write8(hw
, SK_REG(port
, TX_LED_CTRL
), LED_START
);
635 skge_write8(hw
, SK_REG(port
, RX_LED_TST
), LED_T_ON
);
636 skge_write32(hw
, SK_REG(port
, RX_LED_VAL
), 100);
637 skge_write8(hw
, SK_REG(port
, RX_LED_CTRL
), LED_START
);
639 if (hw
->phy_type
== SK_PHY_BCOM
)
640 xm_phy_write(hw
, port
, PHY_BCOM_P_EXT_CTRL
, PHY_B_PEC_LED_ON
);
642 skge_write8(hw
, SK_REG(port
, TX_LED_TST
), LED_T_ON
);
643 skge_write32(hw
, SK_REG(port
, TX_LED_VAL
), 100);
644 skge_write8(hw
, SK_REG(port
, TX_LED_CTRL
), LED_START
);
651 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, 0);
652 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
653 PHY_M_LED_MO_DUP(MO_LED_OFF
) |
654 PHY_M_LED_MO_10(MO_LED_OFF
) |
655 PHY_M_LED_MO_100(MO_LED_OFF
) |
656 PHY_M_LED_MO_1000(MO_LED_OFF
) |
657 PHY_M_LED_MO_RX(MO_LED_OFF
));
660 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
,
661 PHY_M_LED_PULS_DUR(PULS_170MS
) |
662 PHY_M_LED_BLINK_RT(BLINK_84MS
) |
666 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
667 PHY_M_LED_MO_RX(MO_LED_OFF
) |
668 (skge
->speed
== SPEED_100
?
669 PHY_M_LED_MO_100(MO_LED_ON
) : 0));
672 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, 0);
673 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
674 PHY_M_LED_MO_DUP(MO_LED_ON
) |
675 PHY_M_LED_MO_10(MO_LED_ON
) |
676 PHY_M_LED_MO_100(MO_LED_ON
) |
677 PHY_M_LED_MO_1000(MO_LED_ON
) |
678 PHY_M_LED_MO_RX(MO_LED_ON
));
681 mutex_unlock(&hw
->phy_mutex
);
684 /* blink LED's for finding board */
685 static int skge_phys_id(struct net_device
*dev
, u32 data
)
687 struct skge_port
*skge
= netdev_priv(dev
);
689 enum led_mode mode
= LED_MODE_TST
;
691 if (!data
|| data
> (u32
)(MAX_SCHEDULE_TIMEOUT
/ HZ
))
692 ms
= jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT
/ HZ
) * 1000;
697 skge_led(skge
, mode
);
698 mode
^= LED_MODE_TST
;
700 if (msleep_interruptible(BLINK_MS
))
705 /* back to regular LED state */
706 skge_led(skge
, netif_running(dev
) ? LED_MODE_ON
: LED_MODE_OFF
);
711 static const struct ethtool_ops skge_ethtool_ops
= {
712 .get_settings
= skge_get_settings
,
713 .set_settings
= skge_set_settings
,
714 .get_drvinfo
= skge_get_drvinfo
,
715 .get_regs_len
= skge_get_regs_len
,
716 .get_regs
= skge_get_regs
,
717 .get_wol
= skge_get_wol
,
718 .set_wol
= skge_set_wol
,
719 .get_msglevel
= skge_get_msglevel
,
720 .set_msglevel
= skge_set_msglevel
,
721 .nway_reset
= skge_nway_reset
,
722 .get_link
= ethtool_op_get_link
,
723 .get_ringparam
= skge_get_ring_param
,
724 .set_ringparam
= skge_set_ring_param
,
725 .get_pauseparam
= skge_get_pauseparam
,
726 .set_pauseparam
= skge_set_pauseparam
,
727 .get_coalesce
= skge_get_coalesce
,
728 .set_coalesce
= skge_set_coalesce
,
729 .get_sg
= ethtool_op_get_sg
,
730 .set_sg
= skge_set_sg
,
731 .get_tx_csum
= ethtool_op_get_tx_csum
,
732 .set_tx_csum
= skge_set_tx_csum
,
733 .get_rx_csum
= skge_get_rx_csum
,
734 .set_rx_csum
= skge_set_rx_csum
,
735 .get_strings
= skge_get_strings
,
736 .phys_id
= skge_phys_id
,
737 .get_stats_count
= skge_get_stats_count
,
738 .get_ethtool_stats
= skge_get_ethtool_stats
,
739 .get_perm_addr
= ethtool_op_get_perm_addr
,
743 * Allocate ring elements and chain them together
744 * One-to-one association of board descriptors with ring elements
746 static int skge_ring_alloc(struct skge_ring
*ring
, void *vaddr
, u32 base
)
748 struct skge_tx_desc
*d
;
749 struct skge_element
*e
;
752 ring
->start
= kcalloc(sizeof(*e
), ring
->count
, GFP_KERNEL
);
756 for (i
= 0, e
= ring
->start
, d
= vaddr
; i
< ring
->count
; i
++, e
++, d
++) {
758 if (i
== ring
->count
- 1) {
759 e
->next
= ring
->start
;
760 d
->next_offset
= base
;
763 d
->next_offset
= base
+ (i
+1) * sizeof(*d
);
766 ring
->to_use
= ring
->to_clean
= ring
->start
;
771 /* Allocate and setup a new buffer for receiving */
772 static void skge_rx_setup(struct skge_port
*skge
, struct skge_element
*e
,
773 struct sk_buff
*skb
, unsigned int bufsize
)
775 struct skge_rx_desc
*rd
= e
->desc
;
778 map
= pci_map_single(skge
->hw
->pdev
, skb
->data
, bufsize
,
782 rd
->dma_hi
= map
>> 32;
784 rd
->csum1_start
= ETH_HLEN
;
785 rd
->csum2_start
= ETH_HLEN
;
791 rd
->control
= BMU_OWN
| BMU_STF
| BMU_IRQ_EOF
| BMU_TCP_CHECK
| bufsize
;
792 pci_unmap_addr_set(e
, mapaddr
, map
);
793 pci_unmap_len_set(e
, maplen
, bufsize
);
796 /* Resume receiving using existing skb,
797 * Note: DMA address is not changed by chip.
798 * MTU not changed while receiver active.
800 static inline void skge_rx_reuse(struct skge_element
*e
, unsigned int size
)
802 struct skge_rx_desc
*rd
= e
->desc
;
805 rd
->csum2_start
= ETH_HLEN
;
809 rd
->control
= BMU_OWN
| BMU_STF
| BMU_IRQ_EOF
| BMU_TCP_CHECK
| size
;
813 /* Free all buffers in receive ring, assumes receiver stopped */
814 static void skge_rx_clean(struct skge_port
*skge
)
816 struct skge_hw
*hw
= skge
->hw
;
817 struct skge_ring
*ring
= &skge
->rx_ring
;
818 struct skge_element
*e
;
822 struct skge_rx_desc
*rd
= e
->desc
;
825 pci_unmap_single(hw
->pdev
,
826 pci_unmap_addr(e
, mapaddr
),
827 pci_unmap_len(e
, maplen
),
829 dev_kfree_skb(e
->skb
);
832 } while ((e
= e
->next
) != ring
->start
);
836 /* Allocate buffers for receive ring
837 * For receive: to_clean is next received frame.
839 static int skge_rx_fill(struct net_device
*dev
)
841 struct skge_port
*skge
= netdev_priv(dev
);
842 struct skge_ring
*ring
= &skge
->rx_ring
;
843 struct skge_element
*e
;
849 skb
= __netdev_alloc_skb(dev
, skge
->rx_buf_size
+ NET_IP_ALIGN
,
854 skb_reserve(skb
, NET_IP_ALIGN
);
855 skge_rx_setup(skge
, e
, skb
, skge
->rx_buf_size
);
856 } while ( (e
= e
->next
) != ring
->start
);
858 ring
->to_clean
= ring
->start
;
862 static const char *skge_pause(enum pause_status status
)
867 case FLOW_STAT_REM_SEND
:
869 case FLOW_STAT_LOC_SEND
:
871 case FLOW_STAT_SYMMETRIC
: /* Both station may send PAUSE */
874 return "indeterminated";
879 static void skge_link_up(struct skge_port
*skge
)
881 skge_write8(skge
->hw
, SK_REG(skge
->port
, LNK_LED_REG
),
882 LED_BLK_OFF
|LED_SYNC_OFF
|LED_ON
);
884 netif_carrier_on(skge
->netdev
);
885 netif_wake_queue(skge
->netdev
);
887 if (netif_msg_link(skge
)) {
889 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
890 skge
->netdev
->name
, skge
->speed
,
891 skge
->duplex
== DUPLEX_FULL
? "full" : "half",
892 skge_pause(skge
->flow_status
));
896 static void skge_link_down(struct skge_port
*skge
)
898 skge_write8(skge
->hw
, SK_REG(skge
->port
, LNK_LED_REG
), LED_OFF
);
899 netif_carrier_off(skge
->netdev
);
900 netif_stop_queue(skge
->netdev
);
902 if (netif_msg_link(skge
))
903 printk(KERN_INFO PFX
"%s: Link is down.\n", skge
->netdev
->name
);
907 static void xm_link_down(struct skge_hw
*hw
, int port
)
909 struct net_device
*dev
= hw
->dev
[port
];
910 struct skge_port
*skge
= netdev_priv(dev
);
913 if (hw
->phy_type
== SK_PHY_XMAC
) {
914 msk
= xm_read16(hw
, port
, XM_IMSK
);
915 msk
|= XM_IS_INP_ASS
| XM_IS_LIPA_RC
| XM_IS_RX_PAGE
| XM_IS_AND
;
916 xm_write16(hw
, port
, XM_IMSK
, msk
);
919 cmd
= xm_read16(hw
, port
, XM_MMU_CMD
);
920 cmd
&= ~(XM_MMU_ENA_RX
| XM_MMU_ENA_TX
);
921 xm_write16(hw
, port
, XM_MMU_CMD
, cmd
);
922 /* dummy read to ensure writing */
923 (void) xm_read16(hw
, port
, XM_MMU_CMD
);
925 if (netif_carrier_ok(dev
))
926 skge_link_down(skge
);
929 static int __xm_phy_read(struct skge_hw
*hw
, int port
, u16 reg
, u16
*val
)
933 xm_write16(hw
, port
, XM_PHY_ADDR
, reg
| hw
->phy_addr
);
934 *val
= xm_read16(hw
, port
, XM_PHY_DATA
);
936 if (hw
->phy_type
== SK_PHY_XMAC
)
939 for (i
= 0; i
< PHY_RETRIES
; i
++) {
940 if (xm_read16(hw
, port
, XM_MMU_CMD
) & XM_MMU_PHY_RDY
)
947 *val
= xm_read16(hw
, port
, XM_PHY_DATA
);
952 static u16
xm_phy_read(struct skge_hw
*hw
, int port
, u16 reg
)
955 if (__xm_phy_read(hw
, port
, reg
, &v
))
956 printk(KERN_WARNING PFX
"%s: phy read timed out\n",
957 hw
->dev
[port
]->name
);
961 static int xm_phy_write(struct skge_hw
*hw
, int port
, u16 reg
, u16 val
)
965 xm_write16(hw
, port
, XM_PHY_ADDR
, reg
| hw
->phy_addr
);
966 for (i
= 0; i
< PHY_RETRIES
; i
++) {
967 if (!(xm_read16(hw
, port
, XM_MMU_CMD
) & XM_MMU_PHY_BUSY
))
974 xm_write16(hw
, port
, XM_PHY_DATA
, val
);
975 for (i
= 0; i
< PHY_RETRIES
; i
++) {
976 if (!(xm_read16(hw
, port
, XM_MMU_CMD
) & XM_MMU_PHY_BUSY
))
983 static void genesis_init(struct skge_hw
*hw
)
985 /* set blink source counter */
986 skge_write32(hw
, B2_BSC_INI
, (SK_BLK_DUR
* SK_FACT_53
) / 100);
987 skge_write8(hw
, B2_BSC_CTRL
, BSC_START
);
989 /* configure mac arbiter */
990 skge_write16(hw
, B3_MA_TO_CTRL
, MA_RST_CLR
);
992 /* configure mac arbiter timeout values */
993 skge_write8(hw
, B3_MA_TOINI_RX1
, SK_MAC_TO_53
);
994 skge_write8(hw
, B3_MA_TOINI_RX2
, SK_MAC_TO_53
);
995 skge_write8(hw
, B3_MA_TOINI_TX1
, SK_MAC_TO_53
);
996 skge_write8(hw
, B3_MA_TOINI_TX2
, SK_MAC_TO_53
);
998 skge_write8(hw
, B3_MA_RCINI_RX1
, 0);
999 skge_write8(hw
, B3_MA_RCINI_RX2
, 0);
1000 skge_write8(hw
, B3_MA_RCINI_TX1
, 0);
1001 skge_write8(hw
, B3_MA_RCINI_TX2
, 0);
1003 /* configure packet arbiter timeout */
1004 skge_write16(hw
, B3_PA_CTRL
, PA_RST_CLR
);
1005 skge_write16(hw
, B3_PA_TOINI_RX1
, SK_PKT_TO_MAX
);
1006 skge_write16(hw
, B3_PA_TOINI_TX1
, SK_PKT_TO_MAX
);
1007 skge_write16(hw
, B3_PA_TOINI_RX2
, SK_PKT_TO_MAX
);
1008 skge_write16(hw
, B3_PA_TOINI_TX2
, SK_PKT_TO_MAX
);
1011 static void genesis_reset(struct skge_hw
*hw
, int port
)
1013 const u8 zero
[8] = { 0 };
1015 skge_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
1017 /* reset the statistics module */
1018 xm_write32(hw
, port
, XM_GP_PORT
, XM_GP_RES_STAT
);
1019 xm_write16(hw
, port
, XM_IMSK
, 0xffff); /* disable XMAC IRQs */
1020 xm_write32(hw
, port
, XM_MODE
, 0); /* clear Mode Reg */
1021 xm_write16(hw
, port
, XM_TX_CMD
, 0); /* reset TX CMD Reg */
1022 xm_write16(hw
, port
, XM_RX_CMD
, 0); /* reset RX CMD Reg */
1024 /* disable Broadcom PHY IRQ */
1025 if (hw
->phy_type
== SK_PHY_BCOM
)
1026 xm_write16(hw
, port
, PHY_BCOM_INT_MASK
, 0xffff);
1028 xm_outhash(hw
, port
, XM_HSM
, zero
);
1032 /* Convert mode to MII values */
1033 static const u16 phy_pause_map
[] = {
1034 [FLOW_MODE_NONE
] = 0,
1035 [FLOW_MODE_LOC_SEND
] = PHY_AN_PAUSE_ASYM
,
1036 [FLOW_MODE_SYMMETRIC
] = PHY_AN_PAUSE_CAP
,
1037 [FLOW_MODE_SYM_OR_REM
] = PHY_AN_PAUSE_CAP
| PHY_AN_PAUSE_ASYM
,
1040 /* special defines for FIBER (88E1011S only) */
1041 static const u16 fiber_pause_map
[] = {
1042 [FLOW_MODE_NONE
] = PHY_X_P_NO_PAUSE
,
1043 [FLOW_MODE_LOC_SEND
] = PHY_X_P_ASYM_MD
,
1044 [FLOW_MODE_SYMMETRIC
] = PHY_X_P_SYM_MD
,
1045 [FLOW_MODE_SYM_OR_REM
] = PHY_X_P_BOTH_MD
,
1049 /* Check status of Broadcom phy link */
1050 static void bcom_check_link(struct skge_hw
*hw
, int port
)
1052 struct net_device
*dev
= hw
->dev
[port
];
1053 struct skge_port
*skge
= netdev_priv(dev
);
1056 /* read twice because of latch */
1057 (void) xm_phy_read(hw
, port
, PHY_BCOM_STAT
);
1058 status
= xm_phy_read(hw
, port
, PHY_BCOM_STAT
);
1060 if ((status
& PHY_ST_LSYNC
) == 0) {
1061 xm_link_down(hw
, port
);
1065 if (skge
->autoneg
== AUTONEG_ENABLE
) {
1068 if (!(status
& PHY_ST_AN_OVER
))
1071 lpa
= xm_phy_read(hw
, port
, PHY_XMAC_AUNE_LP
);
1072 if (lpa
& PHY_B_AN_RF
) {
1073 printk(KERN_NOTICE PFX
"%s: remote fault\n",
1078 aux
= xm_phy_read(hw
, port
, PHY_BCOM_AUX_STAT
);
1080 /* Check Duplex mismatch */
1081 switch (aux
& PHY_B_AS_AN_RES_MSK
) {
1082 case PHY_B_RES_1000FD
:
1083 skge
->duplex
= DUPLEX_FULL
;
1085 case PHY_B_RES_1000HD
:
1086 skge
->duplex
= DUPLEX_HALF
;
1089 printk(KERN_NOTICE PFX
"%s: duplex mismatch\n",
1094 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1095 switch (aux
& PHY_B_AS_PAUSE_MSK
) {
1096 case PHY_B_AS_PAUSE_MSK
:
1097 skge
->flow_status
= FLOW_STAT_SYMMETRIC
;
1100 skge
->flow_status
= FLOW_STAT_REM_SEND
;
1103 skge
->flow_status
= FLOW_STAT_LOC_SEND
;
1106 skge
->flow_status
= FLOW_STAT_NONE
;
1108 skge
->speed
= SPEED_1000
;
1111 if (!netif_carrier_ok(dev
))
1112 genesis_link_up(skge
);
1115 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1116 * Phy on for 100 or 10Mbit operation
1118 static void bcom_phy_init(struct skge_port
*skge
)
1120 struct skge_hw
*hw
= skge
->hw
;
1121 int port
= skge
->port
;
1123 u16 id1
, r
, ext
, ctl
;
1125 /* magic workaround patterns for Broadcom */
1126 static const struct {
1130 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1131 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1132 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1133 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1135 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1136 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1139 /* read Id from external PHY (all have the same address) */
1140 id1
= xm_phy_read(hw
, port
, PHY_XMAC_ID1
);
1142 /* Optimize MDIO transfer by suppressing preamble. */
1143 r
= xm_read16(hw
, port
, XM_MMU_CMD
);
1145 xm_write16(hw
, port
, XM_MMU_CMD
,r
);
1148 case PHY_BCOM_ID1_C0
:
1150 * Workaround BCOM Errata for the C0 type.
1151 * Write magic patterns to reserved registers.
1153 for (i
= 0; i
< ARRAY_SIZE(C0hack
); i
++)
1154 xm_phy_write(hw
, port
,
1155 C0hack
[i
].reg
, C0hack
[i
].val
);
1158 case PHY_BCOM_ID1_A1
:
1160 * Workaround BCOM Errata for the A1 type.
1161 * Write magic patterns to reserved registers.
1163 for (i
= 0; i
< ARRAY_SIZE(A1hack
); i
++)
1164 xm_phy_write(hw
, port
,
1165 A1hack
[i
].reg
, A1hack
[i
].val
);
1170 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1171 * Disable Power Management after reset.
1173 r
= xm_phy_read(hw
, port
, PHY_BCOM_AUX_CTRL
);
1174 r
|= PHY_B_AC_DIS_PM
;
1175 xm_phy_write(hw
, port
, PHY_BCOM_AUX_CTRL
, r
);
1178 xm_read16(hw
, port
, XM_ISRC
);
1180 ext
= PHY_B_PEC_EN_LTR
; /* enable tx led */
1181 ctl
= PHY_CT_SP1000
; /* always 1000mbit */
1183 if (skge
->autoneg
== AUTONEG_ENABLE
) {
1185 * Workaround BCOM Errata #1 for the C5 type.
1186 * 1000Base-T Link Acquisition Failure in Slave Mode
1187 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1189 u16 adv
= PHY_B_1000C_RD
;
1190 if (skge
->advertising
& ADVERTISED_1000baseT_Half
)
1191 adv
|= PHY_B_1000C_AHD
;
1192 if (skge
->advertising
& ADVERTISED_1000baseT_Full
)
1193 adv
|= PHY_B_1000C_AFD
;
1194 xm_phy_write(hw
, port
, PHY_BCOM_1000T_CTRL
, adv
);
1196 ctl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
1198 if (skge
->duplex
== DUPLEX_FULL
)
1199 ctl
|= PHY_CT_DUP_MD
;
1200 /* Force to slave */
1201 xm_phy_write(hw
, port
, PHY_BCOM_1000T_CTRL
, PHY_B_1000C_MSE
);
1204 /* Set autonegotiation pause parameters */
1205 xm_phy_write(hw
, port
, PHY_BCOM_AUNE_ADV
,
1206 phy_pause_map
[skge
->flow_control
] | PHY_AN_CSMA
);
1208 /* Handle Jumbo frames */
1209 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
) {
1210 xm_phy_write(hw
, port
, PHY_BCOM_AUX_CTRL
,
1211 PHY_B_AC_TX_TST
| PHY_B_AC_LONG_PACK
);
1213 ext
|= PHY_B_PEC_HIGH_LA
;
1217 xm_phy_write(hw
, port
, PHY_BCOM_P_EXT_CTRL
, ext
);
1218 xm_phy_write(hw
, port
, PHY_BCOM_CTRL
, ctl
);
1220 /* Use link status change interrupt */
1221 xm_phy_write(hw
, port
, PHY_BCOM_INT_MASK
, PHY_B_DEF_MSK
);
1224 static void xm_phy_init(struct skge_port
*skge
)
1226 struct skge_hw
*hw
= skge
->hw
;
1227 int port
= skge
->port
;
1230 if (skge
->autoneg
== AUTONEG_ENABLE
) {
1231 if (skge
->advertising
& ADVERTISED_1000baseT_Half
)
1232 ctrl
|= PHY_X_AN_HD
;
1233 if (skge
->advertising
& ADVERTISED_1000baseT_Full
)
1234 ctrl
|= PHY_X_AN_FD
;
1236 ctrl
|= fiber_pause_map
[skge
->flow_control
];
1238 xm_phy_write(hw
, port
, PHY_XMAC_AUNE_ADV
, ctrl
);
1240 /* Restart Auto-negotiation */
1241 ctrl
= PHY_CT_ANE
| PHY_CT_RE_CFG
;
1243 /* Set DuplexMode in Config register */
1244 if (skge
->duplex
== DUPLEX_FULL
)
1245 ctrl
|= PHY_CT_DUP_MD
;
1247 * Do NOT enable Auto-negotiation here. This would hold
1248 * the link down because no IDLEs are transmitted
1252 xm_phy_write(hw
, port
, PHY_XMAC_CTRL
, ctrl
);
1254 /* Poll PHY for status changes */
1255 schedule_delayed_work(&skge
->link_thread
, LINK_HZ
);
1258 static void xm_check_link(struct net_device
*dev
)
1260 struct skge_port
*skge
= netdev_priv(dev
);
1261 struct skge_hw
*hw
= skge
->hw
;
1262 int port
= skge
->port
;
1265 /* read twice because of latch */
1266 (void) xm_phy_read(hw
, port
, PHY_XMAC_STAT
);
1267 status
= xm_phy_read(hw
, port
, PHY_XMAC_STAT
);
1269 if ((status
& PHY_ST_LSYNC
) == 0) {
1270 xm_link_down(hw
, port
);
1274 if (skge
->autoneg
== AUTONEG_ENABLE
) {
1277 if (!(status
& PHY_ST_AN_OVER
))
1280 lpa
= xm_phy_read(hw
, port
, PHY_XMAC_AUNE_LP
);
1281 if (lpa
& PHY_B_AN_RF
) {
1282 printk(KERN_NOTICE PFX
"%s: remote fault\n",
1287 res
= xm_phy_read(hw
, port
, PHY_XMAC_RES_ABI
);
1289 /* Check Duplex mismatch */
1290 switch (res
& (PHY_X_RS_HD
| PHY_X_RS_FD
)) {
1292 skge
->duplex
= DUPLEX_FULL
;
1295 skge
->duplex
= DUPLEX_HALF
;
1298 printk(KERN_NOTICE PFX
"%s: duplex mismatch\n",
1303 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1304 if ((skge
->flow_control
== FLOW_MODE_SYMMETRIC
||
1305 skge
->flow_control
== FLOW_MODE_SYM_OR_REM
) &&
1306 (lpa
& PHY_X_P_SYM_MD
))
1307 skge
->flow_status
= FLOW_STAT_SYMMETRIC
;
1308 else if (skge
->flow_control
== FLOW_MODE_SYM_OR_REM
&&
1309 (lpa
& PHY_X_RS_PAUSE
) == PHY_X_P_ASYM_MD
)
1310 /* Enable PAUSE receive, disable PAUSE transmit */
1311 skge
->flow_status
= FLOW_STAT_REM_SEND
;
1312 else if (skge
->flow_control
== FLOW_MODE_LOC_SEND
&&
1313 (lpa
& PHY_X_RS_PAUSE
) == PHY_X_P_BOTH_MD
)
1314 /* Disable PAUSE receive, enable PAUSE transmit */
1315 skge
->flow_status
= FLOW_STAT_LOC_SEND
;
1317 skge
->flow_status
= FLOW_STAT_NONE
;
1319 skge
->speed
= SPEED_1000
;
1322 if (!netif_carrier_ok(dev
))
1323 genesis_link_up(skge
);
1326 /* Poll to check for link coming up.
1327 * Since internal PHY is wired to a level triggered pin, can't
1328 * get an interrupt when carrier is detected.
1330 static void xm_link_timer(void *arg
)
1332 struct net_device
*dev
= arg
;
1333 struct skge_port
*skge
= netdev_priv(arg
);
1334 struct skge_hw
*hw
= skge
->hw
;
1335 int port
= skge
->port
;
1337 if (!netif_running(dev
))
1340 if (netif_carrier_ok(dev
)) {
1341 xm_read16(hw
, port
, XM_ISRC
);
1342 if (!(xm_read16(hw
, port
, XM_ISRC
) & XM_IS_INP_ASS
))
1345 if (xm_read32(hw
, port
, XM_GP_PORT
) & XM_GP_INP_ASS
)
1347 xm_read16(hw
, port
, XM_ISRC
);
1348 if (xm_read16(hw
, port
, XM_ISRC
) & XM_IS_INP_ASS
)
1352 mutex_lock(&hw
->phy_mutex
);
1354 mutex_unlock(&hw
->phy_mutex
);
1357 schedule_delayed_work(&skge
->link_thread
, LINK_HZ
);
1360 static void genesis_mac_init(struct skge_hw
*hw
, int port
)
1362 struct net_device
*dev
= hw
->dev
[port
];
1363 struct skge_port
*skge
= netdev_priv(dev
);
1364 int jumbo
= hw
->dev
[port
]->mtu
> ETH_DATA_LEN
;
1367 const u8 zero
[6] = { 0 };
1369 for (i
= 0; i
< 10; i
++) {
1370 skge_write16(hw
, SK_REG(port
, TX_MFF_CTRL1
),
1372 if (skge_read16(hw
, SK_REG(port
, TX_MFF_CTRL1
)) & MFF_SET_MAC_RST
)
1377 printk(KERN_WARNING PFX
"%s: genesis reset failed\n", dev
->name
);
1380 /* Unreset the XMAC. */
1381 skge_write16(hw
, SK_REG(port
, TX_MFF_CTRL1
), MFF_CLR_MAC_RST
);
1384 * Perform additional initialization for external PHYs,
1385 * namely for the 1000baseTX cards that use the XMAC's
1388 if (hw
->phy_type
!= SK_PHY_XMAC
) {
1389 /* Take external Phy out of reset */
1390 r
= skge_read32(hw
, B2_GP_IO
);
1392 r
|= GP_DIR_0
|GP_IO_0
;
1394 r
|= GP_DIR_2
|GP_IO_2
;
1396 skge_write32(hw
, B2_GP_IO
, r
);
1398 /* Enable GMII interface */
1399 xm_write16(hw
, port
, XM_HW_CFG
, XM_HW_GMII_MD
);
1403 switch(hw
->phy_type
) {
1408 bcom_phy_init(skge
);
1409 bcom_check_link(hw
, port
);
1412 /* Set Station Address */
1413 xm_outaddr(hw
, port
, XM_SA
, dev
->dev_addr
);
1415 /* We don't use match addresses so clear */
1416 for (i
= 1; i
< 16; i
++)
1417 xm_outaddr(hw
, port
, XM_EXM(i
), zero
);
1419 /* Clear MIB counters */
1420 xm_write16(hw
, port
, XM_STAT_CMD
,
1421 XM_SC_CLR_RXC
| XM_SC_CLR_TXC
);
1422 /* Clear two times according to Errata #3 */
1423 xm_write16(hw
, port
, XM_STAT_CMD
,
1424 XM_SC_CLR_RXC
| XM_SC_CLR_TXC
);
1426 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1427 xm_write16(hw
, port
, XM_RX_HI_WM
, 1450);
1429 /* We don't need the FCS appended to the packet. */
1430 r
= XM_RX_LENERR_OK
| XM_RX_STRIP_FCS
;
1432 r
|= XM_RX_BIG_PK_OK
;
1434 if (skge
->duplex
== DUPLEX_HALF
) {
1436 * If in manual half duplex mode the other side might be in
1437 * full duplex mode, so ignore if a carrier extension is not seen
1438 * on frames received
1440 r
|= XM_RX_DIS_CEXT
;
1442 xm_write16(hw
, port
, XM_RX_CMD
, r
);
1445 /* We want short frames padded to 60 bytes. */
1446 xm_write16(hw
, port
, XM_TX_CMD
, XM_TX_AUTO_PAD
);
1449 * Bump up the transmit threshold. This helps hold off transmit
1450 * underruns when we're blasting traffic from both ports at once.
1452 xm_write16(hw
, port
, XM_TX_THR
, 512);
1455 * Enable the reception of all error frames. This is is
1456 * a necessary evil due to the design of the XMAC. The
1457 * XMAC's receive FIFO is only 8K in size, however jumbo
1458 * frames can be up to 9000 bytes in length. When bad
1459 * frame filtering is enabled, the XMAC's RX FIFO operates
1460 * in 'store and forward' mode. For this to work, the
1461 * entire frame has to fit into the FIFO, but that means
1462 * that jumbo frames larger than 8192 bytes will be
1463 * truncated. Disabling all bad frame filtering causes
1464 * the RX FIFO to operate in streaming mode, in which
1465 * case the XMAC will start transferring frames out of the
1466 * RX FIFO as soon as the FIFO threshold is reached.
1468 xm_write32(hw
, port
, XM_MODE
, XM_DEF_MODE
);
1472 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1473 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1474 * and 'Octets Rx OK Hi Cnt Ov'.
1476 xm_write32(hw
, port
, XM_RX_EV_MSK
, XMR_DEF_MSK
);
1479 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1480 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1481 * and 'Octets Tx OK Hi Cnt Ov'.
1483 xm_write32(hw
, port
, XM_TX_EV_MSK
, XMT_DEF_MSK
);
1485 /* Configure MAC arbiter */
1486 skge_write16(hw
, B3_MA_TO_CTRL
, MA_RST_CLR
);
1488 /* configure timeout values */
1489 skge_write8(hw
, B3_MA_TOINI_RX1
, 72);
1490 skge_write8(hw
, B3_MA_TOINI_RX2
, 72);
1491 skge_write8(hw
, B3_MA_TOINI_TX1
, 72);
1492 skge_write8(hw
, B3_MA_TOINI_TX2
, 72);
1494 skge_write8(hw
, B3_MA_RCINI_RX1
, 0);
1495 skge_write8(hw
, B3_MA_RCINI_RX2
, 0);
1496 skge_write8(hw
, B3_MA_RCINI_TX1
, 0);
1497 skge_write8(hw
, B3_MA_RCINI_TX2
, 0);
1499 /* Configure Rx MAC FIFO */
1500 skge_write8(hw
, SK_REG(port
, RX_MFF_CTRL2
), MFF_RST_CLR
);
1501 skge_write16(hw
, SK_REG(port
, RX_MFF_CTRL1
), MFF_ENA_TIM_PAT
);
1502 skge_write8(hw
, SK_REG(port
, RX_MFF_CTRL2
), MFF_ENA_OP_MD
);
1504 /* Configure Tx MAC FIFO */
1505 skge_write8(hw
, SK_REG(port
, TX_MFF_CTRL2
), MFF_RST_CLR
);
1506 skge_write16(hw
, SK_REG(port
, TX_MFF_CTRL1
), MFF_TX_CTRL_DEF
);
1507 skge_write8(hw
, SK_REG(port
, TX_MFF_CTRL2
), MFF_ENA_OP_MD
);
1510 /* Enable frame flushing if jumbo frames used */
1511 skge_write16(hw
, SK_REG(port
,RX_MFF_CTRL1
), MFF_ENA_FLUSH
);
1513 /* enable timeout timers if normal frames */
1514 skge_write16(hw
, B3_PA_CTRL
,
1515 (port
== 0) ? PA_ENA_TO_TX1
: PA_ENA_TO_TX2
);
1519 static void genesis_stop(struct skge_port
*skge
)
1521 struct skge_hw
*hw
= skge
->hw
;
1522 int port
= skge
->port
;
1525 genesis_reset(hw
, port
);
1527 /* Clear Tx packet arbiter timeout IRQ */
1528 skge_write16(hw
, B3_PA_CTRL
,
1529 port
== 0 ? PA_CLR_TO_TX1
: PA_CLR_TO_TX2
);
1532 * If the transfer sticks at the MAC the STOP command will not
1533 * terminate if we don't flush the XMAC's transmit FIFO !
1535 xm_write32(hw
, port
, XM_MODE
,
1536 xm_read32(hw
, port
, XM_MODE
)|XM_MD_FTF
);
1540 skge_write16(hw
, SK_REG(port
, TX_MFF_CTRL1
), MFF_SET_MAC_RST
);
1542 /* For external PHYs there must be special handling */
1543 if (hw
->phy_type
!= SK_PHY_XMAC
) {
1544 reg
= skge_read32(hw
, B2_GP_IO
);
1552 skge_write32(hw
, B2_GP_IO
, reg
);
1553 skge_read32(hw
, B2_GP_IO
);
1556 xm_write16(hw
, port
, XM_MMU_CMD
,
1557 xm_read16(hw
, port
, XM_MMU_CMD
)
1558 & ~(XM_MMU_ENA_RX
| XM_MMU_ENA_TX
));
1560 xm_read16(hw
, port
, XM_MMU_CMD
);
1564 static void genesis_get_stats(struct skge_port
*skge
, u64
*data
)
1566 struct skge_hw
*hw
= skge
->hw
;
1567 int port
= skge
->port
;
1569 unsigned long timeout
= jiffies
+ HZ
;
1571 xm_write16(hw
, port
,
1572 XM_STAT_CMD
, XM_SC_SNP_TXC
| XM_SC_SNP_RXC
);
1574 /* wait for update to complete */
1575 while (xm_read16(hw
, port
, XM_STAT_CMD
)
1576 & (XM_SC_SNP_TXC
| XM_SC_SNP_RXC
)) {
1577 if (time_after(jiffies
, timeout
))
1582 /* special case for 64 bit octet counter */
1583 data
[0] = (u64
) xm_read32(hw
, port
, XM_TXO_OK_HI
) << 32
1584 | xm_read32(hw
, port
, XM_TXO_OK_LO
);
1585 data
[1] = (u64
) xm_read32(hw
, port
, XM_RXO_OK_HI
) << 32
1586 | xm_read32(hw
, port
, XM_RXO_OK_LO
);
1588 for (i
= 2; i
< ARRAY_SIZE(skge_stats
); i
++)
1589 data
[i
] = xm_read32(hw
, port
, skge_stats
[i
].xmac_offset
);
1592 static void genesis_mac_intr(struct skge_hw
*hw
, int port
)
1594 struct skge_port
*skge
= netdev_priv(hw
->dev
[port
]);
1595 u16 status
= xm_read16(hw
, port
, XM_ISRC
);
1597 if (netif_msg_intr(skge
))
1598 printk(KERN_DEBUG PFX
"%s: mac interrupt status 0x%x\n",
1599 skge
->netdev
->name
, status
);
1601 if (hw
->phy_type
== SK_PHY_XMAC
&&
1602 (status
& (XM_IS_INP_ASS
| XM_IS_LIPA_RC
)))
1603 xm_link_down(hw
, port
);
1605 if (status
& XM_IS_TXF_UR
) {
1606 xm_write32(hw
, port
, XM_MODE
, XM_MD_FTF
);
1607 ++skge
->net_stats
.tx_fifo_errors
;
1609 if (status
& XM_IS_RXF_OV
) {
1610 xm_write32(hw
, port
, XM_MODE
, XM_MD_FRF
);
1611 ++skge
->net_stats
.rx_fifo_errors
;
1615 static void genesis_link_up(struct skge_port
*skge
)
1617 struct skge_hw
*hw
= skge
->hw
;
1618 int port
= skge
->port
;
1622 cmd
= xm_read16(hw
, port
, XM_MMU_CMD
);
1625 * enabling pause frame reception is required for 1000BT
1626 * because the XMAC is not reset if the link is going down
1628 if (skge
->flow_status
== FLOW_STAT_NONE
||
1629 skge
->flow_status
== FLOW_STAT_LOC_SEND
)
1630 /* Disable Pause Frame Reception */
1631 cmd
|= XM_MMU_IGN_PF
;
1633 /* Enable Pause Frame Reception */
1634 cmd
&= ~XM_MMU_IGN_PF
;
1636 xm_write16(hw
, port
, XM_MMU_CMD
, cmd
);
1638 mode
= xm_read32(hw
, port
, XM_MODE
);
1639 if (skge
->flow_status
== FLOW_STAT_SYMMETRIC
||
1640 skge
->flow_status
== FLOW_STAT_LOC_SEND
) {
1642 * Configure Pause Frame Generation
1643 * Use internal and external Pause Frame Generation.
1644 * Sending pause frames is edge triggered.
1645 * Send a Pause frame with the maximum pause time if
1646 * internal oder external FIFO full condition occurs.
1647 * Send a zero pause time frame to re-start transmission.
1649 /* XM_PAUSE_DA = '010000C28001' (default) */
1650 /* XM_MAC_PTIME = 0xffff (maximum) */
1651 /* remember this value is defined in big endian (!) */
1652 xm_write16(hw
, port
, XM_MAC_PTIME
, 0xffff);
1654 mode
|= XM_PAUSE_MODE
;
1655 skge_write16(hw
, SK_REG(port
, RX_MFF_CTRL1
), MFF_ENA_PAUSE
);
1658 * disable pause frame generation is required for 1000BT
1659 * because the XMAC is not reset if the link is going down
1661 /* Disable Pause Mode in Mode Register */
1662 mode
&= ~XM_PAUSE_MODE
;
1664 skge_write16(hw
, SK_REG(port
, RX_MFF_CTRL1
), MFF_DIS_PAUSE
);
1667 xm_write32(hw
, port
, XM_MODE
, mode
);
1669 if (hw
->phy_type
!= SK_PHY_XMAC
)
1670 msk
|= XM_IS_INP_ASS
; /* disable GP0 interrupt bit */
1672 xm_write16(hw
, port
, XM_IMSK
, msk
);
1673 xm_read16(hw
, port
, XM_ISRC
);
1675 /* get MMU Command Reg. */
1676 cmd
= xm_read16(hw
, port
, XM_MMU_CMD
);
1677 if (hw
->phy_type
!= SK_PHY_XMAC
&& skge
->duplex
== DUPLEX_FULL
)
1678 cmd
|= XM_MMU_GMII_FD
;
1681 * Workaround BCOM Errata (#10523) for all BCom Phys
1682 * Enable Power Management after link up
1684 if (hw
->phy_type
== SK_PHY_BCOM
) {
1685 xm_phy_write(hw
, port
, PHY_BCOM_AUX_CTRL
,
1686 xm_phy_read(hw
, port
, PHY_BCOM_AUX_CTRL
)
1687 & ~PHY_B_AC_DIS_PM
);
1688 xm_phy_write(hw
, port
, PHY_BCOM_INT_MASK
, PHY_B_DEF_MSK
);
1692 xm_write16(hw
, port
, XM_MMU_CMD
,
1693 cmd
| XM_MMU_ENA_RX
| XM_MMU_ENA_TX
);
1698 static inline void bcom_phy_intr(struct skge_port
*skge
)
1700 struct skge_hw
*hw
= skge
->hw
;
1701 int port
= skge
->port
;
1704 isrc
= xm_phy_read(hw
, port
, PHY_BCOM_INT_STAT
);
1705 if (netif_msg_intr(skge
))
1706 printk(KERN_DEBUG PFX
"%s: phy interrupt status 0x%x\n",
1707 skge
->netdev
->name
, isrc
);
1709 if (isrc
& PHY_B_IS_PSE
)
1710 printk(KERN_ERR PFX
"%s: uncorrectable pair swap error\n",
1711 hw
->dev
[port
]->name
);
1713 /* Workaround BCom Errata:
1714 * enable and disable loopback mode if "NO HCD" occurs.
1716 if (isrc
& PHY_B_IS_NO_HDCL
) {
1717 u16 ctrl
= xm_phy_read(hw
, port
, PHY_BCOM_CTRL
);
1718 xm_phy_write(hw
, port
, PHY_BCOM_CTRL
,
1719 ctrl
| PHY_CT_LOOP
);
1720 xm_phy_write(hw
, port
, PHY_BCOM_CTRL
,
1721 ctrl
& ~PHY_CT_LOOP
);
1724 if (isrc
& (PHY_B_IS_AN_PR
| PHY_B_IS_LST_CHANGE
))
1725 bcom_check_link(hw
, port
);
1729 static int gm_phy_write(struct skge_hw
*hw
, int port
, u16 reg
, u16 val
)
1733 gma_write16(hw
, port
, GM_SMI_DATA
, val
);
1734 gma_write16(hw
, port
, GM_SMI_CTRL
,
1735 GM_SMI_CT_PHY_AD(hw
->phy_addr
) | GM_SMI_CT_REG_AD(reg
));
1736 for (i
= 0; i
< PHY_RETRIES
; i
++) {
1739 if (!(gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_BUSY
))
1743 printk(KERN_WARNING PFX
"%s: phy write timeout\n",
1744 hw
->dev
[port
]->name
);
1748 static int __gm_phy_read(struct skge_hw
*hw
, int port
, u16 reg
, u16
*val
)
1752 gma_write16(hw
, port
, GM_SMI_CTRL
,
1753 GM_SMI_CT_PHY_AD(hw
->phy_addr
)
1754 | GM_SMI_CT_REG_AD(reg
) | GM_SMI_CT_OP_RD
);
1756 for (i
= 0; i
< PHY_RETRIES
; i
++) {
1758 if (gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_RD_VAL
)
1764 *val
= gma_read16(hw
, port
, GM_SMI_DATA
);
1768 static u16
gm_phy_read(struct skge_hw
*hw
, int port
, u16 reg
)
1771 if (__gm_phy_read(hw
, port
, reg
, &v
))
1772 printk(KERN_WARNING PFX
"%s: phy read timeout\n",
1773 hw
->dev
[port
]->name
);
1777 /* Marvell Phy Initialization */
1778 static void yukon_init(struct skge_hw
*hw
, int port
)
1780 struct skge_port
*skge
= netdev_priv(hw
->dev
[port
]);
1781 u16 ctrl
, ct1000
, adv
;
1783 if (skge
->autoneg
== AUTONEG_ENABLE
) {
1784 u16 ectrl
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
1786 ectrl
&= ~(PHY_M_EC_M_DSC_MSK
| PHY_M_EC_S_DSC_MSK
|
1787 PHY_M_EC_MAC_S_MSK
);
1788 ectrl
|= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ
);
1790 ectrl
|= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1792 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
, ectrl
);
1795 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_CTRL
);
1796 if (skge
->autoneg
== AUTONEG_DISABLE
)
1797 ctrl
&= ~PHY_CT_ANE
;
1799 ctrl
|= PHY_CT_RESET
;
1800 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
1806 if (skge
->autoneg
== AUTONEG_ENABLE
) {
1808 if (skge
->advertising
& ADVERTISED_1000baseT_Full
)
1809 ct1000
|= PHY_M_1000C_AFD
;
1810 if (skge
->advertising
& ADVERTISED_1000baseT_Half
)
1811 ct1000
|= PHY_M_1000C_AHD
;
1812 if (skge
->advertising
& ADVERTISED_100baseT_Full
)
1813 adv
|= PHY_M_AN_100_FD
;
1814 if (skge
->advertising
& ADVERTISED_100baseT_Half
)
1815 adv
|= PHY_M_AN_100_HD
;
1816 if (skge
->advertising
& ADVERTISED_10baseT_Full
)
1817 adv
|= PHY_M_AN_10_FD
;
1818 if (skge
->advertising
& ADVERTISED_10baseT_Half
)
1819 adv
|= PHY_M_AN_10_HD
;
1821 /* Set Flow-control capabilities */
1822 adv
|= phy_pause_map
[skge
->flow_control
];
1824 if (skge
->advertising
& ADVERTISED_1000baseT_Full
)
1825 adv
|= PHY_M_AN_1000X_AFD
;
1826 if (skge
->advertising
& ADVERTISED_1000baseT_Half
)
1827 adv
|= PHY_M_AN_1000X_AHD
;
1829 adv
|= fiber_pause_map
[skge
->flow_control
];
1832 /* Restart Auto-negotiation */
1833 ctrl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
1835 /* forced speed/duplex settings */
1836 ct1000
= PHY_M_1000C_MSE
;
1838 if (skge
->duplex
== DUPLEX_FULL
)
1839 ctrl
|= PHY_CT_DUP_MD
;
1841 switch (skge
->speed
) {
1843 ctrl
|= PHY_CT_SP1000
;
1846 ctrl
|= PHY_CT_SP100
;
1850 ctrl
|= PHY_CT_RESET
;
1853 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, ct1000
);
1855 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, adv
);
1856 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
1858 /* Enable phy interrupt on autonegotiation complete (or link up) */
1859 if (skge
->autoneg
== AUTONEG_ENABLE
)
1860 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_AN_MSK
);
1862 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_DEF_MSK
);
1865 static void yukon_reset(struct skge_hw
*hw
, int port
)
1867 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);/* disable PHY IRQs */
1868 gma_write16(hw
, port
, GM_MC_ADDR_H1
, 0); /* clear MC hash */
1869 gma_write16(hw
, port
, GM_MC_ADDR_H2
, 0);
1870 gma_write16(hw
, port
, GM_MC_ADDR_H3
, 0);
1871 gma_write16(hw
, port
, GM_MC_ADDR_H4
, 0);
1873 gma_write16(hw
, port
, GM_RX_CTRL
,
1874 gma_read16(hw
, port
, GM_RX_CTRL
)
1875 | GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
1878 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
1879 static int is_yukon_lite_a0(struct skge_hw
*hw
)
1884 if (hw
->chip_id
!= CHIP_ID_YUKON
)
1887 reg
= skge_read32(hw
, B2_FAR
);
1888 skge_write8(hw
, B2_FAR
+ 3, 0xff);
1889 ret
= (skge_read8(hw
, B2_FAR
+ 3) != 0);
1890 skge_write32(hw
, B2_FAR
, reg
);
1894 static void yukon_mac_init(struct skge_hw
*hw
, int port
)
1896 struct skge_port
*skge
= netdev_priv(hw
->dev
[port
]);
1899 const u8
*addr
= hw
->dev
[port
]->dev_addr
;
1901 /* WA code for COMA mode -- set PHY reset */
1902 if (hw
->chip_id
== CHIP_ID_YUKON_LITE
&&
1903 hw
->chip_rev
>= CHIP_REV_YU_LITE_A3
) {
1904 reg
= skge_read32(hw
, B2_GP_IO
);
1905 reg
|= GP_DIR_9
| GP_IO_9
;
1906 skge_write32(hw
, B2_GP_IO
, reg
);
1910 skge_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
1911 skge_write32(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
1913 /* WA code for COMA mode -- clear PHY reset */
1914 if (hw
->chip_id
== CHIP_ID_YUKON_LITE
&&
1915 hw
->chip_rev
>= CHIP_REV_YU_LITE_A3
) {
1916 reg
= skge_read32(hw
, B2_GP_IO
);
1919 skge_write32(hw
, B2_GP_IO
, reg
);
1922 /* Set hardware config mode */
1923 reg
= GPC_INT_POL_HI
| GPC_DIS_FC
| GPC_DIS_SLEEP
|
1924 GPC_ENA_XC
| GPC_ANEG_ADV_ALL_M
| GPC_ENA_PAUSE
;
1925 reg
|= hw
->copper
? GPC_HWCFG_GMII_COP
: GPC_HWCFG_GMII_FIB
;
1927 /* Clear GMC reset */
1928 skge_write32(hw
, SK_REG(port
, GPHY_CTRL
), reg
| GPC_RST_SET
);
1929 skge_write32(hw
, SK_REG(port
, GPHY_CTRL
), reg
| GPC_RST_CLR
);
1930 skge_write32(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
| GMC_RST_CLR
);
1932 if (skge
->autoneg
== AUTONEG_DISABLE
) {
1933 reg
= GM_GPCR_AU_ALL_DIS
;
1934 gma_write16(hw
, port
, GM_GP_CTRL
,
1935 gma_read16(hw
, port
, GM_GP_CTRL
) | reg
);
1937 switch (skge
->speed
) {
1939 reg
&= ~GM_GPCR_SPEED_100
;
1940 reg
|= GM_GPCR_SPEED_1000
;
1943 reg
&= ~GM_GPCR_SPEED_1000
;
1944 reg
|= GM_GPCR_SPEED_100
;
1947 reg
&= ~(GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
);
1951 if (skge
->duplex
== DUPLEX_FULL
)
1952 reg
|= GM_GPCR_DUP_FULL
;
1954 reg
= GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
| GM_GPCR_DUP_FULL
;
1956 switch (skge
->flow_control
) {
1957 case FLOW_MODE_NONE
:
1958 skge_write32(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
1959 reg
|= GM_GPCR_FC_TX_DIS
| GM_GPCR_FC_RX_DIS
| GM_GPCR_AU_FCT_DIS
;
1961 case FLOW_MODE_LOC_SEND
:
1962 /* disable Rx flow-control */
1963 reg
|= GM_GPCR_FC_RX_DIS
| GM_GPCR_AU_FCT_DIS
;
1965 case FLOW_MODE_SYMMETRIC
:
1966 case FLOW_MODE_SYM_OR_REM
:
1967 /* enable Tx & Rx flow-control */
1971 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1972 skge_read16(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
1974 yukon_init(hw
, port
);
1977 reg
= gma_read16(hw
, port
, GM_PHY_ADDR
);
1978 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
| GM_PAR_MIB_CLR
);
1980 for (i
= 0; i
< GM_MIB_CNT_SIZE
; i
++)
1981 gma_read16(hw
, port
, GM_MIB_CNT_BASE
+ 8*i
);
1982 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
);
1984 /* transmit control */
1985 gma_write16(hw
, port
, GM_TX_CTRL
, TX_COL_THR(TX_COL_DEF
));
1987 /* receive control reg: unicast + multicast + no FCS */
1988 gma_write16(hw
, port
, GM_RX_CTRL
,
1989 GM_RXCR_UCF_ENA
| GM_RXCR_CRC_DIS
| GM_RXCR_MCF_ENA
);
1991 /* transmit flow control */
1992 gma_write16(hw
, port
, GM_TX_FLOW_CTRL
, 0xffff);
1994 /* transmit parameter */
1995 gma_write16(hw
, port
, GM_TX_PARAM
,
1996 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF
) |
1997 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF
) |
1998 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF
));
2000 /* serial mode register */
2001 reg
= GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
2002 if (hw
->dev
[port
]->mtu
> 1500)
2003 reg
|= GM_SMOD_JUMBO_ENA
;
2005 gma_write16(hw
, port
, GM_SERIAL_MODE
, reg
);
2007 /* physical address: used for pause frames */
2008 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, addr
);
2009 /* virtual address for data */
2010 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, addr
);
2012 /* enable interrupt mask for counter overflows */
2013 gma_write16(hw
, port
, GM_TX_IRQ_MSK
, 0);
2014 gma_write16(hw
, port
, GM_RX_IRQ_MSK
, 0);
2015 gma_write16(hw
, port
, GM_TR_IRQ_MSK
, 0);
2017 /* Initialize Mac Fifo */
2019 /* Configure Rx MAC FIFO */
2020 skge_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), RX_FF_FL_DEF_MSK
);
2021 reg
= GMF_OPER_ON
| GMF_RX_F_FL_ON
;
2023 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2024 if (is_yukon_lite_a0(hw
))
2025 reg
&= ~GMF_RX_F_FL_ON
;
2027 skge_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_CLR
);
2028 skge_write16(hw
, SK_REG(port
, RX_GMF_CTRL_T
), reg
);
2030 * because Pause Packet Truncation in GMAC is not working
2031 * we have to increase the Flush Threshold to 64 bytes
2032 * in order to flush pause packets in Rx FIFO on Yukon-1
2034 skge_write16(hw
, SK_REG(port
, RX_GMF_FL_THR
), RX_GMF_FL_THR_DEF
+1);
2036 /* Configure Tx MAC FIFO */
2037 skge_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_CLR
);
2038 skge_write16(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_OPER_ON
);
2041 /* Go into power down mode */
2042 static void yukon_suspend(struct skge_hw
*hw
, int port
)
2046 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
2047 ctrl
|= PHY_M_PC_POL_R_DIS
;
2048 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
2050 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_CTRL
);
2051 ctrl
|= PHY_CT_RESET
;
2052 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
2054 /* switch IEEE compatible power down mode on */
2055 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_CTRL
);
2056 ctrl
|= PHY_CT_PDOWN
;
2057 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
2060 static void yukon_stop(struct skge_port
*skge
)
2062 struct skge_hw
*hw
= skge
->hw
;
2063 int port
= skge
->port
;
2065 skge_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
2066 yukon_reset(hw
, port
);
2068 gma_write16(hw
, port
, GM_GP_CTRL
,
2069 gma_read16(hw
, port
, GM_GP_CTRL
)
2070 & ~(GM_GPCR_TX_ENA
|GM_GPCR_RX_ENA
));
2071 gma_read16(hw
, port
, GM_GP_CTRL
);
2073 yukon_suspend(hw
, port
);
2075 /* set GPHY Control reset */
2076 skge_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
2077 skge_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
2080 static void yukon_get_stats(struct skge_port
*skge
, u64
*data
)
2082 struct skge_hw
*hw
= skge
->hw
;
2083 int port
= skge
->port
;
2086 data
[0] = (u64
) gma_read32(hw
, port
, GM_TXO_OK_HI
) << 32
2087 | gma_read32(hw
, port
, GM_TXO_OK_LO
);
2088 data
[1] = (u64
) gma_read32(hw
, port
, GM_RXO_OK_HI
) << 32
2089 | gma_read32(hw
, port
, GM_RXO_OK_LO
);
2091 for (i
= 2; i
< ARRAY_SIZE(skge_stats
); i
++)
2092 data
[i
] = gma_read32(hw
, port
,
2093 skge_stats
[i
].gma_offset
);
2096 static void yukon_mac_intr(struct skge_hw
*hw
, int port
)
2098 struct net_device
*dev
= hw
->dev
[port
];
2099 struct skge_port
*skge
= netdev_priv(dev
);
2100 u8 status
= skge_read8(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
2102 if (netif_msg_intr(skge
))
2103 printk(KERN_DEBUG PFX
"%s: mac interrupt status 0x%x\n",
2106 if (status
& GM_IS_RX_FF_OR
) {
2107 ++skge
->net_stats
.rx_fifo_errors
;
2108 skge_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_CLI_RX_FO
);
2111 if (status
& GM_IS_TX_FF_UR
) {
2112 ++skge
->net_stats
.tx_fifo_errors
;
2113 skge_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_FU
);
2118 static u16
yukon_speed(const struct skge_hw
*hw
, u16 aux
)
2120 switch (aux
& PHY_M_PS_SPEED_MSK
) {
2121 case PHY_M_PS_SPEED_1000
:
2123 case PHY_M_PS_SPEED_100
:
2130 static void yukon_link_up(struct skge_port
*skge
)
2132 struct skge_hw
*hw
= skge
->hw
;
2133 int port
= skge
->port
;
2136 /* Enable Transmit FIFO Underrun */
2137 skge_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), GMAC_DEF_MSK
);
2139 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
2140 if (skge
->duplex
== DUPLEX_FULL
|| skge
->autoneg
== AUTONEG_ENABLE
)
2141 reg
|= GM_GPCR_DUP_FULL
;
2144 reg
|= GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
;
2145 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
2147 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_DEF_MSK
);
2151 static void yukon_link_down(struct skge_port
*skge
)
2153 struct skge_hw
*hw
= skge
->hw
;
2154 int port
= skge
->port
;
2157 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
2159 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
2160 ctrl
&= ~(GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
);
2161 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
2163 if (skge
->flow_status
== FLOW_STAT_REM_SEND
) {
2164 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_ADV
);
2165 ctrl
|= PHY_M_AN_ASP
;
2166 /* restore Asymmetric Pause bit */
2167 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, ctrl
);
2170 yukon_reset(hw
, port
);
2171 skge_link_down(skge
);
2173 yukon_init(hw
, port
);
2176 static void yukon_phy_intr(struct skge_port
*skge
)
2178 struct skge_hw
*hw
= skge
->hw
;
2179 int port
= skge
->port
;
2180 const char *reason
= NULL
;
2181 u16 istatus
, phystat
;
2183 istatus
= gm_phy_read(hw
, port
, PHY_MARV_INT_STAT
);
2184 phystat
= gm_phy_read(hw
, port
, PHY_MARV_PHY_STAT
);
2186 if (netif_msg_intr(skge
))
2187 printk(KERN_DEBUG PFX
"%s: phy interrupt status 0x%x 0x%x\n",
2188 skge
->netdev
->name
, istatus
, phystat
);
2190 if (istatus
& PHY_M_IS_AN_COMPL
) {
2191 if (gm_phy_read(hw
, port
, PHY_MARV_AUNE_LP
)
2193 reason
= "remote fault";
2197 if (gm_phy_read(hw
, port
, PHY_MARV_1000T_STAT
) & PHY_B_1000S_MSF
) {
2198 reason
= "master/slave fault";
2202 if (!(phystat
& PHY_M_PS_SPDUP_RES
)) {
2203 reason
= "speed/duplex";
2207 skge
->duplex
= (phystat
& PHY_M_PS_FULL_DUP
)
2208 ? DUPLEX_FULL
: DUPLEX_HALF
;
2209 skge
->speed
= yukon_speed(hw
, phystat
);
2211 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2212 switch (phystat
& PHY_M_PS_PAUSE_MSK
) {
2213 case PHY_M_PS_PAUSE_MSK
:
2214 skge
->flow_status
= FLOW_STAT_SYMMETRIC
;
2216 case PHY_M_PS_RX_P_EN
:
2217 skge
->flow_status
= FLOW_STAT_REM_SEND
;
2219 case PHY_M_PS_TX_P_EN
:
2220 skge
->flow_status
= FLOW_STAT_LOC_SEND
;
2223 skge
->flow_status
= FLOW_STAT_NONE
;
2226 if (skge
->flow_status
== FLOW_STAT_NONE
||
2227 (skge
->speed
< SPEED_1000
&& skge
->duplex
== DUPLEX_HALF
))
2228 skge_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
2230 skge_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
2231 yukon_link_up(skge
);
2235 if (istatus
& PHY_M_IS_LSP_CHANGE
)
2236 skge
->speed
= yukon_speed(hw
, phystat
);
2238 if (istatus
& PHY_M_IS_DUP_CHANGE
)
2239 skge
->duplex
= (phystat
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
2240 if (istatus
& PHY_M_IS_LST_CHANGE
) {
2241 if (phystat
& PHY_M_PS_LINK_UP
)
2242 yukon_link_up(skge
);
2244 yukon_link_down(skge
);
2248 printk(KERN_ERR PFX
"%s: autonegotiation failed (%s)\n",
2249 skge
->netdev
->name
, reason
);
2251 /* XXX restart autonegotiation? */
2254 static void skge_phy_reset(struct skge_port
*skge
)
2256 struct skge_hw
*hw
= skge
->hw
;
2257 int port
= skge
->port
;
2259 netif_stop_queue(skge
->netdev
);
2260 netif_carrier_off(skge
->netdev
);
2262 mutex_lock(&hw
->phy_mutex
);
2263 if (hw
->chip_id
== CHIP_ID_GENESIS
) {
2264 genesis_reset(hw
, port
);
2265 genesis_mac_init(hw
, port
);
2267 yukon_reset(hw
, port
);
2268 yukon_init(hw
, port
);
2270 mutex_unlock(&hw
->phy_mutex
);
2273 /* Basic MII support */
2274 static int skge_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
2276 struct mii_ioctl_data
*data
= if_mii(ifr
);
2277 struct skge_port
*skge
= netdev_priv(dev
);
2278 struct skge_hw
*hw
= skge
->hw
;
2279 int err
= -EOPNOTSUPP
;
2281 if (!netif_running(dev
))
2282 return -ENODEV
; /* Phy still in reset */
2286 data
->phy_id
= hw
->phy_addr
;
2291 mutex_lock(&hw
->phy_mutex
);
2292 if (hw
->chip_id
== CHIP_ID_GENESIS
)
2293 err
= __xm_phy_read(hw
, skge
->port
, data
->reg_num
& 0x1f, &val
);
2295 err
= __gm_phy_read(hw
, skge
->port
, data
->reg_num
& 0x1f, &val
);
2296 mutex_unlock(&hw
->phy_mutex
);
2297 data
->val_out
= val
;
2302 if (!capable(CAP_NET_ADMIN
))
2305 mutex_lock(&hw
->phy_mutex
);
2306 if (hw
->chip_id
== CHIP_ID_GENESIS
)
2307 err
= xm_phy_write(hw
, skge
->port
, data
->reg_num
& 0x1f,
2310 err
= gm_phy_write(hw
, skge
->port
, data
->reg_num
& 0x1f,
2312 mutex_unlock(&hw
->phy_mutex
);
2318 static void skge_ramset(struct skge_hw
*hw
, u16 q
, u32 start
, size_t len
)
2324 end
= start
+ len
- 1;
2326 skge_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_RST_CLR
);
2327 skge_write32(hw
, RB_ADDR(q
, RB_START
), start
);
2328 skge_write32(hw
, RB_ADDR(q
, RB_WP
), start
);
2329 skge_write32(hw
, RB_ADDR(q
, RB_RP
), start
);
2330 skge_write32(hw
, RB_ADDR(q
, RB_END
), end
);
2332 if (q
== Q_R1
|| q
== Q_R2
) {
2333 /* Set thresholds on receive queue's */
2334 skge_write32(hw
, RB_ADDR(q
, RB_RX_UTPP
),
2336 skge_write32(hw
, RB_ADDR(q
, RB_RX_LTPP
),
2339 /* Enable store & forward on Tx queue's because
2340 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2342 skge_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_STFWD
);
2345 skge_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_OP_MD
);
2348 /* Setup Bus Memory Interface */
2349 static void skge_qset(struct skge_port
*skge
, u16 q
,
2350 const struct skge_element
*e
)
2352 struct skge_hw
*hw
= skge
->hw
;
2353 u32 watermark
= 0x600;
2354 u64 base
= skge
->dma
+ (e
->desc
- skge
->mem
);
2356 /* optimization to reduce window on 32bit/33mhz */
2357 if ((skge_read16(hw
, B0_CTST
) & (CS_BUS_CLOCK
| CS_BUS_SLOT_SZ
)) == 0)
2360 skge_write32(hw
, Q_ADDR(q
, Q_CSR
), CSR_CLR_RESET
);
2361 skge_write32(hw
, Q_ADDR(q
, Q_F
), watermark
);
2362 skge_write32(hw
, Q_ADDR(q
, Q_DA_H
), (u32
)(base
>> 32));
2363 skge_write32(hw
, Q_ADDR(q
, Q_DA_L
), (u32
)base
);
2366 static int skge_up(struct net_device
*dev
)
2368 struct skge_port
*skge
= netdev_priv(dev
);
2369 struct skge_hw
*hw
= skge
->hw
;
2370 int port
= skge
->port
;
2371 u32 chunk
, ram_addr
;
2372 size_t rx_size
, tx_size
;
2375 if (netif_msg_ifup(skge
))
2376 printk(KERN_INFO PFX
"%s: enabling interface\n", dev
->name
);
2378 if (dev
->mtu
> RX_BUF_SIZE
)
2379 skge
->rx_buf_size
= dev
->mtu
+ ETH_HLEN
;
2381 skge
->rx_buf_size
= RX_BUF_SIZE
;
2384 rx_size
= skge
->rx_ring
.count
* sizeof(struct skge_rx_desc
);
2385 tx_size
= skge
->tx_ring
.count
* sizeof(struct skge_tx_desc
);
2386 skge
->mem_size
= tx_size
+ rx_size
;
2387 skge
->mem
= pci_alloc_consistent(hw
->pdev
, skge
->mem_size
, &skge
->dma
);
2391 BUG_ON(skge
->dma
& 7);
2393 if ((u64
)skge
->dma
>> 32 != ((u64
) skge
->dma
+ skge
->mem_size
) >> 32) {
2394 printk(KERN_ERR PFX
"pci_alloc_consistent region crosses 4G boundary\n");
2399 memset(skge
->mem
, 0, skge
->mem_size
);
2401 err
= skge_ring_alloc(&skge
->rx_ring
, skge
->mem
, skge
->dma
);
2405 err
= skge_rx_fill(dev
);
2409 err
= skge_ring_alloc(&skge
->tx_ring
, skge
->mem
+ rx_size
,
2410 skge
->dma
+ rx_size
);
2414 /* Initialize MAC */
2415 mutex_lock(&hw
->phy_mutex
);
2416 if (hw
->chip_id
== CHIP_ID_GENESIS
)
2417 genesis_mac_init(hw
, port
);
2419 yukon_mac_init(hw
, port
);
2420 mutex_unlock(&hw
->phy_mutex
);
2422 /* Configure RAMbuffers */
2423 chunk
= hw
->ram_size
/ ((hw
->ports
+ 1)*2);
2424 ram_addr
= hw
->ram_offset
+ 2 * chunk
* port
;
2426 skge_ramset(hw
, rxqaddr
[port
], ram_addr
, chunk
);
2427 skge_qset(skge
, rxqaddr
[port
], skge
->rx_ring
.to_clean
);
2429 BUG_ON(skge
->tx_ring
.to_use
!= skge
->tx_ring
.to_clean
);
2430 skge_ramset(hw
, txqaddr
[port
], ram_addr
+chunk
, chunk
);
2431 skge_qset(skge
, txqaddr
[port
], skge
->tx_ring
.to_use
);
2433 /* Start receiver BMU */
2435 skge_write8(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), CSR_START
| CSR_IRQ_CL_F
);
2436 skge_led(skge
, LED_MODE_ON
);
2438 netif_poll_enable(dev
);
2442 skge_rx_clean(skge
);
2443 kfree(skge
->rx_ring
.start
);
2445 pci_free_consistent(hw
->pdev
, skge
->mem_size
, skge
->mem
, skge
->dma
);
2451 static int skge_down(struct net_device
*dev
)
2453 struct skge_port
*skge
= netdev_priv(dev
);
2454 struct skge_hw
*hw
= skge
->hw
;
2455 int port
= skge
->port
;
2457 if (skge
->mem
== NULL
)
2460 if (netif_msg_ifdown(skge
))
2461 printk(KERN_INFO PFX
"%s: disabling interface\n", dev
->name
);
2463 netif_stop_queue(dev
);
2464 if (hw
->chip_id
== CHIP_ID_GENESIS
&& hw
->phy_type
== SK_PHY_XMAC
)
2465 cancel_rearming_delayed_work(&skge
->link_thread
);
2467 skge_write8(skge
->hw
, SK_REG(skge
->port
, LNK_LED_REG
), LED_OFF
);
2468 if (hw
->chip_id
== CHIP_ID_GENESIS
)
2473 /* Stop transmitter */
2474 skge_write8(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), CSR_STOP
);
2475 skge_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
),
2476 RB_RST_SET
|RB_DIS_OP_MD
);
2479 /* Disable Force Sync bit and Enable Alloc bit */
2480 skge_write8(hw
, SK_REG(port
, TXA_CTRL
),
2481 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
2483 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2484 skge_write32(hw
, SK_REG(port
, TXA_ITI_INI
), 0L);
2485 skge_write32(hw
, SK_REG(port
, TXA_LIM_INI
), 0L);
2487 /* Reset PCI FIFO */
2488 skge_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), CSR_SET_RESET
);
2489 skge_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
), RB_RST_SET
);
2491 /* Reset the RAM Buffer async Tx queue */
2492 skge_write8(hw
, RB_ADDR(port
== 0 ? Q_XA1
: Q_XA2
, RB_CTRL
), RB_RST_SET
);
2494 skge_write8(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), CSR_STOP
);
2495 skge_write32(hw
, RB_ADDR(port
? Q_R2
: Q_R1
, RB_CTRL
),
2496 RB_RST_SET
|RB_DIS_OP_MD
);
2497 skge_write32(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), CSR_SET_RESET
);
2499 if (hw
->chip_id
== CHIP_ID_GENESIS
) {
2500 skge_write8(hw
, SK_REG(port
, TX_MFF_CTRL2
), MFF_RST_SET
);
2501 skge_write8(hw
, SK_REG(port
, RX_MFF_CTRL2
), MFF_RST_SET
);
2503 skge_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
2504 skge_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_SET
);
2507 skge_led(skge
, LED_MODE_OFF
);
2509 netif_poll_disable(dev
);
2511 skge_rx_clean(skge
);
2513 kfree(skge
->rx_ring
.start
);
2514 kfree(skge
->tx_ring
.start
);
2515 pci_free_consistent(hw
->pdev
, skge
->mem_size
, skge
->mem
, skge
->dma
);
2520 static inline int skge_avail(const struct skge_ring
*ring
)
2522 return ((ring
->to_clean
> ring
->to_use
) ? 0 : ring
->count
)
2523 + (ring
->to_clean
- ring
->to_use
) - 1;
2526 static int skge_xmit_frame(struct sk_buff
*skb
, struct net_device
*dev
)
2528 struct skge_port
*skge
= netdev_priv(dev
);
2529 struct skge_hw
*hw
= skge
->hw
;
2530 struct skge_element
*e
;
2531 struct skge_tx_desc
*td
;
2536 if (skb_padto(skb
, ETH_ZLEN
))
2537 return NETDEV_TX_OK
;
2539 if (unlikely(skge_avail(&skge
->tx_ring
) < skb_shinfo(skb
)->nr_frags
+ 1))
2540 return NETDEV_TX_BUSY
;
2542 e
= skge
->tx_ring
.to_use
;
2544 BUG_ON(td
->control
& BMU_OWN
);
2546 len
= skb_headlen(skb
);
2547 map
= pci_map_single(hw
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
2548 pci_unmap_addr_set(e
, mapaddr
, map
);
2549 pci_unmap_len_set(e
, maplen
, len
);
2552 td
->dma_hi
= map
>> 32;
2554 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
2555 int offset
= skb
->h
.raw
- skb
->data
;
2557 /* This seems backwards, but it is what the sk98lin
2558 * does. Looks like hardware is wrong?
2560 if (skb
->h
.ipiph
->protocol
== IPPROTO_UDP
2561 && hw
->chip_rev
== 0 && hw
->chip_id
== CHIP_ID_YUKON
)
2562 control
= BMU_TCP_CHECK
;
2564 control
= BMU_UDP_CHECK
;
2567 td
->csum_start
= offset
;
2568 td
->csum_write
= offset
+ skb
->csum
;
2570 control
= BMU_CHECK
;
2572 if (!skb_shinfo(skb
)->nr_frags
) /* single buffer i.e. no fragments */
2573 control
|= BMU_EOF
| BMU_IRQ_EOF
;
2575 struct skge_tx_desc
*tf
= td
;
2577 control
|= BMU_STFWD
;
2578 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
2579 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2581 map
= pci_map_page(hw
->pdev
, frag
->page
, frag
->page_offset
,
2582 frag
->size
, PCI_DMA_TODEVICE
);
2587 BUG_ON(tf
->control
& BMU_OWN
);
2590 tf
->dma_hi
= (u64
) map
>> 32;
2591 pci_unmap_addr_set(e
, mapaddr
, map
);
2592 pci_unmap_len_set(e
, maplen
, frag
->size
);
2594 tf
->control
= BMU_OWN
| BMU_SW
| control
| frag
->size
;
2596 tf
->control
|= BMU_EOF
| BMU_IRQ_EOF
;
2598 /* Make sure all the descriptors written */
2600 td
->control
= BMU_OWN
| BMU_SW
| BMU_STF
| control
| len
;
2603 skge_write8(hw
, Q_ADDR(txqaddr
[skge
->port
], Q_CSR
), CSR_START
);
2605 if (unlikely(netif_msg_tx_queued(skge
)))
2606 printk(KERN_DEBUG
"%s: tx queued, slot %td, len %d\n",
2607 dev
->name
, e
- skge
->tx_ring
.start
, skb
->len
);
2609 skge
->tx_ring
.to_use
= e
->next
;
2610 if (skge_avail(&skge
->tx_ring
) <= TX_LOW_WATER
) {
2611 pr_debug("%s: transmit queue full\n", dev
->name
);
2612 netif_stop_queue(dev
);
2615 dev
->trans_start
= jiffies
;
2617 return NETDEV_TX_OK
;
2621 /* Free resources associated with this reing element */
2622 static void skge_tx_free(struct skge_port
*skge
, struct skge_element
*e
,
2625 struct pci_dev
*pdev
= skge
->hw
->pdev
;
2629 /* skb header vs. fragment */
2630 if (control
& BMU_STF
)
2631 pci_unmap_single(pdev
, pci_unmap_addr(e
, mapaddr
),
2632 pci_unmap_len(e
, maplen
),
2635 pci_unmap_page(pdev
, pci_unmap_addr(e
, mapaddr
),
2636 pci_unmap_len(e
, maplen
),
2639 if (control
& BMU_EOF
) {
2640 if (unlikely(netif_msg_tx_done(skge
)))
2641 printk(KERN_DEBUG PFX
"%s: tx done slot %td\n",
2642 skge
->netdev
->name
, e
- skge
->tx_ring
.start
);
2644 dev_kfree_skb(e
->skb
);
2649 /* Free all buffers in transmit ring */
2650 static void skge_tx_clean(struct net_device
*dev
)
2652 struct skge_port
*skge
= netdev_priv(dev
);
2653 struct skge_element
*e
;
2655 netif_tx_lock_bh(dev
);
2656 for (e
= skge
->tx_ring
.to_clean
; e
!= skge
->tx_ring
.to_use
; e
= e
->next
) {
2657 struct skge_tx_desc
*td
= e
->desc
;
2658 skge_tx_free(skge
, e
, td
->control
);
2662 skge
->tx_ring
.to_clean
= e
;
2663 netif_wake_queue(dev
);
2664 netif_tx_unlock_bh(dev
);
2667 static void skge_tx_timeout(struct net_device
*dev
)
2669 struct skge_port
*skge
= netdev_priv(dev
);
2671 if (netif_msg_timer(skge
))
2672 printk(KERN_DEBUG PFX
"%s: tx timeout\n", dev
->name
);
2674 skge_write8(skge
->hw
, Q_ADDR(txqaddr
[skge
->port
], Q_CSR
), CSR_STOP
);
2678 static int skge_change_mtu(struct net_device
*dev
, int new_mtu
)
2682 if (new_mtu
< ETH_ZLEN
|| new_mtu
> ETH_JUMBO_MTU
)
2685 if (!netif_running(dev
)) {
2701 static void genesis_set_multicast(struct net_device
*dev
)
2703 struct skge_port
*skge
= netdev_priv(dev
);
2704 struct skge_hw
*hw
= skge
->hw
;
2705 int port
= skge
->port
;
2706 int i
, count
= dev
->mc_count
;
2707 struct dev_mc_list
*list
= dev
->mc_list
;
2711 mode
= xm_read32(hw
, port
, XM_MODE
);
2712 mode
|= XM_MD_ENA_HASH
;
2713 if (dev
->flags
& IFF_PROMISC
)
2714 mode
|= XM_MD_ENA_PROM
;
2716 mode
&= ~XM_MD_ENA_PROM
;
2718 if (dev
->flags
& IFF_ALLMULTI
)
2719 memset(filter
, 0xff, sizeof(filter
));
2721 memset(filter
, 0, sizeof(filter
));
2722 for (i
= 0; list
&& i
< count
; i
++, list
= list
->next
) {
2724 crc
= ether_crc_le(ETH_ALEN
, list
->dmi_addr
);
2726 filter
[bit
/8] |= 1 << (bit
%8);
2730 xm_write32(hw
, port
, XM_MODE
, mode
);
2731 xm_outhash(hw
, port
, XM_HSM
, filter
);
2734 static void yukon_set_multicast(struct net_device
*dev
)
2736 struct skge_port
*skge
= netdev_priv(dev
);
2737 struct skge_hw
*hw
= skge
->hw
;
2738 int port
= skge
->port
;
2739 struct dev_mc_list
*list
= dev
->mc_list
;
2743 memset(filter
, 0, sizeof(filter
));
2745 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
2746 reg
|= GM_RXCR_UCF_ENA
;
2748 if (dev
->flags
& IFF_PROMISC
) /* promiscuous */
2749 reg
&= ~(GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
2750 else if (dev
->flags
& IFF_ALLMULTI
) /* all multicast */
2751 memset(filter
, 0xff, sizeof(filter
));
2752 else if (dev
->mc_count
== 0) /* no multicast */
2753 reg
&= ~GM_RXCR_MCF_ENA
;
2756 reg
|= GM_RXCR_MCF_ENA
;
2758 for (i
= 0; list
&& i
< dev
->mc_count
; i
++, list
= list
->next
) {
2759 u32 bit
= ether_crc(ETH_ALEN
, list
->dmi_addr
) & 0x3f;
2760 filter
[bit
/8] |= 1 << (bit
%8);
2765 gma_write16(hw
, port
, GM_MC_ADDR_H1
,
2766 (u16
)filter
[0] | ((u16
)filter
[1] << 8));
2767 gma_write16(hw
, port
, GM_MC_ADDR_H2
,
2768 (u16
)filter
[2] | ((u16
)filter
[3] << 8));
2769 gma_write16(hw
, port
, GM_MC_ADDR_H3
,
2770 (u16
)filter
[4] | ((u16
)filter
[5] << 8));
2771 gma_write16(hw
, port
, GM_MC_ADDR_H4
,
2772 (u16
)filter
[6] | ((u16
)filter
[7] << 8));
2774 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
2777 static inline u16
phy_length(const struct skge_hw
*hw
, u32 status
)
2779 if (hw
->chip_id
== CHIP_ID_GENESIS
)
2780 return status
>> XMR_FS_LEN_SHIFT
;
2782 return status
>> GMR_FS_LEN_SHIFT
;
2785 static inline int bad_phy_status(const struct skge_hw
*hw
, u32 status
)
2787 if (hw
->chip_id
== CHIP_ID_GENESIS
)
2788 return (status
& (XMR_FS_ERR
| XMR_FS_2L_VLAN
)) != 0;
2790 return (status
& GMR_FS_ANY_ERR
) ||
2791 (status
& GMR_FS_RX_OK
) == 0;
2795 /* Get receive buffer from descriptor.
2796 * Handles copy of small buffers and reallocation failures
2798 static struct sk_buff
*skge_rx_get(struct net_device
*dev
,
2799 struct skge_element
*e
,
2800 u32 control
, u32 status
, u16 csum
)
2802 struct skge_port
*skge
= netdev_priv(dev
);
2803 struct sk_buff
*skb
;
2804 u16 len
= control
& BMU_BBC
;
2806 if (unlikely(netif_msg_rx_status(skge
)))
2807 printk(KERN_DEBUG PFX
"%s: rx slot %td status 0x%x len %d\n",
2808 dev
->name
, e
- skge
->rx_ring
.start
,
2811 if (len
> skge
->rx_buf_size
)
2814 if ((control
& (BMU_EOF
|BMU_STF
)) != (BMU_STF
|BMU_EOF
))
2817 if (bad_phy_status(skge
->hw
, status
))
2820 if (phy_length(skge
->hw
, status
) != len
)
2823 if (len
< RX_COPY_THRESHOLD
) {
2824 skb
= netdev_alloc_skb(dev
, len
+ 2);
2828 skb_reserve(skb
, 2);
2829 pci_dma_sync_single_for_cpu(skge
->hw
->pdev
,
2830 pci_unmap_addr(e
, mapaddr
),
2831 len
, PCI_DMA_FROMDEVICE
);
2832 memcpy(skb
->data
, e
->skb
->data
, len
);
2833 pci_dma_sync_single_for_device(skge
->hw
->pdev
,
2834 pci_unmap_addr(e
, mapaddr
),
2835 len
, PCI_DMA_FROMDEVICE
);
2836 skge_rx_reuse(e
, skge
->rx_buf_size
);
2838 struct sk_buff
*nskb
;
2839 nskb
= netdev_alloc_skb(dev
, skge
->rx_buf_size
+ NET_IP_ALIGN
);
2843 skb_reserve(nskb
, NET_IP_ALIGN
);
2844 pci_unmap_single(skge
->hw
->pdev
,
2845 pci_unmap_addr(e
, mapaddr
),
2846 pci_unmap_len(e
, maplen
),
2847 PCI_DMA_FROMDEVICE
);
2849 prefetch(skb
->data
);
2850 skge_rx_setup(skge
, e
, nskb
, skge
->rx_buf_size
);
2854 if (skge
->rx_csum
) {
2856 skb
->ip_summed
= CHECKSUM_COMPLETE
;
2859 skb
->protocol
= eth_type_trans(skb
, dev
);
2864 if (netif_msg_rx_err(skge
))
2865 printk(KERN_DEBUG PFX
"%s: rx err, slot %td control 0x%x status 0x%x\n",
2866 dev
->name
, e
- skge
->rx_ring
.start
,
2869 if (skge
->hw
->chip_id
== CHIP_ID_GENESIS
) {
2870 if (status
& (XMR_FS_RUNT
|XMR_FS_LNG_ERR
))
2871 skge
->net_stats
.rx_length_errors
++;
2872 if (status
& XMR_FS_FRA_ERR
)
2873 skge
->net_stats
.rx_frame_errors
++;
2874 if (status
& XMR_FS_FCS_ERR
)
2875 skge
->net_stats
.rx_crc_errors
++;
2877 if (status
& (GMR_FS_LONG_ERR
|GMR_FS_UN_SIZE
))
2878 skge
->net_stats
.rx_length_errors
++;
2879 if (status
& GMR_FS_FRAGMENT
)
2880 skge
->net_stats
.rx_frame_errors
++;
2881 if (status
& GMR_FS_CRC_ERR
)
2882 skge
->net_stats
.rx_crc_errors
++;
2886 skge_rx_reuse(e
, skge
->rx_buf_size
);
2890 /* Free all buffers in Tx ring which are no longer owned by device */
2891 static void skge_tx_done(struct net_device
*dev
)
2893 struct skge_port
*skge
= netdev_priv(dev
);
2894 struct skge_ring
*ring
= &skge
->tx_ring
;
2895 struct skge_element
*e
;
2897 skge_write8(skge
->hw
, Q_ADDR(txqaddr
[skge
->port
], Q_CSR
), CSR_IRQ_CL_F
);
2900 for (e
= ring
->to_clean
; e
!= ring
->to_use
; e
= e
->next
) {
2901 struct skge_tx_desc
*td
= e
->desc
;
2903 if (td
->control
& BMU_OWN
)
2906 skge_tx_free(skge
, e
, td
->control
);
2908 skge
->tx_ring
.to_clean
= e
;
2910 if (skge_avail(&skge
->tx_ring
) > TX_LOW_WATER
)
2911 netif_wake_queue(dev
);
2913 netif_tx_unlock(dev
);
2916 static int skge_poll(struct net_device
*dev
, int *budget
)
2918 struct skge_port
*skge
= netdev_priv(dev
);
2919 struct skge_hw
*hw
= skge
->hw
;
2920 struct skge_ring
*ring
= &skge
->rx_ring
;
2921 struct skge_element
*e
;
2922 int to_do
= min(dev
->quota
, *budget
);
2927 skge_write8(hw
, Q_ADDR(rxqaddr
[skge
->port
], Q_CSR
), CSR_IRQ_CL_F
);
2929 for (e
= ring
->to_clean
; prefetch(e
->next
), work_done
< to_do
; e
= e
->next
) {
2930 struct skge_rx_desc
*rd
= e
->desc
;
2931 struct sk_buff
*skb
;
2935 control
= rd
->control
;
2936 if (control
& BMU_OWN
)
2939 skb
= skge_rx_get(dev
, e
, control
, rd
->status
, rd
->csum2
);
2941 dev
->last_rx
= jiffies
;
2942 netif_receive_skb(skb
);
2949 /* restart receiver */
2951 skge_write8(hw
, Q_ADDR(rxqaddr
[skge
->port
], Q_CSR
), CSR_START
);
2953 *budget
-= work_done
;
2954 dev
->quota
-= work_done
;
2956 if (work_done
>= to_do
)
2957 return 1; /* not done */
2959 spin_lock_irq(&hw
->hw_lock
);
2960 __netif_rx_complete(dev
);
2961 hw
->intr_mask
|= irqmask
[skge
->port
];
2962 skge_write32(hw
, B0_IMSK
, hw
->intr_mask
);
2963 skge_read32(hw
, B0_IMSK
);
2964 spin_unlock_irq(&hw
->hw_lock
);
2969 /* Parity errors seem to happen when Genesis is connected to a switch
2970 * with no other ports present. Heartbeat error??
2972 static void skge_mac_parity(struct skge_hw
*hw
, int port
)
2974 struct net_device
*dev
= hw
->dev
[port
];
2977 struct skge_port
*skge
= netdev_priv(dev
);
2978 ++skge
->net_stats
.tx_heartbeat_errors
;
2981 if (hw
->chip_id
== CHIP_ID_GENESIS
)
2982 skge_write16(hw
, SK_REG(port
, TX_MFF_CTRL1
),
2985 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
2986 skge_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
2987 (hw
->chip_id
== CHIP_ID_YUKON
&& hw
->chip_rev
== 0)
2988 ? GMF_CLI_TX_FC
: GMF_CLI_TX_PE
);
2991 static void skge_mac_intr(struct skge_hw
*hw
, int port
)
2993 if (hw
->chip_id
== CHIP_ID_GENESIS
)
2994 genesis_mac_intr(hw
, port
);
2996 yukon_mac_intr(hw
, port
);
2999 /* Handle device specific framing and timeout interrupts */
3000 static void skge_error_irq(struct skge_hw
*hw
)
3002 u32 hwstatus
= skge_read32(hw
, B0_HWE_ISRC
);
3004 if (hw
->chip_id
== CHIP_ID_GENESIS
) {
3005 /* clear xmac errors */
3006 if (hwstatus
& (IS_NO_STAT_M1
|IS_NO_TIST_M1
))
3007 skge_write16(hw
, RX_MFF_CTRL1
, MFF_CLR_INSTAT
);
3008 if (hwstatus
& (IS_NO_STAT_M2
|IS_NO_TIST_M2
))
3009 skge_write16(hw
, RX_MFF_CTRL2
, MFF_CLR_INSTAT
);
3011 /* Timestamp (unused) overflow */
3012 if (hwstatus
& IS_IRQ_TIST_OV
)
3013 skge_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
3016 if (hwstatus
& IS_RAM_RD_PAR
) {
3017 printk(KERN_ERR PFX
"Ram read data parity error\n");
3018 skge_write16(hw
, B3_RI_CTRL
, RI_CLR_RD_PERR
);
3021 if (hwstatus
& IS_RAM_WR_PAR
) {
3022 printk(KERN_ERR PFX
"Ram write data parity error\n");
3023 skge_write16(hw
, B3_RI_CTRL
, RI_CLR_WR_PERR
);
3026 if (hwstatus
& IS_M1_PAR_ERR
)
3027 skge_mac_parity(hw
, 0);
3029 if (hwstatus
& IS_M2_PAR_ERR
)
3030 skge_mac_parity(hw
, 1);
3032 if (hwstatus
& IS_R1_PAR_ERR
) {
3033 printk(KERN_ERR PFX
"%s: receive queue parity error\n",
3035 skge_write32(hw
, B0_R1_CSR
, CSR_IRQ_CL_P
);
3038 if (hwstatus
& IS_R2_PAR_ERR
) {
3039 printk(KERN_ERR PFX
"%s: receive queue parity error\n",
3041 skge_write32(hw
, B0_R2_CSR
, CSR_IRQ_CL_P
);
3044 if (hwstatus
& (IS_IRQ_MST_ERR
|IS_IRQ_STAT
)) {
3045 u16 pci_status
, pci_cmd
;
3047 pci_read_config_word(hw
->pdev
, PCI_COMMAND
, &pci_cmd
);
3048 pci_read_config_word(hw
->pdev
, PCI_STATUS
, &pci_status
);
3050 printk(KERN_ERR PFX
"%s: PCI error cmd=%#x status=%#x\n",
3051 pci_name(hw
->pdev
), pci_cmd
, pci_status
);
3053 /* Write the error bits back to clear them. */
3054 pci_status
&= PCI_STATUS_ERROR_BITS
;
3055 skge_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
3056 pci_write_config_word(hw
->pdev
, PCI_COMMAND
,
3057 pci_cmd
| PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
);
3058 pci_write_config_word(hw
->pdev
, PCI_STATUS
, pci_status
);
3059 skge_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
3061 /* if error still set then just ignore it */
3062 hwstatus
= skge_read32(hw
, B0_HWE_ISRC
);
3063 if (hwstatus
& IS_IRQ_STAT
) {
3064 printk(KERN_INFO PFX
"unable to clear error (so ignoring them)\n");
3065 hw
->intr_mask
&= ~IS_HW_ERR
;
3071 * Interrupt from PHY are handled in work queue
3072 * because accessing phy registers requires spin wait which might
3073 * cause excess interrupt latency.
3075 static void skge_extirq(void *arg
)
3077 struct skge_hw
*hw
= arg
;
3080 mutex_lock(&hw
->phy_mutex
);
3081 for (port
= 0; port
< hw
->ports
; port
++) {
3082 struct net_device
*dev
= hw
->dev
[port
];
3083 struct skge_port
*skge
= netdev_priv(dev
);
3085 if (netif_running(dev
)) {
3086 if (hw
->chip_id
!= CHIP_ID_GENESIS
)
3087 yukon_phy_intr(skge
);
3088 else if (hw
->phy_type
== SK_PHY_BCOM
)
3089 bcom_phy_intr(skge
);
3092 mutex_unlock(&hw
->phy_mutex
);
3094 spin_lock_irq(&hw
->hw_lock
);
3095 hw
->intr_mask
|= IS_EXT_REG
;
3096 skge_write32(hw
, B0_IMSK
, hw
->intr_mask
);
3097 skge_read32(hw
, B0_IMSK
);
3098 spin_unlock_irq(&hw
->hw_lock
);
3101 static irqreturn_t
skge_intr(int irq
, void *dev_id
)
3103 struct skge_hw
*hw
= dev_id
;
3107 spin_lock(&hw
->hw_lock
);
3108 /* Reading this register masks IRQ */
3109 status
= skge_read32(hw
, B0_SP_ISRC
);
3110 if (status
== 0 || status
== ~0)
3114 status
&= hw
->intr_mask
;
3115 if (status
& IS_EXT_REG
) {
3116 hw
->intr_mask
&= ~IS_EXT_REG
;
3117 schedule_work(&hw
->phy_work
);
3120 if (status
& (IS_XA1_F
|IS_R1_F
)) {
3121 hw
->intr_mask
&= ~(IS_XA1_F
|IS_R1_F
);
3122 netif_rx_schedule(hw
->dev
[0]);
3125 if (status
& IS_PA_TO_TX1
)
3126 skge_write16(hw
, B3_PA_CTRL
, PA_CLR_TO_TX1
);
3128 if (status
& IS_PA_TO_RX1
) {
3129 struct skge_port
*skge
= netdev_priv(hw
->dev
[0]);
3131 ++skge
->net_stats
.rx_over_errors
;
3132 skge_write16(hw
, B3_PA_CTRL
, PA_CLR_TO_RX1
);
3136 if (status
& IS_MAC1
)
3137 skge_mac_intr(hw
, 0);
3140 if (status
& (IS_XA2_F
|IS_R2_F
)) {
3141 hw
->intr_mask
&= ~(IS_XA2_F
|IS_R2_F
);
3142 netif_rx_schedule(hw
->dev
[1]);
3145 if (status
& IS_PA_TO_RX2
) {
3146 struct skge_port
*skge
= netdev_priv(hw
->dev
[1]);
3147 ++skge
->net_stats
.rx_over_errors
;
3148 skge_write16(hw
, B3_PA_CTRL
, PA_CLR_TO_RX2
);
3151 if (status
& IS_PA_TO_TX2
)
3152 skge_write16(hw
, B3_PA_CTRL
, PA_CLR_TO_TX2
);
3154 if (status
& IS_MAC2
)
3155 skge_mac_intr(hw
, 1);
3158 if (status
& IS_HW_ERR
)
3161 skge_write32(hw
, B0_IMSK
, hw
->intr_mask
);
3162 skge_read32(hw
, B0_IMSK
);
3164 spin_unlock(&hw
->hw_lock
);
3166 return IRQ_RETVAL(handled
);
3169 #ifdef CONFIG_NET_POLL_CONTROLLER
3170 static void skge_netpoll(struct net_device
*dev
)
3172 struct skge_port
*skge
= netdev_priv(dev
);
3174 disable_irq(dev
->irq
);
3175 skge_intr(dev
->irq
, skge
->hw
);
3176 enable_irq(dev
->irq
);
3180 static int skge_set_mac_address(struct net_device
*dev
, void *p
)
3182 struct skge_port
*skge
= netdev_priv(dev
);
3183 struct skge_hw
*hw
= skge
->hw
;
3184 unsigned port
= skge
->port
;
3185 const struct sockaddr
*addr
= p
;
3187 if (!is_valid_ether_addr(addr
->sa_data
))
3188 return -EADDRNOTAVAIL
;
3190 mutex_lock(&hw
->phy_mutex
);
3191 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
3192 memcpy_toio(hw
->regs
+ B2_MAC_1
+ port
*8,
3193 dev
->dev_addr
, ETH_ALEN
);
3194 memcpy_toio(hw
->regs
+ B2_MAC_2
+ port
*8,
3195 dev
->dev_addr
, ETH_ALEN
);
3197 if (hw
->chip_id
== CHIP_ID_GENESIS
)
3198 xm_outaddr(hw
, port
, XM_SA
, dev
->dev_addr
);
3200 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, dev
->dev_addr
);
3201 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, dev
->dev_addr
);
3203 mutex_unlock(&hw
->phy_mutex
);
3208 static const struct {
3212 { CHIP_ID_GENESIS
, "Genesis" },
3213 { CHIP_ID_YUKON
, "Yukon" },
3214 { CHIP_ID_YUKON_LITE
, "Yukon-Lite"},
3215 { CHIP_ID_YUKON_LP
, "Yukon-LP"},
3218 static const char *skge_board_name(const struct skge_hw
*hw
)
3221 static char buf
[16];
3223 for (i
= 0; i
< ARRAY_SIZE(skge_chips
); i
++)
3224 if (skge_chips
[i
].id
== hw
->chip_id
)
3225 return skge_chips
[i
].name
;
3227 snprintf(buf
, sizeof buf
, "chipid 0x%x", hw
->chip_id
);
3233 * Setup the board data structure, but don't bring up
3236 static int skge_reset(struct skge_hw
*hw
)
3239 u16 ctst
, pci_status
;
3240 u8 t8
, mac_cfg
, pmd_type
;
3243 ctst
= skge_read16(hw
, B0_CTST
);
3246 skge_write8(hw
, B0_CTST
, CS_RST_SET
);
3247 skge_write8(hw
, B0_CTST
, CS_RST_CLR
);
3249 /* clear PCI errors, if any */
3250 skge_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
3251 skge_write8(hw
, B2_TST_CTRL2
, 0);
3253 pci_read_config_word(hw
->pdev
, PCI_STATUS
, &pci_status
);
3254 pci_write_config_word(hw
->pdev
, PCI_STATUS
,
3255 pci_status
| PCI_STATUS_ERROR_BITS
);
3256 skge_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
3257 skge_write8(hw
, B0_CTST
, CS_MRST_CLR
);
3259 /* restore CLK_RUN bits (for Yukon-Lite) */
3260 skge_write16(hw
, B0_CTST
,
3261 ctst
& (CS_CLK_RUN_HOT
|CS_CLK_RUN_RST
|CS_CLK_RUN_ENA
));
3263 hw
->chip_id
= skge_read8(hw
, B2_CHIP_ID
);
3264 hw
->phy_type
= skge_read8(hw
, B2_E_1
) & 0xf;
3265 pmd_type
= skge_read8(hw
, B2_PMD_TYP
);
3266 hw
->copper
= (pmd_type
== 'T' || pmd_type
== '1');
3268 switch (hw
->chip_id
) {
3269 case CHIP_ID_GENESIS
:
3270 switch (hw
->phy_type
) {
3272 hw
->phy_addr
= PHY_ADDR_XMAC
;
3275 hw
->phy_addr
= PHY_ADDR_BCOM
;
3278 printk(KERN_ERR PFX
"%s: unsupported phy type 0x%x\n",
3279 pci_name(hw
->pdev
), hw
->phy_type
);
3285 case CHIP_ID_YUKON_LITE
:
3286 case CHIP_ID_YUKON_LP
:
3287 if (hw
->phy_type
< SK_PHY_MARV_COPPER
&& pmd_type
!= 'S')
3290 hw
->phy_addr
= PHY_ADDR_MARV
;
3294 printk(KERN_ERR PFX
"%s: unsupported chip type 0x%x\n",
3295 pci_name(hw
->pdev
), hw
->chip_id
);
3299 mac_cfg
= skge_read8(hw
, B2_MAC_CFG
);
3300 hw
->ports
= (mac_cfg
& CFG_SNG_MAC
) ? 1 : 2;
3301 hw
->chip_rev
= (mac_cfg
& CFG_CHIP_R_MSK
) >> 4;
3303 /* read the adapters RAM size */
3304 t8
= skge_read8(hw
, B2_E_0
);
3305 if (hw
->chip_id
== CHIP_ID_GENESIS
) {
3307 /* special case: 4 x 64k x 36, offset = 0x80000 */
3308 hw
->ram_size
= 0x100000;
3309 hw
->ram_offset
= 0x80000;
3311 hw
->ram_size
= t8
* 512;
3314 hw
->ram_size
= 0x20000;
3316 hw
->ram_size
= t8
* 4096;
3318 hw
->intr_mask
= IS_HW_ERR
| IS_PORT_1
;
3320 hw
->intr_mask
|= IS_PORT_2
;
3322 if (!(hw
->chip_id
== CHIP_ID_GENESIS
&& hw
->phy_type
== SK_PHY_XMAC
))
3323 hw
->intr_mask
|= IS_EXT_REG
;
3325 if (hw
->chip_id
== CHIP_ID_GENESIS
)
3328 /* switch power to VCC (WA for VAUX problem) */
3329 skge_write8(hw
, B0_POWER_CTRL
,
3330 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_OFF
| PC_VCC_ON
);
3332 /* avoid boards with stuck Hardware error bits */
3333 if ((skge_read32(hw
, B0_ISRC
) & IS_HW_ERR
) &&
3334 (skge_read32(hw
, B0_HWE_ISRC
) & IS_IRQ_SENSOR
)) {
3335 printk(KERN_WARNING PFX
"stuck hardware sensor bit\n");
3336 hw
->intr_mask
&= ~IS_HW_ERR
;
3339 /* Clear PHY COMA */
3340 skge_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
3341 pci_read_config_dword(hw
->pdev
, PCI_DEV_REG1
, ®
);
3342 reg
&= ~PCI_PHY_COMA
;
3343 pci_write_config_dword(hw
->pdev
, PCI_DEV_REG1
, reg
);
3344 skge_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
3347 for (i
= 0; i
< hw
->ports
; i
++) {
3348 skge_write16(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
3349 skge_write16(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
3353 /* turn off hardware timer (unused) */
3354 skge_write8(hw
, B2_TI_CTRL
, TIM_STOP
);
3355 skge_write8(hw
, B2_TI_CTRL
, TIM_CLR_IRQ
);
3356 skge_write8(hw
, B0_LED
, LED_STAT_ON
);
3358 /* enable the Tx Arbiters */
3359 for (i
= 0; i
< hw
->ports
; i
++)
3360 skge_write8(hw
, SK_REG(i
, TXA_CTRL
), TXA_ENA_ARB
);
3362 /* Initialize ram interface */
3363 skge_write16(hw
, B3_RI_CTRL
, RI_RST_CLR
);
3365 skge_write8(hw
, B3_RI_WTO_R1
, SK_RI_TO_53
);
3366 skge_write8(hw
, B3_RI_WTO_XA1
, SK_RI_TO_53
);
3367 skge_write8(hw
, B3_RI_WTO_XS1
, SK_RI_TO_53
);
3368 skge_write8(hw
, B3_RI_RTO_R1
, SK_RI_TO_53
);
3369 skge_write8(hw
, B3_RI_RTO_XA1
, SK_RI_TO_53
);
3370 skge_write8(hw
, B3_RI_RTO_XS1
, SK_RI_TO_53
);
3371 skge_write8(hw
, B3_RI_WTO_R2
, SK_RI_TO_53
);
3372 skge_write8(hw
, B3_RI_WTO_XA2
, SK_RI_TO_53
);
3373 skge_write8(hw
, B3_RI_WTO_XS2
, SK_RI_TO_53
);
3374 skge_write8(hw
, B3_RI_RTO_R2
, SK_RI_TO_53
);
3375 skge_write8(hw
, B3_RI_RTO_XA2
, SK_RI_TO_53
);
3376 skge_write8(hw
, B3_RI_RTO_XS2
, SK_RI_TO_53
);
3378 skge_write32(hw
, B0_HWE_IMSK
, IS_ERR_MSK
);
3380 /* Set interrupt moderation for Transmit only
3381 * Receive interrupts avoided by NAPI
3383 skge_write32(hw
, B2_IRQM_MSK
, IS_XA1_F
|IS_XA2_F
);
3384 skge_write32(hw
, B2_IRQM_INI
, skge_usecs2clk(hw
, 100));
3385 skge_write32(hw
, B2_IRQM_CTRL
, TIM_START
);
3387 skge_write32(hw
, B0_IMSK
, hw
->intr_mask
);
3389 mutex_lock(&hw
->phy_mutex
);
3390 for (i
= 0; i
< hw
->ports
; i
++) {
3391 if (hw
->chip_id
== CHIP_ID_GENESIS
)
3392 genesis_reset(hw
, i
);
3396 mutex_unlock(&hw
->phy_mutex
);
3401 /* Initialize network device */
3402 static struct net_device
*skge_devinit(struct skge_hw
*hw
, int port
,
3405 struct skge_port
*skge
;
3406 struct net_device
*dev
= alloc_etherdev(sizeof(*skge
));
3409 printk(KERN_ERR
"skge etherdev alloc failed");
3413 SET_MODULE_OWNER(dev
);
3414 SET_NETDEV_DEV(dev
, &hw
->pdev
->dev
);
3415 dev
->open
= skge_up
;
3416 dev
->stop
= skge_down
;
3417 dev
->do_ioctl
= skge_ioctl
;
3418 dev
->hard_start_xmit
= skge_xmit_frame
;
3419 dev
->get_stats
= skge_get_stats
;
3420 if (hw
->chip_id
== CHIP_ID_GENESIS
)
3421 dev
->set_multicast_list
= genesis_set_multicast
;
3423 dev
->set_multicast_list
= yukon_set_multicast
;
3425 dev
->set_mac_address
= skge_set_mac_address
;
3426 dev
->change_mtu
= skge_change_mtu
;
3427 SET_ETHTOOL_OPS(dev
, &skge_ethtool_ops
);
3428 dev
->tx_timeout
= skge_tx_timeout
;
3429 dev
->watchdog_timeo
= TX_WATCHDOG
;
3430 dev
->poll
= skge_poll
;
3431 dev
->weight
= NAPI_WEIGHT
;
3432 #ifdef CONFIG_NET_POLL_CONTROLLER
3433 dev
->poll_controller
= skge_netpoll
;
3435 dev
->irq
= hw
->pdev
->irq
;
3438 dev
->features
|= NETIF_F_HIGHDMA
;
3440 skge
= netdev_priv(dev
);
3443 skge
->msg_enable
= netif_msg_init(debug
, default_msg
);
3444 skge
->tx_ring
.count
= DEFAULT_TX_RING_SIZE
;
3445 skge
->rx_ring
.count
= DEFAULT_RX_RING_SIZE
;
3447 /* Auto speed and flow control */
3448 skge
->autoneg
= AUTONEG_ENABLE
;
3449 skge
->flow_control
= FLOW_MODE_SYM_OR_REM
;
3452 skge
->advertising
= skge_supported_modes(hw
);
3454 hw
->dev
[port
] = dev
;
3458 /* Only used for Genesis XMAC */
3459 INIT_WORK(&skge
->link_thread
, xm_link_timer
, dev
);
3461 if (hw
->chip_id
!= CHIP_ID_GENESIS
) {
3462 dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
;
3466 /* read the mac address */
3467 memcpy_fromio(dev
->dev_addr
, hw
->regs
+ B2_MAC_1
+ port
*8, ETH_ALEN
);
3468 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3470 /* device is off until link detection */
3471 netif_carrier_off(dev
);
3472 netif_stop_queue(dev
);
3477 static void __devinit
skge_show_addr(struct net_device
*dev
)
3479 const struct skge_port
*skge
= netdev_priv(dev
);
3481 if (netif_msg_probe(skge
))
3482 printk(KERN_INFO PFX
"%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3484 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
3485 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
3488 static int __devinit
skge_probe(struct pci_dev
*pdev
,
3489 const struct pci_device_id
*ent
)
3491 struct net_device
*dev
, *dev1
;
3493 int err
, using_dac
= 0;
3495 err
= pci_enable_device(pdev
);
3497 printk(KERN_ERR PFX
"%s cannot enable PCI device\n",
3502 err
= pci_request_regions(pdev
, DRV_NAME
);
3504 printk(KERN_ERR PFX
"%s cannot obtain PCI resources\n",
3506 goto err_out_disable_pdev
;
3509 pci_set_master(pdev
);
3511 if (!pci_set_dma_mask(pdev
, DMA_64BIT_MASK
)) {
3513 err
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
3514 } else if (!(err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
))) {
3516 err
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
3520 printk(KERN_ERR PFX
"%s no usable DMA configuration\n",
3522 goto err_out_free_regions
;
3526 /* byte swap descriptors in hardware */
3530 pci_read_config_dword(pdev
, PCI_DEV_REG2
, ®
);
3531 reg
|= PCI_REV_DESC
;
3532 pci_write_config_dword(pdev
, PCI_DEV_REG2
, reg
);
3537 hw
= kzalloc(sizeof(*hw
), GFP_KERNEL
);
3539 printk(KERN_ERR PFX
"%s: cannot allocate hardware struct\n",
3541 goto err_out_free_regions
;
3545 mutex_init(&hw
->phy_mutex
);
3546 INIT_WORK(&hw
->phy_work
, skge_extirq
, hw
);
3547 spin_lock_init(&hw
->hw_lock
);
3549 hw
->regs
= ioremap_nocache(pci_resource_start(pdev
, 0), 0x4000);
3551 printk(KERN_ERR PFX
"%s: cannot map device registers\n",
3553 goto err_out_free_hw
;
3556 err
= skge_reset(hw
);
3558 goto err_out_iounmap
;
3560 printk(KERN_INFO PFX DRV_VERSION
" addr 0x%llx irq %d chip %s rev %d\n",
3561 (unsigned long long)pci_resource_start(pdev
, 0), pdev
->irq
,
3562 skge_board_name(hw
), hw
->chip_rev
);
3564 dev
= skge_devinit(hw
, 0, using_dac
);
3566 goto err_out_led_off
;
3568 if (!is_valid_ether_addr(dev
->dev_addr
)) {
3569 printk(KERN_ERR PFX
"%s: bad (zero?) ethernet address in rom\n",
3572 goto err_out_free_netdev
;
3575 err
= register_netdev(dev
);
3577 printk(KERN_ERR PFX
"%s: cannot register net device\n",
3579 goto err_out_free_netdev
;
3582 err
= request_irq(pdev
->irq
, skge_intr
, IRQF_SHARED
, dev
->name
, hw
);
3584 printk(KERN_ERR PFX
"%s: cannot assign irq %d\n",
3585 dev
->name
, pdev
->irq
);
3586 goto err_out_unregister
;
3588 skge_show_addr(dev
);
3590 if (hw
->ports
> 1 && (dev1
= skge_devinit(hw
, 1, using_dac
))) {
3591 if (register_netdev(dev1
) == 0)
3592 skge_show_addr(dev1
);
3594 /* Failure to register second port need not be fatal */
3595 printk(KERN_WARNING PFX
"register of second port failed\n");
3600 pci_set_drvdata(pdev
, hw
);
3605 unregister_netdev(dev
);
3606 err_out_free_netdev
:
3609 skge_write16(hw
, B0_LED
, LED_STAT_OFF
);
3614 err_out_free_regions
:
3615 pci_release_regions(pdev
);
3616 err_out_disable_pdev
:
3617 pci_disable_device(pdev
);
3618 pci_set_drvdata(pdev
, NULL
);
3623 static void __devexit
skge_remove(struct pci_dev
*pdev
)
3625 struct skge_hw
*hw
= pci_get_drvdata(pdev
);
3626 struct net_device
*dev0
, *dev1
;
3631 if ((dev1
= hw
->dev
[1]))
3632 unregister_netdev(dev1
);
3634 unregister_netdev(dev0
);
3636 spin_lock_irq(&hw
->hw_lock
);
3638 skge_write32(hw
, B0_IMSK
, 0);
3639 skge_read32(hw
, B0_IMSK
);
3640 spin_unlock_irq(&hw
->hw_lock
);
3642 skge_write16(hw
, B0_LED
, LED_STAT_OFF
);
3643 skge_write8(hw
, B0_CTST
, CS_RST_SET
);
3645 flush_scheduled_work();
3647 free_irq(pdev
->irq
, hw
);
3648 pci_release_regions(pdev
);
3649 pci_disable_device(pdev
);
3656 pci_set_drvdata(pdev
, NULL
);
3660 static int skge_suspend(struct pci_dev
*pdev
, pm_message_t state
)
3662 struct skge_hw
*hw
= pci_get_drvdata(pdev
);
3665 pci_save_state(pdev
);
3666 for (i
= 0; i
< hw
->ports
; i
++) {
3667 struct net_device
*dev
= hw
->dev
[i
];
3669 if (netif_running(dev
)) {
3670 struct skge_port
*skge
= netdev_priv(dev
);
3672 netif_carrier_off(dev
);
3674 netif_stop_queue(dev
);
3679 netif_device_detach(dev
);
3682 skge_write32(hw
, B0_IMSK
, 0);
3683 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
), wol
);
3684 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
3689 static int skge_resume(struct pci_dev
*pdev
)
3691 struct skge_hw
*hw
= pci_get_drvdata(pdev
);
3694 pci_set_power_state(pdev
, PCI_D0
);
3695 pci_restore_state(pdev
);
3696 pci_enable_wake(pdev
, PCI_D0
, 0);
3698 err
= skge_reset(hw
);
3702 for (i
= 0; i
< hw
->ports
; i
++) {
3703 struct net_device
*dev
= hw
->dev
[i
];
3705 netif_device_attach(dev
);
3706 if (netif_running(dev
)) {
3710 printk(KERN_ERR PFX
"%s: could not up: %d\n",
3722 static struct pci_driver skge_driver
= {
3724 .id_table
= skge_id_table
,
3725 .probe
= skge_probe
,
3726 .remove
= __devexit_p(skge_remove
),
3728 .suspend
= skge_suspend
,
3729 .resume
= skge_resume
,
3733 static int __init
skge_init_module(void)
3735 return pci_register_driver(&skge_driver
);
3738 static void __exit
skge_cleanup_module(void)
3740 pci_unregister_driver(&skge_driver
);
3743 module_init(skge_init_module
);
3744 module_exit(skge_cleanup_module
);