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Merge git://git.infradead.org/iommu-2.6
[deliverable/linux.git] / drivers / net / sky2.c
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/netdevice.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/etherdevice.h>
31 #include <linux/ethtool.h>
32 #include <linux/pci.h>
33 #include <linux/ip.h>
34 #include <net/ip.h>
35 #include <linux/tcp.h>
36 #include <linux/in.h>
37 #include <linux/delay.h>
38 #include <linux/workqueue.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/debugfs.h>
42 #include <linux/mii.h>
43
44 #include <asm/irq.h>
45
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
48 #endif
49
50 #include "sky2.h"
51
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.26"
54 #define PFX DRV_NAME " "
55
56 /*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
59 * similar to Tigon3.
60 */
61
62 #define RX_LE_SIZE 1024
63 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
64 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
65 #define RX_DEF_PENDING RX_MAX_PENDING
66
67 /* This is the worst case number of transmit list elements for a single skb:
68 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
69 #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
70 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
71 #define TX_MAX_PENDING 4096
72 #define TX_DEF_PENDING 127
73
74 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
75 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
76 #define TX_WATCHDOG (5 * HZ)
77 #define NAPI_WEIGHT 64
78 #define PHY_RETRIES 1000
79
80 #define SKY2_EEPROM_MAGIC 0x9955aabb
81
82
83 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84
85 static const u32 default_msg =
86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
89
90 static int debug = -1; /* defaults above */
91 module_param(debug, int, 0);
92 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
93
94 static int copybreak __read_mostly = 128;
95 module_param(copybreak, int, 0);
96 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
97
98 static int disable_msi = 0;
99 module_param(disable_msi, int, 0);
100 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
101
102 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
143 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
144 { 0 }
145 };
146
147 MODULE_DEVICE_TABLE(pci, sky2_id_table);
148
149 /* Avoid conditionals by using array */
150 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
151 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
152 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
153
154 static void sky2_set_multicast(struct net_device *dev);
155
156 /* Access to PHY via serial interconnect */
157 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
158 {
159 int i;
160
161 gma_write16(hw, port, GM_SMI_DATA, val);
162 gma_write16(hw, port, GM_SMI_CTRL,
163 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
164
165 for (i = 0; i < PHY_RETRIES; i++) {
166 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
167 if (ctrl == 0xffff)
168 goto io_error;
169
170 if (!(ctrl & GM_SMI_CT_BUSY))
171 return 0;
172
173 udelay(10);
174 }
175
176 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
177 return -ETIMEDOUT;
178
179 io_error:
180 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
181 return -EIO;
182 }
183
184 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
185 {
186 int i;
187
188 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
189 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
190
191 for (i = 0; i < PHY_RETRIES; i++) {
192 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
193 if (ctrl == 0xffff)
194 goto io_error;
195
196 if (ctrl & GM_SMI_CT_RD_VAL) {
197 *val = gma_read16(hw, port, GM_SMI_DATA);
198 return 0;
199 }
200
201 udelay(10);
202 }
203
204 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
205 return -ETIMEDOUT;
206 io_error:
207 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
208 return -EIO;
209 }
210
211 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
212 {
213 u16 v;
214 __gm_phy_read(hw, port, reg, &v);
215 return v;
216 }
217
218
219 static void sky2_power_on(struct sky2_hw *hw)
220 {
221 /* switch power to VCC (WA for VAUX problem) */
222 sky2_write8(hw, B0_POWER_CTRL,
223 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
224
225 /* disable Core Clock Division, */
226 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
227
228 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
229 /* enable bits are inverted */
230 sky2_write8(hw, B2_Y2_CLK_GATE,
231 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
232 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
233 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
234 else
235 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
236
237 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
238 u32 reg;
239
240 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
241
242 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
243 /* set all bits to 0 except bits 15..12 and 8 */
244 reg &= P_ASPM_CONTROL_MSK;
245 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
246
247 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
248 /* set all bits to 0 except bits 28 & 27 */
249 reg &= P_CTL_TIM_VMAIN_AV_MSK;
250 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
251
252 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
253
254 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
255 reg = sky2_read32(hw, B2_GP_IO);
256 reg |= GLB_GPIO_STAT_RACE_DIS;
257 sky2_write32(hw, B2_GP_IO, reg);
258
259 sky2_read32(hw, B2_GP_IO);
260 }
261
262 /* Turn on "driver loaded" LED */
263 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
264 }
265
266 static void sky2_power_aux(struct sky2_hw *hw)
267 {
268 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
269 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
270 else
271 /* enable bits are inverted */
272 sky2_write8(hw, B2_Y2_CLK_GATE,
273 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
274 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
275 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
276
277 /* switch power to VAUX if supported and PME from D3cold */
278 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
279 pci_pme_capable(hw->pdev, PCI_D3cold))
280 sky2_write8(hw, B0_POWER_CTRL,
281 (PC_VAUX_ENA | PC_VCC_ENA |
282 PC_VAUX_ON | PC_VCC_OFF));
283
284 /* turn off "driver loaded LED" */
285 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
286 }
287
288 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
289 {
290 u16 reg;
291
292 /* disable all GMAC IRQ's */
293 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
294
295 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
296 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
297 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
298 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
299
300 reg = gma_read16(hw, port, GM_RX_CTRL);
301 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
302 gma_write16(hw, port, GM_RX_CTRL, reg);
303 }
304
305 /* flow control to advertise bits */
306 static const u16 copper_fc_adv[] = {
307 [FC_NONE] = 0,
308 [FC_TX] = PHY_M_AN_ASP,
309 [FC_RX] = PHY_M_AN_PC,
310 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
311 };
312
313 /* flow control to advertise bits when using 1000BaseX */
314 static const u16 fiber_fc_adv[] = {
315 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
316 [FC_TX] = PHY_M_P_ASYM_MD_X,
317 [FC_RX] = PHY_M_P_SYM_MD_X,
318 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
319 };
320
321 /* flow control to GMA disable bits */
322 static const u16 gm_fc_disable[] = {
323 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
324 [FC_TX] = GM_GPCR_FC_RX_DIS,
325 [FC_RX] = GM_GPCR_FC_TX_DIS,
326 [FC_BOTH] = 0,
327 };
328
329
330 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
331 {
332 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
333 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
334
335 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
336 !(hw->flags & SKY2_HW_NEWER_PHY)) {
337 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
338
339 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
340 PHY_M_EC_MAC_S_MSK);
341 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
342
343 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
344 if (hw->chip_id == CHIP_ID_YUKON_EC)
345 /* set downshift counter to 3x and enable downshift */
346 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
347 else
348 /* set master & slave downshift counter to 1x */
349 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
350
351 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
352 }
353
354 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
355 if (sky2_is_copper(hw)) {
356 if (!(hw->flags & SKY2_HW_GIGABIT)) {
357 /* enable automatic crossover */
358 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
359
360 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
361 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
362 u16 spec;
363
364 /* Enable Class A driver for FE+ A0 */
365 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
366 spec |= PHY_M_FESC_SEL_CL_A;
367 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
368 }
369 } else {
370 /* disable energy detect */
371 ctrl &= ~PHY_M_PC_EN_DET_MSK;
372
373 /* enable automatic crossover */
374 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
375
376 /* downshift on PHY 88E1112 and 88E1149 is changed */
377 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
378 (hw->flags & SKY2_HW_NEWER_PHY)) {
379 /* set downshift counter to 3x and enable downshift */
380 ctrl &= ~PHY_M_PC_DSC_MSK;
381 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
382 }
383 }
384 } else {
385 /* workaround for deviation #4.88 (CRC errors) */
386 /* disable Automatic Crossover */
387
388 ctrl &= ~PHY_M_PC_MDIX_MSK;
389 }
390
391 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
392
393 /* special setup for PHY 88E1112 Fiber */
394 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
395 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
396
397 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
398 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
399 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
400 ctrl &= ~PHY_M_MAC_MD_MSK;
401 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
402 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
403
404 if (hw->pmd_type == 'P') {
405 /* select page 1 to access Fiber registers */
406 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
407
408 /* for SFP-module set SIGDET polarity to low */
409 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
410 ctrl |= PHY_M_FIB_SIGD_POL;
411 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
412 }
413
414 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
415 }
416
417 ctrl = PHY_CT_RESET;
418 ct1000 = 0;
419 adv = PHY_AN_CSMA;
420 reg = 0;
421
422 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
423 if (sky2_is_copper(hw)) {
424 if (sky2->advertising & ADVERTISED_1000baseT_Full)
425 ct1000 |= PHY_M_1000C_AFD;
426 if (sky2->advertising & ADVERTISED_1000baseT_Half)
427 ct1000 |= PHY_M_1000C_AHD;
428 if (sky2->advertising & ADVERTISED_100baseT_Full)
429 adv |= PHY_M_AN_100_FD;
430 if (sky2->advertising & ADVERTISED_100baseT_Half)
431 adv |= PHY_M_AN_100_HD;
432 if (sky2->advertising & ADVERTISED_10baseT_Full)
433 adv |= PHY_M_AN_10_FD;
434 if (sky2->advertising & ADVERTISED_10baseT_Half)
435 adv |= PHY_M_AN_10_HD;
436
437 } else { /* special defines for FIBER (88E1040S only) */
438 if (sky2->advertising & ADVERTISED_1000baseT_Full)
439 adv |= PHY_M_AN_1000X_AFD;
440 if (sky2->advertising & ADVERTISED_1000baseT_Half)
441 adv |= PHY_M_AN_1000X_AHD;
442 }
443
444 /* Restart Auto-negotiation */
445 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
446 } else {
447 /* forced speed/duplex settings */
448 ct1000 = PHY_M_1000C_MSE;
449
450 /* Disable auto update for duplex flow control and duplex */
451 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
452
453 switch (sky2->speed) {
454 case SPEED_1000:
455 ctrl |= PHY_CT_SP1000;
456 reg |= GM_GPCR_SPEED_1000;
457 break;
458 case SPEED_100:
459 ctrl |= PHY_CT_SP100;
460 reg |= GM_GPCR_SPEED_100;
461 break;
462 }
463
464 if (sky2->duplex == DUPLEX_FULL) {
465 reg |= GM_GPCR_DUP_FULL;
466 ctrl |= PHY_CT_DUP_MD;
467 } else if (sky2->speed < SPEED_1000)
468 sky2->flow_mode = FC_NONE;
469 }
470
471 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
472 if (sky2_is_copper(hw))
473 adv |= copper_fc_adv[sky2->flow_mode];
474 else
475 adv |= fiber_fc_adv[sky2->flow_mode];
476 } else {
477 reg |= GM_GPCR_AU_FCT_DIS;
478 reg |= gm_fc_disable[sky2->flow_mode];
479
480 /* Forward pause packets to GMAC? */
481 if (sky2->flow_mode & FC_RX)
482 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
483 else
484 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
485 }
486
487 gma_write16(hw, port, GM_GP_CTRL, reg);
488
489 if (hw->flags & SKY2_HW_GIGABIT)
490 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
491
492 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
493 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
494
495 /* Setup Phy LED's */
496 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
497 ledover = 0;
498
499 switch (hw->chip_id) {
500 case CHIP_ID_YUKON_FE:
501 /* on 88E3082 these bits are at 11..9 (shifted left) */
502 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
503
504 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
505
506 /* delete ACT LED control bits */
507 ctrl &= ~PHY_M_FELP_LED1_MSK;
508 /* change ACT LED control to blink mode */
509 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
510 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
511 break;
512
513 case CHIP_ID_YUKON_FE_P:
514 /* Enable Link Partner Next Page */
515 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
516 ctrl |= PHY_M_PC_ENA_LIP_NP;
517
518 /* disable Energy Detect and enable scrambler */
519 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
520 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
521
522 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
523 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
524 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
525 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
526
527 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
528 break;
529
530 case CHIP_ID_YUKON_XL:
531 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
532
533 /* select page 3 to access LED control register */
534 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
535
536 /* set LED Function Control register */
537 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
538 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
539 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
540 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
541 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
542
543 /* set Polarity Control register */
544 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
545 (PHY_M_POLC_LS1_P_MIX(4) |
546 PHY_M_POLC_IS0_P_MIX(4) |
547 PHY_M_POLC_LOS_CTRL(2) |
548 PHY_M_POLC_INIT_CTRL(2) |
549 PHY_M_POLC_STA1_CTRL(2) |
550 PHY_M_POLC_STA0_CTRL(2)));
551
552 /* restore page register */
553 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
554 break;
555
556 case CHIP_ID_YUKON_EC_U:
557 case CHIP_ID_YUKON_EX:
558 case CHIP_ID_YUKON_SUPR:
559 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
560
561 /* select page 3 to access LED control register */
562 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
563
564 /* set LED Function Control register */
565 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
566 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
567 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
568 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
569 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
570
571 /* set Blink Rate in LED Timer Control Register */
572 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
573 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
574 /* restore page register */
575 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
576 break;
577
578 default:
579 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
580 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
581
582 /* turn off the Rx LED (LED_RX) */
583 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
584 }
585
586 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
587 /* apply fixes in PHY AFE */
588 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
589
590 /* increase differential signal amplitude in 10BASE-T */
591 gm_phy_write(hw, port, 0x18, 0xaa99);
592 gm_phy_write(hw, port, 0x17, 0x2011);
593
594 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
595 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
596 gm_phy_write(hw, port, 0x18, 0xa204);
597 gm_phy_write(hw, port, 0x17, 0x2002);
598 }
599
600 /* set page register to 0 */
601 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
602 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
603 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
604 /* apply workaround for integrated resistors calibration */
605 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
606 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
607 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
608 /* apply fixes in PHY AFE */
609 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
610
611 /* apply RDAC termination workaround */
612 gm_phy_write(hw, port, 24, 0x2800);
613 gm_phy_write(hw, port, 23, 0x2001);
614
615 /* set page register back to 0 */
616 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
617 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
618 hw->chip_id < CHIP_ID_YUKON_SUPR) {
619 /* no effect on Yukon-XL */
620 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
621
622 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
623 sky2->speed == SPEED_100) {
624 /* turn on 100 Mbps LED (LED_LINK100) */
625 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
626 }
627
628 if (ledover)
629 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
630
631 }
632
633 /* Enable phy interrupt on auto-negotiation complete (or link up) */
634 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
635 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
636 else
637 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
638 }
639
640 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
641 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
642
643 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
644 {
645 u32 reg1;
646
647 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
648 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
649 reg1 &= ~phy_power[port];
650
651 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
652 reg1 |= coma_mode[port];
653
654 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
655 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
656 sky2_pci_read32(hw, PCI_DEV_REG1);
657
658 if (hw->chip_id == CHIP_ID_YUKON_FE)
659 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
660 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
661 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
662 }
663
664 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
665 {
666 u32 reg1;
667 u16 ctrl;
668
669 /* release GPHY Control reset */
670 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
671
672 /* release GMAC reset */
673 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
674
675 if (hw->flags & SKY2_HW_NEWER_PHY) {
676 /* select page 2 to access MAC control register */
677 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
678
679 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
680 /* allow GMII Power Down */
681 ctrl &= ~PHY_M_MAC_GMIF_PUP;
682 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
683
684 /* set page register back to 0 */
685 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
686 }
687
688 /* setup General Purpose Control Register */
689 gma_write16(hw, port, GM_GP_CTRL,
690 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
691 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
692 GM_GPCR_AU_SPD_DIS);
693
694 if (hw->chip_id != CHIP_ID_YUKON_EC) {
695 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
696 /* select page 2 to access MAC control register */
697 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
698
699 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
700 /* enable Power Down */
701 ctrl |= PHY_M_PC_POW_D_ENA;
702 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
703
704 /* set page register back to 0 */
705 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
706 }
707
708 /* set IEEE compatible Power Down Mode (dev. #4.99) */
709 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
710 }
711
712 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
713 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
714 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
715 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
716 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
717 }
718
719 /* Force a renegotiation */
720 static void sky2_phy_reinit(struct sky2_port *sky2)
721 {
722 spin_lock_bh(&sky2->phy_lock);
723 sky2_phy_init(sky2->hw, sky2->port);
724 spin_unlock_bh(&sky2->phy_lock);
725 }
726
727 /* Put device in state to listen for Wake On Lan */
728 static void sky2_wol_init(struct sky2_port *sky2)
729 {
730 struct sky2_hw *hw = sky2->hw;
731 unsigned port = sky2->port;
732 enum flow_control save_mode;
733 u16 ctrl;
734 u32 reg1;
735
736 /* Bring hardware out of reset */
737 sky2_write16(hw, B0_CTST, CS_RST_CLR);
738 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
739
740 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
741 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
742
743 /* Force to 10/100
744 * sky2_reset will re-enable on resume
745 */
746 save_mode = sky2->flow_mode;
747 ctrl = sky2->advertising;
748
749 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
750 sky2->flow_mode = FC_NONE;
751
752 spin_lock_bh(&sky2->phy_lock);
753 sky2_phy_power_up(hw, port);
754 sky2_phy_init(hw, port);
755 spin_unlock_bh(&sky2->phy_lock);
756
757 sky2->flow_mode = save_mode;
758 sky2->advertising = ctrl;
759
760 /* Set GMAC to no flow control and auto update for speed/duplex */
761 gma_write16(hw, port, GM_GP_CTRL,
762 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
763 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
764
765 /* Set WOL address */
766 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
767 sky2->netdev->dev_addr, ETH_ALEN);
768
769 /* Turn on appropriate WOL control bits */
770 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
771 ctrl = 0;
772 if (sky2->wol & WAKE_PHY)
773 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
774 else
775 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
776
777 if (sky2->wol & WAKE_MAGIC)
778 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
779 else
780 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
781
782 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
783 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
784
785 /* Turn on legacy PCI-Express PME mode */
786 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
787 reg1 |= PCI_Y2_PME_LEGACY;
788 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
789
790 /* block receiver */
791 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
792
793 }
794
795 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
796 {
797 struct net_device *dev = hw->dev[port];
798
799 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
800 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
801 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
802 /* Yukon-Extreme B0 and further Extreme devices */
803 /* enable Store & Forward mode for TX */
804
805 if (dev->mtu <= ETH_DATA_LEN)
806 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
807 TX_JUMBO_DIS | TX_STFW_ENA);
808
809 else
810 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
811 TX_JUMBO_ENA| TX_STFW_ENA);
812 } else {
813 if (dev->mtu <= ETH_DATA_LEN)
814 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
815 else {
816 /* set Tx GMAC FIFO Almost Empty Threshold */
817 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
818 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
819
820 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
821
822 /* Can't do offload because of lack of store/forward */
823 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
824 }
825 }
826 }
827
828 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
829 {
830 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
831 u16 reg;
832 u32 rx_reg;
833 int i;
834 const u8 *addr = hw->dev[port]->dev_addr;
835
836 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
837 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
838
839 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
840
841 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
842 /* WA DEV_472 -- looks like crossed wires on port 2 */
843 /* clear GMAC 1 Control reset */
844 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
845 do {
846 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
847 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
848 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
849 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
850 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
851 }
852
853 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
854
855 /* Enable Transmit FIFO Underrun */
856 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
857
858 spin_lock_bh(&sky2->phy_lock);
859 sky2_phy_power_up(hw, port);
860 sky2_phy_init(hw, port);
861 spin_unlock_bh(&sky2->phy_lock);
862
863 /* MIB clear */
864 reg = gma_read16(hw, port, GM_PHY_ADDR);
865 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
866
867 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
868 gma_read16(hw, port, i);
869 gma_write16(hw, port, GM_PHY_ADDR, reg);
870
871 /* transmit control */
872 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
873
874 /* receive control reg: unicast + multicast + no FCS */
875 gma_write16(hw, port, GM_RX_CTRL,
876 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
877
878 /* transmit flow control */
879 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
880
881 /* transmit parameter */
882 gma_write16(hw, port, GM_TX_PARAM,
883 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
884 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
885 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
886 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
887
888 /* serial mode register */
889 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
890 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
891
892 if (hw->dev[port]->mtu > ETH_DATA_LEN)
893 reg |= GM_SMOD_JUMBO_ENA;
894
895 gma_write16(hw, port, GM_SERIAL_MODE, reg);
896
897 /* virtual address for data */
898 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
899
900 /* physical address: used for pause frames */
901 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
902
903 /* ignore counter overflows */
904 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
905 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
906 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
907
908 /* Configure Rx MAC FIFO */
909 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
910 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
911 if (hw->chip_id == CHIP_ID_YUKON_EX ||
912 hw->chip_id == CHIP_ID_YUKON_FE_P)
913 rx_reg |= GMF_RX_OVER_ON;
914
915 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
916
917 if (hw->chip_id == CHIP_ID_YUKON_XL) {
918 /* Hardware errata - clear flush mask */
919 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
920 } else {
921 /* Flush Rx MAC FIFO on any flow control or error */
922 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
923 }
924
925 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
926 reg = RX_GMF_FL_THR_DEF + 1;
927 /* Another magic mystery workaround from sk98lin */
928 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
929 hw->chip_rev == CHIP_REV_YU_FE2_A0)
930 reg = 0x178;
931 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
932
933 /* Configure Tx MAC FIFO */
934 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
935 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
936
937 /* On chips without ram buffer, pause is controled by MAC level */
938 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
939 /* Pause threshold is scaled by 8 in bytes */
940 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
941 hw->chip_rev == CHIP_REV_YU_FE2_A0)
942 reg = 1568 / 8;
943 else
944 reg = 1024 / 8;
945 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
946 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
947
948 sky2_set_tx_stfwd(hw, port);
949 }
950
951 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
952 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
953 /* disable dynamic watermark */
954 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
955 reg &= ~TX_DYN_WM_ENA;
956 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
957 }
958 }
959
960 /* Assign Ram Buffer allocation to queue */
961 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
962 {
963 u32 end;
964
965 /* convert from K bytes to qwords used for hw register */
966 start *= 1024/8;
967 space *= 1024/8;
968 end = start + space - 1;
969
970 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
971 sky2_write32(hw, RB_ADDR(q, RB_START), start);
972 sky2_write32(hw, RB_ADDR(q, RB_END), end);
973 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
974 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
975
976 if (q == Q_R1 || q == Q_R2) {
977 u32 tp = space - space/4;
978
979 /* On receive queue's set the thresholds
980 * give receiver priority when > 3/4 full
981 * send pause when down to 2K
982 */
983 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
984 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
985
986 tp = space - 2048/8;
987 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
988 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
989 } else {
990 /* Enable store & forward on Tx queue's because
991 * Tx FIFO is only 1K on Yukon
992 */
993 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
994 }
995
996 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
997 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
998 }
999
1000 /* Setup Bus Memory Interface */
1001 static void sky2_qset(struct sky2_hw *hw, u16 q)
1002 {
1003 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1004 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1005 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
1006 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
1007 }
1008
1009 /* Setup prefetch unit registers. This is the interface between
1010 * hardware and driver list elements
1011 */
1012 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
1013 dma_addr_t addr, u32 last)
1014 {
1015 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1016 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
1017 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1018 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
1019 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1020 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
1021
1022 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
1023 }
1024
1025 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
1026 {
1027 struct sky2_tx_le *le = sky2->tx_le + *slot;
1028 struct tx_ring_info *re = sky2->tx_ring + *slot;
1029
1030 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
1031 re->flags = 0;
1032 re->skb = NULL;
1033 le->ctrl = 0;
1034 return le;
1035 }
1036
1037 static void tx_init(struct sky2_port *sky2)
1038 {
1039 struct sky2_tx_le *le;
1040
1041 sky2->tx_prod = sky2->tx_cons = 0;
1042 sky2->tx_tcpsum = 0;
1043 sky2->tx_last_mss = 0;
1044
1045 le = get_tx_le(sky2, &sky2->tx_prod);
1046 le->addr = 0;
1047 le->opcode = OP_ADDR64 | HW_OWNER;
1048 sky2->tx_last_upper = 0;
1049 }
1050
1051 /* Update chip's next pointer */
1052 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1053 {
1054 /* Make sure write' to descriptors are complete before we tell hardware */
1055 wmb();
1056 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1057
1058 /* Synchronize I/O on since next processor may write to tail */
1059 mmiowb();
1060 }
1061
1062
1063 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1064 {
1065 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1066 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1067 le->ctrl = 0;
1068 return le;
1069 }
1070
1071 /* Build description to hardware for one receive segment */
1072 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1073 dma_addr_t map, unsigned len)
1074 {
1075 struct sky2_rx_le *le;
1076
1077 if (sizeof(dma_addr_t) > sizeof(u32)) {
1078 le = sky2_next_rx(sky2);
1079 le->addr = cpu_to_le32(upper_32_bits(map));
1080 le->opcode = OP_ADDR64 | HW_OWNER;
1081 }
1082
1083 le = sky2_next_rx(sky2);
1084 le->addr = cpu_to_le32(lower_32_bits(map));
1085 le->length = cpu_to_le16(len);
1086 le->opcode = op | HW_OWNER;
1087 }
1088
1089 /* Build description to hardware for one possibly fragmented skb */
1090 static void sky2_rx_submit(struct sky2_port *sky2,
1091 const struct rx_ring_info *re)
1092 {
1093 int i;
1094
1095 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1096
1097 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1098 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1099 }
1100
1101
1102 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1103 unsigned size)
1104 {
1105 struct sk_buff *skb = re->skb;
1106 int i;
1107
1108 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1109 if (unlikely(pci_dma_mapping_error(pdev, re->data_addr)))
1110 return -EIO;
1111
1112 pci_unmap_len_set(re, data_size, size);
1113
1114 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1115 re->frag_addr[i] = pci_map_page(pdev,
1116 skb_shinfo(skb)->frags[i].page,
1117 skb_shinfo(skb)->frags[i].page_offset,
1118 skb_shinfo(skb)->frags[i].size,
1119 PCI_DMA_FROMDEVICE);
1120 return 0;
1121 }
1122
1123 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1124 {
1125 struct sk_buff *skb = re->skb;
1126 int i;
1127
1128 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1129 PCI_DMA_FROMDEVICE);
1130
1131 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1132 pci_unmap_page(pdev, re->frag_addr[i],
1133 skb_shinfo(skb)->frags[i].size,
1134 PCI_DMA_FROMDEVICE);
1135 }
1136
1137 /* Tell chip where to start receive checksum.
1138 * Actually has two checksums, but set both same to avoid possible byte
1139 * order problems.
1140 */
1141 static void rx_set_checksum(struct sky2_port *sky2)
1142 {
1143 struct sky2_rx_le *le = sky2_next_rx(sky2);
1144
1145 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1146 le->ctrl = 0;
1147 le->opcode = OP_TCPSTART | HW_OWNER;
1148
1149 sky2_write32(sky2->hw,
1150 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1151 (sky2->flags & SKY2_FLAG_RX_CHECKSUM)
1152 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1153 }
1154
1155 /*
1156 * The RX Stop command will not work for Yukon-2 if the BMU does not
1157 * reach the end of packet and since we can't make sure that we have
1158 * incoming data, we must reset the BMU while it is not doing a DMA
1159 * transfer. Since it is possible that the RX path is still active,
1160 * the RX RAM buffer will be stopped first, so any possible incoming
1161 * data will not trigger a DMA. After the RAM buffer is stopped, the
1162 * BMU is polled until any DMA in progress is ended and only then it
1163 * will be reset.
1164 */
1165 static void sky2_rx_stop(struct sky2_port *sky2)
1166 {
1167 struct sky2_hw *hw = sky2->hw;
1168 unsigned rxq = rxqaddr[sky2->port];
1169 int i;
1170
1171 /* disable the RAM Buffer receive queue */
1172 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1173
1174 for (i = 0; i < 0xffff; i++)
1175 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1176 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1177 goto stopped;
1178
1179 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1180 sky2->netdev->name);
1181 stopped:
1182 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1183
1184 /* reset the Rx prefetch unit */
1185 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1186 mmiowb();
1187 }
1188
1189 /* Clean out receive buffer area, assumes receiver hardware stopped */
1190 static void sky2_rx_clean(struct sky2_port *sky2)
1191 {
1192 unsigned i;
1193
1194 memset(sky2->rx_le, 0, RX_LE_BYTES);
1195 for (i = 0; i < sky2->rx_pending; i++) {
1196 struct rx_ring_info *re = sky2->rx_ring + i;
1197
1198 if (re->skb) {
1199 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1200 kfree_skb(re->skb);
1201 re->skb = NULL;
1202 }
1203 }
1204 }
1205
1206 /* Basic MII support */
1207 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1208 {
1209 struct mii_ioctl_data *data = if_mii(ifr);
1210 struct sky2_port *sky2 = netdev_priv(dev);
1211 struct sky2_hw *hw = sky2->hw;
1212 int err = -EOPNOTSUPP;
1213
1214 if (!netif_running(dev))
1215 return -ENODEV; /* Phy still in reset */
1216
1217 switch (cmd) {
1218 case SIOCGMIIPHY:
1219 data->phy_id = PHY_ADDR_MARV;
1220
1221 /* fallthru */
1222 case SIOCGMIIREG: {
1223 u16 val = 0;
1224
1225 spin_lock_bh(&sky2->phy_lock);
1226 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1227 spin_unlock_bh(&sky2->phy_lock);
1228
1229 data->val_out = val;
1230 break;
1231 }
1232
1233 case SIOCSMIIREG:
1234 spin_lock_bh(&sky2->phy_lock);
1235 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1236 data->val_in);
1237 spin_unlock_bh(&sky2->phy_lock);
1238 break;
1239 }
1240 return err;
1241 }
1242
1243 #ifdef SKY2_VLAN_TAG_USED
1244 static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
1245 {
1246 if (onoff) {
1247 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1248 RX_VLAN_STRIP_ON);
1249 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1250 TX_VLAN_TAG_ON);
1251 } else {
1252 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1253 RX_VLAN_STRIP_OFF);
1254 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1255 TX_VLAN_TAG_OFF);
1256 }
1257 }
1258
1259 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1260 {
1261 struct sky2_port *sky2 = netdev_priv(dev);
1262 struct sky2_hw *hw = sky2->hw;
1263 u16 port = sky2->port;
1264
1265 netif_tx_lock_bh(dev);
1266 napi_disable(&hw->napi);
1267
1268 sky2->vlgrp = grp;
1269 sky2_set_vlan_mode(hw, port, grp != NULL);
1270
1271 sky2_read32(hw, B0_Y2_SP_LISR);
1272 napi_enable(&hw->napi);
1273 netif_tx_unlock_bh(dev);
1274 }
1275 #endif
1276
1277 /* Amount of required worst case padding in rx buffer */
1278 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1279 {
1280 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1281 }
1282
1283 /*
1284 * Allocate an skb for receiving. If the MTU is large enough
1285 * make the skb non-linear with a fragment list of pages.
1286 */
1287 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1288 {
1289 struct sk_buff *skb;
1290 int i;
1291
1292 skb = netdev_alloc_skb(sky2->netdev,
1293 sky2->rx_data_size + sky2_rx_pad(sky2->hw));
1294 if (!skb)
1295 goto nomem;
1296
1297 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1298 unsigned char *start;
1299 /*
1300 * Workaround for a bug in FIFO that cause hang
1301 * if the FIFO if the receive buffer is not 64 byte aligned.
1302 * The buffer returned from netdev_alloc_skb is
1303 * aligned except if slab debugging is enabled.
1304 */
1305 start = PTR_ALIGN(skb->data, 8);
1306 skb_reserve(skb, start - skb->data);
1307 } else
1308 skb_reserve(skb, NET_IP_ALIGN);
1309
1310 for (i = 0; i < sky2->rx_nfrags; i++) {
1311 struct page *page = alloc_page(GFP_ATOMIC);
1312
1313 if (!page)
1314 goto free_partial;
1315 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1316 }
1317
1318 return skb;
1319 free_partial:
1320 kfree_skb(skb);
1321 nomem:
1322 return NULL;
1323 }
1324
1325 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1326 {
1327 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1328 }
1329
1330 /*
1331 * Allocate and setup receiver buffer pool.
1332 * Normal case this ends up creating one list element for skb
1333 * in the receive ring. Worst case if using large MTU and each
1334 * allocation falls on a different 64 bit region, that results
1335 * in 6 list elements per ring entry.
1336 * One element is used for checksum enable/disable, and one
1337 * extra to avoid wrap.
1338 */
1339 static int sky2_rx_start(struct sky2_port *sky2)
1340 {
1341 struct sky2_hw *hw = sky2->hw;
1342 struct rx_ring_info *re;
1343 unsigned rxq = rxqaddr[sky2->port];
1344 unsigned i, size, thresh;
1345
1346 sky2->rx_put = sky2->rx_next = 0;
1347 sky2_qset(hw, rxq);
1348
1349 /* On PCI express lowering the watermark gives better performance */
1350 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1351 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1352
1353 /* These chips have no ram buffer?
1354 * MAC Rx RAM Read is controlled by hardware */
1355 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1356 (hw->chip_rev == CHIP_REV_YU_EC_U_A1 ||
1357 hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1358 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1359
1360 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1361
1362 if (!(hw->flags & SKY2_HW_NEW_LE))
1363 rx_set_checksum(sky2);
1364
1365 /* Space needed for frame data + headers rounded up */
1366 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1367
1368 /* Stopping point for hardware truncation */
1369 thresh = (size - 8) / sizeof(u32);
1370
1371 sky2->rx_nfrags = size >> PAGE_SHIFT;
1372 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1373
1374 /* Compute residue after pages */
1375 size -= sky2->rx_nfrags << PAGE_SHIFT;
1376
1377 /* Optimize to handle small packets and headers */
1378 if (size < copybreak)
1379 size = copybreak;
1380 if (size < ETH_HLEN)
1381 size = ETH_HLEN;
1382
1383 sky2->rx_data_size = size;
1384
1385 /* Fill Rx ring */
1386 for (i = 0; i < sky2->rx_pending; i++) {
1387 re = sky2->rx_ring + i;
1388
1389 re->skb = sky2_rx_alloc(sky2);
1390 if (!re->skb)
1391 goto nomem;
1392
1393 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1394 dev_kfree_skb(re->skb);
1395 re->skb = NULL;
1396 goto nomem;
1397 }
1398
1399 sky2_rx_submit(sky2, re);
1400 }
1401
1402 /*
1403 * The receiver hangs if it receives frames larger than the
1404 * packet buffer. As a workaround, truncate oversize frames, but
1405 * the register is limited to 9 bits, so if you do frames > 2052
1406 * you better get the MTU right!
1407 */
1408 if (thresh > 0x1ff)
1409 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1410 else {
1411 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1412 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1413 }
1414
1415 /* Tell chip about available buffers */
1416 sky2_rx_update(sky2, rxq);
1417
1418 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1419 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1420 /*
1421 * Disable flushing of non ASF packets;
1422 * must be done after initializing the BMUs;
1423 * drivers without ASF support should do this too, otherwise
1424 * it may happen that they cannot run on ASF devices;
1425 * remember that the MAC FIFO isn't reset during initialization.
1426 */
1427 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1428 }
1429
1430 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1431 /* Enable RX Home Address & Routing Header checksum fix */
1432 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1433 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1434
1435 /* Enable TX Home Address & Routing Header checksum fix */
1436 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1437 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1438 }
1439
1440
1441
1442 return 0;
1443 nomem:
1444 sky2_rx_clean(sky2);
1445 return -ENOMEM;
1446 }
1447
1448 static int sky2_alloc_buffers(struct sky2_port *sky2)
1449 {
1450 struct sky2_hw *hw = sky2->hw;
1451
1452 /* must be power of 2 */
1453 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1454 sky2->tx_ring_size *
1455 sizeof(struct sky2_tx_le),
1456 &sky2->tx_le_map);
1457 if (!sky2->tx_le)
1458 goto nomem;
1459
1460 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1461 GFP_KERNEL);
1462 if (!sky2->tx_ring)
1463 goto nomem;
1464
1465 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1466 &sky2->rx_le_map);
1467 if (!sky2->rx_le)
1468 goto nomem;
1469 memset(sky2->rx_le, 0, RX_LE_BYTES);
1470
1471 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1472 GFP_KERNEL);
1473 if (!sky2->rx_ring)
1474 goto nomem;
1475
1476 return 0;
1477 nomem:
1478 return -ENOMEM;
1479 }
1480
1481 static void sky2_free_buffers(struct sky2_port *sky2)
1482 {
1483 struct sky2_hw *hw = sky2->hw;
1484
1485 if (sky2->rx_le) {
1486 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1487 sky2->rx_le, sky2->rx_le_map);
1488 sky2->rx_le = NULL;
1489 }
1490 if (sky2->tx_le) {
1491 pci_free_consistent(hw->pdev,
1492 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1493 sky2->tx_le, sky2->tx_le_map);
1494 sky2->tx_le = NULL;
1495 }
1496 kfree(sky2->tx_ring);
1497 kfree(sky2->rx_ring);
1498
1499 sky2->tx_ring = NULL;
1500 sky2->rx_ring = NULL;
1501 }
1502
1503 /* Bring up network interface. */
1504 static int sky2_up(struct net_device *dev)
1505 {
1506 struct sky2_port *sky2 = netdev_priv(dev);
1507 struct sky2_hw *hw = sky2->hw;
1508 unsigned port = sky2->port;
1509 u32 imask, ramsize;
1510 int cap, err;
1511 struct net_device *otherdev = hw->dev[sky2->port^1];
1512
1513 /*
1514 * On dual port PCI-X card, there is an problem where status
1515 * can be received out of order due to split transactions
1516 */
1517 if (otherdev && netif_running(otherdev) &&
1518 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1519 u16 cmd;
1520
1521 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1522 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1523 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1524
1525 }
1526
1527 netif_carrier_off(dev);
1528
1529 err = sky2_alloc_buffers(sky2);
1530 if (err)
1531 goto err_out;
1532
1533 tx_init(sky2);
1534
1535 sky2_mac_init(hw, port);
1536
1537 /* Register is number of 4K blocks on internal RAM buffer. */
1538 ramsize = sky2_read8(hw, B2_E_0) * 4;
1539 if (ramsize > 0) {
1540 u32 rxspace;
1541
1542 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1543 if (ramsize < 16)
1544 rxspace = ramsize / 2;
1545 else
1546 rxspace = 8 + (2*(ramsize - 16))/3;
1547
1548 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1549 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1550
1551 /* Make sure SyncQ is disabled */
1552 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1553 RB_RST_SET);
1554 }
1555
1556 sky2_qset(hw, txqaddr[port]);
1557
1558 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1559 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1560 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1561
1562 /* Set almost empty threshold */
1563 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1564 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1565 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1566
1567 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1568 sky2->tx_ring_size - 1);
1569
1570 #ifdef SKY2_VLAN_TAG_USED
1571 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1572 #endif
1573
1574 err = sky2_rx_start(sky2);
1575 if (err)
1576 goto err_out;
1577
1578 /* Enable interrupts from phy/mac for port */
1579 imask = sky2_read32(hw, B0_IMSK);
1580 imask |= portirq_msk[port];
1581 sky2_write32(hw, B0_IMSK, imask);
1582 sky2_read32(hw, B0_IMSK);
1583
1584 if (netif_msg_ifup(sky2))
1585 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1586
1587 return 0;
1588
1589 err_out:
1590 sky2_free_buffers(sky2);
1591 return err;
1592 }
1593
1594 /* Modular subtraction in ring */
1595 static inline int tx_inuse(const struct sky2_port *sky2)
1596 {
1597 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
1598 }
1599
1600 /* Number of list elements available for next tx */
1601 static inline int tx_avail(const struct sky2_port *sky2)
1602 {
1603 return sky2->tx_pending - tx_inuse(sky2);
1604 }
1605
1606 /* Estimate of number of transmit list elements required */
1607 static unsigned tx_le_req(const struct sk_buff *skb)
1608 {
1609 unsigned count;
1610
1611 count = (skb_shinfo(skb)->nr_frags + 1)
1612 * (sizeof(dma_addr_t) / sizeof(u32));
1613
1614 if (skb_is_gso(skb))
1615 ++count;
1616 else if (sizeof(dma_addr_t) == sizeof(u32))
1617 ++count; /* possible vlan */
1618
1619 if (skb->ip_summed == CHECKSUM_PARTIAL)
1620 ++count;
1621
1622 return count;
1623 }
1624
1625 static void sky2_tx_unmap(struct pci_dev *pdev,
1626 const struct tx_ring_info *re)
1627 {
1628 if (re->flags & TX_MAP_SINGLE)
1629 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1630 pci_unmap_len(re, maplen),
1631 PCI_DMA_TODEVICE);
1632 else if (re->flags & TX_MAP_PAGE)
1633 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1634 pci_unmap_len(re, maplen),
1635 PCI_DMA_TODEVICE);
1636 }
1637
1638 /*
1639 * Put one packet in ring for transmit.
1640 * A single packet can generate multiple list elements, and
1641 * the number of ring elements will probably be less than the number
1642 * of list elements used.
1643 */
1644 static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1645 struct net_device *dev)
1646 {
1647 struct sky2_port *sky2 = netdev_priv(dev);
1648 struct sky2_hw *hw = sky2->hw;
1649 struct sky2_tx_le *le = NULL;
1650 struct tx_ring_info *re;
1651 unsigned i, len;
1652 dma_addr_t mapping;
1653 u32 upper;
1654 u16 slot;
1655 u16 mss;
1656 u8 ctrl;
1657
1658 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1659 return NETDEV_TX_BUSY;
1660
1661 len = skb_headlen(skb);
1662 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1663
1664 if (pci_dma_mapping_error(hw->pdev, mapping))
1665 goto mapping_error;
1666
1667 slot = sky2->tx_prod;
1668 if (unlikely(netif_msg_tx_queued(sky2)))
1669 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1670 dev->name, slot, skb->len);
1671
1672 /* Send high bits if needed */
1673 upper = upper_32_bits(mapping);
1674 if (upper != sky2->tx_last_upper) {
1675 le = get_tx_le(sky2, &slot);
1676 le->addr = cpu_to_le32(upper);
1677 sky2->tx_last_upper = upper;
1678 le->opcode = OP_ADDR64 | HW_OWNER;
1679 }
1680
1681 /* Check for TCP Segmentation Offload */
1682 mss = skb_shinfo(skb)->gso_size;
1683 if (mss != 0) {
1684
1685 if (!(hw->flags & SKY2_HW_NEW_LE))
1686 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1687
1688 if (mss != sky2->tx_last_mss) {
1689 le = get_tx_le(sky2, &slot);
1690 le->addr = cpu_to_le32(mss);
1691
1692 if (hw->flags & SKY2_HW_NEW_LE)
1693 le->opcode = OP_MSS | HW_OWNER;
1694 else
1695 le->opcode = OP_LRGLEN | HW_OWNER;
1696 sky2->tx_last_mss = mss;
1697 }
1698 }
1699
1700 ctrl = 0;
1701 #ifdef SKY2_VLAN_TAG_USED
1702 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1703 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1704 if (!le) {
1705 le = get_tx_le(sky2, &slot);
1706 le->addr = 0;
1707 le->opcode = OP_VLAN|HW_OWNER;
1708 } else
1709 le->opcode |= OP_VLAN;
1710 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1711 ctrl |= INS_VLAN;
1712 }
1713 #endif
1714
1715 /* Handle TCP checksum offload */
1716 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1717 /* On Yukon EX (some versions) encoding change. */
1718 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1719 ctrl |= CALSUM; /* auto checksum */
1720 else {
1721 const unsigned offset = skb_transport_offset(skb);
1722 u32 tcpsum;
1723
1724 tcpsum = offset << 16; /* sum start */
1725 tcpsum |= offset + skb->csum_offset; /* sum write */
1726
1727 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1728 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1729 ctrl |= UDPTCP;
1730
1731 if (tcpsum != sky2->tx_tcpsum) {
1732 sky2->tx_tcpsum = tcpsum;
1733
1734 le = get_tx_le(sky2, &slot);
1735 le->addr = cpu_to_le32(tcpsum);
1736 le->length = 0; /* initial checksum value */
1737 le->ctrl = 1; /* one packet */
1738 le->opcode = OP_TCPLISW | HW_OWNER;
1739 }
1740 }
1741 }
1742
1743 re = sky2->tx_ring + slot;
1744 re->flags = TX_MAP_SINGLE;
1745 pci_unmap_addr_set(re, mapaddr, mapping);
1746 pci_unmap_len_set(re, maplen, len);
1747
1748 le = get_tx_le(sky2, &slot);
1749 le->addr = cpu_to_le32(lower_32_bits(mapping));
1750 le->length = cpu_to_le16(len);
1751 le->ctrl = ctrl;
1752 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1753
1754
1755 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1756 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1757
1758 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1759 frag->size, PCI_DMA_TODEVICE);
1760
1761 if (pci_dma_mapping_error(hw->pdev, mapping))
1762 goto mapping_unwind;
1763
1764 upper = upper_32_bits(mapping);
1765 if (upper != sky2->tx_last_upper) {
1766 le = get_tx_le(sky2, &slot);
1767 le->addr = cpu_to_le32(upper);
1768 sky2->tx_last_upper = upper;
1769 le->opcode = OP_ADDR64 | HW_OWNER;
1770 }
1771
1772 re = sky2->tx_ring + slot;
1773 re->flags = TX_MAP_PAGE;
1774 pci_unmap_addr_set(re, mapaddr, mapping);
1775 pci_unmap_len_set(re, maplen, frag->size);
1776
1777 le = get_tx_le(sky2, &slot);
1778 le->addr = cpu_to_le32(lower_32_bits(mapping));
1779 le->length = cpu_to_le16(frag->size);
1780 le->ctrl = ctrl;
1781 le->opcode = OP_BUFFER | HW_OWNER;
1782 }
1783
1784 re->skb = skb;
1785 le->ctrl |= EOP;
1786
1787 sky2->tx_prod = slot;
1788
1789 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1790 netif_stop_queue(dev);
1791
1792 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1793
1794 return NETDEV_TX_OK;
1795
1796 mapping_unwind:
1797 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
1798 re = sky2->tx_ring + i;
1799
1800 sky2_tx_unmap(hw->pdev, re);
1801 }
1802
1803 mapping_error:
1804 if (net_ratelimit())
1805 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1806 dev_kfree_skb(skb);
1807 return NETDEV_TX_OK;
1808 }
1809
1810 /*
1811 * Free ring elements from starting at tx_cons until "done"
1812 *
1813 * NB:
1814 * 1. The hardware will tell us about partial completion of multi-part
1815 * buffers so make sure not to free skb to early.
1816 * 2. This may run in parallel start_xmit because the it only
1817 * looks at the tail of the queue of FIFO (tx_cons), not
1818 * the head (tx_prod)
1819 */
1820 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1821 {
1822 struct net_device *dev = sky2->netdev;
1823 unsigned idx;
1824
1825 BUG_ON(done >= sky2->tx_ring_size);
1826
1827 for (idx = sky2->tx_cons; idx != done;
1828 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
1829 struct tx_ring_info *re = sky2->tx_ring + idx;
1830 struct sk_buff *skb = re->skb;
1831
1832 sky2_tx_unmap(sky2->hw->pdev, re);
1833
1834 if (skb) {
1835 if (unlikely(netif_msg_tx_done(sky2)))
1836 printk(KERN_DEBUG "%s: tx done %u\n",
1837 dev->name, idx);
1838
1839 dev->stats.tx_packets++;
1840 dev->stats.tx_bytes += skb->len;
1841
1842 dev_kfree_skb_any(skb);
1843
1844 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
1845 }
1846 }
1847
1848 sky2->tx_cons = idx;
1849 smp_mb();
1850
1851 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1852 netif_wake_queue(dev);
1853 }
1854
1855 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
1856 {
1857 /* Disable Force Sync bit and Enable Alloc bit */
1858 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1859 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1860
1861 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1862 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1863 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1864
1865 /* Reset the PCI FIFO of the async Tx queue */
1866 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1867 BMU_RST_SET | BMU_FIFO_RST);
1868
1869 /* Reset the Tx prefetch units */
1870 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1871 PREF_UNIT_RST_SET);
1872
1873 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1874 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1875 }
1876
1877 /* Network shutdown */
1878 static int sky2_down(struct net_device *dev)
1879 {
1880 struct sky2_port *sky2 = netdev_priv(dev);
1881 struct sky2_hw *hw = sky2->hw;
1882 unsigned port = sky2->port;
1883 u16 ctrl;
1884 u32 imask;
1885
1886 /* Never really got started! */
1887 if (!sky2->tx_le)
1888 return 0;
1889
1890 if (netif_msg_ifdown(sky2))
1891 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1892
1893 /* Force flow control off */
1894 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1895
1896 /* Stop transmitter */
1897 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1898 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1899
1900 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1901 RB_RST_SET | RB_DIS_OP_MD);
1902
1903 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1904 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1905 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1906
1907 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1908
1909 /* Workaround shared GMAC reset */
1910 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
1911 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1912 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1913
1914 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1915
1916 /* Force any delayed status interrrupt and NAPI */
1917 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1918 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1919 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1920 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1921
1922 sky2_rx_stop(sky2);
1923
1924 /* Disable port IRQ */
1925 imask = sky2_read32(hw, B0_IMSK);
1926 imask &= ~portirq_msk[port];
1927 sky2_write32(hw, B0_IMSK, imask);
1928 sky2_read32(hw, B0_IMSK);
1929
1930 synchronize_irq(hw->pdev->irq);
1931 napi_synchronize(&hw->napi);
1932
1933 spin_lock_bh(&sky2->phy_lock);
1934 sky2_phy_power_down(hw, port);
1935 spin_unlock_bh(&sky2->phy_lock);
1936
1937 sky2_tx_reset(hw, port);
1938
1939 /* Free any pending frames stuck in HW queue */
1940 sky2_tx_complete(sky2, sky2->tx_prod);
1941
1942 sky2_rx_clean(sky2);
1943
1944 sky2_free_buffers(sky2);
1945
1946 return 0;
1947 }
1948
1949 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1950 {
1951 if (hw->flags & SKY2_HW_FIBRE_PHY)
1952 return SPEED_1000;
1953
1954 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1955 if (aux & PHY_M_PS_SPEED_100)
1956 return SPEED_100;
1957 else
1958 return SPEED_10;
1959 }
1960
1961 switch (aux & PHY_M_PS_SPEED_MSK) {
1962 case PHY_M_PS_SPEED_1000:
1963 return SPEED_1000;
1964 case PHY_M_PS_SPEED_100:
1965 return SPEED_100;
1966 default:
1967 return SPEED_10;
1968 }
1969 }
1970
1971 static void sky2_link_up(struct sky2_port *sky2)
1972 {
1973 struct sky2_hw *hw = sky2->hw;
1974 unsigned port = sky2->port;
1975 u16 reg;
1976 static const char *fc_name[] = {
1977 [FC_NONE] = "none",
1978 [FC_TX] = "tx",
1979 [FC_RX] = "rx",
1980 [FC_BOTH] = "both",
1981 };
1982
1983 /* enable Rx/Tx */
1984 reg = gma_read16(hw, port, GM_GP_CTRL);
1985 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1986 gma_write16(hw, port, GM_GP_CTRL, reg);
1987
1988 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1989
1990 netif_carrier_on(sky2->netdev);
1991
1992 mod_timer(&hw->watchdog_timer, jiffies + 1);
1993
1994 /* Turn on link LED */
1995 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1996 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1997
1998 if (netif_msg_link(sky2))
1999 printk(KERN_INFO PFX
2000 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
2001 sky2->netdev->name, sky2->speed,
2002 sky2->duplex == DUPLEX_FULL ? "full" : "half",
2003 fc_name[sky2->flow_status]);
2004 }
2005
2006 static void sky2_link_down(struct sky2_port *sky2)
2007 {
2008 struct sky2_hw *hw = sky2->hw;
2009 unsigned port = sky2->port;
2010 u16 reg;
2011
2012 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2013
2014 reg = gma_read16(hw, port, GM_GP_CTRL);
2015 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2016 gma_write16(hw, port, GM_GP_CTRL, reg);
2017
2018 netif_carrier_off(sky2->netdev);
2019
2020 /* Turn off link LED */
2021 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2022
2023 if (netif_msg_link(sky2))
2024 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2025
2026 sky2_phy_init(hw, port);
2027 }
2028
2029 static enum flow_control sky2_flow(int rx, int tx)
2030 {
2031 if (rx)
2032 return tx ? FC_BOTH : FC_RX;
2033 else
2034 return tx ? FC_TX : FC_NONE;
2035 }
2036
2037 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2038 {
2039 struct sky2_hw *hw = sky2->hw;
2040 unsigned port = sky2->port;
2041 u16 advert, lpa;
2042
2043 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2044 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
2045 if (lpa & PHY_M_AN_RF) {
2046 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
2047 return -1;
2048 }
2049
2050 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2051 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
2052 sky2->netdev->name);
2053 return -1;
2054 }
2055
2056 sky2->speed = sky2_phy_speed(hw, aux);
2057 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2058
2059 /* Since the pause result bits seem to in different positions on
2060 * different chips. look at registers.
2061 */
2062 if (hw->flags & SKY2_HW_FIBRE_PHY) {
2063 /* Shift for bits in fiber PHY */
2064 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2065 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2066
2067 if (advert & ADVERTISE_1000XPAUSE)
2068 advert |= ADVERTISE_PAUSE_CAP;
2069 if (advert & ADVERTISE_1000XPSE_ASYM)
2070 advert |= ADVERTISE_PAUSE_ASYM;
2071 if (lpa & LPA_1000XPAUSE)
2072 lpa |= LPA_PAUSE_CAP;
2073 if (lpa & LPA_1000XPAUSE_ASYM)
2074 lpa |= LPA_PAUSE_ASYM;
2075 }
2076
2077 sky2->flow_status = FC_NONE;
2078 if (advert & ADVERTISE_PAUSE_CAP) {
2079 if (lpa & LPA_PAUSE_CAP)
2080 sky2->flow_status = FC_BOTH;
2081 else if (advert & ADVERTISE_PAUSE_ASYM)
2082 sky2->flow_status = FC_RX;
2083 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2084 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2085 sky2->flow_status = FC_TX;
2086 }
2087
2088 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2089 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2090 sky2->flow_status = FC_NONE;
2091
2092 if (sky2->flow_status & FC_TX)
2093 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2094 else
2095 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2096
2097 return 0;
2098 }
2099
2100 /* Interrupt from PHY */
2101 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2102 {
2103 struct net_device *dev = hw->dev[port];
2104 struct sky2_port *sky2 = netdev_priv(dev);
2105 u16 istatus, phystat;
2106
2107 if (!netif_running(dev))
2108 return;
2109
2110 spin_lock(&sky2->phy_lock);
2111 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2112 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2113
2114 if (netif_msg_intr(sky2))
2115 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2116 sky2->netdev->name, istatus, phystat);
2117
2118 if (istatus & PHY_M_IS_AN_COMPL) {
2119 if (sky2_autoneg_done(sky2, phystat) == 0)
2120 sky2_link_up(sky2);
2121 goto out;
2122 }
2123
2124 if (istatus & PHY_M_IS_LSP_CHANGE)
2125 sky2->speed = sky2_phy_speed(hw, phystat);
2126
2127 if (istatus & PHY_M_IS_DUP_CHANGE)
2128 sky2->duplex =
2129 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2130
2131 if (istatus & PHY_M_IS_LST_CHANGE) {
2132 if (phystat & PHY_M_PS_LINK_UP)
2133 sky2_link_up(sky2);
2134 else
2135 sky2_link_down(sky2);
2136 }
2137 out:
2138 spin_unlock(&sky2->phy_lock);
2139 }
2140
2141 /* Special quick link interrupt (Yukon-2 Optima only) */
2142 static void sky2_qlink_intr(struct sky2_hw *hw)
2143 {
2144 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2145 u32 imask;
2146 u16 phy;
2147
2148 /* disable irq */
2149 imask = sky2_read32(hw, B0_IMSK);
2150 imask &= ~Y2_IS_PHY_QLNK;
2151 sky2_write32(hw, B0_IMSK, imask);
2152
2153 /* reset PHY Link Detect */
2154 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
2155 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2156 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
2157 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2158
2159 sky2_link_up(sky2);
2160 }
2161
2162 /* Transmit timeout is only called if we are running, carrier is up
2163 * and tx queue is full (stopped).
2164 */
2165 static void sky2_tx_timeout(struct net_device *dev)
2166 {
2167 struct sky2_port *sky2 = netdev_priv(dev);
2168 struct sky2_hw *hw = sky2->hw;
2169
2170 if (netif_msg_timer(sky2))
2171 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2172
2173 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
2174 dev->name, sky2->tx_cons, sky2->tx_prod,
2175 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2176 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2177
2178 /* can't restart safely under softirq */
2179 schedule_work(&hw->restart_work);
2180 }
2181
2182 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2183 {
2184 struct sky2_port *sky2 = netdev_priv(dev);
2185 struct sky2_hw *hw = sky2->hw;
2186 unsigned port = sky2->port;
2187 int err;
2188 u16 ctl, mode;
2189 u32 imask;
2190
2191 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2192 return -EINVAL;
2193
2194 if (new_mtu > ETH_DATA_LEN &&
2195 (hw->chip_id == CHIP_ID_YUKON_FE ||
2196 hw->chip_id == CHIP_ID_YUKON_FE_P))
2197 return -EINVAL;
2198
2199 if (!netif_running(dev)) {
2200 dev->mtu = new_mtu;
2201 return 0;
2202 }
2203
2204 imask = sky2_read32(hw, B0_IMSK);
2205 sky2_write32(hw, B0_IMSK, 0);
2206
2207 dev->trans_start = jiffies; /* prevent tx timeout */
2208 netif_stop_queue(dev);
2209 napi_disable(&hw->napi);
2210
2211 synchronize_irq(hw->pdev->irq);
2212
2213 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2214 sky2_set_tx_stfwd(hw, port);
2215
2216 ctl = gma_read16(hw, port, GM_GP_CTRL);
2217 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2218 sky2_rx_stop(sky2);
2219 sky2_rx_clean(sky2);
2220
2221 dev->mtu = new_mtu;
2222
2223 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2224 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2225
2226 if (dev->mtu > ETH_DATA_LEN)
2227 mode |= GM_SMOD_JUMBO_ENA;
2228
2229 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2230
2231 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2232
2233 err = sky2_rx_start(sky2);
2234 sky2_write32(hw, B0_IMSK, imask);
2235
2236 sky2_read32(hw, B0_Y2_SP_LISR);
2237 napi_enable(&hw->napi);
2238
2239 if (err)
2240 dev_close(dev);
2241 else {
2242 gma_write16(hw, port, GM_GP_CTRL, ctl);
2243
2244 netif_wake_queue(dev);
2245 }
2246
2247 return err;
2248 }
2249
2250 /* For small just reuse existing skb for next receive */
2251 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2252 const struct rx_ring_info *re,
2253 unsigned length)
2254 {
2255 struct sk_buff *skb;
2256
2257 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
2258 if (likely(skb)) {
2259 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2260 length, PCI_DMA_FROMDEVICE);
2261 skb_copy_from_linear_data(re->skb, skb->data, length);
2262 skb->ip_summed = re->skb->ip_summed;
2263 skb->csum = re->skb->csum;
2264 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2265 length, PCI_DMA_FROMDEVICE);
2266 re->skb->ip_summed = CHECKSUM_NONE;
2267 skb_put(skb, length);
2268 }
2269 return skb;
2270 }
2271
2272 /* Adjust length of skb with fragments to match received data */
2273 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2274 unsigned int length)
2275 {
2276 int i, num_frags;
2277 unsigned int size;
2278
2279 /* put header into skb */
2280 size = min(length, hdr_space);
2281 skb->tail += size;
2282 skb->len += size;
2283 length -= size;
2284
2285 num_frags = skb_shinfo(skb)->nr_frags;
2286 for (i = 0; i < num_frags; i++) {
2287 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2288
2289 if (length == 0) {
2290 /* don't need this page */
2291 __free_page(frag->page);
2292 --skb_shinfo(skb)->nr_frags;
2293 } else {
2294 size = min(length, (unsigned) PAGE_SIZE);
2295
2296 frag->size = size;
2297 skb->data_len += size;
2298 skb->truesize += size;
2299 skb->len += size;
2300 length -= size;
2301 }
2302 }
2303 }
2304
2305 /* Normal packet - take skb from ring element and put in a new one */
2306 static struct sk_buff *receive_new(struct sky2_port *sky2,
2307 struct rx_ring_info *re,
2308 unsigned int length)
2309 {
2310 struct sk_buff *skb, *nskb;
2311 unsigned hdr_space = sky2->rx_data_size;
2312
2313 /* Don't be tricky about reusing pages (yet) */
2314 nskb = sky2_rx_alloc(sky2);
2315 if (unlikely(!nskb))
2316 return NULL;
2317
2318 skb = re->skb;
2319 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2320
2321 prefetch(skb->data);
2322 re->skb = nskb;
2323 if (sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space)) {
2324 dev_kfree_skb(nskb);
2325 re->skb = skb;
2326 return NULL;
2327 }
2328
2329 if (skb_shinfo(skb)->nr_frags)
2330 skb_put_frags(skb, hdr_space, length);
2331 else
2332 skb_put(skb, length);
2333 return skb;
2334 }
2335
2336 /*
2337 * Receive one packet.
2338 * For larger packets, get new buffer.
2339 */
2340 static struct sk_buff *sky2_receive(struct net_device *dev,
2341 u16 length, u32 status)
2342 {
2343 struct sky2_port *sky2 = netdev_priv(dev);
2344 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2345 struct sk_buff *skb = NULL;
2346 u16 count = (status & GMR_FS_LEN) >> 16;
2347
2348 #ifdef SKY2_VLAN_TAG_USED
2349 /* Account for vlan tag */
2350 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2351 count -= VLAN_HLEN;
2352 #endif
2353
2354 if (unlikely(netif_msg_rx_status(sky2)))
2355 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2356 dev->name, sky2->rx_next, status, length);
2357
2358 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2359 prefetch(sky2->rx_ring + sky2->rx_next);
2360
2361 /* This chip has hardware problems that generates bogus status.
2362 * So do only marginal checking and expect higher level protocols
2363 * to handle crap frames.
2364 */
2365 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2366 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2367 length != count)
2368 goto okay;
2369
2370 if (status & GMR_FS_ANY_ERR)
2371 goto error;
2372
2373 if (!(status & GMR_FS_RX_OK))
2374 goto resubmit;
2375
2376 /* if length reported by DMA does not match PHY, packet was truncated */
2377 if (length != count)
2378 goto len_error;
2379
2380 okay:
2381 if (length < copybreak)
2382 skb = receive_copy(sky2, re, length);
2383 else
2384 skb = receive_new(sky2, re, length);
2385 resubmit:
2386 sky2_rx_submit(sky2, re);
2387
2388 return skb;
2389
2390 len_error:
2391 /* Truncation of overlength packets
2392 causes PHY length to not match MAC length */
2393 ++dev->stats.rx_length_errors;
2394 if (netif_msg_rx_err(sky2) && net_ratelimit())
2395 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2396 dev->name, status, length);
2397 goto resubmit;
2398
2399 error:
2400 ++dev->stats.rx_errors;
2401 if (status & GMR_FS_RX_FF_OV) {
2402 dev->stats.rx_over_errors++;
2403 goto resubmit;
2404 }
2405
2406 if (netif_msg_rx_err(sky2) && net_ratelimit())
2407 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2408 dev->name, status, length);
2409
2410 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2411 dev->stats.rx_length_errors++;
2412 if (status & GMR_FS_FRAGMENT)
2413 dev->stats.rx_frame_errors++;
2414 if (status & GMR_FS_CRC_ERR)
2415 dev->stats.rx_crc_errors++;
2416
2417 goto resubmit;
2418 }
2419
2420 /* Transmit complete */
2421 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2422 {
2423 struct sky2_port *sky2 = netdev_priv(dev);
2424
2425 if (netif_running(dev))
2426 sky2_tx_complete(sky2, last);
2427 }
2428
2429 static inline void sky2_skb_rx(const struct sky2_port *sky2,
2430 u32 status, struct sk_buff *skb)
2431 {
2432 #ifdef SKY2_VLAN_TAG_USED
2433 u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
2434 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2435 if (skb->ip_summed == CHECKSUM_NONE)
2436 vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
2437 else
2438 vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
2439 vlan_tag, skb);
2440 return;
2441 }
2442 #endif
2443 if (skb->ip_summed == CHECKSUM_NONE)
2444 netif_receive_skb(skb);
2445 else
2446 napi_gro_receive(&sky2->hw->napi, skb);
2447 }
2448
2449 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2450 unsigned packets, unsigned bytes)
2451 {
2452 if (packets) {
2453 struct net_device *dev = hw->dev[port];
2454
2455 dev->stats.rx_packets += packets;
2456 dev->stats.rx_bytes += bytes;
2457 dev->last_rx = jiffies;
2458 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2459 }
2460 }
2461
2462 /* Process status response ring */
2463 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2464 {
2465 int work_done = 0;
2466 unsigned int total_bytes[2] = { 0 };
2467 unsigned int total_packets[2] = { 0 };
2468
2469 rmb();
2470 do {
2471 struct sky2_port *sky2;
2472 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2473 unsigned port;
2474 struct net_device *dev;
2475 struct sk_buff *skb;
2476 u32 status;
2477 u16 length;
2478 u8 opcode = le->opcode;
2479
2480 if (!(opcode & HW_OWNER))
2481 break;
2482
2483 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2484
2485 port = le->css & CSS_LINK_BIT;
2486 dev = hw->dev[port];
2487 sky2 = netdev_priv(dev);
2488 length = le16_to_cpu(le->length);
2489 status = le32_to_cpu(le->status);
2490
2491 le->opcode = 0;
2492 switch (opcode & ~HW_OWNER) {
2493 case OP_RXSTAT:
2494 total_packets[port]++;
2495 total_bytes[port] += length;
2496 skb = sky2_receive(dev, length, status);
2497 if (unlikely(!skb)) {
2498 dev->stats.rx_dropped++;
2499 break;
2500 }
2501
2502 /* This chip reports checksum status differently */
2503 if (hw->flags & SKY2_HW_NEW_LE) {
2504 if ((sky2->flags & SKY2_FLAG_RX_CHECKSUM) &&
2505 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2506 (le->css & CSS_TCPUDPCSOK))
2507 skb->ip_summed = CHECKSUM_UNNECESSARY;
2508 else
2509 skb->ip_summed = CHECKSUM_NONE;
2510 }
2511
2512 skb->protocol = eth_type_trans(skb, dev);
2513
2514 sky2_skb_rx(sky2, status, skb);
2515
2516 /* Stop after net poll weight */
2517 if (++work_done >= to_do)
2518 goto exit_loop;
2519 break;
2520
2521 #ifdef SKY2_VLAN_TAG_USED
2522 case OP_RXVLAN:
2523 sky2->rx_tag = length;
2524 break;
2525
2526 case OP_RXCHKSVLAN:
2527 sky2->rx_tag = length;
2528 /* fall through */
2529 #endif
2530 case OP_RXCHKS:
2531 if (!(sky2->flags & SKY2_FLAG_RX_CHECKSUM))
2532 break;
2533
2534 /* If this happens then driver assuming wrong format */
2535 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2536 if (net_ratelimit())
2537 printk(KERN_NOTICE "%s: unexpected"
2538 " checksum status\n",
2539 dev->name);
2540 break;
2541 }
2542
2543 /* Both checksum counters are programmed to start at
2544 * the same offset, so unless there is a problem they
2545 * should match. This failure is an early indication that
2546 * hardware receive checksumming won't work.
2547 */
2548 if (likely(status >> 16 == (status & 0xffff))) {
2549 skb = sky2->rx_ring[sky2->rx_next].skb;
2550 skb->ip_summed = CHECKSUM_COMPLETE;
2551 skb->csum = le16_to_cpu(status);
2552 } else {
2553 printk(KERN_NOTICE PFX "%s: hardware receive "
2554 "checksum problem (status = %#x)\n",
2555 dev->name, status);
2556 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
2557
2558 sky2_write32(sky2->hw,
2559 Q_ADDR(rxqaddr[port], Q_CSR),
2560 BMU_DIS_RX_CHKSUM);
2561 }
2562 break;
2563
2564 case OP_TXINDEXLE:
2565 /* TX index reports status for both ports */
2566 sky2_tx_done(hw->dev[0], status & 0xfff);
2567 if (hw->dev[1])
2568 sky2_tx_done(hw->dev[1],
2569 ((status >> 24) & 0xff)
2570 | (u16)(length & 0xf) << 8);
2571 break;
2572
2573 default:
2574 if (net_ratelimit())
2575 printk(KERN_WARNING PFX
2576 "unknown status opcode 0x%x\n", opcode);
2577 }
2578 } while (hw->st_idx != idx);
2579
2580 /* Fully processed status ring so clear irq */
2581 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2582
2583 exit_loop:
2584 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2585 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
2586
2587 return work_done;
2588 }
2589
2590 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2591 {
2592 struct net_device *dev = hw->dev[port];
2593
2594 if (net_ratelimit())
2595 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2596 dev->name, status);
2597
2598 if (status & Y2_IS_PAR_RD1) {
2599 if (net_ratelimit())
2600 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2601 dev->name);
2602 /* Clear IRQ */
2603 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2604 }
2605
2606 if (status & Y2_IS_PAR_WR1) {
2607 if (net_ratelimit())
2608 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2609 dev->name);
2610
2611 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2612 }
2613
2614 if (status & Y2_IS_PAR_MAC1) {
2615 if (net_ratelimit())
2616 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2617 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2618 }
2619
2620 if (status & Y2_IS_PAR_RX1) {
2621 if (net_ratelimit())
2622 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2623 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2624 }
2625
2626 if (status & Y2_IS_TCP_TXA1) {
2627 if (net_ratelimit())
2628 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2629 dev->name);
2630 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2631 }
2632 }
2633
2634 static void sky2_hw_intr(struct sky2_hw *hw)
2635 {
2636 struct pci_dev *pdev = hw->pdev;
2637 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2638 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2639
2640 status &= hwmsk;
2641
2642 if (status & Y2_IS_TIST_OV)
2643 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2644
2645 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2646 u16 pci_err;
2647
2648 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2649 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2650 if (net_ratelimit())
2651 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2652 pci_err);
2653
2654 sky2_pci_write16(hw, PCI_STATUS,
2655 pci_err | PCI_STATUS_ERROR_BITS);
2656 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2657 }
2658
2659 if (status & Y2_IS_PCI_EXP) {
2660 /* PCI-Express uncorrectable Error occurred */
2661 u32 err;
2662
2663 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2664 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2665 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2666 0xfffffffful);
2667 if (net_ratelimit())
2668 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2669
2670 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2671 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2672 }
2673
2674 if (status & Y2_HWE_L1_MASK)
2675 sky2_hw_error(hw, 0, status);
2676 status >>= 8;
2677 if (status & Y2_HWE_L1_MASK)
2678 sky2_hw_error(hw, 1, status);
2679 }
2680
2681 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2682 {
2683 struct net_device *dev = hw->dev[port];
2684 struct sky2_port *sky2 = netdev_priv(dev);
2685 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2686
2687 if (netif_msg_intr(sky2))
2688 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2689 dev->name, status);
2690
2691 if (status & GM_IS_RX_CO_OV)
2692 gma_read16(hw, port, GM_RX_IRQ_SRC);
2693
2694 if (status & GM_IS_TX_CO_OV)
2695 gma_read16(hw, port, GM_TX_IRQ_SRC);
2696
2697 if (status & GM_IS_RX_FF_OR) {
2698 ++dev->stats.rx_fifo_errors;
2699 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2700 }
2701
2702 if (status & GM_IS_TX_FF_UR) {
2703 ++dev->stats.tx_fifo_errors;
2704 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2705 }
2706 }
2707
2708 /* This should never happen it is a bug. */
2709 static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
2710 {
2711 struct net_device *dev = hw->dev[port];
2712 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2713
2714 dev_err(&hw->pdev->dev, PFX
2715 "%s: descriptor error q=%#x get=%u put=%u\n",
2716 dev->name, (unsigned) q, (unsigned) idx,
2717 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2718
2719 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2720 }
2721
2722 static int sky2_rx_hung(struct net_device *dev)
2723 {
2724 struct sky2_port *sky2 = netdev_priv(dev);
2725 struct sky2_hw *hw = sky2->hw;
2726 unsigned port = sky2->port;
2727 unsigned rxq = rxqaddr[port];
2728 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2729 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2730 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2731 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2732
2733 /* If idle and MAC or PCI is stuck */
2734 if (sky2->check.last == dev->last_rx &&
2735 ((mac_rp == sky2->check.mac_rp &&
2736 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2737 /* Check if the PCI RX hang */
2738 (fifo_rp == sky2->check.fifo_rp &&
2739 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2740 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2741 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2742 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2743 return 1;
2744 } else {
2745 sky2->check.last = dev->last_rx;
2746 sky2->check.mac_rp = mac_rp;
2747 sky2->check.mac_lev = mac_lev;
2748 sky2->check.fifo_rp = fifo_rp;
2749 sky2->check.fifo_lev = fifo_lev;
2750 return 0;
2751 }
2752 }
2753
2754 static void sky2_watchdog(unsigned long arg)
2755 {
2756 struct sky2_hw *hw = (struct sky2_hw *) arg;
2757
2758 /* Check for lost IRQ once a second */
2759 if (sky2_read32(hw, B0_ISRC)) {
2760 napi_schedule(&hw->napi);
2761 } else {
2762 int i, active = 0;
2763
2764 for (i = 0; i < hw->ports; i++) {
2765 struct net_device *dev = hw->dev[i];
2766 if (!netif_running(dev))
2767 continue;
2768 ++active;
2769
2770 /* For chips with Rx FIFO, check if stuck */
2771 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2772 sky2_rx_hung(dev)) {
2773 pr_info(PFX "%s: receiver hang detected\n",
2774 dev->name);
2775 schedule_work(&hw->restart_work);
2776 return;
2777 }
2778 }
2779
2780 if (active == 0)
2781 return;
2782 }
2783
2784 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2785 }
2786
2787 /* Hardware/software error handling */
2788 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2789 {
2790 if (net_ratelimit())
2791 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2792
2793 if (status & Y2_IS_HW_ERR)
2794 sky2_hw_intr(hw);
2795
2796 if (status & Y2_IS_IRQ_MAC1)
2797 sky2_mac_intr(hw, 0);
2798
2799 if (status & Y2_IS_IRQ_MAC2)
2800 sky2_mac_intr(hw, 1);
2801
2802 if (status & Y2_IS_CHK_RX1)
2803 sky2_le_error(hw, 0, Q_R1);
2804
2805 if (status & Y2_IS_CHK_RX2)
2806 sky2_le_error(hw, 1, Q_R2);
2807
2808 if (status & Y2_IS_CHK_TXA1)
2809 sky2_le_error(hw, 0, Q_XA1);
2810
2811 if (status & Y2_IS_CHK_TXA2)
2812 sky2_le_error(hw, 1, Q_XA2);
2813 }
2814
2815 static int sky2_poll(struct napi_struct *napi, int work_limit)
2816 {
2817 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2818 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2819 int work_done = 0;
2820 u16 idx;
2821
2822 if (unlikely(status & Y2_IS_ERROR))
2823 sky2_err_intr(hw, status);
2824
2825 if (status & Y2_IS_IRQ_PHY1)
2826 sky2_phy_intr(hw, 0);
2827
2828 if (status & Y2_IS_IRQ_PHY2)
2829 sky2_phy_intr(hw, 1);
2830
2831 if (status & Y2_IS_PHY_QLNK)
2832 sky2_qlink_intr(hw);
2833
2834 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2835 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2836
2837 if (work_done >= work_limit)
2838 goto done;
2839 }
2840
2841 napi_complete(napi);
2842 sky2_read32(hw, B0_Y2_SP_LISR);
2843 done:
2844
2845 return work_done;
2846 }
2847
2848 static irqreturn_t sky2_intr(int irq, void *dev_id)
2849 {
2850 struct sky2_hw *hw = dev_id;
2851 u32 status;
2852
2853 /* Reading this mask interrupts as side effect */
2854 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2855 if (status == 0 || status == ~0)
2856 return IRQ_NONE;
2857
2858 prefetch(&hw->st_le[hw->st_idx]);
2859
2860 napi_schedule(&hw->napi);
2861
2862 return IRQ_HANDLED;
2863 }
2864
2865 #ifdef CONFIG_NET_POLL_CONTROLLER
2866 static void sky2_netpoll(struct net_device *dev)
2867 {
2868 struct sky2_port *sky2 = netdev_priv(dev);
2869
2870 napi_schedule(&sky2->hw->napi);
2871 }
2872 #endif
2873
2874 /* Chip internal frequency for clock calculations */
2875 static u32 sky2_mhz(const struct sky2_hw *hw)
2876 {
2877 switch (hw->chip_id) {
2878 case CHIP_ID_YUKON_EC:
2879 case CHIP_ID_YUKON_EC_U:
2880 case CHIP_ID_YUKON_EX:
2881 case CHIP_ID_YUKON_SUPR:
2882 case CHIP_ID_YUKON_UL_2:
2883 case CHIP_ID_YUKON_OPT:
2884 return 125;
2885
2886 case CHIP_ID_YUKON_FE:
2887 return 100;
2888
2889 case CHIP_ID_YUKON_FE_P:
2890 return 50;
2891
2892 case CHIP_ID_YUKON_XL:
2893 return 156;
2894
2895 default:
2896 BUG();
2897 }
2898 }
2899
2900 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2901 {
2902 return sky2_mhz(hw) * us;
2903 }
2904
2905 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2906 {
2907 return clk / sky2_mhz(hw);
2908 }
2909
2910
2911 static int __devinit sky2_init(struct sky2_hw *hw)
2912 {
2913 u8 t8;
2914
2915 /* Enable all clocks and check for bad PCI access */
2916 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2917
2918 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2919
2920 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2921 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2922
2923 switch(hw->chip_id) {
2924 case CHIP_ID_YUKON_XL:
2925 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
2926 break;
2927
2928 case CHIP_ID_YUKON_EC_U:
2929 hw->flags = SKY2_HW_GIGABIT
2930 | SKY2_HW_NEWER_PHY
2931 | SKY2_HW_ADV_POWER_CTL;
2932 break;
2933
2934 case CHIP_ID_YUKON_EX:
2935 hw->flags = SKY2_HW_GIGABIT
2936 | SKY2_HW_NEWER_PHY
2937 | SKY2_HW_NEW_LE
2938 | SKY2_HW_ADV_POWER_CTL;
2939
2940 /* New transmit checksum */
2941 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2942 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2943 break;
2944
2945 case CHIP_ID_YUKON_EC:
2946 /* This rev is really old, and requires untested workarounds */
2947 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2948 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2949 return -EOPNOTSUPP;
2950 }
2951 hw->flags = SKY2_HW_GIGABIT;
2952 break;
2953
2954 case CHIP_ID_YUKON_FE:
2955 break;
2956
2957 case CHIP_ID_YUKON_FE_P:
2958 hw->flags = SKY2_HW_NEWER_PHY
2959 | SKY2_HW_NEW_LE
2960 | SKY2_HW_AUTO_TX_SUM
2961 | SKY2_HW_ADV_POWER_CTL;
2962 break;
2963
2964 case CHIP_ID_YUKON_SUPR:
2965 hw->flags = SKY2_HW_GIGABIT
2966 | SKY2_HW_NEWER_PHY
2967 | SKY2_HW_NEW_LE
2968 | SKY2_HW_AUTO_TX_SUM
2969 | SKY2_HW_ADV_POWER_CTL;
2970 break;
2971
2972 case CHIP_ID_YUKON_UL_2:
2973 hw->flags = SKY2_HW_GIGABIT
2974 | SKY2_HW_ADV_POWER_CTL;
2975 break;
2976
2977 case CHIP_ID_YUKON_OPT:
2978 hw->flags = SKY2_HW_GIGABIT
2979 | SKY2_HW_NEW_LE
2980 | SKY2_HW_ADV_POWER_CTL;
2981 break;
2982
2983 default:
2984 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2985 hw->chip_id);
2986 return -EOPNOTSUPP;
2987 }
2988
2989 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2990 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2991 hw->flags |= SKY2_HW_FIBRE_PHY;
2992
2993 hw->ports = 1;
2994 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2995 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2996 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2997 ++hw->ports;
2998 }
2999
3000 if (sky2_read8(hw, B2_E_0))
3001 hw->flags |= SKY2_HW_RAM_BUFFER;
3002
3003 return 0;
3004 }
3005
3006 static void sky2_reset(struct sky2_hw *hw)
3007 {
3008 struct pci_dev *pdev = hw->pdev;
3009 u16 status;
3010 int i, cap;
3011 u32 hwe_mask = Y2_HWE_ALL_MASK;
3012
3013 /* disable ASF */
3014 if (hw->chip_id == CHIP_ID_YUKON_EX) {
3015 status = sky2_read16(hw, HCU_CCSR);
3016 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3017 HCU_CCSR_UC_STATE_MSK);
3018 sky2_write16(hw, HCU_CCSR, status);
3019 } else
3020 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3021 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
3022
3023 /* do a SW reset */
3024 sky2_write8(hw, B0_CTST, CS_RST_SET);
3025 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3026
3027 /* allow writes to PCI config */
3028 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3029
3030 /* clear PCI errors, if any */
3031 status = sky2_pci_read16(hw, PCI_STATUS);
3032 status |= PCI_STATUS_ERROR_BITS;
3033 sky2_pci_write16(hw, PCI_STATUS, status);
3034
3035 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3036
3037 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3038 if (cap) {
3039 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3040 0xfffffffful);
3041
3042 /* If error bit is stuck on ignore it */
3043 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3044 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
3045 else
3046 hwe_mask |= Y2_IS_PCI_EXP;
3047 }
3048
3049 sky2_power_on(hw);
3050 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3051
3052 for (i = 0; i < hw->ports; i++) {
3053 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3054 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3055
3056 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3057 hw->chip_id == CHIP_ID_YUKON_SUPR)
3058 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3059 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3060 | GMC_BYP_RETR_ON);
3061
3062 }
3063
3064 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3065 /* enable MACSec clock gating */
3066 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
3067 }
3068
3069 if (hw->chip_id == CHIP_ID_YUKON_OPT) {
3070 u16 reg;
3071 u32 msk;
3072
3073 if (hw->chip_rev == 0) {
3074 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3075 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3076
3077 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3078 reg = 10;
3079 } else {
3080 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3081 reg = 3;
3082 }
3083
3084 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3085
3086 /* reset PHY Link Detect */
3087 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3088 sky2_pci_write16(hw, PSM_CONFIG_REG4,
3089 reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT);
3090 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3091
3092
3093 /* enable PHY Quick Link */
3094 msk = sky2_read32(hw, B0_IMSK);
3095 msk |= Y2_IS_PHY_QLNK;
3096 sky2_write32(hw, B0_IMSK, msk);
3097
3098 /* check if PSMv2 was running before */
3099 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3100 if (reg & PCI_EXP_LNKCTL_ASPMC) {
3101 int cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3102 /* restore the PCIe Link Control register */
3103 sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg);
3104 }
3105 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3106
3107 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3108 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3109 }
3110
3111 /* Clear I2C IRQ noise */
3112 sky2_write32(hw, B2_I2C_IRQ, 1);
3113
3114 /* turn off hardware timer (unused) */
3115 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3116 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3117
3118 /* Turn off descriptor polling */
3119 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
3120
3121 /* Turn off receive timestamp */
3122 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
3123 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3124
3125 /* enable the Tx Arbiters */
3126 for (i = 0; i < hw->ports; i++)
3127 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3128
3129 /* Initialize ram interface */
3130 for (i = 0; i < hw->ports; i++) {
3131 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
3132
3133 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3134 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3135 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3136 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3137 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3138 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3139 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3140 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3141 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3142 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3143 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3144 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3145 }
3146
3147 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3148
3149 for (i = 0; i < hw->ports; i++)
3150 sky2_gmac_reset(hw, i);
3151
3152 memset(hw->st_le, 0, STATUS_LE_BYTES);
3153 hw->st_idx = 0;
3154
3155 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3156 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3157
3158 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3159 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3160
3161 /* Set the list last index */
3162 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
3163
3164 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3165 sky2_write8(hw, STAT_FIFO_WM, 16);
3166
3167 /* set Status-FIFO ISR watermark */
3168 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3169 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3170 else
3171 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3172
3173 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3174 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3175 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3176
3177 /* enable status unit */
3178 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3179
3180 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3181 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3182 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3183 }
3184
3185 /* Take device down (offline).
3186 * Equivalent to doing dev_stop() but this does not
3187 * inform upper layers of the transistion.
3188 */
3189 static void sky2_detach(struct net_device *dev)
3190 {
3191 if (netif_running(dev)) {
3192 netif_device_detach(dev); /* stop txq */
3193 sky2_down(dev);
3194 }
3195 }
3196
3197 /* Bring device back after doing sky2_detach */
3198 static int sky2_reattach(struct net_device *dev)
3199 {
3200 int err = 0;
3201
3202 if (netif_running(dev)) {
3203 err = sky2_up(dev);
3204 if (err) {
3205 printk(KERN_INFO PFX "%s: could not restart %d\n",
3206 dev->name, err);
3207 dev_close(dev);
3208 } else {
3209 netif_device_attach(dev);
3210 sky2_set_multicast(dev);
3211 }
3212 }
3213
3214 return err;
3215 }
3216
3217 static void sky2_restart(struct work_struct *work)
3218 {
3219 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3220 int i;
3221
3222 rtnl_lock();
3223 for (i = 0; i < hw->ports; i++)
3224 sky2_detach(hw->dev[i]);
3225
3226 napi_disable(&hw->napi);
3227 sky2_write32(hw, B0_IMSK, 0);
3228 sky2_reset(hw);
3229 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3230 napi_enable(&hw->napi);
3231
3232 for (i = 0; i < hw->ports; i++)
3233 sky2_reattach(hw->dev[i]);
3234
3235 rtnl_unlock();
3236 }
3237
3238 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3239 {
3240 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3241 }
3242
3243 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3244 {
3245 const struct sky2_port *sky2 = netdev_priv(dev);
3246
3247 wol->supported = sky2_wol_supported(sky2->hw);
3248 wol->wolopts = sky2->wol;
3249 }
3250
3251 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3252 {
3253 struct sky2_port *sky2 = netdev_priv(dev);
3254 struct sky2_hw *hw = sky2->hw;
3255
3256 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3257 !device_can_wakeup(&hw->pdev->dev))
3258 return -EOPNOTSUPP;
3259
3260 sky2->wol = wol->wolopts;
3261
3262 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3263 hw->chip_id == CHIP_ID_YUKON_EX ||
3264 hw->chip_id == CHIP_ID_YUKON_FE_P)
3265 sky2_write32(hw, B0_CTST, sky2->wol
3266 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3267
3268 device_set_wakeup_enable(&hw->pdev->dev, sky2->wol);
3269
3270 if (!netif_running(dev))
3271 sky2_wol_init(sky2);
3272 return 0;
3273 }
3274
3275 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3276 {
3277 if (sky2_is_copper(hw)) {
3278 u32 modes = SUPPORTED_10baseT_Half
3279 | SUPPORTED_10baseT_Full
3280 | SUPPORTED_100baseT_Half
3281 | SUPPORTED_100baseT_Full
3282 | SUPPORTED_Autoneg | SUPPORTED_TP;
3283
3284 if (hw->flags & SKY2_HW_GIGABIT)
3285 modes |= SUPPORTED_1000baseT_Half
3286 | SUPPORTED_1000baseT_Full;
3287 return modes;
3288 } else
3289 return SUPPORTED_1000baseT_Half
3290 | SUPPORTED_1000baseT_Full
3291 | SUPPORTED_Autoneg
3292 | SUPPORTED_FIBRE;
3293 }
3294
3295 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3296 {
3297 struct sky2_port *sky2 = netdev_priv(dev);
3298 struct sky2_hw *hw = sky2->hw;
3299
3300 ecmd->transceiver = XCVR_INTERNAL;
3301 ecmd->supported = sky2_supported_modes(hw);
3302 ecmd->phy_address = PHY_ADDR_MARV;
3303 if (sky2_is_copper(hw)) {
3304 ecmd->port = PORT_TP;
3305 ecmd->speed = sky2->speed;
3306 } else {
3307 ecmd->speed = SPEED_1000;
3308 ecmd->port = PORT_FIBRE;
3309 }
3310
3311 ecmd->advertising = sky2->advertising;
3312 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3313 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3314 ecmd->duplex = sky2->duplex;
3315 return 0;
3316 }
3317
3318 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3319 {
3320 struct sky2_port *sky2 = netdev_priv(dev);
3321 const struct sky2_hw *hw = sky2->hw;
3322 u32 supported = sky2_supported_modes(hw);
3323
3324 if (ecmd->autoneg == AUTONEG_ENABLE) {
3325 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
3326 ecmd->advertising = supported;
3327 sky2->duplex = -1;
3328 sky2->speed = -1;
3329 } else {
3330 u32 setting;
3331
3332 switch (ecmd->speed) {
3333 case SPEED_1000:
3334 if (ecmd->duplex == DUPLEX_FULL)
3335 setting = SUPPORTED_1000baseT_Full;
3336 else if (ecmd->duplex == DUPLEX_HALF)
3337 setting = SUPPORTED_1000baseT_Half;
3338 else
3339 return -EINVAL;
3340 break;
3341 case SPEED_100:
3342 if (ecmd->duplex == DUPLEX_FULL)
3343 setting = SUPPORTED_100baseT_Full;
3344 else if (ecmd->duplex == DUPLEX_HALF)
3345 setting = SUPPORTED_100baseT_Half;
3346 else
3347 return -EINVAL;
3348 break;
3349
3350 case SPEED_10:
3351 if (ecmd->duplex == DUPLEX_FULL)
3352 setting = SUPPORTED_10baseT_Full;
3353 else if (ecmd->duplex == DUPLEX_HALF)
3354 setting = SUPPORTED_10baseT_Half;
3355 else
3356 return -EINVAL;
3357 break;
3358 default:
3359 return -EINVAL;
3360 }
3361
3362 if ((setting & supported) == 0)
3363 return -EINVAL;
3364
3365 sky2->speed = ecmd->speed;
3366 sky2->duplex = ecmd->duplex;
3367 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
3368 }
3369
3370 sky2->advertising = ecmd->advertising;
3371
3372 if (netif_running(dev)) {
3373 sky2_phy_reinit(sky2);
3374 sky2_set_multicast(dev);
3375 }
3376
3377 return 0;
3378 }
3379
3380 static void sky2_get_drvinfo(struct net_device *dev,
3381 struct ethtool_drvinfo *info)
3382 {
3383 struct sky2_port *sky2 = netdev_priv(dev);
3384
3385 strcpy(info->driver, DRV_NAME);
3386 strcpy(info->version, DRV_VERSION);
3387 strcpy(info->fw_version, "N/A");
3388 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3389 }
3390
3391 static const struct sky2_stat {
3392 char name[ETH_GSTRING_LEN];
3393 u16 offset;
3394 } sky2_stats[] = {
3395 { "tx_bytes", GM_TXO_OK_HI },
3396 { "rx_bytes", GM_RXO_OK_HI },
3397 { "tx_broadcast", GM_TXF_BC_OK },
3398 { "rx_broadcast", GM_RXF_BC_OK },
3399 { "tx_multicast", GM_TXF_MC_OK },
3400 { "rx_multicast", GM_RXF_MC_OK },
3401 { "tx_unicast", GM_TXF_UC_OK },
3402 { "rx_unicast", GM_RXF_UC_OK },
3403 { "tx_mac_pause", GM_TXF_MPAUSE },
3404 { "rx_mac_pause", GM_RXF_MPAUSE },
3405 { "collisions", GM_TXF_COL },
3406 { "late_collision",GM_TXF_LAT_COL },
3407 { "aborted", GM_TXF_ABO_COL },
3408 { "single_collisions", GM_TXF_SNG_COL },
3409 { "multi_collisions", GM_TXF_MUL_COL },
3410
3411 { "rx_short", GM_RXF_SHT },
3412 { "rx_runt", GM_RXE_FRAG },
3413 { "rx_64_byte_packets", GM_RXF_64B },
3414 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3415 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3416 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3417 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3418 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3419 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3420 { "rx_too_long", GM_RXF_LNG_ERR },
3421 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3422 { "rx_jabber", GM_RXF_JAB_PKT },
3423 { "rx_fcs_error", GM_RXF_FCS_ERR },
3424
3425 { "tx_64_byte_packets", GM_TXF_64B },
3426 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3427 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3428 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3429 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3430 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3431 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3432 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3433 };
3434
3435 static u32 sky2_get_rx_csum(struct net_device *dev)
3436 {
3437 struct sky2_port *sky2 = netdev_priv(dev);
3438
3439 return !!(sky2->flags & SKY2_FLAG_RX_CHECKSUM);
3440 }
3441
3442 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3443 {
3444 struct sky2_port *sky2 = netdev_priv(dev);
3445
3446 if (data)
3447 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
3448 else
3449 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
3450
3451 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3452 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3453
3454 return 0;
3455 }
3456
3457 static u32 sky2_get_msglevel(struct net_device *netdev)
3458 {
3459 struct sky2_port *sky2 = netdev_priv(netdev);
3460 return sky2->msg_enable;
3461 }
3462
3463 static int sky2_nway_reset(struct net_device *dev)
3464 {
3465 struct sky2_port *sky2 = netdev_priv(dev);
3466
3467 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
3468 return -EINVAL;
3469
3470 sky2_phy_reinit(sky2);
3471 sky2_set_multicast(dev);
3472
3473 return 0;
3474 }
3475
3476 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3477 {
3478 struct sky2_hw *hw = sky2->hw;
3479 unsigned port = sky2->port;
3480 int i;
3481
3482 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3483 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3484 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3485 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3486
3487 for (i = 2; i < count; i++)
3488 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3489 }
3490
3491 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3492 {
3493 struct sky2_port *sky2 = netdev_priv(netdev);
3494 sky2->msg_enable = value;
3495 }
3496
3497 static int sky2_get_sset_count(struct net_device *dev, int sset)
3498 {
3499 switch (sset) {
3500 case ETH_SS_STATS:
3501 return ARRAY_SIZE(sky2_stats);
3502 default:
3503 return -EOPNOTSUPP;
3504 }
3505 }
3506
3507 static void sky2_get_ethtool_stats(struct net_device *dev,
3508 struct ethtool_stats *stats, u64 * data)
3509 {
3510 struct sky2_port *sky2 = netdev_priv(dev);
3511
3512 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3513 }
3514
3515 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3516 {
3517 int i;
3518
3519 switch (stringset) {
3520 case ETH_SS_STATS:
3521 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3522 memcpy(data + i * ETH_GSTRING_LEN,
3523 sky2_stats[i].name, ETH_GSTRING_LEN);
3524 break;
3525 }
3526 }
3527
3528 static int sky2_set_mac_address(struct net_device *dev, void *p)
3529 {
3530 struct sky2_port *sky2 = netdev_priv(dev);
3531 struct sky2_hw *hw = sky2->hw;
3532 unsigned port = sky2->port;
3533 const struct sockaddr *addr = p;
3534
3535 if (!is_valid_ether_addr(addr->sa_data))
3536 return -EADDRNOTAVAIL;
3537
3538 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3539 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3540 dev->dev_addr, ETH_ALEN);
3541 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3542 dev->dev_addr, ETH_ALEN);
3543
3544 /* virtual address for data */
3545 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3546
3547 /* physical address: used for pause frames */
3548 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3549
3550 return 0;
3551 }
3552
3553 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3554 {
3555 u32 bit;
3556
3557 bit = ether_crc(ETH_ALEN, addr) & 63;
3558 filter[bit >> 3] |= 1 << (bit & 7);
3559 }
3560
3561 static void sky2_set_multicast(struct net_device *dev)
3562 {
3563 struct sky2_port *sky2 = netdev_priv(dev);
3564 struct sky2_hw *hw = sky2->hw;
3565 unsigned port = sky2->port;
3566 struct dev_mc_list *list = dev->mc_list;
3567 u16 reg;
3568 u8 filter[8];
3569 int rx_pause;
3570 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3571
3572 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3573 memset(filter, 0, sizeof(filter));
3574
3575 reg = gma_read16(hw, port, GM_RX_CTRL);
3576 reg |= GM_RXCR_UCF_ENA;
3577
3578 if (dev->flags & IFF_PROMISC) /* promiscuous */
3579 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3580 else if (dev->flags & IFF_ALLMULTI)
3581 memset(filter, 0xff, sizeof(filter));
3582 else if (dev->mc_count == 0 && !rx_pause)
3583 reg &= ~GM_RXCR_MCF_ENA;
3584 else {
3585 int i;
3586 reg |= GM_RXCR_MCF_ENA;
3587
3588 if (rx_pause)
3589 sky2_add_filter(filter, pause_mc_addr);
3590
3591 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3592 sky2_add_filter(filter, list->dmi_addr);
3593 }
3594
3595 gma_write16(hw, port, GM_MC_ADDR_H1,
3596 (u16) filter[0] | ((u16) filter[1] << 8));
3597 gma_write16(hw, port, GM_MC_ADDR_H2,
3598 (u16) filter[2] | ((u16) filter[3] << 8));
3599 gma_write16(hw, port, GM_MC_ADDR_H3,
3600 (u16) filter[4] | ((u16) filter[5] << 8));
3601 gma_write16(hw, port, GM_MC_ADDR_H4,
3602 (u16) filter[6] | ((u16) filter[7] << 8));
3603
3604 gma_write16(hw, port, GM_RX_CTRL, reg);
3605 }
3606
3607 /* Can have one global because blinking is controlled by
3608 * ethtool and that is always under RTNL mutex
3609 */
3610 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3611 {
3612 struct sky2_hw *hw = sky2->hw;
3613 unsigned port = sky2->port;
3614
3615 spin_lock_bh(&sky2->phy_lock);
3616 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3617 hw->chip_id == CHIP_ID_YUKON_EX ||
3618 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3619 u16 pg;
3620 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3621 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3622
3623 switch (mode) {
3624 case MO_LED_OFF:
3625 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3626 PHY_M_LEDC_LOS_CTRL(8) |
3627 PHY_M_LEDC_INIT_CTRL(8) |
3628 PHY_M_LEDC_STA1_CTRL(8) |
3629 PHY_M_LEDC_STA0_CTRL(8));
3630 break;
3631 case MO_LED_ON:
3632 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3633 PHY_M_LEDC_LOS_CTRL(9) |
3634 PHY_M_LEDC_INIT_CTRL(9) |
3635 PHY_M_LEDC_STA1_CTRL(9) |
3636 PHY_M_LEDC_STA0_CTRL(9));
3637 break;
3638 case MO_LED_BLINK:
3639 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3640 PHY_M_LEDC_LOS_CTRL(0xa) |
3641 PHY_M_LEDC_INIT_CTRL(0xa) |
3642 PHY_M_LEDC_STA1_CTRL(0xa) |
3643 PHY_M_LEDC_STA0_CTRL(0xa));
3644 break;
3645 case MO_LED_NORM:
3646 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3647 PHY_M_LEDC_LOS_CTRL(1) |
3648 PHY_M_LEDC_INIT_CTRL(8) |
3649 PHY_M_LEDC_STA1_CTRL(7) |
3650 PHY_M_LEDC_STA0_CTRL(7));
3651 }
3652
3653 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3654 } else
3655 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3656 PHY_M_LED_MO_DUP(mode) |
3657 PHY_M_LED_MO_10(mode) |
3658 PHY_M_LED_MO_100(mode) |
3659 PHY_M_LED_MO_1000(mode) |
3660 PHY_M_LED_MO_RX(mode) |
3661 PHY_M_LED_MO_TX(mode));
3662
3663 spin_unlock_bh(&sky2->phy_lock);
3664 }
3665
3666 /* blink LED's for finding board */
3667 static int sky2_phys_id(struct net_device *dev, u32 data)
3668 {
3669 struct sky2_port *sky2 = netdev_priv(dev);
3670 unsigned int i;
3671
3672 if (data == 0)
3673 data = UINT_MAX;
3674
3675 for (i = 0; i < data; i++) {
3676 sky2_led(sky2, MO_LED_ON);
3677 if (msleep_interruptible(500))
3678 break;
3679 sky2_led(sky2, MO_LED_OFF);
3680 if (msleep_interruptible(500))
3681 break;
3682 }
3683 sky2_led(sky2, MO_LED_NORM);
3684
3685 return 0;
3686 }
3687
3688 static void sky2_get_pauseparam(struct net_device *dev,
3689 struct ethtool_pauseparam *ecmd)
3690 {
3691 struct sky2_port *sky2 = netdev_priv(dev);
3692
3693 switch (sky2->flow_mode) {
3694 case FC_NONE:
3695 ecmd->tx_pause = ecmd->rx_pause = 0;
3696 break;
3697 case FC_TX:
3698 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3699 break;
3700 case FC_RX:
3701 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3702 break;
3703 case FC_BOTH:
3704 ecmd->tx_pause = ecmd->rx_pause = 1;
3705 }
3706
3707 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3708 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3709 }
3710
3711 static int sky2_set_pauseparam(struct net_device *dev,
3712 struct ethtool_pauseparam *ecmd)
3713 {
3714 struct sky2_port *sky2 = netdev_priv(dev);
3715
3716 if (ecmd->autoneg == AUTONEG_ENABLE)
3717 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3718 else
3719 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3720
3721 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3722
3723 if (netif_running(dev))
3724 sky2_phy_reinit(sky2);
3725
3726 return 0;
3727 }
3728
3729 static int sky2_get_coalesce(struct net_device *dev,
3730 struct ethtool_coalesce *ecmd)
3731 {
3732 struct sky2_port *sky2 = netdev_priv(dev);
3733 struct sky2_hw *hw = sky2->hw;
3734
3735 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3736 ecmd->tx_coalesce_usecs = 0;
3737 else {
3738 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3739 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3740 }
3741 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3742
3743 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3744 ecmd->rx_coalesce_usecs = 0;
3745 else {
3746 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3747 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3748 }
3749 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3750
3751 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3752 ecmd->rx_coalesce_usecs_irq = 0;
3753 else {
3754 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3755 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3756 }
3757
3758 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3759
3760 return 0;
3761 }
3762
3763 /* Note: this affect both ports */
3764 static int sky2_set_coalesce(struct net_device *dev,
3765 struct ethtool_coalesce *ecmd)
3766 {
3767 struct sky2_port *sky2 = netdev_priv(dev);
3768 struct sky2_hw *hw = sky2->hw;
3769 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3770
3771 if (ecmd->tx_coalesce_usecs > tmax ||
3772 ecmd->rx_coalesce_usecs > tmax ||
3773 ecmd->rx_coalesce_usecs_irq > tmax)
3774 return -EINVAL;
3775
3776 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
3777 return -EINVAL;
3778 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3779 return -EINVAL;
3780 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3781 return -EINVAL;
3782
3783 if (ecmd->tx_coalesce_usecs == 0)
3784 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3785 else {
3786 sky2_write32(hw, STAT_TX_TIMER_INI,
3787 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3788 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3789 }
3790 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3791
3792 if (ecmd->rx_coalesce_usecs == 0)
3793 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3794 else {
3795 sky2_write32(hw, STAT_LEV_TIMER_INI,
3796 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3797 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3798 }
3799 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3800
3801 if (ecmd->rx_coalesce_usecs_irq == 0)
3802 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3803 else {
3804 sky2_write32(hw, STAT_ISR_TIMER_INI,
3805 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3806 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3807 }
3808 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3809 return 0;
3810 }
3811
3812 static void sky2_get_ringparam(struct net_device *dev,
3813 struct ethtool_ringparam *ering)
3814 {
3815 struct sky2_port *sky2 = netdev_priv(dev);
3816
3817 ering->rx_max_pending = RX_MAX_PENDING;
3818 ering->rx_mini_max_pending = 0;
3819 ering->rx_jumbo_max_pending = 0;
3820 ering->tx_max_pending = TX_MAX_PENDING;
3821
3822 ering->rx_pending = sky2->rx_pending;
3823 ering->rx_mini_pending = 0;
3824 ering->rx_jumbo_pending = 0;
3825 ering->tx_pending = sky2->tx_pending;
3826 }
3827
3828 static int sky2_set_ringparam(struct net_device *dev,
3829 struct ethtool_ringparam *ering)
3830 {
3831 struct sky2_port *sky2 = netdev_priv(dev);
3832
3833 if (ering->rx_pending > RX_MAX_PENDING ||
3834 ering->rx_pending < 8 ||
3835 ering->tx_pending < TX_MIN_PENDING ||
3836 ering->tx_pending > TX_MAX_PENDING)
3837 return -EINVAL;
3838
3839 sky2_detach(dev);
3840
3841 sky2->rx_pending = ering->rx_pending;
3842 sky2->tx_pending = ering->tx_pending;
3843 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
3844
3845 return sky2_reattach(dev);
3846 }
3847
3848 static int sky2_get_regs_len(struct net_device *dev)
3849 {
3850 return 0x4000;
3851 }
3852
3853 /*
3854 * Returns copy of control register region
3855 * Note: ethtool_get_regs always provides full size (16k) buffer
3856 */
3857 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3858 void *p)
3859 {
3860 const struct sky2_port *sky2 = netdev_priv(dev);
3861 const void __iomem *io = sky2->hw->regs;
3862 unsigned int b;
3863
3864 regs->version = 1;
3865
3866 for (b = 0; b < 128; b++) {
3867 /* This complicated switch statement is to make sure and
3868 * only access regions that are unreserved.
3869 * Some blocks are only valid on dual port cards.
3870 * and block 3 has some special diagnostic registers that
3871 * are poison.
3872 */
3873 switch (b) {
3874 case 3:
3875 /* skip diagnostic ram region */
3876 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3877 break;
3878
3879 /* dual port cards only */
3880 case 5: /* Tx Arbiter 2 */
3881 case 9: /* RX2 */
3882 case 14 ... 15: /* TX2 */
3883 case 17: case 19: /* Ram Buffer 2 */
3884 case 22 ... 23: /* Tx Ram Buffer 2 */
3885 case 25: /* Rx MAC Fifo 1 */
3886 case 27: /* Tx MAC Fifo 2 */
3887 case 31: /* GPHY 2 */
3888 case 40 ... 47: /* Pattern Ram 2 */
3889 case 52: case 54: /* TCP Segmentation 2 */
3890 case 112 ... 116: /* GMAC 2 */
3891 if (sky2->hw->ports == 1)
3892 goto reserved;
3893 /* fall through */
3894 case 0: /* Control */
3895 case 2: /* Mac address */
3896 case 4: /* Tx Arbiter 1 */
3897 case 7: /* PCI express reg */
3898 case 8: /* RX1 */
3899 case 12 ... 13: /* TX1 */
3900 case 16: case 18:/* Rx Ram Buffer 1 */
3901 case 20 ... 21: /* Tx Ram Buffer 1 */
3902 case 24: /* Rx MAC Fifo 1 */
3903 case 26: /* Tx MAC Fifo 1 */
3904 case 28 ... 29: /* Descriptor and status unit */
3905 case 30: /* GPHY 1*/
3906 case 32 ... 39: /* Pattern Ram 1 */
3907 case 48: case 50: /* TCP Segmentation 1 */
3908 case 56 ... 60: /* PCI space */
3909 case 80 ... 84: /* GMAC 1 */
3910 memcpy_fromio(p, io, 128);
3911 break;
3912 default:
3913 reserved:
3914 memset(p, 0, 128);
3915 }
3916
3917 p += 128;
3918 io += 128;
3919 }
3920 }
3921
3922 /* In order to do Jumbo packets on these chips, need to turn off the
3923 * transmit store/forward. Therefore checksum offload won't work.
3924 */
3925 static int no_tx_offload(struct net_device *dev)
3926 {
3927 const struct sky2_port *sky2 = netdev_priv(dev);
3928 const struct sky2_hw *hw = sky2->hw;
3929
3930 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3931 }
3932
3933 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3934 {
3935 if (data && no_tx_offload(dev))
3936 return -EINVAL;
3937
3938 return ethtool_op_set_tx_csum(dev, data);
3939 }
3940
3941
3942 static int sky2_set_tso(struct net_device *dev, u32 data)
3943 {
3944 if (data && no_tx_offload(dev))
3945 return -EINVAL;
3946
3947 return ethtool_op_set_tso(dev, data);
3948 }
3949
3950 static int sky2_get_eeprom_len(struct net_device *dev)
3951 {
3952 struct sky2_port *sky2 = netdev_priv(dev);
3953 struct sky2_hw *hw = sky2->hw;
3954 u16 reg2;
3955
3956 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3957 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3958 }
3959
3960 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
3961 {
3962 unsigned long start = jiffies;
3963
3964 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
3965 /* Can take up to 10.6 ms for write */
3966 if (time_after(jiffies, start + HZ/4)) {
3967 dev_err(&hw->pdev->dev, PFX "VPD cycle timed out");
3968 return -ETIMEDOUT;
3969 }
3970 mdelay(1);
3971 }
3972
3973 return 0;
3974 }
3975
3976 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
3977 u16 offset, size_t length)
3978 {
3979 int rc = 0;
3980
3981 while (length > 0) {
3982 u32 val;
3983
3984 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3985 rc = sky2_vpd_wait(hw, cap, 0);
3986 if (rc)
3987 break;
3988
3989 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3990
3991 memcpy(data, &val, min(sizeof(val), length));
3992 offset += sizeof(u32);
3993 data += sizeof(u32);
3994 length -= sizeof(u32);
3995 }
3996
3997 return rc;
3998 }
3999
4000 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4001 u16 offset, unsigned int length)
4002 {
4003 unsigned int i;
4004 int rc = 0;
4005
4006 for (i = 0; i < length; i += sizeof(u32)) {
4007 u32 val = *(u32 *)(data + i);
4008
4009 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4010 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4011
4012 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4013 if (rc)
4014 break;
4015 }
4016 return rc;
4017 }
4018
4019 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4020 u8 *data)
4021 {
4022 struct sky2_port *sky2 = netdev_priv(dev);
4023 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4024
4025 if (!cap)
4026 return -EINVAL;
4027
4028 eeprom->magic = SKY2_EEPROM_MAGIC;
4029
4030 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4031 }
4032
4033 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4034 u8 *data)
4035 {
4036 struct sky2_port *sky2 = netdev_priv(dev);
4037 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4038
4039 if (!cap)
4040 return -EINVAL;
4041
4042 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4043 return -EINVAL;
4044
4045 /* Partial writes not supported */
4046 if ((eeprom->offset & 3) || (eeprom->len & 3))
4047 return -EINVAL;
4048
4049 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4050 }
4051
4052
4053 static const struct ethtool_ops sky2_ethtool_ops = {
4054 .get_settings = sky2_get_settings,
4055 .set_settings = sky2_set_settings,
4056 .get_drvinfo = sky2_get_drvinfo,
4057 .get_wol = sky2_get_wol,
4058 .set_wol = sky2_set_wol,
4059 .get_msglevel = sky2_get_msglevel,
4060 .set_msglevel = sky2_set_msglevel,
4061 .nway_reset = sky2_nway_reset,
4062 .get_regs_len = sky2_get_regs_len,
4063 .get_regs = sky2_get_regs,
4064 .get_link = ethtool_op_get_link,
4065 .get_eeprom_len = sky2_get_eeprom_len,
4066 .get_eeprom = sky2_get_eeprom,
4067 .set_eeprom = sky2_set_eeprom,
4068 .set_sg = ethtool_op_set_sg,
4069 .set_tx_csum = sky2_set_tx_csum,
4070 .set_tso = sky2_set_tso,
4071 .get_rx_csum = sky2_get_rx_csum,
4072 .set_rx_csum = sky2_set_rx_csum,
4073 .get_strings = sky2_get_strings,
4074 .get_coalesce = sky2_get_coalesce,
4075 .set_coalesce = sky2_set_coalesce,
4076 .get_ringparam = sky2_get_ringparam,
4077 .set_ringparam = sky2_set_ringparam,
4078 .get_pauseparam = sky2_get_pauseparam,
4079 .set_pauseparam = sky2_set_pauseparam,
4080 .phys_id = sky2_phys_id,
4081 .get_sset_count = sky2_get_sset_count,
4082 .get_ethtool_stats = sky2_get_ethtool_stats,
4083 };
4084
4085 #ifdef CONFIG_SKY2_DEBUG
4086
4087 static struct dentry *sky2_debug;
4088
4089
4090 /*
4091 * Read and parse the first part of Vital Product Data
4092 */
4093 #define VPD_SIZE 128
4094 #define VPD_MAGIC 0x82
4095
4096 static const struct vpd_tag {
4097 char tag[2];
4098 char *label;
4099 } vpd_tags[] = {
4100 { "PN", "Part Number" },
4101 { "EC", "Engineering Level" },
4102 { "MN", "Manufacturer" },
4103 { "SN", "Serial Number" },
4104 { "YA", "Asset Tag" },
4105 { "VL", "First Error Log Message" },
4106 { "VF", "Second Error Log Message" },
4107 { "VB", "Boot Agent ROM Configuration" },
4108 { "VE", "EFI UNDI Configuration" },
4109 };
4110
4111 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4112 {
4113 size_t vpd_size;
4114 loff_t offs;
4115 u8 len;
4116 unsigned char *buf;
4117 u16 reg2;
4118
4119 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4120 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4121
4122 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4123 buf = kmalloc(vpd_size, GFP_KERNEL);
4124 if (!buf) {
4125 seq_puts(seq, "no memory!\n");
4126 return;
4127 }
4128
4129 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4130 seq_puts(seq, "VPD read failed\n");
4131 goto out;
4132 }
4133
4134 if (buf[0] != VPD_MAGIC) {
4135 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4136 goto out;
4137 }
4138 len = buf[1];
4139 if (len == 0 || len > vpd_size - 4) {
4140 seq_printf(seq, "Invalid id length: %d\n", len);
4141 goto out;
4142 }
4143
4144 seq_printf(seq, "%.*s\n", len, buf + 3);
4145 offs = len + 3;
4146
4147 while (offs < vpd_size - 4) {
4148 int i;
4149
4150 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4151 break;
4152 len = buf[offs + 2];
4153 if (offs + len + 3 >= vpd_size)
4154 break;
4155
4156 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4157 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4158 seq_printf(seq, " %s: %.*s\n",
4159 vpd_tags[i].label, len, buf + offs + 3);
4160 break;
4161 }
4162 }
4163 offs += len + 3;
4164 }
4165 out:
4166 kfree(buf);
4167 }
4168
4169 static int sky2_debug_show(struct seq_file *seq, void *v)
4170 {
4171 struct net_device *dev = seq->private;
4172 const struct sky2_port *sky2 = netdev_priv(dev);
4173 struct sky2_hw *hw = sky2->hw;
4174 unsigned port = sky2->port;
4175 unsigned idx, last;
4176 int sop;
4177
4178 sky2_show_vpd(seq, hw);
4179
4180 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
4181 sky2_read32(hw, B0_ISRC),
4182 sky2_read32(hw, B0_IMSK),
4183 sky2_read32(hw, B0_Y2_SP_ICR));
4184
4185 if (!netif_running(dev)) {
4186 seq_printf(seq, "network not running\n");
4187 return 0;
4188 }
4189
4190 napi_disable(&hw->napi);
4191 last = sky2_read16(hw, STAT_PUT_IDX);
4192
4193 if (hw->st_idx == last)
4194 seq_puts(seq, "Status ring (empty)\n");
4195 else {
4196 seq_puts(seq, "Status ring\n");
4197 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4198 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4199 const struct sky2_status_le *le = hw->st_le + idx;
4200 seq_printf(seq, "[%d] %#x %d %#x\n",
4201 idx, le->opcode, le->length, le->status);
4202 }
4203 seq_puts(seq, "\n");
4204 }
4205
4206 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4207 sky2->tx_cons, sky2->tx_prod,
4208 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4209 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4210
4211 /* Dump contents of tx ring */
4212 sop = 1;
4213 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4214 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
4215 const struct sky2_tx_le *le = sky2->tx_le + idx;
4216 u32 a = le32_to_cpu(le->addr);
4217
4218 if (sop)
4219 seq_printf(seq, "%u:", idx);
4220 sop = 0;
4221
4222 switch(le->opcode & ~HW_OWNER) {
4223 case OP_ADDR64:
4224 seq_printf(seq, " %#x:", a);
4225 break;
4226 case OP_LRGLEN:
4227 seq_printf(seq, " mtu=%d", a);
4228 break;
4229 case OP_VLAN:
4230 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4231 break;
4232 case OP_TCPLISW:
4233 seq_printf(seq, " csum=%#x", a);
4234 break;
4235 case OP_LARGESEND:
4236 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4237 break;
4238 case OP_PACKET:
4239 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4240 break;
4241 case OP_BUFFER:
4242 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4243 break;
4244 default:
4245 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4246 a, le16_to_cpu(le->length));
4247 }
4248
4249 if (le->ctrl & EOP) {
4250 seq_putc(seq, '\n');
4251 sop = 1;
4252 }
4253 }
4254
4255 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4256 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4257 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4258 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4259
4260 sky2_read32(hw, B0_Y2_SP_LISR);
4261 napi_enable(&hw->napi);
4262 return 0;
4263 }
4264
4265 static int sky2_debug_open(struct inode *inode, struct file *file)
4266 {
4267 return single_open(file, sky2_debug_show, inode->i_private);
4268 }
4269
4270 static const struct file_operations sky2_debug_fops = {
4271 .owner = THIS_MODULE,
4272 .open = sky2_debug_open,
4273 .read = seq_read,
4274 .llseek = seq_lseek,
4275 .release = single_release,
4276 };
4277
4278 /*
4279 * Use network device events to create/remove/rename
4280 * debugfs file entries
4281 */
4282 static int sky2_device_event(struct notifier_block *unused,
4283 unsigned long event, void *ptr)
4284 {
4285 struct net_device *dev = ptr;
4286 struct sky2_port *sky2 = netdev_priv(dev);
4287
4288 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
4289 return NOTIFY_DONE;
4290
4291 switch(event) {
4292 case NETDEV_CHANGENAME:
4293 if (sky2->debugfs) {
4294 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4295 sky2_debug, dev->name);
4296 }
4297 break;
4298
4299 case NETDEV_GOING_DOWN:
4300 if (sky2->debugfs) {
4301 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4302 dev->name);
4303 debugfs_remove(sky2->debugfs);
4304 sky2->debugfs = NULL;
4305 }
4306 break;
4307
4308 case NETDEV_UP:
4309 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4310 sky2_debug, dev,
4311 &sky2_debug_fops);
4312 if (IS_ERR(sky2->debugfs))
4313 sky2->debugfs = NULL;
4314 }
4315
4316 return NOTIFY_DONE;
4317 }
4318
4319 static struct notifier_block sky2_notifier = {
4320 .notifier_call = sky2_device_event,
4321 };
4322
4323
4324 static __init void sky2_debug_init(void)
4325 {
4326 struct dentry *ent;
4327
4328 ent = debugfs_create_dir("sky2", NULL);
4329 if (!ent || IS_ERR(ent))
4330 return;
4331
4332 sky2_debug = ent;
4333 register_netdevice_notifier(&sky2_notifier);
4334 }
4335
4336 static __exit void sky2_debug_cleanup(void)
4337 {
4338 if (sky2_debug) {
4339 unregister_netdevice_notifier(&sky2_notifier);
4340 debugfs_remove(sky2_debug);
4341 sky2_debug = NULL;
4342 }
4343 }
4344
4345 #else
4346 #define sky2_debug_init()
4347 #define sky2_debug_cleanup()
4348 #endif
4349
4350 /* Two copies of network device operations to handle special case of
4351 not allowing netpoll on second port */
4352 static const struct net_device_ops sky2_netdev_ops[2] = {
4353 {
4354 .ndo_open = sky2_up,
4355 .ndo_stop = sky2_down,
4356 .ndo_start_xmit = sky2_xmit_frame,
4357 .ndo_do_ioctl = sky2_ioctl,
4358 .ndo_validate_addr = eth_validate_addr,
4359 .ndo_set_mac_address = sky2_set_mac_address,
4360 .ndo_set_multicast_list = sky2_set_multicast,
4361 .ndo_change_mtu = sky2_change_mtu,
4362 .ndo_tx_timeout = sky2_tx_timeout,
4363 #ifdef SKY2_VLAN_TAG_USED
4364 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4365 #endif
4366 #ifdef CONFIG_NET_POLL_CONTROLLER
4367 .ndo_poll_controller = sky2_netpoll,
4368 #endif
4369 },
4370 {
4371 .ndo_open = sky2_up,
4372 .ndo_stop = sky2_down,
4373 .ndo_start_xmit = sky2_xmit_frame,
4374 .ndo_do_ioctl = sky2_ioctl,
4375 .ndo_validate_addr = eth_validate_addr,
4376 .ndo_set_mac_address = sky2_set_mac_address,
4377 .ndo_set_multicast_list = sky2_set_multicast,
4378 .ndo_change_mtu = sky2_change_mtu,
4379 .ndo_tx_timeout = sky2_tx_timeout,
4380 #ifdef SKY2_VLAN_TAG_USED
4381 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4382 #endif
4383 },
4384 };
4385
4386 /* Initialize network device */
4387 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
4388 unsigned port,
4389 int highmem, int wol)
4390 {
4391 struct sky2_port *sky2;
4392 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4393
4394 if (!dev) {
4395 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
4396 return NULL;
4397 }
4398
4399 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4400 dev->irq = hw->pdev->irq;
4401 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4402 dev->watchdog_timeo = TX_WATCHDOG;
4403 dev->netdev_ops = &sky2_netdev_ops[port];
4404
4405 sky2 = netdev_priv(dev);
4406 sky2->netdev = dev;
4407 sky2->hw = hw;
4408 sky2->msg_enable = netif_msg_init(debug, default_msg);
4409
4410 /* Auto speed and flow control */
4411 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4412 if (hw->chip_id != CHIP_ID_YUKON_XL)
4413 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
4414
4415 sky2->flow_mode = FC_BOTH;
4416
4417 sky2->duplex = -1;
4418 sky2->speed = -1;
4419 sky2->advertising = sky2_supported_modes(hw);
4420 sky2->wol = wol;
4421
4422 spin_lock_init(&sky2->phy_lock);
4423
4424 sky2->tx_pending = TX_DEF_PENDING;
4425 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
4426 sky2->rx_pending = RX_DEF_PENDING;
4427
4428 hw->dev[port] = dev;
4429
4430 sky2->port = port;
4431
4432 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
4433 if (highmem)
4434 dev->features |= NETIF_F_HIGHDMA;
4435
4436 #ifdef SKY2_VLAN_TAG_USED
4437 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4438 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4439 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4440 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4441 }
4442 #endif
4443
4444 /* read the mac address */
4445 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4446 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4447
4448 return dev;
4449 }
4450
4451 static void __devinit sky2_show_addr(struct net_device *dev)
4452 {
4453 const struct sky2_port *sky2 = netdev_priv(dev);
4454
4455 if (netif_msg_probe(sky2))
4456 printk(KERN_INFO PFX "%s: addr %pM\n",
4457 dev->name, dev->dev_addr);
4458 }
4459
4460 /* Handle software interrupt used during MSI test */
4461 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4462 {
4463 struct sky2_hw *hw = dev_id;
4464 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4465
4466 if (status == 0)
4467 return IRQ_NONE;
4468
4469 if (status & Y2_IS_IRQ_SW) {
4470 hw->flags |= SKY2_HW_USE_MSI;
4471 wake_up(&hw->msi_wait);
4472 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4473 }
4474 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4475
4476 return IRQ_HANDLED;
4477 }
4478
4479 /* Test interrupt path by forcing a a software IRQ */
4480 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4481 {
4482 struct pci_dev *pdev = hw->pdev;
4483 int err;
4484
4485 init_waitqueue_head (&hw->msi_wait);
4486
4487 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4488
4489 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4490 if (err) {
4491 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4492 return err;
4493 }
4494
4495 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4496 sky2_read8(hw, B0_CTST);
4497
4498 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4499
4500 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4501 /* MSI test failed, go back to INTx mode */
4502 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4503 "switching to INTx mode.\n");
4504
4505 err = -EOPNOTSUPP;
4506 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4507 }
4508
4509 sky2_write32(hw, B0_IMSK, 0);
4510 sky2_read32(hw, B0_IMSK);
4511
4512 free_irq(pdev->irq, hw);
4513
4514 return err;
4515 }
4516
4517 /* This driver supports yukon2 chipset only */
4518 static const char *sky2_name(u8 chipid, char *buf, int sz)
4519 {
4520 const char *name[] = {
4521 "XL", /* 0xb3 */
4522 "EC Ultra", /* 0xb4 */
4523 "Extreme", /* 0xb5 */
4524 "EC", /* 0xb6 */
4525 "FE", /* 0xb7 */
4526 "FE+", /* 0xb8 */
4527 "Supreme", /* 0xb9 */
4528 "UL 2", /* 0xba */
4529 "Unknown", /* 0xbb */
4530 "Optima", /* 0xbc */
4531 };
4532
4533 if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_OPT)
4534 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4535 else
4536 snprintf(buf, sz, "(chip %#x)", chipid);
4537 return buf;
4538 }
4539
4540 static int __devinit sky2_probe(struct pci_dev *pdev,
4541 const struct pci_device_id *ent)
4542 {
4543 struct net_device *dev;
4544 struct sky2_hw *hw;
4545 int err, using_dac = 0, wol_default;
4546 u32 reg;
4547 char buf1[16];
4548
4549 err = pci_enable_device(pdev);
4550 if (err) {
4551 dev_err(&pdev->dev, "cannot enable PCI device\n");
4552 goto err_out;
4553 }
4554
4555 /* Get configuration information
4556 * Note: only regular PCI config access once to test for HW issues
4557 * other PCI access through shared memory for speed and to
4558 * avoid MMCONFIG problems.
4559 */
4560 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4561 if (err) {
4562 dev_err(&pdev->dev, "PCI read config failed\n");
4563 goto err_out;
4564 }
4565
4566 if (~reg == 0) {
4567 dev_err(&pdev->dev, "PCI configuration read error\n");
4568 goto err_out;
4569 }
4570
4571 err = pci_request_regions(pdev, DRV_NAME);
4572 if (err) {
4573 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4574 goto err_out_disable;
4575 }
4576
4577 pci_set_master(pdev);
4578
4579 if (sizeof(dma_addr_t) > sizeof(u32) &&
4580 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
4581 using_dac = 1;
4582 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4583 if (err < 0) {
4584 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4585 "for consistent allocations\n");
4586 goto err_out_free_regions;
4587 }
4588 } else {
4589 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4590 if (err) {
4591 dev_err(&pdev->dev, "no usable DMA configuration\n");
4592 goto err_out_free_regions;
4593 }
4594 }
4595
4596
4597 #ifdef __BIG_ENDIAN
4598 /* The sk98lin vendor driver uses hardware byte swapping but
4599 * this driver uses software swapping.
4600 */
4601 reg &= ~PCI_REV_DESC;
4602 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4603 if (err) {
4604 dev_err(&pdev->dev, "PCI write config failed\n");
4605 goto err_out_free_regions;
4606 }
4607 #endif
4608
4609 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
4610
4611 err = -ENOMEM;
4612
4613 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4614 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
4615 if (!hw) {
4616 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4617 goto err_out_free_regions;
4618 }
4619
4620 hw->pdev = pdev;
4621 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
4622
4623 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4624 if (!hw->regs) {
4625 dev_err(&pdev->dev, "cannot map device registers\n");
4626 goto err_out_free_hw;
4627 }
4628
4629 /* ring for status responses */
4630 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
4631 if (!hw->st_le)
4632 goto err_out_iounmap;
4633
4634 err = sky2_init(hw);
4635 if (err)
4636 goto err_out_iounmap;
4637
4638 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4639 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
4640
4641 sky2_reset(hw);
4642
4643 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4644 if (!dev) {
4645 err = -ENOMEM;
4646 goto err_out_free_pci;
4647 }
4648
4649 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4650 err = sky2_test_msi(hw);
4651 if (err == -EOPNOTSUPP)
4652 pci_disable_msi(pdev);
4653 else if (err)
4654 goto err_out_free_netdev;
4655 }
4656
4657 err = register_netdev(dev);
4658 if (err) {
4659 dev_err(&pdev->dev, "cannot register net device\n");
4660 goto err_out_free_netdev;
4661 }
4662
4663 netif_carrier_off(dev);
4664
4665 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4666
4667 err = request_irq(pdev->irq, sky2_intr,
4668 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4669 hw->irq_name, hw);
4670 if (err) {
4671 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4672 goto err_out_unregister;
4673 }
4674 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4675 napi_enable(&hw->napi);
4676
4677 sky2_show_addr(dev);
4678
4679 if (hw->ports > 1) {
4680 struct net_device *dev1;
4681
4682 err = -ENOMEM;
4683 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4684 if (dev1 && (err = register_netdev(dev1)) == 0)
4685 sky2_show_addr(dev1);
4686 else {
4687 dev_warn(&pdev->dev,
4688 "register of second port failed (%d)\n", err);
4689 hw->dev[1] = NULL;
4690 hw->ports = 1;
4691 if (dev1)
4692 free_netdev(dev1);
4693 }
4694 }
4695
4696 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4697 INIT_WORK(&hw->restart_work, sky2_restart);
4698
4699 pci_set_drvdata(pdev, hw);
4700
4701 return 0;
4702
4703 err_out_unregister:
4704 if (hw->flags & SKY2_HW_USE_MSI)
4705 pci_disable_msi(pdev);
4706 unregister_netdev(dev);
4707 err_out_free_netdev:
4708 free_netdev(dev);
4709 err_out_free_pci:
4710 sky2_write8(hw, B0_CTST, CS_RST_SET);
4711 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4712 err_out_iounmap:
4713 iounmap(hw->regs);
4714 err_out_free_hw:
4715 kfree(hw);
4716 err_out_free_regions:
4717 pci_release_regions(pdev);
4718 err_out_disable:
4719 pci_disable_device(pdev);
4720 err_out:
4721 pci_set_drvdata(pdev, NULL);
4722 return err;
4723 }
4724
4725 static void __devexit sky2_remove(struct pci_dev *pdev)
4726 {
4727 struct sky2_hw *hw = pci_get_drvdata(pdev);
4728 int i;
4729
4730 if (!hw)
4731 return;
4732
4733 del_timer_sync(&hw->watchdog_timer);
4734 cancel_work_sync(&hw->restart_work);
4735
4736 for (i = hw->ports-1; i >= 0; --i)
4737 unregister_netdev(hw->dev[i]);
4738
4739 sky2_write32(hw, B0_IMSK, 0);
4740
4741 sky2_power_aux(hw);
4742
4743 sky2_write8(hw, B0_CTST, CS_RST_SET);
4744 sky2_read8(hw, B0_CTST);
4745
4746 free_irq(pdev->irq, hw);
4747 if (hw->flags & SKY2_HW_USE_MSI)
4748 pci_disable_msi(pdev);
4749 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4750 pci_release_regions(pdev);
4751 pci_disable_device(pdev);
4752
4753 for (i = hw->ports-1; i >= 0; --i)
4754 free_netdev(hw->dev[i]);
4755
4756 iounmap(hw->regs);
4757 kfree(hw);
4758
4759 pci_set_drvdata(pdev, NULL);
4760 }
4761
4762 #ifdef CONFIG_PM
4763 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4764 {
4765 struct sky2_hw *hw = pci_get_drvdata(pdev);
4766 int i, wol = 0;
4767
4768 if (!hw)
4769 return 0;
4770
4771 del_timer_sync(&hw->watchdog_timer);
4772 cancel_work_sync(&hw->restart_work);
4773
4774 rtnl_lock();
4775 for (i = 0; i < hw->ports; i++) {
4776 struct net_device *dev = hw->dev[i];
4777 struct sky2_port *sky2 = netdev_priv(dev);
4778
4779 sky2_detach(dev);
4780
4781 if (sky2->wol)
4782 sky2_wol_init(sky2);
4783
4784 wol |= sky2->wol;
4785 }
4786
4787 sky2_write32(hw, B0_IMSK, 0);
4788 napi_disable(&hw->napi);
4789 sky2_power_aux(hw);
4790 rtnl_unlock();
4791
4792 pci_save_state(pdev);
4793 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4794 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4795
4796 return 0;
4797 }
4798
4799 static int sky2_resume(struct pci_dev *pdev)
4800 {
4801 struct sky2_hw *hw = pci_get_drvdata(pdev);
4802 int i, err;
4803
4804 if (!hw)
4805 return 0;
4806
4807 err = pci_set_power_state(pdev, PCI_D0);
4808 if (err)
4809 goto out;
4810
4811 err = pci_restore_state(pdev);
4812 if (err)
4813 goto out;
4814
4815 pci_enable_wake(pdev, PCI_D0, 0);
4816
4817 /* Re-enable all clocks */
4818 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4819 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4820 hw->chip_id == CHIP_ID_YUKON_FE_P)
4821 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4822
4823 sky2_reset(hw);
4824 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4825 napi_enable(&hw->napi);
4826
4827 rtnl_lock();
4828 for (i = 0; i < hw->ports; i++) {
4829 err = sky2_reattach(hw->dev[i]);
4830 if (err)
4831 goto out;
4832 }
4833 rtnl_unlock();
4834
4835 return 0;
4836 out:
4837 rtnl_unlock();
4838
4839 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4840 pci_disable_device(pdev);
4841 return err;
4842 }
4843 #endif
4844
4845 static void sky2_shutdown(struct pci_dev *pdev)
4846 {
4847 struct sky2_hw *hw = pci_get_drvdata(pdev);
4848 int i, wol = 0;
4849
4850 if (!hw)
4851 return;
4852
4853 rtnl_lock();
4854 del_timer_sync(&hw->watchdog_timer);
4855
4856 for (i = 0; i < hw->ports; i++) {
4857 struct net_device *dev = hw->dev[i];
4858 struct sky2_port *sky2 = netdev_priv(dev);
4859
4860 if (sky2->wol) {
4861 wol = 1;
4862 sky2_wol_init(sky2);
4863 }
4864 }
4865
4866 if (wol)
4867 sky2_power_aux(hw);
4868 rtnl_unlock();
4869
4870 pci_enable_wake(pdev, PCI_D3hot, wol);
4871 pci_enable_wake(pdev, PCI_D3cold, wol);
4872
4873 pci_disable_device(pdev);
4874 pci_set_power_state(pdev, PCI_D3hot);
4875 }
4876
4877 static struct pci_driver sky2_driver = {
4878 .name = DRV_NAME,
4879 .id_table = sky2_id_table,
4880 .probe = sky2_probe,
4881 .remove = __devexit_p(sky2_remove),
4882 #ifdef CONFIG_PM
4883 .suspend = sky2_suspend,
4884 .resume = sky2_resume,
4885 #endif
4886 .shutdown = sky2_shutdown,
4887 };
4888
4889 static int __init sky2_init_module(void)
4890 {
4891 pr_info(PFX "driver version " DRV_VERSION "\n");
4892
4893 sky2_debug_init();
4894 return pci_register_driver(&sky2_driver);
4895 }
4896
4897 static void __exit sky2_cleanup_module(void)
4898 {
4899 pci_unregister_driver(&sky2_driver);
4900 sky2_debug_cleanup();
4901 }
4902
4903 module_init(sky2_init_module);
4904 module_exit(sky2_cleanup_module);
4905
4906 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4907 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4908 MODULE_LICENSE("GPL");
4909 MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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