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Merge branch 'velocity' of git://electric-eye.fr.zoreil.com/home/romieu/linux-2.6...
[deliverable/linux.git] / drivers / net / sky2.c
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26 #include <linux/config.h>
27 #include <linux/crc32.h>
28 #include <linux/kernel.h>
29 #include <linux/version.h>
30 #include <linux/module.h>
31 #include <linux/netdevice.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/etherdevice.h>
34 #include <linux/ethtool.h>
35 #include <linux/pci.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/in.h>
39 #include <linux/delay.h>
40 #include <linux/workqueue.h>
41 #include <linux/if_vlan.h>
42 #include <linux/prefetch.h>
43 #include <linux/mii.h>
44
45 #include <asm/irq.h>
46
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
49 #endif
50
51 #include "sky2.h"
52
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "1.4"
55 #define PFX DRV_NAME " "
56
57 /*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
60 * similar to Tigon3. A transmit can require several elements;
61 * a receive requires one (or two if using 64 bit dma).
62 */
63
64 #define RX_LE_SIZE 512
65 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
66 #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
67 #define RX_DEF_PENDING RX_MAX_PENDING
68 #define RX_SKB_ALIGN 8
69
70 #define TX_RING_SIZE 512
71 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
72 #define TX_MIN_PENDING 64
73 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
74
75 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
76 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77 #define ETH_JUMBO_MTU 9000
78 #define TX_WATCHDOG (5 * HZ)
79 #define NAPI_WEIGHT 64
80 #define PHY_RETRIES 1000
81
82 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83
84 static const u32 default_msg =
85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
88
89 static int debug = -1; /* defaults above */
90 module_param(debug, int, 0);
91 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92
93 static int copybreak __read_mostly = 256;
94 module_param(copybreak, int, 0);
95 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96
97 static int disable_msi = 0;
98 module_param(disable_msi, int, 0);
99 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100
101 static int idle_timeout = 100;
102 module_param(idle_timeout, int, 0);
103 MODULE_PARM_DESC(idle_timeout, "Idle timeout workaround for lost interrupts (ms)");
104
105 static const struct pci_device_id sky2_id_table[] = {
106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
124 { 0 }
125 };
126
127 MODULE_DEVICE_TABLE(pci, sky2_id_table);
128
129 /* Avoid conditionals by using array */
130 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
131 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
132 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
133
134 /* This driver supports yukon2 chipset only */
135 static const char *yukon2_name[] = {
136 "XL", /* 0xb3 */
137 "EC Ultra", /* 0xb4 */
138 "UNKNOWN", /* 0xb5 */
139 "EC", /* 0xb6 */
140 "FE", /* 0xb7 */
141 };
142
143 /* Access to external PHY */
144 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
145 {
146 int i;
147
148 gma_write16(hw, port, GM_SMI_DATA, val);
149 gma_write16(hw, port, GM_SMI_CTRL,
150 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
151
152 for (i = 0; i < PHY_RETRIES; i++) {
153 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
154 return 0;
155 udelay(1);
156 }
157
158 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
159 return -ETIMEDOUT;
160 }
161
162 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
163 {
164 int i;
165
166 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
167 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
168
169 for (i = 0; i < PHY_RETRIES; i++) {
170 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
171 *val = gma_read16(hw, port, GM_SMI_DATA);
172 return 0;
173 }
174
175 udelay(1);
176 }
177
178 return -ETIMEDOUT;
179 }
180
181 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
182 {
183 u16 v;
184
185 if (__gm_phy_read(hw, port, reg, &v) != 0)
186 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
187 return v;
188 }
189
190 static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
191 {
192 u16 power_control;
193 u32 reg1;
194 int vaux;
195 int ret = 0;
196
197 pr_debug("sky2_set_power_state %d\n", state);
198 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
199
200 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
201 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
202 (power_control & PCI_PM_CAP_PME_D3cold);
203
204 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
205
206 power_control |= PCI_PM_CTRL_PME_STATUS;
207 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
208
209 switch (state) {
210 case PCI_D0:
211 /* switch power to VCC (WA for VAUX problem) */
212 sky2_write8(hw, B0_POWER_CTRL,
213 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
214
215 /* disable Core Clock Division, */
216 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
217
218 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
219 /* enable bits are inverted */
220 sky2_write8(hw, B2_Y2_CLK_GATE,
221 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
222 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
223 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
224 else
225 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
226
227 /* Turn off phy power saving */
228 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
229 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
230
231 /* looks like this XL is back asswards .. */
232 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
233 reg1 |= PCI_Y2_PHY1_COMA;
234 if (hw->ports > 1)
235 reg1 |= PCI_Y2_PHY2_COMA;
236 }
237
238 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
239 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
240 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
241 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
242 reg1 &= P_ASPM_CONTROL_MSK;
243 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
244 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
245 }
246
247 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
248
249 break;
250
251 case PCI_D3hot:
252 case PCI_D3cold:
253 /* Turn on phy power saving */
254 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
255 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
256 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
257 else
258 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
259 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
260
261 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
262 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
263 else
264 /* enable bits are inverted */
265 sky2_write8(hw, B2_Y2_CLK_GATE,
266 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
267 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
268 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
269
270 /* switch power to VAUX */
271 if (vaux && state != PCI_D3cold)
272 sky2_write8(hw, B0_POWER_CTRL,
273 (PC_VAUX_ENA | PC_VCC_ENA |
274 PC_VAUX_ON | PC_VCC_OFF));
275 break;
276 default:
277 printk(KERN_ERR PFX "Unknown power state %d\n", state);
278 ret = -1;
279 }
280
281 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
282 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
283 return ret;
284 }
285
286 static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
287 {
288 u16 reg;
289
290 /* disable all GMAC IRQ's */
291 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
292 /* disable PHY IRQs */
293 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
294
295 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
296 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
297 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
298 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
299
300 reg = gma_read16(hw, port, GM_RX_CTRL);
301 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
302 gma_write16(hw, port, GM_RX_CTRL, reg);
303 }
304
305 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
306 {
307 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
308 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
309
310 if (sky2->autoneg == AUTONEG_ENABLE &&
311 !(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
312 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
313
314 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
315 PHY_M_EC_MAC_S_MSK);
316 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
317
318 if (hw->chip_id == CHIP_ID_YUKON_EC)
319 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
320 else
321 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
322
323 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
324 }
325
326 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
327 if (hw->copper) {
328 if (hw->chip_id == CHIP_ID_YUKON_FE) {
329 /* enable automatic crossover */
330 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
331 } else {
332 /* disable energy detect */
333 ctrl &= ~PHY_M_PC_EN_DET_MSK;
334
335 /* enable automatic crossover */
336 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
337
338 if (sky2->autoneg == AUTONEG_ENABLE &&
339 (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
340 ctrl &= ~PHY_M_PC_DSC_MSK;
341 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
342 }
343 }
344 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
345 } else {
346 /* workaround for deviation #4.88 (CRC errors) */
347 /* disable Automatic Crossover */
348
349 ctrl &= ~PHY_M_PC_MDIX_MSK;
350 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
351
352 if (hw->chip_id == CHIP_ID_YUKON_XL) {
353 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
354 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
355 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
356 ctrl &= ~PHY_M_MAC_MD_MSK;
357 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
358 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
359
360 /* select page 1 to access Fiber registers */
361 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
362 }
363 }
364
365 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
366 if (sky2->autoneg == AUTONEG_DISABLE)
367 ctrl &= ~PHY_CT_ANE;
368 else
369 ctrl |= PHY_CT_ANE;
370
371 ctrl |= PHY_CT_RESET;
372 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
373
374 ctrl = 0;
375 ct1000 = 0;
376 adv = PHY_AN_CSMA;
377
378 if (sky2->autoneg == AUTONEG_ENABLE) {
379 if (hw->copper) {
380 if (sky2->advertising & ADVERTISED_1000baseT_Full)
381 ct1000 |= PHY_M_1000C_AFD;
382 if (sky2->advertising & ADVERTISED_1000baseT_Half)
383 ct1000 |= PHY_M_1000C_AHD;
384 if (sky2->advertising & ADVERTISED_100baseT_Full)
385 adv |= PHY_M_AN_100_FD;
386 if (sky2->advertising & ADVERTISED_100baseT_Half)
387 adv |= PHY_M_AN_100_HD;
388 if (sky2->advertising & ADVERTISED_10baseT_Full)
389 adv |= PHY_M_AN_10_FD;
390 if (sky2->advertising & ADVERTISED_10baseT_Half)
391 adv |= PHY_M_AN_10_HD;
392 } else /* special defines for FIBER (88E1011S only) */
393 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
394
395 /* Set Flow-control capabilities */
396 if (sky2->tx_pause && sky2->rx_pause)
397 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
398 else if (sky2->rx_pause && !sky2->tx_pause)
399 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
400 else if (!sky2->rx_pause && sky2->tx_pause)
401 adv |= PHY_AN_PAUSE_ASYM; /* local */
402
403 /* Restart Auto-negotiation */
404 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
405 } else {
406 /* forced speed/duplex settings */
407 ct1000 = PHY_M_1000C_MSE;
408
409 if (sky2->duplex == DUPLEX_FULL)
410 ctrl |= PHY_CT_DUP_MD;
411
412 switch (sky2->speed) {
413 case SPEED_1000:
414 ctrl |= PHY_CT_SP1000;
415 break;
416 case SPEED_100:
417 ctrl |= PHY_CT_SP100;
418 break;
419 }
420
421 ctrl |= PHY_CT_RESET;
422 }
423
424 if (hw->chip_id != CHIP_ID_YUKON_FE)
425 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
426
427 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
428 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
429
430 /* Setup Phy LED's */
431 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
432 ledover = 0;
433
434 switch (hw->chip_id) {
435 case CHIP_ID_YUKON_FE:
436 /* on 88E3082 these bits are at 11..9 (shifted left) */
437 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
438
439 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
440
441 /* delete ACT LED control bits */
442 ctrl &= ~PHY_M_FELP_LED1_MSK;
443 /* change ACT LED control to blink mode */
444 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
445 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
446 break;
447
448 case CHIP_ID_YUKON_XL:
449 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
450
451 /* select page 3 to access LED control register */
452 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
453
454 /* set LED Function Control register */
455 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
456 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
457 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
458 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
459 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
460
461 /* set Polarity Control register */
462 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
463 (PHY_M_POLC_LS1_P_MIX(4) |
464 PHY_M_POLC_IS0_P_MIX(4) |
465 PHY_M_POLC_LOS_CTRL(2) |
466 PHY_M_POLC_INIT_CTRL(2) |
467 PHY_M_POLC_STA1_CTRL(2) |
468 PHY_M_POLC_STA0_CTRL(2)));
469
470 /* restore page register */
471 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
472 break;
473 case CHIP_ID_YUKON_EC_U:
474 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
475
476 /* select page 3 to access LED control register */
477 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
478
479 /* set LED Function Control register */
480 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
481 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
482 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
483 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
484 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
485
486 /* set Blink Rate in LED Timer Control Register */
487 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
488 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
489 /* restore page register */
490 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
491 break;
492
493 default:
494 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
495 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
496 /* turn off the Rx LED (LED_RX) */
497 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
498 }
499
500 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
501 /* apply fixes in PHY AFE */
502 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
503 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
504
505 /* increase differential signal amplitude in 10BASE-T */
506 gm_phy_write(hw, port, 0x18, 0xaa99);
507 gm_phy_write(hw, port, 0x17, 0x2011);
508
509 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
510 gm_phy_write(hw, port, 0x18, 0xa204);
511 gm_phy_write(hw, port, 0x17, 0x2002);
512
513 /* set page register to 0 */
514 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
515 } else {
516 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
517
518 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
519 /* turn on 100 Mbps LED (LED_LINK100) */
520 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
521 }
522
523 if (ledover)
524 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
525
526 }
527 /* Enable phy interrupt on auto-negotiation complete (or link up) */
528 if (sky2->autoneg == AUTONEG_ENABLE)
529 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
530 else
531 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
532 }
533
534 /* Force a renegotiation */
535 static void sky2_phy_reinit(struct sky2_port *sky2)
536 {
537 spin_lock_bh(&sky2->phy_lock);
538 sky2_phy_init(sky2->hw, sky2->port);
539 spin_unlock_bh(&sky2->phy_lock);
540 }
541
542 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
543 {
544 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
545 u16 reg;
546 int i;
547 const u8 *addr = hw->dev[port]->dev_addr;
548
549 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
550 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
551
552 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
553
554 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
555 /* WA DEV_472 -- looks like crossed wires on port 2 */
556 /* clear GMAC 1 Control reset */
557 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
558 do {
559 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
560 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
561 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
562 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
563 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
564 }
565
566 if (sky2->autoneg == AUTONEG_DISABLE) {
567 reg = gma_read16(hw, port, GM_GP_CTRL);
568 reg |= GM_GPCR_AU_ALL_DIS;
569 gma_write16(hw, port, GM_GP_CTRL, reg);
570 gma_read16(hw, port, GM_GP_CTRL);
571
572 switch (sky2->speed) {
573 case SPEED_1000:
574 reg &= ~GM_GPCR_SPEED_100;
575 reg |= GM_GPCR_SPEED_1000;
576 break;
577 case SPEED_100:
578 reg &= ~GM_GPCR_SPEED_1000;
579 reg |= GM_GPCR_SPEED_100;
580 break;
581 case SPEED_10:
582 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
583 break;
584 }
585
586 if (sky2->duplex == DUPLEX_FULL)
587 reg |= GM_GPCR_DUP_FULL;
588
589 /* turn off pause in 10/100mbps half duplex */
590 else if (sky2->speed != SPEED_1000 &&
591 hw->chip_id != CHIP_ID_YUKON_EC_U)
592 sky2->tx_pause = sky2->rx_pause = 0;
593 } else
594 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
595
596 if (!sky2->tx_pause && !sky2->rx_pause) {
597 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
598 reg |=
599 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
600 } else if (sky2->tx_pause && !sky2->rx_pause) {
601 /* disable Rx flow-control */
602 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
603 }
604
605 gma_write16(hw, port, GM_GP_CTRL, reg);
606
607 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
608
609 spin_lock_bh(&sky2->phy_lock);
610 sky2_phy_init(hw, port);
611 spin_unlock_bh(&sky2->phy_lock);
612
613 /* MIB clear */
614 reg = gma_read16(hw, port, GM_PHY_ADDR);
615 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
616
617 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
618 gma_read16(hw, port, i);
619 gma_write16(hw, port, GM_PHY_ADDR, reg);
620
621 /* transmit control */
622 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
623
624 /* receive control reg: unicast + multicast + no FCS */
625 gma_write16(hw, port, GM_RX_CTRL,
626 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
627
628 /* transmit flow control */
629 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
630
631 /* transmit parameter */
632 gma_write16(hw, port, GM_TX_PARAM,
633 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
634 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
635 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
636 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
637
638 /* serial mode register */
639 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
640 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
641
642 if (hw->dev[port]->mtu > ETH_DATA_LEN)
643 reg |= GM_SMOD_JUMBO_ENA;
644
645 gma_write16(hw, port, GM_SERIAL_MODE, reg);
646
647 /* virtual address for data */
648 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
649
650 /* physical address: used for pause frames */
651 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
652
653 /* ignore counter overflows */
654 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
655 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
656 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
657
658 /* Configure Rx MAC FIFO */
659 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
660 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
661 GMF_OPER_ON | GMF_RX_F_FL_ON);
662
663 /* Flush Rx MAC FIFO on any flow control or error */
664 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
665
666 /* Set threshold to 0xa (64 bytes)
667 * ASF disabled so no need to do WA dev #4.30
668 */
669 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
670
671 /* Configure Tx MAC FIFO */
672 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
673 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
674
675 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
676 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
677 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
678 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
679 /* set Tx GMAC FIFO Almost Empty Threshold */
680 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
681 /* Disable Store & Forward mode for TX */
682 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
683 }
684 }
685
686 }
687
688 /* Assign Ram Buffer allocation.
689 * start and end are in units of 4k bytes
690 * ram registers are in units of 64bit words
691 */
692 static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
693 {
694 u32 start, end;
695
696 start = startk * 4096/8;
697 end = (endk * 4096/8) - 1;
698
699 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
700 sky2_write32(hw, RB_ADDR(q, RB_START), start);
701 sky2_write32(hw, RB_ADDR(q, RB_END), end);
702 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
703 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
704
705 if (q == Q_R1 || q == Q_R2) {
706 u32 space = (endk - startk) * 4096/8;
707 u32 tp = space - space/4;
708
709 /* On receive queue's set the thresholds
710 * give receiver priority when > 3/4 full
711 * send pause when down to 2K
712 */
713 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
714 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
715
716 tp = space - 2048/8;
717 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
718 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
719 } else {
720 /* Enable store & forward on Tx queue's because
721 * Tx FIFO is only 1K on Yukon
722 */
723 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
724 }
725
726 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
727 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
728 }
729
730 /* Setup Bus Memory Interface */
731 static void sky2_qset(struct sky2_hw *hw, u16 q)
732 {
733 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
734 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
735 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
736 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
737 }
738
739 /* Setup prefetch unit registers. This is the interface between
740 * hardware and driver list elements
741 */
742 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
743 u64 addr, u32 last)
744 {
745 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
746 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
747 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
748 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
749 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
750 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
751
752 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
753 }
754
755 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
756 {
757 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
758
759 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
760 return le;
761 }
762
763 /* Update chip's next pointer */
764 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
765 {
766 wmb();
767 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
768 mmiowb();
769 }
770
771
772 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
773 {
774 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
775 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
776 return le;
777 }
778
779 /* Return high part of DMA address (could be 32 or 64 bit) */
780 static inline u32 high32(dma_addr_t a)
781 {
782 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
783 }
784
785 /* Build description to hardware about buffer */
786 static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
787 {
788 struct sky2_rx_le *le;
789 u32 hi = high32(map);
790 u16 len = sky2->rx_bufsize;
791
792 if (sky2->rx_addr64 != hi) {
793 le = sky2_next_rx(sky2);
794 le->addr = cpu_to_le32(hi);
795 le->ctrl = 0;
796 le->opcode = OP_ADDR64 | HW_OWNER;
797 sky2->rx_addr64 = high32(map + len);
798 }
799
800 le = sky2_next_rx(sky2);
801 le->addr = cpu_to_le32((u32) map);
802 le->length = cpu_to_le16(len);
803 le->ctrl = 0;
804 le->opcode = OP_PACKET | HW_OWNER;
805 }
806
807
808 /* Tell chip where to start receive checksum.
809 * Actually has two checksums, but set both same to avoid possible byte
810 * order problems.
811 */
812 static void rx_set_checksum(struct sky2_port *sky2)
813 {
814 struct sky2_rx_le *le;
815
816 le = sky2_next_rx(sky2);
817 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
818 le->ctrl = 0;
819 le->opcode = OP_TCPSTART | HW_OWNER;
820
821 sky2_write32(sky2->hw,
822 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
823 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
824
825 }
826
827 /*
828 * The RX Stop command will not work for Yukon-2 if the BMU does not
829 * reach the end of packet and since we can't make sure that we have
830 * incoming data, we must reset the BMU while it is not doing a DMA
831 * transfer. Since it is possible that the RX path is still active,
832 * the RX RAM buffer will be stopped first, so any possible incoming
833 * data will not trigger a DMA. After the RAM buffer is stopped, the
834 * BMU is polled until any DMA in progress is ended and only then it
835 * will be reset.
836 */
837 static void sky2_rx_stop(struct sky2_port *sky2)
838 {
839 struct sky2_hw *hw = sky2->hw;
840 unsigned rxq = rxqaddr[sky2->port];
841 int i;
842
843 /* disable the RAM Buffer receive queue */
844 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
845
846 for (i = 0; i < 0xffff; i++)
847 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
848 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
849 goto stopped;
850
851 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
852 sky2->netdev->name);
853 stopped:
854 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
855
856 /* reset the Rx prefetch unit */
857 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
858 }
859
860 /* Clean out receive buffer area, assumes receiver hardware stopped */
861 static void sky2_rx_clean(struct sky2_port *sky2)
862 {
863 unsigned i;
864
865 memset(sky2->rx_le, 0, RX_LE_BYTES);
866 for (i = 0; i < sky2->rx_pending; i++) {
867 struct ring_info *re = sky2->rx_ring + i;
868
869 if (re->skb) {
870 pci_unmap_single(sky2->hw->pdev,
871 re->mapaddr, sky2->rx_bufsize,
872 PCI_DMA_FROMDEVICE);
873 kfree_skb(re->skb);
874 re->skb = NULL;
875 }
876 }
877 }
878
879 /* Basic MII support */
880 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
881 {
882 struct mii_ioctl_data *data = if_mii(ifr);
883 struct sky2_port *sky2 = netdev_priv(dev);
884 struct sky2_hw *hw = sky2->hw;
885 int err = -EOPNOTSUPP;
886
887 if (!netif_running(dev))
888 return -ENODEV; /* Phy still in reset */
889
890 switch (cmd) {
891 case SIOCGMIIPHY:
892 data->phy_id = PHY_ADDR_MARV;
893
894 /* fallthru */
895 case SIOCGMIIREG: {
896 u16 val = 0;
897
898 spin_lock_bh(&sky2->phy_lock);
899 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
900 spin_unlock_bh(&sky2->phy_lock);
901
902 data->val_out = val;
903 break;
904 }
905
906 case SIOCSMIIREG:
907 if (!capable(CAP_NET_ADMIN))
908 return -EPERM;
909
910 spin_lock_bh(&sky2->phy_lock);
911 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
912 data->val_in);
913 spin_unlock_bh(&sky2->phy_lock);
914 break;
915 }
916 return err;
917 }
918
919 #ifdef SKY2_VLAN_TAG_USED
920 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
921 {
922 struct sky2_port *sky2 = netdev_priv(dev);
923 struct sky2_hw *hw = sky2->hw;
924 u16 port = sky2->port;
925
926 spin_lock_bh(&sky2->tx_lock);
927
928 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
929 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
930 sky2->vlgrp = grp;
931
932 spin_unlock_bh(&sky2->tx_lock);
933 }
934
935 static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
936 {
937 struct sky2_port *sky2 = netdev_priv(dev);
938 struct sky2_hw *hw = sky2->hw;
939 u16 port = sky2->port;
940
941 spin_lock_bh(&sky2->tx_lock);
942
943 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
944 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
945 if (sky2->vlgrp)
946 sky2->vlgrp->vlan_devices[vid] = NULL;
947
948 spin_unlock_bh(&sky2->tx_lock);
949 }
950 #endif
951
952 /*
953 * It appears the hardware has a bug in the FIFO logic that
954 * cause it to hang if the FIFO gets overrun and the receive buffer
955 * is not aligned. ALso alloc_skb() won't align properly if slab
956 * debugging is enabled.
957 */
958 static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)
959 {
960 struct sk_buff *skb;
961
962 skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);
963 if (likely(skb)) {
964 unsigned long p = (unsigned long) skb->data;
965 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
966 }
967
968 return skb;
969 }
970
971 /*
972 * Allocate and setup receiver buffer pool.
973 * In case of 64 bit dma, there are 2X as many list elements
974 * available as ring entries
975 * and need to reserve one list element so we don't wrap around.
976 */
977 static int sky2_rx_start(struct sky2_port *sky2)
978 {
979 struct sky2_hw *hw = sky2->hw;
980 unsigned rxq = rxqaddr[sky2->port];
981 int i;
982 unsigned thresh;
983
984 sky2->rx_put = sky2->rx_next = 0;
985 sky2_qset(hw, rxq);
986
987 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
988 /* MAC Rx RAM Read is controlled by hardware */
989 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
990 }
991
992 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
993
994 rx_set_checksum(sky2);
995 for (i = 0; i < sky2->rx_pending; i++) {
996 struct ring_info *re = sky2->rx_ring + i;
997
998 re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);
999 if (!re->skb)
1000 goto nomem;
1001
1002 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
1003 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1004 sky2_rx_add(sky2, re->mapaddr);
1005 }
1006
1007
1008 /*
1009 * The receiver hangs if it receives frames larger than the
1010 * packet buffer. As a workaround, truncate oversize frames, but
1011 * the register is limited to 9 bits, so if you do frames > 2052
1012 * you better get the MTU right!
1013 */
1014 thresh = (sky2->rx_bufsize - 8) / sizeof(u32);
1015 if (thresh > 0x1ff)
1016 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1017 else {
1018 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1019 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1020 }
1021
1022
1023 /* Tell chip about available buffers */
1024 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
1025 return 0;
1026 nomem:
1027 sky2_rx_clean(sky2);
1028 return -ENOMEM;
1029 }
1030
1031 /* Bring up network interface. */
1032 static int sky2_up(struct net_device *dev)
1033 {
1034 struct sky2_port *sky2 = netdev_priv(dev);
1035 struct sky2_hw *hw = sky2->hw;
1036 unsigned port = sky2->port;
1037 u32 ramsize, rxspace, imask;
1038 int cap, err = -ENOMEM;
1039 struct net_device *otherdev = hw->dev[sky2->port^1];
1040
1041 /*
1042 * On dual port PCI-X card, there is an problem where status
1043 * can be received out of order due to split transactions
1044 */
1045 if (otherdev && netif_running(otherdev) &&
1046 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1047 struct sky2_port *osky2 = netdev_priv(otherdev);
1048 u16 cmd;
1049
1050 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1051 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1052 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1053
1054 sky2->rx_csum = 0;
1055 osky2->rx_csum = 0;
1056 }
1057
1058 if (netif_msg_ifup(sky2))
1059 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1060
1061 /* must be power of 2 */
1062 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1063 TX_RING_SIZE *
1064 sizeof(struct sky2_tx_le),
1065 &sky2->tx_le_map);
1066 if (!sky2->tx_le)
1067 goto err_out;
1068
1069 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1070 GFP_KERNEL);
1071 if (!sky2->tx_ring)
1072 goto err_out;
1073 sky2->tx_prod = sky2->tx_cons = 0;
1074
1075 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1076 &sky2->rx_le_map);
1077 if (!sky2->rx_le)
1078 goto err_out;
1079 memset(sky2->rx_le, 0, RX_LE_BYTES);
1080
1081 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
1082 GFP_KERNEL);
1083 if (!sky2->rx_ring)
1084 goto err_out;
1085
1086 sky2_mac_init(hw, port);
1087
1088 /* Determine available ram buffer space (in 4K blocks).
1089 * Note: not sure about the FE setting below yet
1090 */
1091 if (hw->chip_id == CHIP_ID_YUKON_FE)
1092 ramsize = 4;
1093 else
1094 ramsize = sky2_read8(hw, B2_E_0);
1095
1096 /* Give transmitter one third (rounded up) */
1097 rxspace = ramsize - (ramsize + 2) / 3;
1098
1099 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1100 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
1101
1102 /* Make sure SyncQ is disabled */
1103 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1104 RB_RST_SET);
1105
1106 sky2_qset(hw, txqaddr[port]);
1107
1108 /* Set almost empty threshold */
1109 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)
1110 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1111
1112 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1113 TX_RING_SIZE - 1);
1114
1115 err = sky2_rx_start(sky2);
1116 if (err)
1117 goto err_out;
1118
1119 /* Enable interrupts from phy/mac for port */
1120 imask = sky2_read32(hw, B0_IMSK);
1121 imask |= portirq_msk[port];
1122 sky2_write32(hw, B0_IMSK, imask);
1123
1124 return 0;
1125
1126 err_out:
1127 if (sky2->rx_le) {
1128 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1129 sky2->rx_le, sky2->rx_le_map);
1130 sky2->rx_le = NULL;
1131 }
1132 if (sky2->tx_le) {
1133 pci_free_consistent(hw->pdev,
1134 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1135 sky2->tx_le, sky2->tx_le_map);
1136 sky2->tx_le = NULL;
1137 }
1138 kfree(sky2->tx_ring);
1139 kfree(sky2->rx_ring);
1140
1141 sky2->tx_ring = NULL;
1142 sky2->rx_ring = NULL;
1143 return err;
1144 }
1145
1146 /* Modular subtraction in ring */
1147 static inline int tx_dist(unsigned tail, unsigned head)
1148 {
1149 return (head - tail) & (TX_RING_SIZE - 1);
1150 }
1151
1152 /* Number of list elements available for next tx */
1153 static inline int tx_avail(const struct sky2_port *sky2)
1154 {
1155 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1156 }
1157
1158 /* Estimate of number of transmit list elements required */
1159 static unsigned tx_le_req(const struct sk_buff *skb)
1160 {
1161 unsigned count;
1162
1163 count = sizeof(dma_addr_t) / sizeof(u32);
1164 count += skb_shinfo(skb)->nr_frags * count;
1165
1166 if (skb_shinfo(skb)->tso_size)
1167 ++count;
1168
1169 if (skb->ip_summed == CHECKSUM_HW)
1170 ++count;
1171
1172 return count;
1173 }
1174
1175 /*
1176 * Put one packet in ring for transmit.
1177 * A single packet can generate multiple list elements, and
1178 * the number of ring elements will probably be less than the number
1179 * of list elements used.
1180 *
1181 * No BH disabling for tx_lock here (like tg3)
1182 */
1183 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1184 {
1185 struct sky2_port *sky2 = netdev_priv(dev);
1186 struct sky2_hw *hw = sky2->hw;
1187 struct sky2_tx_le *le = NULL;
1188 struct tx_ring_info *re;
1189 unsigned i, len;
1190 int avail;
1191 dma_addr_t mapping;
1192 u32 addr64;
1193 u16 mss;
1194 u8 ctrl;
1195
1196 /* No BH disabling for tx_lock here. We are running in BH disabled
1197 * context and TX reclaim runs via poll inside of a software
1198 * interrupt, and no related locks in IRQ processing.
1199 */
1200 if (!spin_trylock(&sky2->tx_lock))
1201 return NETDEV_TX_LOCKED;
1202
1203 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
1204 /* There is a known but harmless race with lockless tx
1205 * and netif_stop_queue.
1206 */
1207 if (!netif_queue_stopped(dev)) {
1208 netif_stop_queue(dev);
1209 if (net_ratelimit())
1210 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1211 dev->name);
1212 }
1213 spin_unlock(&sky2->tx_lock);
1214
1215 return NETDEV_TX_BUSY;
1216 }
1217
1218 if (unlikely(netif_msg_tx_queued(sky2)))
1219 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1220 dev->name, sky2->tx_prod, skb->len);
1221
1222 len = skb_headlen(skb);
1223 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1224 addr64 = high32(mapping);
1225
1226 re = sky2->tx_ring + sky2->tx_prod;
1227
1228 /* Send high bits if changed or crosses boundary */
1229 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
1230 le = get_tx_le(sky2);
1231 le->tx.addr = cpu_to_le32(addr64);
1232 le->ctrl = 0;
1233 le->opcode = OP_ADDR64 | HW_OWNER;
1234 sky2->tx_addr64 = high32(mapping + len);
1235 }
1236
1237 /* Check for TCP Segmentation Offload */
1238 mss = skb_shinfo(skb)->tso_size;
1239 if (mss != 0) {
1240 /* just drop the packet if non-linear expansion fails */
1241 if (skb_header_cloned(skb) &&
1242 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
1243 dev_kfree_skb(skb);
1244 goto out_unlock;
1245 }
1246
1247 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1248 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1249 mss += ETH_HLEN;
1250 }
1251
1252 if (mss != sky2->tx_last_mss) {
1253 le = get_tx_le(sky2);
1254 le->tx.tso.size = cpu_to_le16(mss);
1255 le->tx.tso.rsvd = 0;
1256 le->opcode = OP_LRGLEN | HW_OWNER;
1257 le->ctrl = 0;
1258 sky2->tx_last_mss = mss;
1259 }
1260
1261 ctrl = 0;
1262 #ifdef SKY2_VLAN_TAG_USED
1263 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1264 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1265 if (!le) {
1266 le = get_tx_le(sky2);
1267 le->tx.addr = 0;
1268 le->opcode = OP_VLAN|HW_OWNER;
1269 le->ctrl = 0;
1270 } else
1271 le->opcode |= OP_VLAN;
1272 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1273 ctrl |= INS_VLAN;
1274 }
1275 #endif
1276
1277 /* Handle TCP checksum offload */
1278 if (skb->ip_summed == CHECKSUM_HW) {
1279 u16 hdr = skb->h.raw - skb->data;
1280 u16 offset = hdr + skb->csum;
1281
1282 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1283 if (skb->nh.iph->protocol == IPPROTO_UDP)
1284 ctrl |= UDPTCP;
1285
1286 le = get_tx_le(sky2);
1287 le->tx.csum.start = cpu_to_le16(hdr);
1288 le->tx.csum.offset = cpu_to_le16(offset);
1289 le->length = 0; /* initial checksum value */
1290 le->ctrl = 1; /* one packet */
1291 le->opcode = OP_TCPLISW | HW_OWNER;
1292 }
1293
1294 le = get_tx_le(sky2);
1295 le->tx.addr = cpu_to_le32((u32) mapping);
1296 le->length = cpu_to_le16(len);
1297 le->ctrl = ctrl;
1298 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1299
1300 /* Record the transmit mapping info */
1301 re->skb = skb;
1302 pci_unmap_addr_set(re, mapaddr, mapping);
1303
1304 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1305 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1306 struct tx_ring_info *fre;
1307
1308 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1309 frag->size, PCI_DMA_TODEVICE);
1310 addr64 = high32(mapping);
1311 if (addr64 != sky2->tx_addr64) {
1312 le = get_tx_le(sky2);
1313 le->tx.addr = cpu_to_le32(addr64);
1314 le->ctrl = 0;
1315 le->opcode = OP_ADDR64 | HW_OWNER;
1316 sky2->tx_addr64 = addr64;
1317 }
1318
1319 le = get_tx_le(sky2);
1320 le->tx.addr = cpu_to_le32((u32) mapping);
1321 le->length = cpu_to_le16(frag->size);
1322 le->ctrl = ctrl;
1323 le->opcode = OP_BUFFER | HW_OWNER;
1324
1325 fre = sky2->tx_ring
1326 + RING_NEXT((re - sky2->tx_ring) + i, TX_RING_SIZE);
1327 pci_unmap_addr_set(fre, mapaddr, mapping);
1328 }
1329
1330 re->idx = sky2->tx_prod;
1331 le->ctrl |= EOP;
1332
1333 avail = tx_avail(sky2);
1334 if (mss != 0 || avail < TX_MIN_PENDING) {
1335 le->ctrl |= FRC_STAT;
1336 if (avail <= MAX_SKB_TX_LE)
1337 netif_stop_queue(dev);
1338 }
1339
1340 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1341
1342 out_unlock:
1343 spin_unlock(&sky2->tx_lock);
1344
1345 dev->trans_start = jiffies;
1346 return NETDEV_TX_OK;
1347 }
1348
1349 /*
1350 * Free ring elements from starting at tx_cons until "done"
1351 *
1352 * NB: the hardware will tell us about partial completion of multi-part
1353 * buffers; these are deferred until completion.
1354 */
1355 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1356 {
1357 struct net_device *dev = sky2->netdev;
1358 struct pci_dev *pdev = sky2->hw->pdev;
1359 u16 nxt, put;
1360 unsigned i;
1361
1362 BUG_ON(done >= TX_RING_SIZE);
1363
1364 if (unlikely(netif_msg_tx_done(sky2)))
1365 printk(KERN_DEBUG "%s: tx done, up to %u\n",
1366 dev->name, done);
1367
1368 for (put = sky2->tx_cons; put != done; put = nxt) {
1369 struct tx_ring_info *re = sky2->tx_ring + put;
1370 struct sk_buff *skb = re->skb;
1371
1372 nxt = re->idx;
1373 BUG_ON(nxt >= TX_RING_SIZE);
1374 prefetch(sky2->tx_ring + nxt);
1375
1376 /* Check for partial status */
1377 if (tx_dist(put, done) < tx_dist(put, nxt))
1378 break;
1379
1380 skb = re->skb;
1381 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1382 skb_headlen(skb), PCI_DMA_TODEVICE);
1383
1384 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1385 struct tx_ring_info *fre;
1386 fre = sky2->tx_ring + RING_NEXT(put + i, TX_RING_SIZE);
1387 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
1388 skb_shinfo(skb)->frags[i].size,
1389 PCI_DMA_TODEVICE);
1390 }
1391
1392 dev_kfree_skb(skb);
1393 }
1394
1395 sky2->tx_cons = put;
1396 if (tx_avail(sky2) > MAX_SKB_TX_LE)
1397 netif_wake_queue(dev);
1398 }
1399
1400 /* Cleanup all untransmitted buffers, assume transmitter not running */
1401 static void sky2_tx_clean(struct sky2_port *sky2)
1402 {
1403 spin_lock_bh(&sky2->tx_lock);
1404 sky2_tx_complete(sky2, sky2->tx_prod);
1405 spin_unlock_bh(&sky2->tx_lock);
1406 }
1407
1408 /* Network shutdown */
1409 static int sky2_down(struct net_device *dev)
1410 {
1411 struct sky2_port *sky2 = netdev_priv(dev);
1412 struct sky2_hw *hw = sky2->hw;
1413 unsigned port = sky2->port;
1414 u16 ctrl;
1415 u32 imask;
1416
1417 /* Never really got started! */
1418 if (!sky2->tx_le)
1419 return 0;
1420
1421 if (netif_msg_ifdown(sky2))
1422 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1423
1424 /* Stop more packets from being queued */
1425 netif_stop_queue(dev);
1426
1427 sky2_phy_reset(hw, port);
1428
1429 /* Stop transmitter */
1430 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1431 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1432
1433 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1434 RB_RST_SET | RB_DIS_OP_MD);
1435
1436 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1437 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1438 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1439
1440 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1441
1442 /* Workaround shared GMAC reset */
1443 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1444 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1445 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1446
1447 /* Disable Force Sync bit and Enable Alloc bit */
1448 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1449 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1450
1451 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1452 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1453 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1454
1455 /* Reset the PCI FIFO of the async Tx queue */
1456 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1457 BMU_RST_SET | BMU_FIFO_RST);
1458
1459 /* Reset the Tx prefetch units */
1460 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1461 PREF_UNIT_RST_SET);
1462
1463 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1464
1465 sky2_rx_stop(sky2);
1466
1467 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1468 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1469
1470 /* Disable port IRQ */
1471 imask = sky2_read32(hw, B0_IMSK);
1472 imask &= ~portirq_msk[port];
1473 sky2_write32(hw, B0_IMSK, imask);
1474
1475 /* turn off LED's */
1476 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1477
1478 synchronize_irq(hw->pdev->irq);
1479
1480 sky2_tx_clean(sky2);
1481 sky2_rx_clean(sky2);
1482
1483 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1484 sky2->rx_le, sky2->rx_le_map);
1485 kfree(sky2->rx_ring);
1486
1487 pci_free_consistent(hw->pdev,
1488 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1489 sky2->tx_le, sky2->tx_le_map);
1490 kfree(sky2->tx_ring);
1491
1492 sky2->tx_le = NULL;
1493 sky2->rx_le = NULL;
1494
1495 sky2->rx_ring = NULL;
1496 sky2->tx_ring = NULL;
1497
1498 return 0;
1499 }
1500
1501 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1502 {
1503 if (!hw->copper)
1504 return SPEED_1000;
1505
1506 if (hw->chip_id == CHIP_ID_YUKON_FE)
1507 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1508
1509 switch (aux & PHY_M_PS_SPEED_MSK) {
1510 case PHY_M_PS_SPEED_1000:
1511 return SPEED_1000;
1512 case PHY_M_PS_SPEED_100:
1513 return SPEED_100;
1514 default:
1515 return SPEED_10;
1516 }
1517 }
1518
1519 static void sky2_link_up(struct sky2_port *sky2)
1520 {
1521 struct sky2_hw *hw = sky2->hw;
1522 unsigned port = sky2->port;
1523 u16 reg;
1524
1525 /* Enable Transmit FIFO Underrun */
1526 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1527
1528 reg = gma_read16(hw, port, GM_GP_CTRL);
1529 if (sky2->autoneg == AUTONEG_DISABLE) {
1530 reg |= GM_GPCR_AU_ALL_DIS;
1531
1532 /* Is write/read necessary? Copied from sky2_mac_init */
1533 gma_write16(hw, port, GM_GP_CTRL, reg);
1534 gma_read16(hw, port, GM_GP_CTRL);
1535
1536 switch (sky2->speed) {
1537 case SPEED_1000:
1538 reg &= ~GM_GPCR_SPEED_100;
1539 reg |= GM_GPCR_SPEED_1000;
1540 break;
1541 case SPEED_100:
1542 reg &= ~GM_GPCR_SPEED_1000;
1543 reg |= GM_GPCR_SPEED_100;
1544 break;
1545 case SPEED_10:
1546 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1547 break;
1548 }
1549 } else
1550 reg &= ~GM_GPCR_AU_ALL_DIS;
1551
1552 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1553 reg |= GM_GPCR_DUP_FULL;
1554
1555 /* enable Rx/Tx */
1556 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1557 gma_write16(hw, port, GM_GP_CTRL, reg);
1558 gma_read16(hw, port, GM_GP_CTRL);
1559
1560 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1561
1562 netif_carrier_on(sky2->netdev);
1563 netif_wake_queue(sky2->netdev);
1564
1565 /* Turn on link LED */
1566 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1567 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1568
1569 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
1570 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1571 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1572
1573 switch(sky2->speed) {
1574 case SPEED_10:
1575 led |= PHY_M_LEDC_INIT_CTRL(7);
1576 break;
1577
1578 case SPEED_100:
1579 led |= PHY_M_LEDC_STA1_CTRL(7);
1580 break;
1581
1582 case SPEED_1000:
1583 led |= PHY_M_LEDC_STA0_CTRL(7);
1584 break;
1585 }
1586
1587 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1588 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
1589 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1590 }
1591
1592 if (netif_msg_link(sky2))
1593 printk(KERN_INFO PFX
1594 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1595 sky2->netdev->name, sky2->speed,
1596 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1597 (sky2->tx_pause && sky2->rx_pause) ? "both" :
1598 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
1599 }
1600
1601 static void sky2_link_down(struct sky2_port *sky2)
1602 {
1603 struct sky2_hw *hw = sky2->hw;
1604 unsigned port = sky2->port;
1605 u16 reg;
1606
1607 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1608
1609 reg = gma_read16(hw, port, GM_GP_CTRL);
1610 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1611 gma_write16(hw, port, GM_GP_CTRL, reg);
1612 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1613
1614 if (sky2->rx_pause && !sky2->tx_pause) {
1615 /* restore Asymmetric Pause bit */
1616 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1617 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1618 | PHY_M_AN_ASP);
1619 }
1620
1621 netif_carrier_off(sky2->netdev);
1622 netif_stop_queue(sky2->netdev);
1623
1624 /* Turn on link LED */
1625 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1626
1627 if (netif_msg_link(sky2))
1628 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1629 sky2_phy_init(hw, port);
1630 }
1631
1632 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1633 {
1634 struct sky2_hw *hw = sky2->hw;
1635 unsigned port = sky2->port;
1636 u16 lpa;
1637
1638 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1639
1640 if (lpa & PHY_M_AN_RF) {
1641 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1642 return -1;
1643 }
1644
1645 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1646 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1647 printk(KERN_ERR PFX "%s: master/slave fault",
1648 sky2->netdev->name);
1649 return -1;
1650 }
1651
1652 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1653 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1654 sky2->netdev->name);
1655 return -1;
1656 }
1657
1658 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1659
1660 sky2->speed = sky2_phy_speed(hw, aux);
1661
1662 /* Pause bits are offset (9..8) */
1663 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
1664 aux >>= 6;
1665
1666 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1667 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1668
1669 if ((sky2->tx_pause || sky2->rx_pause)
1670 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1671 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1672 else
1673 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1674
1675 return 0;
1676 }
1677
1678 /* Interrupt from PHY */
1679 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1680 {
1681 struct net_device *dev = hw->dev[port];
1682 struct sky2_port *sky2 = netdev_priv(dev);
1683 u16 istatus, phystat;
1684
1685 spin_lock(&sky2->phy_lock);
1686 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1687 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1688
1689 if (!netif_running(dev))
1690 goto out;
1691
1692 if (netif_msg_intr(sky2))
1693 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1694 sky2->netdev->name, istatus, phystat);
1695
1696 if (istatus & PHY_M_IS_AN_COMPL) {
1697 if (sky2_autoneg_done(sky2, phystat) == 0)
1698 sky2_link_up(sky2);
1699 goto out;
1700 }
1701
1702 if (istatus & PHY_M_IS_LSP_CHANGE)
1703 sky2->speed = sky2_phy_speed(hw, phystat);
1704
1705 if (istatus & PHY_M_IS_DUP_CHANGE)
1706 sky2->duplex =
1707 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1708
1709 if (istatus & PHY_M_IS_LST_CHANGE) {
1710 if (phystat & PHY_M_PS_LINK_UP)
1711 sky2_link_up(sky2);
1712 else
1713 sky2_link_down(sky2);
1714 }
1715 out:
1716 spin_unlock(&sky2->phy_lock);
1717 }
1718
1719
1720 /* Transmit timeout is only called if we are running, carries is up
1721 * and tx queue is full (stopped).
1722 */
1723 static void sky2_tx_timeout(struct net_device *dev)
1724 {
1725 struct sky2_port *sky2 = netdev_priv(dev);
1726 struct sky2_hw *hw = sky2->hw;
1727 unsigned txq = txqaddr[sky2->port];
1728 u16 report, done;
1729
1730 if (netif_msg_timer(sky2))
1731 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1732
1733 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1734 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
1735
1736 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1737 dev->name,
1738 sky2->tx_cons, sky2->tx_prod, report, done);
1739
1740 if (report != done) {
1741 printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
1742
1743 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1744 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1745 } else if (report != sky2->tx_cons) {
1746 printk(KERN_INFO PFX "status report lost?\n");
1747
1748 spin_lock_bh(&sky2->tx_lock);
1749 sky2_tx_complete(sky2, report);
1750 spin_unlock_bh(&sky2->tx_lock);
1751 } else {
1752 printk(KERN_INFO PFX "hardware hung? flushing\n");
1753
1754 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1755 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1756
1757 sky2_tx_clean(sky2);
1758
1759 sky2_qset(hw, txq);
1760 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1761 }
1762 }
1763
1764
1765 /* Want receive buffer size to be multiple of 64 bits
1766 * and incl room for vlan and truncation
1767 */
1768 static inline unsigned sky2_buf_size(int mtu)
1769 {
1770 return ALIGN(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8;
1771 }
1772
1773 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1774 {
1775 struct sky2_port *sky2 = netdev_priv(dev);
1776 struct sky2_hw *hw = sky2->hw;
1777 int err;
1778 u16 ctl, mode;
1779 u32 imask;
1780
1781 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1782 return -EINVAL;
1783
1784 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1785 return -EINVAL;
1786
1787 if (!netif_running(dev)) {
1788 dev->mtu = new_mtu;
1789 return 0;
1790 }
1791
1792 imask = sky2_read32(hw, B0_IMSK);
1793 sky2_write32(hw, B0_IMSK, 0);
1794
1795 dev->trans_start = jiffies; /* prevent tx timeout */
1796 netif_stop_queue(dev);
1797 netif_poll_disable(hw->dev[0]);
1798
1799 synchronize_irq(hw->pdev->irq);
1800
1801 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1802 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1803 sky2_rx_stop(sky2);
1804 sky2_rx_clean(sky2);
1805
1806 dev->mtu = new_mtu;
1807 sky2->rx_bufsize = sky2_buf_size(new_mtu);
1808 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1809 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1810
1811 if (dev->mtu > ETH_DATA_LEN)
1812 mode |= GM_SMOD_JUMBO_ENA;
1813
1814 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1815
1816 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1817
1818 err = sky2_rx_start(sky2);
1819 sky2_write32(hw, B0_IMSK, imask);
1820
1821 if (err)
1822 dev_close(dev);
1823 else {
1824 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1825
1826 netif_poll_enable(hw->dev[0]);
1827 netif_wake_queue(dev);
1828 }
1829
1830 return err;
1831 }
1832
1833 /*
1834 * Receive one packet.
1835 * For small packets or errors, just reuse existing skb.
1836 * For larger packets, get new buffer.
1837 */
1838 static struct sk_buff *sky2_receive(struct sky2_port *sky2,
1839 u16 length, u32 status)
1840 {
1841 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
1842 struct sk_buff *skb = NULL;
1843
1844 if (unlikely(netif_msg_rx_status(sky2)))
1845 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
1846 sky2->netdev->name, sky2->rx_next, status, length);
1847
1848 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
1849 prefetch(sky2->rx_ring + sky2->rx_next);
1850
1851 if (status & GMR_FS_ANY_ERR)
1852 goto error;
1853
1854 if (!(status & GMR_FS_RX_OK))
1855 goto resubmit;
1856
1857 if (length > sky2->netdev->mtu + ETH_HLEN)
1858 goto oversize;
1859
1860 if (length < copybreak) {
1861 skb = alloc_skb(length + 2, GFP_ATOMIC);
1862 if (!skb)
1863 goto resubmit;
1864
1865 skb_reserve(skb, 2);
1866 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1867 length, PCI_DMA_FROMDEVICE);
1868 memcpy(skb->data, re->skb->data, length);
1869 skb->ip_summed = re->skb->ip_summed;
1870 skb->csum = re->skb->csum;
1871 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1872 length, PCI_DMA_FROMDEVICE);
1873 } else {
1874 struct sk_buff *nskb;
1875
1876 nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);
1877 if (!nskb)
1878 goto resubmit;
1879
1880 skb = re->skb;
1881 re->skb = nskb;
1882 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1883 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1884 prefetch(skb->data);
1885
1886 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
1887 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1888 }
1889
1890 skb_put(skb, length);
1891 resubmit:
1892 re->skb->ip_summed = CHECKSUM_NONE;
1893 sky2_rx_add(sky2, re->mapaddr);
1894
1895 /* Tell receiver about new buffers. */
1896 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put);
1897
1898 return skb;
1899
1900 oversize:
1901 ++sky2->net_stats.rx_over_errors;
1902 goto resubmit;
1903
1904 error:
1905 ++sky2->net_stats.rx_errors;
1906
1907 if (netif_msg_rx_err(sky2) && net_ratelimit())
1908 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1909 sky2->netdev->name, status, length);
1910
1911 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
1912 sky2->net_stats.rx_length_errors++;
1913 if (status & GMR_FS_FRAGMENT)
1914 sky2->net_stats.rx_frame_errors++;
1915 if (status & GMR_FS_CRC_ERR)
1916 sky2->net_stats.rx_crc_errors++;
1917 if (status & GMR_FS_RX_FF_OV)
1918 sky2->net_stats.rx_fifo_errors++;
1919
1920 goto resubmit;
1921 }
1922
1923 /* Transmit complete */
1924 static inline void sky2_tx_done(struct net_device *dev, u16 last)
1925 {
1926 struct sky2_port *sky2 = netdev_priv(dev);
1927
1928 if (netif_running(dev)) {
1929 spin_lock(&sky2->tx_lock);
1930 sky2_tx_complete(sky2, last);
1931 spin_unlock(&sky2->tx_lock);
1932 }
1933 }
1934
1935 /* Is status ring empty or is there more to do? */
1936 static inline int sky2_more_work(const struct sky2_hw *hw)
1937 {
1938 return (hw->st_idx != sky2_read16(hw, STAT_PUT_IDX));
1939 }
1940
1941 /* Process status response ring */
1942 static int sky2_status_intr(struct sky2_hw *hw, int to_do)
1943 {
1944 int work_done = 0;
1945 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1946
1947 rmb();
1948
1949 while (hw->st_idx != hwidx) {
1950 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1951 struct net_device *dev;
1952 struct sky2_port *sky2;
1953 struct sk_buff *skb;
1954 u32 status;
1955 u16 length;
1956
1957 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
1958
1959 BUG_ON(le->link >= 2);
1960 dev = hw->dev[le->link];
1961
1962 sky2 = netdev_priv(dev);
1963 length = le->length;
1964 status = le->status;
1965
1966 switch (le->opcode & ~HW_OWNER) {
1967 case OP_RXSTAT:
1968 skb = sky2_receive(sky2, length, status);
1969 if (!skb)
1970 break;
1971
1972 skb->dev = dev;
1973 skb->protocol = eth_type_trans(skb, dev);
1974 dev->last_rx = jiffies;
1975
1976 #ifdef SKY2_VLAN_TAG_USED
1977 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1978 vlan_hwaccel_receive_skb(skb,
1979 sky2->vlgrp,
1980 be16_to_cpu(sky2->rx_tag));
1981 } else
1982 #endif
1983 netif_receive_skb(skb);
1984
1985 if (++work_done >= to_do)
1986 goto exit_loop;
1987 break;
1988
1989 #ifdef SKY2_VLAN_TAG_USED
1990 case OP_RXVLAN:
1991 sky2->rx_tag = length;
1992 break;
1993
1994 case OP_RXCHKSVLAN:
1995 sky2->rx_tag = length;
1996 /* fall through */
1997 #endif
1998 case OP_RXCHKS:
1999 skb = sky2->rx_ring[sky2->rx_next].skb;
2000 skb->ip_summed = CHECKSUM_HW;
2001 skb->csum = le16_to_cpu(status);
2002 break;
2003
2004 case OP_TXINDEXLE:
2005 /* TX index reports status for both ports */
2006 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2007 sky2_tx_done(hw->dev[0], status & 0xfff);
2008 if (hw->dev[1])
2009 sky2_tx_done(hw->dev[1],
2010 ((status >> 24) & 0xff)
2011 | (u16)(length & 0xf) << 8);
2012 break;
2013
2014 default:
2015 if (net_ratelimit())
2016 printk(KERN_WARNING PFX
2017 "unknown status opcode 0x%x\n", le->opcode);
2018 goto exit_loop;
2019 }
2020 }
2021
2022 exit_loop:
2023 return work_done;
2024 }
2025
2026 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2027 {
2028 struct net_device *dev = hw->dev[port];
2029
2030 if (net_ratelimit())
2031 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2032 dev->name, status);
2033
2034 if (status & Y2_IS_PAR_RD1) {
2035 if (net_ratelimit())
2036 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2037 dev->name);
2038 /* Clear IRQ */
2039 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2040 }
2041
2042 if (status & Y2_IS_PAR_WR1) {
2043 if (net_ratelimit())
2044 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2045 dev->name);
2046
2047 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2048 }
2049
2050 if (status & Y2_IS_PAR_MAC1) {
2051 if (net_ratelimit())
2052 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2053 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2054 }
2055
2056 if (status & Y2_IS_PAR_RX1) {
2057 if (net_ratelimit())
2058 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2059 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2060 }
2061
2062 if (status & Y2_IS_TCP_TXA1) {
2063 if (net_ratelimit())
2064 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2065 dev->name);
2066 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2067 }
2068 }
2069
2070 static void sky2_hw_intr(struct sky2_hw *hw)
2071 {
2072 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2073
2074 if (status & Y2_IS_TIST_OV)
2075 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2076
2077 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2078 u16 pci_err;
2079
2080 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2081 if (net_ratelimit())
2082 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2083 pci_name(hw->pdev), pci_err);
2084
2085 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2086 sky2_pci_write16(hw, PCI_STATUS,
2087 pci_err | PCI_STATUS_ERROR_BITS);
2088 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2089 }
2090
2091 if (status & Y2_IS_PCI_EXP) {
2092 /* PCI-Express uncorrectable Error occurred */
2093 u32 pex_err;
2094
2095 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
2096
2097 if (net_ratelimit())
2098 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2099 pci_name(hw->pdev), pex_err);
2100
2101 /* clear the interrupt */
2102 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2103 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2104 0xffffffffUL);
2105 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2106
2107 if (pex_err & PEX_FATAL_ERRORS) {
2108 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2109 hwmsk &= ~Y2_IS_PCI_EXP;
2110 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2111 }
2112 }
2113
2114 if (status & Y2_HWE_L1_MASK)
2115 sky2_hw_error(hw, 0, status);
2116 status >>= 8;
2117 if (status & Y2_HWE_L1_MASK)
2118 sky2_hw_error(hw, 1, status);
2119 }
2120
2121 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2122 {
2123 struct net_device *dev = hw->dev[port];
2124 struct sky2_port *sky2 = netdev_priv(dev);
2125 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2126
2127 if (netif_msg_intr(sky2))
2128 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2129 dev->name, status);
2130
2131 if (status & GM_IS_RX_FF_OR) {
2132 ++sky2->net_stats.rx_fifo_errors;
2133 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2134 }
2135
2136 if (status & GM_IS_TX_FF_UR) {
2137 ++sky2->net_stats.tx_fifo_errors;
2138 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2139 }
2140 }
2141
2142 /* This should never happen it is a fatal situation */
2143 static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2144 const char *rxtx, u32 mask)
2145 {
2146 struct net_device *dev = hw->dev[port];
2147 struct sky2_port *sky2 = netdev_priv(dev);
2148 u32 imask;
2149
2150 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2151 dev ? dev->name : "<not registered>", rxtx);
2152
2153 imask = sky2_read32(hw, B0_IMSK);
2154 imask &= ~mask;
2155 sky2_write32(hw, B0_IMSK, imask);
2156
2157 if (dev) {
2158 spin_lock(&sky2->phy_lock);
2159 sky2_link_down(sky2);
2160 spin_unlock(&sky2->phy_lock);
2161 }
2162 }
2163
2164 /* If idle then force a fake soft NAPI poll once a second
2165 * to work around cases where sharing an edge triggered interrupt.
2166 */
2167 static void sky2_idle(unsigned long arg)
2168 {
2169 struct sky2_hw *hw = (struct sky2_hw *) arg;
2170 struct net_device *dev = hw->dev[0];
2171
2172 if (__netif_rx_schedule_prep(dev))
2173 __netif_rx_schedule(dev);
2174
2175 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
2176 }
2177
2178
2179 static int sky2_poll(struct net_device *dev0, int *budget)
2180 {
2181 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2182 int work_limit = min(dev0->quota, *budget);
2183 int work_done = 0;
2184 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2185
2186 if (status & Y2_IS_HW_ERR)
2187 sky2_hw_intr(hw);
2188
2189 if (status & Y2_IS_IRQ_PHY1)
2190 sky2_phy_intr(hw, 0);
2191
2192 if (status & Y2_IS_IRQ_PHY2)
2193 sky2_phy_intr(hw, 1);
2194
2195 if (status & Y2_IS_IRQ_MAC1)
2196 sky2_mac_intr(hw, 0);
2197
2198 if (status & Y2_IS_IRQ_MAC2)
2199 sky2_mac_intr(hw, 1);
2200
2201 if (status & Y2_IS_CHK_RX1)
2202 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
2203
2204 if (status & Y2_IS_CHK_RX2)
2205 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
2206
2207 if (status & Y2_IS_CHK_TXA1)
2208 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
2209
2210 if (status & Y2_IS_CHK_TXA2)
2211 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
2212
2213 work_done = sky2_status_intr(hw, work_limit);
2214 *budget -= work_done;
2215 dev0->quota -= work_done;
2216
2217 if (status & Y2_IS_STAT_BMU)
2218 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2219
2220 if (sky2_more_work(hw))
2221 return 1;
2222
2223 netif_rx_complete(dev0);
2224
2225 sky2_read32(hw, B0_Y2_SP_LISR);
2226 return 0;
2227 }
2228
2229 static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2230 {
2231 struct sky2_hw *hw = dev_id;
2232 struct net_device *dev0 = hw->dev[0];
2233 u32 status;
2234
2235 /* Reading this mask interrupts as side effect */
2236 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2237 if (status == 0 || status == ~0)
2238 return IRQ_NONE;
2239
2240 prefetch(&hw->st_le[hw->st_idx]);
2241 if (likely(__netif_rx_schedule_prep(dev0)))
2242 __netif_rx_schedule(dev0);
2243
2244 return IRQ_HANDLED;
2245 }
2246
2247 #ifdef CONFIG_NET_POLL_CONTROLLER
2248 static void sky2_netpoll(struct net_device *dev)
2249 {
2250 struct sky2_port *sky2 = netdev_priv(dev);
2251
2252 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
2253 }
2254 #endif
2255
2256 /* Chip internal frequency for clock calculations */
2257 static inline u32 sky2_mhz(const struct sky2_hw *hw)
2258 {
2259 switch (hw->chip_id) {
2260 case CHIP_ID_YUKON_EC:
2261 case CHIP_ID_YUKON_EC_U:
2262 return 125; /* 125 Mhz */
2263 case CHIP_ID_YUKON_FE:
2264 return 100; /* 100 Mhz */
2265 default: /* YUKON_XL */
2266 return 156; /* 156 Mhz */
2267 }
2268 }
2269
2270 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2271 {
2272 return sky2_mhz(hw) * us;
2273 }
2274
2275 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2276 {
2277 return clk / sky2_mhz(hw);
2278 }
2279
2280
2281 static int __devinit sky2_reset(struct sky2_hw *hw)
2282 {
2283 u16 status;
2284 u8 t8, pmd_type;
2285 int i;
2286
2287 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2288
2289 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2290 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2291 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2292 pci_name(hw->pdev), hw->chip_id);
2293 return -EOPNOTSUPP;
2294 }
2295
2296 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2297
2298 /* This rev is really old, and requires untested workarounds */
2299 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2300 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2301 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2302 hw->chip_id, hw->chip_rev);
2303 return -EOPNOTSUPP;
2304 }
2305
2306 /* disable ASF */
2307 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2308 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2309 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2310 }
2311
2312 /* do a SW reset */
2313 sky2_write8(hw, B0_CTST, CS_RST_SET);
2314 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2315
2316 /* clear PCI errors, if any */
2317 status = sky2_pci_read16(hw, PCI_STATUS);
2318
2319 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2320 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2321
2322
2323 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2324
2325 /* clear any PEX errors */
2326 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2327 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2328
2329
2330 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2331 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2332
2333 hw->ports = 1;
2334 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2335 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2336 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2337 ++hw->ports;
2338 }
2339
2340 sky2_set_power_state(hw, PCI_D0);
2341
2342 for (i = 0; i < hw->ports; i++) {
2343 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2344 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2345 }
2346
2347 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2348
2349 /* Clear I2C IRQ noise */
2350 sky2_write32(hw, B2_I2C_IRQ, 1);
2351
2352 /* turn off hardware timer (unused) */
2353 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2354 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2355
2356 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2357
2358 /* Turn off descriptor polling */
2359 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2360
2361 /* Turn off receive timestamp */
2362 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2363 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2364
2365 /* enable the Tx Arbiters */
2366 for (i = 0; i < hw->ports; i++)
2367 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2368
2369 /* Initialize ram interface */
2370 for (i = 0; i < hw->ports; i++) {
2371 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2372
2373 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2374 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2375 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2376 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2377 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2378 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2379 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2380 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2381 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2382 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2383 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2384 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2385 }
2386
2387 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2388
2389 for (i = 0; i < hw->ports; i++)
2390 sky2_phy_reset(hw, i);
2391
2392 memset(hw->st_le, 0, STATUS_LE_BYTES);
2393 hw->st_idx = 0;
2394
2395 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2396 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2397
2398 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2399 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2400
2401 /* Set the list last index */
2402 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2403
2404 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2405 sky2_write8(hw, STAT_FIFO_WM, 16);
2406
2407 /* set Status-FIFO ISR watermark */
2408 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2409 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2410 else
2411 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2412
2413 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2414 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2415 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2416
2417 /* enable status unit */
2418 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2419
2420 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2421 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2422 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2423
2424 return 0;
2425 }
2426
2427 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2428 {
2429 u32 modes;
2430 if (hw->copper) {
2431 modes = SUPPORTED_10baseT_Half
2432 | SUPPORTED_10baseT_Full
2433 | SUPPORTED_100baseT_Half
2434 | SUPPORTED_100baseT_Full
2435 | SUPPORTED_Autoneg | SUPPORTED_TP;
2436
2437 if (hw->chip_id != CHIP_ID_YUKON_FE)
2438 modes |= SUPPORTED_1000baseT_Half
2439 | SUPPORTED_1000baseT_Full;
2440 } else
2441 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
2442 | SUPPORTED_Autoneg;
2443 return modes;
2444 }
2445
2446 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2447 {
2448 struct sky2_port *sky2 = netdev_priv(dev);
2449 struct sky2_hw *hw = sky2->hw;
2450
2451 ecmd->transceiver = XCVR_INTERNAL;
2452 ecmd->supported = sky2_supported_modes(hw);
2453 ecmd->phy_address = PHY_ADDR_MARV;
2454 if (hw->copper) {
2455 ecmd->supported = SUPPORTED_10baseT_Half
2456 | SUPPORTED_10baseT_Full
2457 | SUPPORTED_100baseT_Half
2458 | SUPPORTED_100baseT_Full
2459 | SUPPORTED_1000baseT_Half
2460 | SUPPORTED_1000baseT_Full
2461 | SUPPORTED_Autoneg | SUPPORTED_TP;
2462 ecmd->port = PORT_TP;
2463 } else
2464 ecmd->port = PORT_FIBRE;
2465
2466 ecmd->advertising = sky2->advertising;
2467 ecmd->autoneg = sky2->autoneg;
2468 ecmd->speed = sky2->speed;
2469 ecmd->duplex = sky2->duplex;
2470 return 0;
2471 }
2472
2473 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2474 {
2475 struct sky2_port *sky2 = netdev_priv(dev);
2476 const struct sky2_hw *hw = sky2->hw;
2477 u32 supported = sky2_supported_modes(hw);
2478
2479 if (ecmd->autoneg == AUTONEG_ENABLE) {
2480 ecmd->advertising = supported;
2481 sky2->duplex = -1;
2482 sky2->speed = -1;
2483 } else {
2484 u32 setting;
2485
2486 switch (ecmd->speed) {
2487 case SPEED_1000:
2488 if (ecmd->duplex == DUPLEX_FULL)
2489 setting = SUPPORTED_1000baseT_Full;
2490 else if (ecmd->duplex == DUPLEX_HALF)
2491 setting = SUPPORTED_1000baseT_Half;
2492 else
2493 return -EINVAL;
2494 break;
2495 case SPEED_100:
2496 if (ecmd->duplex == DUPLEX_FULL)
2497 setting = SUPPORTED_100baseT_Full;
2498 else if (ecmd->duplex == DUPLEX_HALF)
2499 setting = SUPPORTED_100baseT_Half;
2500 else
2501 return -EINVAL;
2502 break;
2503
2504 case SPEED_10:
2505 if (ecmd->duplex == DUPLEX_FULL)
2506 setting = SUPPORTED_10baseT_Full;
2507 else if (ecmd->duplex == DUPLEX_HALF)
2508 setting = SUPPORTED_10baseT_Half;
2509 else
2510 return -EINVAL;
2511 break;
2512 default:
2513 return -EINVAL;
2514 }
2515
2516 if ((setting & supported) == 0)
2517 return -EINVAL;
2518
2519 sky2->speed = ecmd->speed;
2520 sky2->duplex = ecmd->duplex;
2521 }
2522
2523 sky2->autoneg = ecmd->autoneg;
2524 sky2->advertising = ecmd->advertising;
2525
2526 if (netif_running(dev))
2527 sky2_phy_reinit(sky2);
2528
2529 return 0;
2530 }
2531
2532 static void sky2_get_drvinfo(struct net_device *dev,
2533 struct ethtool_drvinfo *info)
2534 {
2535 struct sky2_port *sky2 = netdev_priv(dev);
2536
2537 strcpy(info->driver, DRV_NAME);
2538 strcpy(info->version, DRV_VERSION);
2539 strcpy(info->fw_version, "N/A");
2540 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2541 }
2542
2543 static const struct sky2_stat {
2544 char name[ETH_GSTRING_LEN];
2545 u16 offset;
2546 } sky2_stats[] = {
2547 { "tx_bytes", GM_TXO_OK_HI },
2548 { "rx_bytes", GM_RXO_OK_HI },
2549 { "tx_broadcast", GM_TXF_BC_OK },
2550 { "rx_broadcast", GM_RXF_BC_OK },
2551 { "tx_multicast", GM_TXF_MC_OK },
2552 { "rx_multicast", GM_RXF_MC_OK },
2553 { "tx_unicast", GM_TXF_UC_OK },
2554 { "rx_unicast", GM_RXF_UC_OK },
2555 { "tx_mac_pause", GM_TXF_MPAUSE },
2556 { "rx_mac_pause", GM_RXF_MPAUSE },
2557 { "collisions", GM_TXF_COL },
2558 { "late_collision",GM_TXF_LAT_COL },
2559 { "aborted", GM_TXF_ABO_COL },
2560 { "single_collisions", GM_TXF_SNG_COL },
2561 { "multi_collisions", GM_TXF_MUL_COL },
2562
2563 { "rx_short", GM_RXF_SHT },
2564 { "rx_runt", GM_RXE_FRAG },
2565 { "rx_64_byte_packets", GM_RXF_64B },
2566 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2567 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2568 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2569 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2570 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2571 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
2572 { "rx_too_long", GM_RXF_LNG_ERR },
2573 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2574 { "rx_jabber", GM_RXF_JAB_PKT },
2575 { "rx_fcs_error", GM_RXF_FCS_ERR },
2576
2577 { "tx_64_byte_packets", GM_TXF_64B },
2578 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2579 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2580 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2581 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2582 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2583 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2584 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
2585 };
2586
2587 static u32 sky2_get_rx_csum(struct net_device *dev)
2588 {
2589 struct sky2_port *sky2 = netdev_priv(dev);
2590
2591 return sky2->rx_csum;
2592 }
2593
2594 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2595 {
2596 struct sky2_port *sky2 = netdev_priv(dev);
2597
2598 sky2->rx_csum = data;
2599
2600 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2601 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2602
2603 return 0;
2604 }
2605
2606 static u32 sky2_get_msglevel(struct net_device *netdev)
2607 {
2608 struct sky2_port *sky2 = netdev_priv(netdev);
2609 return sky2->msg_enable;
2610 }
2611
2612 static int sky2_nway_reset(struct net_device *dev)
2613 {
2614 struct sky2_port *sky2 = netdev_priv(dev);
2615
2616 if (sky2->autoneg != AUTONEG_ENABLE)
2617 return -EINVAL;
2618
2619 sky2_phy_reinit(sky2);
2620
2621 return 0;
2622 }
2623
2624 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2625 {
2626 struct sky2_hw *hw = sky2->hw;
2627 unsigned port = sky2->port;
2628 int i;
2629
2630 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2631 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2632 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2633 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2634
2635 for (i = 2; i < count; i++)
2636 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2637 }
2638
2639 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2640 {
2641 struct sky2_port *sky2 = netdev_priv(netdev);
2642 sky2->msg_enable = value;
2643 }
2644
2645 static int sky2_get_stats_count(struct net_device *dev)
2646 {
2647 return ARRAY_SIZE(sky2_stats);
2648 }
2649
2650 static void sky2_get_ethtool_stats(struct net_device *dev,
2651 struct ethtool_stats *stats, u64 * data)
2652 {
2653 struct sky2_port *sky2 = netdev_priv(dev);
2654
2655 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2656 }
2657
2658 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2659 {
2660 int i;
2661
2662 switch (stringset) {
2663 case ETH_SS_STATS:
2664 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2665 memcpy(data + i * ETH_GSTRING_LEN,
2666 sky2_stats[i].name, ETH_GSTRING_LEN);
2667 break;
2668 }
2669 }
2670
2671 /* Use hardware MIB variables for critical path statistics and
2672 * transmit feedback not reported at interrupt.
2673 * Other errors are accounted for in interrupt handler.
2674 */
2675 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2676 {
2677 struct sky2_port *sky2 = netdev_priv(dev);
2678 u64 data[13];
2679
2680 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
2681
2682 sky2->net_stats.tx_bytes = data[0];
2683 sky2->net_stats.rx_bytes = data[1];
2684 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2685 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2686 sky2->net_stats.multicast = data[3] + data[5];
2687 sky2->net_stats.collisions = data[10];
2688 sky2->net_stats.tx_aborted_errors = data[12];
2689
2690 return &sky2->net_stats;
2691 }
2692
2693 static int sky2_set_mac_address(struct net_device *dev, void *p)
2694 {
2695 struct sky2_port *sky2 = netdev_priv(dev);
2696 struct sky2_hw *hw = sky2->hw;
2697 unsigned port = sky2->port;
2698 const struct sockaddr *addr = p;
2699
2700 if (!is_valid_ether_addr(addr->sa_data))
2701 return -EADDRNOTAVAIL;
2702
2703 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2704 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
2705 dev->dev_addr, ETH_ALEN);
2706 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
2707 dev->dev_addr, ETH_ALEN);
2708
2709 /* virtual address for data */
2710 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2711
2712 /* physical address: used for pause frames */
2713 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2714
2715 return 0;
2716 }
2717
2718 static void sky2_set_multicast(struct net_device *dev)
2719 {
2720 struct sky2_port *sky2 = netdev_priv(dev);
2721 struct sky2_hw *hw = sky2->hw;
2722 unsigned port = sky2->port;
2723 struct dev_mc_list *list = dev->mc_list;
2724 u16 reg;
2725 u8 filter[8];
2726
2727 memset(filter, 0, sizeof(filter));
2728
2729 reg = gma_read16(hw, port, GM_RX_CTRL);
2730 reg |= GM_RXCR_UCF_ENA;
2731
2732 if (dev->flags & IFF_PROMISC) /* promiscuous */
2733 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2734 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
2735 memset(filter, 0xff, sizeof(filter));
2736 else if (dev->mc_count == 0) /* no multicast */
2737 reg &= ~GM_RXCR_MCF_ENA;
2738 else {
2739 int i;
2740 reg |= GM_RXCR_MCF_ENA;
2741
2742 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2743 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2744 filter[bit / 8] |= 1 << (bit % 8);
2745 }
2746 }
2747
2748 gma_write16(hw, port, GM_MC_ADDR_H1,
2749 (u16) filter[0] | ((u16) filter[1] << 8));
2750 gma_write16(hw, port, GM_MC_ADDR_H2,
2751 (u16) filter[2] | ((u16) filter[3] << 8));
2752 gma_write16(hw, port, GM_MC_ADDR_H3,
2753 (u16) filter[4] | ((u16) filter[5] << 8));
2754 gma_write16(hw, port, GM_MC_ADDR_H4,
2755 (u16) filter[6] | ((u16) filter[7] << 8));
2756
2757 gma_write16(hw, port, GM_RX_CTRL, reg);
2758 }
2759
2760 /* Can have one global because blinking is controlled by
2761 * ethtool and that is always under RTNL mutex
2762 */
2763 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2764 {
2765 u16 pg;
2766
2767 switch (hw->chip_id) {
2768 case CHIP_ID_YUKON_XL:
2769 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2770 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2771 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2772 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2773 PHY_M_LEDC_INIT_CTRL(7) |
2774 PHY_M_LEDC_STA1_CTRL(7) |
2775 PHY_M_LEDC_STA0_CTRL(7))
2776 : 0);
2777
2778 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2779 break;
2780
2781 default:
2782 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2783 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2784 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2785 PHY_M_LED_MO_10(MO_LED_ON) |
2786 PHY_M_LED_MO_100(MO_LED_ON) |
2787 PHY_M_LED_MO_1000(MO_LED_ON) |
2788 PHY_M_LED_MO_RX(MO_LED_ON)
2789 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2790 PHY_M_LED_MO_10(MO_LED_OFF) |
2791 PHY_M_LED_MO_100(MO_LED_OFF) |
2792 PHY_M_LED_MO_1000(MO_LED_OFF) |
2793 PHY_M_LED_MO_RX(MO_LED_OFF));
2794
2795 }
2796 }
2797
2798 /* blink LED's for finding board */
2799 static int sky2_phys_id(struct net_device *dev, u32 data)
2800 {
2801 struct sky2_port *sky2 = netdev_priv(dev);
2802 struct sky2_hw *hw = sky2->hw;
2803 unsigned port = sky2->port;
2804 u16 ledctrl, ledover = 0;
2805 long ms;
2806 int interrupted;
2807 int onoff = 1;
2808
2809 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
2810 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2811 else
2812 ms = data * 1000;
2813
2814 /* save initial values */
2815 spin_lock_bh(&sky2->phy_lock);
2816 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2817 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2818 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2819 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2820 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2821 } else {
2822 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2823 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2824 }
2825
2826 interrupted = 0;
2827 while (!interrupted && ms > 0) {
2828 sky2_led(hw, port, onoff);
2829 onoff = !onoff;
2830
2831 spin_unlock_bh(&sky2->phy_lock);
2832 interrupted = msleep_interruptible(250);
2833 spin_lock_bh(&sky2->phy_lock);
2834
2835 ms -= 250;
2836 }
2837
2838 /* resume regularly scheduled programming */
2839 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2840 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2841 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2842 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2843 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2844 } else {
2845 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2846 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2847 }
2848 spin_unlock_bh(&sky2->phy_lock);
2849
2850 return 0;
2851 }
2852
2853 static void sky2_get_pauseparam(struct net_device *dev,
2854 struct ethtool_pauseparam *ecmd)
2855 {
2856 struct sky2_port *sky2 = netdev_priv(dev);
2857
2858 ecmd->tx_pause = sky2->tx_pause;
2859 ecmd->rx_pause = sky2->rx_pause;
2860 ecmd->autoneg = sky2->autoneg;
2861 }
2862
2863 static int sky2_set_pauseparam(struct net_device *dev,
2864 struct ethtool_pauseparam *ecmd)
2865 {
2866 struct sky2_port *sky2 = netdev_priv(dev);
2867 int err = 0;
2868
2869 sky2->autoneg = ecmd->autoneg;
2870 sky2->tx_pause = ecmd->tx_pause != 0;
2871 sky2->rx_pause = ecmd->rx_pause != 0;
2872
2873 sky2_phy_reinit(sky2);
2874
2875 return err;
2876 }
2877
2878 static int sky2_get_coalesce(struct net_device *dev,
2879 struct ethtool_coalesce *ecmd)
2880 {
2881 struct sky2_port *sky2 = netdev_priv(dev);
2882 struct sky2_hw *hw = sky2->hw;
2883
2884 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2885 ecmd->tx_coalesce_usecs = 0;
2886 else {
2887 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2888 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2889 }
2890 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2891
2892 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2893 ecmd->rx_coalesce_usecs = 0;
2894 else {
2895 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2896 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2897 }
2898 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2899
2900 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2901 ecmd->rx_coalesce_usecs_irq = 0;
2902 else {
2903 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2904 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2905 }
2906
2907 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2908
2909 return 0;
2910 }
2911
2912 /* Note: this affect both ports */
2913 static int sky2_set_coalesce(struct net_device *dev,
2914 struct ethtool_coalesce *ecmd)
2915 {
2916 struct sky2_port *sky2 = netdev_priv(dev);
2917 struct sky2_hw *hw = sky2->hw;
2918 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
2919
2920 if (ecmd->tx_coalesce_usecs > tmax ||
2921 ecmd->rx_coalesce_usecs > tmax ||
2922 ecmd->rx_coalesce_usecs_irq > tmax)
2923 return -EINVAL;
2924
2925 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
2926 return -EINVAL;
2927 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
2928 return -EINVAL;
2929 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
2930 return -EINVAL;
2931
2932 if (ecmd->tx_coalesce_usecs == 0)
2933 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2934 else {
2935 sky2_write32(hw, STAT_TX_TIMER_INI,
2936 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2937 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2938 }
2939 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2940
2941 if (ecmd->rx_coalesce_usecs == 0)
2942 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2943 else {
2944 sky2_write32(hw, STAT_LEV_TIMER_INI,
2945 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2946 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2947 }
2948 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2949
2950 if (ecmd->rx_coalesce_usecs_irq == 0)
2951 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2952 else {
2953 sky2_write32(hw, STAT_ISR_TIMER_INI,
2954 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2955 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2956 }
2957 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2958 return 0;
2959 }
2960
2961 static void sky2_get_ringparam(struct net_device *dev,
2962 struct ethtool_ringparam *ering)
2963 {
2964 struct sky2_port *sky2 = netdev_priv(dev);
2965
2966 ering->rx_max_pending = RX_MAX_PENDING;
2967 ering->rx_mini_max_pending = 0;
2968 ering->rx_jumbo_max_pending = 0;
2969 ering->tx_max_pending = TX_RING_SIZE - 1;
2970
2971 ering->rx_pending = sky2->rx_pending;
2972 ering->rx_mini_pending = 0;
2973 ering->rx_jumbo_pending = 0;
2974 ering->tx_pending = sky2->tx_pending;
2975 }
2976
2977 static int sky2_set_ringparam(struct net_device *dev,
2978 struct ethtool_ringparam *ering)
2979 {
2980 struct sky2_port *sky2 = netdev_priv(dev);
2981 int err = 0;
2982
2983 if (ering->rx_pending > RX_MAX_PENDING ||
2984 ering->rx_pending < 8 ||
2985 ering->tx_pending < MAX_SKB_TX_LE ||
2986 ering->tx_pending > TX_RING_SIZE - 1)
2987 return -EINVAL;
2988
2989 if (netif_running(dev))
2990 sky2_down(dev);
2991
2992 sky2->rx_pending = ering->rx_pending;
2993 sky2->tx_pending = ering->tx_pending;
2994
2995 if (netif_running(dev)) {
2996 err = sky2_up(dev);
2997 if (err)
2998 dev_close(dev);
2999 else
3000 sky2_set_multicast(dev);
3001 }
3002
3003 return err;
3004 }
3005
3006 static int sky2_get_regs_len(struct net_device *dev)
3007 {
3008 return 0x4000;
3009 }
3010
3011 /*
3012 * Returns copy of control register region
3013 * Note: access to the RAM address register set will cause timeouts.
3014 */
3015 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3016 void *p)
3017 {
3018 const struct sky2_port *sky2 = netdev_priv(dev);
3019 const void __iomem *io = sky2->hw->regs;
3020
3021 BUG_ON(regs->len < B3_RI_WTO_R1);
3022 regs->version = 1;
3023 memset(p, 0, regs->len);
3024
3025 memcpy_fromio(p, io, B3_RAM_ADDR);
3026
3027 memcpy_fromio(p + B3_RI_WTO_R1,
3028 io + B3_RI_WTO_R1,
3029 regs->len - B3_RI_WTO_R1);
3030 }
3031
3032 static struct ethtool_ops sky2_ethtool_ops = {
3033 .get_settings = sky2_get_settings,
3034 .set_settings = sky2_set_settings,
3035 .get_drvinfo = sky2_get_drvinfo,
3036 .get_msglevel = sky2_get_msglevel,
3037 .set_msglevel = sky2_set_msglevel,
3038 .nway_reset = sky2_nway_reset,
3039 .get_regs_len = sky2_get_regs_len,
3040 .get_regs = sky2_get_regs,
3041 .get_link = ethtool_op_get_link,
3042 .get_sg = ethtool_op_get_sg,
3043 .set_sg = ethtool_op_set_sg,
3044 .get_tx_csum = ethtool_op_get_tx_csum,
3045 .set_tx_csum = ethtool_op_set_tx_csum,
3046 .get_tso = ethtool_op_get_tso,
3047 .set_tso = ethtool_op_set_tso,
3048 .get_rx_csum = sky2_get_rx_csum,
3049 .set_rx_csum = sky2_set_rx_csum,
3050 .get_strings = sky2_get_strings,
3051 .get_coalesce = sky2_get_coalesce,
3052 .set_coalesce = sky2_set_coalesce,
3053 .get_ringparam = sky2_get_ringparam,
3054 .set_ringparam = sky2_set_ringparam,
3055 .get_pauseparam = sky2_get_pauseparam,
3056 .set_pauseparam = sky2_set_pauseparam,
3057 .phys_id = sky2_phys_id,
3058 .get_stats_count = sky2_get_stats_count,
3059 .get_ethtool_stats = sky2_get_ethtool_stats,
3060 .get_perm_addr = ethtool_op_get_perm_addr,
3061 };
3062
3063 /* Initialize network device */
3064 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3065 unsigned port, int highmem)
3066 {
3067 struct sky2_port *sky2;
3068 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3069
3070 if (!dev) {
3071 printk(KERN_ERR "sky2 etherdev alloc failed");
3072 return NULL;
3073 }
3074
3075 SET_MODULE_OWNER(dev);
3076 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3077 dev->irq = hw->pdev->irq;
3078 dev->open = sky2_up;
3079 dev->stop = sky2_down;
3080 dev->do_ioctl = sky2_ioctl;
3081 dev->hard_start_xmit = sky2_xmit_frame;
3082 dev->get_stats = sky2_get_stats;
3083 dev->set_multicast_list = sky2_set_multicast;
3084 dev->set_mac_address = sky2_set_mac_address;
3085 dev->change_mtu = sky2_change_mtu;
3086 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3087 dev->tx_timeout = sky2_tx_timeout;
3088 dev->watchdog_timeo = TX_WATCHDOG;
3089 if (port == 0)
3090 dev->poll = sky2_poll;
3091 dev->weight = NAPI_WEIGHT;
3092 #ifdef CONFIG_NET_POLL_CONTROLLER
3093 dev->poll_controller = sky2_netpoll;
3094 #endif
3095
3096 sky2 = netdev_priv(dev);
3097 sky2->netdev = dev;
3098 sky2->hw = hw;
3099 sky2->msg_enable = netif_msg_init(debug, default_msg);
3100
3101 spin_lock_init(&sky2->tx_lock);
3102 /* Auto speed and flow control */
3103 sky2->autoneg = AUTONEG_ENABLE;
3104 sky2->tx_pause = 1;
3105 sky2->rx_pause = 1;
3106 sky2->duplex = -1;
3107 sky2->speed = -1;
3108 sky2->advertising = sky2_supported_modes(hw);
3109 sky2->rx_csum = 1;
3110
3111 spin_lock_init(&sky2->phy_lock);
3112 sky2->tx_pending = TX_DEF_PENDING;
3113 sky2->rx_pending = RX_DEF_PENDING;
3114 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
3115
3116 hw->dev[port] = dev;
3117
3118 sky2->port = port;
3119
3120 dev->features |= NETIF_F_LLTX;
3121 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3122 dev->features |= NETIF_F_TSO;
3123 if (highmem)
3124 dev->features |= NETIF_F_HIGHDMA;
3125 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3126
3127 #ifdef SKY2_VLAN_TAG_USED
3128 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3129 dev->vlan_rx_register = sky2_vlan_rx_register;
3130 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3131 #endif
3132
3133 /* read the mac address */
3134 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3135 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3136
3137 /* device is off until link detection */
3138 netif_carrier_off(dev);
3139 netif_stop_queue(dev);
3140
3141 return dev;
3142 }
3143
3144 static void __devinit sky2_show_addr(struct net_device *dev)
3145 {
3146 const struct sky2_port *sky2 = netdev_priv(dev);
3147
3148 if (netif_msg_probe(sky2))
3149 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3150 dev->name,
3151 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3152 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3153 }
3154
3155 /* Handle software interrupt used during MSI test */
3156 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id,
3157 struct pt_regs *regs)
3158 {
3159 struct sky2_hw *hw = dev_id;
3160 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3161
3162 if (status == 0)
3163 return IRQ_NONE;
3164
3165 if (status & Y2_IS_IRQ_SW) {
3166 hw->msi_detected = 1;
3167 wake_up(&hw->msi_wait);
3168 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3169 }
3170 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3171
3172 return IRQ_HANDLED;
3173 }
3174
3175 /* Test interrupt path by forcing a a software IRQ */
3176 static int __devinit sky2_test_msi(struct sky2_hw *hw)
3177 {
3178 struct pci_dev *pdev = hw->pdev;
3179 int err;
3180
3181 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3182
3183 err = request_irq(pdev->irq, sky2_test_intr, SA_SHIRQ, DRV_NAME, hw);
3184 if (err) {
3185 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3186 pci_name(pdev), pdev->irq);
3187 return err;
3188 }
3189
3190 init_waitqueue_head (&hw->msi_wait);
3191
3192 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3193 wmb();
3194
3195 wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10);
3196
3197 if (!hw->msi_detected) {
3198 /* MSI test failed, go back to INTx mode */
3199 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
3200 "switching to INTx mode. Please report this failure to "
3201 "the PCI maintainer and include system chipset information.\n",
3202 pci_name(pdev));
3203
3204 err = -EOPNOTSUPP;
3205 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3206 }
3207
3208 sky2_write32(hw, B0_IMSK, 0);
3209
3210 free_irq(pdev->irq, hw);
3211
3212 return err;
3213 }
3214
3215 static int __devinit sky2_probe(struct pci_dev *pdev,
3216 const struct pci_device_id *ent)
3217 {
3218 struct net_device *dev, *dev1 = NULL;
3219 struct sky2_hw *hw;
3220 int err, pm_cap, using_dac = 0;
3221
3222 err = pci_enable_device(pdev);
3223 if (err) {
3224 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3225 pci_name(pdev));
3226 goto err_out;
3227 }
3228
3229 err = pci_request_regions(pdev, DRV_NAME);
3230 if (err) {
3231 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3232 pci_name(pdev));
3233 goto err_out;
3234 }
3235
3236 pci_set_master(pdev);
3237
3238 /* Find power-management capability. */
3239 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3240 if (pm_cap == 0) {
3241 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3242 "aborting.\n");
3243 err = -EIO;
3244 goto err_out_free_regions;
3245 }
3246
3247 if (sizeof(dma_addr_t) > sizeof(u32) &&
3248 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3249 using_dac = 1;
3250 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3251 if (err < 0) {
3252 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3253 "for consistent allocations\n", pci_name(pdev));
3254 goto err_out_free_regions;
3255 }
3256
3257 } else {
3258 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3259 if (err) {
3260 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3261 pci_name(pdev));
3262 goto err_out_free_regions;
3263 }
3264 }
3265
3266 err = -ENOMEM;
3267 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3268 if (!hw) {
3269 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3270 pci_name(pdev));
3271 goto err_out_free_regions;
3272 }
3273
3274 hw->pdev = pdev;
3275
3276 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3277 if (!hw->regs) {
3278 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3279 pci_name(pdev));
3280 goto err_out_free_hw;
3281 }
3282 hw->pm_cap = pm_cap;
3283
3284 #ifdef __BIG_ENDIAN
3285 /* byte swap descriptors in hardware */
3286 {
3287 u32 reg;
3288
3289 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3290 reg |= PCI_REV_DESC;
3291 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3292 }
3293 #endif
3294
3295 /* ring for status responses */
3296 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3297 &hw->st_dma);
3298 if (!hw->st_le)
3299 goto err_out_iounmap;
3300
3301 err = sky2_reset(hw);
3302 if (err)
3303 goto err_out_iounmap;
3304
3305 printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3306 DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
3307 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3308 hw->chip_id, hw->chip_rev);
3309
3310 dev = sky2_init_netdev(hw, 0, using_dac);
3311 if (!dev)
3312 goto err_out_free_pci;
3313
3314 err = register_netdev(dev);
3315 if (err) {
3316 printk(KERN_ERR PFX "%s: cannot register net device\n",
3317 pci_name(pdev));
3318 goto err_out_free_netdev;
3319 }
3320
3321 sky2_show_addr(dev);
3322
3323 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3324 if (register_netdev(dev1) == 0)
3325 sky2_show_addr(dev1);
3326 else {
3327 /* Failure to register second port need not be fatal */
3328 printk(KERN_WARNING PFX
3329 "register of second port failed\n");
3330 hw->dev[1] = NULL;
3331 free_netdev(dev1);
3332 }
3333 }
3334
3335 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3336 err = sky2_test_msi(hw);
3337 if (err == -EOPNOTSUPP)
3338 pci_disable_msi(pdev);
3339 else if (err)
3340 goto err_out_unregister;
3341 }
3342
3343 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
3344 if (err) {
3345 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3346 pci_name(pdev), pdev->irq);
3347 goto err_out_unregister;
3348 }
3349
3350 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3351
3352 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
3353 if (idle_timeout > 0)
3354 mod_timer(&hw->idle_timer,
3355 jiffies + msecs_to_jiffies(idle_timeout));
3356
3357 pci_set_drvdata(pdev, hw);
3358
3359 return 0;
3360
3361 err_out_unregister:
3362 pci_disable_msi(pdev);
3363 if (dev1) {
3364 unregister_netdev(dev1);
3365 free_netdev(dev1);
3366 }
3367 unregister_netdev(dev);
3368 err_out_free_netdev:
3369 free_netdev(dev);
3370 err_out_free_pci:
3371 sky2_write8(hw, B0_CTST, CS_RST_SET);
3372 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3373 err_out_iounmap:
3374 iounmap(hw->regs);
3375 err_out_free_hw:
3376 kfree(hw);
3377 err_out_free_regions:
3378 pci_release_regions(pdev);
3379 pci_disable_device(pdev);
3380 err_out:
3381 return err;
3382 }
3383
3384 static void __devexit sky2_remove(struct pci_dev *pdev)
3385 {
3386 struct sky2_hw *hw = pci_get_drvdata(pdev);
3387 struct net_device *dev0, *dev1;
3388
3389 if (!hw)
3390 return;
3391
3392 del_timer_sync(&hw->idle_timer);
3393
3394 sky2_write32(hw, B0_IMSK, 0);
3395 synchronize_irq(hw->pdev->irq);
3396
3397 dev0 = hw->dev[0];
3398 dev1 = hw->dev[1];
3399 if (dev1)
3400 unregister_netdev(dev1);
3401 unregister_netdev(dev0);
3402
3403 sky2_set_power_state(hw, PCI_D3hot);
3404 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
3405 sky2_write8(hw, B0_CTST, CS_RST_SET);
3406 sky2_read8(hw, B0_CTST);
3407
3408 free_irq(pdev->irq, hw);
3409 pci_disable_msi(pdev);
3410 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3411 pci_release_regions(pdev);
3412 pci_disable_device(pdev);
3413
3414 if (dev1)
3415 free_netdev(dev1);
3416 free_netdev(dev0);
3417 iounmap(hw->regs);
3418 kfree(hw);
3419
3420 pci_set_drvdata(pdev, NULL);
3421 }
3422
3423 #ifdef CONFIG_PM
3424 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3425 {
3426 struct sky2_hw *hw = pci_get_drvdata(pdev);
3427 int i;
3428
3429 for (i = 0; i < 2; i++) {
3430 struct net_device *dev = hw->dev[i];
3431
3432 if (dev) {
3433 if (!netif_running(dev))
3434 continue;
3435
3436 sky2_down(dev);
3437 netif_device_detach(dev);
3438 }
3439 }
3440
3441 return sky2_set_power_state(hw, pci_choose_state(pdev, state));
3442 }
3443
3444 static int sky2_resume(struct pci_dev *pdev)
3445 {
3446 struct sky2_hw *hw = pci_get_drvdata(pdev);
3447 int i, err;
3448
3449 pci_restore_state(pdev);
3450 pci_enable_wake(pdev, PCI_D0, 0);
3451 err = sky2_set_power_state(hw, PCI_D0);
3452 if (err)
3453 goto out;
3454
3455 err = sky2_reset(hw);
3456 if (err)
3457 goto out;
3458
3459 for (i = 0; i < 2; i++) {
3460 struct net_device *dev = hw->dev[i];
3461 if (dev && netif_running(dev)) {
3462 netif_device_attach(dev);
3463 err = sky2_up(dev);
3464 if (err) {
3465 printk(KERN_ERR PFX "%s: could not up: %d\n",
3466 dev->name, err);
3467 dev_close(dev);
3468 break;
3469 }
3470 }
3471 }
3472 out:
3473 return err;
3474 }
3475 #endif
3476
3477 static struct pci_driver sky2_driver = {
3478 .name = DRV_NAME,
3479 .id_table = sky2_id_table,
3480 .probe = sky2_probe,
3481 .remove = __devexit_p(sky2_remove),
3482 #ifdef CONFIG_PM
3483 .suspend = sky2_suspend,
3484 .resume = sky2_resume,
3485 #endif
3486 };
3487
3488 static int __init sky2_init_module(void)
3489 {
3490 return pci_register_driver(&sky2_driver);
3491 }
3492
3493 static void __exit sky2_cleanup_module(void)
3494 {
3495 pci_unregister_driver(&sky2_driver);
3496 }
3497
3498 module_init(sky2_init_module);
3499 module_exit(sky2_cleanup_module);
3500
3501 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3502 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3503 MODULE_LICENSE("GPL");
3504 MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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