2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/config.h>
27 #include <linux/crc32.h>
28 #include <linux/kernel.h>
29 #include <linux/version.h>
30 #include <linux/module.h>
31 #include <linux/netdevice.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/etherdevice.h>
34 #include <linux/ethtool.h>
35 #include <linux/pci.h>
37 #include <linux/tcp.h>
39 #include <linux/delay.h>
40 #include <linux/workqueue.h>
41 #include <linux/if_vlan.h>
42 #include <linux/prefetch.h>
43 #include <linux/mii.h>
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "0.15"
55 #define PFX DRV_NAME " "
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
60 * similar to Tigon3. A transmit can require several elements;
61 * a receive requires one (or two if using 64 bit dma).
64 #define is_ec_a1(hw) \
65 unlikely((hw)->chip_id == CHIP_ID_YUKON_EC && \
66 (hw)->chip_rev == CHIP_REV_YU_EC_A1)
68 #define RX_LE_SIZE 512
69 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
70 #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
71 #define RX_DEF_PENDING RX_MAX_PENDING
72 #define RX_SKB_ALIGN 8
74 #define TX_RING_SIZE 512
75 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
76 #define TX_MIN_PENDING 64
77 #define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS)
79 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
80 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
81 #define ETH_JUMBO_MTU 9000
82 #define TX_WATCHDOG (5 * HZ)
83 #define NAPI_WEIGHT 64
84 #define PHY_RETRIES 1000
86 static const u32 default_msg
=
87 NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
88 | NETIF_MSG_TIMER
| NETIF_MSG_TX_ERR
| NETIF_MSG_RX_ERR
89 | NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
;
91 static int debug
= -1; /* defaults above */
92 module_param(debug
, int, 0);
93 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
95 static int copybreak __read_mostly
= 256;
96 module_param(copybreak
, int, 0);
97 MODULE_PARM_DESC(copybreak
, "Receive copy threshold");
99 static int disable_msi
= 0;
100 module_param(disable_msi
, int, 0);
101 MODULE_PARM_DESC(disable_msi
, "Disable Message Signaled Interrupt (MSI)");
103 static const struct pci_device_id sky2_id_table
[] = {
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9000) },
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9E00) },
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4b00) },
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4b01) },
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4340) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4341) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4342) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4343) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4344) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4345) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4346) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4347) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4350) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4351) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4352) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4360) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4361) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4362) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4363) },
126 MODULE_DEVICE_TABLE(pci
, sky2_id_table
);
128 /* Avoid conditionals by using array */
129 static const unsigned txqaddr
[] = { Q_XA1
, Q_XA2
};
130 static const unsigned rxqaddr
[] = { Q_R1
, Q_R2
};
132 /* This driver supports yukon2 chipset only */
133 static const char *yukon2_name
[] = {
135 "EC Ultra", /* 0xb4 */
136 "UNKNOWN", /* 0xb5 */
141 /* Access to external PHY */
142 static int gm_phy_write(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16 val
)
146 gma_write16(hw
, port
, GM_SMI_DATA
, val
);
147 gma_write16(hw
, port
, GM_SMI_CTRL
,
148 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
) | GM_SMI_CT_REG_AD(reg
));
150 for (i
= 0; i
< PHY_RETRIES
; i
++) {
151 if (!(gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_BUSY
))
156 printk(KERN_WARNING PFX
"%s: phy write timeout\n", hw
->dev
[port
]->name
);
160 static int __gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16
*val
)
164 gma_write16(hw
, port
, GM_SMI_CTRL
, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
)
165 | GM_SMI_CT_REG_AD(reg
) | GM_SMI_CT_OP_RD
);
167 for (i
= 0; i
< PHY_RETRIES
; i
++) {
168 if (gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_RD_VAL
) {
169 *val
= gma_read16(hw
, port
, GM_SMI_DATA
);
179 static u16
gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
)
183 if (__gm_phy_read(hw
, port
, reg
, &v
) != 0)
184 printk(KERN_WARNING PFX
"%s: phy read timeout\n", hw
->dev
[port
]->name
);
188 static int sky2_set_power_state(struct sky2_hw
*hw
, pci_power_t state
)
195 pr_debug("sky2_set_power_state %d\n", state
);
196 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
198 pci_read_config_word(hw
->pdev
, hw
->pm_cap
+ PCI_PM_PMC
, &power_control
);
199 vaux
= (sky2_read16(hw
, B0_CTST
) & Y2_VAUX_AVAIL
) &&
200 (power_control
& PCI_PM_CAP_PME_D3cold
);
202 pci_read_config_word(hw
->pdev
, hw
->pm_cap
+ PCI_PM_CTRL
, &power_control
);
204 power_control
|= PCI_PM_CTRL_PME_STATUS
;
205 power_control
&= ~(PCI_PM_CTRL_STATE_MASK
);
209 /* switch power to VCC (WA for VAUX problem) */
210 sky2_write8(hw
, B0_POWER_CTRL
,
211 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_OFF
| PC_VCC_ON
);
213 /* disable Core Clock Division, */
214 sky2_write32(hw
, B2_Y2_CLK_CTRL
, Y2_CLK_DIV_DIS
);
216 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
217 /* enable bits are inverted */
218 sky2_write8(hw
, B2_Y2_CLK_GATE
,
219 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
220 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
221 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
223 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
225 /* Turn off phy power saving */
226 pci_read_config_dword(hw
->pdev
, PCI_DEV_REG1
, ®1
);
227 reg1
&= ~(PCI_Y2_PHY1_POWD
| PCI_Y2_PHY2_POWD
);
229 /* looks like this XL is back asswards .. */
230 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1) {
231 reg1
|= PCI_Y2_PHY1_COMA
;
233 reg1
|= PCI_Y2_PHY2_COMA
;
235 pci_write_config_dword(hw
->pdev
, PCI_DEV_REG1
, reg1
);
240 /* Turn on phy power saving */
241 pci_read_config_dword(hw
->pdev
, PCI_DEV_REG1
, ®1
);
242 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
243 reg1
&= ~(PCI_Y2_PHY1_POWD
| PCI_Y2_PHY2_POWD
);
245 reg1
|= (PCI_Y2_PHY1_POWD
| PCI_Y2_PHY2_POWD
);
246 pci_write_config_dword(hw
->pdev
, PCI_DEV_REG1
, reg1
);
248 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
249 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
251 /* enable bits are inverted */
252 sky2_write8(hw
, B2_Y2_CLK_GATE
,
253 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
254 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
255 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
257 /* switch power to VAUX */
258 if (vaux
&& state
!= PCI_D3cold
)
259 sky2_write8(hw
, B0_POWER_CTRL
,
260 (PC_VAUX_ENA
| PC_VCC_ENA
|
261 PC_VAUX_ON
| PC_VCC_OFF
));
264 printk(KERN_ERR PFX
"Unknown power state %d\n", state
);
268 pci_write_config_byte(hw
->pdev
, hw
->pm_cap
+ PCI_PM_CTRL
, power_control
);
269 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
273 static void sky2_phy_reset(struct sky2_hw
*hw
, unsigned port
)
277 /* disable all GMAC IRQ's */
278 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
279 /* disable PHY IRQs */
280 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
282 gma_write16(hw
, port
, GM_MC_ADDR_H1
, 0); /* clear MC hash */
283 gma_write16(hw
, port
, GM_MC_ADDR_H2
, 0);
284 gma_write16(hw
, port
, GM_MC_ADDR_H3
, 0);
285 gma_write16(hw
, port
, GM_MC_ADDR_H4
, 0);
287 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
288 reg
|= GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
;
289 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
292 static void sky2_phy_init(struct sky2_hw
*hw
, unsigned port
)
294 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
295 u16 ctrl
, ct1000
, adv
, pg
, ledctrl
, ledover
;
297 if (sky2
->autoneg
== AUTONEG_ENABLE
&& hw
->chip_id
!= CHIP_ID_YUKON_XL
) {
298 u16 ectrl
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
300 ectrl
&= ~(PHY_M_EC_M_DSC_MSK
| PHY_M_EC_S_DSC_MSK
|
302 ectrl
|= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ
);
304 if (hw
->chip_id
== CHIP_ID_YUKON_EC
)
305 ectrl
|= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA
;
307 ectrl
|= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
309 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
, ectrl
);
312 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
314 if (hw
->chip_id
== CHIP_ID_YUKON_FE
) {
315 /* enable automatic crossover */
316 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
) >> 1;
318 /* disable energy detect */
319 ctrl
&= ~PHY_M_PC_EN_DET_MSK
;
321 /* enable automatic crossover */
322 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
);
324 if (sky2
->autoneg
== AUTONEG_ENABLE
&&
325 hw
->chip_id
== CHIP_ID_YUKON_XL
) {
326 ctrl
&= ~PHY_M_PC_DSC_MSK
;
327 ctrl
|= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA
;
330 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
332 /* workaround for deviation #4.88 (CRC errors) */
333 /* disable Automatic Crossover */
335 ctrl
&= ~PHY_M_PC_MDIX_MSK
;
336 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
338 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
339 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
340 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
341 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
342 ctrl
&= ~PHY_M_MAC_MD_MSK
;
343 ctrl
|= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX
);
344 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
346 /* select page 1 to access Fiber registers */
347 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 1);
351 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_CTRL
);
352 if (sky2
->autoneg
== AUTONEG_DISABLE
)
357 ctrl
|= PHY_CT_RESET
;
358 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
364 if (sky2
->autoneg
== AUTONEG_ENABLE
) {
366 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
367 ct1000
|= PHY_M_1000C_AFD
;
368 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
369 ct1000
|= PHY_M_1000C_AHD
;
370 if (sky2
->advertising
& ADVERTISED_100baseT_Full
)
371 adv
|= PHY_M_AN_100_FD
;
372 if (sky2
->advertising
& ADVERTISED_100baseT_Half
)
373 adv
|= PHY_M_AN_100_HD
;
374 if (sky2
->advertising
& ADVERTISED_10baseT_Full
)
375 adv
|= PHY_M_AN_10_FD
;
376 if (sky2
->advertising
& ADVERTISED_10baseT_Half
)
377 adv
|= PHY_M_AN_10_HD
;
378 } else /* special defines for FIBER (88E1011S only) */
379 adv
|= PHY_M_AN_1000X_AHD
| PHY_M_AN_1000X_AFD
;
381 /* Set Flow-control capabilities */
382 if (sky2
->tx_pause
&& sky2
->rx_pause
)
383 adv
|= PHY_AN_PAUSE_CAP
; /* symmetric */
384 else if (sky2
->rx_pause
&& !sky2
->tx_pause
)
385 adv
|= PHY_AN_PAUSE_ASYM
| PHY_AN_PAUSE_CAP
;
386 else if (!sky2
->rx_pause
&& sky2
->tx_pause
)
387 adv
|= PHY_AN_PAUSE_ASYM
; /* local */
389 /* Restart Auto-negotiation */
390 ctrl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
392 /* forced speed/duplex settings */
393 ct1000
= PHY_M_1000C_MSE
;
395 if (sky2
->duplex
== DUPLEX_FULL
)
396 ctrl
|= PHY_CT_DUP_MD
;
398 switch (sky2
->speed
) {
400 ctrl
|= PHY_CT_SP1000
;
403 ctrl
|= PHY_CT_SP100
;
407 ctrl
|= PHY_CT_RESET
;
410 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
411 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, ct1000
);
413 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, adv
);
414 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
416 /* Setup Phy LED's */
417 ledctrl
= PHY_M_LED_PULS_DUR(PULS_170MS
);
420 switch (hw
->chip_id
) {
421 case CHIP_ID_YUKON_FE
:
422 /* on 88E3082 these bits are at 11..9 (shifted left) */
423 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) << 1;
425 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_FE_LED_PAR
);
427 /* delete ACT LED control bits */
428 ctrl
&= ~PHY_M_FELP_LED1_MSK
;
429 /* change ACT LED control to blink mode */
430 ctrl
|= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL
);
431 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
434 case CHIP_ID_YUKON_XL
:
435 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
437 /* select page 3 to access LED control register */
438 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
440 /* set LED Function Control register */
441 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
442 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
443 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
444 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
446 /* set Polarity Control register */
447 gm_phy_write(hw
, port
, PHY_MARV_PHY_STAT
,
448 (PHY_M_POLC_LS1_P_MIX(4) |
449 PHY_M_POLC_IS0_P_MIX(4) |
450 PHY_M_POLC_LOS_CTRL(2) |
451 PHY_M_POLC_INIT_CTRL(2) |
452 PHY_M_POLC_STA1_CTRL(2) |
453 PHY_M_POLC_STA0_CTRL(2)));
455 /* restore page register */
456 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
460 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
461 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) | PHY_M_LEDC_TX_CTRL
;
462 /* turn off the Rx LED (LED_RX) */
463 ledover
|= PHY_M_LED_MO_RX(MO_LED_OFF
);
466 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
468 if (sky2
->autoneg
== AUTONEG_DISABLE
|| sky2
->speed
== SPEED_100
) {
469 /* turn on 100 Mbps LED (LED_LINK100) */
470 ledover
|= PHY_M_LED_MO_100(MO_LED_ON
);
474 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
476 /* Enable phy interrupt on auto-negotiation complete (or link up) */
477 if (sky2
->autoneg
== AUTONEG_ENABLE
)
478 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_AN_COMPL
);
480 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
483 /* Force a renegotiation */
484 static void sky2_phy_reinit(struct sky2_port
*sky2
)
486 down(&sky2
->phy_sema
);
487 sky2_phy_init(sky2
->hw
, sky2
->port
);
491 static void sky2_mac_init(struct sky2_hw
*hw
, unsigned port
)
493 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
496 const u8
*addr
= hw
->dev
[port
]->dev_addr
;
498 sky2_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
499 sky2_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
|GPC_ENA_PAUSE
);
501 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
503 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0 && port
== 1) {
504 /* WA DEV_472 -- looks like crossed wires on port 2 */
505 /* clear GMAC 1 Control reset */
506 sky2_write8(hw
, SK_REG(0, GMAC_CTRL
), GMC_RST_CLR
);
508 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_SET
);
509 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_CLR
);
510 } while (gm_phy_read(hw
, 1, PHY_MARV_ID0
) != PHY_MARV_ID0_VAL
||
511 gm_phy_read(hw
, 1, PHY_MARV_ID1
) != PHY_MARV_ID1_Y2
||
512 gm_phy_read(hw
, 1, PHY_MARV_INT_MASK
) != 0);
515 if (sky2
->autoneg
== AUTONEG_DISABLE
) {
516 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
517 reg
|= GM_GPCR_AU_ALL_DIS
;
518 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
519 gma_read16(hw
, port
, GM_GP_CTRL
);
521 switch (sky2
->speed
) {
523 reg
&= ~GM_GPCR_SPEED_100
;
524 reg
|= GM_GPCR_SPEED_1000
;
527 reg
&= ~GM_GPCR_SPEED_1000
;
528 reg
|= GM_GPCR_SPEED_100
;
531 reg
&= ~(GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
);
535 if (sky2
->duplex
== DUPLEX_FULL
)
536 reg
|= GM_GPCR_DUP_FULL
;
538 reg
= GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
| GM_GPCR_DUP_FULL
;
540 if (!sky2
->tx_pause
&& !sky2
->rx_pause
) {
541 sky2_write32(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
543 GM_GPCR_FC_TX_DIS
| GM_GPCR_FC_RX_DIS
| GM_GPCR_AU_FCT_DIS
;
544 } else if (sky2
->tx_pause
&& !sky2
->rx_pause
) {
545 /* disable Rx flow-control */
546 reg
|= GM_GPCR_FC_RX_DIS
| GM_GPCR_AU_FCT_DIS
;
549 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
551 sky2_read16(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
553 down(&sky2
->phy_sema
);
554 sky2_phy_init(hw
, port
);
558 reg
= gma_read16(hw
, port
, GM_PHY_ADDR
);
559 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
| GM_PAR_MIB_CLR
);
561 for (i
= 0; i
< GM_MIB_CNT_SIZE
; i
++)
562 gma_read16(hw
, port
, GM_MIB_CNT_BASE
+ 8 * i
);
563 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
);
565 /* transmit control */
566 gma_write16(hw
, port
, GM_TX_CTRL
, TX_COL_THR(TX_COL_DEF
));
568 /* receive control reg: unicast + multicast + no FCS */
569 gma_write16(hw
, port
, GM_RX_CTRL
,
570 GM_RXCR_UCF_ENA
| GM_RXCR_CRC_DIS
| GM_RXCR_MCF_ENA
);
572 /* transmit flow control */
573 gma_write16(hw
, port
, GM_TX_FLOW_CTRL
, 0xffff);
575 /* transmit parameter */
576 gma_write16(hw
, port
, GM_TX_PARAM
,
577 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF
) |
578 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF
) |
579 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF
) |
580 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF
));
582 /* serial mode register */
583 reg
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
584 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
586 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
)
587 reg
|= GM_SMOD_JUMBO_ENA
;
589 gma_write16(hw
, port
, GM_SERIAL_MODE
, reg
);
591 /* virtual address for data */
592 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, addr
);
594 /* physical address: used for pause frames */
595 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, addr
);
597 /* ignore counter overflows */
598 gma_write16(hw
, port
, GM_TX_IRQ_MSK
, 0);
599 gma_write16(hw
, port
, GM_RX_IRQ_MSK
, 0);
600 gma_write16(hw
, port
, GM_TR_IRQ_MSK
, 0);
602 /* Configure Rx MAC FIFO */
603 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_CLR
);
604 sky2_write16(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
607 /* Flush Rx MAC FIFO on any flow control or error */
608 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), GMR_FS_ANY_ERR
);
610 /* Set threshold to 0xa (64 bytes)
611 * ASF disabled so no need to do WA dev #4.30
613 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_THR
), RX_GMF_FL_THR_DEF
);
615 /* Configure Tx MAC FIFO */
616 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_CLR
);
617 sky2_write16(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_OPER_ON
);
619 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
620 sky2_write8(hw
, SK_REG(port
, RX_GMF_LP_THR
), 768/8);
621 sky2_write8(hw
, SK_REG(port
, RX_GMF_UP_THR
), 1024/8);
622 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
) {
623 /* set Tx GMAC FIFO Almost Empty Threshold */
624 sky2_write32(hw
, SK_REG(port
, TX_GMF_AE_THR
), 0x180);
625 /* Disable Store & Forward mode for TX */
626 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_STFW_DIS
);
632 /* Assign Ram Buffer allocation.
633 * start and end are in units of 4k bytes
634 * ram registers are in units of 64bit words
636 static void sky2_ramset(struct sky2_hw
*hw
, u16 q
, u8 startk
, u8 endk
)
640 start
= startk
* 4096/8;
641 end
= (endk
* 4096/8) - 1;
643 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_RST_CLR
);
644 sky2_write32(hw
, RB_ADDR(q
, RB_START
), start
);
645 sky2_write32(hw
, RB_ADDR(q
, RB_END
), end
);
646 sky2_write32(hw
, RB_ADDR(q
, RB_WP
), start
);
647 sky2_write32(hw
, RB_ADDR(q
, RB_RP
), start
);
649 if (q
== Q_R1
|| q
== Q_R2
) {
650 u32 space
= (endk
- startk
) * 4096/8;
651 u32 tp
= space
- space
/4;
653 /* On receive queue's set the thresholds
654 * give receiver priority when > 3/4 full
655 * send pause when down to 2K
657 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTHP
), tp
);
658 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTHP
), space
/2);
661 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTPP
), tp
);
662 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTPP
), space
/4);
664 /* Enable store & forward on Tx queue's because
665 * Tx FIFO is only 1K on Yukon
667 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_STFWD
);
670 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_OP_MD
);
671 sky2_read8(hw
, RB_ADDR(q
, RB_CTRL
));
674 /* Setup Bus Memory Interface */
675 static void sky2_qset(struct sky2_hw
*hw
, u16 q
)
677 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_RESET
);
678 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_OPER_INIT
);
679 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_FIFO_OP_ON
);
680 sky2_write32(hw
, Q_ADDR(q
, Q_WM
), BMU_WM_DEFAULT
);
683 /* Setup prefetch unit registers. This is the interface between
684 * hardware and driver list elements
686 static void sky2_prefetch_init(struct sky2_hw
*hw
, u32 qaddr
,
689 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
690 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_CLR
);
691 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_HI
), addr
>> 32);
692 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_LO
), (u32
) addr
);
693 sky2_write16(hw
, Y2_QADDR(qaddr
, PREF_UNIT_LAST_IDX
), last
);
694 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_OP_ON
);
696 sky2_read32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
));
699 static inline struct sky2_tx_le
*get_tx_le(struct sky2_port
*sky2
)
701 struct sky2_tx_le
*le
= sky2
->tx_le
+ sky2
->tx_prod
;
703 sky2
->tx_prod
= (sky2
->tx_prod
+ 1) % TX_RING_SIZE
;
708 * This is a workaround code taken from SysKonnect sk98lin driver
709 * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
711 static void sky2_put_idx(struct sky2_hw
*hw
, unsigned q
,
712 u16 idx
, u16
*last
, u16 size
)
715 if (is_ec_a1(hw
) && idx
< *last
) {
716 u16 hwget
= sky2_read16(hw
, Y2_QADDR(q
, PREF_UNIT_GET_IDX
));
719 /* Start prefetching again */
720 sky2_write8(hw
, Y2_QADDR(q
, PREF_UNIT_FIFO_WM
), 0xe0);
724 if (hwget
== size
- 1) {
725 /* set watermark to one list element */
726 sky2_write8(hw
, Y2_QADDR(q
, PREF_UNIT_FIFO_WM
), 8);
728 /* set put index to first list element */
729 sky2_write16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
), 0);
730 } else /* have hardware go to end of list */
731 sky2_write16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
),
735 sky2_write16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
), idx
);
742 static inline struct sky2_rx_le
*sky2_next_rx(struct sky2_port
*sky2
)
744 struct sky2_rx_le
*le
= sky2
->rx_le
+ sky2
->rx_put
;
745 sky2
->rx_put
= (sky2
->rx_put
+ 1) % RX_LE_SIZE
;
749 /* Return high part of DMA address (could be 32 or 64 bit) */
750 static inline u32
high32(dma_addr_t a
)
752 return sizeof(a
) > sizeof(u32
) ? (a
>> 16) >> 16 : 0;
755 /* Build description to hardware about buffer */
756 static void sky2_rx_add(struct sky2_port
*sky2
, dma_addr_t map
)
758 struct sky2_rx_le
*le
;
759 u32 hi
= high32(map
);
760 u16 len
= sky2
->rx_bufsize
;
762 if (sky2
->rx_addr64
!= hi
) {
763 le
= sky2_next_rx(sky2
);
764 le
->addr
= cpu_to_le32(hi
);
766 le
->opcode
= OP_ADDR64
| HW_OWNER
;
767 sky2
->rx_addr64
= high32(map
+ len
);
770 le
= sky2_next_rx(sky2
);
771 le
->addr
= cpu_to_le32((u32
) map
);
772 le
->length
= cpu_to_le16(len
);
774 le
->opcode
= OP_PACKET
| HW_OWNER
;
778 /* Tell chip where to start receive checksum.
779 * Actually has two checksums, but set both same to avoid possible byte
782 static void rx_set_checksum(struct sky2_port
*sky2
)
784 struct sky2_rx_le
*le
;
786 le
= sky2_next_rx(sky2
);
787 le
->addr
= (ETH_HLEN
<< 16) | ETH_HLEN
;
789 le
->opcode
= OP_TCPSTART
| HW_OWNER
;
791 sky2_write32(sky2
->hw
,
792 Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
793 sky2
->rx_csum
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
798 * The RX Stop command will not work for Yukon-2 if the BMU does not
799 * reach the end of packet and since we can't make sure that we have
800 * incoming data, we must reset the BMU while it is not doing a DMA
801 * transfer. Since it is possible that the RX path is still active,
802 * the RX RAM buffer will be stopped first, so any possible incoming
803 * data will not trigger a DMA. After the RAM buffer is stopped, the
804 * BMU is polled until any DMA in progress is ended and only then it
807 static void sky2_rx_stop(struct sky2_port
*sky2
)
809 struct sky2_hw
*hw
= sky2
->hw
;
810 unsigned rxq
= rxqaddr
[sky2
->port
];
813 /* disable the RAM Buffer receive queue */
814 sky2_write8(hw
, RB_ADDR(rxq
, RB_CTRL
), RB_DIS_OP_MD
);
816 for (i
= 0; i
< 0xffff; i
++)
817 if (sky2_read8(hw
, RB_ADDR(rxq
, Q_RSL
))
818 == sky2_read8(hw
, RB_ADDR(rxq
, Q_RL
)))
821 printk(KERN_WARNING PFX
"%s: receiver stop failed\n",
824 sky2_write32(hw
, Q_ADDR(rxq
, Q_CSR
), BMU_RST_SET
| BMU_FIFO_RST
);
826 /* reset the Rx prefetch unit */
827 sky2_write32(hw
, Y2_QADDR(rxq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
830 /* Clean out receive buffer area, assumes receiver hardware stopped */
831 static void sky2_rx_clean(struct sky2_port
*sky2
)
835 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
836 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
837 struct ring_info
*re
= sky2
->rx_ring
+ i
;
840 pci_unmap_single(sky2
->hw
->pdev
,
841 re
->mapaddr
, sky2
->rx_bufsize
,
849 /* Basic MII support */
850 static int sky2_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
852 struct mii_ioctl_data
*data
= if_mii(ifr
);
853 struct sky2_port
*sky2
= netdev_priv(dev
);
854 struct sky2_hw
*hw
= sky2
->hw
;
855 int err
= -EOPNOTSUPP
;
857 if (!netif_running(dev
))
858 return -ENODEV
; /* Phy still in reset */
862 data
->phy_id
= PHY_ADDR_MARV
;
868 down(&sky2
->phy_sema
);
869 err
= __gm_phy_read(hw
, sky2
->port
, data
->reg_num
& 0x1f, &val
);
877 if (!capable(CAP_NET_ADMIN
))
880 down(&sky2
->phy_sema
);
881 err
= gm_phy_write(hw
, sky2
->port
, data
->reg_num
& 0x1f,
889 #ifdef SKY2_VLAN_TAG_USED
890 static void sky2_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
892 struct sky2_port
*sky2
= netdev_priv(dev
);
893 struct sky2_hw
*hw
= sky2
->hw
;
894 u16 port
= sky2
->port
;
896 spin_lock_bh(&sky2
->tx_lock
);
898 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), RX_VLAN_STRIP_ON
);
899 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_VLAN_TAG_ON
);
902 spin_unlock_bh(&sky2
->tx_lock
);
905 static void sky2_vlan_rx_kill_vid(struct net_device
*dev
, unsigned short vid
)
907 struct sky2_port
*sky2
= netdev_priv(dev
);
908 struct sky2_hw
*hw
= sky2
->hw
;
909 u16 port
= sky2
->port
;
911 spin_lock_bh(&sky2
->tx_lock
);
913 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), RX_VLAN_STRIP_OFF
);
914 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_VLAN_TAG_OFF
);
916 sky2
->vlgrp
->vlan_devices
[vid
] = NULL
;
918 spin_unlock_bh(&sky2
->tx_lock
);
923 * It appears the hardware has a bug in the FIFO logic that
924 * cause it to hang if the FIFO gets overrun and the receive buffer
925 * is not aligned. ALso alloc_skb() won't align properly if slab
926 * debugging is enabled.
928 static inline struct sk_buff
*sky2_alloc_skb(unsigned int size
, gfp_t gfp_mask
)
932 skb
= alloc_skb(size
+ RX_SKB_ALIGN
, gfp_mask
);
934 unsigned long p
= (unsigned long) skb
->data
;
936 ((p
+ RX_SKB_ALIGN
- 1) & ~(RX_SKB_ALIGN
- 1)) - p
);
943 * Allocate and setup receiver buffer pool.
944 * In case of 64 bit dma, there are 2X as many list elements
945 * available as ring entries
946 * and need to reserve one list element so we don't wrap around.
948 static int sky2_rx_start(struct sky2_port
*sky2
)
950 struct sky2_hw
*hw
= sky2
->hw
;
951 unsigned rxq
= rxqaddr
[sky2
->port
];
954 sky2
->rx_put
= sky2
->rx_next
= 0;
956 sky2_prefetch_init(hw
, rxq
, sky2
->rx_le_map
, RX_LE_SIZE
- 1);
958 rx_set_checksum(sky2
);
959 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
960 struct ring_info
*re
= sky2
->rx_ring
+ i
;
962 re
->skb
= sky2_alloc_skb(sky2
->rx_bufsize
, GFP_KERNEL
);
966 re
->mapaddr
= pci_map_single(hw
->pdev
, re
->skb
->data
,
967 sky2
->rx_bufsize
, PCI_DMA_FROMDEVICE
);
968 sky2_rx_add(sky2
, re
->mapaddr
);
971 /* Tell chip about available buffers */
972 sky2_write16(hw
, Y2_QADDR(rxq
, PREF_UNIT_PUT_IDX
), sky2
->rx_put
);
973 sky2
->rx_last_put
= sky2_read16(hw
, Y2_QADDR(rxq
, PREF_UNIT_PUT_IDX
));
980 /* Bring up network interface. */
981 static int sky2_up(struct net_device
*dev
)
983 struct sky2_port
*sky2
= netdev_priv(dev
);
984 struct sky2_hw
*hw
= sky2
->hw
;
985 unsigned port
= sky2
->port
;
986 u32 ramsize
, rxspace
;
989 if (netif_msg_ifup(sky2
))
990 printk(KERN_INFO PFX
"%s: enabling interface\n", dev
->name
);
992 /* must be power of 2 */
993 sky2
->tx_le
= pci_alloc_consistent(hw
->pdev
,
995 sizeof(struct sky2_tx_le
),
1000 sky2
->tx_ring
= kcalloc(TX_RING_SIZE
, sizeof(struct tx_ring_info
),
1004 sky2
->tx_prod
= sky2
->tx_cons
= 0;
1006 sky2
->rx_le
= pci_alloc_consistent(hw
->pdev
, RX_LE_BYTES
,
1010 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1012 sky2
->rx_ring
= kcalloc(sky2
->rx_pending
, sizeof(struct ring_info
),
1017 sky2_mac_init(hw
, port
);
1019 /* Determine available ram buffer space (in 4K blocks).
1020 * Note: not sure about the FE setting below yet
1022 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
1025 ramsize
= sky2_read8(hw
, B2_E_0
);
1027 /* Give transmitter one third (rounded up) */
1028 rxspace
= ramsize
- (ramsize
+ 2) / 3;
1030 sky2_ramset(hw
, rxqaddr
[port
], 0, rxspace
);
1031 sky2_ramset(hw
, txqaddr
[port
], rxspace
, ramsize
);
1033 /* Make sure SyncQ is disabled */
1034 sky2_write8(hw
, RB_ADDR(port
== 0 ? Q_XS1
: Q_XS2
, RB_CTRL
),
1037 sky2_qset(hw
, txqaddr
[port
]);
1038 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
)
1039 sky2_write16(hw
, Q_ADDR(txqaddr
[port
], Q_AL
), 0x1a0);
1042 sky2_prefetch_init(hw
, txqaddr
[port
], sky2
->tx_le_map
,
1045 err
= sky2_rx_start(sky2
);
1049 /* Enable interrupts from phy/mac for port */
1050 hw
->intr_mask
|= (port
== 0) ? Y2_IS_PORT_1
: Y2_IS_PORT_2
;
1051 sky2_write32(hw
, B0_IMSK
, hw
->intr_mask
);
1056 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1057 sky2
->rx_le
, sky2
->rx_le_map
);
1061 pci_free_consistent(hw
->pdev
,
1062 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1063 sky2
->tx_le
, sky2
->tx_le_map
);
1066 kfree(sky2
->tx_ring
);
1067 kfree(sky2
->rx_ring
);
1069 sky2
->tx_ring
= NULL
;
1070 sky2
->rx_ring
= NULL
;
1074 /* Modular subtraction in ring */
1075 static inline int tx_dist(unsigned tail
, unsigned head
)
1077 return (head
- tail
) % TX_RING_SIZE
;
1080 /* Number of list elements available for next tx */
1081 static inline int tx_avail(const struct sky2_port
*sky2
)
1083 return sky2
->tx_pending
- tx_dist(sky2
->tx_cons
, sky2
->tx_prod
);
1086 /* Estimate of number of transmit list elements required */
1087 static unsigned tx_le_req(const struct sk_buff
*skb
)
1091 count
= sizeof(dma_addr_t
) / sizeof(u32
);
1092 count
+= skb_shinfo(skb
)->nr_frags
* count
;
1094 if (skb_shinfo(skb
)->tso_size
)
1097 if (skb
->ip_summed
== CHECKSUM_HW
)
1104 * Put one packet in ring for transmit.
1105 * A single packet can generate multiple list elements, and
1106 * the number of ring elements will probably be less than the number
1107 * of list elements used.
1109 * No BH disabling for tx_lock here (like tg3)
1111 static int sky2_xmit_frame(struct sk_buff
*skb
, struct net_device
*dev
)
1113 struct sky2_port
*sky2
= netdev_priv(dev
);
1114 struct sky2_hw
*hw
= sky2
->hw
;
1115 struct sky2_tx_le
*le
= NULL
;
1116 struct tx_ring_info
*re
;
1123 /* No BH disabling for tx_lock here. We are running in BH disabled
1124 * context and TX reclaim runs via poll inside of a software
1125 * interrupt, and no related locks in IRQ processing.
1127 if (!spin_trylock(&sky2
->tx_lock
))
1128 return NETDEV_TX_LOCKED
;
1130 if (unlikely(tx_avail(sky2
) < tx_le_req(skb
))) {
1131 /* There is a known but harmless race with lockless tx
1132 * and netif_stop_queue.
1134 if (!netif_queue_stopped(dev
)) {
1135 netif_stop_queue(dev
);
1136 if (net_ratelimit())
1137 printk(KERN_WARNING PFX
"%s: ring full when queue awake!\n",
1140 spin_unlock(&sky2
->tx_lock
);
1142 return NETDEV_TX_BUSY
;
1145 if (unlikely(netif_msg_tx_queued(sky2
)))
1146 printk(KERN_DEBUG
"%s: tx queued, slot %u, len %d\n",
1147 dev
->name
, sky2
->tx_prod
, skb
->len
);
1149 len
= skb_headlen(skb
);
1150 mapping
= pci_map_single(hw
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
1151 addr64
= high32(mapping
);
1153 re
= sky2
->tx_ring
+ sky2
->tx_prod
;
1155 /* Send high bits if changed or crosses boundary */
1156 if (addr64
!= sky2
->tx_addr64
|| high32(mapping
+ len
) != sky2
->tx_addr64
) {
1157 le
= get_tx_le(sky2
);
1158 le
->tx
.addr
= cpu_to_le32(addr64
);
1160 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1161 sky2
->tx_addr64
= high32(mapping
+ len
);
1164 /* Check for TCP Segmentation Offload */
1165 mss
= skb_shinfo(skb
)->tso_size
;
1167 /* just drop the packet if non-linear expansion fails */
1168 if (skb_header_cloned(skb
) &&
1169 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
1170 dev_kfree_skb_any(skb
);
1174 mss
+= ((skb
->h
.th
->doff
- 5) * 4); /* TCP options */
1175 mss
+= (skb
->nh
.iph
->ihl
* 4) + sizeof(struct tcphdr
);
1179 if (mss
!= sky2
->tx_last_mss
) {
1180 le
= get_tx_le(sky2
);
1181 le
->tx
.tso
.size
= cpu_to_le16(mss
);
1182 le
->tx
.tso
.rsvd
= 0;
1183 le
->opcode
= OP_LRGLEN
| HW_OWNER
;
1185 sky2
->tx_last_mss
= mss
;
1189 #ifdef SKY2_VLAN_TAG_USED
1190 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1191 if (sky2
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1193 le
= get_tx_le(sky2
);
1195 le
->opcode
= OP_VLAN
|HW_OWNER
;
1198 le
->opcode
|= OP_VLAN
;
1199 le
->length
= cpu_to_be16(vlan_tx_tag_get(skb
));
1204 /* Handle TCP checksum offload */
1205 if (skb
->ip_summed
== CHECKSUM_HW
) {
1206 u16 hdr
= skb
->h
.raw
- skb
->data
;
1207 u16 offset
= hdr
+ skb
->csum
;
1209 ctrl
= CALSUM
| WR_SUM
| INIT_SUM
| LOCK_SUM
;
1210 if (skb
->nh
.iph
->protocol
== IPPROTO_UDP
)
1213 le
= get_tx_le(sky2
);
1214 le
->tx
.csum
.start
= cpu_to_le16(hdr
);
1215 le
->tx
.csum
.offset
= cpu_to_le16(offset
);
1216 le
->length
= 0; /* initial checksum value */
1217 le
->ctrl
= 1; /* one packet */
1218 le
->opcode
= OP_TCPLISW
| HW_OWNER
;
1221 le
= get_tx_le(sky2
);
1222 le
->tx
.addr
= cpu_to_le32((u32
) mapping
);
1223 le
->length
= cpu_to_le16(len
);
1225 le
->opcode
= mss
? (OP_LARGESEND
| HW_OWNER
) : (OP_PACKET
| HW_OWNER
);
1227 /* Record the transmit mapping info */
1229 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1231 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1232 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1233 struct tx_ring_info
*fre
;
1235 mapping
= pci_map_page(hw
->pdev
, frag
->page
, frag
->page_offset
,
1236 frag
->size
, PCI_DMA_TODEVICE
);
1237 addr64
= high32(mapping
);
1238 if (addr64
!= sky2
->tx_addr64
) {
1239 le
= get_tx_le(sky2
);
1240 le
->tx
.addr
= cpu_to_le32(addr64
);
1242 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1243 sky2
->tx_addr64
= addr64
;
1246 le
= get_tx_le(sky2
);
1247 le
->tx
.addr
= cpu_to_le32((u32
) mapping
);
1248 le
->length
= cpu_to_le16(frag
->size
);
1250 le
->opcode
= OP_BUFFER
| HW_OWNER
;
1253 + ((re
- sky2
->tx_ring
) + i
+ 1) % TX_RING_SIZE
;
1254 pci_unmap_addr_set(fre
, mapaddr
, mapping
);
1257 re
->idx
= sky2
->tx_prod
;
1260 sky2_put_idx(hw
, txqaddr
[sky2
->port
], sky2
->tx_prod
,
1261 &sky2
->tx_last_put
, TX_RING_SIZE
);
1263 if (tx_avail(sky2
) <= MAX_SKB_TX_LE
)
1264 netif_stop_queue(dev
);
1267 spin_unlock(&sky2
->tx_lock
);
1269 dev
->trans_start
= jiffies
;
1270 return NETDEV_TX_OK
;
1274 * Free ring elements from starting at tx_cons until "done"
1276 * NB: the hardware will tell us about partial completion of multi-part
1277 * buffers; these are deferred until completion.
1279 static void sky2_tx_complete(struct sky2_port
*sky2
, u16 done
)
1281 struct net_device
*dev
= sky2
->netdev
;
1282 struct pci_dev
*pdev
= sky2
->hw
->pdev
;
1286 BUG_ON(done
>= TX_RING_SIZE
);
1288 if (unlikely(netif_msg_tx_done(sky2
)))
1289 printk(KERN_DEBUG
"%s: tx done, up to %u\n",
1292 for (put
= sky2
->tx_cons
; put
!= done
; put
= nxt
) {
1293 struct tx_ring_info
*re
= sky2
->tx_ring
+ put
;
1294 struct sk_buff
*skb
= re
->skb
;
1297 BUG_ON(nxt
>= TX_RING_SIZE
);
1298 prefetch(sky2
->tx_ring
+ nxt
);
1300 /* Check for partial status */
1301 if (tx_dist(put
, done
) < tx_dist(put
, nxt
))
1305 pci_unmap_single(pdev
, pci_unmap_addr(re
, mapaddr
),
1306 skb_headlen(skb
), PCI_DMA_TODEVICE
);
1308 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1309 struct tx_ring_info
*fre
;
1310 fre
= sky2
->tx_ring
+ (put
+ i
+ 1) % TX_RING_SIZE
;
1311 pci_unmap_page(pdev
, pci_unmap_addr(fre
, mapaddr
),
1312 skb_shinfo(skb
)->frags
[i
].size
,
1316 dev_kfree_skb_any(skb
);
1319 sky2
->tx_cons
= put
;
1320 if (netif_queue_stopped(dev
) && tx_avail(sky2
) > MAX_SKB_TX_LE
)
1321 netif_wake_queue(dev
);
1324 /* Cleanup all untransmitted buffers, assume transmitter not running */
1325 static void sky2_tx_clean(struct sky2_port
*sky2
)
1327 spin_lock_bh(&sky2
->tx_lock
);
1328 sky2_tx_complete(sky2
, sky2
->tx_prod
);
1329 spin_unlock_bh(&sky2
->tx_lock
);
1332 /* Network shutdown */
1333 static int sky2_down(struct net_device
*dev
)
1335 struct sky2_port
*sky2
= netdev_priv(dev
);
1336 struct sky2_hw
*hw
= sky2
->hw
;
1337 unsigned port
= sky2
->port
;
1340 /* Never really got started! */
1344 if (netif_msg_ifdown(sky2
))
1345 printk(KERN_INFO PFX
"%s: disabling interface\n", dev
->name
);
1347 /* Stop more packets from being queued */
1348 netif_stop_queue(dev
);
1350 /* Disable port IRQ */
1351 local_irq_disable();
1352 hw
->intr_mask
&= ~((sky2
->port
== 0) ? Y2_IS_IRQ_PHY1
: Y2_IS_IRQ_PHY2
);
1353 sky2_write32(hw
, B0_IMSK
, hw
->intr_mask
);
1356 flush_scheduled_work();
1358 sky2_phy_reset(hw
, port
);
1360 /* Stop transmitter */
1361 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_STOP
);
1362 sky2_read32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
));
1364 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
),
1365 RB_RST_SET
| RB_DIS_OP_MD
);
1367 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
1368 ctrl
&= ~(GM_GPCR_TX_ENA
| GM_GPCR_RX_ENA
);
1369 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
1371 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
1373 /* Workaround shared GMAC reset */
1374 if (!(hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0
1375 && port
== 0 && hw
->dev
[1] && netif_running(hw
->dev
[1])))
1376 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
1378 /* Disable Force Sync bit and Enable Alloc bit */
1379 sky2_write8(hw
, SK_REG(port
, TXA_CTRL
),
1380 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
1382 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1383 sky2_write32(hw
, SK_REG(port
, TXA_ITI_INI
), 0L);
1384 sky2_write32(hw
, SK_REG(port
, TXA_LIM_INI
), 0L);
1386 /* Reset the PCI FIFO of the async Tx queue */
1387 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
),
1388 BMU_RST_SET
| BMU_FIFO_RST
);
1390 /* Reset the Tx prefetch units */
1391 sky2_write32(hw
, Y2_QADDR(txqaddr
[port
], PREF_UNIT_CTRL
),
1394 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
), RB_RST_SET
);
1398 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
1399 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_SET
);
1401 /* turn off LED's */
1402 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
1404 synchronize_irq(hw
->pdev
->irq
);
1406 sky2_tx_clean(sky2
);
1407 sky2_rx_clean(sky2
);
1409 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1410 sky2
->rx_le
, sky2
->rx_le_map
);
1411 kfree(sky2
->rx_ring
);
1413 pci_free_consistent(hw
->pdev
,
1414 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1415 sky2
->tx_le
, sky2
->tx_le_map
);
1416 kfree(sky2
->tx_ring
);
1421 sky2
->rx_ring
= NULL
;
1422 sky2
->tx_ring
= NULL
;
1427 static u16
sky2_phy_speed(const struct sky2_hw
*hw
, u16 aux
)
1432 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
1433 return (aux
& PHY_M_PS_SPEED_100
) ? SPEED_100
: SPEED_10
;
1435 switch (aux
& PHY_M_PS_SPEED_MSK
) {
1436 case PHY_M_PS_SPEED_1000
:
1438 case PHY_M_PS_SPEED_100
:
1445 static void sky2_link_up(struct sky2_port
*sky2
)
1447 struct sky2_hw
*hw
= sky2
->hw
;
1448 unsigned port
= sky2
->port
;
1451 /* Enable Transmit FIFO Underrun */
1452 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), GMAC_DEF_MSK
);
1454 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1455 if (sky2
->autoneg
== AUTONEG_DISABLE
) {
1456 reg
|= GM_GPCR_AU_ALL_DIS
;
1458 /* Is write/read necessary? Copied from sky2_mac_init */
1459 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1460 gma_read16(hw
, port
, GM_GP_CTRL
);
1462 switch (sky2
->speed
) {
1464 reg
&= ~GM_GPCR_SPEED_100
;
1465 reg
|= GM_GPCR_SPEED_1000
;
1468 reg
&= ~GM_GPCR_SPEED_1000
;
1469 reg
|= GM_GPCR_SPEED_100
;
1472 reg
&= ~(GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
);
1476 reg
&= ~GM_GPCR_AU_ALL_DIS
;
1478 if (sky2
->duplex
== DUPLEX_FULL
|| sky2
->autoneg
== AUTONEG_ENABLE
)
1479 reg
|= GM_GPCR_DUP_FULL
;
1482 reg
|= GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
;
1483 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1484 gma_read16(hw
, port
, GM_GP_CTRL
);
1486 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
1488 netif_carrier_on(sky2
->netdev
);
1489 netif_wake_queue(sky2
->netdev
);
1491 /* Turn on link LED */
1492 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
),
1493 LINKLED_ON
| LINKLED_BLINK_OFF
| LINKLED_LINKSYNC_OFF
);
1495 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
1496 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
1498 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
1499 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1500 PHY_M_LEDC_INIT_CTRL(sky2
->speed
==
1502 PHY_M_LEDC_STA1_CTRL(sky2
->speed
==
1503 SPEED_100
? 7 : 0) |
1504 PHY_M_LEDC_STA0_CTRL(sky2
->speed
==
1505 SPEED_1000
? 7 : 0));
1506 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
1509 if (netif_msg_link(sky2
))
1510 printk(KERN_INFO PFX
1511 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1512 sky2
->netdev
->name
, sky2
->speed
,
1513 sky2
->duplex
== DUPLEX_FULL
? "full" : "half",
1514 (sky2
->tx_pause
&& sky2
->rx_pause
) ? "both" :
1515 sky2
->tx_pause
? "tx" : sky2
->rx_pause
? "rx" : "none");
1518 static void sky2_link_down(struct sky2_port
*sky2
)
1520 struct sky2_hw
*hw
= sky2
->hw
;
1521 unsigned port
= sky2
->port
;
1524 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
1526 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1527 reg
&= ~(GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
);
1528 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1529 gma_read16(hw
, port
, GM_GP_CTRL
); /* PCI post */
1531 if (sky2
->rx_pause
&& !sky2
->tx_pause
) {
1532 /* restore Asymmetric Pause bit */
1533 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
,
1534 gm_phy_read(hw
, port
, PHY_MARV_AUNE_ADV
)
1538 netif_carrier_off(sky2
->netdev
);
1539 netif_stop_queue(sky2
->netdev
);
1541 /* Turn on link LED */
1542 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_OFF
);
1544 if (netif_msg_link(sky2
))
1545 printk(KERN_INFO PFX
"%s: Link is down.\n", sky2
->netdev
->name
);
1546 sky2_phy_init(hw
, port
);
1549 static int sky2_autoneg_done(struct sky2_port
*sky2
, u16 aux
)
1551 struct sky2_hw
*hw
= sky2
->hw
;
1552 unsigned port
= sky2
->port
;
1555 lpa
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_LP
);
1557 if (lpa
& PHY_M_AN_RF
) {
1558 printk(KERN_ERR PFX
"%s: remote fault", sky2
->netdev
->name
);
1562 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
&&
1563 gm_phy_read(hw
, port
, PHY_MARV_1000T_STAT
) & PHY_B_1000S_MSF
) {
1564 printk(KERN_ERR PFX
"%s: master/slave fault",
1565 sky2
->netdev
->name
);
1569 if (!(aux
& PHY_M_PS_SPDUP_RES
)) {
1570 printk(KERN_ERR PFX
"%s: speed/duplex mismatch",
1571 sky2
->netdev
->name
);
1575 sky2
->duplex
= (aux
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1577 sky2
->speed
= sky2_phy_speed(hw
, aux
);
1579 /* Pause bits are offset (9..8) */
1580 if (hw
->chip_id
== CHIP_ID_YUKON_XL
)
1583 sky2
->rx_pause
= (aux
& PHY_M_PS_RX_P_EN
) != 0;
1584 sky2
->tx_pause
= (aux
& PHY_M_PS_TX_P_EN
) != 0;
1586 if ((sky2
->tx_pause
|| sky2
->rx_pause
)
1587 && !(sky2
->speed
< SPEED_1000
&& sky2
->duplex
== DUPLEX_HALF
))
1588 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
1590 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
1596 * Interrupt from PHY are handled outside of interrupt context
1597 * because accessing phy registers requires spin wait which might
1598 * cause excess interrupt latency.
1600 static void sky2_phy_task(void *arg
)
1602 struct sky2_port
*sky2
= arg
;
1603 struct sky2_hw
*hw
= sky2
->hw
;
1604 u16 istatus
, phystat
;
1606 down(&sky2
->phy_sema
);
1607 istatus
= gm_phy_read(hw
, sky2
->port
, PHY_MARV_INT_STAT
);
1608 phystat
= gm_phy_read(hw
, sky2
->port
, PHY_MARV_PHY_STAT
);
1610 if (netif_msg_intr(sky2
))
1611 printk(KERN_INFO PFX
"%s: phy interrupt status 0x%x 0x%x\n",
1612 sky2
->netdev
->name
, istatus
, phystat
);
1614 if (istatus
& PHY_M_IS_AN_COMPL
) {
1615 if (sky2_autoneg_done(sky2
, phystat
) == 0)
1620 if (istatus
& PHY_M_IS_LSP_CHANGE
)
1621 sky2
->speed
= sky2_phy_speed(hw
, phystat
);
1623 if (istatus
& PHY_M_IS_DUP_CHANGE
)
1625 (phystat
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1627 if (istatus
& PHY_M_IS_LST_CHANGE
) {
1628 if (phystat
& PHY_M_PS_LINK_UP
)
1631 sky2_link_down(sky2
);
1634 up(&sky2
->phy_sema
);
1636 local_irq_disable();
1637 hw
->intr_mask
|= (sky2
->port
== 0) ? Y2_IS_IRQ_PHY1
: Y2_IS_IRQ_PHY2
;
1638 sky2_write32(hw
, B0_IMSK
, hw
->intr_mask
);
1643 /* Transmit timeout is only called if we are running, carries is up
1644 * and tx queue is full (stopped).
1646 static void sky2_tx_timeout(struct net_device
*dev
)
1648 struct sky2_port
*sky2
= netdev_priv(dev
);
1649 struct sky2_hw
*hw
= sky2
->hw
;
1650 unsigned txq
= txqaddr
[sky2
->port
];
1653 /* Maybe we just missed an status interrupt */
1654 spin_lock(&sky2
->tx_lock
);
1655 ridx
= sky2_read16(hw
,
1656 sky2
->port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
);
1657 sky2_tx_complete(sky2
, ridx
);
1658 spin_unlock(&sky2
->tx_lock
);
1660 if (!netif_queue_stopped(dev
)) {
1661 if (net_ratelimit())
1662 pr_info(PFX
"transmit interrupt missed? recovered\n");
1666 if (netif_msg_timer(sky2
))
1667 printk(KERN_ERR PFX
"%s: tx timeout\n", dev
->name
);
1669 sky2_write32(hw
, Q_ADDR(txq
, Q_CSR
), BMU_STOP
);
1670 sky2_write32(hw
, Y2_QADDR(txq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
1672 sky2_tx_clean(sky2
);
1675 sky2_prefetch_init(hw
, txq
, sky2
->tx_le_map
, TX_RING_SIZE
- 1);
1679 #define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
1680 /* Want receive buffer size to be multiple of 64 bits, and incl room for vlan */
1681 static inline unsigned sky2_buf_size(int mtu
)
1683 return roundup(mtu
+ ETH_HLEN
+ 4, 8);
1686 static int sky2_change_mtu(struct net_device
*dev
, int new_mtu
)
1688 struct sky2_port
*sky2
= netdev_priv(dev
);
1689 struct sky2_hw
*hw
= sky2
->hw
;
1693 if (new_mtu
< ETH_ZLEN
|| new_mtu
> ETH_JUMBO_MTU
)
1696 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& new_mtu
> ETH_DATA_LEN
)
1699 if (!netif_running(dev
)) {
1704 sky2_write32(hw
, B0_IMSK
, 0);
1706 dev
->trans_start
= jiffies
; /* prevent tx timeout */
1707 netif_stop_queue(dev
);
1708 netif_poll_disable(hw
->dev
[0]);
1710 ctl
= gma_read16(hw
, sky2
->port
, GM_GP_CTRL
);
1711 gma_write16(hw
, sky2
->port
, GM_GP_CTRL
, ctl
& ~GM_GPCR_RX_ENA
);
1713 sky2_rx_clean(sky2
);
1716 sky2
->rx_bufsize
= sky2_buf_size(new_mtu
);
1717 mode
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
1718 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
1720 if (dev
->mtu
> ETH_DATA_LEN
)
1721 mode
|= GM_SMOD_JUMBO_ENA
;
1723 gma_write16(hw
, sky2
->port
, GM_SERIAL_MODE
, mode
);
1725 sky2_write8(hw
, RB_ADDR(rxqaddr
[sky2
->port
], RB_CTRL
), RB_ENA_OP_MD
);
1727 err
= sky2_rx_start(sky2
);
1728 sky2_write32(hw
, B0_IMSK
, hw
->intr_mask
);
1733 gma_write16(hw
, sky2
->port
, GM_GP_CTRL
, ctl
);
1735 netif_poll_enable(hw
->dev
[0]);
1736 netif_wake_queue(dev
);
1743 * Receive one packet.
1744 * For small packets or errors, just reuse existing skb.
1745 * For larger packets, get new buffer.
1747 static struct sk_buff
*sky2_receive(struct sky2_port
*sky2
,
1748 u16 length
, u32 status
)
1750 struct ring_info
*re
= sky2
->rx_ring
+ sky2
->rx_next
;
1751 struct sk_buff
*skb
= NULL
;
1753 if (unlikely(netif_msg_rx_status(sky2
)))
1754 printk(KERN_DEBUG PFX
"%s: rx slot %u status 0x%x len %d\n",
1755 sky2
->netdev
->name
, sky2
->rx_next
, status
, length
);
1757 sky2
->rx_next
= (sky2
->rx_next
+ 1) % sky2
->rx_pending
;
1758 prefetch(sky2
->rx_ring
+ sky2
->rx_next
);
1760 if (status
& GMR_FS_ANY_ERR
)
1763 if (!(status
& GMR_FS_RX_OK
))
1766 if ((status
>> 16) != length
|| length
> sky2
->rx_bufsize
)
1769 if (length
< copybreak
) {
1770 skb
= alloc_skb(length
+ 2, GFP_ATOMIC
);
1774 skb_reserve(skb
, 2);
1775 pci_dma_sync_single_for_cpu(sky2
->hw
->pdev
, re
->mapaddr
,
1776 length
, PCI_DMA_FROMDEVICE
);
1777 memcpy(skb
->data
, re
->skb
->data
, length
);
1778 skb
->ip_summed
= re
->skb
->ip_summed
;
1779 skb
->csum
= re
->skb
->csum
;
1780 pci_dma_sync_single_for_device(sky2
->hw
->pdev
, re
->mapaddr
,
1781 length
, PCI_DMA_FROMDEVICE
);
1783 struct sk_buff
*nskb
;
1785 nskb
= sky2_alloc_skb(sky2
->rx_bufsize
, GFP_ATOMIC
);
1791 pci_unmap_single(sky2
->hw
->pdev
, re
->mapaddr
,
1792 sky2
->rx_bufsize
, PCI_DMA_FROMDEVICE
);
1793 prefetch(skb
->data
);
1795 re
->mapaddr
= pci_map_single(sky2
->hw
->pdev
, nskb
->data
,
1796 sky2
->rx_bufsize
, PCI_DMA_FROMDEVICE
);
1799 skb_put(skb
, length
);
1801 re
->skb
->ip_summed
= CHECKSUM_NONE
;
1802 sky2_rx_add(sky2
, re
->mapaddr
);
1804 /* Tell receiver about new buffers. */
1805 sky2_put_idx(sky2
->hw
, rxqaddr
[sky2
->port
], sky2
->rx_put
,
1806 &sky2
->rx_last_put
, RX_LE_SIZE
);
1811 ++sky2
->net_stats
.rx_over_errors
;
1815 ++sky2
->net_stats
.rx_errors
;
1817 if (netif_msg_rx_err(sky2
) && net_ratelimit())
1818 printk(KERN_INFO PFX
"%s: rx error, status 0x%x length %d\n",
1819 sky2
->netdev
->name
, status
, length
);
1821 if (status
& (GMR_FS_LONG_ERR
| GMR_FS_UN_SIZE
))
1822 sky2
->net_stats
.rx_length_errors
++;
1823 if (status
& GMR_FS_FRAGMENT
)
1824 sky2
->net_stats
.rx_frame_errors
++;
1825 if (status
& GMR_FS_CRC_ERR
)
1826 sky2
->net_stats
.rx_crc_errors
++;
1827 if (status
& GMR_FS_RX_FF_OV
)
1828 sky2
->net_stats
.rx_fifo_errors
++;
1834 * Check for transmit complete
1836 #define TX_NO_STATUS 0xffff
1838 static void sky2_tx_check(struct sky2_hw
*hw
, int port
, u16 last
)
1840 if (last
!= TX_NO_STATUS
) {
1841 struct net_device
*dev
= hw
->dev
[port
];
1842 if (dev
&& netif_running(dev
)) {
1843 struct sky2_port
*sky2
= netdev_priv(dev
);
1845 spin_lock(&sky2
->tx_lock
);
1846 sky2_tx_complete(sky2
, last
);
1847 spin_unlock(&sky2
->tx_lock
);
1853 * Both ports share the same status interrupt, therefore there is only
1856 static int sky2_poll(struct net_device
*dev0
, int *budget
)
1858 struct sky2_hw
*hw
= ((struct sky2_port
*) netdev_priv(dev0
))->hw
;
1859 unsigned int to_do
= min(dev0
->quota
, *budget
);
1860 unsigned int work_done
= 0;
1862 u16 tx_done
[2] = { TX_NO_STATUS
, TX_NO_STATUS
};
1864 sky2_write32(hw
, STAT_CTRL
, SC_STAT_CLR_IRQ
);
1866 hwidx
= sky2_read16(hw
, STAT_PUT_IDX
);
1867 BUG_ON(hwidx
>= STATUS_RING_SIZE
);
1870 while (hwidx
!= hw
->st_idx
) {
1871 struct sky2_status_le
*le
= hw
->st_le
+ hw
->st_idx
;
1872 struct net_device
*dev
;
1873 struct sky2_port
*sky2
;
1874 struct sk_buff
*skb
;
1878 le
= hw
->st_le
+ hw
->st_idx
;
1879 hw
->st_idx
= (hw
->st_idx
+ 1) % STATUS_RING_SIZE
;
1880 prefetch(hw
->st_le
+ hw
->st_idx
);
1882 BUG_ON(le
->link
>= 2);
1883 dev
= hw
->dev
[le
->link
];
1884 if (dev
== NULL
|| !netif_running(dev
))
1887 sky2
= netdev_priv(dev
);
1888 status
= le32_to_cpu(le
->status
);
1889 length
= le16_to_cpu(le
->length
);
1891 switch (le
->opcode
& ~HW_OWNER
) {
1893 skb
= sky2_receive(sky2
, length
, status
);
1898 skb
->protocol
= eth_type_trans(skb
, dev
);
1899 dev
->last_rx
= jiffies
;
1901 #ifdef SKY2_VLAN_TAG_USED
1902 if (sky2
->vlgrp
&& (status
& GMR_FS_VLAN
)) {
1903 vlan_hwaccel_receive_skb(skb
,
1905 be16_to_cpu(sky2
->rx_tag
));
1908 netif_receive_skb(skb
);
1910 if (++work_done
>= to_do
)
1914 #ifdef SKY2_VLAN_TAG_USED
1916 sky2
->rx_tag
= length
;
1920 sky2
->rx_tag
= length
;
1924 skb
= sky2
->rx_ring
[sky2
->rx_next
].skb
;
1925 skb
->ip_summed
= CHECKSUM_HW
;
1926 skb
->csum
= le16_to_cpu(status
);
1930 /* TX index reports status for both ports */
1931 tx_done
[0] = status
& 0xffff;
1932 tx_done
[1] = ((status
>> 24) & 0xff)
1933 | (u16
)(length
& 0xf) << 8;
1937 if (net_ratelimit())
1938 printk(KERN_WARNING PFX
1939 "unknown status opcode 0x%x\n", le
->opcode
);
1945 sky2_tx_check(hw
, 0, tx_done
[0]);
1946 sky2_tx_check(hw
, 1, tx_done
[1]);
1948 if (likely(work_done
< to_do
)) {
1949 /* need to restart TX timer */
1951 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
1952 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
1955 netif_rx_complete(dev0
);
1956 hw
->intr_mask
|= Y2_IS_STAT_BMU
;
1957 sky2_write32(hw
, B0_IMSK
, hw
->intr_mask
);
1960 *budget
-= work_done
;
1961 dev0
->quota
-= work_done
;
1966 static void sky2_hw_error(struct sky2_hw
*hw
, unsigned port
, u32 status
)
1968 struct net_device
*dev
= hw
->dev
[port
];
1970 if (net_ratelimit())
1971 printk(KERN_INFO PFX
"%s: hw error interrupt status 0x%x\n",
1974 if (status
& Y2_IS_PAR_RD1
) {
1975 if (net_ratelimit())
1976 printk(KERN_ERR PFX
"%s: ram data read parity error\n",
1979 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_RD_PERR
);
1982 if (status
& Y2_IS_PAR_WR1
) {
1983 if (net_ratelimit())
1984 printk(KERN_ERR PFX
"%s: ram data write parity error\n",
1987 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_WR_PERR
);
1990 if (status
& Y2_IS_PAR_MAC1
) {
1991 if (net_ratelimit())
1992 printk(KERN_ERR PFX
"%s: MAC parity error\n", dev
->name
);
1993 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_PE
);
1996 if (status
& Y2_IS_PAR_RX1
) {
1997 if (net_ratelimit())
1998 printk(KERN_ERR PFX
"%s: RX parity error\n", dev
->name
);
1999 sky2_write32(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_PAR
);
2002 if (status
& Y2_IS_TCP_TXA1
) {
2003 if (net_ratelimit())
2004 printk(KERN_ERR PFX
"%s: TCP segmentation error\n",
2006 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_TCP
);
2010 static void sky2_hw_intr(struct sky2_hw
*hw
)
2012 u32 status
= sky2_read32(hw
, B0_HWE_ISRC
);
2014 if (status
& Y2_IS_TIST_OV
)
2015 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2017 if (status
& (Y2_IS_MST_ERR
| Y2_IS_IRQ_STAT
)) {
2020 pci_read_config_word(hw
->pdev
, PCI_STATUS
, &pci_err
);
2021 if (net_ratelimit())
2022 printk(KERN_ERR PFX
"%s: pci hw error (0x%x)\n",
2023 pci_name(hw
->pdev
), pci_err
);
2025 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2026 pci_write_config_word(hw
->pdev
, PCI_STATUS
,
2027 pci_err
| PCI_STATUS_ERROR_BITS
);
2028 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2031 if (status
& Y2_IS_PCI_EXP
) {
2032 /* PCI-Express uncorrectable Error occurred */
2035 pci_read_config_dword(hw
->pdev
, PEX_UNC_ERR_STAT
, &pex_err
);
2037 if (net_ratelimit())
2038 printk(KERN_ERR PFX
"%s: pci express error (0x%x)\n",
2039 pci_name(hw
->pdev
), pex_err
);
2041 /* clear the interrupt */
2042 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2043 pci_write_config_dword(hw
->pdev
, PEX_UNC_ERR_STAT
,
2045 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2047 if (pex_err
& PEX_FATAL_ERRORS
) {
2048 u32 hwmsk
= sky2_read32(hw
, B0_HWE_IMSK
);
2049 hwmsk
&= ~Y2_IS_PCI_EXP
;
2050 sky2_write32(hw
, B0_HWE_IMSK
, hwmsk
);
2054 if (status
& Y2_HWE_L1_MASK
)
2055 sky2_hw_error(hw
, 0, status
);
2057 if (status
& Y2_HWE_L1_MASK
)
2058 sky2_hw_error(hw
, 1, status
);
2061 static void sky2_mac_intr(struct sky2_hw
*hw
, unsigned port
)
2063 struct net_device
*dev
= hw
->dev
[port
];
2064 struct sky2_port
*sky2
= netdev_priv(dev
);
2065 u8 status
= sky2_read8(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
2067 if (netif_msg_intr(sky2
))
2068 printk(KERN_INFO PFX
"%s: mac interrupt status 0x%x\n",
2071 if (status
& GM_IS_RX_FF_OR
) {
2072 ++sky2
->net_stats
.rx_fifo_errors
;
2073 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_CLI_RX_FO
);
2076 if (status
& GM_IS_TX_FF_UR
) {
2077 ++sky2
->net_stats
.tx_fifo_errors
;
2078 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_FU
);
2082 static void sky2_phy_intr(struct sky2_hw
*hw
, unsigned port
)
2084 struct net_device
*dev
= hw
->dev
[port
];
2085 struct sky2_port
*sky2
= netdev_priv(dev
);
2087 hw
->intr_mask
&= ~(port
== 0 ? Y2_IS_IRQ_PHY1
: Y2_IS_IRQ_PHY2
);
2088 sky2_write32(hw
, B0_IMSK
, hw
->intr_mask
);
2089 schedule_work(&sky2
->phy_task
);
2092 static irqreturn_t
sky2_intr(int irq
, void *dev_id
, struct pt_regs
*regs
)
2094 struct sky2_hw
*hw
= dev_id
;
2095 struct net_device
*dev0
= hw
->dev
[0];
2098 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
2099 if (status
== 0 || status
== ~0)
2102 if (status
& Y2_IS_HW_ERR
)
2105 /* Do NAPI for Rx and Tx status */
2106 if (status
& Y2_IS_STAT_BMU
) {
2107 hw
->intr_mask
&= ~Y2_IS_STAT_BMU
;
2108 sky2_write32(hw
, B0_IMSK
, hw
->intr_mask
);
2110 if (likely(__netif_rx_schedule_prep(dev0
))) {
2111 prefetch(&hw
->st_le
[hw
->st_idx
]);
2112 __netif_rx_schedule(dev0
);
2116 if (status
& Y2_IS_IRQ_PHY1
)
2117 sky2_phy_intr(hw
, 0);
2119 if (status
& Y2_IS_IRQ_PHY2
)
2120 sky2_phy_intr(hw
, 1);
2122 if (status
& Y2_IS_IRQ_MAC1
)
2123 sky2_mac_intr(hw
, 0);
2125 if (status
& Y2_IS_IRQ_MAC2
)
2126 sky2_mac_intr(hw
, 1);
2128 sky2_write32(hw
, B0_Y2_SP_ICR
, 2);
2130 sky2_read32(hw
, B0_IMSK
);
2135 #ifdef CONFIG_NET_POLL_CONTROLLER
2136 static void sky2_netpoll(struct net_device
*dev
)
2138 struct sky2_port
*sky2
= netdev_priv(dev
);
2140 sky2_intr(sky2
->hw
->pdev
->irq
, sky2
->hw
, NULL
);
2144 /* Chip internal frequency for clock calculations */
2145 static inline u32
sky2_mhz(const struct sky2_hw
*hw
)
2147 switch (hw
->chip_id
) {
2148 case CHIP_ID_YUKON_EC
:
2149 case CHIP_ID_YUKON_EC_U
:
2150 return 125; /* 125 Mhz */
2151 case CHIP_ID_YUKON_FE
:
2152 return 100; /* 100 Mhz */
2153 default: /* YUKON_XL */
2154 return 156; /* 156 Mhz */
2158 static inline u32
sky2_us2clk(const struct sky2_hw
*hw
, u32 us
)
2160 return sky2_mhz(hw
) * us
;
2163 static inline u32
sky2_clk2us(const struct sky2_hw
*hw
, u32 clk
)
2165 return clk
/ sky2_mhz(hw
);
2169 static int sky2_reset(struct sky2_hw
*hw
)
2175 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2177 hw
->chip_id
= sky2_read8(hw
, B2_CHIP_ID
);
2178 if (hw
->chip_id
< CHIP_ID_YUKON_XL
|| hw
->chip_id
> CHIP_ID_YUKON_FE
) {
2179 printk(KERN_ERR PFX
"%s: unsupported chip type 0x%x\n",
2180 pci_name(hw
->pdev
), hw
->chip_id
);
2185 if (hw
->chip_id
<= CHIP_ID_YUKON_EC
) {
2186 sky2_write8(hw
, B28_Y2_ASF_STAT_CMD
, Y2_ASF_RESET
);
2187 sky2_write16(hw
, B0_CTST
, Y2_ASF_DISABLE
);
2191 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
2192 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2194 /* clear PCI errors, if any */
2195 err
= pci_read_config_word(hw
->pdev
, PCI_STATUS
, &status
);
2199 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2200 err
= pci_write_config_word(hw
->pdev
, PCI_STATUS
,
2201 status
| PCI_STATUS_ERROR_BITS
);
2205 sky2_write8(hw
, B0_CTST
, CS_MRST_CLR
);
2207 /* clear any PEX errors */
2208 if (pci_find_capability(hw
->pdev
, PCI_CAP_ID_EXP
)) {
2209 err
= pci_write_config_dword(hw
->pdev
, PEX_UNC_ERR_STAT
,
2215 pmd_type
= sky2_read8(hw
, B2_PMD_TYP
);
2216 hw
->copper
= !(pmd_type
== 'L' || pmd_type
== 'S');
2219 t8
= sky2_read8(hw
, B2_Y2_HW_RES
);
2220 if ((t8
& CFG_DUAL_MAC_MSK
) == CFG_DUAL_MAC_MSK
) {
2221 if (!(sky2_read8(hw
, B2_Y2_CLK_GATE
) & Y2_STATUS_LNK2_INAC
))
2224 hw
->chip_rev
= (sky2_read8(hw
, B2_MAC_CFG
) & CFG_CHIP_R_MSK
) >> 4;
2226 sky2_set_power_state(hw
, PCI_D0
);
2228 for (i
= 0; i
< hw
->ports
; i
++) {
2229 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
2230 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
2233 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2235 /* Clear I2C IRQ noise */
2236 sky2_write32(hw
, B2_I2C_IRQ
, 1);
2238 /* turn off hardware timer (unused) */
2239 sky2_write8(hw
, B2_TI_CTRL
, TIM_STOP
);
2240 sky2_write8(hw
, B2_TI_CTRL
, TIM_CLR_IRQ
);
2242 sky2_write8(hw
, B0_Y2LED
, LED_STAT_ON
);
2244 /* Turn off descriptor polling */
2245 sky2_write32(hw
, B28_DPT_CTRL
, DPT_STOP
);
2247 /* Turn off receive timestamp */
2248 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_STOP
);
2249 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2251 /* enable the Tx Arbiters */
2252 for (i
= 0; i
< hw
->ports
; i
++)
2253 sky2_write8(hw
, SK_REG(i
, TXA_CTRL
), TXA_ENA_ARB
);
2255 /* Initialize ram interface */
2256 for (i
= 0; i
< hw
->ports
; i
++) {
2257 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_CTRL
), RI_RST_CLR
);
2259 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R1
), SK_RI_TO_53
);
2260 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA1
), SK_RI_TO_53
);
2261 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS1
), SK_RI_TO_53
);
2262 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R1
), SK_RI_TO_53
);
2263 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA1
), SK_RI_TO_53
);
2264 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS1
), SK_RI_TO_53
);
2265 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R2
), SK_RI_TO_53
);
2266 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA2
), SK_RI_TO_53
);
2267 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS2
), SK_RI_TO_53
);
2268 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R2
), SK_RI_TO_53
);
2269 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA2
), SK_RI_TO_53
);
2270 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS2
), SK_RI_TO_53
);
2273 sky2_write32(hw
, B0_HWE_IMSK
, Y2_HWE_ALL_MASK
);
2275 for (i
= 0; i
< hw
->ports
; i
++)
2276 sky2_phy_reset(hw
, i
);
2278 memset(hw
->st_le
, 0, STATUS_LE_BYTES
);
2281 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_SET
);
2282 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_CLR
);
2284 sky2_write32(hw
, STAT_LIST_ADDR_LO
, hw
->st_dma
);
2285 sky2_write32(hw
, STAT_LIST_ADDR_HI
, (u64
) hw
->st_dma
>> 32);
2287 /* Set the list last index */
2288 sky2_write16(hw
, STAT_LAST_IDX
, STATUS_RING_SIZE
- 1);
2290 /* These status setup values are copied from SysKonnect's driver */
2292 /* WA for dev. #4.3 */
2293 sky2_write16(hw
, STAT_TX_IDX_TH
, 0xfff); /* Tx Threshold */
2295 /* set Status-FIFO watermark */
2296 sky2_write8(hw
, STAT_FIFO_WM
, 0x21); /* WA for dev. #4.18 */
2298 /* set Status-FIFO ISR watermark */
2299 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 0x07); /* WA for dev. #4.18 */
2300 sky2_write32(hw
, STAT_TX_TIMER_INI
, sky2_us2clk(hw
, 10000));
2302 sky2_write16(hw
, STAT_TX_IDX_TH
, 10);
2303 sky2_write8(hw
, STAT_FIFO_WM
, 16);
2305 /* set Status-FIFO ISR watermark */
2306 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0)
2307 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 4);
2309 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 16);
2311 sky2_write32(hw
, STAT_TX_TIMER_INI
, sky2_us2clk(hw
, 1000));
2312 sky2_write32(hw
, STAT_LEV_TIMER_INI
, sky2_us2clk(hw
, 100));
2313 sky2_write32(hw
, STAT_ISR_TIMER_INI
, sky2_us2clk(hw
, 20));
2316 /* enable status unit */
2317 sky2_write32(hw
, STAT_CTRL
, SC_STAT_OP_ON
);
2319 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2320 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
2321 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
2326 /* This is to catch a BIOS bug workaround where
2327 * mmconfig table doesn't have other buses.
2329 printk(KERN_ERR PFX
"%s: can't access PCI config space\n",
2330 pci_name(hw
->pdev
));
2334 static u32
sky2_supported_modes(const struct sky2_hw
*hw
)
2338 modes
= SUPPORTED_10baseT_Half
2339 | SUPPORTED_10baseT_Full
2340 | SUPPORTED_100baseT_Half
2341 | SUPPORTED_100baseT_Full
2342 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2344 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
2345 modes
|= SUPPORTED_1000baseT_Half
2346 | SUPPORTED_1000baseT_Full
;
2348 modes
= SUPPORTED_1000baseT_Full
| SUPPORTED_FIBRE
2349 | SUPPORTED_Autoneg
;
2353 static int sky2_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2355 struct sky2_port
*sky2
= netdev_priv(dev
);
2356 struct sky2_hw
*hw
= sky2
->hw
;
2358 ecmd
->transceiver
= XCVR_INTERNAL
;
2359 ecmd
->supported
= sky2_supported_modes(hw
);
2360 ecmd
->phy_address
= PHY_ADDR_MARV
;
2362 ecmd
->supported
= SUPPORTED_10baseT_Half
2363 | SUPPORTED_10baseT_Full
2364 | SUPPORTED_100baseT_Half
2365 | SUPPORTED_100baseT_Full
2366 | SUPPORTED_1000baseT_Half
2367 | SUPPORTED_1000baseT_Full
2368 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2369 ecmd
->port
= PORT_TP
;
2371 ecmd
->port
= PORT_FIBRE
;
2373 ecmd
->advertising
= sky2
->advertising
;
2374 ecmd
->autoneg
= sky2
->autoneg
;
2375 ecmd
->speed
= sky2
->speed
;
2376 ecmd
->duplex
= sky2
->duplex
;
2380 static int sky2_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2382 struct sky2_port
*sky2
= netdev_priv(dev
);
2383 const struct sky2_hw
*hw
= sky2
->hw
;
2384 u32 supported
= sky2_supported_modes(hw
);
2386 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
2387 ecmd
->advertising
= supported
;
2393 switch (ecmd
->speed
) {
2395 if (ecmd
->duplex
== DUPLEX_FULL
)
2396 setting
= SUPPORTED_1000baseT_Full
;
2397 else if (ecmd
->duplex
== DUPLEX_HALF
)
2398 setting
= SUPPORTED_1000baseT_Half
;
2403 if (ecmd
->duplex
== DUPLEX_FULL
)
2404 setting
= SUPPORTED_100baseT_Full
;
2405 else if (ecmd
->duplex
== DUPLEX_HALF
)
2406 setting
= SUPPORTED_100baseT_Half
;
2412 if (ecmd
->duplex
== DUPLEX_FULL
)
2413 setting
= SUPPORTED_10baseT_Full
;
2414 else if (ecmd
->duplex
== DUPLEX_HALF
)
2415 setting
= SUPPORTED_10baseT_Half
;
2423 if ((setting
& supported
) == 0)
2426 sky2
->speed
= ecmd
->speed
;
2427 sky2
->duplex
= ecmd
->duplex
;
2430 sky2
->autoneg
= ecmd
->autoneg
;
2431 sky2
->advertising
= ecmd
->advertising
;
2433 if (netif_running(dev
))
2434 sky2_phy_reinit(sky2
);
2439 static void sky2_get_drvinfo(struct net_device
*dev
,
2440 struct ethtool_drvinfo
*info
)
2442 struct sky2_port
*sky2
= netdev_priv(dev
);
2444 strcpy(info
->driver
, DRV_NAME
);
2445 strcpy(info
->version
, DRV_VERSION
);
2446 strcpy(info
->fw_version
, "N/A");
2447 strcpy(info
->bus_info
, pci_name(sky2
->hw
->pdev
));
2450 static const struct sky2_stat
{
2451 char name
[ETH_GSTRING_LEN
];
2454 { "tx_bytes", GM_TXO_OK_HI
},
2455 { "rx_bytes", GM_RXO_OK_HI
},
2456 { "tx_broadcast", GM_TXF_BC_OK
},
2457 { "rx_broadcast", GM_RXF_BC_OK
},
2458 { "tx_multicast", GM_TXF_MC_OK
},
2459 { "rx_multicast", GM_RXF_MC_OK
},
2460 { "tx_unicast", GM_TXF_UC_OK
},
2461 { "rx_unicast", GM_RXF_UC_OK
},
2462 { "tx_mac_pause", GM_TXF_MPAUSE
},
2463 { "rx_mac_pause", GM_RXF_MPAUSE
},
2464 { "collisions", GM_TXF_SNG_COL
},
2465 { "late_collision",GM_TXF_LAT_COL
},
2466 { "aborted", GM_TXF_ABO_COL
},
2467 { "multi_collisions", GM_TXF_MUL_COL
},
2468 { "fifo_underrun", GM_TXE_FIFO_UR
},
2469 { "fifo_overflow", GM_RXE_FIFO_OV
},
2470 { "rx_toolong", GM_RXF_LNG_ERR
},
2471 { "rx_jabber", GM_RXF_JAB_PKT
},
2472 { "rx_runt", GM_RXE_FRAG
},
2473 { "rx_too_long", GM_RXF_LNG_ERR
},
2474 { "rx_fcs_error", GM_RXF_FCS_ERR
},
2477 static u32
sky2_get_rx_csum(struct net_device
*dev
)
2479 struct sky2_port
*sky2
= netdev_priv(dev
);
2481 return sky2
->rx_csum
;
2484 static int sky2_set_rx_csum(struct net_device
*dev
, u32 data
)
2486 struct sky2_port
*sky2
= netdev_priv(dev
);
2488 sky2
->rx_csum
= data
;
2490 sky2_write32(sky2
->hw
, Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
2491 data
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
2496 static u32
sky2_get_msglevel(struct net_device
*netdev
)
2498 struct sky2_port
*sky2
= netdev_priv(netdev
);
2499 return sky2
->msg_enable
;
2502 static int sky2_nway_reset(struct net_device
*dev
)
2504 struct sky2_port
*sky2
= netdev_priv(dev
);
2506 if (sky2
->autoneg
!= AUTONEG_ENABLE
)
2509 sky2_phy_reinit(sky2
);
2514 static void sky2_phy_stats(struct sky2_port
*sky2
, u64
* data
, unsigned count
)
2516 struct sky2_hw
*hw
= sky2
->hw
;
2517 unsigned port
= sky2
->port
;
2520 data
[0] = (u64
) gma_read32(hw
, port
, GM_TXO_OK_HI
) << 32
2521 | (u64
) gma_read32(hw
, port
, GM_TXO_OK_LO
);
2522 data
[1] = (u64
) gma_read32(hw
, port
, GM_RXO_OK_HI
) << 32
2523 | (u64
) gma_read32(hw
, port
, GM_RXO_OK_LO
);
2525 for (i
= 2; i
< count
; i
++)
2526 data
[i
] = (u64
) gma_read32(hw
, port
, sky2_stats
[i
].offset
);
2529 static void sky2_set_msglevel(struct net_device
*netdev
, u32 value
)
2531 struct sky2_port
*sky2
= netdev_priv(netdev
);
2532 sky2
->msg_enable
= value
;
2535 static int sky2_get_stats_count(struct net_device
*dev
)
2537 return ARRAY_SIZE(sky2_stats
);
2540 static void sky2_get_ethtool_stats(struct net_device
*dev
,
2541 struct ethtool_stats
*stats
, u64
* data
)
2543 struct sky2_port
*sky2
= netdev_priv(dev
);
2545 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(sky2_stats
));
2548 static void sky2_get_strings(struct net_device
*dev
, u32 stringset
, u8
* data
)
2552 switch (stringset
) {
2554 for (i
= 0; i
< ARRAY_SIZE(sky2_stats
); i
++)
2555 memcpy(data
+ i
* ETH_GSTRING_LEN
,
2556 sky2_stats
[i
].name
, ETH_GSTRING_LEN
);
2561 /* Use hardware MIB variables for critical path statistics and
2562 * transmit feedback not reported at interrupt.
2563 * Other errors are accounted for in interrupt handler.
2565 static struct net_device_stats
*sky2_get_stats(struct net_device
*dev
)
2567 struct sky2_port
*sky2
= netdev_priv(dev
);
2570 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(data
));
2572 sky2
->net_stats
.tx_bytes
= data
[0];
2573 sky2
->net_stats
.rx_bytes
= data
[1];
2574 sky2
->net_stats
.tx_packets
= data
[2] + data
[4] + data
[6];
2575 sky2
->net_stats
.rx_packets
= data
[3] + data
[5] + data
[7];
2576 sky2
->net_stats
.multicast
= data
[5] + data
[7];
2577 sky2
->net_stats
.collisions
= data
[10];
2578 sky2
->net_stats
.tx_aborted_errors
= data
[12];
2580 return &sky2
->net_stats
;
2583 static int sky2_set_mac_address(struct net_device
*dev
, void *p
)
2585 struct sky2_port
*sky2
= netdev_priv(dev
);
2586 struct sky2_hw
*hw
= sky2
->hw
;
2587 unsigned port
= sky2
->port
;
2588 const struct sockaddr
*addr
= p
;
2590 if (!is_valid_ether_addr(addr
->sa_data
))
2591 return -EADDRNOTAVAIL
;
2593 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
2594 memcpy_toio(hw
->regs
+ B2_MAC_1
+ port
* 8,
2595 dev
->dev_addr
, ETH_ALEN
);
2596 memcpy_toio(hw
->regs
+ B2_MAC_2
+ port
* 8,
2597 dev
->dev_addr
, ETH_ALEN
);
2599 /* virtual address for data */
2600 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, dev
->dev_addr
);
2602 /* physical address: used for pause frames */
2603 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, dev
->dev_addr
);
2608 static void sky2_set_multicast(struct net_device
*dev
)
2610 struct sky2_port
*sky2
= netdev_priv(dev
);
2611 struct sky2_hw
*hw
= sky2
->hw
;
2612 unsigned port
= sky2
->port
;
2613 struct dev_mc_list
*list
= dev
->mc_list
;
2617 memset(filter
, 0, sizeof(filter
));
2619 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
2620 reg
|= GM_RXCR_UCF_ENA
;
2622 if (dev
->flags
& IFF_PROMISC
) /* promiscuous */
2623 reg
&= ~(GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
2624 else if ((dev
->flags
& IFF_ALLMULTI
) || dev
->mc_count
> 16) /* all multicast */
2625 memset(filter
, 0xff, sizeof(filter
));
2626 else if (dev
->mc_count
== 0) /* no multicast */
2627 reg
&= ~GM_RXCR_MCF_ENA
;
2630 reg
|= GM_RXCR_MCF_ENA
;
2632 for (i
= 0; list
&& i
< dev
->mc_count
; i
++, list
= list
->next
) {
2633 u32 bit
= ether_crc(ETH_ALEN
, list
->dmi_addr
) & 0x3f;
2634 filter
[bit
/ 8] |= 1 << (bit
% 8);
2638 gma_write16(hw
, port
, GM_MC_ADDR_H1
,
2639 (u16
) filter
[0] | ((u16
) filter
[1] << 8));
2640 gma_write16(hw
, port
, GM_MC_ADDR_H2
,
2641 (u16
) filter
[2] | ((u16
) filter
[3] << 8));
2642 gma_write16(hw
, port
, GM_MC_ADDR_H3
,
2643 (u16
) filter
[4] | ((u16
) filter
[5] << 8));
2644 gma_write16(hw
, port
, GM_MC_ADDR_H4
,
2645 (u16
) filter
[6] | ((u16
) filter
[7] << 8));
2647 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
2650 /* Can have one global because blinking is controlled by
2651 * ethtool and that is always under RTNL mutex
2653 static void sky2_led(struct sky2_hw
*hw
, unsigned port
, int on
)
2657 switch (hw
->chip_id
) {
2658 case CHIP_ID_YUKON_XL
:
2659 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2660 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2661 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
2662 on
? (PHY_M_LEDC_LOS_CTRL(1) |
2663 PHY_M_LEDC_INIT_CTRL(7) |
2664 PHY_M_LEDC_STA1_CTRL(7) |
2665 PHY_M_LEDC_STA0_CTRL(7))
2668 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2672 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, 0);
2673 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
2674 on
? PHY_M_LED_MO_DUP(MO_LED_ON
) |
2675 PHY_M_LED_MO_10(MO_LED_ON
) |
2676 PHY_M_LED_MO_100(MO_LED_ON
) |
2677 PHY_M_LED_MO_1000(MO_LED_ON
) |
2678 PHY_M_LED_MO_RX(MO_LED_ON
)
2679 : PHY_M_LED_MO_DUP(MO_LED_OFF
) |
2680 PHY_M_LED_MO_10(MO_LED_OFF
) |
2681 PHY_M_LED_MO_100(MO_LED_OFF
) |
2682 PHY_M_LED_MO_1000(MO_LED_OFF
) |
2683 PHY_M_LED_MO_RX(MO_LED_OFF
));
2688 /* blink LED's for finding board */
2689 static int sky2_phys_id(struct net_device
*dev
, u32 data
)
2691 struct sky2_port
*sky2
= netdev_priv(dev
);
2692 struct sky2_hw
*hw
= sky2
->hw
;
2693 unsigned port
= sky2
->port
;
2694 u16 ledctrl
, ledover
= 0;
2699 if (!data
|| data
> (u32
) (MAX_SCHEDULE_TIMEOUT
/ HZ
))
2700 ms
= jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT
);
2704 /* save initial values */
2705 down(&sky2
->phy_sema
);
2706 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
2707 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2708 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2709 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
2710 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2712 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_LED_CTRL
);
2713 ledover
= gm_phy_read(hw
, port
, PHY_MARV_LED_OVER
);
2717 while (!interrupted
&& ms
> 0) {
2718 sky2_led(hw
, port
, onoff
);
2721 up(&sky2
->phy_sema
);
2722 interrupted
= msleep_interruptible(250);
2723 down(&sky2
->phy_sema
);
2728 /* resume regularly scheduled programming */
2729 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
2730 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2731 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2732 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ledctrl
);
2733 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2735 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
2736 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
2738 up(&sky2
->phy_sema
);
2743 static void sky2_get_pauseparam(struct net_device
*dev
,
2744 struct ethtool_pauseparam
*ecmd
)
2746 struct sky2_port
*sky2
= netdev_priv(dev
);
2748 ecmd
->tx_pause
= sky2
->tx_pause
;
2749 ecmd
->rx_pause
= sky2
->rx_pause
;
2750 ecmd
->autoneg
= sky2
->autoneg
;
2753 static int sky2_set_pauseparam(struct net_device
*dev
,
2754 struct ethtool_pauseparam
*ecmd
)
2756 struct sky2_port
*sky2
= netdev_priv(dev
);
2759 sky2
->autoneg
= ecmd
->autoneg
;
2760 sky2
->tx_pause
= ecmd
->tx_pause
!= 0;
2761 sky2
->rx_pause
= ecmd
->rx_pause
!= 0;
2763 sky2_phy_reinit(sky2
);
2769 static void sky2_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2771 struct sky2_port
*sky2
= netdev_priv(dev
);
2773 wol
->supported
= WAKE_MAGIC
;
2774 wol
->wolopts
= sky2
->wol
? WAKE_MAGIC
: 0;
2777 static int sky2_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2779 struct sky2_port
*sky2
= netdev_priv(dev
);
2780 struct sky2_hw
*hw
= sky2
->hw
;
2782 if (wol
->wolopts
!= WAKE_MAGIC
&& wol
->wolopts
!= 0)
2785 sky2
->wol
= wol
->wolopts
== WAKE_MAGIC
;
2788 memcpy_toio(hw
->regs
+ WOL_MAC_ADDR
, dev
->dev_addr
, ETH_ALEN
);
2790 sky2_write16(hw
, WOL_CTRL_STAT
,
2791 WOL_CTL_ENA_PME_ON_MAGIC_PKT
|
2792 WOL_CTL_ENA_MAGIC_PKT_UNIT
);
2794 sky2_write16(hw
, WOL_CTRL_STAT
, WOL_CTL_DEFAULT
);
2800 static int sky2_get_coalesce(struct net_device
*dev
,
2801 struct ethtool_coalesce
*ecmd
)
2803 struct sky2_port
*sky2
= netdev_priv(dev
);
2804 struct sky2_hw
*hw
= sky2
->hw
;
2806 if (sky2_read8(hw
, STAT_TX_TIMER_CTRL
) == TIM_STOP
)
2807 ecmd
->tx_coalesce_usecs
= 0;
2809 u32 clks
= sky2_read32(hw
, STAT_TX_TIMER_INI
);
2810 ecmd
->tx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
2812 ecmd
->tx_max_coalesced_frames
= sky2_read16(hw
, STAT_TX_IDX_TH
);
2814 if (sky2_read8(hw
, STAT_LEV_TIMER_CTRL
) == TIM_STOP
)
2815 ecmd
->rx_coalesce_usecs
= 0;
2817 u32 clks
= sky2_read32(hw
, STAT_LEV_TIMER_INI
);
2818 ecmd
->rx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
2820 ecmd
->rx_max_coalesced_frames
= sky2_read8(hw
, STAT_FIFO_WM
);
2822 if (sky2_read8(hw
, STAT_ISR_TIMER_CTRL
) == TIM_STOP
)
2823 ecmd
->rx_coalesce_usecs_irq
= 0;
2825 u32 clks
= sky2_read32(hw
, STAT_ISR_TIMER_INI
);
2826 ecmd
->rx_coalesce_usecs_irq
= sky2_clk2us(hw
, clks
);
2829 ecmd
->rx_max_coalesced_frames_irq
= sky2_read8(hw
, STAT_FIFO_ISR_WM
);
2834 /* Note: this affect both ports */
2835 static int sky2_set_coalesce(struct net_device
*dev
,
2836 struct ethtool_coalesce
*ecmd
)
2838 struct sky2_port
*sky2
= netdev_priv(dev
);
2839 struct sky2_hw
*hw
= sky2
->hw
;
2840 const u32 tmin
= sky2_clk2us(hw
, 1);
2841 const u32 tmax
= 5000;
2843 if (ecmd
->tx_coalesce_usecs
!= 0 &&
2844 (ecmd
->tx_coalesce_usecs
< tmin
|| ecmd
->tx_coalesce_usecs
> tmax
))
2847 if (ecmd
->rx_coalesce_usecs
!= 0 &&
2848 (ecmd
->rx_coalesce_usecs
< tmin
|| ecmd
->rx_coalesce_usecs
> tmax
))
2851 if (ecmd
->rx_coalesce_usecs_irq
!= 0 &&
2852 (ecmd
->rx_coalesce_usecs_irq
< tmin
|| ecmd
->rx_coalesce_usecs_irq
> tmax
))
2855 if (ecmd
->tx_max_coalesced_frames
> 0xffff)
2857 if (ecmd
->rx_max_coalesced_frames
> 0xff)
2859 if (ecmd
->rx_max_coalesced_frames_irq
> 0xff)
2862 if (ecmd
->tx_coalesce_usecs
== 0)
2863 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
2865 sky2_write32(hw
, STAT_TX_TIMER_INI
,
2866 sky2_us2clk(hw
, ecmd
->tx_coalesce_usecs
));
2867 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2869 sky2_write16(hw
, STAT_TX_IDX_TH
, ecmd
->tx_max_coalesced_frames
);
2871 if (ecmd
->rx_coalesce_usecs
== 0)
2872 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_STOP
);
2874 sky2_write32(hw
, STAT_LEV_TIMER_INI
,
2875 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs
));
2876 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
2878 sky2_write8(hw
, STAT_FIFO_WM
, ecmd
->rx_max_coalesced_frames
);
2880 if (ecmd
->rx_coalesce_usecs_irq
== 0)
2881 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_STOP
);
2883 sky2_write32(hw
, STAT_ISR_TIMER_INI
,
2884 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs_irq
));
2885 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
2887 sky2_write8(hw
, STAT_FIFO_ISR_WM
, ecmd
->rx_max_coalesced_frames_irq
);
2891 static void sky2_get_ringparam(struct net_device
*dev
,
2892 struct ethtool_ringparam
*ering
)
2894 struct sky2_port
*sky2
= netdev_priv(dev
);
2896 ering
->rx_max_pending
= RX_MAX_PENDING
;
2897 ering
->rx_mini_max_pending
= 0;
2898 ering
->rx_jumbo_max_pending
= 0;
2899 ering
->tx_max_pending
= TX_RING_SIZE
- 1;
2901 ering
->rx_pending
= sky2
->rx_pending
;
2902 ering
->rx_mini_pending
= 0;
2903 ering
->rx_jumbo_pending
= 0;
2904 ering
->tx_pending
= sky2
->tx_pending
;
2907 static int sky2_set_ringparam(struct net_device
*dev
,
2908 struct ethtool_ringparam
*ering
)
2910 struct sky2_port
*sky2
= netdev_priv(dev
);
2913 if (ering
->rx_pending
> RX_MAX_PENDING
||
2914 ering
->rx_pending
< 8 ||
2915 ering
->tx_pending
< MAX_SKB_TX_LE
||
2916 ering
->tx_pending
> TX_RING_SIZE
- 1)
2919 if (netif_running(dev
))
2922 sky2
->rx_pending
= ering
->rx_pending
;
2923 sky2
->tx_pending
= ering
->tx_pending
;
2925 if (netif_running(dev
)) {
2930 sky2_set_multicast(dev
);
2936 static int sky2_get_regs_len(struct net_device
*dev
)
2942 * Returns copy of control register region
2943 * Note: access to the RAM address register set will cause timeouts.
2945 static void sky2_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
2948 const struct sky2_port
*sky2
= netdev_priv(dev
);
2949 const void __iomem
*io
= sky2
->hw
->regs
;
2951 BUG_ON(regs
->len
< B3_RI_WTO_R1
);
2953 memset(p
, 0, regs
->len
);
2955 memcpy_fromio(p
, io
, B3_RAM_ADDR
);
2957 memcpy_fromio(p
+ B3_RI_WTO_R1
,
2959 regs
->len
- B3_RI_WTO_R1
);
2962 static struct ethtool_ops sky2_ethtool_ops
= {
2963 .get_settings
= sky2_get_settings
,
2964 .set_settings
= sky2_set_settings
,
2965 .get_drvinfo
= sky2_get_drvinfo
,
2966 .get_msglevel
= sky2_get_msglevel
,
2967 .set_msglevel
= sky2_set_msglevel
,
2968 .nway_reset
= sky2_nway_reset
,
2969 .get_regs_len
= sky2_get_regs_len
,
2970 .get_regs
= sky2_get_regs
,
2971 .get_link
= ethtool_op_get_link
,
2972 .get_sg
= ethtool_op_get_sg
,
2973 .set_sg
= ethtool_op_set_sg
,
2974 .get_tx_csum
= ethtool_op_get_tx_csum
,
2975 .set_tx_csum
= ethtool_op_set_tx_csum
,
2976 .get_tso
= ethtool_op_get_tso
,
2977 .set_tso
= ethtool_op_set_tso
,
2978 .get_rx_csum
= sky2_get_rx_csum
,
2979 .set_rx_csum
= sky2_set_rx_csum
,
2980 .get_strings
= sky2_get_strings
,
2981 .get_coalesce
= sky2_get_coalesce
,
2982 .set_coalesce
= sky2_set_coalesce
,
2983 .get_ringparam
= sky2_get_ringparam
,
2984 .set_ringparam
= sky2_set_ringparam
,
2985 .get_pauseparam
= sky2_get_pauseparam
,
2986 .set_pauseparam
= sky2_set_pauseparam
,
2988 .get_wol
= sky2_get_wol
,
2989 .set_wol
= sky2_set_wol
,
2991 .phys_id
= sky2_phys_id
,
2992 .get_stats_count
= sky2_get_stats_count
,
2993 .get_ethtool_stats
= sky2_get_ethtool_stats
,
2994 .get_perm_addr
= ethtool_op_get_perm_addr
,
2997 /* Initialize network device */
2998 static __devinit
struct net_device
*sky2_init_netdev(struct sky2_hw
*hw
,
2999 unsigned port
, int highmem
)
3001 struct sky2_port
*sky2
;
3002 struct net_device
*dev
= alloc_etherdev(sizeof(*sky2
));
3005 printk(KERN_ERR
"sky2 etherdev alloc failed");
3009 SET_MODULE_OWNER(dev
);
3010 SET_NETDEV_DEV(dev
, &hw
->pdev
->dev
);
3011 dev
->irq
= hw
->pdev
->irq
;
3012 dev
->open
= sky2_up
;
3013 dev
->stop
= sky2_down
;
3014 dev
->do_ioctl
= sky2_ioctl
;
3015 dev
->hard_start_xmit
= sky2_xmit_frame
;
3016 dev
->get_stats
= sky2_get_stats
;
3017 dev
->set_multicast_list
= sky2_set_multicast
;
3018 dev
->set_mac_address
= sky2_set_mac_address
;
3019 dev
->change_mtu
= sky2_change_mtu
;
3020 SET_ETHTOOL_OPS(dev
, &sky2_ethtool_ops
);
3021 dev
->tx_timeout
= sky2_tx_timeout
;
3022 dev
->watchdog_timeo
= TX_WATCHDOG
;
3024 dev
->poll
= sky2_poll
;
3025 dev
->weight
= NAPI_WEIGHT
;
3026 #ifdef CONFIG_NET_POLL_CONTROLLER
3027 dev
->poll_controller
= sky2_netpoll
;
3030 sky2
= netdev_priv(dev
);
3033 sky2
->msg_enable
= netif_msg_init(debug
, default_msg
);
3035 spin_lock_init(&sky2
->tx_lock
);
3036 /* Auto speed and flow control */
3037 sky2
->autoneg
= AUTONEG_ENABLE
;
3042 sky2
->advertising
= sky2_supported_modes(hw
);
3044 /* Receive checksum disabled for Yukon XL
3045 * because of observed problems with incorrect
3046 * values when multiple packets are received in one interrupt
3048 sky2
->rx_csum
= (hw
->chip_id
!= CHIP_ID_YUKON_XL
);
3050 INIT_WORK(&sky2
->phy_task
, sky2_phy_task
, sky2
);
3051 init_MUTEX(&sky2
->phy_sema
);
3052 sky2
->tx_pending
= TX_DEF_PENDING
;
3053 sky2
->rx_pending
= is_ec_a1(hw
) ? 8 : RX_DEF_PENDING
;
3054 sky2
->rx_bufsize
= sky2_buf_size(ETH_DATA_LEN
);
3056 hw
->dev
[port
] = dev
;
3060 dev
->features
|= NETIF_F_LLTX
;
3061 if (hw
->chip_id
!= CHIP_ID_YUKON_EC_U
)
3062 dev
->features
|= NETIF_F_TSO
;
3064 dev
->features
|= NETIF_F_HIGHDMA
;
3065 dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
;
3067 #ifdef SKY2_VLAN_TAG_USED
3068 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3069 dev
->vlan_rx_register
= sky2_vlan_rx_register
;
3070 dev
->vlan_rx_kill_vid
= sky2_vlan_rx_kill_vid
;
3073 /* read the mac address */
3074 memcpy_fromio(dev
->dev_addr
, hw
->regs
+ B2_MAC_1
+ port
* 8, ETH_ALEN
);
3075 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3077 /* device is off until link detection */
3078 netif_carrier_off(dev
);
3079 netif_stop_queue(dev
);
3084 static void __devinit
sky2_show_addr(struct net_device
*dev
)
3086 const struct sky2_port
*sky2
= netdev_priv(dev
);
3088 if (netif_msg_probe(sky2
))
3089 printk(KERN_INFO PFX
"%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3091 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
3092 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
3095 /* Handle software interrupt used during MSI test */
3096 static irqreturn_t __devinit
sky2_test_intr(int irq
, void *dev_id
,
3097 struct pt_regs
*regs
)
3099 struct sky2_hw
*hw
= dev_id
;
3100 u32 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
3105 if (status
& Y2_IS_IRQ_SW
) {
3106 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3109 sky2_write32(hw
, B0_Y2_SP_ICR
, 2);
3111 sky2_read32(hw
, B0_IMSK
);
3115 /* Test interrupt path by forcing a a software IRQ */
3116 static int __devinit
sky2_test_msi(struct sky2_hw
*hw
)
3118 struct pci_dev
*pdev
= hw
->pdev
;
3121 sky2_write32(hw
, B0_IMSK
, Y2_IS_IRQ_SW
);
3123 err
= request_irq(pdev
->irq
, sky2_test_intr
, SA_SHIRQ
, DRV_NAME
, hw
);
3125 printk(KERN_ERR PFX
"%s: cannot assign irq %d\n",
3126 pci_name(pdev
), pdev
->irq
);
3130 sky2_write8(hw
, B0_CTST
, CS_ST_SW_IRQ
);
3133 for (i
= 0; i
< 10; i
++) {
3141 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3143 sky2_write32(hw
, B0_IMSK
, 0);
3145 free_irq(pdev
->irq
, hw
);
3150 static int __devinit
sky2_probe(struct pci_dev
*pdev
,
3151 const struct pci_device_id
*ent
)
3153 struct net_device
*dev
, *dev1
= NULL
;
3155 int err
, pm_cap
, using_dac
= 0;
3157 err
= pci_enable_device(pdev
);
3159 printk(KERN_ERR PFX
"%s cannot enable PCI device\n",
3164 err
= pci_request_regions(pdev
, DRV_NAME
);
3166 printk(KERN_ERR PFX
"%s cannot obtain PCI resources\n",
3171 pci_set_master(pdev
);
3173 /* Find power-management capability. */
3174 pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
3176 printk(KERN_ERR PFX
"Cannot find PowerManagement capability, "
3179 goto err_out_free_regions
;
3182 if (sizeof(dma_addr_t
) > sizeof(u32
) &&
3183 !(err
= pci_set_dma_mask(pdev
, DMA_64BIT_MASK
))) {
3185 err
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
3187 printk(KERN_ERR PFX
"%s unable to obtain 64 bit DMA "
3188 "for consistent allocations\n", pci_name(pdev
));
3189 goto err_out_free_regions
;
3193 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
3195 printk(KERN_ERR PFX
"%s no usable DMA configuration\n",
3197 goto err_out_free_regions
;
3202 /* byte swap descriptors in hardware */
3206 pci_read_config_dword(pdev
, PCI_DEV_REG2
, ®
);
3207 reg
|= PCI_REV_DESC
;
3208 pci_write_config_dword(pdev
, PCI_DEV_REG2
, reg
);
3213 hw
= kzalloc(sizeof(*hw
), GFP_KERNEL
);
3215 printk(KERN_ERR PFX
"%s: cannot allocate hardware struct\n",
3217 goto err_out_free_regions
;
3222 hw
->regs
= ioremap_nocache(pci_resource_start(pdev
, 0), 0x4000);
3224 printk(KERN_ERR PFX
"%s: cannot map device registers\n",
3226 goto err_out_free_hw
;
3228 hw
->pm_cap
= pm_cap
;
3230 /* ring for status responses */
3231 hw
->st_le
= pci_alloc_consistent(hw
->pdev
, STATUS_LE_BYTES
,
3234 goto err_out_iounmap
;
3236 err
= sky2_reset(hw
);
3238 goto err_out_iounmap
;
3240 printk(KERN_INFO PFX
"v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3241 DRV_VERSION
, pci_resource_start(pdev
, 0), pdev
->irq
,
3242 yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
3243 hw
->chip_id
, hw
->chip_rev
);
3245 dev
= sky2_init_netdev(hw
, 0, using_dac
);
3247 goto err_out_free_pci
;
3249 err
= register_netdev(dev
);
3251 printk(KERN_ERR PFX
"%s: cannot register net device\n",
3253 goto err_out_free_netdev
;
3256 sky2_show_addr(dev
);
3258 if (hw
->ports
> 1 && (dev1
= sky2_init_netdev(hw
, 1, using_dac
))) {
3259 if (register_netdev(dev1
) == 0)
3260 sky2_show_addr(dev1
);
3262 /* Failure to register second port need not be fatal */
3263 printk(KERN_WARNING PFX
3264 "register of second port failed\n");
3270 if (!disable_msi
&& pci_enable_msi(pdev
) == 0) {
3271 err
= sky2_test_msi(hw
);
3272 if (err
== -EOPNOTSUPP
) {
3273 /* MSI test failed, go back to INTx mode */
3274 printk(KERN_WARNING PFX
"%s: No interrupt was generated using MSI, "
3275 "switching to INTx mode. Please report this failure to "
3276 "the PCI maintainer and include system chipset information.\n",
3278 pci_disable_msi(pdev
);
3281 goto err_out_unregister
;
3284 err
= request_irq(pdev
->irq
, sky2_intr
, SA_SHIRQ
| SA_SAMPLE_RANDOM
,
3287 printk(KERN_ERR PFX
"%s: cannot assign irq %d\n",
3288 pci_name(pdev
), pdev
->irq
);
3289 goto err_out_unregister
;
3292 hw
->intr_mask
= Y2_IS_BASE
;
3293 sky2_write32(hw
, B0_IMSK
, hw
->intr_mask
);
3295 pci_set_drvdata(pdev
, hw
);
3301 pci_disable_msi(pdev
);
3303 unregister_netdev(dev1
);
3306 unregister_netdev(dev
);
3307 err_out_free_netdev
:
3310 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3311 pci_free_consistent(hw
->pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
3316 err_out_free_regions
:
3317 pci_release_regions(pdev
);
3318 pci_disable_device(pdev
);
3323 static void __devexit
sky2_remove(struct pci_dev
*pdev
)
3325 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3326 struct net_device
*dev0
, *dev1
;
3334 unregister_netdev(dev1
);
3335 unregister_netdev(dev0
);
3337 sky2_write32(hw
, B0_IMSK
, 0);
3338 sky2_set_power_state(hw
, PCI_D3hot
);
3339 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
3340 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3341 sky2_read8(hw
, B0_CTST
);
3343 free_irq(pdev
->irq
, hw
);
3345 pci_disable_msi(pdev
);
3346 pci_free_consistent(pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
3347 pci_release_regions(pdev
);
3348 pci_disable_device(pdev
);
3356 pci_set_drvdata(pdev
, NULL
);
3360 static int sky2_suspend(struct pci_dev
*pdev
, pm_message_t state
)
3362 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3365 for (i
= 0; i
< 2; i
++) {
3366 struct net_device
*dev
= hw
->dev
[i
];
3369 if (!netif_running(dev
))
3373 netif_device_detach(dev
);
3377 return sky2_set_power_state(hw
, pci_choose_state(pdev
, state
));
3380 static int sky2_resume(struct pci_dev
*pdev
)
3382 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3385 pci_restore_state(pdev
);
3386 pci_enable_wake(pdev
, PCI_D0
, 0);
3387 err
= sky2_set_power_state(hw
, PCI_D0
);
3391 err
= sky2_reset(hw
);
3395 for (i
= 0; i
< 2; i
++) {
3396 struct net_device
*dev
= hw
->dev
[i
];
3397 if (dev
&& netif_running(dev
)) {
3398 netif_device_attach(dev
);
3401 printk(KERN_ERR PFX
"%s: could not up: %d\n",
3413 static struct pci_driver sky2_driver
= {
3415 .id_table
= sky2_id_table
,
3416 .probe
= sky2_probe
,
3417 .remove
= __devexit_p(sky2_remove
),
3419 .suspend
= sky2_suspend
,
3420 .resume
= sky2_resume
,
3424 static int __init
sky2_init_module(void)
3426 return pci_register_driver(&sky2_driver
);
3429 static void __exit
sky2_cleanup_module(void)
3431 pci_unregister_driver(&sky2_driver
);
3434 module_init(sky2_init_module
);
3435 module_exit(sky2_cleanup_module
);
3437 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3438 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3439 MODULE_LICENSE("GPL");
3440 MODULE_VERSION(DRV_VERSION
);