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sky2: not random enough
[deliverable/linux.git] / drivers / net / sky2.c
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26 #include <linux/config.h>
27 #include <linux/crc32.h>
28 #include <linux/kernel.h>
29 #include <linux/version.h>
30 #include <linux/module.h>
31 #include <linux/netdevice.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/etherdevice.h>
34 #include <linux/ethtool.h>
35 #include <linux/pci.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/in.h>
39 #include <linux/delay.h>
40 #include <linux/workqueue.h>
41 #include <linux/if_vlan.h>
42 #include <linux/prefetch.h>
43 #include <linux/mii.h>
44
45 #include <asm/irq.h>
46
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
49 #endif
50
51 #include "sky2.h"
52
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "0.15"
55 #define PFX DRV_NAME " "
56
57 /*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
60 * similar to Tigon3. A transmit can require several elements;
61 * a receive requires one (or two if using 64 bit dma).
62 */
63
64 #define is_ec_a1(hw) \
65 unlikely((hw)->chip_id == CHIP_ID_YUKON_EC && \
66 (hw)->chip_rev == CHIP_REV_YU_EC_A1)
67
68 #define RX_LE_SIZE 512
69 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
70 #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
71 #define RX_DEF_PENDING RX_MAX_PENDING
72 #define RX_SKB_ALIGN 8
73
74 #define TX_RING_SIZE 512
75 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
76 #define TX_MIN_PENDING 64
77 #define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS)
78
79 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
80 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
81 #define ETH_JUMBO_MTU 9000
82 #define TX_WATCHDOG (5 * HZ)
83 #define NAPI_WEIGHT 64
84 #define PHY_RETRIES 1000
85
86 static const u32 default_msg =
87 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
88 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
89 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
90
91 static int debug = -1; /* defaults above */
92 module_param(debug, int, 0);
93 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
94
95 static int copybreak __read_mostly = 256;
96 module_param(copybreak, int, 0);
97 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
98
99 static const struct pci_device_id sky2_id_table[] = {
100 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
102 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
103 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
104 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
105 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
106 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
119 { 0 }
120 };
121
122 MODULE_DEVICE_TABLE(pci, sky2_id_table);
123
124 /* Avoid conditionals by using array */
125 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
126 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
127
128 /* This driver supports yukon2 chipset only */
129 static const char *yukon2_name[] = {
130 "XL", /* 0xb3 */
131 "EC Ultra", /* 0xb4 */
132 "UNKNOWN", /* 0xb5 */
133 "EC", /* 0xb6 */
134 "FE", /* 0xb7 */
135 };
136
137 /* Access to external PHY */
138 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
139 {
140 int i;
141
142 gma_write16(hw, port, GM_SMI_DATA, val);
143 gma_write16(hw, port, GM_SMI_CTRL,
144 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
145
146 for (i = 0; i < PHY_RETRIES; i++) {
147 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
148 return 0;
149 udelay(1);
150 }
151
152 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
153 return -ETIMEDOUT;
154 }
155
156 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
157 {
158 int i;
159
160 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
161 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
162
163 for (i = 0; i < PHY_RETRIES; i++) {
164 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
165 *val = gma_read16(hw, port, GM_SMI_DATA);
166 return 0;
167 }
168
169 udelay(1);
170 }
171
172 return -ETIMEDOUT;
173 }
174
175 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
176 {
177 u16 v;
178
179 if (__gm_phy_read(hw, port, reg, &v) != 0)
180 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
181 return v;
182 }
183
184 static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
185 {
186 u16 power_control;
187 u32 reg1;
188 int vaux;
189 int ret = 0;
190
191 pr_debug("sky2_set_power_state %d\n", state);
192 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
193
194 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
195 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
196 (power_control & PCI_PM_CAP_PME_D3cold);
197
198 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
199
200 power_control |= PCI_PM_CTRL_PME_STATUS;
201 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
202
203 switch (state) {
204 case PCI_D0:
205 /* switch power to VCC (WA for VAUX problem) */
206 sky2_write8(hw, B0_POWER_CTRL,
207 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
208
209 /* disable Core Clock Division, */
210 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
211
212 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
213 /* enable bits are inverted */
214 sky2_write8(hw, B2_Y2_CLK_GATE,
215 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
216 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
217 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
218 else
219 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
220
221 /* Turn off phy power saving */
222 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
223 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
224
225 /* looks like this XL is back asswards .. */
226 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
227 reg1 |= PCI_Y2_PHY1_COMA;
228 if (hw->ports > 1)
229 reg1 |= PCI_Y2_PHY2_COMA;
230 }
231
232 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
233 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
234 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
235 reg1 &= P_ASPM_CONTROL_MSK;
236 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
237 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
238 }
239
240 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
241
242 break;
243
244 case PCI_D3hot:
245 case PCI_D3cold:
246 /* Turn on phy power saving */
247 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
248 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
249 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
250 else
251 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
252 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
253
254 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
255 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
256 else
257 /* enable bits are inverted */
258 sky2_write8(hw, B2_Y2_CLK_GATE,
259 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
260 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
261 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
262
263 /* switch power to VAUX */
264 if (vaux && state != PCI_D3cold)
265 sky2_write8(hw, B0_POWER_CTRL,
266 (PC_VAUX_ENA | PC_VCC_ENA |
267 PC_VAUX_ON | PC_VCC_OFF));
268 break;
269 default:
270 printk(KERN_ERR PFX "Unknown power state %d\n", state);
271 ret = -1;
272 }
273
274 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
275 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
276 return ret;
277 }
278
279 static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
280 {
281 u16 reg;
282
283 /* disable all GMAC IRQ's */
284 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
285 /* disable PHY IRQs */
286 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
287
288 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
289 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
290 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
291 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
292
293 reg = gma_read16(hw, port, GM_RX_CTRL);
294 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
295 gma_write16(hw, port, GM_RX_CTRL, reg);
296 }
297
298 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
299 {
300 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
301 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
302
303 if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
304 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
305
306 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
307 PHY_M_EC_MAC_S_MSK);
308 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
309
310 if (hw->chip_id == CHIP_ID_YUKON_EC)
311 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
312 else
313 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
314
315 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
316 }
317
318 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
319 if (hw->copper) {
320 if (hw->chip_id == CHIP_ID_YUKON_FE) {
321 /* enable automatic crossover */
322 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
323 } else {
324 /* disable energy detect */
325 ctrl &= ~PHY_M_PC_EN_DET_MSK;
326
327 /* enable automatic crossover */
328 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
329
330 if (sky2->autoneg == AUTONEG_ENABLE &&
331 hw->chip_id == CHIP_ID_YUKON_XL) {
332 ctrl &= ~PHY_M_PC_DSC_MSK;
333 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
334 }
335 }
336 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
337 } else {
338 /* workaround for deviation #4.88 (CRC errors) */
339 /* disable Automatic Crossover */
340
341 ctrl &= ~PHY_M_PC_MDIX_MSK;
342 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
343
344 if (hw->chip_id == CHIP_ID_YUKON_XL) {
345 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
346 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
347 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
348 ctrl &= ~PHY_M_MAC_MD_MSK;
349 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
350 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
351
352 /* select page 1 to access Fiber registers */
353 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
354 }
355 }
356
357 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
358 if (sky2->autoneg == AUTONEG_DISABLE)
359 ctrl &= ~PHY_CT_ANE;
360 else
361 ctrl |= PHY_CT_ANE;
362
363 ctrl |= PHY_CT_RESET;
364 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
365
366 ctrl = 0;
367 ct1000 = 0;
368 adv = PHY_AN_CSMA;
369
370 if (sky2->autoneg == AUTONEG_ENABLE) {
371 if (hw->copper) {
372 if (sky2->advertising & ADVERTISED_1000baseT_Full)
373 ct1000 |= PHY_M_1000C_AFD;
374 if (sky2->advertising & ADVERTISED_1000baseT_Half)
375 ct1000 |= PHY_M_1000C_AHD;
376 if (sky2->advertising & ADVERTISED_100baseT_Full)
377 adv |= PHY_M_AN_100_FD;
378 if (sky2->advertising & ADVERTISED_100baseT_Half)
379 adv |= PHY_M_AN_100_HD;
380 if (sky2->advertising & ADVERTISED_10baseT_Full)
381 adv |= PHY_M_AN_10_FD;
382 if (sky2->advertising & ADVERTISED_10baseT_Half)
383 adv |= PHY_M_AN_10_HD;
384 } else /* special defines for FIBER (88E1011S only) */
385 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
386
387 /* Set Flow-control capabilities */
388 if (sky2->tx_pause && sky2->rx_pause)
389 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
390 else if (sky2->rx_pause && !sky2->tx_pause)
391 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
392 else if (!sky2->rx_pause && sky2->tx_pause)
393 adv |= PHY_AN_PAUSE_ASYM; /* local */
394
395 /* Restart Auto-negotiation */
396 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
397 } else {
398 /* forced speed/duplex settings */
399 ct1000 = PHY_M_1000C_MSE;
400
401 if (sky2->duplex == DUPLEX_FULL)
402 ctrl |= PHY_CT_DUP_MD;
403
404 switch (sky2->speed) {
405 case SPEED_1000:
406 ctrl |= PHY_CT_SP1000;
407 break;
408 case SPEED_100:
409 ctrl |= PHY_CT_SP100;
410 break;
411 }
412
413 ctrl |= PHY_CT_RESET;
414 }
415
416 if (hw->chip_id != CHIP_ID_YUKON_FE)
417 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
418
419 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
420 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
421
422 /* Setup Phy LED's */
423 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
424 ledover = 0;
425
426 switch (hw->chip_id) {
427 case CHIP_ID_YUKON_FE:
428 /* on 88E3082 these bits are at 11..9 (shifted left) */
429 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
430
431 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
432
433 /* delete ACT LED control bits */
434 ctrl &= ~PHY_M_FELP_LED1_MSK;
435 /* change ACT LED control to blink mode */
436 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
437 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
438 break;
439
440 case CHIP_ID_YUKON_XL:
441 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
442
443 /* select page 3 to access LED control register */
444 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
445
446 /* set LED Function Control register */
447 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
448 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
449 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
450 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
451
452 /* set Polarity Control register */
453 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
454 (PHY_M_POLC_LS1_P_MIX(4) |
455 PHY_M_POLC_IS0_P_MIX(4) |
456 PHY_M_POLC_LOS_CTRL(2) |
457 PHY_M_POLC_INIT_CTRL(2) |
458 PHY_M_POLC_STA1_CTRL(2) |
459 PHY_M_POLC_STA0_CTRL(2)));
460
461 /* restore page register */
462 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
463 break;
464
465 default:
466 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
467 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
468 /* turn off the Rx LED (LED_RX) */
469 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
470 }
471
472 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
473 /* apply fixes in PHY AFE */
474 gm_phy_write(hw, port, 22, 255);
475 /* increase differential signal amplitude in 10BASE-T */
476 gm_phy_write(hw, port, 24, 0xaa99);
477 gm_phy_write(hw, port, 23, 0x2011);
478
479 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
480 gm_phy_write(hw, port, 24, 0xa204);
481 gm_phy_write(hw, port, 23, 0x2002);
482
483 /* set page register to 0 */
484 gm_phy_write(hw, port, 22, 0);
485 } else {
486 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
487
488 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
489 /* turn on 100 Mbps LED (LED_LINK100) */
490 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
491 }
492
493 if (ledover)
494 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
495
496 }
497 /* Enable phy interrupt on auto-negotiation complete (or link up) */
498 if (sky2->autoneg == AUTONEG_ENABLE)
499 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
500 else
501 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
502 }
503
504 /* Force a renegotiation */
505 static void sky2_phy_reinit(struct sky2_port *sky2)
506 {
507 down(&sky2->phy_sema);
508 sky2_phy_init(sky2->hw, sky2->port);
509 up(&sky2->phy_sema);
510 }
511
512 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
513 {
514 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
515 u16 reg;
516 int i;
517 const u8 *addr = hw->dev[port]->dev_addr;
518
519 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
520 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
521
522 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
523
524 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
525 /* WA DEV_472 -- looks like crossed wires on port 2 */
526 /* clear GMAC 1 Control reset */
527 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
528 do {
529 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
530 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
531 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
532 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
533 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
534 }
535
536 if (sky2->autoneg == AUTONEG_DISABLE) {
537 reg = gma_read16(hw, port, GM_GP_CTRL);
538 reg |= GM_GPCR_AU_ALL_DIS;
539 gma_write16(hw, port, GM_GP_CTRL, reg);
540 gma_read16(hw, port, GM_GP_CTRL);
541
542 switch (sky2->speed) {
543 case SPEED_1000:
544 reg &= ~GM_GPCR_SPEED_100;
545 reg |= GM_GPCR_SPEED_1000;
546 break;
547 case SPEED_100:
548 reg &= ~GM_GPCR_SPEED_1000;
549 reg |= GM_GPCR_SPEED_100;
550 break;
551 case SPEED_10:
552 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
553 break;
554 }
555
556 if (sky2->duplex == DUPLEX_FULL)
557 reg |= GM_GPCR_DUP_FULL;
558 } else
559 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
560
561 if (!sky2->tx_pause && !sky2->rx_pause) {
562 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
563 reg |=
564 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
565 } else if (sky2->tx_pause && !sky2->rx_pause) {
566 /* disable Rx flow-control */
567 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
568 }
569
570 gma_write16(hw, port, GM_GP_CTRL, reg);
571
572 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
573
574 down(&sky2->phy_sema);
575 sky2_phy_init(hw, port);
576 up(&sky2->phy_sema);
577
578 /* MIB clear */
579 reg = gma_read16(hw, port, GM_PHY_ADDR);
580 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
581
582 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
583 gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);
584 gma_write16(hw, port, GM_PHY_ADDR, reg);
585
586 /* transmit control */
587 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
588
589 /* receive control reg: unicast + multicast + no FCS */
590 gma_write16(hw, port, GM_RX_CTRL,
591 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
592
593 /* transmit flow control */
594 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
595
596 /* transmit parameter */
597 gma_write16(hw, port, GM_TX_PARAM,
598 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
599 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
600 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
601 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
602
603 /* serial mode register */
604 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
605 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
606
607 if (hw->dev[port]->mtu > ETH_DATA_LEN)
608 reg |= GM_SMOD_JUMBO_ENA;
609
610 gma_write16(hw, port, GM_SERIAL_MODE, reg);
611
612 /* virtual address for data */
613 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
614
615 /* physical address: used for pause frames */
616 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
617
618 /* ignore counter overflows */
619 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
620 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
621 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
622
623 /* Configure Rx MAC FIFO */
624 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
625 sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T),
626 GMF_RX_CTRL_DEF);
627
628 /* Flush Rx MAC FIFO on any flow control or error */
629 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
630
631 /* Set threshold to 0xa (64 bytes)
632 * ASF disabled so no need to do WA dev #4.30
633 */
634 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
635
636 /* Configure Tx MAC FIFO */
637 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
638 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
639
640 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
641 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
642 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
643 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
644 /* set Tx GMAC FIFO Almost Empty Threshold */
645 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
646 /* Disable Store & Forward mode for TX */
647 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
648 }
649 }
650
651 }
652
653 /* Assign Ram Buffer allocation.
654 * start and end are in units of 4k bytes
655 * ram registers are in units of 64bit words
656 */
657 static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
658 {
659 u32 start, end;
660
661 start = startk * 4096/8;
662 end = (endk * 4096/8) - 1;
663
664 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
665 sky2_write32(hw, RB_ADDR(q, RB_START), start);
666 sky2_write32(hw, RB_ADDR(q, RB_END), end);
667 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
668 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
669
670 if (q == Q_R1 || q == Q_R2) {
671 u32 space = (endk - startk) * 4096/8;
672 u32 tp = space - space/4;
673
674 /* On receive queue's set the thresholds
675 * give receiver priority when > 3/4 full
676 * send pause when down to 2K
677 */
678 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
679 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
680
681 tp = space - 2048/8;
682 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
683 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
684 } else {
685 /* Enable store & forward on Tx queue's because
686 * Tx FIFO is only 1K on Yukon
687 */
688 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
689 }
690
691 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
692 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
693 }
694
695 /* Setup Bus Memory Interface */
696 static void sky2_qset(struct sky2_hw *hw, u16 q)
697 {
698 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
699 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
700 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
701 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
702 }
703
704 /* Setup prefetch unit registers. This is the interface between
705 * hardware and driver list elements
706 */
707 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
708 u64 addr, u32 last)
709 {
710 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
711 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
712 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
713 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
714 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
715 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
716
717 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
718 }
719
720 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
721 {
722 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
723
724 sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
725 return le;
726 }
727
728 /*
729 * This is a workaround code taken from SysKonnect sk98lin driver
730 * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
731 */
732 static void sky2_put_idx(struct sky2_hw *hw, unsigned q,
733 u16 idx, u16 *last, u16 size)
734 {
735 wmb();
736 if (is_ec_a1(hw) && idx < *last) {
737 u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
738
739 if (hwget == 0) {
740 /* Start prefetching again */
741 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0);
742 goto setnew;
743 }
744
745 if (hwget == size - 1) {
746 /* set watermark to one list element */
747 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8);
748
749 /* set put index to first list element */
750 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0);
751 } else /* have hardware go to end of list */
752 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX),
753 size - 1);
754 } else {
755 setnew:
756 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
757 }
758 *last = idx;
759 mmiowb();
760 }
761
762
763 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
764 {
765 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
766 sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
767 return le;
768 }
769
770 /* Return high part of DMA address (could be 32 or 64 bit) */
771 static inline u32 high32(dma_addr_t a)
772 {
773 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
774 }
775
776 /* Build description to hardware about buffer */
777 static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
778 {
779 struct sky2_rx_le *le;
780 u32 hi = high32(map);
781 u16 len = sky2->rx_bufsize;
782
783 if (sky2->rx_addr64 != hi) {
784 le = sky2_next_rx(sky2);
785 le->addr = cpu_to_le32(hi);
786 le->ctrl = 0;
787 le->opcode = OP_ADDR64 | HW_OWNER;
788 sky2->rx_addr64 = high32(map + len);
789 }
790
791 le = sky2_next_rx(sky2);
792 le->addr = cpu_to_le32((u32) map);
793 le->length = cpu_to_le16(len);
794 le->ctrl = 0;
795 le->opcode = OP_PACKET | HW_OWNER;
796 }
797
798
799 /* Tell chip where to start receive checksum.
800 * Actually has two checksums, but set both same to avoid possible byte
801 * order problems.
802 */
803 static void rx_set_checksum(struct sky2_port *sky2)
804 {
805 struct sky2_rx_le *le;
806
807 le = sky2_next_rx(sky2);
808 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
809 le->ctrl = 0;
810 le->opcode = OP_TCPSTART | HW_OWNER;
811
812 sky2_write32(sky2->hw,
813 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
814 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
815
816 }
817
818 /*
819 * The RX Stop command will not work for Yukon-2 if the BMU does not
820 * reach the end of packet and since we can't make sure that we have
821 * incoming data, we must reset the BMU while it is not doing a DMA
822 * transfer. Since it is possible that the RX path is still active,
823 * the RX RAM buffer will be stopped first, so any possible incoming
824 * data will not trigger a DMA. After the RAM buffer is stopped, the
825 * BMU is polled until any DMA in progress is ended and only then it
826 * will be reset.
827 */
828 static void sky2_rx_stop(struct sky2_port *sky2)
829 {
830 struct sky2_hw *hw = sky2->hw;
831 unsigned rxq = rxqaddr[sky2->port];
832 int i;
833
834 /* disable the RAM Buffer receive queue */
835 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
836
837 for (i = 0; i < 0xffff; i++)
838 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
839 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
840 goto stopped;
841
842 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
843 sky2->netdev->name);
844 stopped:
845 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
846
847 /* reset the Rx prefetch unit */
848 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
849 }
850
851 /* Clean out receive buffer area, assumes receiver hardware stopped */
852 static void sky2_rx_clean(struct sky2_port *sky2)
853 {
854 unsigned i;
855
856 memset(sky2->rx_le, 0, RX_LE_BYTES);
857 for (i = 0; i < sky2->rx_pending; i++) {
858 struct ring_info *re = sky2->rx_ring + i;
859
860 if (re->skb) {
861 pci_unmap_single(sky2->hw->pdev,
862 re->mapaddr, sky2->rx_bufsize,
863 PCI_DMA_FROMDEVICE);
864 kfree_skb(re->skb);
865 re->skb = NULL;
866 }
867 }
868 }
869
870 /* Basic MII support */
871 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
872 {
873 struct mii_ioctl_data *data = if_mii(ifr);
874 struct sky2_port *sky2 = netdev_priv(dev);
875 struct sky2_hw *hw = sky2->hw;
876 int err = -EOPNOTSUPP;
877
878 if (!netif_running(dev))
879 return -ENODEV; /* Phy still in reset */
880
881 switch(cmd) {
882 case SIOCGMIIPHY:
883 data->phy_id = PHY_ADDR_MARV;
884
885 /* fallthru */
886 case SIOCGMIIREG: {
887 u16 val = 0;
888
889 down(&sky2->phy_sema);
890 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
891 up(&sky2->phy_sema);
892
893 data->val_out = val;
894 break;
895 }
896
897 case SIOCSMIIREG:
898 if (!capable(CAP_NET_ADMIN))
899 return -EPERM;
900
901 down(&sky2->phy_sema);
902 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
903 data->val_in);
904 up(&sky2->phy_sema);
905 break;
906 }
907 return err;
908 }
909
910 #ifdef SKY2_VLAN_TAG_USED
911 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
912 {
913 struct sky2_port *sky2 = netdev_priv(dev);
914 struct sky2_hw *hw = sky2->hw;
915 u16 port = sky2->port;
916
917 spin_lock_bh(&sky2->tx_lock);
918
919 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
920 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
921 sky2->vlgrp = grp;
922
923 spin_unlock_bh(&sky2->tx_lock);
924 }
925
926 static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
927 {
928 struct sky2_port *sky2 = netdev_priv(dev);
929 struct sky2_hw *hw = sky2->hw;
930 u16 port = sky2->port;
931
932 spin_lock_bh(&sky2->tx_lock);
933
934 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
935 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
936 if (sky2->vlgrp)
937 sky2->vlgrp->vlan_devices[vid] = NULL;
938
939 spin_unlock_bh(&sky2->tx_lock);
940 }
941 #endif
942
943 /*
944 * It appears the hardware has a bug in the FIFO logic that
945 * cause it to hang if the FIFO gets overrun and the receive buffer
946 * is not aligned. ALso alloc_skb() won't align properly if slab
947 * debugging is enabled.
948 */
949 static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)
950 {
951 struct sk_buff *skb;
952
953 skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);
954 if (likely(skb)) {
955 unsigned long p = (unsigned long) skb->data;
956 skb_reserve(skb,
957 ((p + RX_SKB_ALIGN - 1) & ~(RX_SKB_ALIGN - 1)) - p);
958 }
959
960 return skb;
961 }
962
963 /*
964 * Allocate and setup receiver buffer pool.
965 * In case of 64 bit dma, there are 2X as many list elements
966 * available as ring entries
967 * and need to reserve one list element so we don't wrap around.
968 */
969 static int sky2_rx_start(struct sky2_port *sky2)
970 {
971 struct sky2_hw *hw = sky2->hw;
972 unsigned rxq = rxqaddr[sky2->port];
973 int i;
974
975 sky2->rx_put = sky2->rx_next = 0;
976 sky2_qset(hw, rxq);
977
978 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
979 /* MAC Rx RAM Read is controlled by hardware */
980 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
981 }
982
983 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
984
985 rx_set_checksum(sky2);
986 for (i = 0; i < sky2->rx_pending; i++) {
987 struct ring_info *re = sky2->rx_ring + i;
988
989 re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);
990 if (!re->skb)
991 goto nomem;
992
993 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
994 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
995 sky2_rx_add(sky2, re->mapaddr);
996 }
997
998 /* Tell chip about available buffers */
999 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
1000 sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX));
1001 return 0;
1002 nomem:
1003 sky2_rx_clean(sky2);
1004 return -ENOMEM;
1005 }
1006
1007 /* Bring up network interface. */
1008 static int sky2_up(struct net_device *dev)
1009 {
1010 struct sky2_port *sky2 = netdev_priv(dev);
1011 struct sky2_hw *hw = sky2->hw;
1012 unsigned port = sky2->port;
1013 u32 ramsize, rxspace;
1014 int err = -ENOMEM;
1015
1016 if (netif_msg_ifup(sky2))
1017 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1018
1019 /* must be power of 2 */
1020 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1021 TX_RING_SIZE *
1022 sizeof(struct sky2_tx_le),
1023 &sky2->tx_le_map);
1024 if (!sky2->tx_le)
1025 goto err_out;
1026
1027 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1028 GFP_KERNEL);
1029 if (!sky2->tx_ring)
1030 goto err_out;
1031 sky2->tx_prod = sky2->tx_cons = 0;
1032
1033 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1034 &sky2->rx_le_map);
1035 if (!sky2->rx_le)
1036 goto err_out;
1037 memset(sky2->rx_le, 0, RX_LE_BYTES);
1038
1039 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
1040 GFP_KERNEL);
1041 if (!sky2->rx_ring)
1042 goto err_out;
1043
1044 sky2_mac_init(hw, port);
1045
1046 /* Determine available ram buffer space (in 4K blocks).
1047 * Note: not sure about the FE setting below yet
1048 */
1049 if (hw->chip_id == CHIP_ID_YUKON_FE)
1050 ramsize = 4;
1051 else
1052 ramsize = sky2_read8(hw, B2_E_0);
1053
1054 /* Give transmitter one third (rounded up) */
1055 rxspace = ramsize - (ramsize + 2) / 3;
1056
1057 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1058 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
1059
1060 /* Make sure SyncQ is disabled */
1061 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1062 RB_RST_SET);
1063
1064 sky2_qset(hw, txqaddr[port]);
1065
1066 /* Set almost empty threshold */
1067 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)
1068 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1069
1070 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1071 TX_RING_SIZE - 1);
1072
1073 err = sky2_rx_start(sky2);
1074 if (err)
1075 goto err_out;
1076
1077 /* Enable interrupts from phy/mac for port */
1078 spin_lock_irq(&hw->hw_lock);
1079 hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
1080 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1081 spin_unlock_irq(&hw->hw_lock);
1082 return 0;
1083
1084 err_out:
1085 if (sky2->rx_le) {
1086 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1087 sky2->rx_le, sky2->rx_le_map);
1088 sky2->rx_le = NULL;
1089 }
1090 if (sky2->tx_le) {
1091 pci_free_consistent(hw->pdev,
1092 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1093 sky2->tx_le, sky2->tx_le_map);
1094 sky2->tx_le = NULL;
1095 }
1096 kfree(sky2->tx_ring);
1097 kfree(sky2->rx_ring);
1098
1099 sky2->tx_ring = NULL;
1100 sky2->rx_ring = NULL;
1101 return err;
1102 }
1103
1104 /* Modular subtraction in ring */
1105 static inline int tx_dist(unsigned tail, unsigned head)
1106 {
1107 return (head - tail) % TX_RING_SIZE;
1108 }
1109
1110 /* Number of list elements available for next tx */
1111 static inline int tx_avail(const struct sky2_port *sky2)
1112 {
1113 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1114 }
1115
1116 /* Estimate of number of transmit list elements required */
1117 static unsigned tx_le_req(const struct sk_buff *skb)
1118 {
1119 unsigned count;
1120
1121 count = sizeof(dma_addr_t) / sizeof(u32);
1122 count += skb_shinfo(skb)->nr_frags * count;
1123
1124 if (skb_shinfo(skb)->tso_size)
1125 ++count;
1126
1127 if (skb->ip_summed == CHECKSUM_HW)
1128 ++count;
1129
1130 return count;
1131 }
1132
1133 /*
1134 * Put one packet in ring for transmit.
1135 * A single packet can generate multiple list elements, and
1136 * the number of ring elements will probably be less than the number
1137 * of list elements used.
1138 *
1139 * No BH disabling for tx_lock here (like tg3)
1140 */
1141 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1142 {
1143 struct sky2_port *sky2 = netdev_priv(dev);
1144 struct sky2_hw *hw = sky2->hw;
1145 struct sky2_tx_le *le = NULL;
1146 struct tx_ring_info *re;
1147 unsigned i, len;
1148 dma_addr_t mapping;
1149 u32 addr64;
1150 u16 mss;
1151 u8 ctrl;
1152
1153 /* No BH disabling for tx_lock here. We are running in BH disabled
1154 * context and TX reclaim runs via poll inside of a software
1155 * interrupt, and no related locks in IRQ processing.
1156 */
1157 if (!spin_trylock(&sky2->tx_lock))
1158 return NETDEV_TX_LOCKED;
1159
1160 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
1161 /* There is a known but harmless race with lockless tx
1162 * and netif_stop_queue.
1163 */
1164 if (!netif_queue_stopped(dev)) {
1165 netif_stop_queue(dev);
1166 if (net_ratelimit())
1167 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1168 dev->name);
1169 }
1170 spin_unlock(&sky2->tx_lock);
1171
1172 return NETDEV_TX_BUSY;
1173 }
1174
1175 if (unlikely(netif_msg_tx_queued(sky2)))
1176 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1177 dev->name, sky2->tx_prod, skb->len);
1178
1179 len = skb_headlen(skb);
1180 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1181 addr64 = high32(mapping);
1182
1183 re = sky2->tx_ring + sky2->tx_prod;
1184
1185 /* Send high bits if changed or crosses boundary */
1186 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
1187 le = get_tx_le(sky2);
1188 le->tx.addr = cpu_to_le32(addr64);
1189 le->ctrl = 0;
1190 le->opcode = OP_ADDR64 | HW_OWNER;
1191 sky2->tx_addr64 = high32(mapping + len);
1192 }
1193
1194 /* Check for TCP Segmentation Offload */
1195 mss = skb_shinfo(skb)->tso_size;
1196 if (mss != 0) {
1197 /* just drop the packet if non-linear expansion fails */
1198 if (skb_header_cloned(skb) &&
1199 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
1200 dev_kfree_skb_any(skb);
1201 goto out_unlock;
1202 }
1203
1204 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1205 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1206 mss += ETH_HLEN;
1207 }
1208
1209 if (mss != sky2->tx_last_mss) {
1210 le = get_tx_le(sky2);
1211 le->tx.tso.size = cpu_to_le16(mss);
1212 le->tx.tso.rsvd = 0;
1213 le->opcode = OP_LRGLEN | HW_OWNER;
1214 le->ctrl = 0;
1215 sky2->tx_last_mss = mss;
1216 }
1217
1218 ctrl = 0;
1219 #ifdef SKY2_VLAN_TAG_USED
1220 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1221 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1222 if (!le) {
1223 le = get_tx_le(sky2);
1224 le->tx.addr = 0;
1225 le->opcode = OP_VLAN|HW_OWNER;
1226 le->ctrl = 0;
1227 } else
1228 le->opcode |= OP_VLAN;
1229 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1230 ctrl |= INS_VLAN;
1231 }
1232 #endif
1233
1234 /* Handle TCP checksum offload */
1235 if (skb->ip_summed == CHECKSUM_HW) {
1236 u16 hdr = skb->h.raw - skb->data;
1237 u16 offset = hdr + skb->csum;
1238
1239 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1240 if (skb->nh.iph->protocol == IPPROTO_UDP)
1241 ctrl |= UDPTCP;
1242
1243 le = get_tx_le(sky2);
1244 le->tx.csum.start = cpu_to_le16(hdr);
1245 le->tx.csum.offset = cpu_to_le16(offset);
1246 le->length = 0; /* initial checksum value */
1247 le->ctrl = 1; /* one packet */
1248 le->opcode = OP_TCPLISW | HW_OWNER;
1249 }
1250
1251 le = get_tx_le(sky2);
1252 le->tx.addr = cpu_to_le32((u32) mapping);
1253 le->length = cpu_to_le16(len);
1254 le->ctrl = ctrl;
1255 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1256
1257 /* Record the transmit mapping info */
1258 re->skb = skb;
1259 pci_unmap_addr_set(re, mapaddr, mapping);
1260
1261 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1262 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1263 struct tx_ring_info *fre;
1264
1265 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1266 frag->size, PCI_DMA_TODEVICE);
1267 addr64 = high32(mapping);
1268 if (addr64 != sky2->tx_addr64) {
1269 le = get_tx_le(sky2);
1270 le->tx.addr = cpu_to_le32(addr64);
1271 le->ctrl = 0;
1272 le->opcode = OP_ADDR64 | HW_OWNER;
1273 sky2->tx_addr64 = addr64;
1274 }
1275
1276 le = get_tx_le(sky2);
1277 le->tx.addr = cpu_to_le32((u32) mapping);
1278 le->length = cpu_to_le16(frag->size);
1279 le->ctrl = ctrl;
1280 le->opcode = OP_BUFFER | HW_OWNER;
1281
1282 fre = sky2->tx_ring
1283 + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
1284 pci_unmap_addr_set(fre, mapaddr, mapping);
1285 }
1286
1287 re->idx = sky2->tx_prod;
1288 le->ctrl |= EOP;
1289
1290 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod,
1291 &sky2->tx_last_put, TX_RING_SIZE);
1292
1293 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1294 netif_stop_queue(dev);
1295
1296 out_unlock:
1297 spin_unlock(&sky2->tx_lock);
1298
1299 dev->trans_start = jiffies;
1300 return NETDEV_TX_OK;
1301 }
1302
1303 /*
1304 * Free ring elements from starting at tx_cons until "done"
1305 *
1306 * NB: the hardware will tell us about partial completion of multi-part
1307 * buffers; these are deferred until completion.
1308 */
1309 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1310 {
1311 struct net_device *dev = sky2->netdev;
1312 struct pci_dev *pdev = sky2->hw->pdev;
1313 u16 nxt, put;
1314 unsigned i;
1315
1316 BUG_ON(done >= TX_RING_SIZE);
1317
1318 if (unlikely(netif_msg_tx_done(sky2)))
1319 printk(KERN_DEBUG "%s: tx done, up to %u\n",
1320 dev->name, done);
1321
1322 for (put = sky2->tx_cons; put != done; put = nxt) {
1323 struct tx_ring_info *re = sky2->tx_ring + put;
1324 struct sk_buff *skb = re->skb;
1325
1326 nxt = re->idx;
1327 BUG_ON(nxt >= TX_RING_SIZE);
1328 prefetch(sky2->tx_ring + nxt);
1329
1330 /* Check for partial status */
1331 if (tx_dist(put, done) < tx_dist(put, nxt))
1332 break;
1333
1334 skb = re->skb;
1335 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1336 skb_headlen(skb), PCI_DMA_TODEVICE);
1337
1338 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1339 struct tx_ring_info *fre;
1340 fre = sky2->tx_ring + (put + i + 1) % TX_RING_SIZE;
1341 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
1342 skb_shinfo(skb)->frags[i].size,
1343 PCI_DMA_TODEVICE);
1344 }
1345
1346 dev_kfree_skb_any(skb);
1347 }
1348
1349 sky2->tx_cons = put;
1350 if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)
1351 netif_wake_queue(dev);
1352 }
1353
1354 /* Cleanup all untransmitted buffers, assume transmitter not running */
1355 static void sky2_tx_clean(struct sky2_port *sky2)
1356 {
1357 spin_lock_bh(&sky2->tx_lock);
1358 sky2_tx_complete(sky2, sky2->tx_prod);
1359 spin_unlock_bh(&sky2->tx_lock);
1360 }
1361
1362 /* Network shutdown */
1363 static int sky2_down(struct net_device *dev)
1364 {
1365 struct sky2_port *sky2 = netdev_priv(dev);
1366 struct sky2_hw *hw = sky2->hw;
1367 unsigned port = sky2->port;
1368 u16 ctrl;
1369
1370 /* Never really got started! */
1371 if (!sky2->tx_le)
1372 return 0;
1373
1374 if (netif_msg_ifdown(sky2))
1375 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1376
1377 /* Stop more packets from being queued */
1378 netif_stop_queue(dev);
1379
1380 /* Disable port IRQ */
1381 spin_lock_irq(&hw->hw_lock);
1382 hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1383 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1384 spin_unlock_irq(&hw->hw_lock);
1385
1386 flush_scheduled_work();
1387
1388 sky2_phy_reset(hw, port);
1389
1390 /* Stop transmitter */
1391 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1392 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1393
1394 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1395 RB_RST_SET | RB_DIS_OP_MD);
1396
1397 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1398 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1399 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1400
1401 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1402
1403 /* Workaround shared GMAC reset */
1404 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1405 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1406 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1407
1408 /* Disable Force Sync bit and Enable Alloc bit */
1409 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1410 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1411
1412 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1413 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1414 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1415
1416 /* Reset the PCI FIFO of the async Tx queue */
1417 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1418 BMU_RST_SET | BMU_FIFO_RST);
1419
1420 /* Reset the Tx prefetch units */
1421 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1422 PREF_UNIT_RST_SET);
1423
1424 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1425
1426 sky2_rx_stop(sky2);
1427
1428 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1429 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1430
1431 /* turn off LED's */
1432 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1433
1434 synchronize_irq(hw->pdev->irq);
1435
1436 sky2_tx_clean(sky2);
1437 sky2_rx_clean(sky2);
1438
1439 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1440 sky2->rx_le, sky2->rx_le_map);
1441 kfree(sky2->rx_ring);
1442
1443 pci_free_consistent(hw->pdev,
1444 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1445 sky2->tx_le, sky2->tx_le_map);
1446 kfree(sky2->tx_ring);
1447
1448 sky2->tx_le = NULL;
1449 sky2->rx_le = NULL;
1450
1451 sky2->rx_ring = NULL;
1452 sky2->tx_ring = NULL;
1453
1454 return 0;
1455 }
1456
1457 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1458 {
1459 if (!hw->copper)
1460 return SPEED_1000;
1461
1462 if (hw->chip_id == CHIP_ID_YUKON_FE)
1463 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1464
1465 switch (aux & PHY_M_PS_SPEED_MSK) {
1466 case PHY_M_PS_SPEED_1000:
1467 return SPEED_1000;
1468 case PHY_M_PS_SPEED_100:
1469 return SPEED_100;
1470 default:
1471 return SPEED_10;
1472 }
1473 }
1474
1475 static void sky2_link_up(struct sky2_port *sky2)
1476 {
1477 struct sky2_hw *hw = sky2->hw;
1478 unsigned port = sky2->port;
1479 u16 reg;
1480
1481 /* Enable Transmit FIFO Underrun */
1482 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1483
1484 reg = gma_read16(hw, port, GM_GP_CTRL);
1485 if (sky2->autoneg == AUTONEG_DISABLE) {
1486 reg |= GM_GPCR_AU_ALL_DIS;
1487
1488 /* Is write/read necessary? Copied from sky2_mac_init */
1489 gma_write16(hw, port, GM_GP_CTRL, reg);
1490 gma_read16(hw, port, GM_GP_CTRL);
1491
1492 switch (sky2->speed) {
1493 case SPEED_1000:
1494 reg &= ~GM_GPCR_SPEED_100;
1495 reg |= GM_GPCR_SPEED_1000;
1496 break;
1497 case SPEED_100:
1498 reg &= ~GM_GPCR_SPEED_1000;
1499 reg |= GM_GPCR_SPEED_100;
1500 break;
1501 case SPEED_10:
1502 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1503 break;
1504 }
1505 } else
1506 reg &= ~GM_GPCR_AU_ALL_DIS;
1507
1508 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1509 reg |= GM_GPCR_DUP_FULL;
1510
1511 /* enable Rx/Tx */
1512 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1513 gma_write16(hw, port, GM_GP_CTRL, reg);
1514 gma_read16(hw, port, GM_GP_CTRL);
1515
1516 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1517
1518 netif_carrier_on(sky2->netdev);
1519 netif_wake_queue(sky2->netdev);
1520
1521 /* Turn on link LED */
1522 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1523 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1524
1525 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1526 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1527
1528 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1529 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1530 PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1531 SPEED_10 ? 7 : 0) |
1532 PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1533 SPEED_100 ? 7 : 0) |
1534 PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1535 SPEED_1000 ? 7 : 0));
1536 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1537 }
1538
1539 if (netif_msg_link(sky2))
1540 printk(KERN_INFO PFX
1541 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1542 sky2->netdev->name, sky2->speed,
1543 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1544 (sky2->tx_pause && sky2->rx_pause) ? "both" :
1545 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
1546 }
1547
1548 static void sky2_link_down(struct sky2_port *sky2)
1549 {
1550 struct sky2_hw *hw = sky2->hw;
1551 unsigned port = sky2->port;
1552 u16 reg;
1553
1554 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1555
1556 reg = gma_read16(hw, port, GM_GP_CTRL);
1557 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1558 gma_write16(hw, port, GM_GP_CTRL, reg);
1559 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1560
1561 if (sky2->rx_pause && !sky2->tx_pause) {
1562 /* restore Asymmetric Pause bit */
1563 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1564 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1565 | PHY_M_AN_ASP);
1566 }
1567
1568 netif_carrier_off(sky2->netdev);
1569 netif_stop_queue(sky2->netdev);
1570
1571 /* Turn on link LED */
1572 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1573
1574 if (netif_msg_link(sky2))
1575 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1576 sky2_phy_init(hw, port);
1577 }
1578
1579 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1580 {
1581 struct sky2_hw *hw = sky2->hw;
1582 unsigned port = sky2->port;
1583 u16 lpa;
1584
1585 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1586
1587 if (lpa & PHY_M_AN_RF) {
1588 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1589 return -1;
1590 }
1591
1592 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1593 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1594 printk(KERN_ERR PFX "%s: master/slave fault",
1595 sky2->netdev->name);
1596 return -1;
1597 }
1598
1599 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1600 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1601 sky2->netdev->name);
1602 return -1;
1603 }
1604
1605 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1606
1607 sky2->speed = sky2_phy_speed(hw, aux);
1608
1609 /* Pause bits are offset (9..8) */
1610 if (hw->chip_id == CHIP_ID_YUKON_XL)
1611 aux >>= 6;
1612
1613 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1614 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1615
1616 if ((sky2->tx_pause || sky2->rx_pause)
1617 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1618 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1619 else
1620 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1621
1622 return 0;
1623 }
1624
1625 /*
1626 * Interrupt from PHY are handled outside of interrupt context
1627 * because accessing phy registers requires spin wait which might
1628 * cause excess interrupt latency.
1629 */
1630 static void sky2_phy_task(void *arg)
1631 {
1632 struct sky2_port *sky2 = arg;
1633 struct sky2_hw *hw = sky2->hw;
1634 u16 istatus, phystat;
1635
1636 down(&sky2->phy_sema);
1637 istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);
1638 phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);
1639
1640 if (netif_msg_intr(sky2))
1641 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1642 sky2->netdev->name, istatus, phystat);
1643
1644 if (istatus & PHY_M_IS_AN_COMPL) {
1645 if (sky2_autoneg_done(sky2, phystat) == 0)
1646 sky2_link_up(sky2);
1647 goto out;
1648 }
1649
1650 if (istatus & PHY_M_IS_LSP_CHANGE)
1651 sky2->speed = sky2_phy_speed(hw, phystat);
1652
1653 if (istatus & PHY_M_IS_DUP_CHANGE)
1654 sky2->duplex =
1655 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1656
1657 if (istatus & PHY_M_IS_LST_CHANGE) {
1658 if (phystat & PHY_M_PS_LINK_UP)
1659 sky2_link_up(sky2);
1660 else
1661 sky2_link_down(sky2);
1662 }
1663 out:
1664 up(&sky2->phy_sema);
1665
1666 spin_lock_irq(&hw->hw_lock);
1667 hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
1668 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1669 spin_unlock_irq(&hw->hw_lock);
1670 }
1671
1672
1673 /* Transmit timeout is only called if we are running, carries is up
1674 * and tx queue is full (stopped).
1675 */
1676 static void sky2_tx_timeout(struct net_device *dev)
1677 {
1678 struct sky2_port *sky2 = netdev_priv(dev);
1679 struct sky2_hw *hw = sky2->hw;
1680 unsigned txq = txqaddr[sky2->port];
1681 u16 ridx;
1682
1683 /* Maybe we just missed an status interrupt */
1684 spin_lock(&sky2->tx_lock);
1685 ridx = sky2_read16(hw,
1686 sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1687 sky2_tx_complete(sky2, ridx);
1688 spin_unlock(&sky2->tx_lock);
1689
1690 if (!netif_queue_stopped(dev)) {
1691 if (net_ratelimit())
1692 pr_info(PFX "transmit interrupt missed? recovered\n");
1693 return;
1694 }
1695
1696 if (netif_msg_timer(sky2))
1697 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1698
1699 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1700 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1701
1702 sky2_tx_clean(sky2);
1703
1704 sky2_qset(hw, txq);
1705 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1706 }
1707
1708
1709 #define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
1710 /* Want receive buffer size to be multiple of 64 bits, and incl room for vlan */
1711 static inline unsigned sky2_buf_size(int mtu)
1712 {
1713 return roundup(mtu + ETH_HLEN + 4, 8);
1714 }
1715
1716 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1717 {
1718 struct sky2_port *sky2 = netdev_priv(dev);
1719 struct sky2_hw *hw = sky2->hw;
1720 int err;
1721 u16 ctl, mode;
1722
1723 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1724 return -EINVAL;
1725
1726 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1727 return -EINVAL;
1728
1729 if (!netif_running(dev)) {
1730 dev->mtu = new_mtu;
1731 return 0;
1732 }
1733
1734 sky2_write32(hw, B0_IMSK, 0);
1735
1736 dev->trans_start = jiffies; /* prevent tx timeout */
1737 netif_stop_queue(dev);
1738 netif_poll_disable(hw->dev[0]);
1739
1740 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1741 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1742 sky2_rx_stop(sky2);
1743 sky2_rx_clean(sky2);
1744
1745 dev->mtu = new_mtu;
1746 sky2->rx_bufsize = sky2_buf_size(new_mtu);
1747 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1748 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1749
1750 if (dev->mtu > ETH_DATA_LEN)
1751 mode |= GM_SMOD_JUMBO_ENA;
1752
1753 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1754
1755 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1756
1757 err = sky2_rx_start(sky2);
1758 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1759
1760 if (err)
1761 dev_close(dev);
1762 else {
1763 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1764
1765 netif_poll_enable(hw->dev[0]);
1766 netif_wake_queue(dev);
1767 }
1768
1769 return err;
1770 }
1771
1772 /*
1773 * Receive one packet.
1774 * For small packets or errors, just reuse existing skb.
1775 * For larger packets, get new buffer.
1776 */
1777 static struct sk_buff *sky2_receive(struct sky2_port *sky2,
1778 u16 length, u32 status)
1779 {
1780 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
1781 struct sk_buff *skb = NULL;
1782
1783 if (unlikely(netif_msg_rx_status(sky2)))
1784 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
1785 sky2->netdev->name, sky2->rx_next, status, length);
1786
1787 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
1788 prefetch(sky2->rx_ring + sky2->rx_next);
1789
1790 if (status & GMR_FS_ANY_ERR)
1791 goto error;
1792
1793 if (!(status & GMR_FS_RX_OK))
1794 goto resubmit;
1795
1796 if ((status >> 16) != length || length > sky2->rx_bufsize)
1797 goto oversize;
1798
1799 if (length < copybreak) {
1800 skb = alloc_skb(length + 2, GFP_ATOMIC);
1801 if (!skb)
1802 goto resubmit;
1803
1804 skb_reserve(skb, 2);
1805 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1806 length, PCI_DMA_FROMDEVICE);
1807 memcpy(skb->data, re->skb->data, length);
1808 skb->ip_summed = re->skb->ip_summed;
1809 skb->csum = re->skb->csum;
1810 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1811 length, PCI_DMA_FROMDEVICE);
1812 } else {
1813 struct sk_buff *nskb;
1814
1815 nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);
1816 if (!nskb)
1817 goto resubmit;
1818
1819 skb = re->skb;
1820 re->skb = nskb;
1821 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1822 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1823 prefetch(skb->data);
1824
1825 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
1826 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1827 }
1828
1829 skb_put(skb, length);
1830 resubmit:
1831 re->skb->ip_summed = CHECKSUM_NONE;
1832 sky2_rx_add(sky2, re->mapaddr);
1833
1834 /* Tell receiver about new buffers. */
1835 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put,
1836 &sky2->rx_last_put, RX_LE_SIZE);
1837
1838 return skb;
1839
1840 oversize:
1841 ++sky2->net_stats.rx_over_errors;
1842 goto resubmit;
1843
1844 error:
1845 ++sky2->net_stats.rx_errors;
1846
1847 if (netif_msg_rx_err(sky2) && net_ratelimit())
1848 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1849 sky2->netdev->name, status, length);
1850
1851 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
1852 sky2->net_stats.rx_length_errors++;
1853 if (status & GMR_FS_FRAGMENT)
1854 sky2->net_stats.rx_frame_errors++;
1855 if (status & GMR_FS_CRC_ERR)
1856 sky2->net_stats.rx_crc_errors++;
1857 if (status & GMR_FS_RX_FF_OV)
1858 sky2->net_stats.rx_fifo_errors++;
1859
1860 goto resubmit;
1861 }
1862
1863 /*
1864 * Check for transmit complete
1865 */
1866 #define TX_NO_STATUS 0xffff
1867
1868 static void sky2_tx_check(struct sky2_hw *hw, int port, u16 last)
1869 {
1870 if (last != TX_NO_STATUS) {
1871 struct net_device *dev = hw->dev[port];
1872 if (dev && netif_running(dev)) {
1873 struct sky2_port *sky2 = netdev_priv(dev);
1874
1875 spin_lock(&sky2->tx_lock);
1876 sky2_tx_complete(sky2, last);
1877 spin_unlock(&sky2->tx_lock);
1878 }
1879 }
1880 }
1881
1882 /*
1883 * Both ports share the same status interrupt, therefore there is only
1884 * one poll routine.
1885 */
1886 static int sky2_poll(struct net_device *dev0, int *budget)
1887 {
1888 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
1889 unsigned int to_do = min(dev0->quota, *budget);
1890 unsigned int work_done = 0;
1891 u16 hwidx;
1892 u16 tx_done[2] = { TX_NO_STATUS, TX_NO_STATUS };
1893
1894 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
1895
1896 /*
1897 * Kick the STAT_LEV_TIMER_CTRL timer.
1898 * This fixes my hangs on Yukon-EC (0xb6) rev 1.
1899 * The if clause is there to start the timer only if it has been
1900 * configured correctly and not been disabled via ethtool.
1901 */
1902 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_START) {
1903 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
1904 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
1905 }
1906
1907 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1908 BUG_ON(hwidx >= STATUS_RING_SIZE);
1909 rmb();
1910
1911 while (hwidx != hw->st_idx) {
1912 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1913 struct net_device *dev;
1914 struct sky2_port *sky2;
1915 struct sk_buff *skb;
1916 u32 status;
1917 u16 length;
1918
1919 le = hw->st_le + hw->st_idx;
1920 hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
1921 prefetch(hw->st_le + hw->st_idx);
1922
1923 BUG_ON(le->link >= 2);
1924 dev = hw->dev[le->link];
1925 if (dev == NULL || !netif_running(dev))
1926 continue;
1927
1928 sky2 = netdev_priv(dev);
1929 status = le32_to_cpu(le->status);
1930 length = le16_to_cpu(le->length);
1931
1932 switch (le->opcode & ~HW_OWNER) {
1933 case OP_RXSTAT:
1934 skb = sky2_receive(sky2, length, status);
1935 if (!skb)
1936 break;
1937
1938 skb->dev = dev;
1939 skb->protocol = eth_type_trans(skb, dev);
1940 dev->last_rx = jiffies;
1941
1942 #ifdef SKY2_VLAN_TAG_USED
1943 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1944 vlan_hwaccel_receive_skb(skb,
1945 sky2->vlgrp,
1946 be16_to_cpu(sky2->rx_tag));
1947 } else
1948 #endif
1949 netif_receive_skb(skb);
1950
1951 if (++work_done >= to_do)
1952 goto exit_loop;
1953 break;
1954
1955 #ifdef SKY2_VLAN_TAG_USED
1956 case OP_RXVLAN:
1957 sky2->rx_tag = length;
1958 break;
1959
1960 case OP_RXCHKSVLAN:
1961 sky2->rx_tag = length;
1962 /* fall through */
1963 #endif
1964 case OP_RXCHKS:
1965 skb = sky2->rx_ring[sky2->rx_next].skb;
1966 skb->ip_summed = CHECKSUM_HW;
1967 skb->csum = le16_to_cpu(status);
1968 break;
1969
1970 case OP_TXINDEXLE:
1971 /* TX index reports status for both ports */
1972 tx_done[0] = status & 0xffff;
1973 tx_done[1] = ((status >> 24) & 0xff)
1974 | (u16)(length & 0xf) << 8;
1975 break;
1976
1977 default:
1978 if (net_ratelimit())
1979 printk(KERN_WARNING PFX
1980 "unknown status opcode 0x%x\n", le->opcode);
1981 break;
1982 }
1983 }
1984
1985 exit_loop:
1986 sky2_tx_check(hw, 0, tx_done[0]);
1987 sky2_tx_check(hw, 1, tx_done[1]);
1988
1989 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
1990 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1991 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1992 }
1993
1994 if (likely(work_done < to_do)) {
1995 spin_lock_irq(&hw->hw_lock);
1996 __netif_rx_complete(dev0);
1997
1998 hw->intr_mask |= Y2_IS_STAT_BMU;
1999 sky2_write32(hw, B0_IMSK, hw->intr_mask);
2000 spin_unlock_irq(&hw->hw_lock);
2001
2002 return 0;
2003 } else {
2004 *budget -= work_done;
2005 dev0->quota -= work_done;
2006 return 1;
2007 }
2008 }
2009
2010 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2011 {
2012 struct net_device *dev = hw->dev[port];
2013
2014 if (net_ratelimit())
2015 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2016 dev->name, status);
2017
2018 if (status & Y2_IS_PAR_RD1) {
2019 if (net_ratelimit())
2020 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2021 dev->name);
2022 /* Clear IRQ */
2023 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2024 }
2025
2026 if (status & Y2_IS_PAR_WR1) {
2027 if (net_ratelimit())
2028 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2029 dev->name);
2030
2031 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2032 }
2033
2034 if (status & Y2_IS_PAR_MAC1) {
2035 if (net_ratelimit())
2036 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2037 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2038 }
2039
2040 if (status & Y2_IS_PAR_RX1) {
2041 if (net_ratelimit())
2042 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2043 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2044 }
2045
2046 if (status & Y2_IS_TCP_TXA1) {
2047 if (net_ratelimit())
2048 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2049 dev->name);
2050 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2051 }
2052 }
2053
2054 static void sky2_hw_intr(struct sky2_hw *hw)
2055 {
2056 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2057
2058 if (status & Y2_IS_TIST_OV)
2059 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2060
2061 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2062 u16 pci_err;
2063
2064 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2065 if (net_ratelimit())
2066 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2067 pci_name(hw->pdev), pci_err);
2068
2069 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2070 sky2_pci_write16(hw, PCI_STATUS,
2071 pci_err | PCI_STATUS_ERROR_BITS);
2072 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2073 }
2074
2075 if (status & Y2_IS_PCI_EXP) {
2076 /* PCI-Express uncorrectable Error occurred */
2077 u32 pex_err;
2078
2079 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
2080
2081 if (net_ratelimit())
2082 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2083 pci_name(hw->pdev), pex_err);
2084
2085 /* clear the interrupt */
2086 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2087 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2088 0xffffffffUL);
2089 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2090
2091 if (pex_err & PEX_FATAL_ERRORS) {
2092 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2093 hwmsk &= ~Y2_IS_PCI_EXP;
2094 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2095 }
2096 }
2097
2098 if (status & Y2_HWE_L1_MASK)
2099 sky2_hw_error(hw, 0, status);
2100 status >>= 8;
2101 if (status & Y2_HWE_L1_MASK)
2102 sky2_hw_error(hw, 1, status);
2103 }
2104
2105 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2106 {
2107 struct net_device *dev = hw->dev[port];
2108 struct sky2_port *sky2 = netdev_priv(dev);
2109 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2110
2111 if (netif_msg_intr(sky2))
2112 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2113 dev->name, status);
2114
2115 if (status & GM_IS_RX_FF_OR) {
2116 ++sky2->net_stats.rx_fifo_errors;
2117 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2118 }
2119
2120 if (status & GM_IS_TX_FF_UR) {
2121 ++sky2->net_stats.tx_fifo_errors;
2122 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2123 }
2124 }
2125
2126 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2127 {
2128 struct net_device *dev = hw->dev[port];
2129 struct sky2_port *sky2 = netdev_priv(dev);
2130
2131 hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
2132 sky2_write32(hw, B0_IMSK, hw->intr_mask);
2133
2134 schedule_work(&sky2->phy_task);
2135 }
2136
2137 static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2138 {
2139 struct sky2_hw *hw = dev_id;
2140 struct net_device *dev0 = hw->dev[0];
2141 u32 status;
2142
2143 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2144 if (status == 0 || status == ~0)
2145 return IRQ_NONE;
2146
2147 spin_lock(&hw->hw_lock);
2148 if (status & Y2_IS_HW_ERR)
2149 sky2_hw_intr(hw);
2150
2151 /* Do NAPI for Rx and Tx status */
2152 if (status & Y2_IS_STAT_BMU) {
2153 hw->intr_mask &= ~Y2_IS_STAT_BMU;
2154 sky2_write32(hw, B0_IMSK, hw->intr_mask);
2155
2156 if (likely(__netif_rx_schedule_prep(dev0))) {
2157 prefetch(&hw->st_le[hw->st_idx]);
2158 __netif_rx_schedule(dev0);
2159 }
2160 }
2161
2162 if (status & Y2_IS_IRQ_PHY1)
2163 sky2_phy_intr(hw, 0);
2164
2165 if (status & Y2_IS_IRQ_PHY2)
2166 sky2_phy_intr(hw, 1);
2167
2168 if (status & Y2_IS_IRQ_MAC1)
2169 sky2_mac_intr(hw, 0);
2170
2171 if (status & Y2_IS_IRQ_MAC2)
2172 sky2_mac_intr(hw, 1);
2173
2174 sky2_write32(hw, B0_Y2_SP_ICR, 2);
2175
2176 spin_unlock(&hw->hw_lock);
2177
2178 return IRQ_HANDLED;
2179 }
2180
2181 #ifdef CONFIG_NET_POLL_CONTROLLER
2182 static void sky2_netpoll(struct net_device *dev)
2183 {
2184 struct sky2_port *sky2 = netdev_priv(dev);
2185
2186 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
2187 }
2188 #endif
2189
2190 /* Chip internal frequency for clock calculations */
2191 static inline u32 sky2_mhz(const struct sky2_hw *hw)
2192 {
2193 switch (hw->chip_id) {
2194 case CHIP_ID_YUKON_EC:
2195 case CHIP_ID_YUKON_EC_U:
2196 return 125; /* 125 Mhz */
2197 case CHIP_ID_YUKON_FE:
2198 return 100; /* 100 Mhz */
2199 default: /* YUKON_XL */
2200 return 156; /* 156 Mhz */
2201 }
2202 }
2203
2204 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2205 {
2206 return sky2_mhz(hw) * us;
2207 }
2208
2209 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2210 {
2211 return clk / sky2_mhz(hw);
2212 }
2213
2214
2215 static int sky2_reset(struct sky2_hw *hw)
2216 {
2217 u16 status;
2218 u8 t8, pmd_type;
2219 int i;
2220
2221 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2222
2223 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2224 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2225 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2226 pci_name(hw->pdev), hw->chip_id);
2227 return -EOPNOTSUPP;
2228 }
2229
2230 /* disable ASF */
2231 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2232 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2233 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2234 }
2235
2236 /* do a SW reset */
2237 sky2_write8(hw, B0_CTST, CS_RST_SET);
2238 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2239
2240 /* clear PCI errors, if any */
2241 status = sky2_pci_read16(hw, PCI_STATUS);
2242
2243 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2244 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2245
2246
2247 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2248
2249 /* clear any PEX errors */
2250 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2251 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2252
2253
2254 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2255 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2256
2257 hw->ports = 1;
2258 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2259 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2260 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2261 ++hw->ports;
2262 }
2263 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2264
2265 sky2_set_power_state(hw, PCI_D0);
2266
2267 for (i = 0; i < hw->ports; i++) {
2268 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2269 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2270 }
2271
2272 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2273
2274 /* Clear I2C IRQ noise */
2275 sky2_write32(hw, B2_I2C_IRQ, 1);
2276
2277 /* turn off hardware timer (unused) */
2278 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2279 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2280
2281 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2282
2283 /* Turn off descriptor polling */
2284 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2285
2286 /* Turn off receive timestamp */
2287 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2288 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2289
2290 /* enable the Tx Arbiters */
2291 for (i = 0; i < hw->ports; i++)
2292 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2293
2294 /* Initialize ram interface */
2295 for (i = 0; i < hw->ports; i++) {
2296 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2297
2298 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2299 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2300 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2301 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2302 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2303 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2304 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2305 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2306 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2307 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2308 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2309 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2310 }
2311
2312 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2313
2314 for (i = 0; i < hw->ports; i++)
2315 sky2_phy_reset(hw, i);
2316
2317 memset(hw->st_le, 0, STATUS_LE_BYTES);
2318 hw->st_idx = 0;
2319
2320 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2321 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2322
2323 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2324 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2325
2326 /* Set the list last index */
2327 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2328
2329 /* These status setup values are copied from SysKonnect's driver */
2330 if (is_ec_a1(hw)) {
2331 /* WA for dev. #4.3 */
2332 sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */
2333
2334 /* set Status-FIFO watermark */
2335 sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */
2336
2337 /* set Status-FIFO ISR watermark */
2338 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */
2339 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 10000));
2340 } else {
2341 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2342 sky2_write8(hw, STAT_FIFO_WM, 16);
2343
2344 /* set Status-FIFO ISR watermark */
2345 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2346 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2347 else
2348 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2349
2350 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2351 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 7));
2352 }
2353
2354 /* enable status unit */
2355 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2356
2357 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2358 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2359 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2360
2361 return 0;
2362 }
2363
2364 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2365 {
2366 u32 modes;
2367 if (hw->copper) {
2368 modes = SUPPORTED_10baseT_Half
2369 | SUPPORTED_10baseT_Full
2370 | SUPPORTED_100baseT_Half
2371 | SUPPORTED_100baseT_Full
2372 | SUPPORTED_Autoneg | SUPPORTED_TP;
2373
2374 if (hw->chip_id != CHIP_ID_YUKON_FE)
2375 modes |= SUPPORTED_1000baseT_Half
2376 | SUPPORTED_1000baseT_Full;
2377 } else
2378 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
2379 | SUPPORTED_Autoneg;
2380 return modes;
2381 }
2382
2383 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2384 {
2385 struct sky2_port *sky2 = netdev_priv(dev);
2386 struct sky2_hw *hw = sky2->hw;
2387
2388 ecmd->transceiver = XCVR_INTERNAL;
2389 ecmd->supported = sky2_supported_modes(hw);
2390 ecmd->phy_address = PHY_ADDR_MARV;
2391 if (hw->copper) {
2392 ecmd->supported = SUPPORTED_10baseT_Half
2393 | SUPPORTED_10baseT_Full
2394 | SUPPORTED_100baseT_Half
2395 | SUPPORTED_100baseT_Full
2396 | SUPPORTED_1000baseT_Half
2397 | SUPPORTED_1000baseT_Full
2398 | SUPPORTED_Autoneg | SUPPORTED_TP;
2399 ecmd->port = PORT_TP;
2400 } else
2401 ecmd->port = PORT_FIBRE;
2402
2403 ecmd->advertising = sky2->advertising;
2404 ecmd->autoneg = sky2->autoneg;
2405 ecmd->speed = sky2->speed;
2406 ecmd->duplex = sky2->duplex;
2407 return 0;
2408 }
2409
2410 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2411 {
2412 struct sky2_port *sky2 = netdev_priv(dev);
2413 const struct sky2_hw *hw = sky2->hw;
2414 u32 supported = sky2_supported_modes(hw);
2415
2416 if (ecmd->autoneg == AUTONEG_ENABLE) {
2417 ecmd->advertising = supported;
2418 sky2->duplex = -1;
2419 sky2->speed = -1;
2420 } else {
2421 u32 setting;
2422
2423 switch (ecmd->speed) {
2424 case SPEED_1000:
2425 if (ecmd->duplex == DUPLEX_FULL)
2426 setting = SUPPORTED_1000baseT_Full;
2427 else if (ecmd->duplex == DUPLEX_HALF)
2428 setting = SUPPORTED_1000baseT_Half;
2429 else
2430 return -EINVAL;
2431 break;
2432 case SPEED_100:
2433 if (ecmd->duplex == DUPLEX_FULL)
2434 setting = SUPPORTED_100baseT_Full;
2435 else if (ecmd->duplex == DUPLEX_HALF)
2436 setting = SUPPORTED_100baseT_Half;
2437 else
2438 return -EINVAL;
2439 break;
2440
2441 case SPEED_10:
2442 if (ecmd->duplex == DUPLEX_FULL)
2443 setting = SUPPORTED_10baseT_Full;
2444 else if (ecmd->duplex == DUPLEX_HALF)
2445 setting = SUPPORTED_10baseT_Half;
2446 else
2447 return -EINVAL;
2448 break;
2449 default:
2450 return -EINVAL;
2451 }
2452
2453 if ((setting & supported) == 0)
2454 return -EINVAL;
2455
2456 sky2->speed = ecmd->speed;
2457 sky2->duplex = ecmd->duplex;
2458 }
2459
2460 sky2->autoneg = ecmd->autoneg;
2461 sky2->advertising = ecmd->advertising;
2462
2463 if (netif_running(dev))
2464 sky2_phy_reinit(sky2);
2465
2466 return 0;
2467 }
2468
2469 static void sky2_get_drvinfo(struct net_device *dev,
2470 struct ethtool_drvinfo *info)
2471 {
2472 struct sky2_port *sky2 = netdev_priv(dev);
2473
2474 strcpy(info->driver, DRV_NAME);
2475 strcpy(info->version, DRV_VERSION);
2476 strcpy(info->fw_version, "N/A");
2477 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2478 }
2479
2480 static const struct sky2_stat {
2481 char name[ETH_GSTRING_LEN];
2482 u16 offset;
2483 } sky2_stats[] = {
2484 { "tx_bytes", GM_TXO_OK_HI },
2485 { "rx_bytes", GM_RXO_OK_HI },
2486 { "tx_broadcast", GM_TXF_BC_OK },
2487 { "rx_broadcast", GM_RXF_BC_OK },
2488 { "tx_multicast", GM_TXF_MC_OK },
2489 { "rx_multicast", GM_RXF_MC_OK },
2490 { "tx_unicast", GM_TXF_UC_OK },
2491 { "rx_unicast", GM_RXF_UC_OK },
2492 { "tx_mac_pause", GM_TXF_MPAUSE },
2493 { "rx_mac_pause", GM_RXF_MPAUSE },
2494 { "collisions", GM_TXF_SNG_COL },
2495 { "late_collision",GM_TXF_LAT_COL },
2496 { "aborted", GM_TXF_ABO_COL },
2497 { "multi_collisions", GM_TXF_MUL_COL },
2498 { "fifo_underrun", GM_TXE_FIFO_UR },
2499 { "fifo_overflow", GM_RXE_FIFO_OV },
2500 { "rx_toolong", GM_RXF_LNG_ERR },
2501 { "rx_jabber", GM_RXF_JAB_PKT },
2502 { "rx_runt", GM_RXE_FRAG },
2503 { "rx_too_long", GM_RXF_LNG_ERR },
2504 { "rx_fcs_error", GM_RXF_FCS_ERR },
2505 };
2506
2507 static u32 sky2_get_rx_csum(struct net_device *dev)
2508 {
2509 struct sky2_port *sky2 = netdev_priv(dev);
2510
2511 return sky2->rx_csum;
2512 }
2513
2514 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2515 {
2516 struct sky2_port *sky2 = netdev_priv(dev);
2517
2518 sky2->rx_csum = data;
2519
2520 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2521 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2522
2523 return 0;
2524 }
2525
2526 static u32 sky2_get_msglevel(struct net_device *netdev)
2527 {
2528 struct sky2_port *sky2 = netdev_priv(netdev);
2529 return sky2->msg_enable;
2530 }
2531
2532 static int sky2_nway_reset(struct net_device *dev)
2533 {
2534 struct sky2_port *sky2 = netdev_priv(dev);
2535
2536 if (sky2->autoneg != AUTONEG_ENABLE)
2537 return -EINVAL;
2538
2539 sky2_phy_reinit(sky2);
2540
2541 return 0;
2542 }
2543
2544 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2545 {
2546 struct sky2_hw *hw = sky2->hw;
2547 unsigned port = sky2->port;
2548 int i;
2549
2550 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2551 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2552 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2553 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2554
2555 for (i = 2; i < count; i++)
2556 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2557 }
2558
2559 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2560 {
2561 struct sky2_port *sky2 = netdev_priv(netdev);
2562 sky2->msg_enable = value;
2563 }
2564
2565 static int sky2_get_stats_count(struct net_device *dev)
2566 {
2567 return ARRAY_SIZE(sky2_stats);
2568 }
2569
2570 static void sky2_get_ethtool_stats(struct net_device *dev,
2571 struct ethtool_stats *stats, u64 * data)
2572 {
2573 struct sky2_port *sky2 = netdev_priv(dev);
2574
2575 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2576 }
2577
2578 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2579 {
2580 int i;
2581
2582 switch (stringset) {
2583 case ETH_SS_STATS:
2584 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2585 memcpy(data + i * ETH_GSTRING_LEN,
2586 sky2_stats[i].name, ETH_GSTRING_LEN);
2587 break;
2588 }
2589 }
2590
2591 /* Use hardware MIB variables for critical path statistics and
2592 * transmit feedback not reported at interrupt.
2593 * Other errors are accounted for in interrupt handler.
2594 */
2595 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2596 {
2597 struct sky2_port *sky2 = netdev_priv(dev);
2598 u64 data[13];
2599
2600 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
2601
2602 sky2->net_stats.tx_bytes = data[0];
2603 sky2->net_stats.rx_bytes = data[1];
2604 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2605 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2606 sky2->net_stats.multicast = data[5] + data[7];
2607 sky2->net_stats.collisions = data[10];
2608 sky2->net_stats.tx_aborted_errors = data[12];
2609
2610 return &sky2->net_stats;
2611 }
2612
2613 static int sky2_set_mac_address(struct net_device *dev, void *p)
2614 {
2615 struct sky2_port *sky2 = netdev_priv(dev);
2616 struct sky2_hw *hw = sky2->hw;
2617 unsigned port = sky2->port;
2618 const struct sockaddr *addr = p;
2619
2620 if (!is_valid_ether_addr(addr->sa_data))
2621 return -EADDRNOTAVAIL;
2622
2623 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2624 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
2625 dev->dev_addr, ETH_ALEN);
2626 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
2627 dev->dev_addr, ETH_ALEN);
2628
2629 /* virtual address for data */
2630 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2631
2632 /* physical address: used for pause frames */
2633 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2634
2635 return 0;
2636 }
2637
2638 static void sky2_set_multicast(struct net_device *dev)
2639 {
2640 struct sky2_port *sky2 = netdev_priv(dev);
2641 struct sky2_hw *hw = sky2->hw;
2642 unsigned port = sky2->port;
2643 struct dev_mc_list *list = dev->mc_list;
2644 u16 reg;
2645 u8 filter[8];
2646
2647 memset(filter, 0, sizeof(filter));
2648
2649 reg = gma_read16(hw, port, GM_RX_CTRL);
2650 reg |= GM_RXCR_UCF_ENA;
2651
2652 if (dev->flags & IFF_PROMISC) /* promiscuous */
2653 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2654 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
2655 memset(filter, 0xff, sizeof(filter));
2656 else if (dev->mc_count == 0) /* no multicast */
2657 reg &= ~GM_RXCR_MCF_ENA;
2658 else {
2659 int i;
2660 reg |= GM_RXCR_MCF_ENA;
2661
2662 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2663 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2664 filter[bit / 8] |= 1 << (bit % 8);
2665 }
2666 }
2667
2668 gma_write16(hw, port, GM_MC_ADDR_H1,
2669 (u16) filter[0] | ((u16) filter[1] << 8));
2670 gma_write16(hw, port, GM_MC_ADDR_H2,
2671 (u16) filter[2] | ((u16) filter[3] << 8));
2672 gma_write16(hw, port, GM_MC_ADDR_H3,
2673 (u16) filter[4] | ((u16) filter[5] << 8));
2674 gma_write16(hw, port, GM_MC_ADDR_H4,
2675 (u16) filter[6] | ((u16) filter[7] << 8));
2676
2677 gma_write16(hw, port, GM_RX_CTRL, reg);
2678 }
2679
2680 /* Can have one global because blinking is controlled by
2681 * ethtool and that is always under RTNL mutex
2682 */
2683 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2684 {
2685 u16 pg;
2686
2687 switch (hw->chip_id) {
2688 case CHIP_ID_YUKON_XL:
2689 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2690 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2691 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2692 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2693 PHY_M_LEDC_INIT_CTRL(7) |
2694 PHY_M_LEDC_STA1_CTRL(7) |
2695 PHY_M_LEDC_STA0_CTRL(7))
2696 : 0);
2697
2698 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2699 break;
2700
2701 default:
2702 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2703 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2704 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2705 PHY_M_LED_MO_10(MO_LED_ON) |
2706 PHY_M_LED_MO_100(MO_LED_ON) |
2707 PHY_M_LED_MO_1000(MO_LED_ON) |
2708 PHY_M_LED_MO_RX(MO_LED_ON)
2709 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2710 PHY_M_LED_MO_10(MO_LED_OFF) |
2711 PHY_M_LED_MO_100(MO_LED_OFF) |
2712 PHY_M_LED_MO_1000(MO_LED_OFF) |
2713 PHY_M_LED_MO_RX(MO_LED_OFF));
2714
2715 }
2716 }
2717
2718 /* blink LED's for finding board */
2719 static int sky2_phys_id(struct net_device *dev, u32 data)
2720 {
2721 struct sky2_port *sky2 = netdev_priv(dev);
2722 struct sky2_hw *hw = sky2->hw;
2723 unsigned port = sky2->port;
2724 u16 ledctrl, ledover = 0;
2725 long ms;
2726 int interrupted;
2727 int onoff = 1;
2728
2729 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
2730 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2731 else
2732 ms = data * 1000;
2733
2734 /* save initial values */
2735 down(&sky2->phy_sema);
2736 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2737 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2738 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2739 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2740 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2741 } else {
2742 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2743 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2744 }
2745
2746 interrupted = 0;
2747 while (!interrupted && ms > 0) {
2748 sky2_led(hw, port, onoff);
2749 onoff = !onoff;
2750
2751 up(&sky2->phy_sema);
2752 interrupted = msleep_interruptible(250);
2753 down(&sky2->phy_sema);
2754
2755 ms -= 250;
2756 }
2757
2758 /* resume regularly scheduled programming */
2759 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2760 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2761 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2762 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2763 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2764 } else {
2765 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2766 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2767 }
2768 up(&sky2->phy_sema);
2769
2770 return 0;
2771 }
2772
2773 static void sky2_get_pauseparam(struct net_device *dev,
2774 struct ethtool_pauseparam *ecmd)
2775 {
2776 struct sky2_port *sky2 = netdev_priv(dev);
2777
2778 ecmd->tx_pause = sky2->tx_pause;
2779 ecmd->rx_pause = sky2->rx_pause;
2780 ecmd->autoneg = sky2->autoneg;
2781 }
2782
2783 static int sky2_set_pauseparam(struct net_device *dev,
2784 struct ethtool_pauseparam *ecmd)
2785 {
2786 struct sky2_port *sky2 = netdev_priv(dev);
2787 int err = 0;
2788
2789 sky2->autoneg = ecmd->autoneg;
2790 sky2->tx_pause = ecmd->tx_pause != 0;
2791 sky2->rx_pause = ecmd->rx_pause != 0;
2792
2793 sky2_phy_reinit(sky2);
2794
2795 return err;
2796 }
2797
2798 #ifdef CONFIG_PM
2799 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2800 {
2801 struct sky2_port *sky2 = netdev_priv(dev);
2802
2803 wol->supported = WAKE_MAGIC;
2804 wol->wolopts = sky2->wol ? WAKE_MAGIC : 0;
2805 }
2806
2807 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2808 {
2809 struct sky2_port *sky2 = netdev_priv(dev);
2810 struct sky2_hw *hw = sky2->hw;
2811
2812 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
2813 return -EOPNOTSUPP;
2814
2815 sky2->wol = wol->wolopts == WAKE_MAGIC;
2816
2817 if (sky2->wol) {
2818 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
2819
2820 sky2_write16(hw, WOL_CTRL_STAT,
2821 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
2822 WOL_CTL_ENA_MAGIC_PKT_UNIT);
2823 } else
2824 sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
2825
2826 return 0;
2827 }
2828 #endif
2829
2830 static int sky2_get_coalesce(struct net_device *dev,
2831 struct ethtool_coalesce *ecmd)
2832 {
2833 struct sky2_port *sky2 = netdev_priv(dev);
2834 struct sky2_hw *hw = sky2->hw;
2835
2836 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2837 ecmd->tx_coalesce_usecs = 0;
2838 else {
2839 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2840 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2841 }
2842 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2843
2844 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2845 ecmd->rx_coalesce_usecs = 0;
2846 else {
2847 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2848 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2849 }
2850 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2851
2852 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2853 ecmd->rx_coalesce_usecs_irq = 0;
2854 else {
2855 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2856 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2857 }
2858
2859 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2860
2861 return 0;
2862 }
2863
2864 /* Note: this affect both ports */
2865 static int sky2_set_coalesce(struct net_device *dev,
2866 struct ethtool_coalesce *ecmd)
2867 {
2868 struct sky2_port *sky2 = netdev_priv(dev);
2869 struct sky2_hw *hw = sky2->hw;
2870 const u32 tmin = sky2_clk2us(hw, 1);
2871 const u32 tmax = 5000;
2872
2873 if (ecmd->tx_coalesce_usecs != 0 &&
2874 (ecmd->tx_coalesce_usecs < tmin || ecmd->tx_coalesce_usecs > tmax))
2875 return -EINVAL;
2876
2877 if (ecmd->rx_coalesce_usecs != 0 &&
2878 (ecmd->rx_coalesce_usecs < tmin || ecmd->rx_coalesce_usecs > tmax))
2879 return -EINVAL;
2880
2881 if (ecmd->rx_coalesce_usecs_irq != 0 &&
2882 (ecmd->rx_coalesce_usecs_irq < tmin || ecmd->rx_coalesce_usecs_irq > tmax))
2883 return -EINVAL;
2884
2885 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
2886 return -EINVAL;
2887 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
2888 return -EINVAL;
2889 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
2890 return -EINVAL;
2891
2892 if (ecmd->tx_coalesce_usecs == 0)
2893 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2894 else {
2895 sky2_write32(hw, STAT_TX_TIMER_INI,
2896 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2897 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2898 }
2899 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2900
2901 if (ecmd->rx_coalesce_usecs == 0)
2902 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2903 else {
2904 sky2_write32(hw, STAT_LEV_TIMER_INI,
2905 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2906 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2907 }
2908 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2909
2910 if (ecmd->rx_coalesce_usecs_irq == 0)
2911 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2912 else {
2913 sky2_write32(hw, STAT_ISR_TIMER_INI,
2914 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2915 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2916 }
2917 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2918 return 0;
2919 }
2920
2921 static void sky2_get_ringparam(struct net_device *dev,
2922 struct ethtool_ringparam *ering)
2923 {
2924 struct sky2_port *sky2 = netdev_priv(dev);
2925
2926 ering->rx_max_pending = RX_MAX_PENDING;
2927 ering->rx_mini_max_pending = 0;
2928 ering->rx_jumbo_max_pending = 0;
2929 ering->tx_max_pending = TX_RING_SIZE - 1;
2930
2931 ering->rx_pending = sky2->rx_pending;
2932 ering->rx_mini_pending = 0;
2933 ering->rx_jumbo_pending = 0;
2934 ering->tx_pending = sky2->tx_pending;
2935 }
2936
2937 static int sky2_set_ringparam(struct net_device *dev,
2938 struct ethtool_ringparam *ering)
2939 {
2940 struct sky2_port *sky2 = netdev_priv(dev);
2941 int err = 0;
2942
2943 if (ering->rx_pending > RX_MAX_PENDING ||
2944 ering->rx_pending < 8 ||
2945 ering->tx_pending < MAX_SKB_TX_LE ||
2946 ering->tx_pending > TX_RING_SIZE - 1)
2947 return -EINVAL;
2948
2949 if (netif_running(dev))
2950 sky2_down(dev);
2951
2952 sky2->rx_pending = ering->rx_pending;
2953 sky2->tx_pending = ering->tx_pending;
2954
2955 if (netif_running(dev)) {
2956 err = sky2_up(dev);
2957 if (err)
2958 dev_close(dev);
2959 else
2960 sky2_set_multicast(dev);
2961 }
2962
2963 return err;
2964 }
2965
2966 static int sky2_get_regs_len(struct net_device *dev)
2967 {
2968 return 0x4000;
2969 }
2970
2971 /*
2972 * Returns copy of control register region
2973 * Note: access to the RAM address register set will cause timeouts.
2974 */
2975 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2976 void *p)
2977 {
2978 const struct sky2_port *sky2 = netdev_priv(dev);
2979 const void __iomem *io = sky2->hw->regs;
2980
2981 BUG_ON(regs->len < B3_RI_WTO_R1);
2982 regs->version = 1;
2983 memset(p, 0, regs->len);
2984
2985 memcpy_fromio(p, io, B3_RAM_ADDR);
2986
2987 memcpy_fromio(p + B3_RI_WTO_R1,
2988 io + B3_RI_WTO_R1,
2989 regs->len - B3_RI_WTO_R1);
2990 }
2991
2992 static struct ethtool_ops sky2_ethtool_ops = {
2993 .get_settings = sky2_get_settings,
2994 .set_settings = sky2_set_settings,
2995 .get_drvinfo = sky2_get_drvinfo,
2996 .get_msglevel = sky2_get_msglevel,
2997 .set_msglevel = sky2_set_msglevel,
2998 .nway_reset = sky2_nway_reset,
2999 .get_regs_len = sky2_get_regs_len,
3000 .get_regs = sky2_get_regs,
3001 .get_link = ethtool_op_get_link,
3002 .get_sg = ethtool_op_get_sg,
3003 .set_sg = ethtool_op_set_sg,
3004 .get_tx_csum = ethtool_op_get_tx_csum,
3005 .set_tx_csum = ethtool_op_set_tx_csum,
3006 .get_tso = ethtool_op_get_tso,
3007 .set_tso = ethtool_op_set_tso,
3008 .get_rx_csum = sky2_get_rx_csum,
3009 .set_rx_csum = sky2_set_rx_csum,
3010 .get_strings = sky2_get_strings,
3011 .get_coalesce = sky2_get_coalesce,
3012 .set_coalesce = sky2_set_coalesce,
3013 .get_ringparam = sky2_get_ringparam,
3014 .set_ringparam = sky2_set_ringparam,
3015 .get_pauseparam = sky2_get_pauseparam,
3016 .set_pauseparam = sky2_set_pauseparam,
3017 #ifdef CONFIG_PM
3018 .get_wol = sky2_get_wol,
3019 .set_wol = sky2_set_wol,
3020 #endif
3021 .phys_id = sky2_phys_id,
3022 .get_stats_count = sky2_get_stats_count,
3023 .get_ethtool_stats = sky2_get_ethtool_stats,
3024 .get_perm_addr = ethtool_op_get_perm_addr,
3025 };
3026
3027 /* Initialize network device */
3028 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3029 unsigned port, int highmem)
3030 {
3031 struct sky2_port *sky2;
3032 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3033
3034 if (!dev) {
3035 printk(KERN_ERR "sky2 etherdev alloc failed");
3036 return NULL;
3037 }
3038
3039 SET_MODULE_OWNER(dev);
3040 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3041 dev->irq = hw->pdev->irq;
3042 dev->open = sky2_up;
3043 dev->stop = sky2_down;
3044 dev->do_ioctl = sky2_ioctl;
3045 dev->hard_start_xmit = sky2_xmit_frame;
3046 dev->get_stats = sky2_get_stats;
3047 dev->set_multicast_list = sky2_set_multicast;
3048 dev->set_mac_address = sky2_set_mac_address;
3049 dev->change_mtu = sky2_change_mtu;
3050 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3051 dev->tx_timeout = sky2_tx_timeout;
3052 dev->watchdog_timeo = TX_WATCHDOG;
3053 if (port == 0)
3054 dev->poll = sky2_poll;
3055 dev->weight = NAPI_WEIGHT;
3056 #ifdef CONFIG_NET_POLL_CONTROLLER
3057 dev->poll_controller = sky2_netpoll;
3058 #endif
3059
3060 sky2 = netdev_priv(dev);
3061 sky2->netdev = dev;
3062 sky2->hw = hw;
3063 sky2->msg_enable = netif_msg_init(debug, default_msg);
3064
3065 spin_lock_init(&sky2->tx_lock);
3066 /* Auto speed and flow control */
3067 sky2->autoneg = AUTONEG_ENABLE;
3068 sky2->tx_pause = 1;
3069 sky2->rx_pause = 1;
3070 sky2->duplex = -1;
3071 sky2->speed = -1;
3072 sky2->advertising = sky2_supported_modes(hw);
3073
3074 /* Receive checksum disabled for Yukon XL
3075 * because of observed problems with incorrect
3076 * values when multiple packets are received in one interrupt
3077 */
3078 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
3079
3080 INIT_WORK(&sky2->phy_task, sky2_phy_task, sky2);
3081 init_MUTEX(&sky2->phy_sema);
3082 sky2->tx_pending = TX_DEF_PENDING;
3083 sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING;
3084 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
3085
3086 hw->dev[port] = dev;
3087
3088 sky2->port = port;
3089
3090 dev->features |= NETIF_F_LLTX;
3091 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3092 dev->features |= NETIF_F_TSO;
3093 if (highmem)
3094 dev->features |= NETIF_F_HIGHDMA;
3095 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3096
3097 #ifdef SKY2_VLAN_TAG_USED
3098 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3099 dev->vlan_rx_register = sky2_vlan_rx_register;
3100 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3101 #endif
3102
3103 /* read the mac address */
3104 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3105 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3106
3107 /* device is off until link detection */
3108 netif_carrier_off(dev);
3109 netif_stop_queue(dev);
3110
3111 return dev;
3112 }
3113
3114 static void __devinit sky2_show_addr(struct net_device *dev)
3115 {
3116 const struct sky2_port *sky2 = netdev_priv(dev);
3117
3118 if (netif_msg_probe(sky2))
3119 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3120 dev->name,
3121 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3122 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3123 }
3124
3125 static int __devinit sky2_probe(struct pci_dev *pdev,
3126 const struct pci_device_id *ent)
3127 {
3128 struct net_device *dev, *dev1 = NULL;
3129 struct sky2_hw *hw;
3130 int err, pm_cap, using_dac = 0;
3131
3132 err = pci_enable_device(pdev);
3133 if (err) {
3134 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3135 pci_name(pdev));
3136 goto err_out;
3137 }
3138
3139 err = pci_request_regions(pdev, DRV_NAME);
3140 if (err) {
3141 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3142 pci_name(pdev));
3143 goto err_out;
3144 }
3145
3146 pci_set_master(pdev);
3147
3148 /* Find power-management capability. */
3149 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3150 if (pm_cap == 0) {
3151 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3152 "aborting.\n");
3153 err = -EIO;
3154 goto err_out_free_regions;
3155 }
3156
3157 if (sizeof(dma_addr_t) > sizeof(u32) &&
3158 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3159 using_dac = 1;
3160 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3161 if (err < 0) {
3162 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3163 "for consistent allocations\n", pci_name(pdev));
3164 goto err_out_free_regions;
3165 }
3166
3167 } else {
3168 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3169 if (err) {
3170 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3171 pci_name(pdev));
3172 goto err_out_free_regions;
3173 }
3174 }
3175
3176 err = -ENOMEM;
3177 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3178 if (!hw) {
3179 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3180 pci_name(pdev));
3181 goto err_out_free_regions;
3182 }
3183
3184 hw->pdev = pdev;
3185
3186 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3187 if (!hw->regs) {
3188 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3189 pci_name(pdev));
3190 goto err_out_free_hw;
3191 }
3192 hw->pm_cap = pm_cap;
3193 spin_lock_init(&hw->hw_lock);
3194
3195 #ifdef __BIG_ENDIAN
3196 /* byte swap descriptors in hardware */
3197 {
3198 u32 reg;
3199
3200 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3201 reg |= PCI_REV_DESC;
3202 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3203 }
3204 #endif
3205
3206 /* ring for status responses */
3207 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3208 &hw->st_dma);
3209 if (!hw->st_le)
3210 goto err_out_iounmap;
3211
3212 err = sky2_reset(hw);
3213 if (err)
3214 goto err_out_iounmap;
3215
3216 printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3217 DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
3218 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3219 hw->chip_id, hw->chip_rev);
3220
3221 dev = sky2_init_netdev(hw, 0, using_dac);
3222 if (!dev)
3223 goto err_out_free_pci;
3224
3225 err = register_netdev(dev);
3226 if (err) {
3227 printk(KERN_ERR PFX "%s: cannot register net device\n",
3228 pci_name(pdev));
3229 goto err_out_free_netdev;
3230 }
3231
3232 sky2_show_addr(dev);
3233
3234 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3235 if (register_netdev(dev1) == 0)
3236 sky2_show_addr(dev1);
3237 else {
3238 /* Failure to register second port need not be fatal */
3239 printk(KERN_WARNING PFX
3240 "register of second port failed\n");
3241 hw->dev[1] = NULL;
3242 free_netdev(dev1);
3243 }
3244 }
3245
3246 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
3247 if (err) {
3248 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3249 pci_name(pdev), pdev->irq);
3250 goto err_out_unregister;
3251 }
3252
3253 hw->intr_mask = Y2_IS_BASE;
3254 sky2_write32(hw, B0_IMSK, hw->intr_mask);
3255
3256 pci_set_drvdata(pdev, hw);
3257
3258 return 0;
3259
3260 err_out_unregister:
3261 if (dev1) {
3262 unregister_netdev(dev1);
3263 free_netdev(dev1);
3264 }
3265 unregister_netdev(dev);
3266 err_out_free_netdev:
3267 free_netdev(dev);
3268 err_out_free_pci:
3269 sky2_write8(hw, B0_CTST, CS_RST_SET);
3270 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3271 err_out_iounmap:
3272 iounmap(hw->regs);
3273 err_out_free_hw:
3274 kfree(hw);
3275 err_out_free_regions:
3276 pci_release_regions(pdev);
3277 pci_disable_device(pdev);
3278 err_out:
3279 return err;
3280 }
3281
3282 static void __devexit sky2_remove(struct pci_dev *pdev)
3283 {
3284 struct sky2_hw *hw = pci_get_drvdata(pdev);
3285 struct net_device *dev0, *dev1;
3286
3287 if (!hw)
3288 return;
3289
3290 dev0 = hw->dev[0];
3291 dev1 = hw->dev[1];
3292 if (dev1)
3293 unregister_netdev(dev1);
3294 unregister_netdev(dev0);
3295
3296 sky2_write32(hw, B0_IMSK, 0);
3297 sky2_set_power_state(hw, PCI_D3hot);
3298 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
3299 sky2_write8(hw, B0_CTST, CS_RST_SET);
3300 sky2_read8(hw, B0_CTST);
3301
3302 free_irq(pdev->irq, hw);
3303 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3304 pci_release_regions(pdev);
3305 pci_disable_device(pdev);
3306
3307 if (dev1)
3308 free_netdev(dev1);
3309 free_netdev(dev0);
3310 iounmap(hw->regs);
3311 kfree(hw);
3312
3313 pci_set_drvdata(pdev, NULL);
3314 }
3315
3316 #ifdef CONFIG_PM
3317 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3318 {
3319 struct sky2_hw *hw = pci_get_drvdata(pdev);
3320 int i;
3321
3322 for (i = 0; i < 2; i++) {
3323 struct net_device *dev = hw->dev[i];
3324
3325 if (dev) {
3326 if (!netif_running(dev))
3327 continue;
3328
3329 sky2_down(dev);
3330 netif_device_detach(dev);
3331 }
3332 }
3333
3334 return sky2_set_power_state(hw, pci_choose_state(pdev, state));
3335 }
3336
3337 static int sky2_resume(struct pci_dev *pdev)
3338 {
3339 struct sky2_hw *hw = pci_get_drvdata(pdev);
3340 int i, err;
3341
3342 pci_restore_state(pdev);
3343 pci_enable_wake(pdev, PCI_D0, 0);
3344 err = sky2_set_power_state(hw, PCI_D0);
3345 if (err)
3346 goto out;
3347
3348 err = sky2_reset(hw);
3349 if (err)
3350 goto out;
3351
3352 for (i = 0; i < 2; i++) {
3353 struct net_device *dev = hw->dev[i];
3354 if (dev && netif_running(dev)) {
3355 netif_device_attach(dev);
3356 err = sky2_up(dev);
3357 if (err) {
3358 printk(KERN_ERR PFX "%s: could not up: %d\n",
3359 dev->name, err);
3360 dev_close(dev);
3361 break;
3362 }
3363 }
3364 }
3365 out:
3366 return err;
3367 }
3368 #endif
3369
3370 static struct pci_driver sky2_driver = {
3371 .name = DRV_NAME,
3372 .id_table = sky2_id_table,
3373 .probe = sky2_probe,
3374 .remove = __devexit_p(sky2_remove),
3375 #ifdef CONFIG_PM
3376 .suspend = sky2_suspend,
3377 .resume = sky2_resume,
3378 #endif
3379 };
3380
3381 static int __init sky2_init_module(void)
3382 {
3383 return pci_register_driver(&sky2_driver);
3384 }
3385
3386 static void __exit sky2_cleanup_module(void)
3387 {
3388 pci_unregister_driver(&sky2_driver);
3389 }
3390
3391 module_init(sky2_init_module);
3392 module_exit(sky2_cleanup_module);
3393
3394 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3395 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3396 MODULE_LICENSE("GPL");
3397 MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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