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Merge git://git.kernel.org/pub/scm/linux/kernel/git/bunk/trivial
[deliverable/linux.git] / drivers / net / sky2.h
1 /*
2 * Definitions for the new Marvell Yukon 2 driver.
3 */
4 #ifndef _SKY2_H
5 #define _SKY2_H
6
7 #define ETH_JUMBO_MTU 9000 /* Maximum MTU supported */
8
9 /* PCI device specific config registers */
10 enum {
11 PCI_DEV_REG1 = 0x40,
12 PCI_DEV_REG2 = 0x44,
13 PCI_DEV_REG3 = 0x80,
14 PCI_DEV_REG4 = 0x84,
15 PCI_DEV_REG5 = 0x88,
16 };
17
18 /* Yukon-2 */
19 enum pci_dev_reg_1 {
20 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
21 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
22 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
23 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
24 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
25 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
26 };
27
28 enum pci_dev_reg_2 {
29 PCI_VPD_WR_THR = 0xffL<<24, /* Bit 31..24: VPD Write Threshold */
30 PCI_DEV_SEL = 0x7fL<<17, /* Bit 23..17: EEPROM Device Select */
31 PCI_VPD_ROM_SZ = 7L<<14, /* Bit 16..14: VPD ROM Size */
32
33 PCI_PATCH_DIR = 0xfL<<8, /* Bit 11.. 8: Ext Patches dir 3..0 */
34 PCI_EXT_PATCHS = 0xfL<<4, /* Bit 7.. 4: Extended Patches 3..0 */
35 PCI_EN_DUMMY_RD = 1<<3, /* Enable Dummy Read */
36 PCI_REV_DESC = 1<<2, /* Reverse Desc. Bytes */
37
38 PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */
39 };
40
41 /* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */
42 enum pci_dev_reg_4 {
43 /* (Link Training & Status State Machine) */
44 P_TIMER_VALUE_MSK = 0xffL<<16, /* Bit 23..16: Timer Value Mask */
45 /* (Active State Power Management) */
46 P_FORCE_ASPM_REQUEST = 1<<15, /* Force ASPM Request (A1 only) */
47 P_ASPM_GPHY_LINK_DOWN = 1<<14, /* GPHY Link Down (A1 only) */
48 P_ASPM_INT_FIFO_EMPTY = 1<<13, /* Internal FIFO Empty (A1 only) */
49 P_ASPM_CLKRUN_REQUEST = 1<<12, /* CLKRUN Request (A1 only) */
50
51 P_ASPM_FORCE_CLKREQ_ENA = 1<<4, /* Force CLKREQ Enable (A1b only) */
52 P_ASPM_CLKREQ_PAD_CTL = 1<<3, /* CLKREQ PAD Control (A1 only) */
53 P_ASPM_A1_MODE_SELECT = 1<<2, /* A1 Mode Select (A1 only) */
54 P_CLK_GATE_PEX_UNIT_ENA = 1<<1, /* Enable Gate PEX Unit Clock */
55 P_CLK_GATE_ROOT_COR_ENA = 1<<0, /* Enable Gate Root Core Clock */
56 P_ASPM_CONTROL_MSK = P_FORCE_ASPM_REQUEST | P_ASPM_GPHY_LINK_DOWN
57 | P_ASPM_CLKRUN_REQUEST | P_ASPM_INT_FIFO_EMPTY,
58 };
59
60
61 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
62 PCI_STATUS_SIG_SYSTEM_ERROR | \
63 PCI_STATUS_REC_MASTER_ABORT | \
64 PCI_STATUS_REC_TARGET_ABORT | \
65 PCI_STATUS_PARITY)
66 enum csr_regs {
67 B0_RAP = 0x0000,
68 B0_CTST = 0x0004,
69 B0_Y2LED = 0x0005,
70 B0_POWER_CTRL = 0x0007,
71 B0_ISRC = 0x0008,
72 B0_IMSK = 0x000c,
73 B0_HWE_ISRC = 0x0010,
74 B0_HWE_IMSK = 0x0014,
75
76 /* Special ISR registers (Yukon-2 only) */
77 B0_Y2_SP_ISRC2 = 0x001c,
78 B0_Y2_SP_ISRC3 = 0x0020,
79 B0_Y2_SP_EISR = 0x0024,
80 B0_Y2_SP_LISR = 0x0028,
81 B0_Y2_SP_ICR = 0x002c,
82
83 B2_MAC_1 = 0x0100,
84 B2_MAC_2 = 0x0108,
85 B2_MAC_3 = 0x0110,
86 B2_CONN_TYP = 0x0118,
87 B2_PMD_TYP = 0x0119,
88 B2_MAC_CFG = 0x011a,
89 B2_CHIP_ID = 0x011b,
90 B2_E_0 = 0x011c,
91
92 B2_Y2_CLK_GATE = 0x011d,
93 B2_Y2_HW_RES = 0x011e,
94 B2_E_3 = 0x011f,
95 B2_Y2_CLK_CTRL = 0x0120,
96
97 B2_TI_INI = 0x0130,
98 B2_TI_VAL = 0x0134,
99 B2_TI_CTRL = 0x0138,
100 B2_TI_TEST = 0x0139,
101
102 B2_TST_CTRL1 = 0x0158,
103 B2_TST_CTRL2 = 0x0159,
104 B2_GP_IO = 0x015c,
105
106 B2_I2C_CTRL = 0x0160,
107 B2_I2C_DATA = 0x0164,
108 B2_I2C_IRQ = 0x0168,
109 B2_I2C_SW = 0x016c,
110
111 B3_RAM_ADDR = 0x0180,
112 B3_RAM_DATA_LO = 0x0184,
113 B3_RAM_DATA_HI = 0x0188,
114
115 /* RAM Interface Registers */
116 /* Yukon-2: use RAM_BUFFER() to access the RAM buffer */
117 /*
118 * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
119 * not usable in SW. Please notice these are NOT real timeouts, these are
120 * the number of qWords transferred continuously.
121 */
122 #define RAM_BUFFER(port, reg) (reg | (port <<6))
123
124 B3_RI_WTO_R1 = 0x0190,
125 B3_RI_WTO_XA1 = 0x0191,
126 B3_RI_WTO_XS1 = 0x0192,
127 B3_RI_RTO_R1 = 0x0193,
128 B3_RI_RTO_XA1 = 0x0194,
129 B3_RI_RTO_XS1 = 0x0195,
130 B3_RI_WTO_R2 = 0x0196,
131 B3_RI_WTO_XA2 = 0x0197,
132 B3_RI_WTO_XS2 = 0x0198,
133 B3_RI_RTO_R2 = 0x0199,
134 B3_RI_RTO_XA2 = 0x019a,
135 B3_RI_RTO_XS2 = 0x019b,
136 B3_RI_TO_VAL = 0x019c,
137 B3_RI_CTRL = 0x01a0,
138 B3_RI_TEST = 0x01a2,
139 B3_MA_TOINI_RX1 = 0x01b0,
140 B3_MA_TOINI_RX2 = 0x01b1,
141 B3_MA_TOINI_TX1 = 0x01b2,
142 B3_MA_TOINI_TX2 = 0x01b3,
143 B3_MA_TOVAL_RX1 = 0x01b4,
144 B3_MA_TOVAL_RX2 = 0x01b5,
145 B3_MA_TOVAL_TX1 = 0x01b6,
146 B3_MA_TOVAL_TX2 = 0x01b7,
147 B3_MA_TO_CTRL = 0x01b8,
148 B3_MA_TO_TEST = 0x01ba,
149 B3_MA_RCINI_RX1 = 0x01c0,
150 B3_MA_RCINI_RX2 = 0x01c1,
151 B3_MA_RCINI_TX1 = 0x01c2,
152 B3_MA_RCINI_TX2 = 0x01c3,
153 B3_MA_RCVAL_RX1 = 0x01c4,
154 B3_MA_RCVAL_RX2 = 0x01c5,
155 B3_MA_RCVAL_TX1 = 0x01c6,
156 B3_MA_RCVAL_TX2 = 0x01c7,
157 B3_MA_RC_CTRL = 0x01c8,
158 B3_MA_RC_TEST = 0x01ca,
159 B3_PA_TOINI_RX1 = 0x01d0,
160 B3_PA_TOINI_RX2 = 0x01d4,
161 B3_PA_TOINI_TX1 = 0x01d8,
162 B3_PA_TOINI_TX2 = 0x01dc,
163 B3_PA_TOVAL_RX1 = 0x01e0,
164 B3_PA_TOVAL_RX2 = 0x01e4,
165 B3_PA_TOVAL_TX1 = 0x01e8,
166 B3_PA_TOVAL_TX2 = 0x01ec,
167 B3_PA_CTRL = 0x01f0,
168 B3_PA_TEST = 0x01f2,
169
170 Y2_CFG_SPC = 0x1c00,
171 };
172
173 /* B0_CTST 16 bit Control/Status register */
174 enum {
175 Y2_VMAIN_AVAIL = 1<<17,/* VMAIN available (YUKON-2 only) */
176 Y2_VAUX_AVAIL = 1<<16,/* VAUX available (YUKON-2 only) */
177 Y2_HW_WOL_ON = 1<<15,/* HW WOL On (Yukon-EC Ultra A1 only) */
178 Y2_HW_WOL_OFF = 1<<14,/* HW WOL On (Yukon-EC Ultra A1 only) */
179 Y2_ASF_ENABLE = 1<<13,/* ASF Unit Enable (YUKON-2 only) */
180 Y2_ASF_DISABLE = 1<<12,/* ASF Unit Disable (YUKON-2 only) */
181 Y2_CLK_RUN_ENA = 1<<11,/* CLK_RUN Enable (YUKON-2 only) */
182 Y2_CLK_RUN_DIS = 1<<10,/* CLK_RUN Disable (YUKON-2 only) */
183 Y2_LED_STAT_ON = 1<<9, /* Status LED On (YUKON-2 only) */
184 Y2_LED_STAT_OFF = 1<<8, /* Status LED Off (YUKON-2 only) */
185
186 CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */
187 CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */
188 CS_STOP_DONE = 1<<5, /* Stop Master is finished */
189 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
190 CS_MRST_CLR = 1<<3, /* Clear Master reset */
191 CS_MRST_SET = 1<<2, /* Set Master reset */
192 CS_RST_CLR = 1<<1, /* Clear Software reset */
193 CS_RST_SET = 1, /* Set Software reset */
194 };
195
196 /* B0_LED 8 Bit LED register */
197 enum {
198 /* Bit 7.. 2: reserved */
199 LED_STAT_ON = 1<<1, /* Status LED on */
200 LED_STAT_OFF = 1, /* Status LED off */
201 };
202
203 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
204 enum {
205 PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */
206 PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */
207 PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
208 PC_VCC_DIS = 1<<4, /* Switch VCC Disable */
209 PC_VAUX_ON = 1<<3, /* Switch VAUX On */
210 PC_VAUX_OFF = 1<<2, /* Switch VAUX Off */
211 PC_VCC_ON = 1<<1, /* Switch VCC On */
212 PC_VCC_OFF = 1<<0, /* Switch VCC Off */
213 };
214
215 /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
216
217 /* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */
218 /* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */
219 /* B0_Y2_SP_EISR 32 bit Enter ISR Reg */
220 /* B0_Y2_SP_LISR 32 bit Leave ISR Reg */
221 enum {
222 Y2_IS_HW_ERR = 1<<31, /* Interrupt HW Error */
223 Y2_IS_STAT_BMU = 1<<30, /* Status BMU Interrupt */
224 Y2_IS_ASF = 1<<29, /* ASF subsystem Interrupt */
225
226 Y2_IS_POLL_CHK = 1<<27, /* Check IRQ from polling unit */
227 Y2_IS_TWSI_RDY = 1<<26, /* IRQ on end of TWSI Tx */
228 Y2_IS_IRQ_SW = 1<<25, /* SW forced IRQ */
229 Y2_IS_TIMINT = 1<<24, /* IRQ from Timer */
230
231 Y2_IS_IRQ_PHY2 = 1<<12, /* Interrupt from PHY 2 */
232 Y2_IS_IRQ_MAC2 = 1<<11, /* Interrupt from MAC 2 */
233 Y2_IS_CHK_RX2 = 1<<10, /* Descriptor error Rx 2 */
234 Y2_IS_CHK_TXS2 = 1<<9, /* Descriptor error TXS 2 */
235 Y2_IS_CHK_TXA2 = 1<<8, /* Descriptor error TXA 2 */
236
237 Y2_IS_IRQ_PHY1 = 1<<4, /* Interrupt from PHY 1 */
238 Y2_IS_IRQ_MAC1 = 1<<3, /* Interrupt from MAC 1 */
239 Y2_IS_CHK_RX1 = 1<<2, /* Descriptor error Rx 1 */
240 Y2_IS_CHK_TXS1 = 1<<1, /* Descriptor error TXS 1 */
241 Y2_IS_CHK_TXA1 = 1<<0, /* Descriptor error TXA 1 */
242
243 Y2_IS_BASE = Y2_IS_HW_ERR | Y2_IS_STAT_BMU,
244 Y2_IS_PORT_1 = Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1
245 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1,
246 Y2_IS_PORT_2 = Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2
247 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2,
248 };
249
250 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
251 enum {
252 IS_ERR_MSK = 0x00003fff,/* All Error bits */
253
254 IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
255 IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */
256 IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */
257 IS_IRQ_STAT = 1<<10, /* IRQ status exception */
258 IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */
259 IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */
260 IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */
261 IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */
262 IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */
263 IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */
264 IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */
265 IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */
266 IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */
267 IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */
268 };
269
270 /* Hardware error interrupt mask for Yukon 2 */
271 enum {
272 Y2_IS_TIST_OV = 1<<29,/* Time Stamp Timer overflow interrupt */
273 Y2_IS_SENSOR = 1<<28, /* Sensor interrupt */
274 Y2_IS_MST_ERR = 1<<27, /* Master error interrupt */
275 Y2_IS_IRQ_STAT = 1<<26, /* Status exception interrupt */
276 Y2_IS_PCI_EXP = 1<<25, /* PCI-Express interrupt */
277 Y2_IS_PCI_NEXP = 1<<24, /* PCI-Express error similar to PCI error */
278 /* Link 2 */
279 Y2_IS_PAR_RD2 = 1<<13, /* Read RAM parity error interrupt */
280 Y2_IS_PAR_WR2 = 1<<12, /* Write RAM parity error interrupt */
281 Y2_IS_PAR_MAC2 = 1<<11, /* MAC hardware fault interrupt */
282 Y2_IS_PAR_RX2 = 1<<10, /* Parity Error Rx Queue 2 */
283 Y2_IS_TCP_TXS2 = 1<<9, /* TCP length mismatch sync Tx queue IRQ */
284 Y2_IS_TCP_TXA2 = 1<<8, /* TCP length mismatch async Tx queue IRQ */
285 /* Link 1 */
286 Y2_IS_PAR_RD1 = 1<<5, /* Read RAM parity error interrupt */
287 Y2_IS_PAR_WR1 = 1<<4, /* Write RAM parity error interrupt */
288 Y2_IS_PAR_MAC1 = 1<<3, /* MAC hardware fault interrupt */
289 Y2_IS_PAR_RX1 = 1<<2, /* Parity Error Rx Queue 1 */
290 Y2_IS_TCP_TXS1 = 1<<1, /* TCP length mismatch sync Tx queue IRQ */
291 Y2_IS_TCP_TXA1 = 1<<0, /* TCP length mismatch async Tx queue IRQ */
292
293 Y2_HWE_L1_MASK = Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 |
294 Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1,
295 Y2_HWE_L2_MASK = Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 |
296 Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2,
297
298 Y2_HWE_ALL_MASK = Y2_IS_TIST_OV | Y2_IS_MST_ERR | Y2_IS_IRQ_STAT |
299 Y2_IS_PCI_EXP |
300 Y2_HWE_L1_MASK | Y2_HWE_L2_MASK,
301 };
302
303 /* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */
304 enum {
305 DPT_START = 1<<1,
306 DPT_STOP = 1<<0,
307 };
308
309 /* B2_TST_CTRL1 8 bit Test Control Register 1 */
310 enum {
311 TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
312 TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
313 TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
314 TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
315 TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */
316 TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */
317 TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */
318 TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
319 };
320
321 /* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
322 enum {
323 CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */
324 /* Bit 3.. 2: reserved */
325 CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */
326 CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/
327 };
328
329 /* B2_CHIP_ID 8 bit Chip Identification Number */
330 enum {
331 CHIP_ID_GENESIS = 0x0a, /* Chip ID for GENESIS */
332 CHIP_ID_YUKON = 0xb0, /* Chip ID for YUKON */
333 CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
334 CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
335 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
336 CHIP_ID_YUKON_EC_U = 0xb4, /* Chip ID for YUKON-2 EC Ultra */
337 CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
338 CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
339
340 CHIP_REV_YU_EC_A1 = 0, /* Chip Rev. for Yukon-EC A1/A0 */
341 CHIP_REV_YU_EC_A2 = 1, /* Chip Rev. for Yukon-EC A2 */
342 CHIP_REV_YU_EC_A3 = 2, /* Chip Rev. for Yukon-EC A3 */
343
344 CHIP_REV_YU_EC_U_A0 = 0,
345 CHIP_REV_YU_EC_U_A1 = 1,
346 };
347
348 /* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
349 enum {
350 Y2_STATUS_LNK2_INAC = 1<<7, /* Status Link 2 inactive (0 = active) */
351 Y2_CLK_GAT_LNK2_DIS = 1<<6, /* Disable clock gating Link 2 */
352 Y2_COR_CLK_LNK2_DIS = 1<<5, /* Disable Core clock Link 2 */
353 Y2_PCI_CLK_LNK2_DIS = 1<<4, /* Disable PCI clock Link 2 */
354 Y2_STATUS_LNK1_INAC = 1<<3, /* Status Link 1 inactive (0 = active) */
355 Y2_CLK_GAT_LNK1_DIS = 1<<2, /* Disable clock gating Link 1 */
356 Y2_COR_CLK_LNK1_DIS = 1<<1, /* Disable Core clock Link 1 */
357 Y2_PCI_CLK_LNK1_DIS = 1<<0, /* Disable PCI clock Link 1 */
358 };
359
360 /* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */
361 enum {
362 CFG_LED_MODE_MSK = 7<<2, /* Bit 4.. 2: LED Mode Mask */
363 CFG_LINK_2_AVAIL = 1<<1, /* Link 2 available */
364 CFG_LINK_1_AVAIL = 1<<0, /* Link 1 available */
365 };
366 #define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2)
367 #define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL)
368
369
370 /* B2_Y2_CLK_CTRL 32 bit Clock Frequency Control Register (Yukon-2/EC) */
371 enum {
372 Y2_CLK_DIV_VAL_MSK = 0xff<<16,/* Bit 23..16: Clock Divisor Value */
373 #define Y2_CLK_DIV_VAL(x) (((x)<<16) & Y2_CLK_DIV_VAL_MSK)
374 Y2_CLK_DIV_VAL2_MSK = 7<<21, /* Bit 23..21: Clock Divisor Value */
375 Y2_CLK_SELECT2_MSK = 0x1f<<16,/* Bit 20..16: Clock Select */
376 #define Y2_CLK_DIV_VAL_2(x) (((x)<<21) & Y2_CLK_DIV_VAL2_MSK)
377 #define Y2_CLK_SEL_VAL_2(x) (((x)<<16) & Y2_CLK_SELECT2_MSK)
378 Y2_CLK_DIV_ENA = 1<<1, /* Enable Core Clock Division */
379 Y2_CLK_DIV_DIS = 1<<0, /* Disable Core Clock Division */
380 };
381
382 /* B2_TI_CTRL 8 bit Timer control */
383 /* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
384 enum {
385 TIM_START = 1<<2, /* Start Timer */
386 TIM_STOP = 1<<1, /* Stop Timer */
387 TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */
388 };
389
390 /* B2_TI_TEST 8 Bit Timer Test */
391 /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
392 /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
393 enum {
394 TIM_T_ON = 1<<2, /* Test mode on */
395 TIM_T_OFF = 1<<1, /* Test mode off */
396 TIM_T_STEP = 1<<0, /* Test step */
397 };
398
399 /* B3_RAM_ADDR 32 bit RAM Address, to read or write */
400 /* Bit 31..19: reserved */
401 #define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
402 /* RAM Interface Registers */
403
404 /* B3_RI_CTRL 16 bit RAM Interface Control Register */
405 enum {
406 RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */
407 RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/
408
409 RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */
410 RI_RST_SET = 1<<0, /* Set RAM Interface Reset */
411 };
412
413 #define SK_RI_TO_53 36 /* RAM interface timeout */
414
415
416 /* Port related registers FIFO, and Arbiter */
417 #define SK_REG(port,reg) (((port)<<7)+(reg))
418
419 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
420 /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
421 /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
422 /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
423 /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
424
425 #define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */
426
427 /* TXA_CTRL 8 bit Tx Arbiter Control Register */
428 enum {
429 TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */
430 TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */
431 TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */
432 TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */
433 TXA_START_RC = 1<<3, /* Start sync Rate Control */
434 TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */
435 TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */
436 TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */
437 };
438
439 /*
440 * Bank 4 - 5
441 */
442 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
443 enum {
444 TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
445 TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
446 TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */
447 TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */
448 TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */
449 TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */
450 TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */
451 };
452
453
454 enum {
455 B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */
456 B7_CFG_SPC = 0x0380,/* copy of the Configuration register */
457 B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */
458 B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */
459 B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */
460 B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */
461 B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */
462 B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */
463 B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */
464 };
465
466 /* Queue Register Offsets, use Q_ADDR() to access */
467 enum {
468 B8_Q_REGS = 0x0400, /* base of Queue registers */
469 Q_D = 0x00, /* 8*32 bit Current Descriptor */
470 Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */
471 Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */
472 Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */
473 Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */
474 Q_BC = 0x30, /* 32 bit Current Byte Counter */
475 Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */
476 Q_F = 0x38, /* 32 bit Flag Register */
477 Q_T1 = 0x3c, /* 32 bit Test Register 1 */
478 Q_T1_TR = 0x3c, /* 8 bit Test Register 1 Transfer SM */
479 Q_T1_WR = 0x3d, /* 8 bit Test Register 1 Write Descriptor SM */
480 Q_T1_RD = 0x3e, /* 8 bit Test Register 1 Read Descriptor SM */
481 Q_T1_SV = 0x3f, /* 8 bit Test Register 1 Supervisor SM */
482 Q_T2 = 0x40, /* 32 bit Test Register 2 */
483 Q_T3 = 0x44, /* 32 bit Test Register 3 */
484
485 /* Yukon-2 */
486 Q_DONE = 0x24, /* 16 bit Done Index (Yukon-2 only) */
487 Q_WM = 0x40, /* 16 bit FIFO Watermark */
488 Q_AL = 0x42, /* 8 bit FIFO Alignment */
489 Q_RSP = 0x44, /* 16 bit FIFO Read Shadow Pointer */
490 Q_RSL = 0x46, /* 8 bit FIFO Read Shadow Level */
491 Q_RP = 0x48, /* 8 bit FIFO Read Pointer */
492 Q_RL = 0x4a, /* 8 bit FIFO Read Level */
493 Q_WP = 0x4c, /* 8 bit FIFO Write Pointer */
494 Q_WSP = 0x4d, /* 8 bit FIFO Write Shadow Pointer */
495 Q_WL = 0x4e, /* 8 bit FIFO Write Level */
496 Q_WSL = 0x4f, /* 8 bit FIFO Write Shadow Level */
497 };
498 #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
499
500 /* Q_F 32 bit Flag Register */
501 enum {
502 F_ALM_FULL = 1<<27, /* Rx FIFO: almost full */
503 F_EMPTY = 1<<27, /* Tx FIFO: empty flag */
504 F_FIFO_EOF = 1<<26, /* Tag (EOF Flag) bit in FIFO */
505 F_WM_REACHED = 1<<25, /* Watermark reached */
506 F_M_RX_RAM_DIS = 1<<24, /* MAC Rx RAM Read Port disable */
507 F_FIFO_LEVEL = 0x1fL<<16, /* Bit 23..16: # of Qwords in FIFO */
508 F_WATER_MARK = 0x0007ffL, /* Bit 10.. 0: Watermark */
509 };
510
511 /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
512 enum {
513 Y2_B8_PREF_REGS = 0x0450,
514
515 PREF_UNIT_CTRL = 0x00, /* 32 bit Control register */
516 PREF_UNIT_LAST_IDX = 0x04, /* 16 bit Last Index */
517 PREF_UNIT_ADDR_LO = 0x08, /* 32 bit List start addr, low part */
518 PREF_UNIT_ADDR_HI = 0x0c, /* 32 bit List start addr, high part*/
519 PREF_UNIT_GET_IDX = 0x10, /* 16 bit Get Index */
520 PREF_UNIT_PUT_IDX = 0x14, /* 16 bit Put Index */
521 PREF_UNIT_FIFO_WP = 0x20, /* 8 bit FIFO write pointer */
522 PREF_UNIT_FIFO_RP = 0x24, /* 8 bit FIFO read pointer */
523 PREF_UNIT_FIFO_WM = 0x28, /* 8 bit FIFO watermark */
524 PREF_UNIT_FIFO_LEV = 0x2c, /* 8 bit FIFO level */
525
526 PREF_UNIT_MASK_IDX = 0x0fff,
527 };
528 #define Y2_QADDR(q,reg) (Y2_B8_PREF_REGS + (q) + (reg))
529
530 /* RAM Buffer Register Offsets */
531 enum {
532
533 RB_START = 0x00,/* 32 bit RAM Buffer Start Address */
534 RB_END = 0x04,/* 32 bit RAM Buffer End Address */
535 RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */
536 RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */
537 RB_RX_UTPP = 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
538 RB_RX_LTPP = 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
539 RB_RX_UTHP = 0x18,/* 32 bit Rx Upper Threshold, High Prio */
540 RB_RX_LTHP = 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
541 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
542 RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */
543 RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */
544 RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */
545 RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */
546 RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */
547 };
548
549 /* Receive and Transmit Queues */
550 enum {
551 Q_R1 = 0x0000, /* Receive Queue 1 */
552 Q_R2 = 0x0080, /* Receive Queue 2 */
553 Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */
554 Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */
555 Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */
556 Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */
557 };
558
559 /* Different PHY Types */
560 enum {
561 PHY_ADDR_MARV = 0,
562 };
563
564 #define RB_ADDR(offs, queue) (B16_RAM_REGS + (queue) + (offs))
565
566
567 enum {
568 LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */
569 LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */
570 LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */
571 LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */
572
573 LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */
574
575 /* Receive GMAC FIFO (YUKON and Yukon-2) */
576
577 RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
578 RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
579 RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
580 RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
581 RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */
582 RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */
583 RX_GMF_UP_THR = 0x0c58,/* 8 bit Rx Upper Pause Thr (Yukon-EC_U) */
584 RX_GMF_LP_THR = 0x0c5a,/* 8 bit Rx Lower Pause Thr (Yukon-EC_U) */
585 RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */
586 RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
587
588 RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
589
590 RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
591
592 RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
593 };
594
595
596 /* Q_BC 32 bit Current Byte Counter */
597
598 /* BMU Control Status Registers */
599 /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
600 /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
601 /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
602 /* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
603 /* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
604 /* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
605 /* Q_CSR 32 bit BMU Control/Status Register */
606
607 /* Rx BMU Control / Status Registers (Yukon-2) */
608 enum {
609 BMU_IDLE = 1<<31, /* BMU Idle State */
610 BMU_RX_TCP_PKT = 1<<30, /* Rx TCP Packet (when RSS Hash enabled) */
611 BMU_RX_IP_PKT = 1<<29, /* Rx IP Packet (when RSS Hash enabled) */
612
613 BMU_ENA_RX_RSS_HASH = 1<<15, /* Enable Rx RSS Hash */
614 BMU_DIS_RX_RSS_HASH = 1<<14, /* Disable Rx RSS Hash */
615 BMU_ENA_RX_CHKSUM = 1<<13, /* Enable Rx TCP/IP Checksum Check */
616 BMU_DIS_RX_CHKSUM = 1<<12, /* Disable Rx TCP/IP Checksum Check */
617 BMU_CLR_IRQ_PAR = 1<<11, /* Clear IRQ on Parity errors (Rx) */
618 BMU_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment. error (Tx) */
619 BMU_CLR_IRQ_CHK = 1<<10, /* Clear IRQ Check */
620 BMU_STOP = 1<<9, /* Stop Rx/Tx Queue */
621 BMU_START = 1<<8, /* Start Rx/Tx Queue */
622 BMU_FIFO_OP_ON = 1<<7, /* FIFO Operational On */
623 BMU_FIFO_OP_OFF = 1<<6, /* FIFO Operational Off */
624 BMU_FIFO_ENA = 1<<5, /* Enable FIFO */
625 BMU_FIFO_RST = 1<<4, /* Reset FIFO */
626 BMU_OP_ON = 1<<3, /* BMU Operational On */
627 BMU_OP_OFF = 1<<2, /* BMU Operational Off */
628 BMU_RST_CLR = 1<<1, /* Clear BMU Reset (Enable) */
629 BMU_RST_SET = 1<<0, /* Set BMU Reset */
630
631 BMU_CLR_RESET = BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR,
632 BMU_OPER_INIT = BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START |
633 BMU_FIFO_ENA | BMU_OP_ON,
634
635 BMU_WM_DEFAULT = 0x600,
636 };
637
638 /* Tx BMU Control / Status Registers (Yukon-2) */
639 /* Bit 31: same as for Rx */
640 enum {
641 BMU_TX_IPIDINCR_ON = 1<<13, /* Enable IP ID Increment */
642 BMU_TX_IPIDINCR_OFF = 1<<12, /* Disable IP ID Increment */
643 BMU_TX_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment length mismatch */
644 };
645
646 /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
647 /* PREF_UNIT_CTRL 32 bit Prefetch Control register */
648 enum {
649 PREF_UNIT_OP_ON = 1<<3, /* prefetch unit operational */
650 PREF_UNIT_OP_OFF = 1<<2, /* prefetch unit not operational */
651 PREF_UNIT_RST_CLR = 1<<1, /* Clear Prefetch Unit Reset */
652 PREF_UNIT_RST_SET = 1<<0, /* Set Prefetch Unit Reset */
653 };
654
655 /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
656 /* RB_START 32 bit RAM Buffer Start Address */
657 /* RB_END 32 bit RAM Buffer End Address */
658 /* RB_WP 32 bit RAM Buffer Write Pointer */
659 /* RB_RP 32 bit RAM Buffer Read Pointer */
660 /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
661 /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
662 /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
663 /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
664 /* RB_PC 32 bit RAM Buffer Packet Counter */
665 /* RB_LEV 32 bit RAM Buffer Level Register */
666
667 #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
668 /* RB_TST2 8 bit RAM Buffer Test Register 2 */
669 /* RB_TST1 8 bit RAM Buffer Test Register 1 */
670
671 /* RB_CTRL 8 bit RAM Buffer Control Register */
672 enum {
673 RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */
674 RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */
675 RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
676 RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
677 RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */
678 RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */
679 };
680
681
682 /* Transmit GMAC FIFO (YUKON only) */
683 enum {
684 TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
685 TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
686 TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
687
688 TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */
689 TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
690 TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */
691
692 TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */
693 TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */
694 TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */
695 };
696
697 /* Descriptor Poll Timer Registers */
698 enum {
699 B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */
700 B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */
701 B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */
702
703 B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */
704 };
705
706 /* Time Stamp Timer Registers (YUKON only) */
707 enum {
708 GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */
709 GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */
710 GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */
711 };
712
713 /* Polling Unit Registers (Yukon-2 only) */
714 enum {
715 POLL_CTRL = 0x0e20, /* 32 bit Polling Unit Control Reg */
716 POLL_LAST_IDX = 0x0e24,/* 16 bit Polling Unit List Last Index */
717
718 POLL_LIST_ADDR_LO= 0x0e28,/* 32 bit Poll. List Start Addr (low) */
719 POLL_LIST_ADDR_HI= 0x0e2c,/* 32 bit Poll. List Start Addr (high) */
720 };
721
722 /* ASF Subsystem Registers (Yukon-2 only) */
723 enum {
724 B28_Y2_SMB_CONFIG = 0x0e40,/* 32 bit ASF SMBus Config Register */
725 B28_Y2_SMB_CSD_REG = 0x0e44,/* 32 bit ASF SMB Control/Status/Data */
726 B28_Y2_ASF_IRQ_V_BASE=0x0e60,/* 32 bit ASF IRQ Vector Base */
727
728 B28_Y2_ASF_STAT_CMD= 0x0e68,/* 32 bit ASF Status and Command Reg */
729 B28_Y2_ASF_HOST_COM= 0x0e6c,/* 32 bit ASF Host Communication Reg */
730 B28_Y2_DATA_REG_1 = 0x0e70,/* 32 bit ASF/Host Data Register 1 */
731 B28_Y2_DATA_REG_2 = 0x0e74,/* 32 bit ASF/Host Data Register 2 */
732 B28_Y2_DATA_REG_3 = 0x0e78,/* 32 bit ASF/Host Data Register 3 */
733 B28_Y2_DATA_REG_4 = 0x0e7c,/* 32 bit ASF/Host Data Register 4 */
734 };
735
736 /* Status BMU Registers (Yukon-2 only)*/
737 enum {
738 STAT_CTRL = 0x0e80,/* 32 bit Status BMU Control Reg */
739 STAT_LAST_IDX = 0x0e84,/* 16 bit Status BMU Last Index */
740
741 STAT_LIST_ADDR_LO= 0x0e88,/* 32 bit Status List Start Addr (low) */
742 STAT_LIST_ADDR_HI= 0x0e8c,/* 32 bit Status List Start Addr (high) */
743 STAT_TXA1_RIDX = 0x0e90,/* 16 bit Status TxA1 Report Index Reg */
744 STAT_TXS1_RIDX = 0x0e92,/* 16 bit Status TxS1 Report Index Reg */
745 STAT_TXA2_RIDX = 0x0e94,/* 16 bit Status TxA2 Report Index Reg */
746 STAT_TXS2_RIDX = 0x0e96,/* 16 bit Status TxS2 Report Index Reg */
747 STAT_TX_IDX_TH = 0x0e98,/* 16 bit Status Tx Index Threshold Reg */
748 STAT_PUT_IDX = 0x0e9c,/* 16 bit Status Put Index Reg */
749
750 /* FIFO Control/Status Registers (Yukon-2 only)*/
751 STAT_FIFO_WP = 0x0ea0,/* 8 bit Status FIFO Write Pointer Reg */
752 STAT_FIFO_RP = 0x0ea4,/* 8 bit Status FIFO Read Pointer Reg */
753 STAT_FIFO_RSP = 0x0ea6,/* 8 bit Status FIFO Read Shadow Ptr */
754 STAT_FIFO_LEVEL = 0x0ea8,/* 8 bit Status FIFO Level Reg */
755 STAT_FIFO_SHLVL = 0x0eaa,/* 8 bit Status FIFO Shadow Level Reg */
756 STAT_FIFO_WM = 0x0eac,/* 8 bit Status FIFO Watermark Reg */
757 STAT_FIFO_ISR_WM= 0x0ead,/* 8 bit Status FIFO ISR Watermark Reg */
758
759 /* Level and ISR Timer Registers (Yukon-2 only)*/
760 STAT_LEV_TIMER_INI= 0x0eb0,/* 32 bit Level Timer Init. Value Reg */
761 STAT_LEV_TIMER_CNT= 0x0eb4,/* 32 bit Level Timer Counter Reg */
762 STAT_LEV_TIMER_CTRL= 0x0eb8,/* 8 bit Level Timer Control Reg */
763 STAT_LEV_TIMER_TEST= 0x0eb9,/* 8 bit Level Timer Test Reg */
764 STAT_TX_TIMER_INI = 0x0ec0,/* 32 bit Tx Timer Init. Value Reg */
765 STAT_TX_TIMER_CNT = 0x0ec4,/* 32 bit Tx Timer Counter Reg */
766 STAT_TX_TIMER_CTRL = 0x0ec8,/* 8 bit Tx Timer Control Reg */
767 STAT_TX_TIMER_TEST = 0x0ec9,/* 8 bit Tx Timer Test Reg */
768 STAT_ISR_TIMER_INI = 0x0ed0,/* 32 bit ISR Timer Init. Value Reg */
769 STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit ISR Timer Counter Reg */
770 STAT_ISR_TIMER_CTRL= 0x0ed8,/* 8 bit ISR Timer Control Reg */
771 STAT_ISR_TIMER_TEST= 0x0ed9,/* 8 bit ISR Timer Test Reg */
772 };
773
774 enum {
775 LINKLED_OFF = 0x01,
776 LINKLED_ON = 0x02,
777 LINKLED_LINKSYNC_OFF = 0x04,
778 LINKLED_LINKSYNC_ON = 0x08,
779 LINKLED_BLINK_OFF = 0x10,
780 LINKLED_BLINK_ON = 0x20,
781 };
782
783 /* GMAC and GPHY Control Registers (YUKON only) */
784 enum {
785 GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */
786 GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */
787 GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */
788 GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */
789 GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */
790
791 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
792
793 WOL_REG_OFFS = 0x20,/* HW-Bug: Address is + 0x20 against spec. */
794
795 WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */
796 WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */
797 WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */
798 WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */
799 WOL_PATT_PME = 0x0f2a,/* 8 bit WOL PME Match Enable (Yukon-2) */
800 WOL_PATT_ASFM = 0x0f2b,/* 8 bit WOL ASF Match Enable (Yukon-2) */
801 WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */
802
803 /* WOL Pattern Length Registers (YUKON only) */
804
805 WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */
806 WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */
807
808 /* WOL Pattern Counter Registers (YUKON only) */
809
810
811 WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
812 WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
813 };
814
815 enum {
816 WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */
817 WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */
818 };
819
820 enum {
821 BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */
822 BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */
823 };
824
825 /*
826 * Marvel-PHY Registers, indirect addressed over GMAC
827 */
828 enum {
829 PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
830 PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */
831 PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
832 PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
833 PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
834 PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
835 PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
836 PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */
837 PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
838 /* Marvel-specific registers */
839 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
840 PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
841 PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
842 PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */
843 PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */
844 PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */
845 PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */
846 PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */
847 PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */
848 PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */
849 PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */
850 PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */
851 PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */
852 PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */
853 PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */
854 PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */
855 PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */
856 PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */
857
858 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
859 PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */
860 PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */
861 PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */
862 PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */
863 PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */
864 };
865
866 enum {
867 PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */
868 PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */
869 PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */
870 PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
871 PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */
872 PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */
873 PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
874 PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */
875 PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */
876 PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */
877 };
878
879 enum {
880 PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */
881 PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */
882 PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */
883 };
884
885 enum {
886 PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */
887
888 PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */
889 PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
890 PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occured */
891 PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
892 PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */
893 PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */
894 PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */
895 };
896
897 enum {
898 PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */
899 PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */
900 PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */
901 };
902
903 /* different Marvell PHY Ids */
904 enum {
905 PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */
906
907 PHY_BCOM_ID1_A1 = 0x6041,
908 PHY_BCOM_ID1_B2 = 0x6043,
909 PHY_BCOM_ID1_C0 = 0x6044,
910 PHY_BCOM_ID1_C5 = 0x6047,
911
912 PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */
913 PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
914 PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
915 PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
916 PHY_MARV_ID1_FE = 0x0C83, /* Yukon-FE (PHY 88E3082 Rev.A1) */
917 PHY_MARV_ID1_ECU= 0x0CB0, /* Yukon-ECU (PHY 88E1149 Rev.B2?) */
918 };
919
920 /* Advertisement register bits */
921 enum {
922 PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
923 PHY_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
924 PHY_AN_RF = 1<<13, /* Bit 13: Remote Fault Bits */
925
926 PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */
927 PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: Try for pause */
928 PHY_AN_100BASE4 = 1<<9, /* Bit 9: Try for 100mbps 4k packets */
929 PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */
930 PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */
931 PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */
932 PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
933 PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */
934 PHY_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
935 PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA,
936 PHY_AN_ALL = PHY_AN_10HALF | PHY_AN_10FULL |
937 PHY_AN_100HALF | PHY_AN_100FULL,
938 };
939
940 /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
941 /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
942 enum {
943 PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */
944 PHY_B_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */
945 PHY_B_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */
946 PHY_B_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */
947 PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */
948 PHY_B_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */
949 /* Bit 9..8: reserved */
950 PHY_B_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */
951 };
952
953 /** Marvell-Specific */
954 enum {
955 PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */
956 PHY_M_AN_ACK = 1<<14, /* (ro) Acknowledge Received */
957 PHY_M_AN_RF = 1<<13, /* Remote Fault */
958
959 PHY_M_AN_ASP = 1<<11, /* Asymmetric Pause */
960 PHY_M_AN_PC = 1<<10, /* MAC Pause implemented */
961 PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
962 PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
963 PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
964 PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
965 PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
966 PHY_M_AN_SEL_MSK =0x1f<<4, /* Bit 4.. 0: Selector Field Mask */
967 };
968
969 /* special defines for FIBER (88E1011S only) */
970 enum {
971 PHY_M_AN_ASP_X = 1<<8, /* Asymmetric Pause */
972 PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */
973 PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
974 PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
975 };
976
977 /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
978 enum {
979 PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 8.. 7: no Pause Mode */
980 PHY_M_P_SYM_MD_X = 1<<7, /* Bit 8.. 7: symmetric Pause Mode */
981 PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */
982 PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 8.. 7: both Pause Mode */
983 };
984
985 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
986 enum {
987 PHY_M_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
988 PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */
989 PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */
990 PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
991 PHY_M_1000C_AFD = 1<<9, /* Advertise Full Duplex */
992 PHY_M_1000C_AHD = 1<<8, /* Advertise Half Duplex */
993 };
994
995 /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
996 enum {
997 PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
998 PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */
999 PHY_M_PC_ASS_CRS_TX = 1<<11, /* Assert CRS on Transmit */
1000 PHY_M_PC_FL_GOOD = 1<<10, /* Force Link Good */
1001 PHY_M_PC_EN_DET_MSK = 3<<8,/* Bit 9.. 8: Energy Detect Mask */
1002 PHY_M_PC_ENA_EXT_D = 1<<7, /* Enable Ext. Distance (10BT) */
1003 PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */
1004 PHY_M_PC_DIS_125CLK = 1<<4, /* Disable 125 CLK */
1005 PHY_M_PC_MAC_POW_UP = 1<<3, /* MAC Power up */
1006 PHY_M_PC_SQE_T_ENA = 1<<2, /* SQE Test Enabled */
1007 PHY_M_PC_POL_R_DIS = 1<<1, /* Polarity Reversal Disabled */
1008 PHY_M_PC_DIS_JABBER = 1<<0, /* Disable Jabber */
1009 };
1010
1011 enum {
1012 PHY_M_PC_EN_DET = 2<<8, /* Energy Detect (Mode 1) */
1013 PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */
1014 };
1015
1016 #define PHY_M_PC_MDI_XMODE(x) (((x)<<5) & PHY_M_PC_MDIX_MSK)
1017
1018 enum {
1019 PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */
1020 PHY_M_PC_MAN_MDIX = 1, /* 01 = Manual MDIX configuration */
1021 PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */
1022 };
1023
1024 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1025 enum {
1026 PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
1027 PHY_M_PC_ENA_ENE_DT = 1<<14, /* Enable Energy Detect (sense & pulse) */
1028 PHY_M_PC_DIS_NLP_CK = 1<<13, /* Disable Normal Link Puls (NLP) Check */
1029 PHY_M_PC_ENA_LIP_NP = 1<<12, /* Enable Link Partner Next Page Reg. */
1030 PHY_M_PC_DIS_NLP_GN = 1<<11, /* Disable Normal Link Puls Generation */
1031
1032 PHY_M_PC_DIS_SCRAMB = 1<<9, /* Disable Scrambler */
1033 PHY_M_PC_DIS_FEFI = 1<<8, /* Disable Far End Fault Indic. (FEFI) */
1034
1035 PHY_M_PC_SH_TP_SEL = 1<<6, /* Shielded Twisted Pair Select */
1036 PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */
1037 };
1038
1039 /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
1040 enum {
1041 PHY_M_PS_SPEED_MSK = 3<<14, /* Bit 15..14: Speed Mask */
1042 PHY_M_PS_SPEED_1000 = 1<<15, /* 10 = 1000 Mbps */
1043 PHY_M_PS_SPEED_100 = 1<<14, /* 01 = 100 Mbps */
1044 PHY_M_PS_SPEED_10 = 0, /* 00 = 10 Mbps */
1045 PHY_M_PS_FULL_DUP = 1<<13, /* Full Duplex */
1046 PHY_M_PS_PAGE_REC = 1<<12, /* Page Received */
1047 PHY_M_PS_SPDUP_RES = 1<<11, /* Speed & Duplex Resolved */
1048 PHY_M_PS_LINK_UP = 1<<10, /* Link Up */
1049 PHY_M_PS_CABLE_MSK = 7<<7, /* Bit 9.. 7: Cable Length Mask */
1050 PHY_M_PS_MDI_X_STAT = 1<<6, /* MDI Crossover Stat (1=MDIX) */
1051 PHY_M_PS_DOWNS_STAT = 1<<5, /* Downshift Status (1=downsh.) */
1052 PHY_M_PS_ENDET_STAT = 1<<4, /* Energy Detect Status (1=act) */
1053 PHY_M_PS_TX_P_EN = 1<<3, /* Tx Pause Enabled */
1054 PHY_M_PS_RX_P_EN = 1<<2, /* Rx Pause Enabled */
1055 PHY_M_PS_POL_REV = 1<<1, /* Polarity Reversed */
1056 PHY_M_PS_JABBER = 1<<0, /* Jabber */
1057 };
1058
1059 #define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
1060
1061 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1062 enum {
1063 PHY_M_PS_DTE_DETECT = 1<<15, /* Data Terminal Equipment (DTE) Detected */
1064 PHY_M_PS_RES_SPEED = 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
1065 };
1066
1067 enum {
1068 PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */
1069 PHY_M_IS_LSP_CHANGE = 1<<14, /* Link Speed Changed */
1070 PHY_M_IS_DUP_CHANGE = 1<<13, /* Duplex Mode Changed */
1071 PHY_M_IS_AN_PR = 1<<12, /* Page Received */
1072 PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
1073 PHY_M_IS_LST_CHANGE = 1<<10, /* Link Status Changed */
1074 PHY_M_IS_SYMB_ERROR = 1<<9, /* Symbol Error */
1075 PHY_M_IS_FALSE_CARR = 1<<8, /* False Carrier */
1076 PHY_M_IS_FIFO_ERROR = 1<<7, /* FIFO Overflow/Underrun Error */
1077 PHY_M_IS_MDI_CHANGE = 1<<6, /* MDI Crossover Changed */
1078 PHY_M_IS_DOWNSH_DET = 1<<5, /* Downshift Detected */
1079 PHY_M_IS_END_CHANGE = 1<<4, /* Energy Detect Changed */
1080
1081 PHY_M_IS_DTE_CHANGE = 1<<2, /* DTE Power Det. Status Changed */
1082 PHY_M_IS_POL_CHANGE = 1<<1, /* Polarity Changed */
1083 PHY_M_IS_JABBER = 1<<0, /* Jabber */
1084
1085 PHY_M_DEF_MSK = PHY_M_IS_LSP_CHANGE | PHY_M_IS_LST_CHANGE
1086 | PHY_M_IS_FIFO_ERROR,
1087 PHY_M_AN_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL,
1088 };
1089
1090
1091 /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
1092 enum {
1093 PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */
1094 PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */
1095
1096 PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */
1097 PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */
1098 /* (88E1011 only) */
1099 PHY_M_EC_S_DSC_MSK = 3<<8,/* Bit 9.. 8: Slave Downshift Counter */
1100 /* (88E1011 only) */
1101 PHY_M_EC_M_DSC_MSK2 = 7<<9,/* Bit 11.. 9: Master Downshift Counter */
1102 /* (88E1111 only) */
1103 PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */
1104 /* !!! Errata in spec. (1 = disable) */
1105 PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/
1106 PHY_M_EC_MAC_S_MSK = 7<<4,/* Bit 6.. 4: Def. MAC interface speed */
1107 PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
1108 PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */
1109 PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */
1110 PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */};
1111
1112 #define PHY_M_EC_M_DSC(x) ((x)<<10 & PHY_M_EC_M_DSC_MSK)
1113 /* 00=1x; 01=2x; 10=3x; 11=4x */
1114 #define PHY_M_EC_S_DSC(x) ((x)<<8 & PHY_M_EC_S_DSC_MSK)
1115 /* 00=dis; 01=1x; 10=2x; 11=3x */
1116 #define PHY_M_EC_DSC_2(x) ((x)<<9 & PHY_M_EC_M_DSC_MSK2)
1117 /* 000=1x; 001=2x; 010=3x; 011=4x */
1118 #define PHY_M_EC_MAC_S(x) ((x)<<4 & PHY_M_EC_MAC_S_MSK)
1119 /* 01X=0; 110=2.5; 111=25 (MHz) */
1120
1121 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1122 enum {
1123 PHY_M_PC_DIS_LINK_Pa = 1<<15,/* Disable Link Pulses */
1124 PHY_M_PC_DSC_MSK = 7<<12,/* Bit 14..12: Downshift Counter */
1125 PHY_M_PC_DOWN_S_ENA = 1<<11,/* Downshift Enable */
1126 };
1127 /* !!! Errata in spec. (1 = disable) */
1128
1129 #define PHY_M_PC_DSC(x) (((x)<<12) & PHY_M_PC_DSC_MSK)
1130 /* 100=5x; 101=6x; 110=7x; 111=8x */
1131 enum {
1132 MAC_TX_CLK_0_MHZ = 2,
1133 MAC_TX_CLK_2_5_MHZ = 6,
1134 MAC_TX_CLK_25_MHZ = 7,
1135 };
1136
1137 /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
1138 enum {
1139 PHY_M_LEDC_DIS_LED = 1<<15, /* Disable LED */
1140 PHY_M_LEDC_PULS_MSK = 7<<12,/* Bit 14..12: Pulse Stretch Mask */
1141 PHY_M_LEDC_F_INT = 1<<11, /* Force Interrupt */
1142 PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 10.. 8: Blink Rate Mask */
1143 PHY_M_LEDC_DP_C_LSB = 1<<7, /* Duplex Control (LSB, 88E1111 only) */
1144 PHY_M_LEDC_TX_C_LSB = 1<<6, /* Tx Control (LSB, 88E1111 only) */
1145 PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */
1146 /* (88E1111 only) */
1147 };
1148
1149 enum {
1150 PHY_M_LEDC_LINK_MSK = 3<<3,/* Bit 4.. 3: Link Control Mask */
1151 /* (88E1011 only) */
1152 PHY_M_LEDC_DP_CTRL = 1<<2, /* Duplex Control */
1153 PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */
1154 PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */
1155 PHY_M_LEDC_TX_CTRL = 1<<0, /* Tx Activity / Link */
1156 PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */
1157 };
1158
1159 #define PHY_M_LED_PULS_DUR(x) (((x)<<12) & PHY_M_LEDC_PULS_MSK)
1160
1161 /***** PHY_MARV_PHY_STAT (page 3)16 bit r/w Polarity Control Reg. *****/
1162 enum {
1163 PHY_M_POLC_LS1M_MSK = 0xf<<12, /* Bit 15..12: LOS,STAT1 Mix % Mask */
1164 PHY_M_POLC_IS0M_MSK = 0xf<<8, /* Bit 11.. 8: INIT,STAT0 Mix % Mask */
1165 PHY_M_POLC_LOS_MSK = 0x3<<6, /* Bit 7.. 6: LOS Pol. Ctrl. Mask */
1166 PHY_M_POLC_INIT_MSK = 0x3<<4, /* Bit 5.. 4: INIT Pol. Ctrl. Mask */
1167 PHY_M_POLC_STA1_MSK = 0x3<<2, /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */
1168 PHY_M_POLC_STA0_MSK = 0x3, /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */
1169 };
1170
1171 #define PHY_M_POLC_LS1_P_MIX(x) (((x)<<12) & PHY_M_POLC_LS1M_MSK)
1172 #define PHY_M_POLC_IS0_P_MIX(x) (((x)<<8) & PHY_M_POLC_IS0M_MSK)
1173 #define PHY_M_POLC_LOS_CTRL(x) (((x)<<6) & PHY_M_POLC_LOS_MSK)
1174 #define PHY_M_POLC_INIT_CTRL(x) (((x)<<4) & PHY_M_POLC_INIT_MSK)
1175 #define PHY_M_POLC_STA1_CTRL(x) (((x)<<2) & PHY_M_POLC_STA1_MSK)
1176 #define PHY_M_POLC_STA0_CTRL(x) (((x)<<0) & PHY_M_POLC_STA0_MSK)
1177
1178 enum {
1179 PULS_NO_STR = 0,/* no pulse stretching */
1180 PULS_21MS = 1,/* 21 ms to 42 ms */
1181 PULS_42MS = 2,/* 42 ms to 84 ms */
1182 PULS_84MS = 3,/* 84 ms to 170 ms */
1183 PULS_170MS = 4,/* 170 ms to 340 ms */
1184 PULS_340MS = 5,/* 340 ms to 670 ms */
1185 PULS_670MS = 6,/* 670 ms to 1.3 s */
1186 PULS_1300MS = 7,/* 1.3 s to 2.7 s */
1187 };
1188
1189 #define PHY_M_LED_BLINK_RT(x) (((x)<<8) & PHY_M_LEDC_BL_R_MSK)
1190
1191 enum {
1192 BLINK_42MS = 0,/* 42 ms */
1193 BLINK_84MS = 1,/* 84 ms */
1194 BLINK_170MS = 2,/* 170 ms */
1195 BLINK_340MS = 3,/* 340 ms */
1196 BLINK_670MS = 4,/* 670 ms */
1197 };
1198
1199 /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
1200 #define PHY_M_LED_MO_SGMII(x) ((x)<<14) /* Bit 15..14: SGMII AN Timer */
1201 /* Bit 13..12: reserved */
1202 #define PHY_M_LED_MO_DUP(x) ((x)<<10) /* Bit 11..10: Duplex */
1203 #define PHY_M_LED_MO_10(x) ((x)<<8) /* Bit 9.. 8: Link 10 */
1204 #define PHY_M_LED_MO_100(x) ((x)<<6) /* Bit 7.. 6: Link 100 */
1205 #define PHY_M_LED_MO_1000(x) ((x)<<4) /* Bit 5.. 4: Link 1000 */
1206 #define PHY_M_LED_MO_RX(x) ((x)<<2) /* Bit 3.. 2: Rx */
1207 #define PHY_M_LED_MO_TX(x) ((x)<<0) /* Bit 1.. 0: Tx */
1208
1209 enum {
1210 MO_LED_NORM = 0,
1211 MO_LED_BLINK = 1,
1212 MO_LED_OFF = 2,
1213 MO_LED_ON = 3,
1214 };
1215
1216 /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
1217 enum {
1218 PHY_M_EC2_FI_IMPED = 1<<6, /* Fiber Input Impedance */
1219 PHY_M_EC2_FO_IMPED = 1<<5, /* Fiber Output Impedance */
1220 PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */
1221 PHY_M_EC2_FO_BOOST = 1<<3, /* Fiber Output Boost */
1222 PHY_M_EC2_FO_AM_MSK = 7,/* Bit 2.. 0: Fiber Output Amplitude */
1223 };
1224
1225 /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
1226 enum {
1227 PHY_M_FC_AUTO_SEL = 1<<15, /* Fiber/Copper Auto Sel. Dis. */
1228 PHY_M_FC_AN_REG_ACC = 1<<14, /* Fiber/Copper AN Reg. Access */
1229 PHY_M_FC_RESOLUTION = 1<<13, /* Fiber/Copper Resolution */
1230 PHY_M_SER_IF_AN_BP = 1<<12, /* Ser. IF AN Bypass Enable */
1231 PHY_M_SER_IF_BP_ST = 1<<11, /* Ser. IF AN Bypass Status */
1232 PHY_M_IRQ_POLARITY = 1<<10, /* IRQ polarity */
1233 PHY_M_DIS_AUT_MED = 1<<9, /* Disable Aut. Medium Reg. Selection */
1234 /* (88E1111 only) */
1235
1236 PHY_M_UNDOC1 = 1<<7, /* undocumented bit !! */
1237 PHY_M_DTE_POW_STAT = 1<<4, /* DTE Power Status (88E1111 only) */
1238 PHY_M_MODE_MASK = 0xf, /* Bit 3.. 0: copy of HWCFG MODE[3:0] */
1239 };
1240
1241 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1242 /***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
1243 /* Bit 15..12: reserved (used internally) */
1244 enum {
1245 PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */
1246 PHY_M_FELP_LED1_MSK = 0xf<<4, /* Bit 7.. 4: LED1 Mask (ACT) */
1247 PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */
1248 };
1249
1250 #define PHY_M_FELP_LED2_CTRL(x) (((x)<<8) & PHY_M_FELP_LED2_MSK)
1251 #define PHY_M_FELP_LED1_CTRL(x) (((x)<<4) & PHY_M_FELP_LED1_MSK)
1252 #define PHY_M_FELP_LED0_CTRL(x) (((x)<<0) & PHY_M_FELP_LED0_MSK)
1253
1254 enum {
1255 LED_PAR_CTRL_COLX = 0x00,
1256 LED_PAR_CTRL_ERROR = 0x01,
1257 LED_PAR_CTRL_DUPLEX = 0x02,
1258 LED_PAR_CTRL_DP_COL = 0x03,
1259 LED_PAR_CTRL_SPEED = 0x04,
1260 LED_PAR_CTRL_LINK = 0x05,
1261 LED_PAR_CTRL_TX = 0x06,
1262 LED_PAR_CTRL_RX = 0x07,
1263 LED_PAR_CTRL_ACT = 0x08,
1264 LED_PAR_CTRL_LNK_RX = 0x09,
1265 LED_PAR_CTRL_LNK_AC = 0x0a,
1266 LED_PAR_CTRL_ACT_BL = 0x0b,
1267 LED_PAR_CTRL_TX_BL = 0x0c,
1268 LED_PAR_CTRL_RX_BL = 0x0d,
1269 LED_PAR_CTRL_COL_BL = 0x0e,
1270 LED_PAR_CTRL_INACT = 0x0f
1271 };
1272
1273 /*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
1274 enum {
1275 PHY_M_FESC_DIS_WAIT = 1<<2, /* Disable TDR Waiting Period */
1276 PHY_M_FESC_ENA_MCLK = 1<<1, /* Enable MAC Rx Clock in sleep mode */
1277 PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */
1278 };
1279
1280 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1281 /***** PHY_MARV_PHY_CTRL (page 1) 16 bit r/w Fiber Specific Ctrl *****/
1282 enum {
1283 PHY_M_FIB_FORCE_LNK = 1<<10,/* Force Link Good */
1284 PHY_M_FIB_SIGD_POL = 1<<9, /* SIGDET Polarity */
1285 PHY_M_FIB_TX_DIS = 1<<3, /* Transmitter Disable */
1286 };
1287
1288 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1289 /***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/
1290 enum {
1291 PHY_M_MAC_MD_MSK = 7<<7, /* Bit 9.. 7: Mode Select Mask */
1292 PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */
1293 PHY_M_MAC_MD_COPPER = 5,/* Copper only */
1294 PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */
1295 };
1296 #define PHY_M_MAC_MODE_SEL(x) (((x)<<7) & PHY_M_MAC_MD_MSK)
1297
1298 /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
1299 enum {
1300 PHY_M_LEDC_LOS_MSK = 0xf<<12,/* Bit 15..12: LOS LED Ctrl. Mask */
1301 PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
1302 PHY_M_LEDC_STA1_MSK = 0xf<<4,/* Bit 7.. 4: STAT1 LED Ctrl. Mask */
1303 PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
1304 };
1305
1306 #define PHY_M_LEDC_LOS_CTRL(x) (((x)<<12) & PHY_M_LEDC_LOS_MSK)
1307 #define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & PHY_M_LEDC_INIT_MSK)
1308 #define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & PHY_M_LEDC_STA1_MSK)
1309 #define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & PHY_M_LEDC_STA0_MSK)
1310
1311 /* GMAC registers */
1312 /* Port Registers */
1313 enum {
1314 GM_GP_STAT = 0x0000, /* 16 bit r/o General Purpose Status */
1315 GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */
1316 GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */
1317 GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */
1318 GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
1319 GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */
1320 GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */
1321 /* Source Address Registers */
1322 GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */
1323 GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */
1324 GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */
1325 GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */
1326 GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */
1327 GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */
1328
1329 /* Multicast Address Hash Registers */
1330 GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */
1331 GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */
1332 GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */
1333 GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */
1334
1335 /* Interrupt Source Registers */
1336 GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */
1337 GM_RX_IRQ_SRC = 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */
1338 GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */
1339
1340 /* Interrupt Mask Registers */
1341 GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */
1342 GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */
1343 GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */
1344
1345 /* Serial Management Interface (SMI) Registers */
1346 GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */
1347 GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */
1348 GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */
1349 /* MIB Counters */
1350 GM_MIB_CNT_BASE = 0x0100, /* Base Address of MIB Counters */
1351 GM_MIB_CNT_END = 0x025C, /* Last MIB counter */
1352 };
1353
1354
1355 /*
1356 * MIB Counters base address definitions (low word) -
1357 * use offset 4 for access to high word (32 bit r/o)
1358 */
1359 enum {
1360 GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, /* Unicast Frames Received OK */
1361 GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, /* Broadcast Frames Received OK */
1362 GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */
1363 GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */
1364 GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */
1365
1366 GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */
1367 GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */
1368 GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */
1369 GM_RXO_ERR_HI = GM_MIB_CNT_BASE + 72, /* Octets Received Invalid High */
1370 GM_RXF_SHT = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */
1371 GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */
1372 GM_RXF_64B = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */
1373 GM_RXF_127B = GM_MIB_CNT_BASE + 104,/* 65-127 Byte Rx Frame */
1374 GM_RXF_255B = GM_MIB_CNT_BASE + 112,/* 128-255 Byte Rx Frame */
1375 GM_RXF_511B = GM_MIB_CNT_BASE + 120,/* 256-511 Byte Rx Frame */
1376 GM_RXF_1023B = GM_MIB_CNT_BASE + 128,/* 512-1023 Byte Rx Frame */
1377 GM_RXF_1518B = GM_MIB_CNT_BASE + 136,/* 1024-1518 Byte Rx Frame */
1378 GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144,/* 1519-MaxSize Byte Rx Frame */
1379 GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152,/* Rx Frame too Long Error */
1380 GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160,/* Rx Jabber Packet Frame */
1381
1382 GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176,/* Rx FIFO overflow Event */
1383 GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192,/* Unicast Frames Xmitted OK */
1384 GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200,/* Broadcast Frames Xmitted OK */
1385 GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208,/* Pause MAC Ctrl Frames Xmitted */
1386 GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216,/* Multicast Frames Xmitted OK */
1387 GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224,/* Octets Transmitted OK Low */
1388 GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232,/* Octets Transmitted OK High */
1389 GM_TXF_64B = GM_MIB_CNT_BASE + 240,/* 64 Byte Tx Frame */
1390 GM_TXF_127B = GM_MIB_CNT_BASE + 248,/* 65-127 Byte Tx Frame */
1391 GM_TXF_255B = GM_MIB_CNT_BASE + 256,/* 128-255 Byte Tx Frame */
1392 GM_TXF_511B = GM_MIB_CNT_BASE + 264,/* 256-511 Byte Tx Frame */
1393 GM_TXF_1023B = GM_MIB_CNT_BASE + 272,/* 512-1023 Byte Tx Frame */
1394 GM_TXF_1518B = GM_MIB_CNT_BASE + 280,/* 1024-1518 Byte Tx Frame */
1395 GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288,/* 1519-MaxSize Byte Tx Frame */
1396
1397 GM_TXF_COL = GM_MIB_CNT_BASE + 304,/* Tx Collision */
1398 GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312,/* Tx Late Collision */
1399 GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320,/* Tx aborted due to Exces. Col. */
1400 GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328,/* Tx Multiple Collision */
1401 GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336,/* Tx Single Collision */
1402 GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344,/* Tx FIFO Underrun Event */
1403 };
1404
1405 /* GMAC Bit Definitions */
1406 /* GM_GP_STAT 16 bit r/o General Purpose Status Register */
1407 enum {
1408 GM_GPSR_SPEED = 1<<15, /* Bit 15: Port Speed (1 = 100 Mbps) */
1409 GM_GPSR_DUPLEX = 1<<14, /* Bit 14: Duplex Mode (1 = Full) */
1410 GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
1411 GM_GPSR_LINK_UP = 1<<12, /* Bit 12: Link Up Status */
1412 GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */
1413 GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */
1414 GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occured */
1415 GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occured */
1416
1417 GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */
1418 GM_GPSR_GIG_SPEED = 1<<4, /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */
1419 GM_GPSR_PART_MODE = 1<<3, /* Bit 3: Partition mode */
1420 GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
1421 GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */
1422 };
1423
1424 /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
1425 enum {
1426 GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */
1427 GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
1428 GM_GPCR_TX_ENA = 1<<12, /* Bit 12: Enable Transmit */
1429 GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */
1430 GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */
1431 GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */
1432 GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */
1433 GM_GPCR_GIGS_ENA = 1<<7, /* Bit 7: Gigabit Speed (1000 Mbps) */
1434 GM_GPCR_FL_PASS = 1<<6, /* Bit 6: Force Link Pass */
1435 GM_GPCR_DUP_FULL = 1<<5, /* Bit 5: Full Duplex Mode */
1436 GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
1437 GM_GPCR_SPEED_100 = 1<<3, /* Bit 3: Port Speed 100 Mbps */
1438 GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */
1439 GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */
1440 GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */
1441 };
1442
1443 #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
1444 #define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS)
1445
1446 /* GM_TX_CTRL 16 bit r/w Transmit Control Register */
1447 enum {
1448 GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
1449 GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */
1450 GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */
1451 GM_TXCR_COL_THR_MSK = 7<<10, /* Bit 12..10: Collision Threshold */
1452 };
1453
1454 #define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK)
1455 #define TX_COL_DEF 0x04
1456
1457 /* GM_RX_CTRL 16 bit r/w Receive Control Register */
1458 enum {
1459 GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */
1460 GM_RXCR_MCF_ENA = 1<<14, /* Bit 14: Enable Multicast filtering */
1461 GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
1462 GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */
1463 };
1464
1465 /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
1466 enum {
1467 GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */
1468 GM_TXPA_JAMIPG_MSK = 0x1f<<9, /* Bit 13..9: Jam IPG */
1469 GM_TXPA_JAMDAT_MSK = 0x1f<<4, /* Bit 8..4: IPG Jam to Data */
1470 GM_TXPA_BO_LIM_MSK = 0x0f, /* Bit 3.. 0: Backoff Limit Mask */
1471
1472 TX_JAM_LEN_DEF = 0x03,
1473 TX_JAM_IPG_DEF = 0x0b,
1474 TX_IPG_JAM_DEF = 0x1c,
1475 TX_BOF_LIM_DEF = 0x04,
1476 };
1477
1478 #define TX_JAM_LEN_VAL(x) (((x)<<14) & GM_TXPA_JAMLEN_MSK)
1479 #define TX_JAM_IPG_VAL(x) (((x)<<9) & GM_TXPA_JAMIPG_MSK)
1480 #define TX_IPG_JAM_DATA(x) (((x)<<4) & GM_TXPA_JAMDAT_MSK)
1481 #define TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK)
1482
1483
1484 /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
1485 enum {
1486 GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */
1487 GM_SMOD_LIMIT_4 = 1<<10, /* Bit 10: 4 consecutive Tx trials */
1488 GM_SMOD_VLAN_ENA = 1<<9, /* Bit 9: Enable VLAN (Max. Frame Len) */
1489 GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */
1490 GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
1491 };
1492
1493 #define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK)
1494 #define DATA_BLIND_DEF 0x04
1495
1496 #define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK)
1497 #define IPG_DATA_DEF 0x1e
1498
1499 /* GM_SMI_CTRL 16 bit r/w SMI Control Register */
1500 enum {
1501 GM_SMI_CT_PHY_A_MSK = 0x1f<<11,/* Bit 15..11: PHY Device Address */
1502 GM_SMI_CT_REG_A_MSK = 0x1f<<6,/* Bit 10.. 6: PHY Register Address */
1503 GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/
1504 GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */
1505 GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */
1506 };
1507
1508 #define GM_SMI_CT_PHY_AD(x) (((x)<<11) & GM_SMI_CT_PHY_A_MSK)
1509 #define GM_SMI_CT_REG_AD(x) (((x)<<6) & GM_SMI_CT_REG_A_MSK)
1510
1511 /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
1512 enum {
1513 GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */
1514 GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */
1515 };
1516
1517 /* Receive Frame Status Encoding */
1518 enum {
1519 GMR_FS_LEN = 0xffff<<16, /* Bit 31..16: Rx Frame Length */
1520 GMR_FS_VLAN = 1<<13, /* VLAN Packet */
1521 GMR_FS_JABBER = 1<<12, /* Jabber Packet */
1522 GMR_FS_UN_SIZE = 1<<11, /* Undersize Packet */
1523 GMR_FS_MC = 1<<10, /* Multicast Packet */
1524 GMR_FS_BC = 1<<9, /* Broadcast Packet */
1525 GMR_FS_RX_OK = 1<<8, /* Receive OK (Good Packet) */
1526 GMR_FS_GOOD_FC = 1<<7, /* Good Flow-Control Packet */
1527 GMR_FS_BAD_FC = 1<<6, /* Bad Flow-Control Packet */
1528 GMR_FS_MII_ERR = 1<<5, /* MII Error */
1529 GMR_FS_LONG_ERR = 1<<4, /* Too Long Packet */
1530 GMR_FS_FRAGMENT = 1<<3, /* Fragment */
1531
1532 GMR_FS_CRC_ERR = 1<<1, /* CRC Error */
1533 GMR_FS_RX_FF_OV = 1<<0, /* Rx FIFO Overflow */
1534
1535 GMR_FS_ANY_ERR = GMR_FS_RX_FF_OV | GMR_FS_CRC_ERR |
1536 GMR_FS_FRAGMENT | GMR_FS_LONG_ERR |
1537 GMR_FS_MII_ERR | GMR_FS_BAD_FC |
1538 GMR_FS_UN_SIZE | GMR_FS_JABBER,
1539 };
1540
1541 /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
1542 enum {
1543 RX_TRUNC_ON = 1<<27, /* enable packet truncation */
1544 RX_TRUNC_OFF = 1<<26, /* disable packet truncation */
1545 RX_VLAN_STRIP_ON = 1<<25, /* enable VLAN stripping */
1546 RX_VLAN_STRIP_OFF = 1<<24, /* disable VLAN stripping */
1547
1548 GMF_WP_TST_ON = 1<<14, /* Write Pointer Test On */
1549 GMF_WP_TST_OFF = 1<<13, /* Write Pointer Test Off */
1550 GMF_WP_STEP = 1<<12, /* Write Pointer Step/Increment */
1551
1552 GMF_RP_TST_ON = 1<<10, /* Read Pointer Test On */
1553 GMF_RP_TST_OFF = 1<<9, /* Read Pointer Test Off */
1554 GMF_RP_STEP = 1<<8, /* Read Pointer Step/Increment */
1555 GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */
1556 GMF_RX_F_FL_OFF = 1<<6, /* Rx FIFO Flush Mode Off */
1557 GMF_CLI_RX_FO = 1<<5, /* Clear IRQ Rx FIFO Overrun */
1558 GMF_CLI_RX_C = 1<<4, /* Clear IRQ Rx Frame Complete */
1559
1560 GMF_OPER_ON = 1<<3, /* Operational Mode On */
1561 GMF_OPER_OFF = 1<<2, /* Operational Mode Off */
1562 GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */
1563 GMF_RST_SET = 1<<0, /* Set GMAC FIFO Reset */
1564
1565 RX_GMF_FL_THR_DEF = 0xa, /* flush threshold (default) */
1566
1567 GMF_RX_CTRL_DEF = GMF_OPER_ON | GMF_RX_F_FL_ON,
1568 };
1569
1570
1571 /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
1572 enum {
1573 TX_STFW_DIS = 1<<31,/* Disable Store & Forward (Yukon-EC Ultra) */
1574 TX_STFW_ENA = 1<<30,/* Enable Store & Forward (Yukon-EC Ultra) */
1575
1576 TX_VLAN_TAG_ON = 1<<25,/* enable VLAN tagging */
1577 TX_VLAN_TAG_OFF = 1<<24,/* disable VLAN tagging */
1578
1579 GMF_WSP_TST_ON = 1<<18,/* Write Shadow Pointer Test On */
1580 GMF_WSP_TST_OFF = 1<<17,/* Write Shadow Pointer Test Off */
1581 GMF_WSP_STEP = 1<<16,/* Write Shadow Pointer Step/Increment */
1582
1583 GMF_CLI_TX_FU = 1<<6, /* Clear IRQ Tx FIFO Underrun */
1584 GMF_CLI_TX_FC = 1<<5, /* Clear IRQ Tx Frame Complete */
1585 GMF_CLI_TX_PE = 1<<4, /* Clear IRQ Tx Parity Error */
1586 };
1587
1588 /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
1589 enum {
1590 GMT_ST_START = 1<<2, /* Start Time Stamp Timer */
1591 GMT_ST_STOP = 1<<1, /* Stop Time Stamp Timer */
1592 GMT_ST_CLR_IRQ = 1<<0, /* Clear Time Stamp Timer IRQ */
1593 };
1594
1595 /* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */
1596 enum {
1597 Y2_ASF_OS_PRES = 1<<4, /* ASF operation system present */
1598 Y2_ASF_RESET = 1<<3, /* ASF system in reset state */
1599 Y2_ASF_RUNNING = 1<<2, /* ASF system operational */
1600 Y2_ASF_CLR_HSTI = 1<<1, /* Clear ASF IRQ */
1601 Y2_ASF_IRQ = 1<<0, /* Issue an IRQ to ASF system */
1602
1603 Y2_ASF_UC_STATE = 3<<2, /* ASF uC State */
1604 Y2_ASF_CLK_HALT = 0, /* ASF system clock stopped */
1605 };
1606
1607 /* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */
1608 enum {
1609 Y2_ASF_CLR_ASFI = 1<<1, /* Clear host IRQ */
1610 Y2_ASF_HOST_IRQ = 1<<0, /* Issue an IRQ to HOST system */
1611 };
1612
1613 /* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */
1614 enum {
1615 SC_STAT_CLR_IRQ = 1<<4, /* Status Burst IRQ clear */
1616 SC_STAT_OP_ON = 1<<3, /* Operational Mode On */
1617 SC_STAT_OP_OFF = 1<<2, /* Operational Mode Off */
1618 SC_STAT_RST_CLR = 1<<1, /* Clear Status Unit Reset (Enable) */
1619 SC_STAT_RST_SET = 1<<0, /* Set Status Unit Reset */
1620 };
1621
1622 /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
1623 enum {
1624 GMC_H_BURST_ON = 1<<7, /* Half Duplex Burst Mode On */
1625 GMC_H_BURST_OFF = 1<<6, /* Half Duplex Burst Mode Off */
1626 GMC_F_LOOPB_ON = 1<<5, /* FIFO Loopback On */
1627 GMC_F_LOOPB_OFF = 1<<4, /* FIFO Loopback Off */
1628 GMC_PAUSE_ON = 1<<3, /* Pause On */
1629 GMC_PAUSE_OFF = 1<<2, /* Pause Off */
1630 GMC_RST_CLR = 1<<1, /* Clear GMAC Reset */
1631 GMC_RST_SET = 1<<0, /* Set GMAC Reset */
1632 };
1633
1634 /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
1635 enum {
1636 GPC_SEL_BDT = 1<<28, /* Select Bi-Dir. Transfer for MDC/MDIO */
1637 GPC_INT_POL_HI = 1<<27, /* IRQ Polarity is Active HIGH */
1638 GPC_75_OHM = 1<<26, /* Use 75 Ohm Termination instead of 50 */
1639 GPC_DIS_FC = 1<<25, /* Disable Automatic Fiber/Copper Detection */
1640 GPC_DIS_SLEEP = 1<<24, /* Disable Energy Detect */
1641 GPC_HWCFG_M_3 = 1<<23, /* HWCFG_MODE[3] */
1642 GPC_HWCFG_M_2 = 1<<22, /* HWCFG_MODE[2] */
1643 GPC_HWCFG_M_1 = 1<<21, /* HWCFG_MODE[1] */
1644 GPC_HWCFG_M_0 = 1<<20, /* HWCFG_MODE[0] */
1645 GPC_ANEG_0 = 1<<19, /* ANEG[0] */
1646 GPC_ENA_XC = 1<<18, /* Enable MDI crossover */
1647 GPC_DIS_125 = 1<<17, /* Disable 125 MHz clock */
1648 GPC_ANEG_3 = 1<<16, /* ANEG[3] */
1649 GPC_ANEG_2 = 1<<15, /* ANEG[2] */
1650 GPC_ANEG_1 = 1<<14, /* ANEG[1] */
1651 GPC_ENA_PAUSE = 1<<13, /* Enable Pause (SYM_OR_REM) */
1652 GPC_PHYADDR_4 = 1<<12, /* Bit 4 of Phy Addr */
1653 GPC_PHYADDR_3 = 1<<11, /* Bit 3 of Phy Addr */
1654 GPC_PHYADDR_2 = 1<<10, /* Bit 2 of Phy Addr */
1655 GPC_PHYADDR_1 = 1<<9, /* Bit 1 of Phy Addr */
1656 GPC_PHYADDR_0 = 1<<8, /* Bit 0 of Phy Addr */
1657 /* Bits 7..2: reserved */
1658 GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */
1659 GPC_RST_SET = 1<<0, /* Set GPHY Reset */
1660 };
1661
1662 /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
1663 /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
1664 enum {
1665 GM_IS_TX_CO_OV = 1<<5, /* Transmit Counter Overflow IRQ */
1666 GM_IS_RX_CO_OV = 1<<4, /* Receive Counter Overflow IRQ */
1667 GM_IS_TX_FF_UR = 1<<3, /* Transmit FIFO Underrun */
1668 GM_IS_TX_COMPL = 1<<2, /* Frame Transmission Complete */
1669 GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */
1670 GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */
1671
1672 #define GMAC_DEF_MSK GM_IS_TX_FF_UR
1673
1674 /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
1675 /* Bits 15.. 2: reserved */
1676 GMLC_RST_CLR = 1<<1, /* Clear GMAC Link Reset */
1677 GMLC_RST_SET = 1<<0, /* Set GMAC Link Reset */
1678
1679
1680 /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
1681 WOL_CTL_LINK_CHG_OCC = 1<<15,
1682 WOL_CTL_MAGIC_PKT_OCC = 1<<14,
1683 WOL_CTL_PATTERN_OCC = 1<<13,
1684 WOL_CTL_CLEAR_RESULT = 1<<12,
1685 WOL_CTL_ENA_PME_ON_LINK_CHG = 1<<11,
1686 WOL_CTL_DIS_PME_ON_LINK_CHG = 1<<10,
1687 WOL_CTL_ENA_PME_ON_MAGIC_PKT = 1<<9,
1688 WOL_CTL_DIS_PME_ON_MAGIC_PKT = 1<<8,
1689 WOL_CTL_ENA_PME_ON_PATTERN = 1<<7,
1690 WOL_CTL_DIS_PME_ON_PATTERN = 1<<6,
1691 WOL_CTL_ENA_LINK_CHG_UNIT = 1<<5,
1692 WOL_CTL_DIS_LINK_CHG_UNIT = 1<<4,
1693 WOL_CTL_ENA_MAGIC_PKT_UNIT = 1<<3,
1694 WOL_CTL_DIS_MAGIC_PKT_UNIT = 1<<2,
1695 WOL_CTL_ENA_PATTERN_UNIT = 1<<1,
1696 WOL_CTL_DIS_PATTERN_UNIT = 1<<0,
1697 };
1698
1699 #define WOL_CTL_DEFAULT \
1700 (WOL_CTL_DIS_PME_ON_LINK_CHG | \
1701 WOL_CTL_DIS_PME_ON_PATTERN | \
1702 WOL_CTL_DIS_PME_ON_MAGIC_PKT | \
1703 WOL_CTL_DIS_LINK_CHG_UNIT | \
1704 WOL_CTL_DIS_PATTERN_UNIT | \
1705 WOL_CTL_DIS_MAGIC_PKT_UNIT)
1706
1707 /* WOL_MATCH_CTL 8 bit WOL Match Control Reg */
1708 #define WOL_CTL_PATT_ENA(x) (1 << (x))
1709
1710
1711 /* Control flags */
1712 enum {
1713 UDPTCP = 1<<0,
1714 CALSUM = 1<<1,
1715 WR_SUM = 1<<2,
1716 INIT_SUM= 1<<3,
1717 LOCK_SUM= 1<<4,
1718 INS_VLAN= 1<<5,
1719 EOP = 1<<7,
1720 };
1721
1722 enum {
1723 HW_OWNER = 1<<7,
1724 OP_TCPWRITE = 0x11,
1725 OP_TCPSTART = 0x12,
1726 OP_TCPINIT = 0x14,
1727 OP_TCPLCK = 0x18,
1728 OP_TCPCHKSUM = OP_TCPSTART,
1729 OP_TCPIS = OP_TCPINIT | OP_TCPSTART,
1730 OP_TCPLW = OP_TCPLCK | OP_TCPWRITE,
1731 OP_TCPLSW = OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE,
1732 OP_TCPLISW = OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE,
1733
1734 OP_ADDR64 = 0x21,
1735 OP_VLAN = 0x22,
1736 OP_ADDR64VLAN = OP_ADDR64 | OP_VLAN,
1737 OP_LRGLEN = 0x24,
1738 OP_LRGLENVLAN = OP_LRGLEN | OP_VLAN,
1739 OP_BUFFER = 0x40,
1740 OP_PACKET = 0x41,
1741 OP_LARGESEND = 0x43,
1742
1743 /* YUKON-2 STATUS opcodes defines */
1744 OP_RXSTAT = 0x60,
1745 OP_RXTIMESTAMP = 0x61,
1746 OP_RXVLAN = 0x62,
1747 OP_RXCHKS = 0x64,
1748 OP_RXCHKSVLAN = OP_RXCHKS | OP_RXVLAN,
1749 OP_RXTIMEVLAN = OP_RXTIMESTAMP | OP_RXVLAN,
1750 OP_RSS_HASH = 0x65,
1751 OP_TXINDEXLE = 0x68,
1752 };
1753
1754 /* Yukon 2 hardware interface */
1755 struct sky2_tx_le {
1756 __le32 addr;
1757 __le16 length; /* also vlan tag or checksum start */
1758 u8 ctrl;
1759 u8 opcode;
1760 } __attribute((packed));
1761
1762 struct sky2_rx_le {
1763 __le32 addr;
1764 __le16 length;
1765 u8 ctrl;
1766 u8 opcode;
1767 } __attribute((packed));
1768
1769 struct sky2_status_le {
1770 __le32 status; /* also checksum */
1771 __le16 length; /* also vlan tag */
1772 u8 link;
1773 u8 opcode;
1774 } __attribute((packed));
1775
1776 struct tx_ring_info {
1777 struct sk_buff *skb;
1778 DECLARE_PCI_UNMAP_ADDR(mapaddr);
1779 DECLARE_PCI_UNMAP_ADDR(maplen);
1780 };
1781
1782 struct rx_ring_info {
1783 struct sk_buff *skb;
1784 dma_addr_t data_addr;
1785 DECLARE_PCI_UNMAP_ADDR(data_size);
1786 dma_addr_t frag_addr[ETH_JUMBO_MTU >> PAGE_SHIFT];
1787 };
1788
1789 struct sky2_port {
1790 struct sky2_hw *hw;
1791 struct net_device *netdev;
1792 unsigned port;
1793 u32 msg_enable;
1794 spinlock_t phy_lock;
1795
1796 struct tx_ring_info *tx_ring;
1797 struct sky2_tx_le *tx_le;
1798 u16 tx_cons; /* next le to check */
1799 u16 tx_prod; /* next le to use */
1800 u32 tx_addr64;
1801 u16 tx_pending;
1802 u16 tx_last_mss;
1803 u32 tx_tcpsum;
1804
1805 struct rx_ring_info *rx_ring ____cacheline_aligned_in_smp;
1806 struct sky2_rx_le *rx_le;
1807 u32 rx_addr64;
1808 u16 rx_next; /* next re to check */
1809 u16 rx_put; /* next le index to use */
1810 u16 rx_pending;
1811 u16 rx_data_size;
1812 u16 rx_nfrags;
1813
1814 #ifdef SKY2_VLAN_TAG_USED
1815 u16 rx_tag;
1816 struct vlan_group *vlgrp;
1817 #endif
1818
1819 dma_addr_t rx_le_map;
1820 dma_addr_t tx_le_map;
1821 u32 advertising; /* ADVERTISED_ bits */
1822 u16 speed; /* SPEED_1000, SPEED_100, ... */
1823 u8 autoneg; /* AUTONEG_ENABLE, AUTONEG_DISABLE */
1824 u8 duplex; /* DUPLEX_HALF, DUPLEX_FULL */
1825 u8 rx_pause;
1826 u8 tx_pause;
1827 u8 rx_csum;
1828
1829 struct net_device_stats net_stats;
1830
1831 };
1832
1833 struct sky2_hw {
1834 void __iomem *regs;
1835 struct pci_dev *pdev;
1836 struct net_device *dev[2];
1837
1838 int pm_cap;
1839 int err_cap;
1840 u8 chip_id;
1841 u8 chip_rev;
1842 u8 pmd_type;
1843 u8 ports;
1844
1845 struct sky2_status_le *st_le;
1846 u32 st_idx;
1847 dma_addr_t st_dma;
1848
1849 struct timer_list idle_timer;
1850 int msi_detected;
1851 wait_queue_head_t msi_wait;
1852 };
1853
1854 static inline int sky2_is_copper(const struct sky2_hw *hw)
1855 {
1856 return !(hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P');
1857 }
1858
1859 /* Register accessor for memory mapped device */
1860 static inline u32 sky2_read32(const struct sky2_hw *hw, unsigned reg)
1861 {
1862 return readl(hw->regs + reg);
1863 }
1864
1865 static inline u16 sky2_read16(const struct sky2_hw *hw, unsigned reg)
1866 {
1867 return readw(hw->regs + reg);
1868 }
1869
1870 static inline u8 sky2_read8(const struct sky2_hw *hw, unsigned reg)
1871 {
1872 return readb(hw->regs + reg);
1873 }
1874
1875 static inline void sky2_write32(const struct sky2_hw *hw, unsigned reg, u32 val)
1876 {
1877 writel(val, hw->regs + reg);
1878 }
1879
1880 static inline void sky2_write16(const struct sky2_hw *hw, unsigned reg, u16 val)
1881 {
1882 writew(val, hw->regs + reg);
1883 }
1884
1885 static inline void sky2_write8(const struct sky2_hw *hw, unsigned reg, u8 val)
1886 {
1887 writeb(val, hw->regs + reg);
1888 }
1889
1890 /* Yukon PHY related registers */
1891 #define SK_GMAC_REG(port,reg) \
1892 (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
1893 #define GM_PHY_RETRIES 100
1894
1895 static inline u16 gma_read16(const struct sky2_hw *hw, unsigned port, unsigned reg)
1896 {
1897 return sky2_read16(hw, SK_GMAC_REG(port,reg));
1898 }
1899
1900 static inline u32 gma_read32(struct sky2_hw *hw, unsigned port, unsigned reg)
1901 {
1902 unsigned base = SK_GMAC_REG(port, reg);
1903 return (u32) sky2_read16(hw, base)
1904 | (u32) sky2_read16(hw, base+4) << 16;
1905 }
1906
1907 static inline void gma_write16(const struct sky2_hw *hw, unsigned port, int r, u16 v)
1908 {
1909 sky2_write16(hw, SK_GMAC_REG(port,r), v);
1910 }
1911
1912 static inline void gma_set_addr(struct sky2_hw *hw, unsigned port, unsigned reg,
1913 const u8 *addr)
1914 {
1915 gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8));
1916 gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
1917 gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
1918 }
1919
1920 /* PCI config space access */
1921 static inline u32 sky2_pci_read32(const struct sky2_hw *hw, unsigned reg)
1922 {
1923 return sky2_read32(hw, Y2_CFG_SPC + reg);
1924 }
1925
1926 static inline u16 sky2_pci_read16(const struct sky2_hw *hw, unsigned reg)
1927 {
1928 return sky2_read16(hw, Y2_CFG_SPC + reg);
1929 }
1930
1931 static inline void sky2_pci_write32(struct sky2_hw *hw, unsigned reg, u32 val)
1932 {
1933 sky2_write32(hw, Y2_CFG_SPC + reg, val);
1934 }
1935
1936 static inline void sky2_pci_write16(struct sky2_hw *hw, unsigned reg, u16 val)
1937 {
1938 sky2_write16(hw, Y2_CFG_SPC + reg, val);
1939 }
1940 #endif
Linux kernel - Deliverables
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