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[PATCH] AT91RM9200 Ethernet: Add netpoll / netconsole support
[deliverable/linux.git] / drivers / net / smc91x.h
1 /*------------------------------------------------------------------------
2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
3 .
4 . Copyright (C) 1996 by Erik Stahlman
5 . Copyright (C) 2001 Standard Microsystems Corporation
6 . Developed by Simple Network Magic Corporation
7 . Copyright (C) 2003 Monta Vista Software, Inc.
8 . Unified SMC91x driver by Nicolas Pitre
9 .
10 . This program is free software; you can redistribute it and/or modify
11 . it under the terms of the GNU General Public License as published by
12 . the Free Software Foundation; either version 2 of the License, or
13 . (at your option) any later version.
14 .
15 . This program is distributed in the hope that it will be useful,
16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 . GNU General Public License for more details.
19 .
20 . You should have received a copy of the GNU General Public License
21 . along with this program; if not, write to the Free Software
22 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 .
24 . Information contained in this file was obtained from the LAN91C111
25 . manual from SMC. To get a copy, if you really want one, you can find
26 . information under www.smsc.com.
27 .
28 . Authors
29 . Erik Stahlman <erik@vt.edu>
30 . Daris A Nevil <dnevil@snmc.com>
31 . Nicolas Pitre <nico@cam.org>
32 .
33 ---------------------------------------------------------------------------*/
34 #ifndef _SMC91X_H_
35 #define _SMC91X_H_
36
37
38 /*
39 * Define your architecture specific bus configuration parameters here.
40 */
41
42 #if defined(CONFIG_ARCH_LUBBOCK)
43
44 /* We can only do 16-bit reads and writes in the static memory space. */
45 #define SMC_CAN_USE_8BIT 0
46 #define SMC_CAN_USE_16BIT 1
47 #define SMC_CAN_USE_32BIT 0
48 #define SMC_NOWAIT 1
49
50 /* The first two address lines aren't connected... */
51 #define SMC_IO_SHIFT 2
52
53 #define SMC_inw(a, r) readw((a) + (r))
54 #define SMC_outw(v, a, r) writew(v, (a) + (r))
55 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
56 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
57
58 #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
59
60 /* We can only do 16-bit reads and writes in the static memory space. */
61 #define SMC_CAN_USE_8BIT 0
62 #define SMC_CAN_USE_16BIT 1
63 #define SMC_CAN_USE_32BIT 0
64 #define SMC_NOWAIT 1
65
66 #define SMC_IO_SHIFT 0
67
68 #define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r)))
69 #define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v)
70 #define SMC_insw(a, r, p, l) \
71 do { \
72 unsigned long __port = (a) + (r); \
73 u16 *__p = (u16 *)(p); \
74 int __l = (l); \
75 insw(__port, __p, __l); \
76 while (__l > 0) { \
77 *__p = swab16(*__p); \
78 __p++; \
79 __l--; \
80 } \
81 } while (0)
82 #define SMC_outsw(a, r, p, l) \
83 do { \
84 unsigned long __port = (a) + (r); \
85 u16 *__p = (u16 *)(p); \
86 int __l = (l); \
87 while (__l > 0) { \
88 /* Believe it or not, the swab isn't needed. */ \
89 outw( /* swab16 */ (*__p++), __port); \
90 __l--; \
91 } \
92 } while (0)
93 #define SMC_IRQ_FLAGS (0)
94
95 #elif defined(CONFIG_SA1100_PLEB)
96 /* We can only do 16-bit reads and writes in the static memory space. */
97 #define SMC_CAN_USE_8BIT 1
98 #define SMC_CAN_USE_16BIT 1
99 #define SMC_CAN_USE_32BIT 0
100 #define SMC_IO_SHIFT 0
101 #define SMC_NOWAIT 1
102
103 #define SMC_inb(a, r) readb((a) + (r))
104 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
105 #define SMC_inw(a, r) readw((a) + (r))
106 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
107 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
108 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
109 #define SMC_outw(v, a, r) writew(v, (a) + (r))
110 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
111
112 #define SMC_IRQ_FLAGS (0)
113
114 #elif defined(CONFIG_SA1100_ASSABET)
115
116 #include <asm/arch/neponset.h>
117
118 /* We can only do 8-bit reads and writes in the static memory space. */
119 #define SMC_CAN_USE_8BIT 1
120 #define SMC_CAN_USE_16BIT 0
121 #define SMC_CAN_USE_32BIT 0
122 #define SMC_NOWAIT 1
123
124 /* The first two address lines aren't connected... */
125 #define SMC_IO_SHIFT 2
126
127 #define SMC_inb(a, r) readb((a) + (r))
128 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
129 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
130 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
131
132 #elif defined(CONFIG_MACH_LOGICPD_PXA270)
133
134 #define SMC_CAN_USE_8BIT 0
135 #define SMC_CAN_USE_16BIT 1
136 #define SMC_CAN_USE_32BIT 0
137 #define SMC_IO_SHIFT 0
138 #define SMC_NOWAIT 1
139
140 #define SMC_inw(a, r) readw((a) + (r))
141 #define SMC_outw(v, a, r) writew(v, (a) + (r))
142 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
143 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
144
145 #elif defined(CONFIG_ARCH_INNOKOM) || \
146 defined(CONFIG_MACH_MAINSTONE) || \
147 defined(CONFIG_ARCH_PXA_IDP) || \
148 defined(CONFIG_ARCH_RAMSES)
149
150 #define SMC_CAN_USE_8BIT 1
151 #define SMC_CAN_USE_16BIT 1
152 #define SMC_CAN_USE_32BIT 1
153 #define SMC_IO_SHIFT 0
154 #define SMC_NOWAIT 1
155 #define SMC_USE_PXA_DMA 1
156
157 #define SMC_inb(a, r) readb((a) + (r))
158 #define SMC_inw(a, r) readw((a) + (r))
159 #define SMC_inl(a, r) readl((a) + (r))
160 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
161 #define SMC_outl(v, a, r) writel(v, (a) + (r))
162 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
163 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
164
165 /* We actually can't write halfwords properly if not word aligned */
166 static inline void
167 SMC_outw(u16 val, void __iomem *ioaddr, int reg)
168 {
169 if (reg & 2) {
170 unsigned int v = val << 16;
171 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
172 writel(v, ioaddr + (reg & ~2));
173 } else {
174 writew(val, ioaddr + reg);
175 }
176 }
177
178 #elif defined(CONFIG_ARCH_OMAP)
179
180 /* We can only do 16-bit reads and writes in the static memory space. */
181 #define SMC_CAN_USE_8BIT 0
182 #define SMC_CAN_USE_16BIT 1
183 #define SMC_CAN_USE_32BIT 0
184 #define SMC_IO_SHIFT 0
185 #define SMC_NOWAIT 1
186
187 #define SMC_inw(a, r) readw((a) + (r))
188 #define SMC_outw(v, a, r) writew(v, (a) + (r))
189 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
190 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
191
192 #include <asm/mach-types.h>
193 #include <asm/arch/cpu.h>
194
195 #define SMC_IRQ_FLAGS (( \
196 machine_is_omap_h2() \
197 || machine_is_omap_h3() \
198 || machine_is_omap_h4() \
199 || (machine_is_omap_innovator() && !cpu_is_omap1510()) \
200 ) ? IRQF_TRIGGER_FALLING : IRQF_TRIGGER_RISING)
201
202
203 #elif defined(CONFIG_SH_SH4202_MICRODEV)
204
205 #define SMC_CAN_USE_8BIT 0
206 #define SMC_CAN_USE_16BIT 1
207 #define SMC_CAN_USE_32BIT 0
208
209 #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
210 #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
211 #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
212 #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
213 #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
214 #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
215 #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
216 #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
217 #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
218 #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
219
220 #define SMC_IRQ_FLAGS (0)
221
222 #elif defined(CONFIG_ISA)
223
224 #define SMC_CAN_USE_8BIT 1
225 #define SMC_CAN_USE_16BIT 1
226 #define SMC_CAN_USE_32BIT 0
227
228 #define SMC_inb(a, r) inb((a) + (r))
229 #define SMC_inw(a, r) inw((a) + (r))
230 #define SMC_outb(v, a, r) outb(v, (a) + (r))
231 #define SMC_outw(v, a, r) outw(v, (a) + (r))
232 #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
233 #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
234
235 #elif defined(CONFIG_M32R)
236
237 #define SMC_CAN_USE_8BIT 0
238 #define SMC_CAN_USE_16BIT 1
239 #define SMC_CAN_USE_32BIT 0
240
241 #define SMC_inb(a, r) inb(((u32)a) + (r))
242 #define SMC_inw(a, r) inw(((u32)a) + (r))
243 #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r))
244 #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r))
245 #define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l)
246 #define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l)
247
248 #define SMC_IRQ_FLAGS (0)
249
250 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
251 #define RPC_LSB_DEFAULT RPC_LED_100_10
252
253 #elif defined(CONFIG_MACH_LPD79520) \
254 || defined(CONFIG_MACH_LPD7A400) \
255 || defined(CONFIG_MACH_LPD7A404)
256
257 /* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the
258 * way that the CPU handles chip selects and the way that the SMC chip
259 * expects the chip select to operate. Refer to
260 * Documentation/arm/Sharp-LH/IOBarrier for details. The read from
261 * IOBARRIER is a byte, in order that we read the least-common
262 * denominator. It would be wasteful to read 32 bits from an 8-bit
263 * accessible region.
264 *
265 * There is no explicit protection against interrupts intervening
266 * between the writew and the IOBARRIER. In SMC ISR there is a
267 * preamble that performs an IOBARRIER in the extremely unlikely event
268 * that the driver interrupts itself between a writew to the chip an
269 * the IOBARRIER that follows *and* the cache is large enough that the
270 * first off-chip access while handing the interrupt is to the SMC
271 * chip. Other devices in the same address space as the SMC chip must
272 * be aware of the potential for trouble and perform a similar
273 * IOBARRIER on entry to their ISR.
274 */
275
276 #include <asm/arch/constants.h> /* IOBARRIER_VIRT */
277
278 #define SMC_CAN_USE_8BIT 0
279 #define SMC_CAN_USE_16BIT 1
280 #define SMC_CAN_USE_32BIT 0
281 #define SMC_NOWAIT 0
282 #define LPD7X_IOBARRIER readb (IOBARRIER_VIRT)
283
284 #define SMC_inw(a,r)\
285 ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; })
286 #define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; })
287
288 #define SMC_insw LPD7_SMC_insw
289 static inline void LPD7_SMC_insw (unsigned char* a, int r,
290 unsigned char* p, int l)
291 {
292 unsigned short* ps = (unsigned short*) p;
293 while (l-- > 0) {
294 *ps++ = readw (a + r);
295 LPD7X_IOBARRIER;
296 }
297 }
298
299 #define SMC_outsw LPD7_SMC_outsw
300 static inline void LPD7_SMC_outsw (unsigned char* a, int r,
301 unsigned char* p, int l)
302 {
303 unsigned short* ps = (unsigned short*) p;
304 while (l-- > 0) {
305 writew (*ps++, a + r);
306 LPD7X_IOBARRIER;
307 }
308 }
309
310 #define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIER
311
312 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
313 #define RPC_LSB_DEFAULT RPC_LED_100_10
314
315 #elif defined(CONFIG_SOC_AU1X00)
316
317 #include <au1xxx.h>
318
319 /* We can only do 16-bit reads and writes in the static memory space. */
320 #define SMC_CAN_USE_8BIT 0
321 #define SMC_CAN_USE_16BIT 1
322 #define SMC_CAN_USE_32BIT 0
323 #define SMC_IO_SHIFT 0
324 #define SMC_NOWAIT 1
325
326 #define SMC_inw(a, r) au_readw((unsigned long)((a) + (r)))
327 #define SMC_insw(a, r, p, l) \
328 do { \
329 unsigned long _a = (unsigned long)((a) + (r)); \
330 int _l = (l); \
331 u16 *_p = (u16 *)(p); \
332 while (_l-- > 0) \
333 *_p++ = au_readw(_a); \
334 } while(0)
335 #define SMC_outw(v, a, r) au_writew(v, (unsigned long)((a) + (r)))
336 #define SMC_outsw(a, r, p, l) \
337 do { \
338 unsigned long _a = (unsigned long)((a) + (r)); \
339 int _l = (l); \
340 const u16 *_p = (const u16 *)(p); \
341 while (_l-- > 0) \
342 au_writew(*_p++ , _a); \
343 } while(0)
344
345 #define SMC_IRQ_FLAGS (0)
346
347 #elif defined(CONFIG_ARCH_VERSATILE)
348
349 #define SMC_CAN_USE_8BIT 1
350 #define SMC_CAN_USE_16BIT 1
351 #define SMC_CAN_USE_32BIT 1
352 #define SMC_NOWAIT 1
353
354 #define SMC_inb(a, r) readb((a) + (r))
355 #define SMC_inw(a, r) readw((a) + (r))
356 #define SMC_inl(a, r) readl((a) + (r))
357 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
358 #define SMC_outw(v, a, r) writew(v, (a) + (r))
359 #define SMC_outl(v, a, r) writel(v, (a) + (r))
360 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
361 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
362
363 #define SMC_IRQ_FLAGS (0)
364
365 #elif defined(CONFIG_ARCH_VERSATILE)
366
367 #define SMC_CAN_USE_8BIT 1
368 #define SMC_CAN_USE_16BIT 1
369 #define SMC_CAN_USE_32BIT 1
370 #define SMC_NOWAIT 1
371
372 #define SMC_inb(a, r) readb((a) + (r))
373 #define SMC_inw(a, r) readw((a) + (r))
374 #define SMC_inl(a, r) readl((a) + (r))
375 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
376 #define SMC_outw(v, a, r) writew(v, (a) + (r))
377 #define SMC_outl(v, a, r) writel(v, (a) + (r))
378 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
379 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
380
381 #define SMC_IRQ_FLAGS (0)
382
383 #elif defined(CONFIG_ARCH_VERSATILE)
384
385 #define SMC_CAN_USE_8BIT 1
386 #define SMC_CAN_USE_16BIT 1
387 #define SMC_CAN_USE_32BIT 1
388 #define SMC_NOWAIT 1
389
390 #define SMC_inb(a, r) readb((a) + (r))
391 #define SMC_inw(a, r) readw((a) + (r))
392 #define SMC_inl(a, r) readl((a) + (r))
393 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
394 #define SMC_outw(v, a, r) writew(v, (a) + (r))
395 #define SMC_outl(v, a, r) writel(v, (a) + (r))
396 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
397 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
398
399 #define SMC_IRQ_FLAGS (0)
400
401 #elif defined(CONFIG_ARCH_VERSATILE)
402
403 #define SMC_CAN_USE_8BIT 1
404 #define SMC_CAN_USE_16BIT 1
405 #define SMC_CAN_USE_32BIT 1
406 #define SMC_NOWAIT 1
407
408 #define SMC_inb(a, r) readb((a) + (r))
409 #define SMC_inw(a, r) readw((a) + (r))
410 #define SMC_inl(a, r) readl((a) + (r))
411 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
412 #define SMC_outw(v, a, r) writew(v, (a) + (r))
413 #define SMC_outl(v, a, r) writel(v, (a) + (r))
414 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
415 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
416
417 #define SMC_IRQ_FLAGS (0)
418
419 #elif defined(CONFIG_ARCH_VERSATILE)
420
421 #define SMC_CAN_USE_8BIT 1
422 #define SMC_CAN_USE_16BIT 1
423 #define SMC_CAN_USE_32BIT 1
424 #define SMC_NOWAIT 1
425
426 #define SMC_inb(a, r) readb((a) + (r))
427 #define SMC_inw(a, r) readw((a) + (r))
428 #define SMC_inl(a, r) readl((a) + (r))
429 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
430 #define SMC_outw(v, a, r) writew(v, (a) + (r))
431 #define SMC_outl(v, a, r) writel(v, (a) + (r))
432 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
433 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
434
435 #define SMC_IRQ_FLAGS (0)
436
437 #elif defined(CONFIG_ARCH_VERSATILE)
438
439 #define SMC_CAN_USE_8BIT 1
440 #define SMC_CAN_USE_16BIT 1
441 #define SMC_CAN_USE_32BIT 1
442 #define SMC_NOWAIT 1
443
444 #define SMC_inb(a, r) readb((a) + (r))
445 #define SMC_inw(a, r) readw((a) + (r))
446 #define SMC_inl(a, r) readl((a) + (r))
447 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
448 #define SMC_outw(v, a, r) writew(v, (a) + (r))
449 #define SMC_outl(v, a, r) writel(v, (a) + (r))
450 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
451 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
452
453 #define SMC_IRQ_FLAGS (0)
454
455 #else
456
457 #define SMC_CAN_USE_8BIT 1
458 #define SMC_CAN_USE_16BIT 1
459 #define SMC_CAN_USE_32BIT 1
460 #define SMC_NOWAIT 1
461
462 #define SMC_inb(a, r) readb((a) + (r))
463 #define SMC_inw(a, r) readw((a) + (r))
464 #define SMC_inl(a, r) readl((a) + (r))
465 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
466 #define SMC_outw(v, a, r) writew(v, (a) + (r))
467 #define SMC_outl(v, a, r) writel(v, (a) + (r))
468 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
469 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
470
471 #define RPC_LSA_DEFAULT RPC_LED_100_10
472 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
473
474 #endif
475
476 #ifdef SMC_USE_PXA_DMA
477 /*
478 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
479 * always happening in irq context so no need to worry about races. TX is
480 * different and probably not worth it for that reason, and not as critical
481 * as RX which can overrun memory and lose packets.
482 */
483 #include <linux/dma-mapping.h>
484 #include <asm/dma.h>
485 #include <asm/arch/pxa-regs.h>
486
487 #ifdef SMC_insl
488 #undef SMC_insl
489 #define SMC_insl(a, r, p, l) \
490 smc_pxa_dma_insl(a, lp->physaddr, r, dev->dma, p, l)
491 static inline void
492 smc_pxa_dma_insl(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
493 u_char *buf, int len)
494 {
495 dma_addr_t dmabuf;
496
497 /* fallback if no DMA available */
498 if (dma == (unsigned char)-1) {
499 readsl(ioaddr + reg, buf, len);
500 return;
501 }
502
503 /* 64 bit alignment is required for memory to memory DMA */
504 if ((long)buf & 4) {
505 *((u32 *)buf) = SMC_inl(ioaddr, reg);
506 buf += 4;
507 len--;
508 }
509
510 len *= 4;
511 dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE);
512 DCSR(dma) = DCSR_NODESC;
513 DTADR(dma) = dmabuf;
514 DSADR(dma) = physaddr + reg;
515 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
516 DCMD_WIDTH4 | (DCMD_LENGTH & len));
517 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
518 while (!(DCSR(dma) & DCSR_STOPSTATE))
519 cpu_relax();
520 DCSR(dma) = 0;
521 dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE);
522 }
523 #endif
524
525 #ifdef SMC_insw
526 #undef SMC_insw
527 #define SMC_insw(a, r, p, l) \
528 smc_pxa_dma_insw(a, lp->physaddr, r, dev->dma, p, l)
529 static inline void
530 smc_pxa_dma_insw(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
531 u_char *buf, int len)
532 {
533 dma_addr_t dmabuf;
534
535 /* fallback if no DMA available */
536 if (dma == (unsigned char)-1) {
537 readsw(ioaddr + reg, buf, len);
538 return;
539 }
540
541 /* 64 bit alignment is required for memory to memory DMA */
542 while ((long)buf & 6) {
543 *((u16 *)buf) = SMC_inw(ioaddr, reg);
544 buf += 2;
545 len--;
546 }
547
548 len *= 2;
549 dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE);
550 DCSR(dma) = DCSR_NODESC;
551 DTADR(dma) = dmabuf;
552 DSADR(dma) = physaddr + reg;
553 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
554 DCMD_WIDTH2 | (DCMD_LENGTH & len));
555 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
556 while (!(DCSR(dma) & DCSR_STOPSTATE))
557 cpu_relax();
558 DCSR(dma) = 0;
559 dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE);
560 }
561 #endif
562
563 static void
564 smc_pxa_dma_irq(int dma, void *dummy)
565 {
566 DCSR(dma) = 0;
567 }
568 #endif /* SMC_USE_PXA_DMA */
569
570
571 /*
572 * Everything a particular hardware setup needs should have been defined
573 * at this point. Add stubs for the undefined cases, mainly to avoid
574 * compilation warnings since they'll be optimized away, or to prevent buggy
575 * use of them.
576 */
577
578 #if ! SMC_CAN_USE_32BIT
579 #define SMC_inl(ioaddr, reg) ({ BUG(); 0; })
580 #define SMC_outl(x, ioaddr, reg) BUG()
581 #define SMC_insl(a, r, p, l) BUG()
582 #define SMC_outsl(a, r, p, l) BUG()
583 #endif
584
585 #if !defined(SMC_insl) || !defined(SMC_outsl)
586 #define SMC_insl(a, r, p, l) BUG()
587 #define SMC_outsl(a, r, p, l) BUG()
588 #endif
589
590 #if ! SMC_CAN_USE_16BIT
591
592 /*
593 * Any 16-bit access is performed with two 8-bit accesses if the hardware
594 * can't do it directly. Most registers are 16-bit so those are mandatory.
595 */
596 #define SMC_outw(x, ioaddr, reg) \
597 do { \
598 unsigned int __val16 = (x); \
599 SMC_outb( __val16, ioaddr, reg ); \
600 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
601 } while (0)
602 #define SMC_inw(ioaddr, reg) \
603 ({ \
604 unsigned int __val16; \
605 __val16 = SMC_inb( ioaddr, reg ); \
606 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
607 __val16; \
608 })
609
610 #define SMC_insw(a, r, p, l) BUG()
611 #define SMC_outsw(a, r, p, l) BUG()
612
613 #endif
614
615 #if !defined(SMC_insw) || !defined(SMC_outsw)
616 #define SMC_insw(a, r, p, l) BUG()
617 #define SMC_outsw(a, r, p, l) BUG()
618 #endif
619
620 #if ! SMC_CAN_USE_8BIT
621 #define SMC_inb(ioaddr, reg) ({ BUG(); 0; })
622 #define SMC_outb(x, ioaddr, reg) BUG()
623 #define SMC_insb(a, r, p, l) BUG()
624 #define SMC_outsb(a, r, p, l) BUG()
625 #endif
626
627 #if !defined(SMC_insb) || !defined(SMC_outsb)
628 #define SMC_insb(a, r, p, l) BUG()
629 #define SMC_outsb(a, r, p, l) BUG()
630 #endif
631
632 #ifndef SMC_CAN_USE_DATACS
633 #define SMC_CAN_USE_DATACS 0
634 #endif
635
636 #ifndef SMC_IO_SHIFT
637 #define SMC_IO_SHIFT 0
638 #endif
639
640 #ifndef SMC_IRQ_FLAGS
641 #define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING
642 #endif
643
644 #ifndef SMC_INTERRUPT_PREAMBLE
645 #define SMC_INTERRUPT_PREAMBLE
646 #endif
647
648
649 /* Because of bank switching, the LAN91x uses only 16 I/O ports */
650 #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
651 #define SMC_DATA_EXTENT (4)
652
653 /*
654 . Bank Select Register:
655 .
656 . yyyy yyyy 0000 00xx
657 . xx = bank number
658 . yyyy yyyy = 0x33, for identification purposes.
659 */
660 #define BANK_SELECT (14 << SMC_IO_SHIFT)
661
662
663 // Transmit Control Register
664 /* BANK 0 */
665 #define TCR_REG SMC_REG(0x0000, 0)
666 #define TCR_ENABLE 0x0001 // When 1 we can transmit
667 #define TCR_LOOP 0x0002 // Controls output pin LBK
668 #define TCR_FORCOL 0x0004 // When 1 will force a collision
669 #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
670 #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
671 #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
672 #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
673 #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
674 #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
675 #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
676
677 #define TCR_CLEAR 0 /* do NOTHING */
678 /* the default settings for the TCR register : */
679 #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
680
681
682 // EPH Status Register
683 /* BANK 0 */
684 #define EPH_STATUS_REG SMC_REG(0x0002, 0)
685 #define ES_TX_SUC 0x0001 // Last TX was successful
686 #define ES_SNGL_COL 0x0002 // Single collision detected for last tx
687 #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
688 #define ES_LTX_MULT 0x0008 // Last tx was a multicast
689 #define ES_16COL 0x0010 // 16 Collisions Reached
690 #define ES_SQET 0x0020 // Signal Quality Error Test
691 #define ES_LTXBRD 0x0040 // Last tx was a broadcast
692 #define ES_TXDEFR 0x0080 // Transmit Deferred
693 #define ES_LATCOL 0x0200 // Late collision detected on last tx
694 #define ES_LOSTCARR 0x0400 // Lost Carrier Sense
695 #define ES_EXC_DEF 0x0800 // Excessive Deferral
696 #define ES_CTR_ROL 0x1000 // Counter Roll Over indication
697 #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
698 #define ES_TXUNRN 0x8000 // Tx Underrun
699
700
701 // Receive Control Register
702 /* BANK 0 */
703 #define RCR_REG SMC_REG(0x0004, 0)
704 #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
705 #define RCR_PRMS 0x0002 // Enable promiscuous mode
706 #define RCR_ALMUL 0x0004 // When set accepts all multicast frames
707 #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
708 #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
709 #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
710 #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
711 #define RCR_SOFTRST 0x8000 // resets the chip
712
713 /* the normal settings for the RCR register : */
714 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
715 #define RCR_CLEAR 0x0 // set it to a base state
716
717
718 // Counter Register
719 /* BANK 0 */
720 #define COUNTER_REG SMC_REG(0x0006, 0)
721
722
723 // Memory Information Register
724 /* BANK 0 */
725 #define MIR_REG SMC_REG(0x0008, 0)
726
727
728 // Receive/Phy Control Register
729 /* BANK 0 */
730 #define RPC_REG SMC_REG(0x000A, 0)
731 #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
732 #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
733 #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
734 #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
735 #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
736 #define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect
737 #define RPC_LED_RES (0x01) // LED = Reserved
738 #define RPC_LED_10 (0x02) // LED = 10Mbps link detect
739 #define RPC_LED_FD (0x03) // LED = Full Duplex Mode
740 #define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
741 #define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
742 #define RPC_LED_TX (0x06) // LED = TX packet occurred
743 #define RPC_LED_RX (0x07) // LED = RX packet occurred
744
745 #ifndef RPC_LSA_DEFAULT
746 #define RPC_LSA_DEFAULT RPC_LED_100
747 #endif
748 #ifndef RPC_LSB_DEFAULT
749 #define RPC_LSB_DEFAULT RPC_LED_FD
750 #endif
751
752 #define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
753
754
755 /* Bank 0 0x0C is reserved */
756
757 // Bank Select Register
758 /* All Banks */
759 #define BSR_REG 0x000E
760
761
762 // Configuration Reg
763 /* BANK 1 */
764 #define CONFIG_REG SMC_REG(0x0000, 1)
765 #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
766 #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
767 #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
768 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
769
770 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
771 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
772
773
774 // Base Address Register
775 /* BANK 1 */
776 #define BASE_REG SMC_REG(0x0002, 1)
777
778
779 // Individual Address Registers
780 /* BANK 1 */
781 #define ADDR0_REG SMC_REG(0x0004, 1)
782 #define ADDR1_REG SMC_REG(0x0006, 1)
783 #define ADDR2_REG SMC_REG(0x0008, 1)
784
785
786 // General Purpose Register
787 /* BANK 1 */
788 #define GP_REG SMC_REG(0x000A, 1)
789
790
791 // Control Register
792 /* BANK 1 */
793 #define CTL_REG SMC_REG(0x000C, 1)
794 #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
795 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
796 #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
797 #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
798 #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
799 #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
800 #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
801 #define CTL_STORE 0x0001 // When set stores registers into EEPROM
802
803
804 // MMU Command Register
805 /* BANK 2 */
806 #define MMU_CMD_REG SMC_REG(0x0000, 2)
807 #define MC_BUSY 1 // When 1 the last release has not completed
808 #define MC_NOP (0<<5) // No Op
809 #define MC_ALLOC (1<<5) // OR with number of 256 byte packets
810 #define MC_RESET (2<<5) // Reset MMU to initial state
811 #define MC_REMOVE (3<<5) // Remove the current rx packet
812 #define MC_RELEASE (4<<5) // Remove and release the current rx packet
813 #define MC_FREEPKT (5<<5) // Release packet in PNR register
814 #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
815 #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
816
817
818 // Packet Number Register
819 /* BANK 2 */
820 #define PN_REG SMC_REG(0x0002, 2)
821
822
823 // Allocation Result Register
824 /* BANK 2 */
825 #define AR_REG SMC_REG(0x0003, 2)
826 #define AR_FAILED 0x80 // Alocation Failed
827
828
829 // TX FIFO Ports Register
830 /* BANK 2 */
831 #define TXFIFO_REG SMC_REG(0x0004, 2)
832 #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
833
834 // RX FIFO Ports Register
835 /* BANK 2 */
836 #define RXFIFO_REG SMC_REG(0x0005, 2)
837 #define RXFIFO_REMPTY 0x80 // RX FIFO Empty
838
839 #define FIFO_REG SMC_REG(0x0004, 2)
840
841 // Pointer Register
842 /* BANK 2 */
843 #define PTR_REG SMC_REG(0x0006, 2)
844 #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
845 #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
846 #define PTR_READ 0x2000 // When 1 the operation is a read
847
848
849 // Data Register
850 /* BANK 2 */
851 #define DATA_REG SMC_REG(0x0008, 2)
852
853
854 // Interrupt Status/Acknowledge Register
855 /* BANK 2 */
856 #define INT_REG SMC_REG(0x000C, 2)
857
858
859 // Interrupt Mask Register
860 /* BANK 2 */
861 #define IM_REG SMC_REG(0x000D, 2)
862 #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
863 #define IM_ERCV_INT 0x40 // Early Receive Interrupt
864 #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
865 #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
866 #define IM_ALLOC_INT 0x08 // Set when allocation request is completed
867 #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
868 #define IM_TX_INT 0x02 // Transmit Interrupt
869 #define IM_RCV_INT 0x01 // Receive Interrupt
870
871
872 // Multicast Table Registers
873 /* BANK 3 */
874 #define MCAST_REG1 SMC_REG(0x0000, 3)
875 #define MCAST_REG2 SMC_REG(0x0002, 3)
876 #define MCAST_REG3 SMC_REG(0x0004, 3)
877 #define MCAST_REG4 SMC_REG(0x0006, 3)
878
879
880 // Management Interface Register (MII)
881 /* BANK 3 */
882 #define MII_REG SMC_REG(0x0008, 3)
883 #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
884 #define MII_MDOE 0x0008 // MII Output Enable
885 #define MII_MCLK 0x0004 // MII Clock, pin MDCLK
886 #define MII_MDI 0x0002 // MII Input, pin MDI
887 #define MII_MDO 0x0001 // MII Output, pin MDO
888
889
890 // Revision Register
891 /* BANK 3 */
892 /* ( hi: chip id low: rev # ) */
893 #define REV_REG SMC_REG(0x000A, 3)
894
895
896 // Early RCV Register
897 /* BANK 3 */
898 /* this is NOT on SMC9192 */
899 #define ERCV_REG SMC_REG(0x000C, 3)
900 #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
901 #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
902
903
904 // External Register
905 /* BANK 7 */
906 #define EXT_REG SMC_REG(0x0000, 7)
907
908
909 #define CHIP_9192 3
910 #define CHIP_9194 4
911 #define CHIP_9195 5
912 #define CHIP_9196 6
913 #define CHIP_91100 7
914 #define CHIP_91100FD 8
915 #define CHIP_91111FD 9
916
917 static const char * chip_ids[ 16 ] = {
918 NULL, NULL, NULL,
919 /* 3 */ "SMC91C90/91C92",
920 /* 4 */ "SMC91C94",
921 /* 5 */ "SMC91C95",
922 /* 6 */ "SMC91C96",
923 /* 7 */ "SMC91C100",
924 /* 8 */ "SMC91C100FD",
925 /* 9 */ "SMC91C11xFD",
926 NULL, NULL, NULL,
927 NULL, NULL, NULL};
928
929
930 /*
931 . Receive status bits
932 */
933 #define RS_ALGNERR 0x8000
934 #define RS_BRODCAST 0x4000
935 #define RS_BADCRC 0x2000
936 #define RS_ODDFRAME 0x1000
937 #define RS_TOOLONG 0x0800
938 #define RS_TOOSHORT 0x0400
939 #define RS_MULTICAST 0x0001
940 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
941
942
943 /*
944 * PHY IDs
945 * LAN83C183 == LAN91C111 Internal PHY
946 */
947 #define PHY_LAN83C183 0x0016f840
948 #define PHY_LAN83C180 0x02821c50
949
950 /*
951 * PHY Register Addresses (LAN91C111 Internal PHY)
952 *
953 * Generic PHY registers can be found in <linux/mii.h>
954 *
955 * These phy registers are specific to our on-board phy.
956 */
957
958 // PHY Configuration Register 1
959 #define PHY_CFG1_REG 0x10
960 #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
961 #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
962 #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
963 #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
964 #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
965 #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
966 #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
967 #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
968 #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
969 #define PHY_CFG1_TLVL_MASK 0x003C
970 #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
971
972
973 // PHY Configuration Register 2
974 #define PHY_CFG2_REG 0x11
975 #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
976 #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
977 #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
978 #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
979
980 // PHY Status Output (and Interrupt status) Register
981 #define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
982 #define PHY_INT_INT 0x8000 // 1=bits have changed since last read
983 #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
984 #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
985 #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
986 #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
987 #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
988 #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
989 #define PHY_INT_JAB 0x0100 // 1=Jabber detected
990 #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
991 #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
992
993 // PHY Interrupt/Status Mask Register
994 #define PHY_MASK_REG 0x13 // Interrupt Mask
995 // Uses the same bit definitions as PHY_INT_REG
996
997
998 /*
999 * SMC91C96 ethernet config and status registers.
1000 * These are in the "attribute" space.
1001 */
1002 #define ECOR 0x8000
1003 #define ECOR_RESET 0x80
1004 #define ECOR_LEVEL_IRQ 0x40
1005 #define ECOR_WR_ATTRIB 0x04
1006 #define ECOR_ENABLE 0x01
1007
1008 #define ECSR 0x8002
1009 #define ECSR_IOIS8 0x20
1010 #define ECSR_PWRDWN 0x04
1011 #define ECSR_INT 0x02
1012
1013 #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
1014
1015
1016 /*
1017 * Macros to abstract register access according to the data bus
1018 * capabilities. Please use those and not the in/out primitives.
1019 * Note: the following macros do *not* select the bank -- this must
1020 * be done separately as needed in the main code. The SMC_REG() macro
1021 * only uses the bank argument for debugging purposes (when enabled).
1022 *
1023 * Note: despite inline functions being safer, everything leading to this
1024 * should preferably be macros to let BUG() display the line number in
1025 * the core source code since we're interested in the top call site
1026 * not in any inline function location.
1027 */
1028
1029 #if SMC_DEBUG > 0
1030 #define SMC_REG(reg, bank) \
1031 ({ \
1032 int __b = SMC_CURRENT_BANK(); \
1033 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
1034 printk( "%s: bank reg screwed (0x%04x)\n", \
1035 CARDNAME, __b ); \
1036 BUG(); \
1037 } \
1038 reg<<SMC_IO_SHIFT; \
1039 })
1040 #else
1041 #define SMC_REG(reg, bank) (reg<<SMC_IO_SHIFT)
1042 #endif
1043
1044 /*
1045 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
1046 * aligned to a 32 bit boundary. I tell you that does exist!
1047 * Fortunately the affected register accesses can be easily worked around
1048 * since we can write zeroes to the preceeding 16 bits without adverse
1049 * effects and use a 32-bit access.
1050 *
1051 * Enforce it on any 32-bit capable setup for now.
1052 */
1053 #define SMC_MUST_ALIGN_WRITE SMC_CAN_USE_32BIT
1054
1055 #define SMC_GET_PN() \
1056 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, PN_REG)) \
1057 : (SMC_inw(ioaddr, PN_REG) & 0xFF) )
1058
1059 #define SMC_SET_PN(x) \
1060 do { \
1061 if (SMC_MUST_ALIGN_WRITE) \
1062 SMC_outl((x)<<16, ioaddr, SMC_REG(0, 2)); \
1063 else if (SMC_CAN_USE_8BIT) \
1064 SMC_outb(x, ioaddr, PN_REG); \
1065 else \
1066 SMC_outw(x, ioaddr, PN_REG); \
1067 } while (0)
1068
1069 #define SMC_GET_AR() \
1070 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, AR_REG)) \
1071 : (SMC_inw(ioaddr, PN_REG) >> 8) )
1072
1073 #define SMC_GET_TXFIFO() \
1074 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, TXFIFO_REG)) \
1075 : (SMC_inw(ioaddr, TXFIFO_REG) & 0xFF) )
1076
1077 #define SMC_GET_RXFIFO() \
1078 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, RXFIFO_REG)) \
1079 : (SMC_inw(ioaddr, TXFIFO_REG) >> 8) )
1080
1081 #define SMC_GET_INT() \
1082 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, INT_REG)) \
1083 : (SMC_inw(ioaddr, INT_REG) & 0xFF) )
1084
1085 #define SMC_ACK_INT(x) \
1086 do { \
1087 if (SMC_CAN_USE_8BIT) \
1088 SMC_outb(x, ioaddr, INT_REG); \
1089 else { \
1090 unsigned long __flags; \
1091 int __mask; \
1092 local_irq_save(__flags); \
1093 __mask = SMC_inw( ioaddr, INT_REG ) & ~0xff; \
1094 SMC_outw( __mask | (x), ioaddr, INT_REG ); \
1095 local_irq_restore(__flags); \
1096 } \
1097 } while (0)
1098
1099 #define SMC_GET_INT_MASK() \
1100 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, IM_REG)) \
1101 : (SMC_inw( ioaddr, INT_REG ) >> 8) )
1102
1103 #define SMC_SET_INT_MASK(x) \
1104 do { \
1105 if (SMC_CAN_USE_8BIT) \
1106 SMC_outb(x, ioaddr, IM_REG); \
1107 else \
1108 SMC_outw((x) << 8, ioaddr, INT_REG); \
1109 } while (0)
1110
1111 #define SMC_CURRENT_BANK() SMC_inw(ioaddr, BANK_SELECT)
1112
1113 #define SMC_SELECT_BANK(x) \
1114 do { \
1115 if (SMC_MUST_ALIGN_WRITE) \
1116 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
1117 else \
1118 SMC_outw(x, ioaddr, BANK_SELECT); \
1119 } while (0)
1120
1121 #define SMC_GET_BASE() SMC_inw(ioaddr, BASE_REG)
1122
1123 #define SMC_SET_BASE(x) SMC_outw(x, ioaddr, BASE_REG)
1124
1125 #define SMC_GET_CONFIG() SMC_inw(ioaddr, CONFIG_REG)
1126
1127 #define SMC_SET_CONFIG(x) SMC_outw(x, ioaddr, CONFIG_REG)
1128
1129 #define SMC_GET_COUNTER() SMC_inw(ioaddr, COUNTER_REG)
1130
1131 #define SMC_GET_CTL() SMC_inw(ioaddr, CTL_REG)
1132
1133 #define SMC_SET_CTL(x) SMC_outw(x, ioaddr, CTL_REG)
1134
1135 #define SMC_GET_MII() SMC_inw(ioaddr, MII_REG)
1136
1137 #define SMC_SET_MII(x) SMC_outw(x, ioaddr, MII_REG)
1138
1139 #define SMC_GET_MIR() SMC_inw(ioaddr, MIR_REG)
1140
1141 #define SMC_SET_MIR(x) SMC_outw(x, ioaddr, MIR_REG)
1142
1143 #define SMC_GET_MMU_CMD() SMC_inw(ioaddr, MMU_CMD_REG)
1144
1145 #define SMC_SET_MMU_CMD(x) SMC_outw(x, ioaddr, MMU_CMD_REG)
1146
1147 #define SMC_GET_FIFO() SMC_inw(ioaddr, FIFO_REG)
1148
1149 #define SMC_GET_PTR() SMC_inw(ioaddr, PTR_REG)
1150
1151 #define SMC_SET_PTR(x) \
1152 do { \
1153 if (SMC_MUST_ALIGN_WRITE) \
1154 SMC_outl((x)<<16, ioaddr, SMC_REG(4, 2)); \
1155 else \
1156 SMC_outw(x, ioaddr, PTR_REG); \
1157 } while (0)
1158
1159 #define SMC_GET_EPH_STATUS() SMC_inw(ioaddr, EPH_STATUS_REG)
1160
1161 #define SMC_GET_RCR() SMC_inw(ioaddr, RCR_REG)
1162
1163 #define SMC_SET_RCR(x) SMC_outw(x, ioaddr, RCR_REG)
1164
1165 #define SMC_GET_REV() SMC_inw(ioaddr, REV_REG)
1166
1167 #define SMC_GET_RPC() SMC_inw(ioaddr, RPC_REG)
1168
1169 #define SMC_SET_RPC(x) \
1170 do { \
1171 if (SMC_MUST_ALIGN_WRITE) \
1172 SMC_outl((x)<<16, ioaddr, SMC_REG(8, 0)); \
1173 else \
1174 SMC_outw(x, ioaddr, RPC_REG); \
1175 } while (0)
1176
1177 #define SMC_GET_TCR() SMC_inw(ioaddr, TCR_REG)
1178
1179 #define SMC_SET_TCR(x) SMC_outw(x, ioaddr, TCR_REG)
1180
1181 #ifndef SMC_GET_MAC_ADDR
1182 #define SMC_GET_MAC_ADDR(addr) \
1183 do { \
1184 unsigned int __v; \
1185 __v = SMC_inw( ioaddr, ADDR0_REG ); \
1186 addr[0] = __v; addr[1] = __v >> 8; \
1187 __v = SMC_inw( ioaddr, ADDR1_REG ); \
1188 addr[2] = __v; addr[3] = __v >> 8; \
1189 __v = SMC_inw( ioaddr, ADDR2_REG ); \
1190 addr[4] = __v; addr[5] = __v >> 8; \
1191 } while (0)
1192 #endif
1193
1194 #define SMC_SET_MAC_ADDR(addr) \
1195 do { \
1196 SMC_outw( addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG ); \
1197 SMC_outw( addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG ); \
1198 SMC_outw( addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG ); \
1199 } while (0)
1200
1201 #define SMC_SET_MCAST(x) \
1202 do { \
1203 const unsigned char *mt = (x); \
1204 SMC_outw( mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1 ); \
1205 SMC_outw( mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2 ); \
1206 SMC_outw( mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3 ); \
1207 SMC_outw( mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4 ); \
1208 } while (0)
1209
1210 #define SMC_PUT_PKT_HDR(status, length) \
1211 do { \
1212 if (SMC_CAN_USE_32BIT) \
1213 SMC_outl((status) | (length)<<16, ioaddr, DATA_REG); \
1214 else { \
1215 SMC_outw(status, ioaddr, DATA_REG); \
1216 SMC_outw(length, ioaddr, DATA_REG); \
1217 } \
1218 } while (0)
1219
1220 #define SMC_GET_PKT_HDR(status, length) \
1221 do { \
1222 if (SMC_CAN_USE_32BIT) { \
1223 unsigned int __val = SMC_inl(ioaddr, DATA_REG); \
1224 (status) = __val & 0xffff; \
1225 (length) = __val >> 16; \
1226 } else { \
1227 (status) = SMC_inw(ioaddr, DATA_REG); \
1228 (length) = SMC_inw(ioaddr, DATA_REG); \
1229 } \
1230 } while (0)
1231
1232 #define SMC_PUSH_DATA(p, l) \
1233 do { \
1234 if (SMC_CAN_USE_32BIT) { \
1235 void *__ptr = (p); \
1236 int __len = (l); \
1237 void __iomem *__ioaddr = ioaddr; \
1238 if (__len >= 2 && (unsigned long)__ptr & 2) { \
1239 __len -= 2; \
1240 SMC_outw(*(u16 *)__ptr, ioaddr, DATA_REG); \
1241 __ptr += 2; \
1242 } \
1243 if (SMC_CAN_USE_DATACS && lp->datacs) \
1244 __ioaddr = lp->datacs; \
1245 SMC_outsl(__ioaddr, DATA_REG, __ptr, __len>>2); \
1246 if (__len & 2) { \
1247 __ptr += (__len & ~3); \
1248 SMC_outw(*((u16 *)__ptr), ioaddr, DATA_REG); \
1249 } \
1250 } else if (SMC_CAN_USE_16BIT) \
1251 SMC_outsw(ioaddr, DATA_REG, p, (l) >> 1); \
1252 else if (SMC_CAN_USE_8BIT) \
1253 SMC_outsb(ioaddr, DATA_REG, p, l); \
1254 } while (0)
1255
1256 #define SMC_PULL_DATA(p, l) \
1257 do { \
1258 if (SMC_CAN_USE_32BIT) { \
1259 void *__ptr = (p); \
1260 int __len = (l); \
1261 void __iomem *__ioaddr = ioaddr; \
1262 if ((unsigned long)__ptr & 2) { \
1263 /* \
1264 * We want 32bit alignment here. \
1265 * Since some buses perform a full \
1266 * 32bit fetch even for 16bit data \
1267 * we can't use SMC_inw() here. \
1268 * Back both source (on-chip) and \
1269 * destination pointers of 2 bytes. \
1270 * This is possible since the call to \
1271 * SMC_GET_PKT_HDR() already advanced \
1272 * the source pointer of 4 bytes, and \
1273 * the skb_reserve(skb, 2) advanced \
1274 * the destination pointer of 2 bytes. \
1275 */ \
1276 __ptr -= 2; \
1277 __len += 2; \
1278 SMC_SET_PTR(2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1279 } \
1280 if (SMC_CAN_USE_DATACS && lp->datacs) \
1281 __ioaddr = lp->datacs; \
1282 __len += 2; \
1283 SMC_insl(__ioaddr, DATA_REG, __ptr, __len>>2); \
1284 } else if (SMC_CAN_USE_16BIT) \
1285 SMC_insw(ioaddr, DATA_REG, p, (l) >> 1); \
1286 else if (SMC_CAN_USE_8BIT) \
1287 SMC_insb(ioaddr, DATA_REG, p, l); \
1288 } while (0)
1289
1290 #endif /* _SMC91X_H_ */
Linux kernel - Deliverables
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