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Merge master.kernel.org:/home/rmk/linux-2.6-arm
[deliverable/linux.git] / drivers / net / sungem.c
1 /* $Id: sungem.c,v 1.44.2.22 2002/03/13 01:18:12 davem Exp $
2 * sungem.c: Sun GEM ethernet driver.
3 *
4 * Copyright (C) 2000, 2001, 2002, 2003 David S. Miller (davem@redhat.com)
5 *
6 * Support for Apple GMAC and assorted PHYs, WOL, Power Management
7 * (C) 2001,2002,2003 Benjamin Herrenscmidt (benh@kernel.crashing.org)
8 * (C) 2004,2005 Benjamin Herrenscmidt, IBM Corp.
9 *
10 * NAPI and NETPOLL support
11 * (C) 2004 by Eric Lemoine (eric.lemoine@gmail.com)
12 *
13 * TODO:
14 * - Now that the driver was significantly simplified, I need to rework
15 * the locking. I'm sure we don't need _2_ spinlocks, and we probably
16 * can avoid taking most of them for so long period of time (and schedule
17 * instead). The main issues at this point are caused by the netdev layer
18 * though:
19 *
20 * gem_change_mtu() and gem_set_multicast() are called with a read_lock()
21 * help by net/core/dev.c, thus they can't schedule. That means they can't
22 * call netif_poll_disable() neither, thus force gem_poll() to keep a spinlock
23 * where it could have been dropped. change_mtu especially would love also to
24 * be able to msleep instead of horrid locked delays when resetting the HW,
25 * but that read_lock() makes it impossible, unless I defer it's action to
26 * the reset task, which means it'll be asynchronous (won't take effect until
27 * the system schedules a bit).
28 *
29 * Also, it would probably be possible to also remove most of the long-life
30 * locking in open/resume code path (gem_reinit_chip) by beeing more careful
31 * about when we can start taking interrupts or get xmit() called...
32 */
33
34 #include <linux/module.h>
35 #include <linux/kernel.h>
36 #include <linux/types.h>
37 #include <linux/fcntl.h>
38 #include <linux/interrupt.h>
39 #include <linux/ioport.h>
40 #include <linux/in.h>
41 #include <linux/slab.h>
42 #include <linux/string.h>
43 #include <linux/delay.h>
44 #include <linux/init.h>
45 #include <linux/errno.h>
46 #include <linux/pci.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/netdevice.h>
49 #include <linux/etherdevice.h>
50 #include <linux/skbuff.h>
51 #include <linux/mii.h>
52 #include <linux/ethtool.h>
53 #include <linux/crc32.h>
54 #include <linux/random.h>
55 #include <linux/workqueue.h>
56 #include <linux/if_vlan.h>
57 #include <linux/bitops.h>
58
59 #include <asm/system.h>
60 #include <asm/io.h>
61 #include <asm/byteorder.h>
62 #include <asm/uaccess.h>
63 #include <asm/irq.h>
64
65 #ifdef __sparc__
66 #include <asm/idprom.h>
67 #include <asm/openprom.h>
68 #include <asm/oplib.h>
69 #include <asm/pbm.h>
70 #endif
71
72 #ifdef CONFIG_PPC_PMAC
73 #include <asm/pci-bridge.h>
74 #include <asm/prom.h>
75 #include <asm/machdep.h>
76 #include <asm/pmac_feature.h>
77 #endif
78
79 #include "sungem_phy.h"
80 #include "sungem.h"
81
82 /* Stripping FCS is causing problems, disabled for now */
83 #undef STRIP_FCS
84
85 #define DEFAULT_MSG (NETIF_MSG_DRV | \
86 NETIF_MSG_PROBE | \
87 NETIF_MSG_LINK)
88
89 #define ADVERTISE_MASK (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
90 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
91 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)
92
93 #define DRV_NAME "sungem"
94 #define DRV_VERSION "0.98"
95 #define DRV_RELDATE "8/24/03"
96 #define DRV_AUTHOR "David S. Miller (davem@redhat.com)"
97
98 static char version[] __devinitdata =
99 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
100
101 MODULE_AUTHOR(DRV_AUTHOR);
102 MODULE_DESCRIPTION("Sun GEM Gbit ethernet driver");
103 MODULE_LICENSE("GPL");
104
105 #define GEM_MODULE_NAME "gem"
106 #define PFX GEM_MODULE_NAME ": "
107
108 static struct pci_device_id gem_pci_tbl[] = {
109 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_GEM,
110 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
111
112 /* These models only differ from the original GEM in
113 * that their tx/rx fifos are of a different size and
114 * they only support 10/100 speeds. -DaveM
115 *
116 * Apple's GMAC does support gigabit on machines with
117 * the BCM54xx PHYs. -BenH
118 */
119 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_RIO_GEM,
120 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
121 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC,
122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
123 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMACP,
124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
125 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC2,
126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
127 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_GMAC,
128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
129 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_SUNGEM,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
131 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID2_GMAC,
132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
133 {0, }
134 };
135
136 MODULE_DEVICE_TABLE(pci, gem_pci_tbl);
137
138 static u16 __phy_read(struct gem *gp, int phy_addr, int reg)
139 {
140 u32 cmd;
141 int limit = 10000;
142
143 cmd = (1 << 30);
144 cmd |= (2 << 28);
145 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
146 cmd |= (reg << 18) & MIF_FRAME_REGAD;
147 cmd |= (MIF_FRAME_TAMSB);
148 writel(cmd, gp->regs + MIF_FRAME);
149
150 while (limit--) {
151 cmd = readl(gp->regs + MIF_FRAME);
152 if (cmd & MIF_FRAME_TALSB)
153 break;
154
155 udelay(10);
156 }
157
158 if (!limit)
159 cmd = 0xffff;
160
161 return cmd & MIF_FRAME_DATA;
162 }
163
164 static inline int _phy_read(struct net_device *dev, int mii_id, int reg)
165 {
166 struct gem *gp = dev->priv;
167 return __phy_read(gp, mii_id, reg);
168 }
169
170 static inline u16 phy_read(struct gem *gp, int reg)
171 {
172 return __phy_read(gp, gp->mii_phy_addr, reg);
173 }
174
175 static void __phy_write(struct gem *gp, int phy_addr, int reg, u16 val)
176 {
177 u32 cmd;
178 int limit = 10000;
179
180 cmd = (1 << 30);
181 cmd |= (1 << 28);
182 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
183 cmd |= (reg << 18) & MIF_FRAME_REGAD;
184 cmd |= (MIF_FRAME_TAMSB);
185 cmd |= (val & MIF_FRAME_DATA);
186 writel(cmd, gp->regs + MIF_FRAME);
187
188 while (limit--) {
189 cmd = readl(gp->regs + MIF_FRAME);
190 if (cmd & MIF_FRAME_TALSB)
191 break;
192
193 udelay(10);
194 }
195 }
196
197 static inline void _phy_write(struct net_device *dev, int mii_id, int reg, int val)
198 {
199 struct gem *gp = dev->priv;
200 __phy_write(gp, mii_id, reg, val & 0xffff);
201 }
202
203 static inline void phy_write(struct gem *gp, int reg, u16 val)
204 {
205 __phy_write(gp, gp->mii_phy_addr, reg, val);
206 }
207
208 static inline void gem_enable_ints(struct gem *gp)
209 {
210 /* Enable all interrupts but TXDONE */
211 writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
212 }
213
214 static inline void gem_disable_ints(struct gem *gp)
215 {
216 /* Disable all interrupts, including TXDONE */
217 writel(GREG_STAT_NAPI | GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
218 }
219
220 static void gem_get_cell(struct gem *gp)
221 {
222 BUG_ON(gp->cell_enabled < 0);
223 gp->cell_enabled++;
224 #ifdef CONFIG_PPC_PMAC
225 if (gp->cell_enabled == 1) {
226 mb();
227 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 1);
228 udelay(10);
229 }
230 #endif /* CONFIG_PPC_PMAC */
231 }
232
233 /* Turn off the chip's clock */
234 static void gem_put_cell(struct gem *gp)
235 {
236 BUG_ON(gp->cell_enabled <= 0);
237 gp->cell_enabled--;
238 #ifdef CONFIG_PPC_PMAC
239 if (gp->cell_enabled == 0) {
240 mb();
241 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 0);
242 udelay(10);
243 }
244 #endif /* CONFIG_PPC_PMAC */
245 }
246
247 static void gem_handle_mif_event(struct gem *gp, u32 reg_val, u32 changed_bits)
248 {
249 if (netif_msg_intr(gp))
250 printk(KERN_DEBUG "%s: mif interrupt\n", gp->dev->name);
251 }
252
253 static int gem_pcs_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
254 {
255 u32 pcs_istat = readl(gp->regs + PCS_ISTAT);
256 u32 pcs_miistat;
257
258 if (netif_msg_intr(gp))
259 printk(KERN_DEBUG "%s: pcs interrupt, pcs_istat: 0x%x\n",
260 gp->dev->name, pcs_istat);
261
262 if (!(pcs_istat & PCS_ISTAT_LSC)) {
263 printk(KERN_ERR "%s: PCS irq but no link status change???\n",
264 dev->name);
265 return 0;
266 }
267
268 /* The link status bit latches on zero, so you must
269 * read it twice in such a case to see a transition
270 * to the link being up.
271 */
272 pcs_miistat = readl(gp->regs + PCS_MIISTAT);
273 if (!(pcs_miistat & PCS_MIISTAT_LS))
274 pcs_miistat |=
275 (readl(gp->regs + PCS_MIISTAT) &
276 PCS_MIISTAT_LS);
277
278 if (pcs_miistat & PCS_MIISTAT_ANC) {
279 /* The remote-fault indication is only valid
280 * when autoneg has completed.
281 */
282 if (pcs_miistat & PCS_MIISTAT_RF)
283 printk(KERN_INFO "%s: PCS AutoNEG complete, "
284 "RemoteFault\n", dev->name);
285 else
286 printk(KERN_INFO "%s: PCS AutoNEG complete.\n",
287 dev->name);
288 }
289
290 if (pcs_miistat & PCS_MIISTAT_LS) {
291 printk(KERN_INFO "%s: PCS link is now up.\n",
292 dev->name);
293 netif_carrier_on(gp->dev);
294 } else {
295 printk(KERN_INFO "%s: PCS link is now down.\n",
296 dev->name);
297 netif_carrier_off(gp->dev);
298 /* If this happens and the link timer is not running,
299 * reset so we re-negotiate.
300 */
301 if (!timer_pending(&gp->link_timer))
302 return 1;
303 }
304
305 return 0;
306 }
307
308 static int gem_txmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
309 {
310 u32 txmac_stat = readl(gp->regs + MAC_TXSTAT);
311
312 if (netif_msg_intr(gp))
313 printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n",
314 gp->dev->name, txmac_stat);
315
316 /* Defer timer expiration is quite normal,
317 * don't even log the event.
318 */
319 if ((txmac_stat & MAC_TXSTAT_DTE) &&
320 !(txmac_stat & ~MAC_TXSTAT_DTE))
321 return 0;
322
323 if (txmac_stat & MAC_TXSTAT_URUN) {
324 printk(KERN_ERR "%s: TX MAC xmit underrun.\n",
325 dev->name);
326 gp->net_stats.tx_fifo_errors++;
327 }
328
329 if (txmac_stat & MAC_TXSTAT_MPE) {
330 printk(KERN_ERR "%s: TX MAC max packet size error.\n",
331 dev->name);
332 gp->net_stats.tx_errors++;
333 }
334
335 /* The rest are all cases of one of the 16-bit TX
336 * counters expiring.
337 */
338 if (txmac_stat & MAC_TXSTAT_NCE)
339 gp->net_stats.collisions += 0x10000;
340
341 if (txmac_stat & MAC_TXSTAT_ECE) {
342 gp->net_stats.tx_aborted_errors += 0x10000;
343 gp->net_stats.collisions += 0x10000;
344 }
345
346 if (txmac_stat & MAC_TXSTAT_LCE) {
347 gp->net_stats.tx_aborted_errors += 0x10000;
348 gp->net_stats.collisions += 0x10000;
349 }
350
351 /* We do not keep track of MAC_TXSTAT_FCE and
352 * MAC_TXSTAT_PCE events.
353 */
354 return 0;
355 }
356
357 /* When we get a RX fifo overflow, the RX unit in GEM is probably hung
358 * so we do the following.
359 *
360 * If any part of the reset goes wrong, we return 1 and that causes the
361 * whole chip to be reset.
362 */
363 static int gem_rxmac_reset(struct gem *gp)
364 {
365 struct net_device *dev = gp->dev;
366 int limit, i;
367 u64 desc_dma;
368 u32 val;
369
370 /* First, reset & disable MAC RX. */
371 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
372 for (limit = 0; limit < 5000; limit++) {
373 if (!(readl(gp->regs + MAC_RXRST) & MAC_RXRST_CMD))
374 break;
375 udelay(10);
376 }
377 if (limit == 5000) {
378 printk(KERN_ERR "%s: RX MAC will not reset, resetting whole "
379 "chip.\n", dev->name);
380 return 1;
381 }
382
383 writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB,
384 gp->regs + MAC_RXCFG);
385 for (limit = 0; limit < 5000; limit++) {
386 if (!(readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB))
387 break;
388 udelay(10);
389 }
390 if (limit == 5000) {
391 printk(KERN_ERR "%s: RX MAC will not disable, resetting whole "
392 "chip.\n", dev->name);
393 return 1;
394 }
395
396 /* Second, disable RX DMA. */
397 writel(0, gp->regs + RXDMA_CFG);
398 for (limit = 0; limit < 5000; limit++) {
399 if (!(readl(gp->regs + RXDMA_CFG) & RXDMA_CFG_ENABLE))
400 break;
401 udelay(10);
402 }
403 if (limit == 5000) {
404 printk(KERN_ERR "%s: RX DMA will not disable, resetting whole "
405 "chip.\n", dev->name);
406 return 1;
407 }
408
409 udelay(5000);
410
411 /* Execute RX reset command. */
412 writel(gp->swrst_base | GREG_SWRST_RXRST,
413 gp->regs + GREG_SWRST);
414 for (limit = 0; limit < 5000; limit++) {
415 if (!(readl(gp->regs + GREG_SWRST) & GREG_SWRST_RXRST))
416 break;
417 udelay(10);
418 }
419 if (limit == 5000) {
420 printk(KERN_ERR "%s: RX reset command will not execute, resetting "
421 "whole chip.\n", dev->name);
422 return 1;
423 }
424
425 /* Refresh the RX ring. */
426 for (i = 0; i < RX_RING_SIZE; i++) {
427 struct gem_rxd *rxd = &gp->init_block->rxd[i];
428
429 if (gp->rx_skbs[i] == NULL) {
430 printk(KERN_ERR "%s: Parts of RX ring empty, resetting "
431 "whole chip.\n", dev->name);
432 return 1;
433 }
434
435 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
436 }
437 gp->rx_new = gp->rx_old = 0;
438
439 /* Now we must reprogram the rest of RX unit. */
440 desc_dma = (u64) gp->gblock_dvma;
441 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
442 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
443 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
444 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
445 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
446 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
447 writel(val, gp->regs + RXDMA_CFG);
448 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
449 writel(((5 & RXDMA_BLANK_IPKTS) |
450 ((8 << 12) & RXDMA_BLANK_ITIME)),
451 gp->regs + RXDMA_BLANK);
452 else
453 writel(((5 & RXDMA_BLANK_IPKTS) |
454 ((4 << 12) & RXDMA_BLANK_ITIME)),
455 gp->regs + RXDMA_BLANK);
456 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
457 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
458 writel(val, gp->regs + RXDMA_PTHRESH);
459 val = readl(gp->regs + RXDMA_CFG);
460 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
461 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
462 val = readl(gp->regs + MAC_RXCFG);
463 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
464
465 return 0;
466 }
467
468 static int gem_rxmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
469 {
470 u32 rxmac_stat = readl(gp->regs + MAC_RXSTAT);
471 int ret = 0;
472
473 if (netif_msg_intr(gp))
474 printk(KERN_DEBUG "%s: rxmac interrupt, rxmac_stat: 0x%x\n",
475 gp->dev->name, rxmac_stat);
476
477 if (rxmac_stat & MAC_RXSTAT_OFLW) {
478 u32 smac = readl(gp->regs + MAC_SMACHINE);
479
480 printk(KERN_ERR "%s: RX MAC fifo overflow smac[%08x].\n",
481 dev->name, smac);
482 gp->net_stats.rx_over_errors++;
483 gp->net_stats.rx_fifo_errors++;
484
485 ret = gem_rxmac_reset(gp);
486 }
487
488 if (rxmac_stat & MAC_RXSTAT_ACE)
489 gp->net_stats.rx_frame_errors += 0x10000;
490
491 if (rxmac_stat & MAC_RXSTAT_CCE)
492 gp->net_stats.rx_crc_errors += 0x10000;
493
494 if (rxmac_stat & MAC_RXSTAT_LCE)
495 gp->net_stats.rx_length_errors += 0x10000;
496
497 /* We do not track MAC_RXSTAT_FCE and MAC_RXSTAT_VCE
498 * events.
499 */
500 return ret;
501 }
502
503 static int gem_mac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
504 {
505 u32 mac_cstat = readl(gp->regs + MAC_CSTAT);
506
507 if (netif_msg_intr(gp))
508 printk(KERN_DEBUG "%s: mac interrupt, mac_cstat: 0x%x\n",
509 gp->dev->name, mac_cstat);
510
511 /* This interrupt is just for pause frame and pause
512 * tracking. It is useful for diagnostics and debug
513 * but probably by default we will mask these events.
514 */
515 if (mac_cstat & MAC_CSTAT_PS)
516 gp->pause_entered++;
517
518 if (mac_cstat & MAC_CSTAT_PRCV)
519 gp->pause_last_time_recvd = (mac_cstat >> 16);
520
521 return 0;
522 }
523
524 static int gem_mif_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
525 {
526 u32 mif_status = readl(gp->regs + MIF_STATUS);
527 u32 reg_val, changed_bits;
528
529 reg_val = (mif_status & MIF_STATUS_DATA) >> 16;
530 changed_bits = (mif_status & MIF_STATUS_STAT);
531
532 gem_handle_mif_event(gp, reg_val, changed_bits);
533
534 return 0;
535 }
536
537 static int gem_pci_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
538 {
539 u32 pci_estat = readl(gp->regs + GREG_PCIESTAT);
540
541 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
542 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
543 printk(KERN_ERR "%s: PCI error [%04x] ",
544 dev->name, pci_estat);
545
546 if (pci_estat & GREG_PCIESTAT_BADACK)
547 printk("<No ACK64# during ABS64 cycle> ");
548 if (pci_estat & GREG_PCIESTAT_DTRTO)
549 printk("<Delayed transaction timeout> ");
550 if (pci_estat & GREG_PCIESTAT_OTHER)
551 printk("<other>");
552 printk("\n");
553 } else {
554 pci_estat |= GREG_PCIESTAT_OTHER;
555 printk(KERN_ERR "%s: PCI error\n", dev->name);
556 }
557
558 if (pci_estat & GREG_PCIESTAT_OTHER) {
559 u16 pci_cfg_stat;
560
561 /* Interrogate PCI config space for the
562 * true cause.
563 */
564 pci_read_config_word(gp->pdev, PCI_STATUS,
565 &pci_cfg_stat);
566 printk(KERN_ERR "%s: Read PCI cfg space status [%04x]\n",
567 dev->name, pci_cfg_stat);
568 if (pci_cfg_stat & PCI_STATUS_PARITY)
569 printk(KERN_ERR "%s: PCI parity error detected.\n",
570 dev->name);
571 if (pci_cfg_stat & PCI_STATUS_SIG_TARGET_ABORT)
572 printk(KERN_ERR "%s: PCI target abort.\n",
573 dev->name);
574 if (pci_cfg_stat & PCI_STATUS_REC_TARGET_ABORT)
575 printk(KERN_ERR "%s: PCI master acks target abort.\n",
576 dev->name);
577 if (pci_cfg_stat & PCI_STATUS_REC_MASTER_ABORT)
578 printk(KERN_ERR "%s: PCI master abort.\n",
579 dev->name);
580 if (pci_cfg_stat & PCI_STATUS_SIG_SYSTEM_ERROR)
581 printk(KERN_ERR "%s: PCI system error SERR#.\n",
582 dev->name);
583 if (pci_cfg_stat & PCI_STATUS_DETECTED_PARITY)
584 printk(KERN_ERR "%s: PCI parity error.\n",
585 dev->name);
586
587 /* Write the error bits back to clear them. */
588 pci_cfg_stat &= (PCI_STATUS_PARITY |
589 PCI_STATUS_SIG_TARGET_ABORT |
590 PCI_STATUS_REC_TARGET_ABORT |
591 PCI_STATUS_REC_MASTER_ABORT |
592 PCI_STATUS_SIG_SYSTEM_ERROR |
593 PCI_STATUS_DETECTED_PARITY);
594 pci_write_config_word(gp->pdev,
595 PCI_STATUS, pci_cfg_stat);
596 }
597
598 /* For all PCI errors, we should reset the chip. */
599 return 1;
600 }
601
602 /* All non-normal interrupt conditions get serviced here.
603 * Returns non-zero if we should just exit the interrupt
604 * handler right now (ie. if we reset the card which invalidates
605 * all of the other original irq status bits).
606 */
607 static int gem_abnormal_irq(struct net_device *dev, struct gem *gp, u32 gem_status)
608 {
609 if (gem_status & GREG_STAT_RXNOBUF) {
610 /* Frame arrived, no free RX buffers available. */
611 if (netif_msg_rx_err(gp))
612 printk(KERN_DEBUG "%s: no buffer for rx frame\n",
613 gp->dev->name);
614 gp->net_stats.rx_dropped++;
615 }
616
617 if (gem_status & GREG_STAT_RXTAGERR) {
618 /* corrupt RX tag framing */
619 if (netif_msg_rx_err(gp))
620 printk(KERN_DEBUG "%s: corrupt rx tag framing\n",
621 gp->dev->name);
622 gp->net_stats.rx_errors++;
623
624 goto do_reset;
625 }
626
627 if (gem_status & GREG_STAT_PCS) {
628 if (gem_pcs_interrupt(dev, gp, gem_status))
629 goto do_reset;
630 }
631
632 if (gem_status & GREG_STAT_TXMAC) {
633 if (gem_txmac_interrupt(dev, gp, gem_status))
634 goto do_reset;
635 }
636
637 if (gem_status & GREG_STAT_RXMAC) {
638 if (gem_rxmac_interrupt(dev, gp, gem_status))
639 goto do_reset;
640 }
641
642 if (gem_status & GREG_STAT_MAC) {
643 if (gem_mac_interrupt(dev, gp, gem_status))
644 goto do_reset;
645 }
646
647 if (gem_status & GREG_STAT_MIF) {
648 if (gem_mif_interrupt(dev, gp, gem_status))
649 goto do_reset;
650 }
651
652 if (gem_status & GREG_STAT_PCIERR) {
653 if (gem_pci_interrupt(dev, gp, gem_status))
654 goto do_reset;
655 }
656
657 return 0;
658
659 do_reset:
660 gp->reset_task_pending = 1;
661 schedule_work(&gp->reset_task);
662
663 return 1;
664 }
665
666 static __inline__ void gem_tx(struct net_device *dev, struct gem *gp, u32 gem_status)
667 {
668 int entry, limit;
669
670 if (netif_msg_intr(gp))
671 printk(KERN_DEBUG "%s: tx interrupt, gem_status: 0x%x\n",
672 gp->dev->name, gem_status);
673
674 entry = gp->tx_old;
675 limit = ((gem_status & GREG_STAT_TXNR) >> GREG_STAT_TXNR_SHIFT);
676 while (entry != limit) {
677 struct sk_buff *skb;
678 struct gem_txd *txd;
679 dma_addr_t dma_addr;
680 u32 dma_len;
681 int frag;
682
683 if (netif_msg_tx_done(gp))
684 printk(KERN_DEBUG "%s: tx done, slot %d\n",
685 gp->dev->name, entry);
686 skb = gp->tx_skbs[entry];
687 if (skb_shinfo(skb)->nr_frags) {
688 int last = entry + skb_shinfo(skb)->nr_frags;
689 int walk = entry;
690 int incomplete = 0;
691
692 last &= (TX_RING_SIZE - 1);
693 for (;;) {
694 walk = NEXT_TX(walk);
695 if (walk == limit)
696 incomplete = 1;
697 if (walk == last)
698 break;
699 }
700 if (incomplete)
701 break;
702 }
703 gp->tx_skbs[entry] = NULL;
704 gp->net_stats.tx_bytes += skb->len;
705
706 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
707 txd = &gp->init_block->txd[entry];
708
709 dma_addr = le64_to_cpu(txd->buffer);
710 dma_len = le64_to_cpu(txd->control_word) & TXDCTRL_BUFSZ;
711
712 pci_unmap_page(gp->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
713 entry = NEXT_TX(entry);
714 }
715
716 gp->net_stats.tx_packets++;
717 dev_kfree_skb_irq(skb);
718 }
719 gp->tx_old = entry;
720
721 if (netif_queue_stopped(dev) &&
722 TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))
723 netif_wake_queue(dev);
724 }
725
726 static __inline__ void gem_post_rxds(struct gem *gp, int limit)
727 {
728 int cluster_start, curr, count, kick;
729
730 cluster_start = curr = (gp->rx_new & ~(4 - 1));
731 count = 0;
732 kick = -1;
733 wmb();
734 while (curr != limit) {
735 curr = NEXT_RX(curr);
736 if (++count == 4) {
737 struct gem_rxd *rxd =
738 &gp->init_block->rxd[cluster_start];
739 for (;;) {
740 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
741 rxd++;
742 cluster_start = NEXT_RX(cluster_start);
743 if (cluster_start == curr)
744 break;
745 }
746 kick = curr;
747 count = 0;
748 }
749 }
750 if (kick >= 0) {
751 mb();
752 writel(kick, gp->regs + RXDMA_KICK);
753 }
754 }
755
756 static int gem_rx(struct gem *gp, int work_to_do)
757 {
758 int entry, drops, work_done = 0;
759 u32 done;
760
761 if (netif_msg_rx_status(gp))
762 printk(KERN_DEBUG "%s: rx interrupt, done: %d, rx_new: %d\n",
763 gp->dev->name, readl(gp->regs + RXDMA_DONE), gp->rx_new);
764
765 entry = gp->rx_new;
766 drops = 0;
767 done = readl(gp->regs + RXDMA_DONE);
768 for (;;) {
769 struct gem_rxd *rxd = &gp->init_block->rxd[entry];
770 struct sk_buff *skb;
771 u64 status = cpu_to_le64(rxd->status_word);
772 dma_addr_t dma_addr;
773 int len;
774
775 if ((status & RXDCTRL_OWN) != 0)
776 break;
777
778 if (work_done >= RX_RING_SIZE || work_done >= work_to_do)
779 break;
780
781 /* When writing back RX descriptor, GEM writes status
782 * then buffer address, possibly in seperate transactions.
783 * If we don't wait for the chip to write both, we could
784 * post a new buffer to this descriptor then have GEM spam
785 * on the buffer address. We sync on the RX completion
786 * register to prevent this from happening.
787 */
788 if (entry == done) {
789 done = readl(gp->regs + RXDMA_DONE);
790 if (entry == done)
791 break;
792 }
793
794 /* We can now account for the work we're about to do */
795 work_done++;
796
797 skb = gp->rx_skbs[entry];
798
799 len = (status & RXDCTRL_BUFSZ) >> 16;
800 if ((len < ETH_ZLEN) || (status & RXDCTRL_BAD)) {
801 gp->net_stats.rx_errors++;
802 if (len < ETH_ZLEN)
803 gp->net_stats.rx_length_errors++;
804 if (len & RXDCTRL_BAD)
805 gp->net_stats.rx_crc_errors++;
806
807 /* We'll just return it to GEM. */
808 drop_it:
809 gp->net_stats.rx_dropped++;
810 goto next;
811 }
812
813 dma_addr = cpu_to_le64(rxd->buffer);
814 if (len > RX_COPY_THRESHOLD) {
815 struct sk_buff *new_skb;
816
817 new_skb = gem_alloc_skb(RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
818 if (new_skb == NULL) {
819 drops++;
820 goto drop_it;
821 }
822 pci_unmap_page(gp->pdev, dma_addr,
823 RX_BUF_ALLOC_SIZE(gp),
824 PCI_DMA_FROMDEVICE);
825 gp->rx_skbs[entry] = new_skb;
826 new_skb->dev = gp->dev;
827 skb_put(new_skb, (gp->rx_buf_sz + RX_OFFSET));
828 rxd->buffer = cpu_to_le64(pci_map_page(gp->pdev,
829 virt_to_page(new_skb->data),
830 offset_in_page(new_skb->data),
831 RX_BUF_ALLOC_SIZE(gp),
832 PCI_DMA_FROMDEVICE));
833 skb_reserve(new_skb, RX_OFFSET);
834
835 /* Trim the original skb for the netif. */
836 skb_trim(skb, len);
837 } else {
838 struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
839
840 if (copy_skb == NULL) {
841 drops++;
842 goto drop_it;
843 }
844
845 copy_skb->dev = gp->dev;
846 skb_reserve(copy_skb, 2);
847 skb_put(copy_skb, len);
848 pci_dma_sync_single_for_cpu(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
849 memcpy(copy_skb->data, skb->data, len);
850 pci_dma_sync_single_for_device(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
851
852 /* We'll reuse the original ring buffer. */
853 skb = copy_skb;
854 }
855
856 skb->csum = ntohs((status & RXDCTRL_TCPCSUM) ^ 0xffff);
857 skb->ip_summed = CHECKSUM_HW;
858 skb->protocol = eth_type_trans(skb, gp->dev);
859
860 netif_receive_skb(skb);
861
862 gp->net_stats.rx_packets++;
863 gp->net_stats.rx_bytes += len;
864 gp->dev->last_rx = jiffies;
865
866 next:
867 entry = NEXT_RX(entry);
868 }
869
870 gem_post_rxds(gp, entry);
871
872 gp->rx_new = entry;
873
874 if (drops)
875 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n",
876 gp->dev->name);
877
878 return work_done;
879 }
880
881 static int gem_poll(struct net_device *dev, int *budget)
882 {
883 struct gem *gp = dev->priv;
884 unsigned long flags;
885
886 /*
887 * NAPI locking nightmare: See comment at head of driver
888 */
889 spin_lock_irqsave(&gp->lock, flags);
890
891 do {
892 int work_to_do, work_done;
893
894 /* Handle anomalies */
895 if (gp->status & GREG_STAT_ABNORMAL) {
896 if (gem_abnormal_irq(dev, gp, gp->status))
897 break;
898 }
899
900 /* Run TX completion thread */
901 spin_lock(&gp->tx_lock);
902 gem_tx(dev, gp, gp->status);
903 spin_unlock(&gp->tx_lock);
904
905 spin_unlock_irqrestore(&gp->lock, flags);
906
907 /* Run RX thread. We don't use any locking here,
908 * code willing to do bad things - like cleaning the
909 * rx ring - must call netif_poll_disable(), which
910 * schedule_timeout()'s if polling is already disabled.
911 */
912 work_to_do = min(*budget, dev->quota);
913
914 work_done = gem_rx(gp, work_to_do);
915
916 *budget -= work_done;
917 dev->quota -= work_done;
918
919 if (work_done >= work_to_do)
920 return 1;
921
922 spin_lock_irqsave(&gp->lock, flags);
923
924 gp->status = readl(gp->regs + GREG_STAT);
925 } while (gp->status & GREG_STAT_NAPI);
926
927 __netif_rx_complete(dev);
928 gem_enable_ints(gp);
929
930 spin_unlock_irqrestore(&gp->lock, flags);
931 return 0;
932 }
933
934 static irqreturn_t gem_interrupt(int irq, void *dev_id, struct pt_regs *regs)
935 {
936 struct net_device *dev = dev_id;
937 struct gem *gp = dev->priv;
938 unsigned long flags;
939
940 /* Swallow interrupts when shutting the chip down, though
941 * that shouldn't happen, we should have done free_irq() at
942 * this point...
943 */
944 if (!gp->running)
945 return IRQ_HANDLED;
946
947 spin_lock_irqsave(&gp->lock, flags);
948
949 if (netif_rx_schedule_prep(dev)) {
950 u32 gem_status = readl(gp->regs + GREG_STAT);
951
952 if (gem_status == 0) {
953 netif_poll_enable(dev);
954 spin_unlock_irqrestore(&gp->lock, flags);
955 return IRQ_NONE;
956 }
957 gp->status = gem_status;
958 gem_disable_ints(gp);
959 __netif_rx_schedule(dev);
960 }
961
962 spin_unlock_irqrestore(&gp->lock, flags);
963
964 /* If polling was disabled at the time we received that
965 * interrupt, we may return IRQ_HANDLED here while we
966 * should return IRQ_NONE. No big deal...
967 */
968 return IRQ_HANDLED;
969 }
970
971 #ifdef CONFIG_NET_POLL_CONTROLLER
972 static void gem_poll_controller(struct net_device *dev)
973 {
974 /* gem_interrupt is safe to reentrance so no need
975 * to disable_irq here.
976 */
977 gem_interrupt(dev->irq, dev, NULL);
978 }
979 #endif
980
981 static void gem_tx_timeout(struct net_device *dev)
982 {
983 struct gem *gp = dev->priv;
984
985 printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
986 if (!gp->running) {
987 printk("%s: hrm.. hw not running !\n", dev->name);
988 return;
989 }
990 printk(KERN_ERR "%s: TX_STATE[%08x:%08x:%08x]\n",
991 dev->name,
992 readl(gp->regs + TXDMA_CFG),
993 readl(gp->regs + MAC_TXSTAT),
994 readl(gp->regs + MAC_TXCFG));
995 printk(KERN_ERR "%s: RX_STATE[%08x:%08x:%08x]\n",
996 dev->name,
997 readl(gp->regs + RXDMA_CFG),
998 readl(gp->regs + MAC_RXSTAT),
999 readl(gp->regs + MAC_RXCFG));
1000
1001 spin_lock_irq(&gp->lock);
1002 spin_lock(&gp->tx_lock);
1003
1004 gp->reset_task_pending = 1;
1005 schedule_work(&gp->reset_task);
1006
1007 spin_unlock(&gp->tx_lock);
1008 spin_unlock_irq(&gp->lock);
1009 }
1010
1011 static __inline__ int gem_intme(int entry)
1012 {
1013 /* Algorithm: IRQ every 1/2 of descriptors. */
1014 if (!(entry & ((TX_RING_SIZE>>1)-1)))
1015 return 1;
1016
1017 return 0;
1018 }
1019
1020 static int gem_start_xmit(struct sk_buff *skb, struct net_device *dev)
1021 {
1022 struct gem *gp = dev->priv;
1023 int entry;
1024 u64 ctrl;
1025 unsigned long flags;
1026
1027 ctrl = 0;
1028 if (skb->ip_summed == CHECKSUM_HW) {
1029 u64 csum_start_off, csum_stuff_off;
1030
1031 csum_start_off = (u64) (skb->h.raw - skb->data);
1032 csum_stuff_off = (u64) ((skb->h.raw + skb->csum) - skb->data);
1033
1034 ctrl = (TXDCTRL_CENAB |
1035 (csum_start_off << 15) |
1036 (csum_stuff_off << 21));
1037 }
1038
1039 local_irq_save(flags);
1040 if (!spin_trylock(&gp->tx_lock)) {
1041 /* Tell upper layer to requeue */
1042 local_irq_restore(flags);
1043 return NETDEV_TX_LOCKED;
1044 }
1045 /* We raced with gem_do_stop() */
1046 if (!gp->running) {
1047 spin_unlock_irqrestore(&gp->tx_lock, flags);
1048 return NETDEV_TX_BUSY;
1049 }
1050
1051 /* This is a hard error, log it. */
1052 if (TX_BUFFS_AVAIL(gp) <= (skb_shinfo(skb)->nr_frags + 1)) {
1053 netif_stop_queue(dev);
1054 spin_unlock_irqrestore(&gp->tx_lock, flags);
1055 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
1056 dev->name);
1057 return NETDEV_TX_BUSY;
1058 }
1059
1060 entry = gp->tx_new;
1061 gp->tx_skbs[entry] = skb;
1062
1063 if (skb_shinfo(skb)->nr_frags == 0) {
1064 struct gem_txd *txd = &gp->init_block->txd[entry];
1065 dma_addr_t mapping;
1066 u32 len;
1067
1068 len = skb->len;
1069 mapping = pci_map_page(gp->pdev,
1070 virt_to_page(skb->data),
1071 offset_in_page(skb->data),
1072 len, PCI_DMA_TODEVICE);
1073 ctrl |= TXDCTRL_SOF | TXDCTRL_EOF | len;
1074 if (gem_intme(entry))
1075 ctrl |= TXDCTRL_INTME;
1076 txd->buffer = cpu_to_le64(mapping);
1077 wmb();
1078 txd->control_word = cpu_to_le64(ctrl);
1079 entry = NEXT_TX(entry);
1080 } else {
1081 struct gem_txd *txd;
1082 u32 first_len;
1083 u64 intme;
1084 dma_addr_t first_mapping;
1085 int frag, first_entry = entry;
1086
1087 intme = 0;
1088 if (gem_intme(entry))
1089 intme |= TXDCTRL_INTME;
1090
1091 /* We must give this initial chunk to the device last.
1092 * Otherwise we could race with the device.
1093 */
1094 first_len = skb_headlen(skb);
1095 first_mapping = pci_map_page(gp->pdev, virt_to_page(skb->data),
1096 offset_in_page(skb->data),
1097 first_len, PCI_DMA_TODEVICE);
1098 entry = NEXT_TX(entry);
1099
1100 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1101 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1102 u32 len;
1103 dma_addr_t mapping;
1104 u64 this_ctrl;
1105
1106 len = this_frag->size;
1107 mapping = pci_map_page(gp->pdev,
1108 this_frag->page,
1109 this_frag->page_offset,
1110 len, PCI_DMA_TODEVICE);
1111 this_ctrl = ctrl;
1112 if (frag == skb_shinfo(skb)->nr_frags - 1)
1113 this_ctrl |= TXDCTRL_EOF;
1114
1115 txd = &gp->init_block->txd[entry];
1116 txd->buffer = cpu_to_le64(mapping);
1117 wmb();
1118 txd->control_word = cpu_to_le64(this_ctrl | len);
1119
1120 if (gem_intme(entry))
1121 intme |= TXDCTRL_INTME;
1122
1123 entry = NEXT_TX(entry);
1124 }
1125 txd = &gp->init_block->txd[first_entry];
1126 txd->buffer = cpu_to_le64(first_mapping);
1127 wmb();
1128 txd->control_word =
1129 cpu_to_le64(ctrl | TXDCTRL_SOF | intme | first_len);
1130 }
1131
1132 gp->tx_new = entry;
1133 if (TX_BUFFS_AVAIL(gp) <= (MAX_SKB_FRAGS + 1))
1134 netif_stop_queue(dev);
1135
1136 if (netif_msg_tx_queued(gp))
1137 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
1138 dev->name, entry, skb->len);
1139 mb();
1140 writel(gp->tx_new, gp->regs + TXDMA_KICK);
1141 spin_unlock_irqrestore(&gp->tx_lock, flags);
1142
1143 dev->trans_start = jiffies;
1144
1145 return NETDEV_TX_OK;
1146 }
1147
1148 #define STOP_TRIES 32
1149
1150 /* Must be invoked under gp->lock and gp->tx_lock. */
1151 static void gem_reset(struct gem *gp)
1152 {
1153 int limit;
1154 u32 val;
1155
1156 /* Make sure we won't get any more interrupts */
1157 writel(0xffffffff, gp->regs + GREG_IMASK);
1158
1159 /* Reset the chip */
1160 writel(gp->swrst_base | GREG_SWRST_TXRST | GREG_SWRST_RXRST,
1161 gp->regs + GREG_SWRST);
1162
1163 limit = STOP_TRIES;
1164
1165 do {
1166 udelay(20);
1167 val = readl(gp->regs + GREG_SWRST);
1168 if (limit-- <= 0)
1169 break;
1170 } while (val & (GREG_SWRST_TXRST | GREG_SWRST_RXRST));
1171
1172 if (limit <= 0)
1173 printk(KERN_ERR "%s: SW reset is ghetto.\n", gp->dev->name);
1174 }
1175
1176 /* Must be invoked under gp->lock and gp->tx_lock. */
1177 static void gem_start_dma(struct gem *gp)
1178 {
1179 u32 val;
1180
1181 /* We are ready to rock, turn everything on. */
1182 val = readl(gp->regs + TXDMA_CFG);
1183 writel(val | TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1184 val = readl(gp->regs + RXDMA_CFG);
1185 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1186 val = readl(gp->regs + MAC_TXCFG);
1187 writel(val | MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1188 val = readl(gp->regs + MAC_RXCFG);
1189 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1190
1191 (void) readl(gp->regs + MAC_RXCFG);
1192 udelay(100);
1193
1194 gem_enable_ints(gp);
1195
1196 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1197 }
1198
1199 /* Must be invoked under gp->lock and gp->tx_lock. DMA won't be
1200 * actually stopped before about 4ms tho ...
1201 */
1202 static void gem_stop_dma(struct gem *gp)
1203 {
1204 u32 val;
1205
1206 /* We are done rocking, turn everything off. */
1207 val = readl(gp->regs + TXDMA_CFG);
1208 writel(val & ~TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1209 val = readl(gp->regs + RXDMA_CFG);
1210 writel(val & ~RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1211 val = readl(gp->regs + MAC_TXCFG);
1212 writel(val & ~MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1213 val = readl(gp->regs + MAC_RXCFG);
1214 writel(val & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1215
1216 (void) readl(gp->regs + MAC_RXCFG);
1217
1218 /* Need to wait a bit ... done by the caller */
1219 }
1220
1221
1222 /* Must be invoked under gp->lock and gp->tx_lock. */
1223 // XXX dbl check what that function should do when called on PCS PHY
1224 static void gem_begin_auto_negotiation(struct gem *gp, struct ethtool_cmd *ep)
1225 {
1226 u32 advertise, features;
1227 int autoneg;
1228 int speed;
1229 int duplex;
1230
1231 if (gp->phy_type != phy_mii_mdio0 &&
1232 gp->phy_type != phy_mii_mdio1)
1233 goto non_mii;
1234
1235 /* Setup advertise */
1236 if (found_mii_phy(gp))
1237 features = gp->phy_mii.def->features;
1238 else
1239 features = 0;
1240
1241 advertise = features & ADVERTISE_MASK;
1242 if (gp->phy_mii.advertising != 0)
1243 advertise &= gp->phy_mii.advertising;
1244
1245 autoneg = gp->want_autoneg;
1246 speed = gp->phy_mii.speed;
1247 duplex = gp->phy_mii.duplex;
1248
1249 /* Setup link parameters */
1250 if (!ep)
1251 goto start_aneg;
1252 if (ep->autoneg == AUTONEG_ENABLE) {
1253 advertise = ep->advertising;
1254 autoneg = 1;
1255 } else {
1256 autoneg = 0;
1257 speed = ep->speed;
1258 duplex = ep->duplex;
1259 }
1260
1261 start_aneg:
1262 /* Sanitize settings based on PHY capabilities */
1263 if ((features & SUPPORTED_Autoneg) == 0)
1264 autoneg = 0;
1265 if (speed == SPEED_1000 &&
1266 !(features & (SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)))
1267 speed = SPEED_100;
1268 if (speed == SPEED_100 &&
1269 !(features & (SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full)))
1270 speed = SPEED_10;
1271 if (duplex == DUPLEX_FULL &&
1272 !(features & (SUPPORTED_1000baseT_Full |
1273 SUPPORTED_100baseT_Full |
1274 SUPPORTED_10baseT_Full)))
1275 duplex = DUPLEX_HALF;
1276 if (speed == 0)
1277 speed = SPEED_10;
1278
1279 /* If we are asleep, we don't try to actually setup the PHY, we
1280 * just store the settings
1281 */
1282 if (gp->asleep) {
1283 gp->phy_mii.autoneg = gp->want_autoneg = autoneg;
1284 gp->phy_mii.speed = speed;
1285 gp->phy_mii.duplex = duplex;
1286 return;
1287 }
1288
1289 /* Configure PHY & start aneg */
1290 gp->want_autoneg = autoneg;
1291 if (autoneg) {
1292 if (found_mii_phy(gp))
1293 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, advertise);
1294 gp->lstate = link_aneg;
1295 } else {
1296 if (found_mii_phy(gp))
1297 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, speed, duplex);
1298 gp->lstate = link_force_ok;
1299 }
1300
1301 non_mii:
1302 gp->timer_ticks = 0;
1303 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1304 }
1305
1306 /* A link-up condition has occurred, initialize and enable the
1307 * rest of the chip.
1308 *
1309 * Must be invoked under gp->lock and gp->tx_lock.
1310 */
1311 static int gem_set_link_modes(struct gem *gp)
1312 {
1313 u32 val;
1314 int full_duplex, speed, pause;
1315
1316 full_duplex = 0;
1317 speed = SPEED_10;
1318 pause = 0;
1319
1320 if (found_mii_phy(gp)) {
1321 if (gp->phy_mii.def->ops->read_link(&gp->phy_mii))
1322 return 1;
1323 full_duplex = (gp->phy_mii.duplex == DUPLEX_FULL);
1324 speed = gp->phy_mii.speed;
1325 pause = gp->phy_mii.pause;
1326 } else if (gp->phy_type == phy_serialink ||
1327 gp->phy_type == phy_serdes) {
1328 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1329
1330 if (pcs_lpa & PCS_MIIADV_FD)
1331 full_duplex = 1;
1332 speed = SPEED_1000;
1333 }
1334
1335 if (netif_msg_link(gp))
1336 printk(KERN_INFO "%s: Link is up at %d Mbps, %s-duplex.\n",
1337 gp->dev->name, speed, (full_duplex ? "full" : "half"));
1338
1339 if (!gp->running)
1340 return 0;
1341
1342 val = (MAC_TXCFG_EIPG0 | MAC_TXCFG_NGU);
1343 if (full_duplex) {
1344 val |= (MAC_TXCFG_ICS | MAC_TXCFG_ICOLL);
1345 } else {
1346 /* MAC_TXCFG_NBO must be zero. */
1347 }
1348 writel(val, gp->regs + MAC_TXCFG);
1349
1350 val = (MAC_XIFCFG_OE | MAC_XIFCFG_LLED);
1351 if (!full_duplex &&
1352 (gp->phy_type == phy_mii_mdio0 ||
1353 gp->phy_type == phy_mii_mdio1)) {
1354 val |= MAC_XIFCFG_DISE;
1355 } else if (full_duplex) {
1356 val |= MAC_XIFCFG_FLED;
1357 }
1358
1359 if (speed == SPEED_1000)
1360 val |= (MAC_XIFCFG_GMII);
1361
1362 writel(val, gp->regs + MAC_XIFCFG);
1363
1364 /* If gigabit and half-duplex, enable carrier extension
1365 * mode. Else, disable it.
1366 */
1367 if (speed == SPEED_1000 && !full_duplex) {
1368 val = readl(gp->regs + MAC_TXCFG);
1369 writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1370
1371 val = readl(gp->regs + MAC_RXCFG);
1372 writel(val | MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1373 } else {
1374 val = readl(gp->regs + MAC_TXCFG);
1375 writel(val & ~MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1376
1377 val = readl(gp->regs + MAC_RXCFG);
1378 writel(val & ~MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1379 }
1380
1381 if (gp->phy_type == phy_serialink ||
1382 gp->phy_type == phy_serdes) {
1383 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1384
1385 if (pcs_lpa & (PCS_MIIADV_SP | PCS_MIIADV_AP))
1386 pause = 1;
1387 }
1388
1389 if (netif_msg_link(gp)) {
1390 if (pause) {
1391 printk(KERN_INFO "%s: Pause is enabled "
1392 "(rxfifo: %d off: %d on: %d)\n",
1393 gp->dev->name,
1394 gp->rx_fifo_sz,
1395 gp->rx_pause_off,
1396 gp->rx_pause_on);
1397 } else {
1398 printk(KERN_INFO "%s: Pause is disabled\n",
1399 gp->dev->name);
1400 }
1401 }
1402
1403 if (!full_duplex)
1404 writel(512, gp->regs + MAC_STIME);
1405 else
1406 writel(64, gp->regs + MAC_STIME);
1407 val = readl(gp->regs + MAC_MCCFG);
1408 if (pause)
1409 val |= (MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1410 else
1411 val &= ~(MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1412 writel(val, gp->regs + MAC_MCCFG);
1413
1414 gem_start_dma(gp);
1415
1416 return 0;
1417 }
1418
1419 /* Must be invoked under gp->lock and gp->tx_lock. */
1420 static int gem_mdio_link_not_up(struct gem *gp)
1421 {
1422 switch (gp->lstate) {
1423 case link_force_ret:
1424 if (netif_msg_link(gp))
1425 printk(KERN_INFO "%s: Autoneg failed again, keeping"
1426 " forced mode\n", gp->dev->name);
1427 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii,
1428 gp->last_forced_speed, DUPLEX_HALF);
1429 gp->timer_ticks = 5;
1430 gp->lstate = link_force_ok;
1431 return 0;
1432 case link_aneg:
1433 /* We try forced modes after a failed aneg only on PHYs that don't
1434 * have "magic_aneg" bit set, which means they internally do the
1435 * while forced-mode thingy. On these, we just restart aneg
1436 */
1437 if (gp->phy_mii.def->magic_aneg)
1438 return 1;
1439 if (netif_msg_link(gp))
1440 printk(KERN_INFO "%s: switching to forced 100bt\n",
1441 gp->dev->name);
1442 /* Try forced modes. */
1443 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_100,
1444 DUPLEX_HALF);
1445 gp->timer_ticks = 5;
1446 gp->lstate = link_force_try;
1447 return 0;
1448 case link_force_try:
1449 /* Downgrade from 100 to 10 Mbps if necessary.
1450 * If already at 10Mbps, warn user about the
1451 * situation every 10 ticks.
1452 */
1453 if (gp->phy_mii.speed == SPEED_100) {
1454 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_10,
1455 DUPLEX_HALF);
1456 gp->timer_ticks = 5;
1457 if (netif_msg_link(gp))
1458 printk(KERN_INFO "%s: switching to forced 10bt\n",
1459 gp->dev->name);
1460 return 0;
1461 } else
1462 return 1;
1463 default:
1464 return 0;
1465 }
1466 }
1467
1468 static void gem_link_timer(unsigned long data)
1469 {
1470 struct gem *gp = (struct gem *) data;
1471 int restart_aneg = 0;
1472
1473 if (gp->asleep)
1474 return;
1475
1476 spin_lock_irq(&gp->lock);
1477 spin_lock(&gp->tx_lock);
1478 gem_get_cell(gp);
1479
1480 /* If the reset task is still pending, we just
1481 * reschedule the link timer
1482 */
1483 if (gp->reset_task_pending)
1484 goto restart;
1485
1486 if (gp->phy_type == phy_serialink ||
1487 gp->phy_type == phy_serdes) {
1488 u32 val = readl(gp->regs + PCS_MIISTAT);
1489
1490 if (!(val & PCS_MIISTAT_LS))
1491 val = readl(gp->regs + PCS_MIISTAT);
1492
1493 if ((val & PCS_MIISTAT_LS) != 0) {
1494 gp->lstate = link_up;
1495 netif_carrier_on(gp->dev);
1496 (void)gem_set_link_modes(gp);
1497 }
1498 goto restart;
1499 }
1500 if (found_mii_phy(gp) && gp->phy_mii.def->ops->poll_link(&gp->phy_mii)) {
1501 /* Ok, here we got a link. If we had it due to a forced
1502 * fallback, and we were configured for autoneg, we do
1503 * retry a short autoneg pass. If you know your hub is
1504 * broken, use ethtool ;)
1505 */
1506 if (gp->lstate == link_force_try && gp->want_autoneg) {
1507 gp->lstate = link_force_ret;
1508 gp->last_forced_speed = gp->phy_mii.speed;
1509 gp->timer_ticks = 5;
1510 if (netif_msg_link(gp))
1511 printk(KERN_INFO "%s: Got link after fallback, retrying"
1512 " autoneg once...\n", gp->dev->name);
1513 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, gp->phy_mii.advertising);
1514 } else if (gp->lstate != link_up) {
1515 gp->lstate = link_up;
1516 netif_carrier_on(gp->dev);
1517 if (gem_set_link_modes(gp))
1518 restart_aneg = 1;
1519 }
1520 } else {
1521 /* If the link was previously up, we restart the
1522 * whole process
1523 */
1524 if (gp->lstate == link_up) {
1525 gp->lstate = link_down;
1526 if (netif_msg_link(gp))
1527 printk(KERN_INFO "%s: Link down\n",
1528 gp->dev->name);
1529 netif_carrier_off(gp->dev);
1530 gp->reset_task_pending = 1;
1531 schedule_work(&gp->reset_task);
1532 restart_aneg = 1;
1533 } else if (++gp->timer_ticks > 10) {
1534 if (found_mii_phy(gp))
1535 restart_aneg = gem_mdio_link_not_up(gp);
1536 else
1537 restart_aneg = 1;
1538 }
1539 }
1540 if (restart_aneg) {
1541 gem_begin_auto_negotiation(gp, NULL);
1542 goto out_unlock;
1543 }
1544 restart:
1545 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1546 out_unlock:
1547 gem_put_cell(gp);
1548 spin_unlock(&gp->tx_lock);
1549 spin_unlock_irq(&gp->lock);
1550 }
1551
1552 /* Must be invoked under gp->lock and gp->tx_lock. */
1553 static void gem_clean_rings(struct gem *gp)
1554 {
1555 struct gem_init_block *gb = gp->init_block;
1556 struct sk_buff *skb;
1557 int i;
1558 dma_addr_t dma_addr;
1559
1560 for (i = 0; i < RX_RING_SIZE; i++) {
1561 struct gem_rxd *rxd;
1562
1563 rxd = &gb->rxd[i];
1564 if (gp->rx_skbs[i] != NULL) {
1565 skb = gp->rx_skbs[i];
1566 dma_addr = le64_to_cpu(rxd->buffer);
1567 pci_unmap_page(gp->pdev, dma_addr,
1568 RX_BUF_ALLOC_SIZE(gp),
1569 PCI_DMA_FROMDEVICE);
1570 dev_kfree_skb_any(skb);
1571 gp->rx_skbs[i] = NULL;
1572 }
1573 rxd->status_word = 0;
1574 wmb();
1575 rxd->buffer = 0;
1576 }
1577
1578 for (i = 0; i < TX_RING_SIZE; i++) {
1579 if (gp->tx_skbs[i] != NULL) {
1580 struct gem_txd *txd;
1581 int frag;
1582
1583 skb = gp->tx_skbs[i];
1584 gp->tx_skbs[i] = NULL;
1585
1586 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1587 int ent = i & (TX_RING_SIZE - 1);
1588
1589 txd = &gb->txd[ent];
1590 dma_addr = le64_to_cpu(txd->buffer);
1591 pci_unmap_page(gp->pdev, dma_addr,
1592 le64_to_cpu(txd->control_word) &
1593 TXDCTRL_BUFSZ, PCI_DMA_TODEVICE);
1594
1595 if (frag != skb_shinfo(skb)->nr_frags)
1596 i++;
1597 }
1598 dev_kfree_skb_any(skb);
1599 }
1600 }
1601 }
1602
1603 /* Must be invoked under gp->lock and gp->tx_lock. */
1604 static void gem_init_rings(struct gem *gp)
1605 {
1606 struct gem_init_block *gb = gp->init_block;
1607 struct net_device *dev = gp->dev;
1608 int i;
1609 dma_addr_t dma_addr;
1610
1611 gp->rx_new = gp->rx_old = gp->tx_new = gp->tx_old = 0;
1612
1613 gem_clean_rings(gp);
1614
1615 gp->rx_buf_sz = max(dev->mtu + ETH_HLEN + VLAN_HLEN,
1616 (unsigned)VLAN_ETH_FRAME_LEN);
1617
1618 for (i = 0; i < RX_RING_SIZE; i++) {
1619 struct sk_buff *skb;
1620 struct gem_rxd *rxd = &gb->rxd[i];
1621
1622 skb = gem_alloc_skb(RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
1623 if (!skb) {
1624 rxd->buffer = 0;
1625 rxd->status_word = 0;
1626 continue;
1627 }
1628
1629 gp->rx_skbs[i] = skb;
1630 skb->dev = dev;
1631 skb_put(skb, (gp->rx_buf_sz + RX_OFFSET));
1632 dma_addr = pci_map_page(gp->pdev,
1633 virt_to_page(skb->data),
1634 offset_in_page(skb->data),
1635 RX_BUF_ALLOC_SIZE(gp),
1636 PCI_DMA_FROMDEVICE);
1637 rxd->buffer = cpu_to_le64(dma_addr);
1638 wmb();
1639 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
1640 skb_reserve(skb, RX_OFFSET);
1641 }
1642
1643 for (i = 0; i < TX_RING_SIZE; i++) {
1644 struct gem_txd *txd = &gb->txd[i];
1645
1646 txd->control_word = 0;
1647 wmb();
1648 txd->buffer = 0;
1649 }
1650 wmb();
1651 }
1652
1653 /* Init PHY interface and start link poll state machine */
1654 static void gem_init_phy(struct gem *gp)
1655 {
1656 u32 mif_cfg;
1657
1658 /* Revert MIF CFG setting done on stop_phy */
1659 mif_cfg = readl(gp->regs + MIF_CFG);
1660 mif_cfg &= ~(MIF_CFG_PSELECT|MIF_CFG_POLL|MIF_CFG_BBMODE|MIF_CFG_MDI1);
1661 mif_cfg |= MIF_CFG_MDI0;
1662 writel(mif_cfg, gp->regs + MIF_CFG);
1663 writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE);
1664 writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG);
1665
1666 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
1667 int i;
1668 u16 ctrl;
1669
1670 #ifdef CONFIG_PPC_PMAC
1671 pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0);
1672 #endif
1673
1674 /* Some PHYs used by apple have problem getting back
1675 * to us, we do an additional reset here
1676 */
1677 phy_write(gp, MII_BMCR, BMCR_RESET);
1678 for (i = 0; i < 50; i++) {
1679 if ((phy_read(gp, MII_BMCR) & BMCR_RESET) == 0)
1680 break;
1681 msleep(10);
1682 }
1683 if (i == 50)
1684 printk(KERN_WARNING "%s: GMAC PHY not responding !\n",
1685 gp->dev->name);
1686 /* Make sure isolate is off */
1687 ctrl = phy_read(gp, MII_BMCR);
1688 if (ctrl & BMCR_ISOLATE)
1689 phy_write(gp, MII_BMCR, ctrl & ~BMCR_ISOLATE);
1690 }
1691
1692 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
1693 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
1694 u32 val;
1695
1696 /* Init datapath mode register. */
1697 if (gp->phy_type == phy_mii_mdio0 ||
1698 gp->phy_type == phy_mii_mdio1) {
1699 val = PCS_DMODE_MGM;
1700 } else if (gp->phy_type == phy_serialink) {
1701 val = PCS_DMODE_SM | PCS_DMODE_GMOE;
1702 } else {
1703 val = PCS_DMODE_ESM;
1704 }
1705
1706 writel(val, gp->regs + PCS_DMODE);
1707 }
1708
1709 if (gp->phy_type == phy_mii_mdio0 ||
1710 gp->phy_type == phy_mii_mdio1) {
1711 // XXX check for errors
1712 mii_phy_probe(&gp->phy_mii, gp->mii_phy_addr);
1713
1714 /* Init PHY */
1715 if (gp->phy_mii.def && gp->phy_mii.def->ops->init)
1716 gp->phy_mii.def->ops->init(&gp->phy_mii);
1717 } else {
1718 u32 val;
1719 int limit;
1720
1721 /* Reset PCS unit. */
1722 val = readl(gp->regs + PCS_MIICTRL);
1723 val |= PCS_MIICTRL_RST;
1724 writeb(val, gp->regs + PCS_MIICTRL);
1725
1726 limit = 32;
1727 while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) {
1728 udelay(100);
1729 if (limit-- <= 0)
1730 break;
1731 }
1732 if (limit <= 0)
1733 printk(KERN_WARNING "%s: PCS reset bit would not clear.\n",
1734 gp->dev->name);
1735
1736 /* Make sure PCS is disabled while changing advertisement
1737 * configuration.
1738 */
1739 val = readl(gp->regs + PCS_CFG);
1740 val &= ~(PCS_CFG_ENABLE | PCS_CFG_TO);
1741 writel(val, gp->regs + PCS_CFG);
1742
1743 /* Advertise all capabilities except assymetric
1744 * pause.
1745 */
1746 val = readl(gp->regs + PCS_MIIADV);
1747 val |= (PCS_MIIADV_FD | PCS_MIIADV_HD |
1748 PCS_MIIADV_SP | PCS_MIIADV_AP);
1749 writel(val, gp->regs + PCS_MIIADV);
1750
1751 /* Enable and restart auto-negotiation, disable wrapback/loopback,
1752 * and re-enable PCS.
1753 */
1754 val = readl(gp->regs + PCS_MIICTRL);
1755 val |= (PCS_MIICTRL_RAN | PCS_MIICTRL_ANE);
1756 val &= ~PCS_MIICTRL_WB;
1757 writel(val, gp->regs + PCS_MIICTRL);
1758
1759 val = readl(gp->regs + PCS_CFG);
1760 val |= PCS_CFG_ENABLE;
1761 writel(val, gp->regs + PCS_CFG);
1762
1763 /* Make sure serialink loopback is off. The meaning
1764 * of this bit is logically inverted based upon whether
1765 * you are in Serialink or SERDES mode.
1766 */
1767 val = readl(gp->regs + PCS_SCTRL);
1768 if (gp->phy_type == phy_serialink)
1769 val &= ~PCS_SCTRL_LOOP;
1770 else
1771 val |= PCS_SCTRL_LOOP;
1772 writel(val, gp->regs + PCS_SCTRL);
1773 }
1774
1775 /* Default aneg parameters */
1776 gp->timer_ticks = 0;
1777 gp->lstate = link_down;
1778 netif_carrier_off(gp->dev);
1779
1780 /* Can I advertise gigabit here ? I'd need BCM PHY docs... */
1781 spin_lock_irq(&gp->lock);
1782 gem_begin_auto_negotiation(gp, NULL);
1783 spin_unlock_irq(&gp->lock);
1784 }
1785
1786 /* Must be invoked under gp->lock and gp->tx_lock. */
1787 static void gem_init_dma(struct gem *gp)
1788 {
1789 u64 desc_dma = (u64) gp->gblock_dvma;
1790 u32 val;
1791
1792 val = (TXDMA_CFG_BASE | (0x7ff << 10) | TXDMA_CFG_PMODE);
1793 writel(val, gp->regs + TXDMA_CFG);
1794
1795 writel(desc_dma >> 32, gp->regs + TXDMA_DBHI);
1796 writel(desc_dma & 0xffffffff, gp->regs + TXDMA_DBLOW);
1797 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
1798
1799 writel(0, gp->regs + TXDMA_KICK);
1800
1801 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
1802 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
1803 writel(val, gp->regs + RXDMA_CFG);
1804
1805 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
1806 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
1807
1808 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1809
1810 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
1811 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
1812 writel(val, gp->regs + RXDMA_PTHRESH);
1813
1814 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
1815 writel(((5 & RXDMA_BLANK_IPKTS) |
1816 ((8 << 12) & RXDMA_BLANK_ITIME)),
1817 gp->regs + RXDMA_BLANK);
1818 else
1819 writel(((5 & RXDMA_BLANK_IPKTS) |
1820 ((4 << 12) & RXDMA_BLANK_ITIME)),
1821 gp->regs + RXDMA_BLANK);
1822 }
1823
1824 /* Must be invoked under gp->lock and gp->tx_lock. */
1825 static u32 gem_setup_multicast(struct gem *gp)
1826 {
1827 u32 rxcfg = 0;
1828 int i;
1829
1830 if ((gp->dev->flags & IFF_ALLMULTI) ||
1831 (gp->dev->mc_count > 256)) {
1832 for (i=0; i<16; i++)
1833 writel(0xffff, gp->regs + MAC_HASH0 + (i << 2));
1834 rxcfg |= MAC_RXCFG_HFE;
1835 } else if (gp->dev->flags & IFF_PROMISC) {
1836 rxcfg |= MAC_RXCFG_PROM;
1837 } else {
1838 u16 hash_table[16];
1839 u32 crc;
1840 struct dev_mc_list *dmi = gp->dev->mc_list;
1841 int i;
1842
1843 for (i = 0; i < 16; i++)
1844 hash_table[i] = 0;
1845
1846 for (i = 0; i < gp->dev->mc_count; i++) {
1847 char *addrs = dmi->dmi_addr;
1848
1849 dmi = dmi->next;
1850
1851 if (!(*addrs & 1))
1852 continue;
1853
1854 crc = ether_crc_le(6, addrs);
1855 crc >>= 24;
1856 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
1857 }
1858 for (i=0; i<16; i++)
1859 writel(hash_table[i], gp->regs + MAC_HASH0 + (i << 2));
1860 rxcfg |= MAC_RXCFG_HFE;
1861 }
1862
1863 return rxcfg;
1864 }
1865
1866 /* Must be invoked under gp->lock and gp->tx_lock. */
1867 static void gem_init_mac(struct gem *gp)
1868 {
1869 unsigned char *e = &gp->dev->dev_addr[0];
1870
1871 writel(0x1bf0, gp->regs + MAC_SNDPAUSE);
1872
1873 writel(0x00, gp->regs + MAC_IPG0);
1874 writel(0x08, gp->regs + MAC_IPG1);
1875 writel(0x04, gp->regs + MAC_IPG2);
1876 writel(0x40, gp->regs + MAC_STIME);
1877 writel(0x40, gp->regs + MAC_MINFSZ);
1878
1879 /* Ethernet payload + header + FCS + optional VLAN tag. */
1880 writel(0x20000000 | (gp->rx_buf_sz + 4), gp->regs + MAC_MAXFSZ);
1881
1882 writel(0x07, gp->regs + MAC_PASIZE);
1883 writel(0x04, gp->regs + MAC_JAMSIZE);
1884 writel(0x10, gp->regs + MAC_ATTLIM);
1885 writel(0x8808, gp->regs + MAC_MCTYPE);
1886
1887 writel((e[5] | (e[4] << 8)) & 0x3ff, gp->regs + MAC_RANDSEED);
1888
1889 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
1890 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
1891 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
1892
1893 writel(0, gp->regs + MAC_ADDR3);
1894 writel(0, gp->regs + MAC_ADDR4);
1895 writel(0, gp->regs + MAC_ADDR5);
1896
1897 writel(0x0001, gp->regs + MAC_ADDR6);
1898 writel(0xc200, gp->regs + MAC_ADDR7);
1899 writel(0x0180, gp->regs + MAC_ADDR8);
1900
1901 writel(0, gp->regs + MAC_AFILT0);
1902 writel(0, gp->regs + MAC_AFILT1);
1903 writel(0, gp->regs + MAC_AFILT2);
1904 writel(0, gp->regs + MAC_AF21MSK);
1905 writel(0, gp->regs + MAC_AF0MSK);
1906
1907 gp->mac_rx_cfg = gem_setup_multicast(gp);
1908 #ifdef STRIP_FCS
1909 gp->mac_rx_cfg |= MAC_RXCFG_SFCS;
1910 #endif
1911 writel(0, gp->regs + MAC_NCOLL);
1912 writel(0, gp->regs + MAC_FASUCC);
1913 writel(0, gp->regs + MAC_ECOLL);
1914 writel(0, gp->regs + MAC_LCOLL);
1915 writel(0, gp->regs + MAC_DTIMER);
1916 writel(0, gp->regs + MAC_PATMPS);
1917 writel(0, gp->regs + MAC_RFCTR);
1918 writel(0, gp->regs + MAC_LERR);
1919 writel(0, gp->regs + MAC_AERR);
1920 writel(0, gp->regs + MAC_FCSERR);
1921 writel(0, gp->regs + MAC_RXCVERR);
1922
1923 /* Clear RX/TX/MAC/XIF config, we will set these up and enable
1924 * them once a link is established.
1925 */
1926 writel(0, gp->regs + MAC_TXCFG);
1927 writel(gp->mac_rx_cfg, gp->regs + MAC_RXCFG);
1928 writel(0, gp->regs + MAC_MCCFG);
1929 writel(0, gp->regs + MAC_XIFCFG);
1930
1931 /* Setup MAC interrupts. We want to get all of the interesting
1932 * counter expiration events, but we do not want to hear about
1933 * normal rx/tx as the DMA engine tells us that.
1934 */
1935 writel(MAC_TXSTAT_XMIT, gp->regs + MAC_TXMASK);
1936 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
1937
1938 /* Don't enable even the PAUSE interrupts for now, we
1939 * make no use of those events other than to record them.
1940 */
1941 writel(0xffffffff, gp->regs + MAC_MCMASK);
1942
1943 /* Don't enable GEM's WOL in normal operations
1944 */
1945 if (gp->has_wol)
1946 writel(0, gp->regs + WOL_WAKECSR);
1947 }
1948
1949 /* Must be invoked under gp->lock and gp->tx_lock. */
1950 static void gem_init_pause_thresholds(struct gem *gp)
1951 {
1952 u32 cfg;
1953
1954 /* Calculate pause thresholds. Setting the OFF threshold to the
1955 * full RX fifo size effectively disables PAUSE generation which
1956 * is what we do for 10/100 only GEMs which have FIFOs too small
1957 * to make real gains from PAUSE.
1958 */
1959 if (gp->rx_fifo_sz <= (2 * 1024)) {
1960 gp->rx_pause_off = gp->rx_pause_on = gp->rx_fifo_sz;
1961 } else {
1962 int max_frame = (gp->rx_buf_sz + 4 + 64) & ~63;
1963 int off = (gp->rx_fifo_sz - (max_frame * 2));
1964 int on = off - max_frame;
1965
1966 gp->rx_pause_off = off;
1967 gp->rx_pause_on = on;
1968 }
1969
1970
1971 /* Configure the chip "burst" DMA mode & enable some
1972 * HW bug fixes on Apple version
1973 */
1974 cfg = 0;
1975 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE)
1976 cfg |= GREG_CFG_RONPAULBIT | GREG_CFG_ENBUG2FIX;
1977 #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
1978 cfg |= GREG_CFG_IBURST;
1979 #endif
1980 cfg |= ((31 << 1) & GREG_CFG_TXDMALIM);
1981 cfg |= ((31 << 6) & GREG_CFG_RXDMALIM);
1982 writel(cfg, gp->regs + GREG_CFG);
1983
1984 /* If Infinite Burst didn't stick, then use different
1985 * thresholds (and Apple bug fixes don't exist)
1986 */
1987 if (!(readl(gp->regs + GREG_CFG) & GREG_CFG_IBURST)) {
1988 cfg = ((2 << 1) & GREG_CFG_TXDMALIM);
1989 cfg |= ((8 << 6) & GREG_CFG_RXDMALIM);
1990 writel(cfg, gp->regs + GREG_CFG);
1991 }
1992 }
1993
1994 static int gem_check_invariants(struct gem *gp)
1995 {
1996 struct pci_dev *pdev = gp->pdev;
1997 u32 mif_cfg;
1998
1999 /* On Apple's sungem, we can't rely on registers as the chip
2000 * was been powered down by the firmware. The PHY is looked
2001 * up later on.
2002 */
2003 if (pdev->vendor == PCI_VENDOR_ID_APPLE) {
2004 gp->phy_type = phy_mii_mdio0;
2005 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
2006 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
2007 gp->swrst_base = 0;
2008
2009 mif_cfg = readl(gp->regs + MIF_CFG);
2010 mif_cfg &= ~(MIF_CFG_PSELECT|MIF_CFG_POLL|MIF_CFG_BBMODE|MIF_CFG_MDI1);
2011 mif_cfg |= MIF_CFG_MDI0;
2012 writel(mif_cfg, gp->regs + MIF_CFG);
2013 writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE);
2014 writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG);
2015
2016 /* We hard-code the PHY address so we can properly bring it out of
2017 * reset later on, we can't really probe it at this point, though
2018 * that isn't an issue.
2019 */
2020 if (gp->pdev->device == PCI_DEVICE_ID_APPLE_K2_GMAC)
2021 gp->mii_phy_addr = 1;
2022 else
2023 gp->mii_phy_addr = 0;
2024
2025 return 0;
2026 }
2027
2028 mif_cfg = readl(gp->regs + MIF_CFG);
2029
2030 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
2031 pdev->device == PCI_DEVICE_ID_SUN_RIO_GEM) {
2032 /* One of the MII PHYs _must_ be present
2033 * as this chip has no gigabit PHY.
2034 */
2035 if ((mif_cfg & (MIF_CFG_MDI0 | MIF_CFG_MDI1)) == 0) {
2036 printk(KERN_ERR PFX "RIO GEM lacks MII phy, mif_cfg[%08x]\n",
2037 mif_cfg);
2038 return -1;
2039 }
2040 }
2041
2042 /* Determine initial PHY interface type guess. MDIO1 is the
2043 * external PHY and thus takes precedence over MDIO0.
2044 */
2045
2046 if (mif_cfg & MIF_CFG_MDI1) {
2047 gp->phy_type = phy_mii_mdio1;
2048 mif_cfg |= MIF_CFG_PSELECT;
2049 writel(mif_cfg, gp->regs + MIF_CFG);
2050 } else if (mif_cfg & MIF_CFG_MDI0) {
2051 gp->phy_type = phy_mii_mdio0;
2052 mif_cfg &= ~MIF_CFG_PSELECT;
2053 writel(mif_cfg, gp->regs + MIF_CFG);
2054 } else {
2055 gp->phy_type = phy_serialink;
2056 }
2057 if (gp->phy_type == phy_mii_mdio1 ||
2058 gp->phy_type == phy_mii_mdio0) {
2059 int i;
2060
2061 for (i = 0; i < 32; i++) {
2062 gp->mii_phy_addr = i;
2063 if (phy_read(gp, MII_BMCR) != 0xffff)
2064 break;
2065 }
2066 if (i == 32) {
2067 if (pdev->device != PCI_DEVICE_ID_SUN_GEM) {
2068 printk(KERN_ERR PFX "RIO MII phy will not respond.\n");
2069 return -1;
2070 }
2071 gp->phy_type = phy_serdes;
2072 }
2073 }
2074
2075 /* Fetch the FIFO configurations now too. */
2076 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
2077 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
2078
2079 if (pdev->vendor == PCI_VENDOR_ID_SUN) {
2080 if (pdev->device == PCI_DEVICE_ID_SUN_GEM) {
2081 if (gp->tx_fifo_sz != (9 * 1024) ||
2082 gp->rx_fifo_sz != (20 * 1024)) {
2083 printk(KERN_ERR PFX "GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2084 gp->tx_fifo_sz, gp->rx_fifo_sz);
2085 return -1;
2086 }
2087 gp->swrst_base = 0;
2088 } else {
2089 if (gp->tx_fifo_sz != (2 * 1024) ||
2090 gp->rx_fifo_sz != (2 * 1024)) {
2091 printk(KERN_ERR PFX "RIO GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2092 gp->tx_fifo_sz, gp->rx_fifo_sz);
2093 return -1;
2094 }
2095 gp->swrst_base = (64 / 4) << GREG_SWRST_CACHE_SHIFT;
2096 }
2097 }
2098
2099 return 0;
2100 }
2101
2102 /* Must be invoked under gp->lock and gp->tx_lock. */
2103 static void gem_reinit_chip(struct gem *gp)
2104 {
2105 /* Reset the chip */
2106 gem_reset(gp);
2107
2108 /* Make sure ints are disabled */
2109 gem_disable_ints(gp);
2110
2111 /* Allocate & setup ring buffers */
2112 gem_init_rings(gp);
2113
2114 /* Configure pause thresholds */
2115 gem_init_pause_thresholds(gp);
2116
2117 /* Init DMA & MAC engines */
2118 gem_init_dma(gp);
2119 gem_init_mac(gp);
2120 }
2121
2122
2123 /* Must be invoked with no lock held. */
2124 static void gem_stop_phy(struct gem *gp, int wol)
2125 {
2126 u32 mif_cfg;
2127 unsigned long flags;
2128
2129 /* Let the chip settle down a bit, it seems that helps
2130 * for sleep mode on some models
2131 */
2132 msleep(10);
2133
2134 /* Make sure we aren't polling PHY status change. We
2135 * don't currently use that feature though
2136 */
2137 mif_cfg = readl(gp->regs + MIF_CFG);
2138 mif_cfg &= ~MIF_CFG_POLL;
2139 writel(mif_cfg, gp->regs + MIF_CFG);
2140
2141 if (wol && gp->has_wol) {
2142 unsigned char *e = &gp->dev->dev_addr[0];
2143 u32 csr;
2144
2145 /* Setup wake-on-lan for MAGIC packet */
2146 writel(MAC_RXCFG_HFE | MAC_RXCFG_SFCS | MAC_RXCFG_ENAB,
2147 gp->regs + MAC_RXCFG);
2148 writel((e[4] << 8) | e[5], gp->regs + WOL_MATCH0);
2149 writel((e[2] << 8) | e[3], gp->regs + WOL_MATCH1);
2150 writel((e[0] << 8) | e[1], gp->regs + WOL_MATCH2);
2151
2152 writel(WOL_MCOUNT_N | WOL_MCOUNT_M, gp->regs + WOL_MCOUNT);
2153 csr = WOL_WAKECSR_ENABLE;
2154 if ((readl(gp->regs + MAC_XIFCFG) & MAC_XIFCFG_GMII) == 0)
2155 csr |= WOL_WAKECSR_MII;
2156 writel(csr, gp->regs + WOL_WAKECSR);
2157 } else {
2158 writel(0, gp->regs + MAC_RXCFG);
2159 (void)readl(gp->regs + MAC_RXCFG);
2160 /* Machine sleep will die in strange ways if we
2161 * dont wait a bit here, looks like the chip takes
2162 * some time to really shut down
2163 */
2164 msleep(10);
2165 }
2166
2167 writel(0, gp->regs + MAC_TXCFG);
2168 writel(0, gp->regs + MAC_XIFCFG);
2169 writel(0, gp->regs + TXDMA_CFG);
2170 writel(0, gp->regs + RXDMA_CFG);
2171
2172 if (!wol) {
2173 spin_lock_irqsave(&gp->lock, flags);
2174 spin_lock(&gp->tx_lock);
2175 gem_reset(gp);
2176 writel(MAC_TXRST_CMD, gp->regs + MAC_TXRST);
2177 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
2178 spin_unlock(&gp->tx_lock);
2179 spin_unlock_irqrestore(&gp->lock, flags);
2180
2181 /* No need to take the lock here */
2182
2183 if (found_mii_phy(gp) && gp->phy_mii.def->ops->suspend)
2184 gp->phy_mii.def->ops->suspend(&gp->phy_mii);
2185
2186 /* According to Apple, we must set the MDIO pins to this begnign
2187 * state or we may 1) eat more current, 2) damage some PHYs
2188 */
2189 mif_cfg = 0;
2190 writel(mif_cfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG);
2191 writel(0, gp->regs + MIF_BBCLK);
2192 writel(0, gp->regs + MIF_BBDATA);
2193 writel(0, gp->regs + MIF_BBOENAB);
2194 writel(MAC_XIFCFG_GMII | MAC_XIFCFG_LBCK, gp->regs + MAC_XIFCFG);
2195 (void) readl(gp->regs + MAC_XIFCFG);
2196 }
2197 }
2198
2199
2200 static int gem_do_start(struct net_device *dev)
2201 {
2202 struct gem *gp = dev->priv;
2203 unsigned long flags;
2204
2205 spin_lock_irqsave(&gp->lock, flags);
2206 spin_lock(&gp->tx_lock);
2207
2208 /* Enable the cell */
2209 gem_get_cell(gp);
2210
2211 /* Init & setup chip hardware */
2212 gem_reinit_chip(gp);
2213
2214 gp->running = 1;
2215
2216 if (gp->lstate == link_up) {
2217 netif_carrier_on(gp->dev);
2218 gem_set_link_modes(gp);
2219 }
2220
2221 netif_wake_queue(gp->dev);
2222
2223 spin_unlock(&gp->tx_lock);
2224 spin_unlock_irqrestore(&gp->lock, flags);
2225
2226 if (request_irq(gp->pdev->irq, gem_interrupt,
2227 SA_SHIRQ, dev->name, (void *)dev)) {
2228 printk(KERN_ERR "%s: failed to request irq !\n", gp->dev->name);
2229
2230 spin_lock_irqsave(&gp->lock, flags);
2231 spin_lock(&gp->tx_lock);
2232
2233 gp->running = 0;
2234 gem_reset(gp);
2235 gem_clean_rings(gp);
2236 gem_put_cell(gp);
2237
2238 spin_unlock(&gp->tx_lock);
2239 spin_unlock_irqrestore(&gp->lock, flags);
2240
2241 return -EAGAIN;
2242 }
2243
2244 return 0;
2245 }
2246
2247 static void gem_do_stop(struct net_device *dev, int wol)
2248 {
2249 struct gem *gp = dev->priv;
2250 unsigned long flags;
2251
2252 spin_lock_irqsave(&gp->lock, flags);
2253 spin_lock(&gp->tx_lock);
2254
2255 gp->running = 0;
2256
2257 /* Stop netif queue */
2258 netif_stop_queue(dev);
2259
2260 /* Make sure ints are disabled */
2261 gem_disable_ints(gp);
2262
2263 /* We can drop the lock now */
2264 spin_unlock(&gp->tx_lock);
2265 spin_unlock_irqrestore(&gp->lock, flags);
2266
2267 /* If we are going to sleep with WOL */
2268 gem_stop_dma(gp);
2269 msleep(10);
2270 if (!wol)
2271 gem_reset(gp);
2272 msleep(10);
2273
2274 /* Get rid of rings */
2275 gem_clean_rings(gp);
2276
2277 /* No irq needed anymore */
2278 free_irq(gp->pdev->irq, (void *) dev);
2279
2280 /* Cell not needed neither if no WOL */
2281 if (!wol) {
2282 spin_lock_irqsave(&gp->lock, flags);
2283 gem_put_cell(gp);
2284 spin_unlock_irqrestore(&gp->lock, flags);
2285 }
2286 }
2287
2288 static void gem_reset_task(void *data)
2289 {
2290 struct gem *gp = (struct gem *) data;
2291
2292 down(&gp->pm_sem);
2293
2294 netif_poll_disable(gp->dev);
2295
2296 spin_lock_irq(&gp->lock);
2297 spin_lock(&gp->tx_lock);
2298
2299 if (gp->running == 0)
2300 goto not_running;
2301
2302 if (gp->running) {
2303 netif_stop_queue(gp->dev);
2304
2305 /* Reset the chip & rings */
2306 gem_reinit_chip(gp);
2307 if (gp->lstate == link_up)
2308 gem_set_link_modes(gp);
2309 netif_wake_queue(gp->dev);
2310 }
2311 not_running:
2312 gp->reset_task_pending = 0;
2313
2314 spin_unlock(&gp->tx_lock);
2315 spin_unlock_irq(&gp->lock);
2316
2317 netif_poll_enable(gp->dev);
2318
2319 up(&gp->pm_sem);
2320 }
2321
2322
2323 static int gem_open(struct net_device *dev)
2324 {
2325 struct gem *gp = dev->priv;
2326 int rc = 0;
2327
2328 down(&gp->pm_sem);
2329
2330 /* We need the cell enabled */
2331 if (!gp->asleep)
2332 rc = gem_do_start(dev);
2333 gp->opened = (rc == 0);
2334
2335 up(&gp->pm_sem);
2336
2337 return rc;
2338 }
2339
2340 static int gem_close(struct net_device *dev)
2341 {
2342 struct gem *gp = dev->priv;
2343
2344 /* Note: we don't need to call netif_poll_disable() here because
2345 * our caller (dev_close) already did it for us
2346 */
2347
2348 down(&gp->pm_sem);
2349
2350 gp->opened = 0;
2351 if (!gp->asleep)
2352 gem_do_stop(dev, 0);
2353
2354 up(&gp->pm_sem);
2355
2356 return 0;
2357 }
2358
2359 #ifdef CONFIG_PM
2360 static int gem_suspend(struct pci_dev *pdev, pm_message_t state)
2361 {
2362 struct net_device *dev = pci_get_drvdata(pdev);
2363 struct gem *gp = dev->priv;
2364 unsigned long flags;
2365
2366 down(&gp->pm_sem);
2367
2368 netif_poll_disable(dev);
2369
2370 printk(KERN_INFO "%s: suspending, WakeOnLan %s\n",
2371 dev->name,
2372 (gp->wake_on_lan && gp->opened) ? "enabled" : "disabled");
2373
2374 /* Keep the cell enabled during the entire operation */
2375 spin_lock_irqsave(&gp->lock, flags);
2376 spin_lock(&gp->tx_lock);
2377 gem_get_cell(gp);
2378 spin_unlock(&gp->tx_lock);
2379 spin_unlock_irqrestore(&gp->lock, flags);
2380
2381 /* If the driver is opened, we stop the MAC */
2382 if (gp->opened) {
2383 /* Stop traffic, mark us closed */
2384 netif_device_detach(dev);
2385
2386 /* Switch off MAC, remember WOL setting */
2387 gp->asleep_wol = gp->wake_on_lan;
2388 gem_do_stop(dev, gp->asleep_wol);
2389 } else
2390 gp->asleep_wol = 0;
2391
2392 /* Mark us asleep */
2393 gp->asleep = 1;
2394 wmb();
2395
2396 /* Stop the link timer */
2397 del_timer_sync(&gp->link_timer);
2398
2399 /* Now we release the semaphore to not block the reset task who
2400 * can take it too. We are marked asleep, so there will be no
2401 * conflict here
2402 */
2403 up(&gp->pm_sem);
2404
2405 /* Wait for a pending reset task to complete */
2406 while (gp->reset_task_pending)
2407 yield();
2408 flush_scheduled_work();
2409
2410 /* Shut the PHY down eventually and setup WOL */
2411 gem_stop_phy(gp, gp->asleep_wol);
2412
2413 /* Make sure bus master is disabled */
2414 pci_disable_device(gp->pdev);
2415
2416 /* Release the cell, no need to take a lock at this point since
2417 * nothing else can happen now
2418 */
2419 gem_put_cell(gp);
2420
2421 return 0;
2422 }
2423
2424 static int gem_resume(struct pci_dev *pdev)
2425 {
2426 struct net_device *dev = pci_get_drvdata(pdev);
2427 struct gem *gp = dev->priv;
2428 unsigned long flags;
2429
2430 printk(KERN_INFO "%s: resuming\n", dev->name);
2431
2432 down(&gp->pm_sem);
2433
2434 /* Keep the cell enabled during the entire operation, no need to
2435 * take a lock here tho since nothing else can happen while we are
2436 * marked asleep
2437 */
2438 gem_get_cell(gp);
2439
2440 /* Make sure PCI access and bus master are enabled */
2441 if (pci_enable_device(gp->pdev)) {
2442 printk(KERN_ERR "%s: Can't re-enable chip !\n",
2443 dev->name);
2444 /* Put cell and forget it for now, it will be considered as
2445 * still asleep, a new sleep cycle may bring it back
2446 */
2447 gem_put_cell(gp);
2448 up(&gp->pm_sem);
2449 return 0;
2450 }
2451 pci_set_master(gp->pdev);
2452
2453 /* Reset everything */
2454 gem_reset(gp);
2455
2456 /* Mark us woken up */
2457 gp->asleep = 0;
2458 wmb();
2459
2460 /* Bring the PHY back. Again, lock is useless at this point as
2461 * nothing can be happening until we restart the whole thing
2462 */
2463 gem_init_phy(gp);
2464
2465 /* If we were opened, bring everything back */
2466 if (gp->opened) {
2467 /* Restart MAC */
2468 gem_do_start(dev);
2469
2470 /* Re-attach net device */
2471 netif_device_attach(dev);
2472
2473 }
2474
2475 spin_lock_irqsave(&gp->lock, flags);
2476 spin_lock(&gp->tx_lock);
2477
2478 /* If we had WOL enabled, the cell clock was never turned off during
2479 * sleep, so we end up beeing unbalanced. Fix that here
2480 */
2481 if (gp->asleep_wol)
2482 gem_put_cell(gp);
2483
2484 /* This function doesn't need to hold the cell, it will be held if the
2485 * driver is open by gem_do_start().
2486 */
2487 gem_put_cell(gp);
2488
2489 spin_unlock(&gp->tx_lock);
2490 spin_unlock_irqrestore(&gp->lock, flags);
2491
2492 netif_poll_enable(dev);
2493
2494 up(&gp->pm_sem);
2495
2496 return 0;
2497 }
2498 #endif /* CONFIG_PM */
2499
2500 static struct net_device_stats *gem_get_stats(struct net_device *dev)
2501 {
2502 struct gem *gp = dev->priv;
2503 struct net_device_stats *stats = &gp->net_stats;
2504
2505 spin_lock_irq(&gp->lock);
2506 spin_lock(&gp->tx_lock);
2507
2508 /* I have seen this being called while the PM was in progress,
2509 * so we shield against this
2510 */
2511 if (gp->running) {
2512 stats->rx_crc_errors += readl(gp->regs + MAC_FCSERR);
2513 writel(0, gp->regs + MAC_FCSERR);
2514
2515 stats->rx_frame_errors += readl(gp->regs + MAC_AERR);
2516 writel(0, gp->regs + MAC_AERR);
2517
2518 stats->rx_length_errors += readl(gp->regs + MAC_LERR);
2519 writel(0, gp->regs + MAC_LERR);
2520
2521 stats->tx_aborted_errors += readl(gp->regs + MAC_ECOLL);
2522 stats->collisions +=
2523 (readl(gp->regs + MAC_ECOLL) +
2524 readl(gp->regs + MAC_LCOLL));
2525 writel(0, gp->regs + MAC_ECOLL);
2526 writel(0, gp->regs + MAC_LCOLL);
2527 }
2528
2529 spin_unlock(&gp->tx_lock);
2530 spin_unlock_irq(&gp->lock);
2531
2532 return &gp->net_stats;
2533 }
2534
2535 static void gem_set_multicast(struct net_device *dev)
2536 {
2537 struct gem *gp = dev->priv;
2538 u32 rxcfg, rxcfg_new;
2539 int limit = 10000;
2540
2541
2542 spin_lock_irq(&gp->lock);
2543 spin_lock(&gp->tx_lock);
2544
2545 if (!gp->running)
2546 goto bail;
2547
2548 netif_stop_queue(dev);
2549
2550 rxcfg = readl(gp->regs + MAC_RXCFG);
2551 rxcfg_new = gem_setup_multicast(gp);
2552 #ifdef STRIP_FCS
2553 rxcfg_new |= MAC_RXCFG_SFCS;
2554 #endif
2555 gp->mac_rx_cfg = rxcfg_new;
2556
2557 writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
2558 while (readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB) {
2559 if (!limit--)
2560 break;
2561 udelay(10);
2562 }
2563
2564 rxcfg &= ~(MAC_RXCFG_PROM | MAC_RXCFG_HFE);
2565 rxcfg |= rxcfg_new;
2566
2567 writel(rxcfg, gp->regs + MAC_RXCFG);
2568
2569 netif_wake_queue(dev);
2570
2571 bail:
2572 spin_unlock(&gp->tx_lock);
2573 spin_unlock_irq(&gp->lock);
2574 }
2575
2576 /* Jumbo-grams don't seem to work :-( */
2577 #define GEM_MIN_MTU 68
2578 #if 1
2579 #define GEM_MAX_MTU 1500
2580 #else
2581 #define GEM_MAX_MTU 9000
2582 #endif
2583
2584 static int gem_change_mtu(struct net_device *dev, int new_mtu)
2585 {
2586 struct gem *gp = dev->priv;
2587
2588 if (new_mtu < GEM_MIN_MTU || new_mtu > GEM_MAX_MTU)
2589 return -EINVAL;
2590
2591 if (!netif_running(dev) || !netif_device_present(dev)) {
2592 /* We'll just catch it later when the
2593 * device is up'd or resumed.
2594 */
2595 dev->mtu = new_mtu;
2596 return 0;
2597 }
2598
2599 down(&gp->pm_sem);
2600 spin_lock_irq(&gp->lock);
2601 spin_lock(&gp->tx_lock);
2602 dev->mtu = new_mtu;
2603 if (gp->running) {
2604 gem_reinit_chip(gp);
2605 if (gp->lstate == link_up)
2606 gem_set_link_modes(gp);
2607 }
2608 spin_unlock(&gp->tx_lock);
2609 spin_unlock_irq(&gp->lock);
2610 up(&gp->pm_sem);
2611
2612 return 0;
2613 }
2614
2615 static void gem_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2616 {
2617 struct gem *gp = dev->priv;
2618
2619 strcpy(info->driver, DRV_NAME);
2620 strcpy(info->version, DRV_VERSION);
2621 strcpy(info->bus_info, pci_name(gp->pdev));
2622 }
2623
2624 static int gem_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2625 {
2626 struct gem *gp = dev->priv;
2627
2628 if (gp->phy_type == phy_mii_mdio0 ||
2629 gp->phy_type == phy_mii_mdio1) {
2630 if (gp->phy_mii.def)
2631 cmd->supported = gp->phy_mii.def->features;
2632 else
2633 cmd->supported = (SUPPORTED_10baseT_Half |
2634 SUPPORTED_10baseT_Full);
2635
2636 /* XXX hardcoded stuff for now */
2637 cmd->port = PORT_MII;
2638 cmd->transceiver = XCVR_EXTERNAL;
2639 cmd->phy_address = 0; /* XXX fixed PHYAD */
2640
2641 /* Return current PHY settings */
2642 spin_lock_irq(&gp->lock);
2643 cmd->autoneg = gp->want_autoneg;
2644 cmd->speed = gp->phy_mii.speed;
2645 cmd->duplex = gp->phy_mii.duplex;
2646 cmd->advertising = gp->phy_mii.advertising;
2647
2648 /* If we started with a forced mode, we don't have a default
2649 * advertise set, we need to return something sensible so
2650 * userland can re-enable autoneg properly.
2651 */
2652 if (cmd->advertising == 0)
2653 cmd->advertising = cmd->supported;
2654 spin_unlock_irq(&gp->lock);
2655 } else { // XXX PCS ?
2656 cmd->supported =
2657 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2658 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2659 SUPPORTED_Autoneg);
2660 cmd->advertising = cmd->supported;
2661 cmd->speed = 0;
2662 cmd->duplex = cmd->port = cmd->phy_address =
2663 cmd->transceiver = cmd->autoneg = 0;
2664 }
2665 cmd->maxtxpkt = cmd->maxrxpkt = 0;
2666
2667 return 0;
2668 }
2669
2670 static int gem_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2671 {
2672 struct gem *gp = dev->priv;
2673
2674 /* Verify the settings we care about. */
2675 if (cmd->autoneg != AUTONEG_ENABLE &&
2676 cmd->autoneg != AUTONEG_DISABLE)
2677 return -EINVAL;
2678
2679 if (cmd->autoneg == AUTONEG_ENABLE &&
2680 cmd->advertising == 0)
2681 return -EINVAL;
2682
2683 if (cmd->autoneg == AUTONEG_DISABLE &&
2684 ((cmd->speed != SPEED_1000 &&
2685 cmd->speed != SPEED_100 &&
2686 cmd->speed != SPEED_10) ||
2687 (cmd->duplex != DUPLEX_HALF &&
2688 cmd->duplex != DUPLEX_FULL)))
2689 return -EINVAL;
2690
2691 /* Apply settings and restart link process. */
2692 spin_lock_irq(&gp->lock);
2693 gem_get_cell(gp);
2694 gem_begin_auto_negotiation(gp, cmd);
2695 gem_put_cell(gp);
2696 spin_unlock_irq(&gp->lock);
2697
2698 return 0;
2699 }
2700
2701 static int gem_nway_reset(struct net_device *dev)
2702 {
2703 struct gem *gp = dev->priv;
2704
2705 if (!gp->want_autoneg)
2706 return -EINVAL;
2707
2708 /* Restart link process. */
2709 spin_lock_irq(&gp->lock);
2710 gem_get_cell(gp);
2711 gem_begin_auto_negotiation(gp, NULL);
2712 gem_put_cell(gp);
2713 spin_unlock_irq(&gp->lock);
2714
2715 return 0;
2716 }
2717
2718 static u32 gem_get_msglevel(struct net_device *dev)
2719 {
2720 struct gem *gp = dev->priv;
2721 return gp->msg_enable;
2722 }
2723
2724 static void gem_set_msglevel(struct net_device *dev, u32 value)
2725 {
2726 struct gem *gp = dev->priv;
2727 gp->msg_enable = value;
2728 }
2729
2730
2731 /* Add more when I understand how to program the chip */
2732 /* like WAKE_UCAST | WAKE_MCAST | WAKE_BCAST */
2733
2734 #define WOL_SUPPORTED_MASK (WAKE_MAGIC)
2735
2736 static void gem_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2737 {
2738 struct gem *gp = dev->priv;
2739
2740 /* Add more when I understand how to program the chip */
2741 if (gp->has_wol) {
2742 wol->supported = WOL_SUPPORTED_MASK;
2743 wol->wolopts = gp->wake_on_lan;
2744 } else {
2745 wol->supported = 0;
2746 wol->wolopts = 0;
2747 }
2748 }
2749
2750 static int gem_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2751 {
2752 struct gem *gp = dev->priv;
2753
2754 if (!gp->has_wol)
2755 return -EOPNOTSUPP;
2756 gp->wake_on_lan = wol->wolopts & WOL_SUPPORTED_MASK;
2757 return 0;
2758 }
2759
2760 static struct ethtool_ops gem_ethtool_ops = {
2761 .get_drvinfo = gem_get_drvinfo,
2762 .get_link = ethtool_op_get_link,
2763 .get_settings = gem_get_settings,
2764 .set_settings = gem_set_settings,
2765 .nway_reset = gem_nway_reset,
2766 .get_msglevel = gem_get_msglevel,
2767 .set_msglevel = gem_set_msglevel,
2768 .get_wol = gem_get_wol,
2769 .set_wol = gem_set_wol,
2770 };
2771
2772 static int gem_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2773 {
2774 struct gem *gp = dev->priv;
2775 struct mii_ioctl_data *data = if_mii(ifr);
2776 int rc = -EOPNOTSUPP;
2777 unsigned long flags;
2778
2779 /* Hold the PM semaphore while doing ioctl's or we may collide
2780 * with power management.
2781 */
2782 down(&gp->pm_sem);
2783
2784 spin_lock_irqsave(&gp->lock, flags);
2785 gem_get_cell(gp);
2786 spin_unlock_irqrestore(&gp->lock, flags);
2787
2788 switch (cmd) {
2789 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
2790 data->phy_id = gp->mii_phy_addr;
2791 /* Fallthrough... */
2792
2793 case SIOCGMIIREG: /* Read MII PHY register. */
2794 if (!gp->running)
2795 rc = -EAGAIN;
2796 else {
2797 data->val_out = __phy_read(gp, data->phy_id & 0x1f,
2798 data->reg_num & 0x1f);
2799 rc = 0;
2800 }
2801 break;
2802
2803 case SIOCSMIIREG: /* Write MII PHY register. */
2804 if (!capable(CAP_NET_ADMIN))
2805 rc = -EPERM;
2806 else if (!gp->running)
2807 rc = -EAGAIN;
2808 else {
2809 __phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f,
2810 data->val_in);
2811 rc = 0;
2812 }
2813 break;
2814 };
2815
2816 spin_lock_irqsave(&gp->lock, flags);
2817 gem_put_cell(gp);
2818 spin_unlock_irqrestore(&gp->lock, flags);
2819
2820 up(&gp->pm_sem);
2821
2822 return rc;
2823 }
2824
2825 #if (!defined(__sparc__) && !defined(CONFIG_PPC_PMAC))
2826 /* Fetch MAC address from vital product data of PCI ROM. */
2827 static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, unsigned char *dev_addr)
2828 {
2829 int this_offset;
2830
2831 for (this_offset = 0x20; this_offset < len; this_offset++) {
2832 void __iomem *p = rom_base + this_offset;
2833 int i;
2834
2835 if (readb(p + 0) != 0x90 ||
2836 readb(p + 1) != 0x00 ||
2837 readb(p + 2) != 0x09 ||
2838 readb(p + 3) != 0x4e ||
2839 readb(p + 4) != 0x41 ||
2840 readb(p + 5) != 0x06)
2841 continue;
2842
2843 this_offset += 6;
2844 p += 6;
2845
2846 for (i = 0; i < 6; i++)
2847 dev_addr[i] = readb(p + i);
2848 return 1;
2849 }
2850 return 0;
2851 }
2852
2853 static void get_gem_mac_nonobp(struct pci_dev *pdev, unsigned char *dev_addr)
2854 {
2855 size_t size;
2856 void __iomem *p = pci_map_rom(pdev, &size);
2857
2858 if (p) {
2859 int found;
2860
2861 found = readb(p) == 0x55 &&
2862 readb(p + 1) == 0xaa &&
2863 find_eth_addr_in_vpd(p, (64 * 1024), dev_addr);
2864 pci_unmap_rom(pdev, p);
2865 if (found)
2866 return;
2867 }
2868
2869 /* Sun MAC prefix then 3 random bytes. */
2870 dev_addr[0] = 0x08;
2871 dev_addr[1] = 0x00;
2872 dev_addr[2] = 0x20;
2873 get_random_bytes(dev_addr + 3, 3);
2874 return;
2875 }
2876 #endif /* not Sparc and not PPC */
2877
2878 static int __devinit gem_get_device_address(struct gem *gp)
2879 {
2880 #if defined(__sparc__) || defined(CONFIG_PPC_PMAC)
2881 struct net_device *dev = gp->dev;
2882 #endif
2883
2884 #if defined(__sparc__)
2885 struct pci_dev *pdev = gp->pdev;
2886 struct pcidev_cookie *pcp = pdev->sysdata;
2887 int node = -1;
2888
2889 if (pcp != NULL) {
2890 node = pcp->prom_node;
2891 if (prom_getproplen(node, "local-mac-address") == 6)
2892 prom_getproperty(node, "local-mac-address",
2893 dev->dev_addr, 6);
2894 else
2895 node = -1;
2896 }
2897 if (node == -1)
2898 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2899 #elif defined(CONFIG_PPC_PMAC)
2900 unsigned char *addr;
2901
2902 addr = get_property(gp->of_node, "local-mac-address", NULL);
2903 if (addr == NULL) {
2904 printk("\n");
2905 printk(KERN_ERR "%s: can't get mac-address\n", dev->name);
2906 return -1;
2907 }
2908 memcpy(dev->dev_addr, addr, 6);
2909 #else
2910 get_gem_mac_nonobp(gp->pdev, gp->dev->dev_addr);
2911 #endif
2912 return 0;
2913 }
2914
2915 static void gem_remove_one(struct pci_dev *pdev)
2916 {
2917 struct net_device *dev = pci_get_drvdata(pdev);
2918
2919 if (dev) {
2920 struct gem *gp = dev->priv;
2921
2922 unregister_netdev(dev);
2923
2924 /* Stop the link timer */
2925 del_timer_sync(&gp->link_timer);
2926
2927 /* We shouldn't need any locking here */
2928 gem_get_cell(gp);
2929
2930 /* Wait for a pending reset task to complete */
2931 while (gp->reset_task_pending)
2932 yield();
2933 flush_scheduled_work();
2934
2935 /* Shut the PHY down */
2936 gem_stop_phy(gp, 0);
2937
2938 gem_put_cell(gp);
2939
2940 /* Make sure bus master is disabled */
2941 pci_disable_device(gp->pdev);
2942
2943 /* Free resources */
2944 pci_free_consistent(pdev,
2945 sizeof(struct gem_init_block),
2946 gp->init_block,
2947 gp->gblock_dvma);
2948 iounmap(gp->regs);
2949 pci_release_regions(pdev);
2950 free_netdev(dev);
2951
2952 pci_set_drvdata(pdev, NULL);
2953 }
2954 }
2955
2956 static int __devinit gem_init_one(struct pci_dev *pdev,
2957 const struct pci_device_id *ent)
2958 {
2959 static int gem_version_printed = 0;
2960 unsigned long gemreg_base, gemreg_len;
2961 struct net_device *dev;
2962 struct gem *gp;
2963 int i, err, pci_using_dac;
2964
2965 if (gem_version_printed++ == 0)
2966 printk(KERN_INFO "%s", version);
2967
2968 /* Apple gmac note: during probe, the chip is powered up by
2969 * the arch code to allow the code below to work (and to let
2970 * the chip be probed on the config space. It won't stay powered
2971 * up until the interface is brought up however, so we can't rely
2972 * on register configuration done at this point.
2973 */
2974 err = pci_enable_device(pdev);
2975 if (err) {
2976 printk(KERN_ERR PFX "Cannot enable MMIO operation, "
2977 "aborting.\n");
2978 return err;
2979 }
2980 pci_set_master(pdev);
2981
2982 /* Configure DMA attributes. */
2983
2984 /* All of the GEM documentation states that 64-bit DMA addressing
2985 * is fully supported and should work just fine. However the
2986 * front end for RIO based GEMs is different and only supports
2987 * 32-bit addressing.
2988 *
2989 * For now we assume the various PPC GEMs are 32-bit only as well.
2990 */
2991 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
2992 pdev->device == PCI_DEVICE_ID_SUN_GEM &&
2993 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
2994 pci_using_dac = 1;
2995 } else {
2996 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2997 if (err) {
2998 printk(KERN_ERR PFX "No usable DMA configuration, "
2999 "aborting.\n");
3000 goto err_disable_device;
3001 }
3002 pci_using_dac = 0;
3003 }
3004
3005 gemreg_base = pci_resource_start(pdev, 0);
3006 gemreg_len = pci_resource_len(pdev, 0);
3007
3008 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
3009 printk(KERN_ERR PFX "Cannot find proper PCI device "
3010 "base address, aborting.\n");
3011 err = -ENODEV;
3012 goto err_disable_device;
3013 }
3014
3015 dev = alloc_etherdev(sizeof(*gp));
3016 if (!dev) {
3017 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
3018 err = -ENOMEM;
3019 goto err_disable_device;
3020 }
3021 SET_MODULE_OWNER(dev);
3022 SET_NETDEV_DEV(dev, &pdev->dev);
3023
3024 gp = dev->priv;
3025
3026 err = pci_request_regions(pdev, DRV_NAME);
3027 if (err) {
3028 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
3029 "aborting.\n");
3030 goto err_out_free_netdev;
3031 }
3032
3033 gp->pdev = pdev;
3034 dev->base_addr = (long) pdev;
3035 gp->dev = dev;
3036
3037 gp->msg_enable = DEFAULT_MSG;
3038
3039 spin_lock_init(&gp->lock);
3040 spin_lock_init(&gp->tx_lock);
3041 init_MUTEX(&gp->pm_sem);
3042
3043 init_timer(&gp->link_timer);
3044 gp->link_timer.function = gem_link_timer;
3045 gp->link_timer.data = (unsigned long) gp;
3046
3047 INIT_WORK(&gp->reset_task, gem_reset_task, gp);
3048
3049 gp->lstate = link_down;
3050 gp->timer_ticks = 0;
3051 netif_carrier_off(dev);
3052
3053 gp->regs = ioremap(gemreg_base, gemreg_len);
3054 if (gp->regs == 0UL) {
3055 printk(KERN_ERR PFX "Cannot map device registers, "
3056 "aborting.\n");
3057 err = -EIO;
3058 goto err_out_free_res;
3059 }
3060
3061 /* On Apple, we want a reference to the Open Firmware device-tree
3062 * node. We use it for clock control.
3063 */
3064 #ifdef CONFIG_PPC_PMAC
3065 gp->of_node = pci_device_to_OF_node(pdev);
3066 #endif
3067
3068 /* Only Apple version supports WOL afaik */
3069 if (pdev->vendor == PCI_VENDOR_ID_APPLE)
3070 gp->has_wol = 1;
3071
3072 /* Make sure cell is enabled */
3073 gem_get_cell(gp);
3074
3075 /* Make sure everything is stopped and in init state */
3076 gem_reset(gp);
3077
3078 /* Fill up the mii_phy structure (even if we won't use it) */
3079 gp->phy_mii.dev = dev;
3080 gp->phy_mii.mdio_read = _phy_read;
3081 gp->phy_mii.mdio_write = _phy_write;
3082 #ifdef CONFIG_PPC_PMAC
3083 gp->phy_mii.platform_data = gp->of_node;
3084 #endif
3085 /* By default, we start with autoneg */
3086 gp->want_autoneg = 1;
3087
3088 /* Check fifo sizes, PHY type, etc... */
3089 if (gem_check_invariants(gp)) {
3090 err = -ENODEV;
3091 goto err_out_iounmap;
3092 }
3093
3094 /* It is guaranteed that the returned buffer will be at least
3095 * PAGE_SIZE aligned.
3096 */
3097 gp->init_block = (struct gem_init_block *)
3098 pci_alloc_consistent(pdev, sizeof(struct gem_init_block),
3099 &gp->gblock_dvma);
3100 if (!gp->init_block) {
3101 printk(KERN_ERR PFX "Cannot allocate init block, "
3102 "aborting.\n");
3103 err = -ENOMEM;
3104 goto err_out_iounmap;
3105 }
3106
3107 if (gem_get_device_address(gp))
3108 goto err_out_free_consistent;
3109
3110 dev->open = gem_open;
3111 dev->stop = gem_close;
3112 dev->hard_start_xmit = gem_start_xmit;
3113 dev->get_stats = gem_get_stats;
3114 dev->set_multicast_list = gem_set_multicast;
3115 dev->do_ioctl = gem_ioctl;
3116 dev->poll = gem_poll;
3117 dev->weight = 64;
3118 dev->ethtool_ops = &gem_ethtool_ops;
3119 dev->tx_timeout = gem_tx_timeout;
3120 dev->watchdog_timeo = 5 * HZ;
3121 dev->change_mtu = gem_change_mtu;
3122 dev->irq = pdev->irq;
3123 dev->dma = 0;
3124 #ifdef CONFIG_NET_POLL_CONTROLLER
3125 dev->poll_controller = gem_poll_controller;
3126 #endif
3127
3128 /* Set that now, in case PM kicks in now */
3129 pci_set_drvdata(pdev, dev);
3130
3131 /* Detect & init PHY, start autoneg, we release the cell now
3132 * too, it will be managed by whoever needs it
3133 */
3134 gem_init_phy(gp);
3135
3136 spin_lock_irq(&gp->lock);
3137 gem_put_cell(gp);
3138 spin_unlock_irq(&gp->lock);
3139
3140 /* Register with kernel */
3141 if (register_netdev(dev)) {
3142 printk(KERN_ERR PFX "Cannot register net device, "
3143 "aborting.\n");
3144 err = -ENOMEM;
3145 goto err_out_free_consistent;
3146 }
3147
3148 printk(KERN_INFO "%s: Sun GEM (PCI) 10/100/1000BaseT Ethernet ",
3149 dev->name);
3150 for (i = 0; i < 6; i++)
3151 printk("%2.2x%c", dev->dev_addr[i],
3152 i == 5 ? ' ' : ':');
3153 printk("\n");
3154
3155 if (gp->phy_type == phy_mii_mdio0 ||
3156 gp->phy_type == phy_mii_mdio1)
3157 printk(KERN_INFO "%s: Found %s PHY\n", dev->name,
3158 gp->phy_mii.def ? gp->phy_mii.def->name : "no");
3159
3160 /* GEM can do it all... */
3161 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_LLTX;
3162 if (pci_using_dac)
3163 dev->features |= NETIF_F_HIGHDMA;
3164
3165 return 0;
3166
3167 err_out_free_consistent:
3168 gem_remove_one(pdev);
3169 err_out_iounmap:
3170 gem_put_cell(gp);
3171 iounmap(gp->regs);
3172
3173 err_out_free_res:
3174 pci_release_regions(pdev);
3175
3176 err_out_free_netdev:
3177 free_netdev(dev);
3178 err_disable_device:
3179 pci_disable_device(pdev);
3180 return err;
3181
3182 }
3183
3184
3185 static struct pci_driver gem_driver = {
3186 .name = GEM_MODULE_NAME,
3187 .id_table = gem_pci_tbl,
3188 .probe = gem_init_one,
3189 .remove = gem_remove_one,
3190 #ifdef CONFIG_PM
3191 .suspend = gem_suspend,
3192 .resume = gem_resume,
3193 #endif /* CONFIG_PM */
3194 };
3195
3196 static int __init gem_init(void)
3197 {
3198 return pci_module_init(&gem_driver);
3199 }
3200
3201 static void __exit gem_cleanup(void)
3202 {
3203 pci_unregister_driver(&gem_driver);
3204 }
3205
3206 module_init(gem_init);
3207 module_exit(gem_cleanup);
Linux kernel - Deliverables
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