1 /* $Id: sungem.c,v 1.44.2.22 2002/03/13 01:18:12 davem Exp $
2 * sungem.c: Sun GEM ethernet driver.
4 * Copyright (C) 2000, 2001, 2002, 2003 David S. Miller (davem@redhat.com)
6 * Support for Apple GMAC and assorted PHYs, WOL, Power Management
7 * (C) 2001,2002,2003 Benjamin Herrenscmidt (benh@kernel.crashing.org)
8 * (C) 2004,2005 Benjamin Herrenscmidt, IBM Corp.
10 * NAPI and NETPOLL support
11 * (C) 2004 by Eric Lemoine (eric.lemoine@gmail.com)
14 * - Now that the driver was significantly simplified, I need to rework
15 * the locking. I'm sure we don't need _2_ spinlocks, and we probably
16 * can avoid taking most of them for so long period of time (and schedule
17 * instead). The main issues at this point are caused by the netdev layer
20 * gem_change_mtu() and gem_set_multicast() are called with a read_lock()
21 * help by net/core/dev.c, thus they can't schedule. That means they can't
22 * call netif_poll_disable() neither, thus force gem_poll() to keep a spinlock
23 * where it could have been dropped. change_mtu especially would love also to
24 * be able to msleep instead of horrid locked delays when resetting the HW,
25 * but that read_lock() makes it impossible, unless I defer it's action to
26 * the reset task, which means it'll be asynchronous (won't take effect until
27 * the system schedules a bit).
29 * Also, it would probably be possible to also remove most of the long-life
30 * locking in open/resume code path (gem_reinit_chip) by beeing more careful
31 * about when we can start taking interrupts or get xmit() called...
34 #include <linux/module.h>
35 #include <linux/kernel.h>
36 #include <linux/types.h>
37 #include <linux/fcntl.h>
38 #include <linux/interrupt.h>
39 #include <linux/ioport.h>
41 #include <linux/slab.h>
42 #include <linux/string.h>
43 #include <linux/delay.h>
44 #include <linux/init.h>
45 #include <linux/errno.h>
46 #include <linux/pci.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/netdevice.h>
49 #include <linux/etherdevice.h>
50 #include <linux/skbuff.h>
51 #include <linux/mii.h>
52 #include <linux/ethtool.h>
53 #include <linux/crc32.h>
54 #include <linux/random.h>
55 #include <linux/workqueue.h>
56 #include <linux/if_vlan.h>
57 #include <linux/bitops.h>
59 #include <asm/system.h>
61 #include <asm/byteorder.h>
62 #include <asm/uaccess.h>
66 #include <asm/idprom.h>
67 #include <asm/openprom.h>
68 #include <asm/oplib.h>
72 #ifdef CONFIG_PPC_PMAC
73 #include <asm/pci-bridge.h>
75 #include <asm/machdep.h>
76 #include <asm/pmac_feature.h>
79 #include "sungem_phy.h"
82 /* Stripping FCS is causing problems, disabled for now */
85 #define DEFAULT_MSG (NETIF_MSG_DRV | \
89 #define ADVERTISE_MASK (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
90 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
91 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)
93 #define DRV_NAME "sungem"
94 #define DRV_VERSION "0.98"
95 #define DRV_RELDATE "8/24/03"
96 #define DRV_AUTHOR "David S. Miller (davem@redhat.com)"
98 static char version
[] __devinitdata
=
99 DRV_NAME
".c:v" DRV_VERSION
" " DRV_RELDATE
" " DRV_AUTHOR
"\n";
101 MODULE_AUTHOR(DRV_AUTHOR
);
102 MODULE_DESCRIPTION("Sun GEM Gbit ethernet driver");
103 MODULE_LICENSE("GPL");
105 #define GEM_MODULE_NAME "gem"
106 #define PFX GEM_MODULE_NAME ": "
108 static struct pci_device_id gem_pci_tbl
[] = {
109 { PCI_VENDOR_ID_SUN
, PCI_DEVICE_ID_SUN_GEM
,
110 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
112 /* These models only differ from the original GEM in
113 * that their tx/rx fifos are of a different size and
114 * they only support 10/100 speeds. -DaveM
116 * Apple's GMAC does support gigabit on machines with
117 * the BCM54xx PHYs. -BenH
119 { PCI_VENDOR_ID_SUN
, PCI_DEVICE_ID_SUN_RIO_GEM
,
120 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
121 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_UNI_N_GMAC
,
122 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
123 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_UNI_N_GMACP
,
124 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
125 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_UNI_N_GMAC2
,
126 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
127 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_K2_GMAC
,
128 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
129 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_SH_SUNGEM
,
130 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
131 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_IPID2_GMAC
,
132 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
136 MODULE_DEVICE_TABLE(pci
, gem_pci_tbl
);
138 static u16
__phy_read(struct gem
*gp
, int phy_addr
, int reg
)
145 cmd
|= (phy_addr
<< 23) & MIF_FRAME_PHYAD
;
146 cmd
|= (reg
<< 18) & MIF_FRAME_REGAD
;
147 cmd
|= (MIF_FRAME_TAMSB
);
148 writel(cmd
, gp
->regs
+ MIF_FRAME
);
151 cmd
= readl(gp
->regs
+ MIF_FRAME
);
152 if (cmd
& MIF_FRAME_TALSB
)
161 return cmd
& MIF_FRAME_DATA
;
164 static inline int _phy_read(struct net_device
*dev
, int mii_id
, int reg
)
166 struct gem
*gp
= dev
->priv
;
167 return __phy_read(gp
, mii_id
, reg
);
170 static inline u16
phy_read(struct gem
*gp
, int reg
)
172 return __phy_read(gp
, gp
->mii_phy_addr
, reg
);
175 static void __phy_write(struct gem
*gp
, int phy_addr
, int reg
, u16 val
)
182 cmd
|= (phy_addr
<< 23) & MIF_FRAME_PHYAD
;
183 cmd
|= (reg
<< 18) & MIF_FRAME_REGAD
;
184 cmd
|= (MIF_FRAME_TAMSB
);
185 cmd
|= (val
& MIF_FRAME_DATA
);
186 writel(cmd
, gp
->regs
+ MIF_FRAME
);
189 cmd
= readl(gp
->regs
+ MIF_FRAME
);
190 if (cmd
& MIF_FRAME_TALSB
)
197 static inline void _phy_write(struct net_device
*dev
, int mii_id
, int reg
, int val
)
199 struct gem
*gp
= dev
->priv
;
200 __phy_write(gp
, mii_id
, reg
, val
& 0xffff);
203 static inline void phy_write(struct gem
*gp
, int reg
, u16 val
)
205 __phy_write(gp
, gp
->mii_phy_addr
, reg
, val
);
208 static inline void gem_enable_ints(struct gem
*gp
)
210 /* Enable all interrupts but TXDONE */
211 writel(GREG_STAT_TXDONE
, gp
->regs
+ GREG_IMASK
);
214 static inline void gem_disable_ints(struct gem
*gp
)
216 /* Disable all interrupts, including TXDONE */
217 writel(GREG_STAT_NAPI
| GREG_STAT_TXDONE
, gp
->regs
+ GREG_IMASK
);
220 static void gem_get_cell(struct gem
*gp
)
222 BUG_ON(gp
->cell_enabled
< 0);
224 #ifdef CONFIG_PPC_PMAC
225 if (gp
->cell_enabled
== 1) {
227 pmac_call_feature(PMAC_FTR_GMAC_ENABLE
, gp
->of_node
, 0, 1);
230 #endif /* CONFIG_PPC_PMAC */
233 /* Turn off the chip's clock */
234 static void gem_put_cell(struct gem
*gp
)
236 BUG_ON(gp
->cell_enabled
<= 0);
238 #ifdef CONFIG_PPC_PMAC
239 if (gp
->cell_enabled
== 0) {
241 pmac_call_feature(PMAC_FTR_GMAC_ENABLE
, gp
->of_node
, 0, 0);
244 #endif /* CONFIG_PPC_PMAC */
247 static void gem_handle_mif_event(struct gem
*gp
, u32 reg_val
, u32 changed_bits
)
249 if (netif_msg_intr(gp
))
250 printk(KERN_DEBUG
"%s: mif interrupt\n", gp
->dev
->name
);
253 static int gem_pcs_interrupt(struct net_device
*dev
, struct gem
*gp
, u32 gem_status
)
255 u32 pcs_istat
= readl(gp
->regs
+ PCS_ISTAT
);
258 if (netif_msg_intr(gp
))
259 printk(KERN_DEBUG
"%s: pcs interrupt, pcs_istat: 0x%x\n",
260 gp
->dev
->name
, pcs_istat
);
262 if (!(pcs_istat
& PCS_ISTAT_LSC
)) {
263 printk(KERN_ERR
"%s: PCS irq but no link status change???\n",
268 /* The link status bit latches on zero, so you must
269 * read it twice in such a case to see a transition
270 * to the link being up.
272 pcs_miistat
= readl(gp
->regs
+ PCS_MIISTAT
);
273 if (!(pcs_miistat
& PCS_MIISTAT_LS
))
275 (readl(gp
->regs
+ PCS_MIISTAT
) &
278 if (pcs_miistat
& PCS_MIISTAT_ANC
) {
279 /* The remote-fault indication is only valid
280 * when autoneg has completed.
282 if (pcs_miistat
& PCS_MIISTAT_RF
)
283 printk(KERN_INFO
"%s: PCS AutoNEG complete, "
284 "RemoteFault\n", dev
->name
);
286 printk(KERN_INFO
"%s: PCS AutoNEG complete.\n",
290 if (pcs_miistat
& PCS_MIISTAT_LS
) {
291 printk(KERN_INFO
"%s: PCS link is now up.\n",
293 netif_carrier_on(gp
->dev
);
295 printk(KERN_INFO
"%s: PCS link is now down.\n",
297 netif_carrier_off(gp
->dev
);
298 /* If this happens and the link timer is not running,
299 * reset so we re-negotiate.
301 if (!timer_pending(&gp
->link_timer
))
308 static int gem_txmac_interrupt(struct net_device
*dev
, struct gem
*gp
, u32 gem_status
)
310 u32 txmac_stat
= readl(gp
->regs
+ MAC_TXSTAT
);
312 if (netif_msg_intr(gp
))
313 printk(KERN_DEBUG
"%s: txmac interrupt, txmac_stat: 0x%x\n",
314 gp
->dev
->name
, txmac_stat
);
316 /* Defer timer expiration is quite normal,
317 * don't even log the event.
319 if ((txmac_stat
& MAC_TXSTAT_DTE
) &&
320 !(txmac_stat
& ~MAC_TXSTAT_DTE
))
323 if (txmac_stat
& MAC_TXSTAT_URUN
) {
324 printk(KERN_ERR
"%s: TX MAC xmit underrun.\n",
326 gp
->net_stats
.tx_fifo_errors
++;
329 if (txmac_stat
& MAC_TXSTAT_MPE
) {
330 printk(KERN_ERR
"%s: TX MAC max packet size error.\n",
332 gp
->net_stats
.tx_errors
++;
335 /* The rest are all cases of one of the 16-bit TX
338 if (txmac_stat
& MAC_TXSTAT_NCE
)
339 gp
->net_stats
.collisions
+= 0x10000;
341 if (txmac_stat
& MAC_TXSTAT_ECE
) {
342 gp
->net_stats
.tx_aborted_errors
+= 0x10000;
343 gp
->net_stats
.collisions
+= 0x10000;
346 if (txmac_stat
& MAC_TXSTAT_LCE
) {
347 gp
->net_stats
.tx_aborted_errors
+= 0x10000;
348 gp
->net_stats
.collisions
+= 0x10000;
351 /* We do not keep track of MAC_TXSTAT_FCE and
352 * MAC_TXSTAT_PCE events.
357 /* When we get a RX fifo overflow, the RX unit in GEM is probably hung
358 * so we do the following.
360 * If any part of the reset goes wrong, we return 1 and that causes the
361 * whole chip to be reset.
363 static int gem_rxmac_reset(struct gem
*gp
)
365 struct net_device
*dev
= gp
->dev
;
370 /* First, reset & disable MAC RX. */
371 writel(MAC_RXRST_CMD
, gp
->regs
+ MAC_RXRST
);
372 for (limit
= 0; limit
< 5000; limit
++) {
373 if (!(readl(gp
->regs
+ MAC_RXRST
) & MAC_RXRST_CMD
))
378 printk(KERN_ERR
"%s: RX MAC will not reset, resetting whole "
379 "chip.\n", dev
->name
);
383 writel(gp
->mac_rx_cfg
& ~MAC_RXCFG_ENAB
,
384 gp
->regs
+ MAC_RXCFG
);
385 for (limit
= 0; limit
< 5000; limit
++) {
386 if (!(readl(gp
->regs
+ MAC_RXCFG
) & MAC_RXCFG_ENAB
))
391 printk(KERN_ERR
"%s: RX MAC will not disable, resetting whole "
392 "chip.\n", dev
->name
);
396 /* Second, disable RX DMA. */
397 writel(0, gp
->regs
+ RXDMA_CFG
);
398 for (limit
= 0; limit
< 5000; limit
++) {
399 if (!(readl(gp
->regs
+ RXDMA_CFG
) & RXDMA_CFG_ENABLE
))
404 printk(KERN_ERR
"%s: RX DMA will not disable, resetting whole "
405 "chip.\n", dev
->name
);
411 /* Execute RX reset command. */
412 writel(gp
->swrst_base
| GREG_SWRST_RXRST
,
413 gp
->regs
+ GREG_SWRST
);
414 for (limit
= 0; limit
< 5000; limit
++) {
415 if (!(readl(gp
->regs
+ GREG_SWRST
) & GREG_SWRST_RXRST
))
420 printk(KERN_ERR
"%s: RX reset command will not execute, resetting "
421 "whole chip.\n", dev
->name
);
425 /* Refresh the RX ring. */
426 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
427 struct gem_rxd
*rxd
= &gp
->init_block
->rxd
[i
];
429 if (gp
->rx_skbs
[i
] == NULL
) {
430 printk(KERN_ERR
"%s: Parts of RX ring empty, resetting "
431 "whole chip.\n", dev
->name
);
435 rxd
->status_word
= cpu_to_le64(RXDCTRL_FRESH(gp
));
437 gp
->rx_new
= gp
->rx_old
= 0;
439 /* Now we must reprogram the rest of RX unit. */
440 desc_dma
= (u64
) gp
->gblock_dvma
;
441 desc_dma
+= (INIT_BLOCK_TX_RING_SIZE
* sizeof(struct gem_txd
));
442 writel(desc_dma
>> 32, gp
->regs
+ RXDMA_DBHI
);
443 writel(desc_dma
& 0xffffffff, gp
->regs
+ RXDMA_DBLOW
);
444 writel(RX_RING_SIZE
- 4, gp
->regs
+ RXDMA_KICK
);
445 val
= (RXDMA_CFG_BASE
| (RX_OFFSET
<< 10) |
446 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128
);
447 writel(val
, gp
->regs
+ RXDMA_CFG
);
448 if (readl(gp
->regs
+ GREG_BIFCFG
) & GREG_BIFCFG_M66EN
)
449 writel(((5 & RXDMA_BLANK_IPKTS
) |
450 ((8 << 12) & RXDMA_BLANK_ITIME
)),
451 gp
->regs
+ RXDMA_BLANK
);
453 writel(((5 & RXDMA_BLANK_IPKTS
) |
454 ((4 << 12) & RXDMA_BLANK_ITIME
)),
455 gp
->regs
+ RXDMA_BLANK
);
456 val
= (((gp
->rx_pause_off
/ 64) << 0) & RXDMA_PTHRESH_OFF
);
457 val
|= (((gp
->rx_pause_on
/ 64) << 12) & RXDMA_PTHRESH_ON
);
458 writel(val
, gp
->regs
+ RXDMA_PTHRESH
);
459 val
= readl(gp
->regs
+ RXDMA_CFG
);
460 writel(val
| RXDMA_CFG_ENABLE
, gp
->regs
+ RXDMA_CFG
);
461 writel(MAC_RXSTAT_RCV
, gp
->regs
+ MAC_RXMASK
);
462 val
= readl(gp
->regs
+ MAC_RXCFG
);
463 writel(val
| MAC_RXCFG_ENAB
, gp
->regs
+ MAC_RXCFG
);
468 static int gem_rxmac_interrupt(struct net_device
*dev
, struct gem
*gp
, u32 gem_status
)
470 u32 rxmac_stat
= readl(gp
->regs
+ MAC_RXSTAT
);
473 if (netif_msg_intr(gp
))
474 printk(KERN_DEBUG
"%s: rxmac interrupt, rxmac_stat: 0x%x\n",
475 gp
->dev
->name
, rxmac_stat
);
477 if (rxmac_stat
& MAC_RXSTAT_OFLW
) {
478 u32 smac
= readl(gp
->regs
+ MAC_SMACHINE
);
480 printk(KERN_ERR
"%s: RX MAC fifo overflow smac[%08x].\n",
482 gp
->net_stats
.rx_over_errors
++;
483 gp
->net_stats
.rx_fifo_errors
++;
485 ret
= gem_rxmac_reset(gp
);
488 if (rxmac_stat
& MAC_RXSTAT_ACE
)
489 gp
->net_stats
.rx_frame_errors
+= 0x10000;
491 if (rxmac_stat
& MAC_RXSTAT_CCE
)
492 gp
->net_stats
.rx_crc_errors
+= 0x10000;
494 if (rxmac_stat
& MAC_RXSTAT_LCE
)
495 gp
->net_stats
.rx_length_errors
+= 0x10000;
497 /* We do not track MAC_RXSTAT_FCE and MAC_RXSTAT_VCE
503 static int gem_mac_interrupt(struct net_device
*dev
, struct gem
*gp
, u32 gem_status
)
505 u32 mac_cstat
= readl(gp
->regs
+ MAC_CSTAT
);
507 if (netif_msg_intr(gp
))
508 printk(KERN_DEBUG
"%s: mac interrupt, mac_cstat: 0x%x\n",
509 gp
->dev
->name
, mac_cstat
);
511 /* This interrupt is just for pause frame and pause
512 * tracking. It is useful for diagnostics and debug
513 * but probably by default we will mask these events.
515 if (mac_cstat
& MAC_CSTAT_PS
)
518 if (mac_cstat
& MAC_CSTAT_PRCV
)
519 gp
->pause_last_time_recvd
= (mac_cstat
>> 16);
524 static int gem_mif_interrupt(struct net_device
*dev
, struct gem
*gp
, u32 gem_status
)
526 u32 mif_status
= readl(gp
->regs
+ MIF_STATUS
);
527 u32 reg_val
, changed_bits
;
529 reg_val
= (mif_status
& MIF_STATUS_DATA
) >> 16;
530 changed_bits
= (mif_status
& MIF_STATUS_STAT
);
532 gem_handle_mif_event(gp
, reg_val
, changed_bits
);
537 static int gem_pci_interrupt(struct net_device
*dev
, struct gem
*gp
, u32 gem_status
)
539 u32 pci_estat
= readl(gp
->regs
+ GREG_PCIESTAT
);
541 if (gp
->pdev
->vendor
== PCI_VENDOR_ID_SUN
&&
542 gp
->pdev
->device
== PCI_DEVICE_ID_SUN_GEM
) {
543 printk(KERN_ERR
"%s: PCI error [%04x] ",
544 dev
->name
, pci_estat
);
546 if (pci_estat
& GREG_PCIESTAT_BADACK
)
547 printk("<No ACK64# during ABS64 cycle> ");
548 if (pci_estat
& GREG_PCIESTAT_DTRTO
)
549 printk("<Delayed transaction timeout> ");
550 if (pci_estat
& GREG_PCIESTAT_OTHER
)
554 pci_estat
|= GREG_PCIESTAT_OTHER
;
555 printk(KERN_ERR
"%s: PCI error\n", dev
->name
);
558 if (pci_estat
& GREG_PCIESTAT_OTHER
) {
561 /* Interrogate PCI config space for the
564 pci_read_config_word(gp
->pdev
, PCI_STATUS
,
566 printk(KERN_ERR
"%s: Read PCI cfg space status [%04x]\n",
567 dev
->name
, pci_cfg_stat
);
568 if (pci_cfg_stat
& PCI_STATUS_PARITY
)
569 printk(KERN_ERR
"%s: PCI parity error detected.\n",
571 if (pci_cfg_stat
& PCI_STATUS_SIG_TARGET_ABORT
)
572 printk(KERN_ERR
"%s: PCI target abort.\n",
574 if (pci_cfg_stat
& PCI_STATUS_REC_TARGET_ABORT
)
575 printk(KERN_ERR
"%s: PCI master acks target abort.\n",
577 if (pci_cfg_stat
& PCI_STATUS_REC_MASTER_ABORT
)
578 printk(KERN_ERR
"%s: PCI master abort.\n",
580 if (pci_cfg_stat
& PCI_STATUS_SIG_SYSTEM_ERROR
)
581 printk(KERN_ERR
"%s: PCI system error SERR#.\n",
583 if (pci_cfg_stat
& PCI_STATUS_DETECTED_PARITY
)
584 printk(KERN_ERR
"%s: PCI parity error.\n",
587 /* Write the error bits back to clear them. */
588 pci_cfg_stat
&= (PCI_STATUS_PARITY
|
589 PCI_STATUS_SIG_TARGET_ABORT
|
590 PCI_STATUS_REC_TARGET_ABORT
|
591 PCI_STATUS_REC_MASTER_ABORT
|
592 PCI_STATUS_SIG_SYSTEM_ERROR
|
593 PCI_STATUS_DETECTED_PARITY
);
594 pci_write_config_word(gp
->pdev
,
595 PCI_STATUS
, pci_cfg_stat
);
598 /* For all PCI errors, we should reset the chip. */
602 /* All non-normal interrupt conditions get serviced here.
603 * Returns non-zero if we should just exit the interrupt
604 * handler right now (ie. if we reset the card which invalidates
605 * all of the other original irq status bits).
607 static int gem_abnormal_irq(struct net_device
*dev
, struct gem
*gp
, u32 gem_status
)
609 if (gem_status
& GREG_STAT_RXNOBUF
) {
610 /* Frame arrived, no free RX buffers available. */
611 if (netif_msg_rx_err(gp
))
612 printk(KERN_DEBUG
"%s: no buffer for rx frame\n",
614 gp
->net_stats
.rx_dropped
++;
617 if (gem_status
& GREG_STAT_RXTAGERR
) {
618 /* corrupt RX tag framing */
619 if (netif_msg_rx_err(gp
))
620 printk(KERN_DEBUG
"%s: corrupt rx tag framing\n",
622 gp
->net_stats
.rx_errors
++;
627 if (gem_status
& GREG_STAT_PCS
) {
628 if (gem_pcs_interrupt(dev
, gp
, gem_status
))
632 if (gem_status
& GREG_STAT_TXMAC
) {
633 if (gem_txmac_interrupt(dev
, gp
, gem_status
))
637 if (gem_status
& GREG_STAT_RXMAC
) {
638 if (gem_rxmac_interrupt(dev
, gp
, gem_status
))
642 if (gem_status
& GREG_STAT_MAC
) {
643 if (gem_mac_interrupt(dev
, gp
, gem_status
))
647 if (gem_status
& GREG_STAT_MIF
) {
648 if (gem_mif_interrupt(dev
, gp
, gem_status
))
652 if (gem_status
& GREG_STAT_PCIERR
) {
653 if (gem_pci_interrupt(dev
, gp
, gem_status
))
660 gp
->reset_task_pending
= 1;
661 schedule_work(&gp
->reset_task
);
666 static __inline__
void gem_tx(struct net_device
*dev
, struct gem
*gp
, u32 gem_status
)
670 if (netif_msg_intr(gp
))
671 printk(KERN_DEBUG
"%s: tx interrupt, gem_status: 0x%x\n",
672 gp
->dev
->name
, gem_status
);
675 limit
= ((gem_status
& GREG_STAT_TXNR
) >> GREG_STAT_TXNR_SHIFT
);
676 while (entry
!= limit
) {
683 if (netif_msg_tx_done(gp
))
684 printk(KERN_DEBUG
"%s: tx done, slot %d\n",
685 gp
->dev
->name
, entry
);
686 skb
= gp
->tx_skbs
[entry
];
687 if (skb_shinfo(skb
)->nr_frags
) {
688 int last
= entry
+ skb_shinfo(skb
)->nr_frags
;
692 last
&= (TX_RING_SIZE
- 1);
694 walk
= NEXT_TX(walk
);
703 gp
->tx_skbs
[entry
] = NULL
;
704 gp
->net_stats
.tx_bytes
+= skb
->len
;
706 for (frag
= 0; frag
<= skb_shinfo(skb
)->nr_frags
; frag
++) {
707 txd
= &gp
->init_block
->txd
[entry
];
709 dma_addr
= le64_to_cpu(txd
->buffer
);
710 dma_len
= le64_to_cpu(txd
->control_word
) & TXDCTRL_BUFSZ
;
712 pci_unmap_page(gp
->pdev
, dma_addr
, dma_len
, PCI_DMA_TODEVICE
);
713 entry
= NEXT_TX(entry
);
716 gp
->net_stats
.tx_packets
++;
717 dev_kfree_skb_irq(skb
);
721 if (netif_queue_stopped(dev
) &&
722 TX_BUFFS_AVAIL(gp
) > (MAX_SKB_FRAGS
+ 1))
723 netif_wake_queue(dev
);
726 static __inline__
void gem_post_rxds(struct gem
*gp
, int limit
)
728 int cluster_start
, curr
, count
, kick
;
730 cluster_start
= curr
= (gp
->rx_new
& ~(4 - 1));
734 while (curr
!= limit
) {
735 curr
= NEXT_RX(curr
);
737 struct gem_rxd
*rxd
=
738 &gp
->init_block
->rxd
[cluster_start
];
740 rxd
->status_word
= cpu_to_le64(RXDCTRL_FRESH(gp
));
742 cluster_start
= NEXT_RX(cluster_start
);
743 if (cluster_start
== curr
)
752 writel(kick
, gp
->regs
+ RXDMA_KICK
);
756 static int gem_rx(struct gem
*gp
, int work_to_do
)
758 int entry
, drops
, work_done
= 0;
761 if (netif_msg_rx_status(gp
))
762 printk(KERN_DEBUG
"%s: rx interrupt, done: %d, rx_new: %d\n",
763 gp
->dev
->name
, readl(gp
->regs
+ RXDMA_DONE
), gp
->rx_new
);
767 done
= readl(gp
->regs
+ RXDMA_DONE
);
769 struct gem_rxd
*rxd
= &gp
->init_block
->rxd
[entry
];
771 u64 status
= cpu_to_le64(rxd
->status_word
);
775 if ((status
& RXDCTRL_OWN
) != 0)
778 if (work_done
>= RX_RING_SIZE
|| work_done
>= work_to_do
)
781 /* When writing back RX descriptor, GEM writes status
782 * then buffer address, possibly in seperate transactions.
783 * If we don't wait for the chip to write both, we could
784 * post a new buffer to this descriptor then have GEM spam
785 * on the buffer address. We sync on the RX completion
786 * register to prevent this from happening.
789 done
= readl(gp
->regs
+ RXDMA_DONE
);
794 /* We can now account for the work we're about to do */
797 skb
= gp
->rx_skbs
[entry
];
799 len
= (status
& RXDCTRL_BUFSZ
) >> 16;
800 if ((len
< ETH_ZLEN
) || (status
& RXDCTRL_BAD
)) {
801 gp
->net_stats
.rx_errors
++;
803 gp
->net_stats
.rx_length_errors
++;
804 if (len
& RXDCTRL_BAD
)
805 gp
->net_stats
.rx_crc_errors
++;
807 /* We'll just return it to GEM. */
809 gp
->net_stats
.rx_dropped
++;
813 dma_addr
= cpu_to_le64(rxd
->buffer
);
814 if (len
> RX_COPY_THRESHOLD
) {
815 struct sk_buff
*new_skb
;
817 new_skb
= gem_alloc_skb(RX_BUF_ALLOC_SIZE(gp
), GFP_ATOMIC
);
818 if (new_skb
== NULL
) {
822 pci_unmap_page(gp
->pdev
, dma_addr
,
823 RX_BUF_ALLOC_SIZE(gp
),
825 gp
->rx_skbs
[entry
] = new_skb
;
826 new_skb
->dev
= gp
->dev
;
827 skb_put(new_skb
, (gp
->rx_buf_sz
+ RX_OFFSET
));
828 rxd
->buffer
= cpu_to_le64(pci_map_page(gp
->pdev
,
829 virt_to_page(new_skb
->data
),
830 offset_in_page(new_skb
->data
),
831 RX_BUF_ALLOC_SIZE(gp
),
832 PCI_DMA_FROMDEVICE
));
833 skb_reserve(new_skb
, RX_OFFSET
);
835 /* Trim the original skb for the netif. */
838 struct sk_buff
*copy_skb
= dev_alloc_skb(len
+ 2);
840 if (copy_skb
== NULL
) {
845 copy_skb
->dev
= gp
->dev
;
846 skb_reserve(copy_skb
, 2);
847 skb_put(copy_skb
, len
);
848 pci_dma_sync_single_for_cpu(gp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
849 memcpy(copy_skb
->data
, skb
->data
, len
);
850 pci_dma_sync_single_for_device(gp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
852 /* We'll reuse the original ring buffer. */
856 skb
->csum
= ntohs((status
& RXDCTRL_TCPCSUM
) ^ 0xffff);
857 skb
->ip_summed
= CHECKSUM_HW
;
858 skb
->protocol
= eth_type_trans(skb
, gp
->dev
);
860 netif_receive_skb(skb
);
862 gp
->net_stats
.rx_packets
++;
863 gp
->net_stats
.rx_bytes
+= len
;
864 gp
->dev
->last_rx
= jiffies
;
867 entry
= NEXT_RX(entry
);
870 gem_post_rxds(gp
, entry
);
875 printk(KERN_INFO
"%s: Memory squeeze, deferring packet.\n",
881 static int gem_poll(struct net_device
*dev
, int *budget
)
883 struct gem
*gp
= dev
->priv
;
887 * NAPI locking nightmare: See comment at head of driver
889 spin_lock_irqsave(&gp
->lock
, flags
);
892 int work_to_do
, work_done
;
894 /* Handle anomalies */
895 if (gp
->status
& GREG_STAT_ABNORMAL
) {
896 if (gem_abnormal_irq(dev
, gp
, gp
->status
))
900 /* Run TX completion thread */
901 spin_lock(&gp
->tx_lock
);
902 gem_tx(dev
, gp
, gp
->status
);
903 spin_unlock(&gp
->tx_lock
);
905 spin_unlock_irqrestore(&gp
->lock
, flags
);
907 /* Run RX thread. We don't use any locking here,
908 * code willing to do bad things - like cleaning the
909 * rx ring - must call netif_poll_disable(), which
910 * schedule_timeout()'s if polling is already disabled.
912 work_to_do
= min(*budget
, dev
->quota
);
914 work_done
= gem_rx(gp
, work_to_do
);
916 *budget
-= work_done
;
917 dev
->quota
-= work_done
;
919 if (work_done
>= work_to_do
)
922 spin_lock_irqsave(&gp
->lock
, flags
);
924 gp
->status
= readl(gp
->regs
+ GREG_STAT
);
925 } while (gp
->status
& GREG_STAT_NAPI
);
927 __netif_rx_complete(dev
);
930 spin_unlock_irqrestore(&gp
->lock
, flags
);
934 static irqreturn_t
gem_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
)
936 struct net_device
*dev
= dev_id
;
937 struct gem
*gp
= dev
->priv
;
940 /* Swallow interrupts when shutting the chip down, though
941 * that shouldn't happen, we should have done free_irq() at
947 spin_lock_irqsave(&gp
->lock
, flags
);
949 if (netif_rx_schedule_prep(dev
)) {
950 u32 gem_status
= readl(gp
->regs
+ GREG_STAT
);
952 if (gem_status
== 0) {
953 netif_poll_enable(dev
);
954 spin_unlock_irqrestore(&gp
->lock
, flags
);
957 gp
->status
= gem_status
;
958 gem_disable_ints(gp
);
959 __netif_rx_schedule(dev
);
962 spin_unlock_irqrestore(&gp
->lock
, flags
);
964 /* If polling was disabled at the time we received that
965 * interrupt, we may return IRQ_HANDLED here while we
966 * should return IRQ_NONE. No big deal...
971 #ifdef CONFIG_NET_POLL_CONTROLLER
972 static void gem_poll_controller(struct net_device
*dev
)
974 /* gem_interrupt is safe to reentrance so no need
975 * to disable_irq here.
977 gem_interrupt(dev
->irq
, dev
, NULL
);
981 static void gem_tx_timeout(struct net_device
*dev
)
983 struct gem
*gp
= dev
->priv
;
985 printk(KERN_ERR
"%s: transmit timed out, resetting\n", dev
->name
);
987 printk("%s: hrm.. hw not running !\n", dev
->name
);
990 printk(KERN_ERR
"%s: TX_STATE[%08x:%08x:%08x]\n",
992 readl(gp
->regs
+ TXDMA_CFG
),
993 readl(gp
->regs
+ MAC_TXSTAT
),
994 readl(gp
->regs
+ MAC_TXCFG
));
995 printk(KERN_ERR
"%s: RX_STATE[%08x:%08x:%08x]\n",
997 readl(gp
->regs
+ RXDMA_CFG
),
998 readl(gp
->regs
+ MAC_RXSTAT
),
999 readl(gp
->regs
+ MAC_RXCFG
));
1001 spin_lock_irq(&gp
->lock
);
1002 spin_lock(&gp
->tx_lock
);
1004 gp
->reset_task_pending
= 1;
1005 schedule_work(&gp
->reset_task
);
1007 spin_unlock(&gp
->tx_lock
);
1008 spin_unlock_irq(&gp
->lock
);
1011 static __inline__
int gem_intme(int entry
)
1013 /* Algorithm: IRQ every 1/2 of descriptors. */
1014 if (!(entry
& ((TX_RING_SIZE
>>1)-1)))
1020 static int gem_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1022 struct gem
*gp
= dev
->priv
;
1025 unsigned long flags
;
1028 if (skb
->ip_summed
== CHECKSUM_HW
) {
1029 u64 csum_start_off
, csum_stuff_off
;
1031 csum_start_off
= (u64
) (skb
->h
.raw
- skb
->data
);
1032 csum_stuff_off
= (u64
) ((skb
->h
.raw
+ skb
->csum
) - skb
->data
);
1034 ctrl
= (TXDCTRL_CENAB
|
1035 (csum_start_off
<< 15) |
1036 (csum_stuff_off
<< 21));
1039 local_irq_save(flags
);
1040 if (!spin_trylock(&gp
->tx_lock
)) {
1041 /* Tell upper layer to requeue */
1042 local_irq_restore(flags
);
1043 return NETDEV_TX_LOCKED
;
1045 /* We raced with gem_do_stop() */
1047 spin_unlock_irqrestore(&gp
->tx_lock
, flags
);
1048 return NETDEV_TX_BUSY
;
1051 /* This is a hard error, log it. */
1052 if (TX_BUFFS_AVAIL(gp
) <= (skb_shinfo(skb
)->nr_frags
+ 1)) {
1053 netif_stop_queue(dev
);
1054 spin_unlock_irqrestore(&gp
->tx_lock
, flags
);
1055 printk(KERN_ERR PFX
"%s: BUG! Tx Ring full when queue awake!\n",
1057 return NETDEV_TX_BUSY
;
1061 gp
->tx_skbs
[entry
] = skb
;
1063 if (skb_shinfo(skb
)->nr_frags
== 0) {
1064 struct gem_txd
*txd
= &gp
->init_block
->txd
[entry
];
1069 mapping
= pci_map_page(gp
->pdev
,
1070 virt_to_page(skb
->data
),
1071 offset_in_page(skb
->data
),
1072 len
, PCI_DMA_TODEVICE
);
1073 ctrl
|= TXDCTRL_SOF
| TXDCTRL_EOF
| len
;
1074 if (gem_intme(entry
))
1075 ctrl
|= TXDCTRL_INTME
;
1076 txd
->buffer
= cpu_to_le64(mapping
);
1078 txd
->control_word
= cpu_to_le64(ctrl
);
1079 entry
= NEXT_TX(entry
);
1081 struct gem_txd
*txd
;
1084 dma_addr_t first_mapping
;
1085 int frag
, first_entry
= entry
;
1088 if (gem_intme(entry
))
1089 intme
|= TXDCTRL_INTME
;
1091 /* We must give this initial chunk to the device last.
1092 * Otherwise we could race with the device.
1094 first_len
= skb_headlen(skb
);
1095 first_mapping
= pci_map_page(gp
->pdev
, virt_to_page(skb
->data
),
1096 offset_in_page(skb
->data
),
1097 first_len
, PCI_DMA_TODEVICE
);
1098 entry
= NEXT_TX(entry
);
1100 for (frag
= 0; frag
< skb_shinfo(skb
)->nr_frags
; frag
++) {
1101 skb_frag_t
*this_frag
= &skb_shinfo(skb
)->frags
[frag
];
1106 len
= this_frag
->size
;
1107 mapping
= pci_map_page(gp
->pdev
,
1109 this_frag
->page_offset
,
1110 len
, PCI_DMA_TODEVICE
);
1112 if (frag
== skb_shinfo(skb
)->nr_frags
- 1)
1113 this_ctrl
|= TXDCTRL_EOF
;
1115 txd
= &gp
->init_block
->txd
[entry
];
1116 txd
->buffer
= cpu_to_le64(mapping
);
1118 txd
->control_word
= cpu_to_le64(this_ctrl
| len
);
1120 if (gem_intme(entry
))
1121 intme
|= TXDCTRL_INTME
;
1123 entry
= NEXT_TX(entry
);
1125 txd
= &gp
->init_block
->txd
[first_entry
];
1126 txd
->buffer
= cpu_to_le64(first_mapping
);
1129 cpu_to_le64(ctrl
| TXDCTRL_SOF
| intme
| first_len
);
1133 if (TX_BUFFS_AVAIL(gp
) <= (MAX_SKB_FRAGS
+ 1))
1134 netif_stop_queue(dev
);
1136 if (netif_msg_tx_queued(gp
))
1137 printk(KERN_DEBUG
"%s: tx queued, slot %d, skblen %d\n",
1138 dev
->name
, entry
, skb
->len
);
1140 writel(gp
->tx_new
, gp
->regs
+ TXDMA_KICK
);
1141 spin_unlock_irqrestore(&gp
->tx_lock
, flags
);
1143 dev
->trans_start
= jiffies
;
1145 return NETDEV_TX_OK
;
1148 #define STOP_TRIES 32
1150 /* Must be invoked under gp->lock and gp->tx_lock. */
1151 static void gem_reset(struct gem
*gp
)
1156 /* Make sure we won't get any more interrupts */
1157 writel(0xffffffff, gp
->regs
+ GREG_IMASK
);
1159 /* Reset the chip */
1160 writel(gp
->swrst_base
| GREG_SWRST_TXRST
| GREG_SWRST_RXRST
,
1161 gp
->regs
+ GREG_SWRST
);
1167 val
= readl(gp
->regs
+ GREG_SWRST
);
1170 } while (val
& (GREG_SWRST_TXRST
| GREG_SWRST_RXRST
));
1173 printk(KERN_ERR
"%s: SW reset is ghetto.\n", gp
->dev
->name
);
1176 /* Must be invoked under gp->lock and gp->tx_lock. */
1177 static void gem_start_dma(struct gem
*gp
)
1181 /* We are ready to rock, turn everything on. */
1182 val
= readl(gp
->regs
+ TXDMA_CFG
);
1183 writel(val
| TXDMA_CFG_ENABLE
, gp
->regs
+ TXDMA_CFG
);
1184 val
= readl(gp
->regs
+ RXDMA_CFG
);
1185 writel(val
| RXDMA_CFG_ENABLE
, gp
->regs
+ RXDMA_CFG
);
1186 val
= readl(gp
->regs
+ MAC_TXCFG
);
1187 writel(val
| MAC_TXCFG_ENAB
, gp
->regs
+ MAC_TXCFG
);
1188 val
= readl(gp
->regs
+ MAC_RXCFG
);
1189 writel(val
| MAC_RXCFG_ENAB
, gp
->regs
+ MAC_RXCFG
);
1191 (void) readl(gp
->regs
+ MAC_RXCFG
);
1194 gem_enable_ints(gp
);
1196 writel(RX_RING_SIZE
- 4, gp
->regs
+ RXDMA_KICK
);
1199 /* Must be invoked under gp->lock and gp->tx_lock. DMA won't be
1200 * actually stopped before about 4ms tho ...
1202 static void gem_stop_dma(struct gem
*gp
)
1206 /* We are done rocking, turn everything off. */
1207 val
= readl(gp
->regs
+ TXDMA_CFG
);
1208 writel(val
& ~TXDMA_CFG_ENABLE
, gp
->regs
+ TXDMA_CFG
);
1209 val
= readl(gp
->regs
+ RXDMA_CFG
);
1210 writel(val
& ~RXDMA_CFG_ENABLE
, gp
->regs
+ RXDMA_CFG
);
1211 val
= readl(gp
->regs
+ MAC_TXCFG
);
1212 writel(val
& ~MAC_TXCFG_ENAB
, gp
->regs
+ MAC_TXCFG
);
1213 val
= readl(gp
->regs
+ MAC_RXCFG
);
1214 writel(val
& ~MAC_RXCFG_ENAB
, gp
->regs
+ MAC_RXCFG
);
1216 (void) readl(gp
->regs
+ MAC_RXCFG
);
1218 /* Need to wait a bit ... done by the caller */
1222 /* Must be invoked under gp->lock and gp->tx_lock. */
1223 // XXX dbl check what that function should do when called on PCS PHY
1224 static void gem_begin_auto_negotiation(struct gem
*gp
, struct ethtool_cmd
*ep
)
1226 u32 advertise
, features
;
1231 if (gp
->phy_type
!= phy_mii_mdio0
&&
1232 gp
->phy_type
!= phy_mii_mdio1
)
1235 /* Setup advertise */
1236 if (found_mii_phy(gp
))
1237 features
= gp
->phy_mii
.def
->features
;
1241 advertise
= features
& ADVERTISE_MASK
;
1242 if (gp
->phy_mii
.advertising
!= 0)
1243 advertise
&= gp
->phy_mii
.advertising
;
1245 autoneg
= gp
->want_autoneg
;
1246 speed
= gp
->phy_mii
.speed
;
1247 duplex
= gp
->phy_mii
.duplex
;
1249 /* Setup link parameters */
1252 if (ep
->autoneg
== AUTONEG_ENABLE
) {
1253 advertise
= ep
->advertising
;
1258 duplex
= ep
->duplex
;
1262 /* Sanitize settings based on PHY capabilities */
1263 if ((features
& SUPPORTED_Autoneg
) == 0)
1265 if (speed
== SPEED_1000
&&
1266 !(features
& (SUPPORTED_1000baseT_Half
| SUPPORTED_1000baseT_Full
)))
1268 if (speed
== SPEED_100
&&
1269 !(features
& (SUPPORTED_100baseT_Half
| SUPPORTED_100baseT_Full
)))
1271 if (duplex
== DUPLEX_FULL
&&
1272 !(features
& (SUPPORTED_1000baseT_Full
|
1273 SUPPORTED_100baseT_Full
|
1274 SUPPORTED_10baseT_Full
)))
1275 duplex
= DUPLEX_HALF
;
1279 /* If we are asleep, we don't try to actually setup the PHY, we
1280 * just store the settings
1283 gp
->phy_mii
.autoneg
= gp
->want_autoneg
= autoneg
;
1284 gp
->phy_mii
.speed
= speed
;
1285 gp
->phy_mii
.duplex
= duplex
;
1289 /* Configure PHY & start aneg */
1290 gp
->want_autoneg
= autoneg
;
1292 if (found_mii_phy(gp
))
1293 gp
->phy_mii
.def
->ops
->setup_aneg(&gp
->phy_mii
, advertise
);
1294 gp
->lstate
= link_aneg
;
1296 if (found_mii_phy(gp
))
1297 gp
->phy_mii
.def
->ops
->setup_forced(&gp
->phy_mii
, speed
, duplex
);
1298 gp
->lstate
= link_force_ok
;
1302 gp
->timer_ticks
= 0;
1303 mod_timer(&gp
->link_timer
, jiffies
+ ((12 * HZ
) / 10));
1306 /* A link-up condition has occurred, initialize and enable the
1309 * Must be invoked under gp->lock and gp->tx_lock.
1311 static int gem_set_link_modes(struct gem
*gp
)
1314 int full_duplex
, speed
, pause
;
1320 if (found_mii_phy(gp
)) {
1321 if (gp
->phy_mii
.def
->ops
->read_link(&gp
->phy_mii
))
1323 full_duplex
= (gp
->phy_mii
.duplex
== DUPLEX_FULL
);
1324 speed
= gp
->phy_mii
.speed
;
1325 pause
= gp
->phy_mii
.pause
;
1326 } else if (gp
->phy_type
== phy_serialink
||
1327 gp
->phy_type
== phy_serdes
) {
1328 u32 pcs_lpa
= readl(gp
->regs
+ PCS_MIILP
);
1330 if (pcs_lpa
& PCS_MIIADV_FD
)
1335 if (netif_msg_link(gp
))
1336 printk(KERN_INFO
"%s: Link is up at %d Mbps, %s-duplex.\n",
1337 gp
->dev
->name
, speed
, (full_duplex
? "full" : "half"));
1342 val
= (MAC_TXCFG_EIPG0
| MAC_TXCFG_NGU
);
1344 val
|= (MAC_TXCFG_ICS
| MAC_TXCFG_ICOLL
);
1346 /* MAC_TXCFG_NBO must be zero. */
1348 writel(val
, gp
->regs
+ MAC_TXCFG
);
1350 val
= (MAC_XIFCFG_OE
| MAC_XIFCFG_LLED
);
1352 (gp
->phy_type
== phy_mii_mdio0
||
1353 gp
->phy_type
== phy_mii_mdio1
)) {
1354 val
|= MAC_XIFCFG_DISE
;
1355 } else if (full_duplex
) {
1356 val
|= MAC_XIFCFG_FLED
;
1359 if (speed
== SPEED_1000
)
1360 val
|= (MAC_XIFCFG_GMII
);
1362 writel(val
, gp
->regs
+ MAC_XIFCFG
);
1364 /* If gigabit and half-duplex, enable carrier extension
1365 * mode. Else, disable it.
1367 if (speed
== SPEED_1000
&& !full_duplex
) {
1368 val
= readl(gp
->regs
+ MAC_TXCFG
);
1369 writel(val
| MAC_TXCFG_TCE
, gp
->regs
+ MAC_TXCFG
);
1371 val
= readl(gp
->regs
+ MAC_RXCFG
);
1372 writel(val
| MAC_RXCFG_RCE
, gp
->regs
+ MAC_RXCFG
);
1374 val
= readl(gp
->regs
+ MAC_TXCFG
);
1375 writel(val
& ~MAC_TXCFG_TCE
, gp
->regs
+ MAC_TXCFG
);
1377 val
= readl(gp
->regs
+ MAC_RXCFG
);
1378 writel(val
& ~MAC_RXCFG_RCE
, gp
->regs
+ MAC_RXCFG
);
1381 if (gp
->phy_type
== phy_serialink
||
1382 gp
->phy_type
== phy_serdes
) {
1383 u32 pcs_lpa
= readl(gp
->regs
+ PCS_MIILP
);
1385 if (pcs_lpa
& (PCS_MIIADV_SP
| PCS_MIIADV_AP
))
1389 if (netif_msg_link(gp
)) {
1391 printk(KERN_INFO
"%s: Pause is enabled "
1392 "(rxfifo: %d off: %d on: %d)\n",
1398 printk(KERN_INFO
"%s: Pause is disabled\n",
1404 writel(512, gp
->regs
+ MAC_STIME
);
1406 writel(64, gp
->regs
+ MAC_STIME
);
1407 val
= readl(gp
->regs
+ MAC_MCCFG
);
1409 val
|= (MAC_MCCFG_SPE
| MAC_MCCFG_RPE
);
1411 val
&= ~(MAC_MCCFG_SPE
| MAC_MCCFG_RPE
);
1412 writel(val
, gp
->regs
+ MAC_MCCFG
);
1419 /* Must be invoked under gp->lock and gp->tx_lock. */
1420 static int gem_mdio_link_not_up(struct gem
*gp
)
1422 switch (gp
->lstate
) {
1423 case link_force_ret
:
1424 if (netif_msg_link(gp
))
1425 printk(KERN_INFO
"%s: Autoneg failed again, keeping"
1426 " forced mode\n", gp
->dev
->name
);
1427 gp
->phy_mii
.def
->ops
->setup_forced(&gp
->phy_mii
,
1428 gp
->last_forced_speed
, DUPLEX_HALF
);
1429 gp
->timer_ticks
= 5;
1430 gp
->lstate
= link_force_ok
;
1433 /* We try forced modes after a failed aneg only on PHYs that don't
1434 * have "magic_aneg" bit set, which means they internally do the
1435 * while forced-mode thingy. On these, we just restart aneg
1437 if (gp
->phy_mii
.def
->magic_aneg
)
1439 if (netif_msg_link(gp
))
1440 printk(KERN_INFO
"%s: switching to forced 100bt\n",
1442 /* Try forced modes. */
1443 gp
->phy_mii
.def
->ops
->setup_forced(&gp
->phy_mii
, SPEED_100
,
1445 gp
->timer_ticks
= 5;
1446 gp
->lstate
= link_force_try
;
1448 case link_force_try
:
1449 /* Downgrade from 100 to 10 Mbps if necessary.
1450 * If already at 10Mbps, warn user about the
1451 * situation every 10 ticks.
1453 if (gp
->phy_mii
.speed
== SPEED_100
) {
1454 gp
->phy_mii
.def
->ops
->setup_forced(&gp
->phy_mii
, SPEED_10
,
1456 gp
->timer_ticks
= 5;
1457 if (netif_msg_link(gp
))
1458 printk(KERN_INFO
"%s: switching to forced 10bt\n",
1468 static void gem_link_timer(unsigned long data
)
1470 struct gem
*gp
= (struct gem
*) data
;
1471 int restart_aneg
= 0;
1476 spin_lock_irq(&gp
->lock
);
1477 spin_lock(&gp
->tx_lock
);
1480 /* If the reset task is still pending, we just
1481 * reschedule the link timer
1483 if (gp
->reset_task_pending
)
1486 if (gp
->phy_type
== phy_serialink
||
1487 gp
->phy_type
== phy_serdes
) {
1488 u32 val
= readl(gp
->regs
+ PCS_MIISTAT
);
1490 if (!(val
& PCS_MIISTAT_LS
))
1491 val
= readl(gp
->regs
+ PCS_MIISTAT
);
1493 if ((val
& PCS_MIISTAT_LS
) != 0) {
1494 gp
->lstate
= link_up
;
1495 netif_carrier_on(gp
->dev
);
1496 (void)gem_set_link_modes(gp
);
1500 if (found_mii_phy(gp
) && gp
->phy_mii
.def
->ops
->poll_link(&gp
->phy_mii
)) {
1501 /* Ok, here we got a link. If we had it due to a forced
1502 * fallback, and we were configured for autoneg, we do
1503 * retry a short autoneg pass. If you know your hub is
1504 * broken, use ethtool ;)
1506 if (gp
->lstate
== link_force_try
&& gp
->want_autoneg
) {
1507 gp
->lstate
= link_force_ret
;
1508 gp
->last_forced_speed
= gp
->phy_mii
.speed
;
1509 gp
->timer_ticks
= 5;
1510 if (netif_msg_link(gp
))
1511 printk(KERN_INFO
"%s: Got link after fallback, retrying"
1512 " autoneg once...\n", gp
->dev
->name
);
1513 gp
->phy_mii
.def
->ops
->setup_aneg(&gp
->phy_mii
, gp
->phy_mii
.advertising
);
1514 } else if (gp
->lstate
!= link_up
) {
1515 gp
->lstate
= link_up
;
1516 netif_carrier_on(gp
->dev
);
1517 if (gem_set_link_modes(gp
))
1521 /* If the link was previously up, we restart the
1524 if (gp
->lstate
== link_up
) {
1525 gp
->lstate
= link_down
;
1526 if (netif_msg_link(gp
))
1527 printk(KERN_INFO
"%s: Link down\n",
1529 netif_carrier_off(gp
->dev
);
1530 gp
->reset_task_pending
= 1;
1531 schedule_work(&gp
->reset_task
);
1533 } else if (++gp
->timer_ticks
> 10) {
1534 if (found_mii_phy(gp
))
1535 restart_aneg
= gem_mdio_link_not_up(gp
);
1541 gem_begin_auto_negotiation(gp
, NULL
);
1545 mod_timer(&gp
->link_timer
, jiffies
+ ((12 * HZ
) / 10));
1548 spin_unlock(&gp
->tx_lock
);
1549 spin_unlock_irq(&gp
->lock
);
1552 /* Must be invoked under gp->lock and gp->tx_lock. */
1553 static void gem_clean_rings(struct gem
*gp
)
1555 struct gem_init_block
*gb
= gp
->init_block
;
1556 struct sk_buff
*skb
;
1558 dma_addr_t dma_addr
;
1560 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
1561 struct gem_rxd
*rxd
;
1564 if (gp
->rx_skbs
[i
] != NULL
) {
1565 skb
= gp
->rx_skbs
[i
];
1566 dma_addr
= le64_to_cpu(rxd
->buffer
);
1567 pci_unmap_page(gp
->pdev
, dma_addr
,
1568 RX_BUF_ALLOC_SIZE(gp
),
1569 PCI_DMA_FROMDEVICE
);
1570 dev_kfree_skb_any(skb
);
1571 gp
->rx_skbs
[i
] = NULL
;
1573 rxd
->status_word
= 0;
1578 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
1579 if (gp
->tx_skbs
[i
] != NULL
) {
1580 struct gem_txd
*txd
;
1583 skb
= gp
->tx_skbs
[i
];
1584 gp
->tx_skbs
[i
] = NULL
;
1586 for (frag
= 0; frag
<= skb_shinfo(skb
)->nr_frags
; frag
++) {
1587 int ent
= i
& (TX_RING_SIZE
- 1);
1589 txd
= &gb
->txd
[ent
];
1590 dma_addr
= le64_to_cpu(txd
->buffer
);
1591 pci_unmap_page(gp
->pdev
, dma_addr
,
1592 le64_to_cpu(txd
->control_word
) &
1593 TXDCTRL_BUFSZ
, PCI_DMA_TODEVICE
);
1595 if (frag
!= skb_shinfo(skb
)->nr_frags
)
1598 dev_kfree_skb_any(skb
);
1603 /* Must be invoked under gp->lock and gp->tx_lock. */
1604 static void gem_init_rings(struct gem
*gp
)
1606 struct gem_init_block
*gb
= gp
->init_block
;
1607 struct net_device
*dev
= gp
->dev
;
1609 dma_addr_t dma_addr
;
1611 gp
->rx_new
= gp
->rx_old
= gp
->tx_new
= gp
->tx_old
= 0;
1613 gem_clean_rings(gp
);
1615 gp
->rx_buf_sz
= max(dev
->mtu
+ ETH_HLEN
+ VLAN_HLEN
,
1616 (unsigned)VLAN_ETH_FRAME_LEN
);
1618 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
1619 struct sk_buff
*skb
;
1620 struct gem_rxd
*rxd
= &gb
->rxd
[i
];
1622 skb
= gem_alloc_skb(RX_BUF_ALLOC_SIZE(gp
), GFP_ATOMIC
);
1625 rxd
->status_word
= 0;
1629 gp
->rx_skbs
[i
] = skb
;
1631 skb_put(skb
, (gp
->rx_buf_sz
+ RX_OFFSET
));
1632 dma_addr
= pci_map_page(gp
->pdev
,
1633 virt_to_page(skb
->data
),
1634 offset_in_page(skb
->data
),
1635 RX_BUF_ALLOC_SIZE(gp
),
1636 PCI_DMA_FROMDEVICE
);
1637 rxd
->buffer
= cpu_to_le64(dma_addr
);
1639 rxd
->status_word
= cpu_to_le64(RXDCTRL_FRESH(gp
));
1640 skb_reserve(skb
, RX_OFFSET
);
1643 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
1644 struct gem_txd
*txd
= &gb
->txd
[i
];
1646 txd
->control_word
= 0;
1653 /* Init PHY interface and start link poll state machine */
1654 static void gem_init_phy(struct gem
*gp
)
1658 /* Revert MIF CFG setting done on stop_phy */
1659 mif_cfg
= readl(gp
->regs
+ MIF_CFG
);
1660 mif_cfg
&= ~(MIF_CFG_PSELECT
|MIF_CFG_POLL
|MIF_CFG_BBMODE
|MIF_CFG_MDI1
);
1661 mif_cfg
|= MIF_CFG_MDI0
;
1662 writel(mif_cfg
, gp
->regs
+ MIF_CFG
);
1663 writel(PCS_DMODE_MGM
, gp
->regs
+ PCS_DMODE
);
1664 writel(MAC_XIFCFG_OE
, gp
->regs
+ MAC_XIFCFG
);
1666 if (gp
->pdev
->vendor
== PCI_VENDOR_ID_APPLE
) {
1670 #ifdef CONFIG_PPC_PMAC
1671 pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET
, gp
->of_node
, 0, 0);
1674 /* Some PHYs used by apple have problem getting back
1675 * to us, we do an additional reset here
1677 phy_write(gp
, MII_BMCR
, BMCR_RESET
);
1678 for (i
= 0; i
< 50; i
++) {
1679 if ((phy_read(gp
, MII_BMCR
) & BMCR_RESET
) == 0)
1684 printk(KERN_WARNING
"%s: GMAC PHY not responding !\n",
1686 /* Make sure isolate is off */
1687 ctrl
= phy_read(gp
, MII_BMCR
);
1688 if (ctrl
& BMCR_ISOLATE
)
1689 phy_write(gp
, MII_BMCR
, ctrl
& ~BMCR_ISOLATE
);
1692 if (gp
->pdev
->vendor
== PCI_VENDOR_ID_SUN
&&
1693 gp
->pdev
->device
== PCI_DEVICE_ID_SUN_GEM
) {
1696 /* Init datapath mode register. */
1697 if (gp
->phy_type
== phy_mii_mdio0
||
1698 gp
->phy_type
== phy_mii_mdio1
) {
1699 val
= PCS_DMODE_MGM
;
1700 } else if (gp
->phy_type
== phy_serialink
) {
1701 val
= PCS_DMODE_SM
| PCS_DMODE_GMOE
;
1703 val
= PCS_DMODE_ESM
;
1706 writel(val
, gp
->regs
+ PCS_DMODE
);
1709 if (gp
->phy_type
== phy_mii_mdio0
||
1710 gp
->phy_type
== phy_mii_mdio1
) {
1711 // XXX check for errors
1712 mii_phy_probe(&gp
->phy_mii
, gp
->mii_phy_addr
);
1715 if (gp
->phy_mii
.def
&& gp
->phy_mii
.def
->ops
->init
)
1716 gp
->phy_mii
.def
->ops
->init(&gp
->phy_mii
);
1721 /* Reset PCS unit. */
1722 val
= readl(gp
->regs
+ PCS_MIICTRL
);
1723 val
|= PCS_MIICTRL_RST
;
1724 writeb(val
, gp
->regs
+ PCS_MIICTRL
);
1727 while (readl(gp
->regs
+ PCS_MIICTRL
) & PCS_MIICTRL_RST
) {
1733 printk(KERN_WARNING
"%s: PCS reset bit would not clear.\n",
1736 /* Make sure PCS is disabled while changing advertisement
1739 val
= readl(gp
->regs
+ PCS_CFG
);
1740 val
&= ~(PCS_CFG_ENABLE
| PCS_CFG_TO
);
1741 writel(val
, gp
->regs
+ PCS_CFG
);
1743 /* Advertise all capabilities except assymetric
1746 val
= readl(gp
->regs
+ PCS_MIIADV
);
1747 val
|= (PCS_MIIADV_FD
| PCS_MIIADV_HD
|
1748 PCS_MIIADV_SP
| PCS_MIIADV_AP
);
1749 writel(val
, gp
->regs
+ PCS_MIIADV
);
1751 /* Enable and restart auto-negotiation, disable wrapback/loopback,
1752 * and re-enable PCS.
1754 val
= readl(gp
->regs
+ PCS_MIICTRL
);
1755 val
|= (PCS_MIICTRL_RAN
| PCS_MIICTRL_ANE
);
1756 val
&= ~PCS_MIICTRL_WB
;
1757 writel(val
, gp
->regs
+ PCS_MIICTRL
);
1759 val
= readl(gp
->regs
+ PCS_CFG
);
1760 val
|= PCS_CFG_ENABLE
;
1761 writel(val
, gp
->regs
+ PCS_CFG
);
1763 /* Make sure serialink loopback is off. The meaning
1764 * of this bit is logically inverted based upon whether
1765 * you are in Serialink or SERDES mode.
1767 val
= readl(gp
->regs
+ PCS_SCTRL
);
1768 if (gp
->phy_type
== phy_serialink
)
1769 val
&= ~PCS_SCTRL_LOOP
;
1771 val
|= PCS_SCTRL_LOOP
;
1772 writel(val
, gp
->regs
+ PCS_SCTRL
);
1775 /* Default aneg parameters */
1776 gp
->timer_ticks
= 0;
1777 gp
->lstate
= link_down
;
1778 netif_carrier_off(gp
->dev
);
1780 /* Can I advertise gigabit here ? I'd need BCM PHY docs... */
1781 spin_lock_irq(&gp
->lock
);
1782 gem_begin_auto_negotiation(gp
, NULL
);
1783 spin_unlock_irq(&gp
->lock
);
1786 /* Must be invoked under gp->lock and gp->tx_lock. */
1787 static void gem_init_dma(struct gem
*gp
)
1789 u64 desc_dma
= (u64
) gp
->gblock_dvma
;
1792 val
= (TXDMA_CFG_BASE
| (0x7ff << 10) | TXDMA_CFG_PMODE
);
1793 writel(val
, gp
->regs
+ TXDMA_CFG
);
1795 writel(desc_dma
>> 32, gp
->regs
+ TXDMA_DBHI
);
1796 writel(desc_dma
& 0xffffffff, gp
->regs
+ TXDMA_DBLOW
);
1797 desc_dma
+= (INIT_BLOCK_TX_RING_SIZE
* sizeof(struct gem_txd
));
1799 writel(0, gp
->regs
+ TXDMA_KICK
);
1801 val
= (RXDMA_CFG_BASE
| (RX_OFFSET
<< 10) |
1802 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128
);
1803 writel(val
, gp
->regs
+ RXDMA_CFG
);
1805 writel(desc_dma
>> 32, gp
->regs
+ RXDMA_DBHI
);
1806 writel(desc_dma
& 0xffffffff, gp
->regs
+ RXDMA_DBLOW
);
1808 writel(RX_RING_SIZE
- 4, gp
->regs
+ RXDMA_KICK
);
1810 val
= (((gp
->rx_pause_off
/ 64) << 0) & RXDMA_PTHRESH_OFF
);
1811 val
|= (((gp
->rx_pause_on
/ 64) << 12) & RXDMA_PTHRESH_ON
);
1812 writel(val
, gp
->regs
+ RXDMA_PTHRESH
);
1814 if (readl(gp
->regs
+ GREG_BIFCFG
) & GREG_BIFCFG_M66EN
)
1815 writel(((5 & RXDMA_BLANK_IPKTS
) |
1816 ((8 << 12) & RXDMA_BLANK_ITIME
)),
1817 gp
->regs
+ RXDMA_BLANK
);
1819 writel(((5 & RXDMA_BLANK_IPKTS
) |
1820 ((4 << 12) & RXDMA_BLANK_ITIME
)),
1821 gp
->regs
+ RXDMA_BLANK
);
1824 /* Must be invoked under gp->lock and gp->tx_lock. */
1825 static u32
gem_setup_multicast(struct gem
*gp
)
1830 if ((gp
->dev
->flags
& IFF_ALLMULTI
) ||
1831 (gp
->dev
->mc_count
> 256)) {
1832 for (i
=0; i
<16; i
++)
1833 writel(0xffff, gp
->regs
+ MAC_HASH0
+ (i
<< 2));
1834 rxcfg
|= MAC_RXCFG_HFE
;
1835 } else if (gp
->dev
->flags
& IFF_PROMISC
) {
1836 rxcfg
|= MAC_RXCFG_PROM
;
1840 struct dev_mc_list
*dmi
= gp
->dev
->mc_list
;
1843 for (i
= 0; i
< 16; i
++)
1846 for (i
= 0; i
< gp
->dev
->mc_count
; i
++) {
1847 char *addrs
= dmi
->dmi_addr
;
1854 crc
= ether_crc_le(6, addrs
);
1856 hash_table
[crc
>> 4] |= 1 << (15 - (crc
& 0xf));
1858 for (i
=0; i
<16; i
++)
1859 writel(hash_table
[i
], gp
->regs
+ MAC_HASH0
+ (i
<< 2));
1860 rxcfg
|= MAC_RXCFG_HFE
;
1866 /* Must be invoked under gp->lock and gp->tx_lock. */
1867 static void gem_init_mac(struct gem
*gp
)
1869 unsigned char *e
= &gp
->dev
->dev_addr
[0];
1871 writel(0x1bf0, gp
->regs
+ MAC_SNDPAUSE
);
1873 writel(0x00, gp
->regs
+ MAC_IPG0
);
1874 writel(0x08, gp
->regs
+ MAC_IPG1
);
1875 writel(0x04, gp
->regs
+ MAC_IPG2
);
1876 writel(0x40, gp
->regs
+ MAC_STIME
);
1877 writel(0x40, gp
->regs
+ MAC_MINFSZ
);
1879 /* Ethernet payload + header + FCS + optional VLAN tag. */
1880 writel(0x20000000 | (gp
->rx_buf_sz
+ 4), gp
->regs
+ MAC_MAXFSZ
);
1882 writel(0x07, gp
->regs
+ MAC_PASIZE
);
1883 writel(0x04, gp
->regs
+ MAC_JAMSIZE
);
1884 writel(0x10, gp
->regs
+ MAC_ATTLIM
);
1885 writel(0x8808, gp
->regs
+ MAC_MCTYPE
);
1887 writel((e
[5] | (e
[4] << 8)) & 0x3ff, gp
->regs
+ MAC_RANDSEED
);
1889 writel((e
[4] << 8) | e
[5], gp
->regs
+ MAC_ADDR0
);
1890 writel((e
[2] << 8) | e
[3], gp
->regs
+ MAC_ADDR1
);
1891 writel((e
[0] << 8) | e
[1], gp
->regs
+ MAC_ADDR2
);
1893 writel(0, gp
->regs
+ MAC_ADDR3
);
1894 writel(0, gp
->regs
+ MAC_ADDR4
);
1895 writel(0, gp
->regs
+ MAC_ADDR5
);
1897 writel(0x0001, gp
->regs
+ MAC_ADDR6
);
1898 writel(0xc200, gp
->regs
+ MAC_ADDR7
);
1899 writel(0x0180, gp
->regs
+ MAC_ADDR8
);
1901 writel(0, gp
->regs
+ MAC_AFILT0
);
1902 writel(0, gp
->regs
+ MAC_AFILT1
);
1903 writel(0, gp
->regs
+ MAC_AFILT2
);
1904 writel(0, gp
->regs
+ MAC_AF21MSK
);
1905 writel(0, gp
->regs
+ MAC_AF0MSK
);
1907 gp
->mac_rx_cfg
= gem_setup_multicast(gp
);
1909 gp
->mac_rx_cfg
|= MAC_RXCFG_SFCS
;
1911 writel(0, gp
->regs
+ MAC_NCOLL
);
1912 writel(0, gp
->regs
+ MAC_FASUCC
);
1913 writel(0, gp
->regs
+ MAC_ECOLL
);
1914 writel(0, gp
->regs
+ MAC_LCOLL
);
1915 writel(0, gp
->regs
+ MAC_DTIMER
);
1916 writel(0, gp
->regs
+ MAC_PATMPS
);
1917 writel(0, gp
->regs
+ MAC_RFCTR
);
1918 writel(0, gp
->regs
+ MAC_LERR
);
1919 writel(0, gp
->regs
+ MAC_AERR
);
1920 writel(0, gp
->regs
+ MAC_FCSERR
);
1921 writel(0, gp
->regs
+ MAC_RXCVERR
);
1923 /* Clear RX/TX/MAC/XIF config, we will set these up and enable
1924 * them once a link is established.
1926 writel(0, gp
->regs
+ MAC_TXCFG
);
1927 writel(gp
->mac_rx_cfg
, gp
->regs
+ MAC_RXCFG
);
1928 writel(0, gp
->regs
+ MAC_MCCFG
);
1929 writel(0, gp
->regs
+ MAC_XIFCFG
);
1931 /* Setup MAC interrupts. We want to get all of the interesting
1932 * counter expiration events, but we do not want to hear about
1933 * normal rx/tx as the DMA engine tells us that.
1935 writel(MAC_TXSTAT_XMIT
, gp
->regs
+ MAC_TXMASK
);
1936 writel(MAC_RXSTAT_RCV
, gp
->regs
+ MAC_RXMASK
);
1938 /* Don't enable even the PAUSE interrupts for now, we
1939 * make no use of those events other than to record them.
1941 writel(0xffffffff, gp
->regs
+ MAC_MCMASK
);
1943 /* Don't enable GEM's WOL in normal operations
1946 writel(0, gp
->regs
+ WOL_WAKECSR
);
1949 /* Must be invoked under gp->lock and gp->tx_lock. */
1950 static void gem_init_pause_thresholds(struct gem
*gp
)
1954 /* Calculate pause thresholds. Setting the OFF threshold to the
1955 * full RX fifo size effectively disables PAUSE generation which
1956 * is what we do for 10/100 only GEMs which have FIFOs too small
1957 * to make real gains from PAUSE.
1959 if (gp
->rx_fifo_sz
<= (2 * 1024)) {
1960 gp
->rx_pause_off
= gp
->rx_pause_on
= gp
->rx_fifo_sz
;
1962 int max_frame
= (gp
->rx_buf_sz
+ 4 + 64) & ~63;
1963 int off
= (gp
->rx_fifo_sz
- (max_frame
* 2));
1964 int on
= off
- max_frame
;
1966 gp
->rx_pause_off
= off
;
1967 gp
->rx_pause_on
= on
;
1971 /* Configure the chip "burst" DMA mode & enable some
1972 * HW bug fixes on Apple version
1975 if (gp
->pdev
->vendor
== PCI_VENDOR_ID_APPLE
)
1976 cfg
|= GREG_CFG_RONPAULBIT
| GREG_CFG_ENBUG2FIX
;
1977 #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
1978 cfg
|= GREG_CFG_IBURST
;
1980 cfg
|= ((31 << 1) & GREG_CFG_TXDMALIM
);
1981 cfg
|= ((31 << 6) & GREG_CFG_RXDMALIM
);
1982 writel(cfg
, gp
->regs
+ GREG_CFG
);
1984 /* If Infinite Burst didn't stick, then use different
1985 * thresholds (and Apple bug fixes don't exist)
1987 if (!(readl(gp
->regs
+ GREG_CFG
) & GREG_CFG_IBURST
)) {
1988 cfg
= ((2 << 1) & GREG_CFG_TXDMALIM
);
1989 cfg
|= ((8 << 6) & GREG_CFG_RXDMALIM
);
1990 writel(cfg
, gp
->regs
+ GREG_CFG
);
1994 static int gem_check_invariants(struct gem
*gp
)
1996 struct pci_dev
*pdev
= gp
->pdev
;
1999 /* On Apple's sungem, we can't rely on registers as the chip
2000 * was been powered down by the firmware. The PHY is looked
2003 if (pdev
->vendor
== PCI_VENDOR_ID_APPLE
) {
2004 gp
->phy_type
= phy_mii_mdio0
;
2005 gp
->tx_fifo_sz
= readl(gp
->regs
+ TXDMA_FSZ
) * 64;
2006 gp
->rx_fifo_sz
= readl(gp
->regs
+ RXDMA_FSZ
) * 64;
2009 mif_cfg
= readl(gp
->regs
+ MIF_CFG
);
2010 mif_cfg
&= ~(MIF_CFG_PSELECT
|MIF_CFG_POLL
|MIF_CFG_BBMODE
|MIF_CFG_MDI1
);
2011 mif_cfg
|= MIF_CFG_MDI0
;
2012 writel(mif_cfg
, gp
->regs
+ MIF_CFG
);
2013 writel(PCS_DMODE_MGM
, gp
->regs
+ PCS_DMODE
);
2014 writel(MAC_XIFCFG_OE
, gp
->regs
+ MAC_XIFCFG
);
2016 /* We hard-code the PHY address so we can properly bring it out of
2017 * reset later on, we can't really probe it at this point, though
2018 * that isn't an issue.
2020 if (gp
->pdev
->device
== PCI_DEVICE_ID_APPLE_K2_GMAC
)
2021 gp
->mii_phy_addr
= 1;
2023 gp
->mii_phy_addr
= 0;
2028 mif_cfg
= readl(gp
->regs
+ MIF_CFG
);
2030 if (pdev
->vendor
== PCI_VENDOR_ID_SUN
&&
2031 pdev
->device
== PCI_DEVICE_ID_SUN_RIO_GEM
) {
2032 /* One of the MII PHYs _must_ be present
2033 * as this chip has no gigabit PHY.
2035 if ((mif_cfg
& (MIF_CFG_MDI0
| MIF_CFG_MDI1
)) == 0) {
2036 printk(KERN_ERR PFX
"RIO GEM lacks MII phy, mif_cfg[%08x]\n",
2042 /* Determine initial PHY interface type guess. MDIO1 is the
2043 * external PHY and thus takes precedence over MDIO0.
2046 if (mif_cfg
& MIF_CFG_MDI1
) {
2047 gp
->phy_type
= phy_mii_mdio1
;
2048 mif_cfg
|= MIF_CFG_PSELECT
;
2049 writel(mif_cfg
, gp
->regs
+ MIF_CFG
);
2050 } else if (mif_cfg
& MIF_CFG_MDI0
) {
2051 gp
->phy_type
= phy_mii_mdio0
;
2052 mif_cfg
&= ~MIF_CFG_PSELECT
;
2053 writel(mif_cfg
, gp
->regs
+ MIF_CFG
);
2055 gp
->phy_type
= phy_serialink
;
2057 if (gp
->phy_type
== phy_mii_mdio1
||
2058 gp
->phy_type
== phy_mii_mdio0
) {
2061 for (i
= 0; i
< 32; i
++) {
2062 gp
->mii_phy_addr
= i
;
2063 if (phy_read(gp
, MII_BMCR
) != 0xffff)
2067 if (pdev
->device
!= PCI_DEVICE_ID_SUN_GEM
) {
2068 printk(KERN_ERR PFX
"RIO MII phy will not respond.\n");
2071 gp
->phy_type
= phy_serdes
;
2075 /* Fetch the FIFO configurations now too. */
2076 gp
->tx_fifo_sz
= readl(gp
->regs
+ TXDMA_FSZ
) * 64;
2077 gp
->rx_fifo_sz
= readl(gp
->regs
+ RXDMA_FSZ
) * 64;
2079 if (pdev
->vendor
== PCI_VENDOR_ID_SUN
) {
2080 if (pdev
->device
== PCI_DEVICE_ID_SUN_GEM
) {
2081 if (gp
->tx_fifo_sz
!= (9 * 1024) ||
2082 gp
->rx_fifo_sz
!= (20 * 1024)) {
2083 printk(KERN_ERR PFX
"GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2084 gp
->tx_fifo_sz
, gp
->rx_fifo_sz
);
2089 if (gp
->tx_fifo_sz
!= (2 * 1024) ||
2090 gp
->rx_fifo_sz
!= (2 * 1024)) {
2091 printk(KERN_ERR PFX
"RIO GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2092 gp
->tx_fifo_sz
, gp
->rx_fifo_sz
);
2095 gp
->swrst_base
= (64 / 4) << GREG_SWRST_CACHE_SHIFT
;
2102 /* Must be invoked under gp->lock and gp->tx_lock. */
2103 static void gem_reinit_chip(struct gem
*gp
)
2105 /* Reset the chip */
2108 /* Make sure ints are disabled */
2109 gem_disable_ints(gp
);
2111 /* Allocate & setup ring buffers */
2114 /* Configure pause thresholds */
2115 gem_init_pause_thresholds(gp
);
2117 /* Init DMA & MAC engines */
2123 /* Must be invoked with no lock held. */
2124 static void gem_stop_phy(struct gem
*gp
, int wol
)
2127 unsigned long flags
;
2129 /* Let the chip settle down a bit, it seems that helps
2130 * for sleep mode on some models
2134 /* Make sure we aren't polling PHY status change. We
2135 * don't currently use that feature though
2137 mif_cfg
= readl(gp
->regs
+ MIF_CFG
);
2138 mif_cfg
&= ~MIF_CFG_POLL
;
2139 writel(mif_cfg
, gp
->regs
+ MIF_CFG
);
2141 if (wol
&& gp
->has_wol
) {
2142 unsigned char *e
= &gp
->dev
->dev_addr
[0];
2145 /* Setup wake-on-lan for MAGIC packet */
2146 writel(MAC_RXCFG_HFE
| MAC_RXCFG_SFCS
| MAC_RXCFG_ENAB
,
2147 gp
->regs
+ MAC_RXCFG
);
2148 writel((e
[4] << 8) | e
[5], gp
->regs
+ WOL_MATCH0
);
2149 writel((e
[2] << 8) | e
[3], gp
->regs
+ WOL_MATCH1
);
2150 writel((e
[0] << 8) | e
[1], gp
->regs
+ WOL_MATCH2
);
2152 writel(WOL_MCOUNT_N
| WOL_MCOUNT_M
, gp
->regs
+ WOL_MCOUNT
);
2153 csr
= WOL_WAKECSR_ENABLE
;
2154 if ((readl(gp
->regs
+ MAC_XIFCFG
) & MAC_XIFCFG_GMII
) == 0)
2155 csr
|= WOL_WAKECSR_MII
;
2156 writel(csr
, gp
->regs
+ WOL_WAKECSR
);
2158 writel(0, gp
->regs
+ MAC_RXCFG
);
2159 (void)readl(gp
->regs
+ MAC_RXCFG
);
2160 /* Machine sleep will die in strange ways if we
2161 * dont wait a bit here, looks like the chip takes
2162 * some time to really shut down
2167 writel(0, gp
->regs
+ MAC_TXCFG
);
2168 writel(0, gp
->regs
+ MAC_XIFCFG
);
2169 writel(0, gp
->regs
+ TXDMA_CFG
);
2170 writel(0, gp
->regs
+ RXDMA_CFG
);
2173 spin_lock_irqsave(&gp
->lock
, flags
);
2174 spin_lock(&gp
->tx_lock
);
2176 writel(MAC_TXRST_CMD
, gp
->regs
+ MAC_TXRST
);
2177 writel(MAC_RXRST_CMD
, gp
->regs
+ MAC_RXRST
);
2178 spin_unlock(&gp
->tx_lock
);
2179 spin_unlock_irqrestore(&gp
->lock
, flags
);
2181 /* No need to take the lock here */
2183 if (found_mii_phy(gp
) && gp
->phy_mii
.def
->ops
->suspend
)
2184 gp
->phy_mii
.def
->ops
->suspend(&gp
->phy_mii
);
2186 /* According to Apple, we must set the MDIO pins to this begnign
2187 * state or we may 1) eat more current, 2) damage some PHYs
2190 writel(mif_cfg
| MIF_CFG_BBMODE
, gp
->regs
+ MIF_CFG
);
2191 writel(0, gp
->regs
+ MIF_BBCLK
);
2192 writel(0, gp
->regs
+ MIF_BBDATA
);
2193 writel(0, gp
->regs
+ MIF_BBOENAB
);
2194 writel(MAC_XIFCFG_GMII
| MAC_XIFCFG_LBCK
, gp
->regs
+ MAC_XIFCFG
);
2195 (void) readl(gp
->regs
+ MAC_XIFCFG
);
2200 static int gem_do_start(struct net_device
*dev
)
2202 struct gem
*gp
= dev
->priv
;
2203 unsigned long flags
;
2205 spin_lock_irqsave(&gp
->lock
, flags
);
2206 spin_lock(&gp
->tx_lock
);
2208 /* Enable the cell */
2211 /* Init & setup chip hardware */
2212 gem_reinit_chip(gp
);
2216 if (gp
->lstate
== link_up
) {
2217 netif_carrier_on(gp
->dev
);
2218 gem_set_link_modes(gp
);
2221 netif_wake_queue(gp
->dev
);
2223 spin_unlock(&gp
->tx_lock
);
2224 spin_unlock_irqrestore(&gp
->lock
, flags
);
2226 if (request_irq(gp
->pdev
->irq
, gem_interrupt
,
2227 SA_SHIRQ
, dev
->name
, (void *)dev
)) {
2228 printk(KERN_ERR
"%s: failed to request irq !\n", gp
->dev
->name
);
2230 spin_lock_irqsave(&gp
->lock
, flags
);
2231 spin_lock(&gp
->tx_lock
);
2235 gem_clean_rings(gp
);
2238 spin_unlock(&gp
->tx_lock
);
2239 spin_unlock_irqrestore(&gp
->lock
, flags
);
2247 static void gem_do_stop(struct net_device
*dev
, int wol
)
2249 struct gem
*gp
= dev
->priv
;
2250 unsigned long flags
;
2252 spin_lock_irqsave(&gp
->lock
, flags
);
2253 spin_lock(&gp
->tx_lock
);
2257 /* Stop netif queue */
2258 netif_stop_queue(dev
);
2260 /* Make sure ints are disabled */
2261 gem_disable_ints(gp
);
2263 /* We can drop the lock now */
2264 spin_unlock(&gp
->tx_lock
);
2265 spin_unlock_irqrestore(&gp
->lock
, flags
);
2267 /* If we are going to sleep with WOL */
2274 /* Get rid of rings */
2275 gem_clean_rings(gp
);
2277 /* No irq needed anymore */
2278 free_irq(gp
->pdev
->irq
, (void *) dev
);
2280 /* Cell not needed neither if no WOL */
2282 spin_lock_irqsave(&gp
->lock
, flags
);
2284 spin_unlock_irqrestore(&gp
->lock
, flags
);
2288 static void gem_reset_task(void *data
)
2290 struct gem
*gp
= (struct gem
*) data
;
2294 netif_poll_disable(gp
->dev
);
2296 spin_lock_irq(&gp
->lock
);
2297 spin_lock(&gp
->tx_lock
);
2299 if (gp
->running
== 0)
2303 netif_stop_queue(gp
->dev
);
2305 /* Reset the chip & rings */
2306 gem_reinit_chip(gp
);
2307 if (gp
->lstate
== link_up
)
2308 gem_set_link_modes(gp
);
2309 netif_wake_queue(gp
->dev
);
2312 gp
->reset_task_pending
= 0;
2314 spin_unlock(&gp
->tx_lock
);
2315 spin_unlock_irq(&gp
->lock
);
2317 netif_poll_enable(gp
->dev
);
2323 static int gem_open(struct net_device
*dev
)
2325 struct gem
*gp
= dev
->priv
;
2330 /* We need the cell enabled */
2332 rc
= gem_do_start(dev
);
2333 gp
->opened
= (rc
== 0);
2340 static int gem_close(struct net_device
*dev
)
2342 struct gem
*gp
= dev
->priv
;
2344 /* Note: we don't need to call netif_poll_disable() here because
2345 * our caller (dev_close) already did it for us
2352 gem_do_stop(dev
, 0);
2360 static int gem_suspend(struct pci_dev
*pdev
, pm_message_t state
)
2362 struct net_device
*dev
= pci_get_drvdata(pdev
);
2363 struct gem
*gp
= dev
->priv
;
2364 unsigned long flags
;
2368 netif_poll_disable(dev
);
2370 printk(KERN_INFO
"%s: suspending, WakeOnLan %s\n",
2372 (gp
->wake_on_lan
&& gp
->opened
) ? "enabled" : "disabled");
2374 /* Keep the cell enabled during the entire operation */
2375 spin_lock_irqsave(&gp
->lock
, flags
);
2376 spin_lock(&gp
->tx_lock
);
2378 spin_unlock(&gp
->tx_lock
);
2379 spin_unlock_irqrestore(&gp
->lock
, flags
);
2381 /* If the driver is opened, we stop the MAC */
2383 /* Stop traffic, mark us closed */
2384 netif_device_detach(dev
);
2386 /* Switch off MAC, remember WOL setting */
2387 gp
->asleep_wol
= gp
->wake_on_lan
;
2388 gem_do_stop(dev
, gp
->asleep_wol
);
2392 /* Mark us asleep */
2396 /* Stop the link timer */
2397 del_timer_sync(&gp
->link_timer
);
2399 /* Now we release the semaphore to not block the reset task who
2400 * can take it too. We are marked asleep, so there will be no
2405 /* Wait for a pending reset task to complete */
2406 while (gp
->reset_task_pending
)
2408 flush_scheduled_work();
2410 /* Shut the PHY down eventually and setup WOL */
2411 gem_stop_phy(gp
, gp
->asleep_wol
);
2413 /* Make sure bus master is disabled */
2414 pci_disable_device(gp
->pdev
);
2416 /* Release the cell, no need to take a lock at this point since
2417 * nothing else can happen now
2424 static int gem_resume(struct pci_dev
*pdev
)
2426 struct net_device
*dev
= pci_get_drvdata(pdev
);
2427 struct gem
*gp
= dev
->priv
;
2428 unsigned long flags
;
2430 printk(KERN_INFO
"%s: resuming\n", dev
->name
);
2434 /* Keep the cell enabled during the entire operation, no need to
2435 * take a lock here tho since nothing else can happen while we are
2440 /* Make sure PCI access and bus master are enabled */
2441 if (pci_enable_device(gp
->pdev
)) {
2442 printk(KERN_ERR
"%s: Can't re-enable chip !\n",
2444 /* Put cell and forget it for now, it will be considered as
2445 * still asleep, a new sleep cycle may bring it back
2451 pci_set_master(gp
->pdev
);
2453 /* Reset everything */
2456 /* Mark us woken up */
2460 /* Bring the PHY back. Again, lock is useless at this point as
2461 * nothing can be happening until we restart the whole thing
2465 /* If we were opened, bring everything back */
2470 /* Re-attach net device */
2471 netif_device_attach(dev
);
2475 spin_lock_irqsave(&gp
->lock
, flags
);
2476 spin_lock(&gp
->tx_lock
);
2478 /* If we had WOL enabled, the cell clock was never turned off during
2479 * sleep, so we end up beeing unbalanced. Fix that here
2484 /* This function doesn't need to hold the cell, it will be held if the
2485 * driver is open by gem_do_start().
2489 spin_unlock(&gp
->tx_lock
);
2490 spin_unlock_irqrestore(&gp
->lock
, flags
);
2492 netif_poll_enable(dev
);
2498 #endif /* CONFIG_PM */
2500 static struct net_device_stats
*gem_get_stats(struct net_device
*dev
)
2502 struct gem
*gp
= dev
->priv
;
2503 struct net_device_stats
*stats
= &gp
->net_stats
;
2505 spin_lock_irq(&gp
->lock
);
2506 spin_lock(&gp
->tx_lock
);
2508 /* I have seen this being called while the PM was in progress,
2509 * so we shield against this
2512 stats
->rx_crc_errors
+= readl(gp
->regs
+ MAC_FCSERR
);
2513 writel(0, gp
->regs
+ MAC_FCSERR
);
2515 stats
->rx_frame_errors
+= readl(gp
->regs
+ MAC_AERR
);
2516 writel(0, gp
->regs
+ MAC_AERR
);
2518 stats
->rx_length_errors
+= readl(gp
->regs
+ MAC_LERR
);
2519 writel(0, gp
->regs
+ MAC_LERR
);
2521 stats
->tx_aborted_errors
+= readl(gp
->regs
+ MAC_ECOLL
);
2522 stats
->collisions
+=
2523 (readl(gp
->regs
+ MAC_ECOLL
) +
2524 readl(gp
->regs
+ MAC_LCOLL
));
2525 writel(0, gp
->regs
+ MAC_ECOLL
);
2526 writel(0, gp
->regs
+ MAC_LCOLL
);
2529 spin_unlock(&gp
->tx_lock
);
2530 spin_unlock_irq(&gp
->lock
);
2532 return &gp
->net_stats
;
2535 static void gem_set_multicast(struct net_device
*dev
)
2537 struct gem
*gp
= dev
->priv
;
2538 u32 rxcfg
, rxcfg_new
;
2542 spin_lock_irq(&gp
->lock
);
2543 spin_lock(&gp
->tx_lock
);
2548 netif_stop_queue(dev
);
2550 rxcfg
= readl(gp
->regs
+ MAC_RXCFG
);
2551 rxcfg_new
= gem_setup_multicast(gp
);
2553 rxcfg_new
|= MAC_RXCFG_SFCS
;
2555 gp
->mac_rx_cfg
= rxcfg_new
;
2557 writel(rxcfg
& ~MAC_RXCFG_ENAB
, gp
->regs
+ MAC_RXCFG
);
2558 while (readl(gp
->regs
+ MAC_RXCFG
) & MAC_RXCFG_ENAB
) {
2564 rxcfg
&= ~(MAC_RXCFG_PROM
| MAC_RXCFG_HFE
);
2567 writel(rxcfg
, gp
->regs
+ MAC_RXCFG
);
2569 netif_wake_queue(dev
);
2572 spin_unlock(&gp
->tx_lock
);
2573 spin_unlock_irq(&gp
->lock
);
2576 /* Jumbo-grams don't seem to work :-( */
2577 #define GEM_MIN_MTU 68
2579 #define GEM_MAX_MTU 1500
2581 #define GEM_MAX_MTU 9000
2584 static int gem_change_mtu(struct net_device
*dev
, int new_mtu
)
2586 struct gem
*gp
= dev
->priv
;
2588 if (new_mtu
< GEM_MIN_MTU
|| new_mtu
> GEM_MAX_MTU
)
2591 if (!netif_running(dev
) || !netif_device_present(dev
)) {
2592 /* We'll just catch it later when the
2593 * device is up'd or resumed.
2600 spin_lock_irq(&gp
->lock
);
2601 spin_lock(&gp
->tx_lock
);
2604 gem_reinit_chip(gp
);
2605 if (gp
->lstate
== link_up
)
2606 gem_set_link_modes(gp
);
2608 spin_unlock(&gp
->tx_lock
);
2609 spin_unlock_irq(&gp
->lock
);
2615 static void gem_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
2617 struct gem
*gp
= dev
->priv
;
2619 strcpy(info
->driver
, DRV_NAME
);
2620 strcpy(info
->version
, DRV_VERSION
);
2621 strcpy(info
->bus_info
, pci_name(gp
->pdev
));
2624 static int gem_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
2626 struct gem
*gp
= dev
->priv
;
2628 if (gp
->phy_type
== phy_mii_mdio0
||
2629 gp
->phy_type
== phy_mii_mdio1
) {
2630 if (gp
->phy_mii
.def
)
2631 cmd
->supported
= gp
->phy_mii
.def
->features
;
2633 cmd
->supported
= (SUPPORTED_10baseT_Half
|
2634 SUPPORTED_10baseT_Full
);
2636 /* XXX hardcoded stuff for now */
2637 cmd
->port
= PORT_MII
;
2638 cmd
->transceiver
= XCVR_EXTERNAL
;
2639 cmd
->phy_address
= 0; /* XXX fixed PHYAD */
2641 /* Return current PHY settings */
2642 spin_lock_irq(&gp
->lock
);
2643 cmd
->autoneg
= gp
->want_autoneg
;
2644 cmd
->speed
= gp
->phy_mii
.speed
;
2645 cmd
->duplex
= gp
->phy_mii
.duplex
;
2646 cmd
->advertising
= gp
->phy_mii
.advertising
;
2648 /* If we started with a forced mode, we don't have a default
2649 * advertise set, we need to return something sensible so
2650 * userland can re-enable autoneg properly.
2652 if (cmd
->advertising
== 0)
2653 cmd
->advertising
= cmd
->supported
;
2654 spin_unlock_irq(&gp
->lock
);
2655 } else { // XXX PCS ?
2657 (SUPPORTED_10baseT_Half
| SUPPORTED_10baseT_Full
|
2658 SUPPORTED_100baseT_Half
| SUPPORTED_100baseT_Full
|
2660 cmd
->advertising
= cmd
->supported
;
2662 cmd
->duplex
= cmd
->port
= cmd
->phy_address
=
2663 cmd
->transceiver
= cmd
->autoneg
= 0;
2665 cmd
->maxtxpkt
= cmd
->maxrxpkt
= 0;
2670 static int gem_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
2672 struct gem
*gp
= dev
->priv
;
2674 /* Verify the settings we care about. */
2675 if (cmd
->autoneg
!= AUTONEG_ENABLE
&&
2676 cmd
->autoneg
!= AUTONEG_DISABLE
)
2679 if (cmd
->autoneg
== AUTONEG_ENABLE
&&
2680 cmd
->advertising
== 0)
2683 if (cmd
->autoneg
== AUTONEG_DISABLE
&&
2684 ((cmd
->speed
!= SPEED_1000
&&
2685 cmd
->speed
!= SPEED_100
&&
2686 cmd
->speed
!= SPEED_10
) ||
2687 (cmd
->duplex
!= DUPLEX_HALF
&&
2688 cmd
->duplex
!= DUPLEX_FULL
)))
2691 /* Apply settings and restart link process. */
2692 spin_lock_irq(&gp
->lock
);
2694 gem_begin_auto_negotiation(gp
, cmd
);
2696 spin_unlock_irq(&gp
->lock
);
2701 static int gem_nway_reset(struct net_device
*dev
)
2703 struct gem
*gp
= dev
->priv
;
2705 if (!gp
->want_autoneg
)
2708 /* Restart link process. */
2709 spin_lock_irq(&gp
->lock
);
2711 gem_begin_auto_negotiation(gp
, NULL
);
2713 spin_unlock_irq(&gp
->lock
);
2718 static u32
gem_get_msglevel(struct net_device
*dev
)
2720 struct gem
*gp
= dev
->priv
;
2721 return gp
->msg_enable
;
2724 static void gem_set_msglevel(struct net_device
*dev
, u32 value
)
2726 struct gem
*gp
= dev
->priv
;
2727 gp
->msg_enable
= value
;
2731 /* Add more when I understand how to program the chip */
2732 /* like WAKE_UCAST | WAKE_MCAST | WAKE_BCAST */
2734 #define WOL_SUPPORTED_MASK (WAKE_MAGIC)
2736 static void gem_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2738 struct gem
*gp
= dev
->priv
;
2740 /* Add more when I understand how to program the chip */
2742 wol
->supported
= WOL_SUPPORTED_MASK
;
2743 wol
->wolopts
= gp
->wake_on_lan
;
2750 static int gem_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2752 struct gem
*gp
= dev
->priv
;
2756 gp
->wake_on_lan
= wol
->wolopts
& WOL_SUPPORTED_MASK
;
2760 static struct ethtool_ops gem_ethtool_ops
= {
2761 .get_drvinfo
= gem_get_drvinfo
,
2762 .get_link
= ethtool_op_get_link
,
2763 .get_settings
= gem_get_settings
,
2764 .set_settings
= gem_set_settings
,
2765 .nway_reset
= gem_nway_reset
,
2766 .get_msglevel
= gem_get_msglevel
,
2767 .set_msglevel
= gem_set_msglevel
,
2768 .get_wol
= gem_get_wol
,
2769 .set_wol
= gem_set_wol
,
2772 static int gem_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
2774 struct gem
*gp
= dev
->priv
;
2775 struct mii_ioctl_data
*data
= if_mii(ifr
);
2776 int rc
= -EOPNOTSUPP
;
2777 unsigned long flags
;
2779 /* Hold the PM semaphore while doing ioctl's or we may collide
2780 * with power management.
2784 spin_lock_irqsave(&gp
->lock
, flags
);
2786 spin_unlock_irqrestore(&gp
->lock
, flags
);
2789 case SIOCGMIIPHY
: /* Get address of MII PHY in use. */
2790 data
->phy_id
= gp
->mii_phy_addr
;
2791 /* Fallthrough... */
2793 case SIOCGMIIREG
: /* Read MII PHY register. */
2797 data
->val_out
= __phy_read(gp
, data
->phy_id
& 0x1f,
2798 data
->reg_num
& 0x1f);
2803 case SIOCSMIIREG
: /* Write MII PHY register. */
2804 if (!capable(CAP_NET_ADMIN
))
2806 else if (!gp
->running
)
2809 __phy_write(gp
, data
->phy_id
& 0x1f, data
->reg_num
& 0x1f,
2816 spin_lock_irqsave(&gp
->lock
, flags
);
2818 spin_unlock_irqrestore(&gp
->lock
, flags
);
2825 #if (!defined(__sparc__) && !defined(CONFIG_PPC_PMAC))
2826 /* Fetch MAC address from vital product data of PCI ROM. */
2827 static int find_eth_addr_in_vpd(void __iomem
*rom_base
, int len
, unsigned char *dev_addr
)
2831 for (this_offset
= 0x20; this_offset
< len
; this_offset
++) {
2832 void __iomem
*p
= rom_base
+ this_offset
;
2835 if (readb(p
+ 0) != 0x90 ||
2836 readb(p
+ 1) != 0x00 ||
2837 readb(p
+ 2) != 0x09 ||
2838 readb(p
+ 3) != 0x4e ||
2839 readb(p
+ 4) != 0x41 ||
2840 readb(p
+ 5) != 0x06)
2846 for (i
= 0; i
< 6; i
++)
2847 dev_addr
[i
] = readb(p
+ i
);
2853 static void get_gem_mac_nonobp(struct pci_dev
*pdev
, unsigned char *dev_addr
)
2856 void __iomem
*p
= pci_map_rom(pdev
, &size
);
2861 found
= readb(p
) == 0x55 &&
2862 readb(p
+ 1) == 0xaa &&
2863 find_eth_addr_in_vpd(p
, (64 * 1024), dev_addr
);
2864 pci_unmap_rom(pdev
, p
);
2869 /* Sun MAC prefix then 3 random bytes. */
2873 get_random_bytes(dev_addr
+ 3, 3);
2876 #endif /* not Sparc and not PPC */
2878 static int __devinit
gem_get_device_address(struct gem
*gp
)
2880 #if defined(__sparc__) || defined(CONFIG_PPC_PMAC)
2881 struct net_device
*dev
= gp
->dev
;
2884 #if defined(__sparc__)
2885 struct pci_dev
*pdev
= gp
->pdev
;
2886 struct pcidev_cookie
*pcp
= pdev
->sysdata
;
2890 node
= pcp
->prom_node
;
2891 if (prom_getproplen(node
, "local-mac-address") == 6)
2892 prom_getproperty(node
, "local-mac-address",
2898 memcpy(dev
->dev_addr
, idprom
->id_ethaddr
, 6);
2899 #elif defined(CONFIG_PPC_PMAC)
2900 unsigned char *addr
;
2902 addr
= get_property(gp
->of_node
, "local-mac-address", NULL
);
2905 printk(KERN_ERR
"%s: can't get mac-address\n", dev
->name
);
2908 memcpy(dev
->dev_addr
, addr
, 6);
2910 get_gem_mac_nonobp(gp
->pdev
, gp
->dev
->dev_addr
);
2915 static void gem_remove_one(struct pci_dev
*pdev
)
2917 struct net_device
*dev
= pci_get_drvdata(pdev
);
2920 struct gem
*gp
= dev
->priv
;
2922 unregister_netdev(dev
);
2924 /* Stop the link timer */
2925 del_timer_sync(&gp
->link_timer
);
2927 /* We shouldn't need any locking here */
2930 /* Wait for a pending reset task to complete */
2931 while (gp
->reset_task_pending
)
2933 flush_scheduled_work();
2935 /* Shut the PHY down */
2936 gem_stop_phy(gp
, 0);
2940 /* Make sure bus master is disabled */
2941 pci_disable_device(gp
->pdev
);
2943 /* Free resources */
2944 pci_free_consistent(pdev
,
2945 sizeof(struct gem_init_block
),
2949 pci_release_regions(pdev
);
2952 pci_set_drvdata(pdev
, NULL
);
2956 static int __devinit
gem_init_one(struct pci_dev
*pdev
,
2957 const struct pci_device_id
*ent
)
2959 static int gem_version_printed
= 0;
2960 unsigned long gemreg_base
, gemreg_len
;
2961 struct net_device
*dev
;
2963 int i
, err
, pci_using_dac
;
2965 if (gem_version_printed
++ == 0)
2966 printk(KERN_INFO
"%s", version
);
2968 /* Apple gmac note: during probe, the chip is powered up by
2969 * the arch code to allow the code below to work (and to let
2970 * the chip be probed on the config space. It won't stay powered
2971 * up until the interface is brought up however, so we can't rely
2972 * on register configuration done at this point.
2974 err
= pci_enable_device(pdev
);
2976 printk(KERN_ERR PFX
"Cannot enable MMIO operation, "
2980 pci_set_master(pdev
);
2982 /* Configure DMA attributes. */
2984 /* All of the GEM documentation states that 64-bit DMA addressing
2985 * is fully supported and should work just fine. However the
2986 * front end for RIO based GEMs is different and only supports
2987 * 32-bit addressing.
2989 * For now we assume the various PPC GEMs are 32-bit only as well.
2991 if (pdev
->vendor
== PCI_VENDOR_ID_SUN
&&
2992 pdev
->device
== PCI_DEVICE_ID_SUN_GEM
&&
2993 !pci_set_dma_mask(pdev
, DMA_64BIT_MASK
)) {
2996 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
2998 printk(KERN_ERR PFX
"No usable DMA configuration, "
3000 goto err_disable_device
;
3005 gemreg_base
= pci_resource_start(pdev
, 0);
3006 gemreg_len
= pci_resource_len(pdev
, 0);
3008 if ((pci_resource_flags(pdev
, 0) & IORESOURCE_IO
) != 0) {
3009 printk(KERN_ERR PFX
"Cannot find proper PCI device "
3010 "base address, aborting.\n");
3012 goto err_disable_device
;
3015 dev
= alloc_etherdev(sizeof(*gp
));
3017 printk(KERN_ERR PFX
"Etherdev alloc failed, aborting.\n");
3019 goto err_disable_device
;
3021 SET_MODULE_OWNER(dev
);
3022 SET_NETDEV_DEV(dev
, &pdev
->dev
);
3026 err
= pci_request_regions(pdev
, DRV_NAME
);
3028 printk(KERN_ERR PFX
"Cannot obtain PCI resources, "
3030 goto err_out_free_netdev
;
3034 dev
->base_addr
= (long) pdev
;
3037 gp
->msg_enable
= DEFAULT_MSG
;
3039 spin_lock_init(&gp
->lock
);
3040 spin_lock_init(&gp
->tx_lock
);
3041 init_MUTEX(&gp
->pm_sem
);
3043 init_timer(&gp
->link_timer
);
3044 gp
->link_timer
.function
= gem_link_timer
;
3045 gp
->link_timer
.data
= (unsigned long) gp
;
3047 INIT_WORK(&gp
->reset_task
, gem_reset_task
, gp
);
3049 gp
->lstate
= link_down
;
3050 gp
->timer_ticks
= 0;
3051 netif_carrier_off(dev
);
3053 gp
->regs
= ioremap(gemreg_base
, gemreg_len
);
3054 if (gp
->regs
== 0UL) {
3055 printk(KERN_ERR PFX
"Cannot map device registers, "
3058 goto err_out_free_res
;
3061 /* On Apple, we want a reference to the Open Firmware device-tree
3062 * node. We use it for clock control.
3064 #ifdef CONFIG_PPC_PMAC
3065 gp
->of_node
= pci_device_to_OF_node(pdev
);
3068 /* Only Apple version supports WOL afaik */
3069 if (pdev
->vendor
== PCI_VENDOR_ID_APPLE
)
3072 /* Make sure cell is enabled */
3075 /* Make sure everything is stopped and in init state */
3078 /* Fill up the mii_phy structure (even if we won't use it) */
3079 gp
->phy_mii
.dev
= dev
;
3080 gp
->phy_mii
.mdio_read
= _phy_read
;
3081 gp
->phy_mii
.mdio_write
= _phy_write
;
3082 #ifdef CONFIG_PPC_PMAC
3083 gp
->phy_mii
.platform_data
= gp
->of_node
;
3085 /* By default, we start with autoneg */
3086 gp
->want_autoneg
= 1;
3088 /* Check fifo sizes, PHY type, etc... */
3089 if (gem_check_invariants(gp
)) {
3091 goto err_out_iounmap
;
3094 /* It is guaranteed that the returned buffer will be at least
3095 * PAGE_SIZE aligned.
3097 gp
->init_block
= (struct gem_init_block
*)
3098 pci_alloc_consistent(pdev
, sizeof(struct gem_init_block
),
3100 if (!gp
->init_block
) {
3101 printk(KERN_ERR PFX
"Cannot allocate init block, "
3104 goto err_out_iounmap
;
3107 if (gem_get_device_address(gp
))
3108 goto err_out_free_consistent
;
3110 dev
->open
= gem_open
;
3111 dev
->stop
= gem_close
;
3112 dev
->hard_start_xmit
= gem_start_xmit
;
3113 dev
->get_stats
= gem_get_stats
;
3114 dev
->set_multicast_list
= gem_set_multicast
;
3115 dev
->do_ioctl
= gem_ioctl
;
3116 dev
->poll
= gem_poll
;
3118 dev
->ethtool_ops
= &gem_ethtool_ops
;
3119 dev
->tx_timeout
= gem_tx_timeout
;
3120 dev
->watchdog_timeo
= 5 * HZ
;
3121 dev
->change_mtu
= gem_change_mtu
;
3122 dev
->irq
= pdev
->irq
;
3124 #ifdef CONFIG_NET_POLL_CONTROLLER
3125 dev
->poll_controller
= gem_poll_controller
;
3128 /* Set that now, in case PM kicks in now */
3129 pci_set_drvdata(pdev
, dev
);
3131 /* Detect & init PHY, start autoneg, we release the cell now
3132 * too, it will be managed by whoever needs it
3136 spin_lock_irq(&gp
->lock
);
3138 spin_unlock_irq(&gp
->lock
);
3140 /* Register with kernel */
3141 if (register_netdev(dev
)) {
3142 printk(KERN_ERR PFX
"Cannot register net device, "
3145 goto err_out_free_consistent
;
3148 printk(KERN_INFO
"%s: Sun GEM (PCI) 10/100/1000BaseT Ethernet ",
3150 for (i
= 0; i
< 6; i
++)
3151 printk("%2.2x%c", dev
->dev_addr
[i
],
3152 i
== 5 ? ' ' : ':');
3155 if (gp
->phy_type
== phy_mii_mdio0
||
3156 gp
->phy_type
== phy_mii_mdio1
)
3157 printk(KERN_INFO
"%s: Found %s PHY\n", dev
->name
,
3158 gp
->phy_mii
.def
? gp
->phy_mii
.def
->name
: "no");
3160 /* GEM can do it all... */
3161 dev
->features
|= NETIF_F_SG
| NETIF_F_HW_CSUM
| NETIF_F_LLTX
;
3163 dev
->features
|= NETIF_F_HIGHDMA
;
3167 err_out_free_consistent
:
3168 gem_remove_one(pdev
);
3174 pci_release_regions(pdev
);
3176 err_out_free_netdev
:
3179 pci_disable_device(pdev
);
3185 static struct pci_driver gem_driver
= {
3186 .name
= GEM_MODULE_NAME
,
3187 .id_table
= gem_pci_tbl
,
3188 .probe
= gem_init_one
,
3189 .remove
= gem_remove_one
,
3191 .suspend
= gem_suspend
,
3192 .resume
= gem_resume
,
3193 #endif /* CONFIG_PM */
3196 static int __init
gem_init(void)
3198 return pci_module_init(&gem_driver
);
3201 static void __exit
gem_cleanup(void)
3203 pci_unregister_driver(&gem_driver
);
3206 module_init(gem_init
);
3207 module_exit(gem_cleanup
);