2 * Tehuti Networks(R) Network Driver
3 * ethtool interface implementation
4 * Copyright (C) 2007 Tehuti Networks Ltd. All rights reserved
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
13 * RX HW/SW interaction overview
14 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
15 * There are 2 types of RX communication channels betwean driver and NIC.
16 * 1) RX Free Fifo - RXF - holds descriptors of empty buffers to accept incoming
17 * traffic. This Fifo is filled by SW and is readen by HW. Each descriptor holds
18 * info about buffer's location, size and ID. An ID field is used to identify a
19 * buffer when it's returned with data via RXD Fifo (see below)
20 * 2) RX Data Fifo - RXD - holds descriptors of full buffers. This Fifo is
21 * filled by HW and is readen by SW. Each descriptor holds status and ID.
22 * HW pops descriptor from RXF Fifo, stores ID, fills buffer with incoming data,
23 * via dma moves it into host memory, builds new RXD descriptor with same ID,
24 * pushes it into RXD Fifo and raises interrupt to indicate new RX data.
26 * Current NIC configuration (registers + firmware) makes NIC use 2 RXF Fifos.
27 * One holds 1.5K packets and another - 26K packets. Depending on incoming
28 * packet size, HW desides on a RXF Fifo to pop buffer from. When packet is
29 * filled with data, HW builds new RXD descriptor for it and push it into single
32 * RX SW Data Structures
33 * ~~~~~~~~~~~~~~~~~~~~~
34 * skb db - used to keep track of all skbs owned by SW and their dma addresses.
35 * For RX case, ownership lasts from allocating new empty skb for RXF until
36 * accepting full skb from RXD and passing it to OS. Each RXF Fifo has its own
37 * skb db. Implemented as array with bitmask.
38 * fifo - keeps info about fifo's size and location, relevant HW registers,
39 * usage and skb db. Each RXD and RXF Fifo has its own fifo structure.
40 * Implemented as simple struct.
42 * RX SW Execution Flow
43 * ~~~~~~~~~~~~~~~~~~~~
44 * Upon initialization (ifconfig up) driver creates RX fifos and initializes
45 * relevant registers. At the end of init phase, driver enables interrupts.
46 * NIC sees that there is no RXF buffers and raises
47 * RD_INTR interrupt, isr fills skbs and Rx begins.
48 * Driver has two receive operation modes:
49 * NAPI - interrupt-driven mixed with polling
50 * interrupt-driven only
52 * Interrupt-driven only flow is following. When buffer is ready, HW raises
53 * interrupt and isr is called. isr collects all available packets
54 * (bdx_rx_receive), refills skbs (bdx_rx_alloc_skbs) and exit.
56 * Rx buffer allocation note
57 * ~~~~~~~~~~~~~~~~~~~~~~~~~
58 * Driver cares to feed such amount of RxF descriptors that respective amount of
59 * RxD descriptors can not fill entire RxD fifo. The main reason is lack of
60 * overflow check in Bordeaux for RxD fifo free/used size.
61 * FIXME: this is NOT fully implemented, more work should be done
67 static DEFINE_PCI_DEVICE_TABLE(bdx_pci_tbl
) = {
68 {0x1FC9, 0x3009, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
69 {0x1FC9, 0x3010, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
70 {0x1FC9, 0x3014, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
74 MODULE_DEVICE_TABLE(pci
, bdx_pci_tbl
);
76 /* Definitions needed by ISR or NAPI functions */
77 static void bdx_rx_alloc_skbs(struct bdx_priv
*priv
, struct rxf_fifo
*f
);
78 static void bdx_tx_cleanup(struct bdx_priv
*priv
);
79 static int bdx_rx_receive(struct bdx_priv
*priv
, struct rxd_fifo
*f
, int budget
);
81 /* Definitions needed by FW loading */
82 static void bdx_tx_push_desc_safe(struct bdx_priv
*priv
, void *data
, int size
);
84 /* Definitions needed by hw_start */
85 static int bdx_tx_init(struct bdx_priv
*priv
);
86 static int bdx_rx_init(struct bdx_priv
*priv
);
88 /* Definitions needed by bdx_close */
89 static void bdx_rx_free(struct bdx_priv
*priv
);
90 static void bdx_tx_free(struct bdx_priv
*priv
);
92 /* Definitions needed by bdx_probe */
93 static void bdx_ethtool_ops(struct net_device
*netdev
);
95 /*************************************************************************
97 *************************************************************************/
99 static void print_hw_id(struct pci_dev
*pdev
)
101 struct pci_nic
*nic
= pci_get_drvdata(pdev
);
102 u16 pci_link_status
= 0;
105 pci_read_config_word(pdev
, PCI_LINK_STATUS_REG
, &pci_link_status
);
106 pci_read_config_word(pdev
, PCI_DEV_CTRL_REG
, &pci_ctrl
);
108 printk(KERN_INFO
"tehuti: %s%s\n", BDX_NIC_NAME
,
109 nic
->port_num
== 1 ? "" : ", 2-Port");
111 "tehuti: srom 0x%x fpga %d build %u lane# %d"
112 " max_pl 0x%x mrrs 0x%x\n",
113 readl(nic
->regs
+ SROM_VER
), readl(nic
->regs
+ FPGA_VER
) & 0xFFF,
114 readl(nic
->regs
+ FPGA_SEED
),
115 GET_LINK_STATUS_LANES(pci_link_status
),
116 GET_DEV_CTRL_MAXPL(pci_ctrl
), GET_DEV_CTRL_MRRS(pci_ctrl
));
119 static void print_fw_id(struct pci_nic
*nic
)
121 printk(KERN_INFO
"tehuti: fw 0x%x\n", readl(nic
->regs
+ FW_VER
));
124 static void print_eth_id(struct net_device
*ndev
)
126 printk(KERN_INFO
"%s: %s, Port %c\n", ndev
->name
, BDX_NIC_NAME
,
127 (ndev
->if_port
== 0) ? 'A' : 'B');
131 /*************************************************************************
133 *************************************************************************/
135 #define bdx_enable_interrupts(priv) \
136 do { WRITE_REG(priv, regIMR, IR_RUN); } while (0)
137 #define bdx_disable_interrupts(priv) \
138 do { WRITE_REG(priv, regIMR, 0); } while (0)
141 * create TX/RX descriptor fifo for host-NIC communication.
142 * 1K extra space is allocated at the end of the fifo to simplify
143 * processing of descriptors that wraps around fifo's end
144 * @priv - NIC private structure
145 * @f - fifo to initialize
146 * @fsz_type - fifo size type: 0-4KB, 1-8KB, 2-16KB, 3-32KB
147 * @reg_XXX - offsets of registers relative to base address
149 * Returns 0 on success, negative value on failure
153 bdx_fifo_init(struct bdx_priv
*priv
, struct fifo
*f
, int fsz_type
,
154 u16 reg_CFG0
, u16 reg_CFG1
, u16 reg_RPTR
, u16 reg_WPTR
)
156 u16 memsz
= FIFO_SIZE
* (1 << fsz_type
);
158 memset(f
, 0, sizeof(struct fifo
));
159 /* pci_alloc_consistent gives us 4k-aligned memory */
160 f
->va
= pci_alloc_consistent(priv
->pdev
,
161 memsz
+ FIFO_EXTRA_SPACE
, &f
->da
);
163 ERR("pci_alloc_consistent failed\n");
166 f
->reg_CFG0
= reg_CFG0
;
167 f
->reg_CFG1
= reg_CFG1
;
168 f
->reg_RPTR
= reg_RPTR
;
169 f
->reg_WPTR
= reg_WPTR
;
173 f
->size_mask
= memsz
- 1;
174 WRITE_REG(priv
, reg_CFG0
, (u32
) ((f
->da
& TX_RX_CFG0_BASE
) | fsz_type
));
175 WRITE_REG(priv
, reg_CFG1
, H32_64(f
->da
));
180 /* bdx_fifo_free - free all resources used by fifo
181 * @priv - NIC private structure
182 * @f - fifo to release
184 static void bdx_fifo_free(struct bdx_priv
*priv
, struct fifo
*f
)
188 pci_free_consistent(priv
->pdev
,
189 f
->memsz
+ FIFO_EXTRA_SPACE
, f
->va
, f
->da
);
196 * bdx_link_changed - notifies OS about hw link state.
197 * @bdx_priv - hw adapter structure
199 static void bdx_link_changed(struct bdx_priv
*priv
)
201 u32 link
= READ_REG(priv
, regMAC_LNK_STAT
) & MAC_LINK_STAT
;
204 if (netif_carrier_ok(priv
->ndev
)) {
205 netif_stop_queue(priv
->ndev
);
206 netif_carrier_off(priv
->ndev
);
207 ERR("%s: Link Down\n", priv
->ndev
->name
);
210 if (!netif_carrier_ok(priv
->ndev
)) {
211 netif_wake_queue(priv
->ndev
);
212 netif_carrier_on(priv
->ndev
);
213 ERR("%s: Link Up\n", priv
->ndev
->name
);
218 static void bdx_isr_extra(struct bdx_priv
*priv
, u32 isr
)
220 if (isr
& IR_RX_FREE_0
) {
221 bdx_rx_alloc_skbs(priv
, &priv
->rxf_fifo0
);
225 if (isr
& IR_LNKCHG0
)
226 bdx_link_changed(priv
);
228 if (isr
& IR_PCIE_LINK
)
229 ERR("%s: PCI-E Link Fault\n", priv
->ndev
->name
);
231 if (isr
& IR_PCIE_TOUT
)
232 ERR("%s: PCI-E Time Out\n", priv
->ndev
->name
);
236 /* bdx_isr - Interrupt Service Routine for Bordeaux NIC
237 * @irq - interrupt number
238 * @ndev - network device
239 * @regs - CPU registers
241 * Return IRQ_NONE if it was not our interrupt, IRQ_HANDLED - otherwise
243 * It reads ISR register to know interrupt reasons, and proceed them one by one.
244 * Reasons of interest are:
245 * RX_DESC - new packet has arrived and RXD fifo holds its descriptor
246 * RX_FREE - number of free Rx buffers in RXF fifo gets low
247 * TX_FREE - packet was transmited and RXF fifo holds its descriptor
250 static irqreturn_t
bdx_isr_napi(int irq
, void *dev
)
252 struct net_device
*ndev
= dev
;
253 struct bdx_priv
*priv
= netdev_priv(ndev
);
257 isr
= (READ_REG(priv
, regISR
) & IR_RUN
);
258 if (unlikely(!isr
)) {
259 bdx_enable_interrupts(priv
);
260 return IRQ_NONE
; /* Not our interrupt */
264 bdx_isr_extra(priv
, isr
);
266 if (isr
& (IR_RX_DESC_0
| IR_TX_FREE_0
)) {
267 if (likely(napi_schedule_prep(&priv
->napi
))) {
268 __napi_schedule(&priv
->napi
);
271 /* NOTE: we get here if intr has slipped into window
272 * between these lines in bdx_poll:
273 * bdx_enable_interrupts(priv);
275 * currently intrs are disabled (since we read ISR),
276 * and we have failed to register next poll.
277 * so we read the regs to trigger chip
278 * and allow further interupts. */
279 READ_REG(priv
, regTXF_WPTR_0
);
280 READ_REG(priv
, regRXD_WPTR_0
);
284 bdx_enable_interrupts(priv
);
288 static int bdx_poll(struct napi_struct
*napi
, int budget
)
290 struct bdx_priv
*priv
= container_of(napi
, struct bdx_priv
, napi
);
294 bdx_tx_cleanup(priv
);
295 work_done
= bdx_rx_receive(priv
, &priv
->rxd_fifo0
, budget
);
296 if ((work_done
< budget
) ||
297 (priv
->napi_stop
++ >= 30)) {
298 DBG("rx poll is done. backing to isr-driven\n");
300 /* from time to time we exit to let NAPI layer release
301 * device lock and allow waiting tasks (eg rmmod) to advance) */
305 bdx_enable_interrupts(priv
);
310 /* bdx_fw_load - loads firmware to NIC
311 * @priv - NIC private structure
312 * Firmware is loaded via TXD fifo, so it must be initialized first.
313 * Firware must be loaded once per NIC not per PCI device provided by NIC (NIC
314 * can have few of them). So all drivers use semaphore register to choose one
315 * that will actually load FW to NIC.
318 static int bdx_fw_load(struct bdx_priv
*priv
)
320 const struct firmware
*fw
= NULL
;
325 master
= READ_REG(priv
, regINIT_SEMAPHORE
);
326 if (!READ_REG(priv
, regINIT_STATUS
) && master
) {
327 rc
= request_firmware(&fw
, "tehuti/firmware.bin", &priv
->pdev
->dev
);
330 bdx_tx_push_desc_safe(priv
, (char *)fw
->data
, fw
->size
);
333 for (i
= 0; i
< 200; i
++) {
334 if (READ_REG(priv
, regINIT_STATUS
)) {
343 WRITE_REG(priv
, regINIT_SEMAPHORE
, 1);
345 release_firmware(fw
);
348 ERR("%s: firmware loading failed\n", priv
->ndev
->name
);
350 DBG("VPC = 0x%x VIC = 0x%x INIT_STATUS = 0x%x i=%d\n",
351 READ_REG(priv
, regVPC
),
352 READ_REG(priv
, regVIC
),
353 READ_REG(priv
, regINIT_STATUS
), i
);
356 DBG("%s: firmware loading success\n", priv
->ndev
->name
);
361 static void bdx_restore_mac(struct net_device
*ndev
, struct bdx_priv
*priv
)
366 DBG("mac0=%x mac1=%x mac2=%x\n",
367 READ_REG(priv
, regUNC_MAC0_A
),
368 READ_REG(priv
, regUNC_MAC1_A
), READ_REG(priv
, regUNC_MAC2_A
));
370 val
= (ndev
->dev_addr
[0] << 8) | (ndev
->dev_addr
[1]);
371 WRITE_REG(priv
, regUNC_MAC2_A
, val
);
372 val
= (ndev
->dev_addr
[2] << 8) | (ndev
->dev_addr
[3]);
373 WRITE_REG(priv
, regUNC_MAC1_A
, val
);
374 val
= (ndev
->dev_addr
[4] << 8) | (ndev
->dev_addr
[5]);
375 WRITE_REG(priv
, regUNC_MAC0_A
, val
);
377 DBG("mac0=%x mac1=%x mac2=%x\n",
378 READ_REG(priv
, regUNC_MAC0_A
),
379 READ_REG(priv
, regUNC_MAC1_A
), READ_REG(priv
, regUNC_MAC2_A
));
383 /* bdx_hw_start - inits registers and starts HW's Rx and Tx engines
384 * @priv - NIC private structure
386 static int bdx_hw_start(struct bdx_priv
*priv
)
389 struct net_device
*ndev
= priv
->ndev
;
392 bdx_link_changed(priv
);
394 /* 10G overall max length (vlan, eth&ip header, ip payload, crc) */
395 WRITE_REG(priv
, regFRM_LENGTH
, 0X3FE0);
396 WRITE_REG(priv
, regPAUSE_QUANT
, 0x96);
397 WRITE_REG(priv
, regRX_FIFO_SECTION
, 0x800010);
398 WRITE_REG(priv
, regTX_FIFO_SECTION
, 0xE00010);
399 WRITE_REG(priv
, regRX_FULLNESS
, 0);
400 WRITE_REG(priv
, regTX_FULLNESS
, 0);
401 WRITE_REG(priv
, regCTRLST
,
402 regCTRLST_BASE
| regCTRLST_RX_ENA
| regCTRLST_TX_ENA
);
404 WRITE_REG(priv
, regVGLB
, 0);
405 WRITE_REG(priv
, regMAX_FRAME_A
,
406 priv
->rxf_fifo0
.m
.pktsz
& MAX_FRAME_AB_VAL
);
408 DBG("RDINTCM=%08x\n", priv
->rdintcm
); /*NOTE: test script uses this */
409 WRITE_REG(priv
, regRDINTCM0
, priv
->rdintcm
);
410 WRITE_REG(priv
, regRDINTCM2
, 0); /*cpu_to_le32(rcm.val)); */
412 DBG("TDINTCM=%08x\n", priv
->tdintcm
); /*NOTE: test script uses this */
413 WRITE_REG(priv
, regTDINTCM0
, priv
->tdintcm
); /* old val = 0x300064 */
415 /* Enable timer interrupt once in 2 secs. */
416 /*WRITE_REG(priv, regGTMR0, ((GTMR_SEC * 2) & GTMR_DATA)); */
417 bdx_restore_mac(priv
->ndev
, priv
);
419 WRITE_REG(priv
, regGMAC_RXF_A
, GMAC_RX_FILTER_OSEN
|
420 GMAC_RX_FILTER_AM
| GMAC_RX_FILTER_AB
);
422 #define BDX_IRQ_TYPE ((priv->nic->irq_type == IRQ_MSI)?0:IRQF_SHARED)
423 if ((rc
= request_irq(priv
->pdev
->irq
, bdx_isr_napi
, BDX_IRQ_TYPE
,
426 bdx_enable_interrupts(priv
);
434 static void bdx_hw_stop(struct bdx_priv
*priv
)
437 bdx_disable_interrupts(priv
);
438 free_irq(priv
->pdev
->irq
, priv
->ndev
);
440 netif_carrier_off(priv
->ndev
);
441 netif_stop_queue(priv
->ndev
);
446 static int bdx_hw_reset_direct(void __iomem
*regs
)
451 /* reset sequences: read, write 1, read, write 0 */
452 val
= readl(regs
+ regCLKPLL
);
453 writel((val
| CLKPLL_SFTRST
) + 0x8, regs
+ regCLKPLL
);
455 val
= readl(regs
+ regCLKPLL
);
456 writel(val
& ~CLKPLL_SFTRST
, regs
+ regCLKPLL
);
458 /* check that the PLLs are locked and reset ended */
459 for (i
= 0; i
< 70; i
++, mdelay(10))
460 if ((readl(regs
+ regCLKPLL
) & CLKPLL_LKD
) == CLKPLL_LKD
) {
461 /* do any PCI-E read transaction */
462 readl(regs
+ regRXD_CFG0_0
);
465 ERR("tehuti: HW reset failed\n");
466 return 1; /* failure */
469 static int bdx_hw_reset(struct bdx_priv
*priv
)
474 if (priv
->port
== 0) {
475 /* reset sequences: read, write 1, read, write 0 */
476 val
= READ_REG(priv
, regCLKPLL
);
477 WRITE_REG(priv
, regCLKPLL
, (val
| CLKPLL_SFTRST
) + 0x8);
479 val
= READ_REG(priv
, regCLKPLL
);
480 WRITE_REG(priv
, regCLKPLL
, val
& ~CLKPLL_SFTRST
);
482 /* check that the PLLs are locked and reset ended */
483 for (i
= 0; i
< 70; i
++, mdelay(10))
484 if ((READ_REG(priv
, regCLKPLL
) & CLKPLL_LKD
) == CLKPLL_LKD
) {
485 /* do any PCI-E read transaction */
486 READ_REG(priv
, regRXD_CFG0_0
);
489 ERR("tehuti: HW reset failed\n");
490 return 1; /* failure */
493 static int bdx_sw_reset(struct bdx_priv
*priv
)
498 /* 1. load MAC (obsolete) */
499 /* 2. disable Rx (and Tx) */
500 WRITE_REG(priv
, regGMAC_RXF_A
, 0);
502 /* 3. disable port */
503 WRITE_REG(priv
, regDIS_PORT
, 1);
504 /* 4. disable queue */
505 WRITE_REG(priv
, regDIS_QU
, 1);
506 /* 5. wait until hw is disabled */
507 for (i
= 0; i
< 50; i
++) {
508 if (READ_REG(priv
, regRST_PORT
) & 1)
513 ERR("%s: SW reset timeout. continuing anyway\n",
516 /* 6. disable intrs */
517 WRITE_REG(priv
, regRDINTCM0
, 0);
518 WRITE_REG(priv
, regTDINTCM0
, 0);
519 WRITE_REG(priv
, regIMR
, 0);
520 READ_REG(priv
, regISR
);
523 WRITE_REG(priv
, regRST_QU
, 1);
525 WRITE_REG(priv
, regRST_PORT
, 1);
526 /* 9. zero all read and write pointers */
527 for (i
= regTXD_WPTR_0
; i
<= regTXF_RPTR_3
; i
+= 0x10)
528 DBG("%x = %x\n", i
, READ_REG(priv
, i
) & TXF_WPTR_WR_PTR
);
529 for (i
= regTXD_WPTR_0
; i
<= regTXF_RPTR_3
; i
+= 0x10)
530 WRITE_REG(priv
, i
, 0);
531 /* 10. unseet port disable */
532 WRITE_REG(priv
, regDIS_PORT
, 0);
533 /* 11. unset queue disable */
534 WRITE_REG(priv
, regDIS_QU
, 0);
535 /* 12. unset queue reset */
536 WRITE_REG(priv
, regRST_QU
, 0);
537 /* 13. unset port reset */
538 WRITE_REG(priv
, regRST_PORT
, 0);
540 /* skiped. will be done later */
541 /* 15. save MAC (obsolete) */
542 for (i
= regTXD_WPTR_0
; i
<= regTXF_RPTR_3
; i
+= 0x10)
543 DBG("%x = %x\n", i
, READ_REG(priv
, i
) & TXF_WPTR_WR_PTR
);
548 /* bdx_reset - performs right type of reset depending on hw type */
549 static int bdx_reset(struct bdx_priv
*priv
)
552 RET((priv
->pdev
->device
== 0x3009)
554 : bdx_sw_reset(priv
));
558 * bdx_close - Disables a network interface
559 * @netdev: network interface device structure
561 * Returns 0, this is not allowed to fail
563 * The close entry point is called when an interface is de-activated
564 * by the OS. The hardware is still under the drivers control, but
565 * needs to be disabled. A global MAC reset is issued to stop the
566 * hardware, and all transmit and receive resources are freed.
568 static int bdx_close(struct net_device
*ndev
)
570 struct bdx_priv
*priv
= NULL
;
573 priv
= netdev_priv(ndev
);
575 napi_disable(&priv
->napi
);
585 * bdx_open - Called when a network interface is made active
586 * @netdev: network interface device structure
588 * Returns 0 on success, negative value on failure
590 * The open entry point is called when a network interface is made
591 * active by the system (IFF_UP). At this point all resources needed
592 * for transmit and receive operations are allocated, the interrupt
593 * handler is registered with the OS, the watchdog timer is started,
594 * and the stack is notified that the interface is ready.
596 static int bdx_open(struct net_device
*ndev
)
598 struct bdx_priv
*priv
;
602 priv
= netdev_priv(ndev
);
604 if (netif_running(ndev
))
605 netif_stop_queue(priv
->ndev
);
607 if ((rc
= bdx_tx_init(priv
)))
610 if ((rc
= bdx_rx_init(priv
)))
613 if ((rc
= bdx_fw_load(priv
)))
616 bdx_rx_alloc_skbs(priv
, &priv
->rxf_fifo0
);
618 if ((rc
= bdx_hw_start(priv
)))
621 napi_enable(&priv
->napi
);
623 print_fw_id(priv
->nic
);
632 static int bdx_range_check(struct bdx_priv
*priv
, u32 offset
)
634 return (offset
> (u32
) (BDX_REGS_SIZE
/ priv
->nic
->port_num
)) ?
638 static int bdx_ioctl_priv(struct net_device
*ndev
, struct ifreq
*ifr
, int cmd
)
640 struct bdx_priv
*priv
= netdev_priv(ndev
);
646 DBG("jiffies=%ld cmd=%d\n", jiffies
, cmd
);
647 if (cmd
!= SIOCDEVPRIVATE
) {
648 error
= copy_from_user(data
, ifr
->ifr_data
, sizeof(data
));
650 ERR("cant copy from user\n");
653 DBG("%d 0x%x 0x%x\n", data
[0], data
[1], data
[2]);
656 if (!capable(CAP_SYS_RAWIO
))
662 error
= bdx_range_check(priv
, data
[1]);
665 data
[2] = READ_REG(priv
, data
[1]);
666 DBG("read_reg(0x%x)=0x%x (dec %d)\n", data
[1], data
[2],
668 error
= copy_to_user(ifr
->ifr_data
, data
, sizeof(data
));
674 error
= bdx_range_check(priv
, data
[1]);
677 WRITE_REG(priv
, data
[1], data
[2]);
678 DBG("write_reg(0x%x, 0x%x)\n", data
[1], data
[2]);
687 static int bdx_ioctl(struct net_device
*ndev
, struct ifreq
*ifr
, int cmd
)
690 if (cmd
>= SIOCDEVPRIVATE
&& cmd
<= (SIOCDEVPRIVATE
+ 15))
691 RET(bdx_ioctl_priv(ndev
, ifr
, cmd
));
697 * __bdx_vlan_rx_vid - private helper for adding/killing VLAN vid
698 * by passing VLAN filter table to hardware
699 * @ndev network device
701 * @op add or kill operation
703 static void __bdx_vlan_rx_vid(struct net_device
*ndev
, uint16_t vid
, int enable
)
705 struct bdx_priv
*priv
= netdev_priv(ndev
);
709 DBG2("vid=%d value=%d\n", (int)vid
, enable
);
710 if (unlikely(vid
>= 4096)) {
711 ERR("tehuti: invalid VID: %u (> 4096)\n", vid
);
714 reg
= regVLAN_0
+ (vid
/ 32) * 4;
716 val
= READ_REG(priv
, reg
);
717 DBG2("reg=%x, val=%x, bit=%d\n", reg
, val
, bit
);
722 DBG2("new val %x\n", val
);
723 WRITE_REG(priv
, reg
, val
);
728 * bdx_vlan_rx_add_vid - kernel hook for adding VLAN vid to hw filtering table
729 * @ndev network device
730 * @vid VLAN vid to add
732 static void bdx_vlan_rx_add_vid(struct net_device
*ndev
, uint16_t vid
)
734 __bdx_vlan_rx_vid(ndev
, vid
, 1);
738 * bdx_vlan_rx_kill_vid - kernel hook for killing VLAN vid in hw filtering table
739 * @ndev network device
740 * @vid VLAN vid to kill
742 static void bdx_vlan_rx_kill_vid(struct net_device
*ndev
, unsigned short vid
)
744 __bdx_vlan_rx_vid(ndev
, vid
, 0);
748 * bdx_vlan_rx_register - kernel hook for adding VLAN group
749 * @ndev network device
753 bdx_vlan_rx_register(struct net_device
*ndev
, struct vlan_group
*grp
)
755 struct bdx_priv
*priv
= netdev_priv(ndev
);
758 DBG("device='%s', group='%p'\n", ndev
->name
, grp
);
764 * bdx_change_mtu - Change the Maximum Transfer Unit
765 * @netdev: network interface device structure
766 * @new_mtu: new value for maximum frame size
768 * Returns 0 on success, negative on failure
770 static int bdx_change_mtu(struct net_device
*ndev
, int new_mtu
)
774 if (new_mtu
== ndev
->mtu
)
777 /* enforce minimum frame size */
778 if (new_mtu
< ETH_ZLEN
) {
779 ERR("%s: %s mtu %d is less then minimal %d\n",
780 BDX_DRV_NAME
, ndev
->name
, new_mtu
, ETH_ZLEN
);
785 if (netif_running(ndev
)) {
792 static void bdx_setmulti(struct net_device
*ndev
)
794 struct bdx_priv
*priv
= netdev_priv(ndev
);
797 GMAC_RX_FILTER_AM
| GMAC_RX_FILTER_AB
| GMAC_RX_FILTER_OSEN
;
801 /* IMF - imperfect (hash) rx multicat filter */
802 /* PMF - perfect rx multicat filter */
804 /* FIXME: RXE(OFF) */
805 if (ndev
->flags
& IFF_PROMISC
) {
806 rxf_val
|= GMAC_RX_FILTER_PRM
;
807 } else if (ndev
->flags
& IFF_ALLMULTI
) {
808 /* set IMF to accept all multicast frmaes */
809 for (i
= 0; i
< MAC_MCST_HASH_NUM
; i
++)
810 WRITE_REG(priv
, regRX_MCST_HASH0
+ i
* 4, ~0);
811 } else if (!netdev_mc_empty(ndev
)) {
813 struct dev_mc_list
*mclist
;
816 /* set IMF to deny all multicast frames */
817 for (i
= 0; i
< MAC_MCST_HASH_NUM
; i
++)
818 WRITE_REG(priv
, regRX_MCST_HASH0
+ i
* 4, 0);
819 /* set PMF to deny all multicast frames */
820 for (i
= 0; i
< MAC_MCST_NUM
; i
++) {
821 WRITE_REG(priv
, regRX_MAC_MCST0
+ i
* 8, 0);
822 WRITE_REG(priv
, regRX_MAC_MCST1
+ i
* 8, 0);
825 /* use PMF to accept first MAC_MCST_NUM (15) addresses */
826 /* TBD: sort addreses and write them in ascending order
827 * into RX_MAC_MCST regs. we skip this phase now and accept ALL
828 * multicast frames throu IMF */
829 mclist
= ndev
->mc_list
;
831 /* accept the rest of addresses throu IMF */
832 for (; mclist
; mclist
= mclist
->next
) {
834 for (i
= 0; i
< ETH_ALEN
; i
++)
835 hash
^= mclist
->dmi_addr
[i
];
836 reg
= regRX_MCST_HASH0
+ ((hash
>> 5) << 2);
837 val
= READ_REG(priv
, reg
);
838 val
|= (1 << (hash
% 32));
839 WRITE_REG(priv
, reg
, val
);
843 DBG("only own mac %d\n", netdev_mc_count(ndev
));
844 rxf_val
|= GMAC_RX_FILTER_AB
;
846 WRITE_REG(priv
, regGMAC_RXF_A
, rxf_val
);
852 static int bdx_set_mac(struct net_device
*ndev
, void *p
)
854 struct bdx_priv
*priv
= netdev_priv(ndev
);
855 struct sockaddr
*addr
= p
;
859 if (netif_running(dev))
862 memcpy(ndev
->dev_addr
, addr
->sa_data
, ndev
->addr_len
);
863 bdx_restore_mac(ndev
, priv
);
867 static int bdx_read_mac(struct bdx_priv
*priv
)
869 u16 macAddress
[3], i
;
872 macAddress
[2] = READ_REG(priv
, regUNC_MAC0_A
);
873 macAddress
[2] = READ_REG(priv
, regUNC_MAC0_A
);
874 macAddress
[1] = READ_REG(priv
, regUNC_MAC1_A
);
875 macAddress
[1] = READ_REG(priv
, regUNC_MAC1_A
);
876 macAddress
[0] = READ_REG(priv
, regUNC_MAC2_A
);
877 macAddress
[0] = READ_REG(priv
, regUNC_MAC2_A
);
878 for (i
= 0; i
< 3; i
++) {
879 priv
->ndev
->dev_addr
[i
* 2 + 1] = macAddress
[i
];
880 priv
->ndev
->dev_addr
[i
* 2] = macAddress
[i
] >> 8;
885 static u64
bdx_read_l2stat(struct bdx_priv
*priv
, int reg
)
889 val
= READ_REG(priv
, reg
);
890 val
|= ((u64
) READ_REG(priv
, reg
+ 8)) << 32;
894 /*Do the statistics-update work*/
895 static void bdx_update_stats(struct bdx_priv
*priv
)
897 struct bdx_stats
*stats
= &priv
->hw_stats
;
898 u64
*stats_vector
= (u64
*) stats
;
902 /*Fill HW structure */
904 /*First 12 statistics - 0x7200 - 0x72B0 */
905 for (i
= 0; i
< 12; i
++) {
906 stats_vector
[i
] = bdx_read_l2stat(priv
, addr
);
909 BDX_ASSERT(addr
!= 0x72C0);
910 /* 0x72C0-0x72E0 RSRV */
912 for (; i
< 16; i
++) {
913 stats_vector
[i
] = bdx_read_l2stat(priv
, addr
);
916 BDX_ASSERT(addr
!= 0x7330);
917 /* 0x7330-0x7360 RSRV */
919 for (; i
< 19; i
++) {
920 stats_vector
[i
] = bdx_read_l2stat(priv
, addr
);
923 BDX_ASSERT(addr
!= 0x73A0);
924 /* 0x73A0-0x73B0 RSRV */
926 for (; i
< 23; i
++) {
927 stats_vector
[i
] = bdx_read_l2stat(priv
, addr
);
930 BDX_ASSERT(addr
!= 0x7400);
931 BDX_ASSERT((sizeof(struct bdx_stats
) / sizeof(u64
)) != i
);
934 static struct net_device_stats
*bdx_get_stats(struct net_device
*ndev
)
936 struct bdx_priv
*priv
= netdev_priv(ndev
);
937 struct net_device_stats
*net_stat
= &priv
->net_stats
;
941 static void print_rxdd(struct rxd_desc
*rxdd
, u32 rxd_val1
, u16 len
,
943 static void print_rxfd(struct rxf_desc
*rxfd
);
945 /*************************************************************************
947 *************************************************************************/
949 static void bdx_rxdb_destroy(struct rxdb
*db
)
954 static struct rxdb
*bdx_rxdb_create(int nelem
)
959 db
= vmalloc(sizeof(struct rxdb
)
960 + (nelem
* sizeof(int))
961 + (nelem
* sizeof(struct rx_map
)));
962 if (likely(db
!= NULL
)) {
963 db
->stack
= (int *)(db
+ 1);
964 db
->elems
= (void *)(db
->stack
+ nelem
);
967 for (i
= 0; i
< nelem
; i
++)
968 db
->stack
[i
] = nelem
- i
- 1; /* to make first allocs
975 static inline int bdx_rxdb_alloc_elem(struct rxdb
*db
)
977 BDX_ASSERT(db
->top
<= 0);
978 return db
->stack
[--(db
->top
)];
981 static inline void *bdx_rxdb_addr_elem(struct rxdb
*db
, int n
)
983 BDX_ASSERT((n
< 0) || (n
>= db
->nelem
));
984 return db
->elems
+ n
;
987 static inline int bdx_rxdb_available(struct rxdb
*db
)
992 static inline void bdx_rxdb_free_elem(struct rxdb
*db
, int n
)
994 BDX_ASSERT((n
>= db
->nelem
) || (n
< 0));
995 db
->stack
[(db
->top
)++] = n
;
998 /*************************************************************************
1000 *************************************************************************/
1002 /* bdx_rx_init - initialize RX all related HW and SW resources
1003 * @priv - NIC private structure
1005 * Returns 0 on success, negative value on failure
1007 * It creates rxf and rxd fifos, update relevant HW registers, preallocate
1008 * skb for rx. It assumes that Rx is desabled in HW
1009 * funcs are grouped for better cache usage
1011 * RxD fifo is smaller than RxF fifo by design. Upon high load, RxD will be
1012 * filled and packets will be dropped by nic without getting into host or
1013 * cousing interrupt. Anyway, in that condition, host has no chance to proccess
1014 * all packets, but dropping in nic is cheaper, since it takes 0 cpu cycles
1017 /* TBD: ensure proper packet size */
1019 static int bdx_rx_init(struct bdx_priv
*priv
)
1023 if (bdx_fifo_init(priv
, &priv
->rxd_fifo0
.m
, priv
->rxd_size
,
1024 regRXD_CFG0_0
, regRXD_CFG1_0
,
1025 regRXD_RPTR_0
, regRXD_WPTR_0
))
1027 if (bdx_fifo_init(priv
, &priv
->rxf_fifo0
.m
, priv
->rxf_size
,
1028 regRXF_CFG0_0
, regRXF_CFG1_0
,
1029 regRXF_RPTR_0
, regRXF_WPTR_0
))
1033 bdx_rxdb_create(priv
->rxf_fifo0
.m
.memsz
/
1034 sizeof(struct rxf_desc
))))
1037 priv
->rxf_fifo0
.m
.pktsz
= priv
->ndev
->mtu
+ VLAN_ETH_HLEN
;
1041 ERR("%s: %s: Rx init failed\n", BDX_DRV_NAME
, priv
->ndev
->name
);
1045 /* bdx_rx_free_skbs - frees and unmaps all skbs allocated for the fifo
1046 * @priv - NIC private structure
1049 static void bdx_rx_free_skbs(struct bdx_priv
*priv
, struct rxf_fifo
*f
)
1052 struct rxdb
*db
= priv
->rxdb
;
1056 DBG("total=%d free=%d busy=%d\n", db
->nelem
, bdx_rxdb_available(db
),
1057 db
->nelem
- bdx_rxdb_available(db
));
1058 while (bdx_rxdb_available(db
) > 0) {
1059 i
= bdx_rxdb_alloc_elem(db
);
1060 dm
= bdx_rxdb_addr_elem(db
, i
);
1063 for (i
= 0; i
< db
->nelem
; i
++) {
1064 dm
= bdx_rxdb_addr_elem(db
, i
);
1066 pci_unmap_single(priv
->pdev
,
1067 dm
->dma
, f
->m
.pktsz
,
1068 PCI_DMA_FROMDEVICE
);
1069 dev_kfree_skb(dm
->skb
);
1074 /* bdx_rx_free - release all Rx resources
1075 * @priv - NIC private structure
1076 * It assumes that Rx is desabled in HW
1078 static void bdx_rx_free(struct bdx_priv
*priv
)
1082 bdx_rx_free_skbs(priv
, &priv
->rxf_fifo0
);
1083 bdx_rxdb_destroy(priv
->rxdb
);
1086 bdx_fifo_free(priv
, &priv
->rxf_fifo0
.m
);
1087 bdx_fifo_free(priv
, &priv
->rxd_fifo0
.m
);
1092 /*************************************************************************
1094 *************************************************************************/
1096 /* bdx_rx_alloc_skbs - fill rxf fifo with new skbs
1097 * @priv - nic's private structure
1098 * @f - RXF fifo that needs skbs
1099 * It allocates skbs, build rxf descs and push it (rxf descr) into rxf fifo.
1100 * skb's virtual and physical addresses are stored in skb db.
1101 * To calculate free space, func uses cached values of RPTR and WPTR
1102 * When needed, it also updates RPTR and WPTR.
1105 /* TBD: do not update WPTR if no desc were written */
1107 static void bdx_rx_alloc_skbs(struct bdx_priv
*priv
, struct rxf_fifo
*f
)
1109 struct sk_buff
*skb
;
1110 struct rxf_desc
*rxfd
;
1112 int dno
, delta
, idx
;
1113 struct rxdb
*db
= priv
->rxdb
;
1116 dno
= bdx_rxdb_available(db
) - 1;
1118 if (!(skb
= dev_alloc_skb(f
->m
.pktsz
+ NET_IP_ALIGN
))) {
1119 ERR("NO MEM: dev_alloc_skb failed\n");
1122 skb
->dev
= priv
->ndev
;
1123 skb_reserve(skb
, NET_IP_ALIGN
);
1125 idx
= bdx_rxdb_alloc_elem(db
);
1126 dm
= bdx_rxdb_addr_elem(db
, idx
);
1127 dm
->dma
= pci_map_single(priv
->pdev
,
1128 skb
->data
, f
->m
.pktsz
,
1129 PCI_DMA_FROMDEVICE
);
1131 rxfd
= (struct rxf_desc
*)(f
->m
.va
+ f
->m
.wptr
);
1132 rxfd
->info
= CPU_CHIP_SWAP32(0x10003); /* INFO=1 BC=3 */
1134 rxfd
->pa_lo
= CPU_CHIP_SWAP32(L32_64(dm
->dma
));
1135 rxfd
->pa_hi
= CPU_CHIP_SWAP32(H32_64(dm
->dma
));
1136 rxfd
->len
= CPU_CHIP_SWAP32(f
->m
.pktsz
);
1139 f
->m
.wptr
+= sizeof(struct rxf_desc
);
1140 delta
= f
->m
.wptr
- f
->m
.memsz
;
1141 if (unlikely(delta
>= 0)) {
1144 memcpy(f
->m
.va
, f
->m
.va
+ f
->m
.memsz
, delta
);
1145 DBG("wrapped descriptor\n");
1150 /*TBD: to do - delayed rxf wptr like in txd */
1151 WRITE_REG(priv
, f
->m
.reg_WPTR
, f
->m
.wptr
& TXF_WPTR_WR_PTR
);
1156 NETIF_RX_MUX(struct bdx_priv
*priv
, u32 rxd_val1
, u16 rxd_vlan
,
1157 struct sk_buff
*skb
)
1160 DBG("rxdd->flags.bits.vtag=%d vlgrp=%p\n", GET_RXD_VTAG(rxd_val1
),
1162 if (priv
->vlgrp
&& GET_RXD_VTAG(rxd_val1
)) {
1163 DBG("%s: vlan rcv vlan '%x' vtag '%x', device name '%s'\n",
1165 GET_RXD_VLAN_ID(rxd_vlan
),
1166 GET_RXD_VTAG(rxd_val1
),
1167 vlan_group_get_device(priv
->vlgrp
,
1168 GET_RXD_VLAN_ID(rxd_vlan
))->name
);
1169 /* NAPI variant of receive functions */
1170 vlan_hwaccel_receive_skb(skb
, priv
->vlgrp
,
1171 GET_RXD_VLAN_TCI(rxd_vlan
));
1173 netif_receive_skb(skb
);
1177 static void bdx_recycle_skb(struct bdx_priv
*priv
, struct rxd_desc
*rxdd
)
1179 struct rxf_desc
*rxfd
;
1183 struct sk_buff
*skb
;
1187 DBG("priv=%p rxdd=%p\n", priv
, rxdd
);
1188 f
= &priv
->rxf_fifo0
;
1190 DBG("db=%p f=%p\n", db
, f
);
1191 dm
= bdx_rxdb_addr_elem(db
, rxdd
->va_lo
);
1194 rxfd
= (struct rxf_desc
*)(f
->m
.va
+ f
->m
.wptr
);
1195 rxfd
->info
= CPU_CHIP_SWAP32(0x10003); /* INFO=1 BC=3 */
1196 rxfd
->va_lo
= rxdd
->va_lo
;
1197 rxfd
->pa_lo
= CPU_CHIP_SWAP32(L32_64(dm
->dma
));
1198 rxfd
->pa_hi
= CPU_CHIP_SWAP32(H32_64(dm
->dma
));
1199 rxfd
->len
= CPU_CHIP_SWAP32(f
->m
.pktsz
);
1202 f
->m
.wptr
+= sizeof(struct rxf_desc
);
1203 delta
= f
->m
.wptr
- f
->m
.memsz
;
1204 if (unlikely(delta
>= 0)) {
1207 memcpy(f
->m
.va
, f
->m
.va
+ f
->m
.memsz
, delta
);
1208 DBG("wrapped descriptor\n");
1214 /* bdx_rx_receive - recieves full packets from RXD fifo and pass them to OS
1215 * NOTE: a special treatment is given to non-continous descriptors
1216 * that start near the end, wraps around and continue at the beginning. a second
1217 * part is copied right after the first, and then descriptor is interpreted as
1218 * normal. fifo has an extra space to allow such operations
1219 * @priv - nic's private structure
1220 * @f - RXF fifo that needs skbs
1223 /* TBD: replace memcpy func call by explicite inline asm */
1225 static int bdx_rx_receive(struct bdx_priv
*priv
, struct rxd_fifo
*f
, int budget
)
1227 struct sk_buff
*skb
, *skb2
;
1228 struct rxd_desc
*rxdd
;
1230 struct rxf_fifo
*rxf_fifo
;
1233 int max_done
= BDX_MAX_RX_DONE
;
1234 struct rxdb
*db
= NULL
;
1235 /* Unmarshalled descriptor - copy of descriptor in host order */
1243 f
->m
.wptr
= READ_REG(priv
, f
->m
.reg_WPTR
) & TXF_WPTR_WR_PTR
;
1245 size
= f
->m
.wptr
- f
->m
.rptr
;
1247 size
= f
->m
.memsz
+ size
; /* size is negative :-) */
1251 rxdd
= (struct rxd_desc
*)(f
->m
.va
+ f
->m
.rptr
);
1252 rxd_val1
= CPU_CHIP_SWAP32(rxdd
->rxd_val1
);
1254 len
= CPU_CHIP_SWAP16(rxdd
->len
);
1256 rxd_vlan
= CPU_CHIP_SWAP16(rxdd
->rxd_vlan
);
1258 print_rxdd(rxdd
, rxd_val1
, len
, rxd_vlan
);
1260 tmp_len
= GET_RXD_BC(rxd_val1
) << 3;
1261 BDX_ASSERT(tmp_len
<= 0);
1263 if (size
< 0) /* test for partially arrived descriptor */
1266 f
->m
.rptr
+= tmp_len
;
1268 tmp_len
= f
->m
.rptr
- f
->m
.memsz
;
1269 if (unlikely(tmp_len
>= 0)) {
1270 f
->m
.rptr
= tmp_len
;
1272 DBG("wrapped desc rptr=%d tmp_len=%d\n",
1273 f
->m
.rptr
, tmp_len
);
1274 memcpy(f
->m
.va
+ f
->m
.memsz
, f
->m
.va
, tmp_len
);
1278 if (unlikely(GET_RXD_ERR(rxd_val1
))) {
1279 DBG("rxd_err = 0x%x\n", GET_RXD_ERR(rxd_val1
));
1280 priv
->net_stats
.rx_errors
++;
1281 bdx_recycle_skb(priv
, rxdd
);
1285 rxf_fifo
= &priv
->rxf_fifo0
;
1287 dm
= bdx_rxdb_addr_elem(db
, rxdd
->va_lo
);
1290 if (len
< BDX_COPYBREAK
&&
1291 (skb2
= dev_alloc_skb(len
+ NET_IP_ALIGN
))) {
1292 skb_reserve(skb2
, NET_IP_ALIGN
);
1293 /*skb_put(skb2, len); */
1294 pci_dma_sync_single_for_cpu(priv
->pdev
,
1295 dm
->dma
, rxf_fifo
->m
.pktsz
,
1296 PCI_DMA_FROMDEVICE
);
1297 memcpy(skb2
->data
, skb
->data
, len
);
1298 bdx_recycle_skb(priv
, rxdd
);
1301 pci_unmap_single(priv
->pdev
,
1302 dm
->dma
, rxf_fifo
->m
.pktsz
,
1303 PCI_DMA_FROMDEVICE
);
1304 bdx_rxdb_free_elem(db
, rxdd
->va_lo
);
1307 priv
->net_stats
.rx_bytes
+= len
;
1310 skb
->dev
= priv
->ndev
;
1311 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1312 skb
->protocol
= eth_type_trans(skb
, priv
->ndev
);
1314 /* Non-IP packets aren't checksum-offloaded */
1315 if (GET_RXD_PKT_ID(rxd_val1
) == 0)
1316 skb
->ip_summed
= CHECKSUM_NONE
;
1318 NETIF_RX_MUX(priv
, rxd_val1
, rxd_vlan
, skb
);
1320 if (++done
>= max_done
)
1324 priv
->net_stats
.rx_packets
+= done
;
1326 /* FIXME: do smth to minimize pci accesses */
1327 WRITE_REG(priv
, f
->m
.reg_RPTR
, f
->m
.rptr
& TXF_WPTR_WR_PTR
);
1329 bdx_rx_alloc_skbs(priv
, &priv
->rxf_fifo0
);
1334 /*************************************************************************
1335 * Debug / Temprorary Code *
1336 *************************************************************************/
1337 static void print_rxdd(struct rxd_desc
*rxdd
, u32 rxd_val1
, u16 len
,
1340 DBG("ERROR: rxdd bc %d rxfq %d to %d type %d err %d rxp %d "
1341 "pkt_id %d vtag %d len %d vlan_id %d cfi %d prio %d "
1342 "va_lo %d va_hi %d\n",
1343 GET_RXD_BC(rxd_val1
), GET_RXD_RXFQ(rxd_val1
), GET_RXD_TO(rxd_val1
),
1344 GET_RXD_TYPE(rxd_val1
), GET_RXD_ERR(rxd_val1
),
1345 GET_RXD_RXP(rxd_val1
), GET_RXD_PKT_ID(rxd_val1
),
1346 GET_RXD_VTAG(rxd_val1
), len
, GET_RXD_VLAN_ID(rxd_vlan
),
1347 GET_RXD_CFI(rxd_vlan
), GET_RXD_PRIO(rxd_vlan
), rxdd
->va_lo
,
1351 static void print_rxfd(struct rxf_desc
*rxfd
)
1353 DBG("=== RxF desc CHIP ORDER/ENDIANESS =============\n"
1354 "info 0x%x va_lo %u pa_lo 0x%x pa_hi 0x%x len 0x%x\n",
1355 rxfd
->info
, rxfd
->va_lo
, rxfd
->pa_lo
, rxfd
->pa_hi
, rxfd
->len
);
1359 * TX HW/SW interaction overview
1360 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1361 * There are 2 types of TX communication channels betwean driver and NIC.
1362 * 1) TX Free Fifo - TXF - holds ack descriptors for sent packets
1363 * 2) TX Data Fifo - TXD - holds descriptors of full buffers.
1365 * Currently NIC supports TSO, checksuming and gather DMA
1366 * UFO and IP fragmentation is on the way
1368 * RX SW Data Structures
1369 * ~~~~~~~~~~~~~~~~~~~~~
1370 * txdb - used to keep track of all skbs owned by SW and their dma addresses.
1371 * For TX case, ownership lasts from geting packet via hard_xmit and until HW
1372 * acknowledges sent by TXF descriptors.
1373 * Implemented as cyclic buffer.
1374 * fifo - keeps info about fifo's size and location, relevant HW registers,
1375 * usage and skb db. Each RXD and RXF Fifo has its own fifo structure.
1376 * Implemented as simple struct.
1378 * TX SW Execution Flow
1379 * ~~~~~~~~~~~~~~~~~~~~
1380 * OS calls driver's hard_xmit method with packet to sent.
1381 * Driver creates DMA mappings, builds TXD descriptors and kicks HW
1382 * by updating TXD WPTR.
1383 * When packet is sent, HW write us TXF descriptor and SW frees original skb.
1384 * To prevent TXD fifo overflow without reading HW registers every time,
1385 * SW deploys "tx level" technique.
1386 * Upon strart up, tx level is initialized to TXD fifo length.
1387 * For every sent packet, SW gets its TXD descriptor sizei
1388 * (from precalculated array) and substructs it from tx level.
1389 * The size is also stored in txdb. When TXF ack arrives, SW fetch size of
1390 * original TXD descriptor from txdb and adds it to tx level.
1391 * When Tx level drops under some predefined treshhold, the driver
1392 * stops the TX queue. When TX level rises above that level,
1393 * the tx queue is enabled again.
1395 * This technique avoids eccessive reading of RPTR and WPTR registers.
1396 * As our benchmarks shows, it adds 1.5 Gbit/sec to NIS's throuput.
1399 /*************************************************************************
1401 *************************************************************************/
1402 static inline int bdx_tx_db_size(struct txdb
*db
)
1404 int taken
= db
->wptr
- db
->rptr
;
1406 taken
= db
->size
+ 1 + taken
; /* (size + 1) equals memsz */
1408 return db
->size
- taken
;
1411 /* __bdx_tx_ptr_next - helper function, increment read/write pointer + wrap
1413 * @ptr - read or write pointer
1415 static inline void __bdx_tx_db_ptr_next(struct txdb
*db
, struct tx_map
**pptr
)
1417 BDX_ASSERT(db
== NULL
|| pptr
== NULL
); /* sanity */
1419 BDX_ASSERT(*pptr
!= db
->rptr
&& /* expect either read */
1420 *pptr
!= db
->wptr
); /* or write pointer */
1422 BDX_ASSERT(*pptr
< db
->start
|| /* pointer has to be */
1423 *pptr
>= db
->end
); /* in range */
1426 if (unlikely(*pptr
== db
->end
))
1430 /* bdx_tx_db_inc_rptr - increment read pointer
1433 static inline void bdx_tx_db_inc_rptr(struct txdb
*db
)
1435 BDX_ASSERT(db
->rptr
== db
->wptr
); /* can't read from empty db */
1436 __bdx_tx_db_ptr_next(db
, &db
->rptr
);
1439 /* bdx_tx_db_inc_rptr - increment write pointer
1442 static inline void bdx_tx_db_inc_wptr(struct txdb
*db
)
1444 __bdx_tx_db_ptr_next(db
, &db
->wptr
);
1445 BDX_ASSERT(db
->rptr
== db
->wptr
); /* we can not get empty db as
1446 a result of write */
1449 /* bdx_tx_db_init - creates and initializes tx db
1451 * @sz_type - size of tx fifo
1452 * Returns 0 on success, error code otherwise
1454 static int bdx_tx_db_init(struct txdb
*d
, int sz_type
)
1456 int memsz
= FIFO_SIZE
* (1 << (sz_type
+ 1));
1458 d
->start
= vmalloc(memsz
);
1463 * In order to differentiate between db is empty and db is full
1464 * states at least one element should always be empty in order to
1465 * avoid rptr == wptr which means db is empty
1467 d
->size
= memsz
/ sizeof(struct tx_map
) - 1;
1468 d
->end
= d
->start
+ d
->size
+ 1; /* just after last element */
1470 /* all dbs are created equally empty */
1477 /* bdx_tx_db_close - closes tx db and frees all memory
1480 static void bdx_tx_db_close(struct txdb
*d
)
1482 BDX_ASSERT(d
== NULL
);
1488 /*************************************************************************
1490 *************************************************************************/
1492 /* sizes of tx desc (including padding if needed) as function
1493 * of skb's frag number */
1496 u16 qwords
; /* qword = 64 bit */
1497 } txd_sizes
[MAX_SKB_FRAGS
+ 1];
1499 /* txdb_map_skb - creates and stores dma mappings for skb's data blocks
1500 * @priv - NIC private structure
1501 * @skb - socket buffer to map
1503 * It makes dma mappings for skb's data blocks and writes them to PBL of
1504 * new tx descriptor. It also stores them in the tx db, so they could be
1505 * unmaped after data was sent. It is reponsibility of a caller to make
1506 * sure that there is enough space in the tx db. Last element holds pointer
1507 * to skb itself and marked with zero length
1510 bdx_tx_map_skb(struct bdx_priv
*priv
, struct sk_buff
*skb
,
1511 struct txd_desc
*txdd
)
1513 struct txdb
*db
= &priv
->txdb
;
1514 struct pbl
*pbl
= &txdd
->pbl
[0];
1515 int nr_frags
= skb_shinfo(skb
)->nr_frags
;
1518 db
->wptr
->len
= skb
->len
- skb
->data_len
;
1519 db
->wptr
->addr
.dma
= pci_map_single(priv
->pdev
, skb
->data
,
1520 db
->wptr
->len
, PCI_DMA_TODEVICE
);
1521 pbl
->len
= CPU_CHIP_SWAP32(db
->wptr
->len
);
1522 pbl
->pa_lo
= CPU_CHIP_SWAP32(L32_64(db
->wptr
->addr
.dma
));
1523 pbl
->pa_hi
= CPU_CHIP_SWAP32(H32_64(db
->wptr
->addr
.dma
));
1524 DBG("=== pbl len: 0x%x ================\n", pbl
->len
);
1525 DBG("=== pbl pa_lo: 0x%x ================\n", pbl
->pa_lo
);
1526 DBG("=== pbl pa_hi: 0x%x ================\n", pbl
->pa_hi
);
1527 bdx_tx_db_inc_wptr(db
);
1529 for (i
= 0; i
< nr_frags
; i
++) {
1530 struct skb_frag_struct
*frag
;
1532 frag
= &skb_shinfo(skb
)->frags
[i
];
1533 db
->wptr
->len
= frag
->size
;
1534 db
->wptr
->addr
.dma
=
1535 pci_map_page(priv
->pdev
, frag
->page
, frag
->page_offset
,
1536 frag
->size
, PCI_DMA_TODEVICE
);
1539 pbl
->len
= CPU_CHIP_SWAP32(db
->wptr
->len
);
1540 pbl
->pa_lo
= CPU_CHIP_SWAP32(L32_64(db
->wptr
->addr
.dma
));
1541 pbl
->pa_hi
= CPU_CHIP_SWAP32(H32_64(db
->wptr
->addr
.dma
));
1542 bdx_tx_db_inc_wptr(db
);
1545 /* add skb clean up info. */
1546 db
->wptr
->len
= -txd_sizes
[nr_frags
].bytes
;
1547 db
->wptr
->addr
.skb
= skb
;
1548 bdx_tx_db_inc_wptr(db
);
1551 /* init_txd_sizes - precalculate sizes of descriptors for skbs up to 16 frags
1552 * number of frags is used as index to fetch correct descriptors size,
1553 * instead of calculating it each time */
1554 static void __init
init_txd_sizes(void)
1558 /* 7 - is number of lwords in txd with one phys buffer
1559 * 3 - is number of lwords used for every additional phys buffer */
1560 for (i
= 0; i
< MAX_SKB_FRAGS
+ 1; i
++) {
1561 lwords
= 7 + (i
* 3);
1563 lwords
++; /* pad it with 1 lword */
1564 txd_sizes
[i
].qwords
= lwords
>> 1;
1565 txd_sizes
[i
].bytes
= lwords
<< 2;
1569 /* bdx_tx_init - initialize all Tx related stuff.
1570 * Namely, TXD and TXF fifos, database etc */
1571 static int bdx_tx_init(struct bdx_priv
*priv
)
1573 if (bdx_fifo_init(priv
, &priv
->txd_fifo0
.m
, priv
->txd_size
,
1575 regTXD_CFG1_0
, regTXD_RPTR_0
, regTXD_WPTR_0
))
1577 if (bdx_fifo_init(priv
, &priv
->txf_fifo0
.m
, priv
->txf_size
,
1579 regTXF_CFG1_0
, regTXF_RPTR_0
, regTXF_WPTR_0
))
1582 /* The TX db has to keep mappings for all packets sent (on TxD)
1583 * and not yet reclaimed (on TxF) */
1584 if (bdx_tx_db_init(&priv
->txdb
, max(priv
->txd_size
, priv
->txf_size
)))
1587 priv
->tx_level
= BDX_MAX_TX_LEVEL
;
1588 #ifdef BDX_DELAY_WPTR
1589 priv
->tx_update_mark
= priv
->tx_level
- 1024;
1594 ERR("tehuti: %s: Tx init failed\n", priv
->ndev
->name
);
1599 * bdx_tx_space - calculates avalable space in TX fifo
1600 * @priv - NIC private structure
1601 * Returns avaliable space in TX fifo in bytes
1603 static inline int bdx_tx_space(struct bdx_priv
*priv
)
1605 struct txd_fifo
*f
= &priv
->txd_fifo0
;
1608 f
->m
.rptr
= READ_REG(priv
, f
->m
.reg_RPTR
) & TXF_WPTR_WR_PTR
;
1609 fsize
= f
->m
.rptr
- f
->m
.wptr
;
1611 fsize
= f
->m
.memsz
+ fsize
;
1615 /* bdx_tx_transmit - send packet to NIC
1616 * @skb - packet to send
1617 * ndev - network device assigned to NIC
1619 * o NETDEV_TX_OK everything ok.
1620 * o NETDEV_TX_BUSY Cannot transmit packet, try later
1621 * Usually a bug, means queue start/stop flow control is broken in
1622 * the driver. Note: the driver must NOT put the skb in its DMA ring.
1623 * o NETDEV_TX_LOCKED Locking failed, please retry quickly.
1625 static netdev_tx_t
bdx_tx_transmit(struct sk_buff
*skb
,
1626 struct net_device
*ndev
)
1628 struct bdx_priv
*priv
= netdev_priv(ndev
);
1629 struct txd_fifo
*f
= &priv
->txd_fifo0
;
1630 int txd_checksum
= 7; /* full checksum */
1632 int txd_vlan_id
= 0;
1636 int nr_frags
= skb_shinfo(skb
)->nr_frags
;
1637 struct txd_desc
*txdd
;
1639 unsigned long flags
;
1642 local_irq_save(flags
);
1643 if (!spin_trylock(&priv
->tx_lock
)) {
1644 local_irq_restore(flags
);
1645 DBG("%s[%s]: TX locked, returning NETDEV_TX_LOCKED\n",
1646 BDX_DRV_NAME
, ndev
->name
);
1647 return NETDEV_TX_LOCKED
;
1650 /* build tx descriptor */
1651 BDX_ASSERT(f
->m
.wptr
>= f
->m
.memsz
); /* started with valid wptr */
1652 txdd
= (struct txd_desc
*)(f
->m
.va
+ f
->m
.wptr
);
1653 if (unlikely(skb
->ip_summed
!= CHECKSUM_PARTIAL
))
1656 if (skb_shinfo(skb
)->gso_size
) {
1657 txd_mss
= skb_shinfo(skb
)->gso_size
;
1659 DBG("skb %p skb len %d gso size = %d\n", skb
, skb
->len
,
1663 if (vlan_tx_tag_present(skb
)) {
1664 /*Cut VLAN ID to 12 bits */
1665 txd_vlan_id
= vlan_tx_tag_get(skb
) & BITS_MASK(12);
1669 txdd
->length
= CPU_CHIP_SWAP16(skb
->len
);
1670 txdd
->mss
= CPU_CHIP_SWAP16(txd_mss
);
1672 CPU_CHIP_SWAP32(TXD_W1_VAL
1673 (txd_sizes
[nr_frags
].qwords
, txd_checksum
, txd_vtag
,
1674 txd_lgsnd
, txd_vlan_id
));
1675 DBG("=== TxD desc =====================\n");
1676 DBG("=== w1: 0x%x ================\n", txdd
->txd_val1
);
1677 DBG("=== w2: mss 0x%x len 0x%x\n", txdd
->mss
, txdd
->length
);
1679 bdx_tx_map_skb(priv
, skb
, txdd
);
1681 /* increment TXD write pointer. In case of
1682 fifo wrapping copy reminder of the descriptor
1684 f
->m
.wptr
+= txd_sizes
[nr_frags
].bytes
;
1685 len
= f
->m
.wptr
- f
->m
.memsz
;
1686 if (unlikely(len
>= 0)) {
1689 BDX_ASSERT(len
> f
->m
.memsz
);
1690 memcpy(f
->m
.va
, f
->m
.va
+ f
->m
.memsz
, len
);
1693 BDX_ASSERT(f
->m
.wptr
>= f
->m
.memsz
); /* finished with valid wptr */
1695 priv
->tx_level
-= txd_sizes
[nr_frags
].bytes
;
1696 BDX_ASSERT(priv
->tx_level
<= 0 || priv
->tx_level
> BDX_MAX_TX_LEVEL
);
1697 #ifdef BDX_DELAY_WPTR
1698 if (priv
->tx_level
> priv
->tx_update_mark
) {
1699 /* Force memory writes to complete before letting h/w
1700 know there are new descriptors to fetch.
1701 (might be needed on platforms like IA64)
1703 WRITE_REG(priv
, f
->m
.reg_WPTR
, f
->m
.wptr
& TXF_WPTR_WR_PTR
);
1705 if (priv
->tx_noupd
++ > BDX_NO_UPD_PACKETS
) {
1707 WRITE_REG(priv
, f
->m
.reg_WPTR
,
1708 f
->m
.wptr
& TXF_WPTR_WR_PTR
);
1712 /* Force memory writes to complete before letting h/w
1713 know there are new descriptors to fetch.
1714 (might be needed on platforms like IA64)
1716 WRITE_REG(priv
, f
->m
.reg_WPTR
, f
->m
.wptr
& TXF_WPTR_WR_PTR
);
1720 ndev
->trans_start
= jiffies
; /* NETIF_F_LLTX driver :( */
1722 priv
->net_stats
.tx_packets
++;
1723 priv
->net_stats
.tx_bytes
+= skb
->len
;
1725 if (priv
->tx_level
< BDX_MIN_TX_LEVEL
) {
1726 DBG("%s: %s: TX Q STOP level %d\n",
1727 BDX_DRV_NAME
, ndev
->name
, priv
->tx_level
);
1728 netif_stop_queue(ndev
);
1731 spin_unlock_irqrestore(&priv
->tx_lock
, flags
);
1732 return NETDEV_TX_OK
;
1735 /* bdx_tx_cleanup - clean TXF fifo, run in the context of IRQ.
1736 * @priv - bdx adapter
1737 * It scans TXF fifo for descriptors, frees DMA mappings and reports to OS
1738 * that those packets were sent
1740 static void bdx_tx_cleanup(struct bdx_priv
*priv
)
1742 struct txf_fifo
*f
= &priv
->txf_fifo0
;
1743 struct txdb
*db
= &priv
->txdb
;
1747 f
->m
.wptr
= READ_REG(priv
, f
->m
.reg_WPTR
) & TXF_WPTR_MASK
;
1748 BDX_ASSERT(f
->m
.rptr
>= f
->m
.memsz
); /* started with valid rptr */
1750 while (f
->m
.wptr
!= f
->m
.rptr
) {
1751 f
->m
.rptr
+= BDX_TXF_DESC_SZ
;
1752 f
->m
.rptr
&= f
->m
.size_mask
;
1754 /* unmap all the fragments */
1755 /* first has to come tx_maps containing dma */
1756 BDX_ASSERT(db
->rptr
->len
== 0);
1758 BDX_ASSERT(db
->rptr
->addr
.dma
== 0);
1759 pci_unmap_page(priv
->pdev
, db
->rptr
->addr
.dma
,
1760 db
->rptr
->len
, PCI_DMA_TODEVICE
);
1761 bdx_tx_db_inc_rptr(db
);
1762 } while (db
->rptr
->len
> 0);
1763 tx_level
-= db
->rptr
->len
; /* '-' koz len is negative */
1765 /* now should come skb pointer - free it */
1766 dev_kfree_skb_irq(db
->rptr
->addr
.skb
);
1767 bdx_tx_db_inc_rptr(db
);
1770 /* let h/w know which TXF descriptors were cleaned */
1771 BDX_ASSERT((f
->m
.wptr
& TXF_WPTR_WR_PTR
) >= f
->m
.memsz
);
1772 WRITE_REG(priv
, f
->m
.reg_RPTR
, f
->m
.rptr
& TXF_WPTR_WR_PTR
);
1774 /* We reclaimed resources, so in case the Q is stopped by xmit callback,
1775 * we resume the transmition and use tx_lock to synchronize with xmit.*/
1776 spin_lock(&priv
->tx_lock
);
1777 priv
->tx_level
+= tx_level
;
1778 BDX_ASSERT(priv
->tx_level
<= 0 || priv
->tx_level
> BDX_MAX_TX_LEVEL
);
1779 #ifdef BDX_DELAY_WPTR
1780 if (priv
->tx_noupd
) {
1782 WRITE_REG(priv
, priv
->txd_fifo0
.m
.reg_WPTR
,
1783 priv
->txd_fifo0
.m
.wptr
& TXF_WPTR_WR_PTR
);
1787 if (unlikely(netif_queue_stopped(priv
->ndev
) &&
1788 netif_carrier_ok(priv
->ndev
) &&
1789 (priv
->tx_level
>= BDX_MIN_TX_LEVEL
))) {
1790 DBG("%s: %s: TX Q WAKE level %d\n",
1791 BDX_DRV_NAME
, priv
->ndev
->name
, priv
->tx_level
);
1792 netif_wake_queue(priv
->ndev
);
1794 spin_unlock(&priv
->tx_lock
);
1797 /* bdx_tx_free_skbs - frees all skbs from TXD fifo.
1798 * It gets called when OS stops this dev, eg upon "ifconfig down" or rmmod
1800 static void bdx_tx_free_skbs(struct bdx_priv
*priv
)
1802 struct txdb
*db
= &priv
->txdb
;
1805 while (db
->rptr
!= db
->wptr
) {
1806 if (likely(db
->rptr
->len
))
1807 pci_unmap_page(priv
->pdev
, db
->rptr
->addr
.dma
,
1808 db
->rptr
->len
, PCI_DMA_TODEVICE
);
1810 dev_kfree_skb(db
->rptr
->addr
.skb
);
1811 bdx_tx_db_inc_rptr(db
);
1816 /* bdx_tx_free - frees all Tx resources */
1817 static void bdx_tx_free(struct bdx_priv
*priv
)
1820 bdx_tx_free_skbs(priv
);
1821 bdx_fifo_free(priv
, &priv
->txd_fifo0
.m
);
1822 bdx_fifo_free(priv
, &priv
->txf_fifo0
.m
);
1823 bdx_tx_db_close(&priv
->txdb
);
1826 /* bdx_tx_push_desc - push descriptor to TxD fifo
1827 * @priv - NIC private structure
1828 * @data - desc's data
1829 * @size - desc's size
1831 * Pushes desc to TxD fifo and overlaps it if needed.
1832 * NOTE: this func does not check for available space. this is responsibility
1833 * of the caller. Neither does it check that data size is smaller than
1836 static void bdx_tx_push_desc(struct bdx_priv
*priv
, void *data
, int size
)
1838 struct txd_fifo
*f
= &priv
->txd_fifo0
;
1839 int i
= f
->m
.memsz
- f
->m
.wptr
;
1845 memcpy(f
->m
.va
+ f
->m
.wptr
, data
, size
);
1848 memcpy(f
->m
.va
+ f
->m
.wptr
, data
, i
);
1849 f
->m
.wptr
= size
- i
;
1850 memcpy(f
->m
.va
, data
+ i
, f
->m
.wptr
);
1852 WRITE_REG(priv
, f
->m
.reg_WPTR
, f
->m
.wptr
& TXF_WPTR_WR_PTR
);
1855 /* bdx_tx_push_desc_safe - push descriptor to TxD fifo in a safe way
1856 * @priv - NIC private structure
1857 * @data - desc's data
1858 * @size - desc's size
1860 * NOTE: this func does check for available space and, if neccessary, waits for
1861 * NIC to read existing data before writing new one.
1863 static void bdx_tx_push_desc_safe(struct bdx_priv
*priv
, void *data
, int size
)
1869 /* we substruct 8 because when fifo is full rptr == wptr
1870 which also means that fifo is empty, we can understand
1871 the difference, but could hw do the same ??? :) */
1872 int avail
= bdx_tx_space(priv
) - 8;
1874 if (timer
++ > 300) { /* prevent endless loop */
1875 DBG("timeout while writing desc to TxD fifo\n");
1878 udelay(50); /* give hw a chance to clean fifo */
1881 avail
= min(avail
, size
);
1882 DBG("about to push %d bytes starting %p size %d\n", avail
,
1884 bdx_tx_push_desc(priv
, data
, avail
);
1891 static const struct net_device_ops bdx_netdev_ops
= {
1892 .ndo_open
= bdx_open
,
1893 .ndo_stop
= bdx_close
,
1894 .ndo_start_xmit
= bdx_tx_transmit
,
1895 .ndo_validate_addr
= eth_validate_addr
,
1896 .ndo_do_ioctl
= bdx_ioctl
,
1897 .ndo_set_multicast_list
= bdx_setmulti
,
1898 .ndo_get_stats
= bdx_get_stats
,
1899 .ndo_change_mtu
= bdx_change_mtu
,
1900 .ndo_set_mac_address
= bdx_set_mac
,
1901 .ndo_vlan_rx_register
= bdx_vlan_rx_register
,
1902 .ndo_vlan_rx_add_vid
= bdx_vlan_rx_add_vid
,
1903 .ndo_vlan_rx_kill_vid
= bdx_vlan_rx_kill_vid
,
1907 * bdx_probe - Device Initialization Routine
1908 * @pdev: PCI device information struct
1909 * @ent: entry in bdx_pci_tbl
1911 * Returns 0 on success, negative on failure
1913 * bdx_probe initializes an adapter identified by a pci_dev structure.
1914 * The OS initialization, configuring of the adapter private structure,
1915 * and a hardware reset occur.
1917 * functions and their order used as explained in
1918 * /usr/src/linux/Documentation/DMA-{API,mapping}.txt
1922 /* TBD: netif_msg should be checked and implemented. I disable it for now */
1923 static int __devinit
1924 bdx_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1926 struct net_device
*ndev
;
1927 struct bdx_priv
*priv
;
1928 int err
, pci_using_dac
, port
;
1929 unsigned long pciaddr
;
1931 struct pci_nic
*nic
;
1935 nic
= vmalloc(sizeof(*nic
));
1939 /************** pci *****************/
1940 if ((err
= pci_enable_device(pdev
))) /* it trigers interrupt, dunno why. */
1941 goto err_pci
; /* it's not a problem though */
1943 if (!(err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(64))) &&
1944 !(err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64)))) {
1947 if ((err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32))) ||
1948 (err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32)))) {
1949 printk(KERN_ERR
"tehuti: No usable DMA configuration"
1956 if ((err
= pci_request_regions(pdev
, BDX_DRV_NAME
)))
1959 pci_set_master(pdev
);
1961 pciaddr
= pci_resource_start(pdev
, 0);
1964 ERR("tehuti: no MMIO resource\n");
1967 if ((regionSize
= pci_resource_len(pdev
, 0)) < BDX_REGS_SIZE
) {
1969 ERR("tehuti: MMIO resource (%x) too small\n", regionSize
);
1973 nic
->regs
= ioremap(pciaddr
, regionSize
);
1976 ERR("tehuti: ioremap failed\n");
1980 if (pdev
->irq
< 2) {
1982 ERR("tehuti: invalid irq (%d)\n", pdev
->irq
);
1985 pci_set_drvdata(pdev
, nic
);
1987 if (pdev
->device
== 0x3014)
1994 bdx_hw_reset_direct(nic
->regs
);
1996 nic
->irq_type
= IRQ_INTX
;
1998 if ((readl(nic
->regs
+ FPGA_VER
) & 0xFFF) >= 378) {
1999 if ((err
= pci_enable_msi(pdev
)))
2000 ERR("Tehuti: Can't eneble msi. error is %d\n", err
);
2002 nic
->irq_type
= IRQ_MSI
;
2004 DBG("HW does not support MSI\n");
2007 /************** netdev **************/
2008 for (port
= 0; port
< nic
->port_num
; port
++) {
2009 if (!(ndev
= alloc_etherdev(sizeof(struct bdx_priv
)))) {
2011 printk(KERN_ERR
"tehuti: alloc_etherdev failed\n");
2015 ndev
->netdev_ops
= &bdx_netdev_ops
;
2016 ndev
->tx_queue_len
= BDX_NDEV_TXQ_LEN
;
2018 bdx_ethtool_ops(ndev
); /* ethtool interface */
2020 /* these fields are used for info purposes only
2021 * so we can have them same for all ports of the board */
2022 ndev
->if_port
= port
;
2023 ndev
->base_addr
= pciaddr
;
2024 ndev
->mem_start
= pciaddr
;
2025 ndev
->mem_end
= pciaddr
+ regionSize
;
2026 ndev
->irq
= pdev
->irq
;
2027 ndev
->features
= NETIF_F_IP_CSUM
| NETIF_F_SG
| NETIF_F_TSO
2028 | NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
|
2029 NETIF_F_HW_VLAN_FILTER
2030 /*| NETIF_F_FRAGLIST */
2034 ndev
->features
|= NETIF_F_HIGHDMA
;
2036 /************** priv ****************/
2037 priv
= nic
->priv
[port
] = netdev_priv(ndev
);
2039 memset(priv
, 0, sizeof(struct bdx_priv
));
2040 priv
->pBdxRegs
= nic
->regs
+ port
* 0x8000;
2045 priv
->msg_enable
= BDX_DEF_MSG_ENABLE
;
2047 netif_napi_add(ndev
, &priv
->napi
, bdx_poll
, 64);
2049 if ((readl(nic
->regs
+ FPGA_VER
) & 0xFFF) == 308) {
2050 DBG("HW statistics not supported\n");
2051 priv
->stats_flag
= 0;
2053 priv
->stats_flag
= 1;
2056 /* Initialize fifo sizes. */
2062 /* Initialize the initial coalescing registers. */
2063 priv
->rdintcm
= INT_REG_VAL(0x20, 1, 4, 12);
2064 priv
->tdintcm
= INT_REG_VAL(0x20, 1, 0, 12);
2066 /* ndev->xmit_lock spinlock is not used.
2067 * Private priv->tx_lock is used for synchronization
2068 * between transmit and TX irq cleanup. In addition
2069 * set multicast list callback has to use priv->tx_lock.
2072 ndev
->features
|= NETIF_F_LLTX
;
2074 spin_lock_init(&priv
->tx_lock
);
2076 /*bdx_hw_reset(priv); */
2077 if (bdx_read_mac(priv
)) {
2078 printk(KERN_ERR
"tehuti: load MAC address failed\n");
2081 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
2082 if ((err
= register_netdev(ndev
))) {
2083 printk(KERN_ERR
"tehuti: register_netdev failed\n");
2086 netif_carrier_off(ndev
);
2087 netif_stop_queue(ndev
);
2098 pci_release_regions(pdev
);
2100 pci_disable_device(pdev
);
2107 /****************** Ethtool interface *********************/
2108 /* get strings for statistics counters */
2110 bdx_stat_names
[][ETH_GSTRING_LEN
] = {
2111 "InUCast", /* 0x7200 */
2112 "InMCast", /* 0x7210 */
2113 "InBCast", /* 0x7220 */
2114 "InPkts", /* 0x7230 */
2115 "InErrors", /* 0x7240 */
2116 "InDropped", /* 0x7250 */
2117 "FrameTooLong", /* 0x7260 */
2118 "FrameSequenceErrors", /* 0x7270 */
2119 "InVLAN", /* 0x7280 */
2120 "InDroppedDFE", /* 0x7290 */
2121 "InDroppedIntFull", /* 0x72A0 */
2122 "InFrameAlignErrors", /* 0x72B0 */
2124 /* 0x72C0-0x72E0 RSRV */
2126 "OutUCast", /* 0x72F0 */
2127 "OutMCast", /* 0x7300 */
2128 "OutBCast", /* 0x7310 */
2129 "OutPkts", /* 0x7320 */
2131 /* 0x7330-0x7360 RSRV */
2133 "OutVLAN", /* 0x7370 */
2134 "InUCastOctects", /* 0x7380 */
2135 "OutUCastOctects", /* 0x7390 */
2137 /* 0x73A0-0x73B0 RSRV */
2139 "InBCastOctects", /* 0x73C0 */
2140 "OutBCastOctects", /* 0x73D0 */
2141 "InOctects", /* 0x73E0 */
2142 "OutOctects", /* 0x73F0 */
2146 * bdx_get_settings - get device-specific settings
2150 static int bdx_get_settings(struct net_device
*netdev
, struct ethtool_cmd
*ecmd
)
2154 struct bdx_priv
*priv
= netdev_priv(netdev
);
2156 rdintcm
= priv
->rdintcm
;
2157 tdintcm
= priv
->tdintcm
;
2159 ecmd
->supported
= (SUPPORTED_10000baseT_Full
| SUPPORTED_FIBRE
);
2160 ecmd
->advertising
= (ADVERTISED_10000baseT_Full
| ADVERTISED_FIBRE
);
2161 ecmd
->speed
= SPEED_10000
;
2162 ecmd
->duplex
= DUPLEX_FULL
;
2163 ecmd
->port
= PORT_FIBRE
;
2164 ecmd
->transceiver
= XCVR_EXTERNAL
; /* what does it mean? */
2165 ecmd
->autoneg
= AUTONEG_DISABLE
;
2167 /* PCK_TH measures in multiples of FIFO bytes
2168 We translate to packets */
2170 ((GET_PCK_TH(tdintcm
) * PCK_TH_MULT
) / BDX_TXF_DESC_SZ
);
2172 ((GET_PCK_TH(rdintcm
) * PCK_TH_MULT
) / sizeof(struct rxf_desc
));
2178 * bdx_get_drvinfo - report driver information
2183 bdx_get_drvinfo(struct net_device
*netdev
, struct ethtool_drvinfo
*drvinfo
)
2185 struct bdx_priv
*priv
= netdev_priv(netdev
);
2187 strlcat(drvinfo
->driver
, BDX_DRV_NAME
, sizeof(drvinfo
->driver
));
2188 strlcat(drvinfo
->version
, BDX_DRV_VERSION
, sizeof(drvinfo
->version
));
2189 strlcat(drvinfo
->fw_version
, "N/A", sizeof(drvinfo
->fw_version
));
2190 strlcat(drvinfo
->bus_info
, pci_name(priv
->pdev
),
2191 sizeof(drvinfo
->bus_info
));
2193 drvinfo
->n_stats
= ((priv
->stats_flag
) ? ARRAY_SIZE(bdx_stat_names
) : 0);
2194 drvinfo
->testinfo_len
= 0;
2195 drvinfo
->regdump_len
= 0;
2196 drvinfo
->eedump_len
= 0;
2200 * bdx_get_rx_csum - report whether receive checksums are turned on or off
2203 static u32
bdx_get_rx_csum(struct net_device
*netdev
)
2205 return 1; /* always on */
2209 * bdx_get_tx_csum - report whether transmit checksums are turned on or off
2212 static u32
bdx_get_tx_csum(struct net_device
*netdev
)
2214 return (netdev
->features
& NETIF_F_IP_CSUM
) != 0;
2218 * bdx_get_coalesce - get interrupt coalescing parameters
2223 bdx_get_coalesce(struct net_device
*netdev
, struct ethtool_coalesce
*ecoal
)
2227 struct bdx_priv
*priv
= netdev_priv(netdev
);
2229 rdintcm
= priv
->rdintcm
;
2230 tdintcm
= priv
->tdintcm
;
2232 /* PCK_TH measures in multiples of FIFO bytes
2233 We translate to packets */
2234 ecoal
->rx_coalesce_usecs
= GET_INT_COAL(rdintcm
) * INT_COAL_MULT
;
2235 ecoal
->rx_max_coalesced_frames
=
2236 ((GET_PCK_TH(rdintcm
) * PCK_TH_MULT
) / sizeof(struct rxf_desc
));
2238 ecoal
->tx_coalesce_usecs
= GET_INT_COAL(tdintcm
) * INT_COAL_MULT
;
2239 ecoal
->tx_max_coalesced_frames
=
2240 ((GET_PCK_TH(tdintcm
) * PCK_TH_MULT
) / BDX_TXF_DESC_SZ
);
2242 /* adaptive parameters ignored */
2247 * bdx_set_coalesce - set interrupt coalescing parameters
2252 bdx_set_coalesce(struct net_device
*netdev
, struct ethtool_coalesce
*ecoal
)
2256 struct bdx_priv
*priv
= netdev_priv(netdev
);
2262 /* Check for valid input */
2263 rx_coal
= ecoal
->rx_coalesce_usecs
/ INT_COAL_MULT
;
2264 tx_coal
= ecoal
->tx_coalesce_usecs
/ INT_COAL_MULT
;
2265 rx_max_coal
= ecoal
->rx_max_coalesced_frames
;
2266 tx_max_coal
= ecoal
->tx_max_coalesced_frames
;
2268 /* Translate from packets to multiples of FIFO bytes */
2270 (((rx_max_coal
* sizeof(struct rxf_desc
)) + PCK_TH_MULT
- 1)
2273 (((tx_max_coal
* BDX_TXF_DESC_SZ
) + PCK_TH_MULT
- 1)
2276 if ((rx_coal
> 0x7FFF) || (tx_coal
> 0x7FFF) ||
2277 (rx_max_coal
> 0xF) || (tx_max_coal
> 0xF))
2280 rdintcm
= INT_REG_VAL(rx_coal
, GET_INT_COAL_RC(priv
->rdintcm
),
2281 GET_RXF_TH(priv
->rdintcm
), rx_max_coal
);
2282 tdintcm
= INT_REG_VAL(tx_coal
, GET_INT_COAL_RC(priv
->tdintcm
), 0,
2285 priv
->rdintcm
= rdintcm
;
2286 priv
->tdintcm
= tdintcm
;
2288 WRITE_REG(priv
, regRDINTCM0
, rdintcm
);
2289 WRITE_REG(priv
, regTDINTCM0
, tdintcm
);
2294 /* Convert RX fifo size to number of pending packets */
2295 static inline int bdx_rx_fifo_size_to_packets(int rx_size
)
2297 return ((FIFO_SIZE
* (1 << rx_size
)) / sizeof(struct rxf_desc
));
2300 /* Convert TX fifo size to number of pending packets */
2301 static inline int bdx_tx_fifo_size_to_packets(int tx_size
)
2303 return ((FIFO_SIZE
* (1 << tx_size
)) / BDX_TXF_DESC_SZ
);
2307 * bdx_get_ringparam - report ring sizes
2312 bdx_get_ringparam(struct net_device
*netdev
, struct ethtool_ringparam
*ring
)
2314 struct bdx_priv
*priv
= netdev_priv(netdev
);
2316 /*max_pending - the maximum-sized FIFO we allow */
2317 ring
->rx_max_pending
= bdx_rx_fifo_size_to_packets(3);
2318 ring
->tx_max_pending
= bdx_tx_fifo_size_to_packets(3);
2319 ring
->rx_pending
= bdx_rx_fifo_size_to_packets(priv
->rxf_size
);
2320 ring
->tx_pending
= bdx_tx_fifo_size_to_packets(priv
->txd_size
);
2324 * bdx_set_ringparam - set ring sizes
2329 bdx_set_ringparam(struct net_device
*netdev
, struct ethtool_ringparam
*ring
)
2331 struct bdx_priv
*priv
= netdev_priv(netdev
);
2335 for (; rx_size
< 4; rx_size
++) {
2336 if (bdx_rx_fifo_size_to_packets(rx_size
) >= ring
->rx_pending
)
2342 for (; tx_size
< 4; tx_size
++) {
2343 if (bdx_tx_fifo_size_to_packets(tx_size
) >= ring
->tx_pending
)
2349 /*Is there anything to do? */
2350 if ((rx_size
== priv
->rxf_size
) &&
2351 (tx_size
== priv
->txd_size
))
2354 priv
->rxf_size
= rx_size
;
2356 priv
->rxd_size
= rx_size
- 1;
2358 priv
->rxd_size
= rx_size
;
2360 priv
->txf_size
= priv
->txd_size
= tx_size
;
2362 if (netif_running(netdev
)) {
2370 * bdx_get_strings - return a set of strings that describe the requested objects
2374 static void bdx_get_strings(struct net_device
*netdev
, u32 stringset
, u8
*data
)
2376 switch (stringset
) {
2378 memcpy(data
, *bdx_stat_names
, sizeof(bdx_stat_names
));
2384 * bdx_get_sset_count - return number of statistics or tests
2387 static int bdx_get_sset_count(struct net_device
*netdev
, int stringset
)
2389 struct bdx_priv
*priv
= netdev_priv(netdev
);
2391 switch (stringset
) {
2393 BDX_ASSERT(ARRAY_SIZE(bdx_stat_names
)
2394 != sizeof(struct bdx_stats
) / sizeof(u64
));
2395 return ((priv
->stats_flag
) ? ARRAY_SIZE(bdx_stat_names
) : 0);
2402 * bdx_get_ethtool_stats - return device's hardware L2 statistics
2407 static void bdx_get_ethtool_stats(struct net_device
*netdev
,
2408 struct ethtool_stats
*stats
, u64
*data
)
2410 struct bdx_priv
*priv
= netdev_priv(netdev
);
2412 if (priv
->stats_flag
) {
2414 /* Update stats from HW */
2415 bdx_update_stats(priv
);
2417 /* Copy data to user buffer */
2418 memcpy(data
, &priv
->hw_stats
, sizeof(priv
->hw_stats
));
2423 * bdx_ethtool_ops - ethtool interface implementation
2426 static void bdx_ethtool_ops(struct net_device
*netdev
)
2428 static const struct ethtool_ops bdx_ethtool_ops
= {
2429 .get_settings
= bdx_get_settings
,
2430 .get_drvinfo
= bdx_get_drvinfo
,
2431 .get_link
= ethtool_op_get_link
,
2432 .get_coalesce
= bdx_get_coalesce
,
2433 .set_coalesce
= bdx_set_coalesce
,
2434 .get_ringparam
= bdx_get_ringparam
,
2435 .set_ringparam
= bdx_set_ringparam
,
2436 .get_rx_csum
= bdx_get_rx_csum
,
2437 .get_tx_csum
= bdx_get_tx_csum
,
2438 .get_sg
= ethtool_op_get_sg
,
2439 .get_tso
= ethtool_op_get_tso
,
2440 .get_strings
= bdx_get_strings
,
2441 .get_sset_count
= bdx_get_sset_count
,
2442 .get_ethtool_stats
= bdx_get_ethtool_stats
,
2445 SET_ETHTOOL_OPS(netdev
, &bdx_ethtool_ops
);
2449 * bdx_remove - Device Removal Routine
2450 * @pdev: PCI device information struct
2452 * bdx_remove is called by the PCI subsystem to alert the driver
2453 * that it should release a PCI device. The could be caused by a
2454 * Hot-Plug event, or because the driver is going to be removed from
2457 static void __devexit
bdx_remove(struct pci_dev
*pdev
)
2459 struct pci_nic
*nic
= pci_get_drvdata(pdev
);
2460 struct net_device
*ndev
;
2463 for (port
= 0; port
< nic
->port_num
; port
++) {
2464 ndev
= nic
->priv
[port
]->ndev
;
2465 unregister_netdev(ndev
);
2469 /*bdx_hw_reset_direct(nic->regs); */
2471 if (nic
->irq_type
== IRQ_MSI
)
2472 pci_disable_msi(pdev
);
2476 pci_release_regions(pdev
);
2477 pci_disable_device(pdev
);
2478 pci_set_drvdata(pdev
, NULL
);
2484 static struct pci_driver bdx_pci_driver
= {
2485 .name
= BDX_DRV_NAME
,
2486 .id_table
= bdx_pci_tbl
,
2488 .remove
= __devexit_p(bdx_remove
),
2492 * print_driver_id - print parameters of the driver build
2494 static void __init
print_driver_id(void)
2496 printk(KERN_INFO
"%s: %s, %s\n", BDX_DRV_NAME
, BDX_DRV_DESC
,
2498 printk(KERN_INFO
"%s: Options: hw_csum %s\n", BDX_DRV_NAME
,
2502 static int __init
bdx_module_init(void)
2507 RET(pci_register_driver(&bdx_pci_driver
));
2510 module_init(bdx_module_init
);
2512 static void __exit
bdx_module_exit(void)
2515 pci_unregister_driver(&bdx_pci_driver
);
2519 module_exit(bdx_module_exit
);
2521 MODULE_LICENSE("GPL");
2522 MODULE_AUTHOR(DRIVER_AUTHOR
);
2523 MODULE_DESCRIPTION(BDX_DRV_DESC
);
2524 MODULE_FIRMWARE("tehuti/firmware.bin");