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[TG3]: Walk PCI capability lists.
[deliverable/linux.git] / drivers / net / tg3.c
1 /*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2007 Broadcom Corporation.
8 *
9 * Firmware is:
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
16 */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
26 #include <linux/in.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/if_vlan.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/workqueue.h>
39 #include <linux/prefetch.h>
40 #include <linux/dma-mapping.h>
41
42 #include <net/checksum.h>
43 #include <net/ip.h>
44
45 #include <asm/system.h>
46 #include <asm/io.h>
47 #include <asm/byteorder.h>
48 #include <asm/uaccess.h>
49
50 #ifdef CONFIG_SPARC
51 #include <asm/idprom.h>
52 #include <asm/prom.h>
53 #endif
54
55 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
56 #define TG3_VLAN_TAG_USED 1
57 #else
58 #define TG3_VLAN_TAG_USED 0
59 #endif
60
61 #define TG3_TSO_SUPPORT 1
62
63 #include "tg3.h"
64
65 #define DRV_MODULE_NAME "tg3"
66 #define PFX DRV_MODULE_NAME ": "
67 #define DRV_MODULE_VERSION "3.81"
68 #define DRV_MODULE_RELDATE "September 5, 2007"
69
70 #define TG3_DEF_MAC_MODE 0
71 #define TG3_DEF_RX_MODE 0
72 #define TG3_DEF_TX_MODE 0
73 #define TG3_DEF_MSG_ENABLE \
74 (NETIF_MSG_DRV | \
75 NETIF_MSG_PROBE | \
76 NETIF_MSG_LINK | \
77 NETIF_MSG_TIMER | \
78 NETIF_MSG_IFDOWN | \
79 NETIF_MSG_IFUP | \
80 NETIF_MSG_RX_ERR | \
81 NETIF_MSG_TX_ERR)
82
83 /* length of time before we decide the hardware is borked,
84 * and dev->tx_timeout() should be called to fix the problem
85 */
86 #define TG3_TX_TIMEOUT (5 * HZ)
87
88 /* hardware minimum and maximum for a single frame's data payload */
89 #define TG3_MIN_MTU 60
90 #define TG3_MAX_MTU(tp) \
91 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
92
93 /* These numbers seem to be hard coded in the NIC firmware somehow.
94 * You can't change the ring sizes, but you can change where you place
95 * them in the NIC onboard memory.
96 */
97 #define TG3_RX_RING_SIZE 512
98 #define TG3_DEF_RX_RING_PENDING 200
99 #define TG3_RX_JUMBO_RING_SIZE 256
100 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
101
102 /* Do not place this n-ring entries value into the tp struct itself,
103 * we really want to expose these constants to GCC so that modulo et
104 * al. operations are done with shifts and masks instead of with
105 * hw multiply/modulo instructions. Another solution would be to
106 * replace things like '% foo' with '& (foo - 1)'.
107 */
108 #define TG3_RX_RCB_RING_SIZE(tp) \
109 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
110
111 #define TG3_TX_RING_SIZE 512
112 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
113
114 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
115 TG3_RX_RING_SIZE)
116 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
117 TG3_RX_JUMBO_RING_SIZE)
118 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_RCB_RING_SIZE(tp))
120 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
121 TG3_TX_RING_SIZE)
122 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
123
124 #define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
125 #define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
126
127 /* minimum number of free TX descriptors required to wake up TX process */
128 #define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
129
130 /* number of ETHTOOL_GSTATS u64's */
131 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
132
133 #define TG3_NUM_TEST 6
134
135 static char version[] __devinitdata =
136 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
137
138 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
139 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
140 MODULE_LICENSE("GPL");
141 MODULE_VERSION(DRV_MODULE_VERSION);
142
143 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
144 module_param(tg3_debug, int, 0);
145 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
146
147 static struct pci_device_id tg3_pci_tbl[] = {
148 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
149 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
150 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
151 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
152 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
153 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
154 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
155 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
156 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
157 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
158 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
159 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
160 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
161 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
162 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
163 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
164 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
165 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
166 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
167 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
168 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
201 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
202 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
203 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
204 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
205 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
206 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
207 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
208 {}
209 };
210
211 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
212
213 static const struct {
214 const char string[ETH_GSTRING_LEN];
215 } ethtool_stats_keys[TG3_NUM_STATS] = {
216 { "rx_octets" },
217 { "rx_fragments" },
218 { "rx_ucast_packets" },
219 { "rx_mcast_packets" },
220 { "rx_bcast_packets" },
221 { "rx_fcs_errors" },
222 { "rx_align_errors" },
223 { "rx_xon_pause_rcvd" },
224 { "rx_xoff_pause_rcvd" },
225 { "rx_mac_ctrl_rcvd" },
226 { "rx_xoff_entered" },
227 { "rx_frame_too_long_errors" },
228 { "rx_jabbers" },
229 { "rx_undersize_packets" },
230 { "rx_in_length_errors" },
231 { "rx_out_length_errors" },
232 { "rx_64_or_less_octet_packets" },
233 { "rx_65_to_127_octet_packets" },
234 { "rx_128_to_255_octet_packets" },
235 { "rx_256_to_511_octet_packets" },
236 { "rx_512_to_1023_octet_packets" },
237 { "rx_1024_to_1522_octet_packets" },
238 { "rx_1523_to_2047_octet_packets" },
239 { "rx_2048_to_4095_octet_packets" },
240 { "rx_4096_to_8191_octet_packets" },
241 { "rx_8192_to_9022_octet_packets" },
242
243 { "tx_octets" },
244 { "tx_collisions" },
245
246 { "tx_xon_sent" },
247 { "tx_xoff_sent" },
248 { "tx_flow_control" },
249 { "tx_mac_errors" },
250 { "tx_single_collisions" },
251 { "tx_mult_collisions" },
252 { "tx_deferred" },
253 { "tx_excessive_collisions" },
254 { "tx_late_collisions" },
255 { "tx_collide_2times" },
256 { "tx_collide_3times" },
257 { "tx_collide_4times" },
258 { "tx_collide_5times" },
259 { "tx_collide_6times" },
260 { "tx_collide_7times" },
261 { "tx_collide_8times" },
262 { "tx_collide_9times" },
263 { "tx_collide_10times" },
264 { "tx_collide_11times" },
265 { "tx_collide_12times" },
266 { "tx_collide_13times" },
267 { "tx_collide_14times" },
268 { "tx_collide_15times" },
269 { "tx_ucast_packets" },
270 { "tx_mcast_packets" },
271 { "tx_bcast_packets" },
272 { "tx_carrier_sense_errors" },
273 { "tx_discards" },
274 { "tx_errors" },
275
276 { "dma_writeq_full" },
277 { "dma_write_prioq_full" },
278 { "rxbds_empty" },
279 { "rx_discards" },
280 { "rx_errors" },
281 { "rx_threshold_hit" },
282
283 { "dma_readq_full" },
284 { "dma_read_prioq_full" },
285 { "tx_comp_queue_full" },
286
287 { "ring_set_send_prod_index" },
288 { "ring_status_update" },
289 { "nic_irqs" },
290 { "nic_avoided_irqs" },
291 { "nic_tx_threshold_hit" }
292 };
293
294 static const struct {
295 const char string[ETH_GSTRING_LEN];
296 } ethtool_test_keys[TG3_NUM_TEST] = {
297 { "nvram test (online) " },
298 { "link test (online) " },
299 { "register test (offline)" },
300 { "memory test (offline)" },
301 { "loopback test (offline)" },
302 { "interrupt test (offline)" },
303 };
304
305 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
306 {
307 writel(val, tp->regs + off);
308 }
309
310 static u32 tg3_read32(struct tg3 *tp, u32 off)
311 {
312 return (readl(tp->regs + off));
313 }
314
315 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
316 {
317 unsigned long flags;
318
319 spin_lock_irqsave(&tp->indirect_lock, flags);
320 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
321 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
322 spin_unlock_irqrestore(&tp->indirect_lock, flags);
323 }
324
325 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
326 {
327 writel(val, tp->regs + off);
328 readl(tp->regs + off);
329 }
330
331 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
332 {
333 unsigned long flags;
334 u32 val;
335
336 spin_lock_irqsave(&tp->indirect_lock, flags);
337 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
338 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
339 spin_unlock_irqrestore(&tp->indirect_lock, flags);
340 return val;
341 }
342
343 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
344 {
345 unsigned long flags;
346
347 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
348 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
349 TG3_64BIT_REG_LOW, val);
350 return;
351 }
352 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
353 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
354 TG3_64BIT_REG_LOW, val);
355 return;
356 }
357
358 spin_lock_irqsave(&tp->indirect_lock, flags);
359 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
360 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
361 spin_unlock_irqrestore(&tp->indirect_lock, flags);
362
363 /* In indirect mode when disabling interrupts, we also need
364 * to clear the interrupt bit in the GRC local ctrl register.
365 */
366 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
367 (val == 0x1)) {
368 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
369 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
370 }
371 }
372
373 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
374 {
375 unsigned long flags;
376 u32 val;
377
378 spin_lock_irqsave(&tp->indirect_lock, flags);
379 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
380 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
381 spin_unlock_irqrestore(&tp->indirect_lock, flags);
382 return val;
383 }
384
385 /* usec_wait specifies the wait time in usec when writing to certain registers
386 * where it is unsafe to read back the register without some delay.
387 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
388 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
389 */
390 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
391 {
392 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
393 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
394 /* Non-posted methods */
395 tp->write32(tp, off, val);
396 else {
397 /* Posted method */
398 tg3_write32(tp, off, val);
399 if (usec_wait)
400 udelay(usec_wait);
401 tp->read32(tp, off);
402 }
403 /* Wait again after the read for the posted method to guarantee that
404 * the wait time is met.
405 */
406 if (usec_wait)
407 udelay(usec_wait);
408 }
409
410 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
411 {
412 tp->write32_mbox(tp, off, val);
413 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
414 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
415 tp->read32_mbox(tp, off);
416 }
417
418 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
419 {
420 void __iomem *mbox = tp->regs + off;
421 writel(val, mbox);
422 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
423 writel(val, mbox);
424 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
425 readl(mbox);
426 }
427
428 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
429 {
430 return (readl(tp->regs + off + GRCMBOX_BASE));
431 }
432
433 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
434 {
435 writel(val, tp->regs + off + GRCMBOX_BASE);
436 }
437
438 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
439 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
440 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
441 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
442 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
443
444 #define tw32(reg,val) tp->write32(tp, reg, val)
445 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
446 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
447 #define tr32(reg) tp->read32(tp, reg)
448
449 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
450 {
451 unsigned long flags;
452
453 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
454 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
455 return;
456
457 spin_lock_irqsave(&tp->indirect_lock, flags);
458 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
459 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
460 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
461
462 /* Always leave this as zero. */
463 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
464 } else {
465 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
466 tw32_f(TG3PCI_MEM_WIN_DATA, val);
467
468 /* Always leave this as zero. */
469 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
470 }
471 spin_unlock_irqrestore(&tp->indirect_lock, flags);
472 }
473
474 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
475 {
476 unsigned long flags;
477
478 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
479 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
480 *val = 0;
481 return;
482 }
483
484 spin_lock_irqsave(&tp->indirect_lock, flags);
485 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
486 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
487 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
488
489 /* Always leave this as zero. */
490 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
491 } else {
492 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
493 *val = tr32(TG3PCI_MEM_WIN_DATA);
494
495 /* Always leave this as zero. */
496 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
497 }
498 spin_unlock_irqrestore(&tp->indirect_lock, flags);
499 }
500
501 static void tg3_disable_ints(struct tg3 *tp)
502 {
503 tw32(TG3PCI_MISC_HOST_CTRL,
504 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
505 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
506 }
507
508 static inline void tg3_cond_int(struct tg3 *tp)
509 {
510 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
511 (tp->hw_status->status & SD_STATUS_UPDATED))
512 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
513 else
514 tw32(HOSTCC_MODE, tp->coalesce_mode |
515 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
516 }
517
518 static void tg3_enable_ints(struct tg3 *tp)
519 {
520 tp->irq_sync = 0;
521 wmb();
522
523 tw32(TG3PCI_MISC_HOST_CTRL,
524 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
525 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
526 (tp->last_tag << 24));
527 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
528 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
529 (tp->last_tag << 24));
530 tg3_cond_int(tp);
531 }
532
533 static inline unsigned int tg3_has_work(struct tg3 *tp)
534 {
535 struct tg3_hw_status *sblk = tp->hw_status;
536 unsigned int work_exists = 0;
537
538 /* check for phy events */
539 if (!(tp->tg3_flags &
540 (TG3_FLAG_USE_LINKCHG_REG |
541 TG3_FLAG_POLL_SERDES))) {
542 if (sblk->status & SD_STATUS_LINK_CHG)
543 work_exists = 1;
544 }
545 /* check for RX/TX work to do */
546 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
547 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
548 work_exists = 1;
549
550 return work_exists;
551 }
552
553 /* tg3_restart_ints
554 * similar to tg3_enable_ints, but it accurately determines whether there
555 * is new work pending and can return without flushing the PIO write
556 * which reenables interrupts
557 */
558 static void tg3_restart_ints(struct tg3 *tp)
559 {
560 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
561 tp->last_tag << 24);
562 mmiowb();
563
564 /* When doing tagged status, this work check is unnecessary.
565 * The last_tag we write above tells the chip which piece of
566 * work we've completed.
567 */
568 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
569 tg3_has_work(tp))
570 tw32(HOSTCC_MODE, tp->coalesce_mode |
571 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
572 }
573
574 static inline void tg3_netif_stop(struct tg3 *tp)
575 {
576 tp->dev->trans_start = jiffies; /* prevent tx timeout */
577 napi_disable(&tp->napi);
578 netif_tx_disable(tp->dev);
579 }
580
581 static inline void tg3_netif_start(struct tg3 *tp)
582 {
583 netif_wake_queue(tp->dev);
584 /* NOTE: unconditional netif_wake_queue is only appropriate
585 * so long as all callers are assured to have free tx slots
586 * (such as after tg3_init_hw)
587 */
588 napi_enable(&tp->napi);
589 tp->hw_status->status |= SD_STATUS_UPDATED;
590 tg3_enable_ints(tp);
591 }
592
593 static void tg3_switch_clocks(struct tg3 *tp)
594 {
595 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
596 u32 orig_clock_ctrl;
597
598 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
599 return;
600
601 orig_clock_ctrl = clock_ctrl;
602 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
603 CLOCK_CTRL_CLKRUN_OENABLE |
604 0x1f);
605 tp->pci_clock_ctrl = clock_ctrl;
606
607 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
608 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
609 tw32_wait_f(TG3PCI_CLOCK_CTRL,
610 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
611 }
612 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
613 tw32_wait_f(TG3PCI_CLOCK_CTRL,
614 clock_ctrl |
615 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
616 40);
617 tw32_wait_f(TG3PCI_CLOCK_CTRL,
618 clock_ctrl | (CLOCK_CTRL_ALTCLK),
619 40);
620 }
621 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
622 }
623
624 #define PHY_BUSY_LOOPS 5000
625
626 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
627 {
628 u32 frame_val;
629 unsigned int loops;
630 int ret;
631
632 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
633 tw32_f(MAC_MI_MODE,
634 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
635 udelay(80);
636 }
637
638 *val = 0x0;
639
640 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
641 MI_COM_PHY_ADDR_MASK);
642 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
643 MI_COM_REG_ADDR_MASK);
644 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
645
646 tw32_f(MAC_MI_COM, frame_val);
647
648 loops = PHY_BUSY_LOOPS;
649 while (loops != 0) {
650 udelay(10);
651 frame_val = tr32(MAC_MI_COM);
652
653 if ((frame_val & MI_COM_BUSY) == 0) {
654 udelay(5);
655 frame_val = tr32(MAC_MI_COM);
656 break;
657 }
658 loops -= 1;
659 }
660
661 ret = -EBUSY;
662 if (loops != 0) {
663 *val = frame_val & MI_COM_DATA_MASK;
664 ret = 0;
665 }
666
667 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
668 tw32_f(MAC_MI_MODE, tp->mi_mode);
669 udelay(80);
670 }
671
672 return ret;
673 }
674
675 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
676 {
677 u32 frame_val;
678 unsigned int loops;
679 int ret;
680
681 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
682 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
683 return 0;
684
685 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
686 tw32_f(MAC_MI_MODE,
687 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
688 udelay(80);
689 }
690
691 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
692 MI_COM_PHY_ADDR_MASK);
693 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
694 MI_COM_REG_ADDR_MASK);
695 frame_val |= (val & MI_COM_DATA_MASK);
696 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
697
698 tw32_f(MAC_MI_COM, frame_val);
699
700 loops = PHY_BUSY_LOOPS;
701 while (loops != 0) {
702 udelay(10);
703 frame_val = tr32(MAC_MI_COM);
704 if ((frame_val & MI_COM_BUSY) == 0) {
705 udelay(5);
706 frame_val = tr32(MAC_MI_COM);
707 break;
708 }
709 loops -= 1;
710 }
711
712 ret = -EBUSY;
713 if (loops != 0)
714 ret = 0;
715
716 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
717 tw32_f(MAC_MI_MODE, tp->mi_mode);
718 udelay(80);
719 }
720
721 return ret;
722 }
723
724 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
725 {
726 u32 phy;
727
728 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
729 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
730 return;
731
732 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
733 u32 ephy;
734
735 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
736 tg3_writephy(tp, MII_TG3_EPHY_TEST,
737 ephy | MII_TG3_EPHY_SHADOW_EN);
738 if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
739 if (enable)
740 phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
741 else
742 phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
743 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
744 }
745 tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
746 }
747 } else {
748 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
749 MII_TG3_AUXCTL_SHDWSEL_MISC;
750 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
751 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
752 if (enable)
753 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
754 else
755 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
756 phy |= MII_TG3_AUXCTL_MISC_WREN;
757 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
758 }
759 }
760 }
761
762 static void tg3_phy_set_wirespeed(struct tg3 *tp)
763 {
764 u32 val;
765
766 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
767 return;
768
769 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
770 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
771 tg3_writephy(tp, MII_TG3_AUX_CTRL,
772 (val | (1 << 15) | (1 << 4)));
773 }
774
775 static int tg3_bmcr_reset(struct tg3 *tp)
776 {
777 u32 phy_control;
778 int limit, err;
779
780 /* OK, reset it, and poll the BMCR_RESET bit until it
781 * clears or we time out.
782 */
783 phy_control = BMCR_RESET;
784 err = tg3_writephy(tp, MII_BMCR, phy_control);
785 if (err != 0)
786 return -EBUSY;
787
788 limit = 5000;
789 while (limit--) {
790 err = tg3_readphy(tp, MII_BMCR, &phy_control);
791 if (err != 0)
792 return -EBUSY;
793
794 if ((phy_control & BMCR_RESET) == 0) {
795 udelay(40);
796 break;
797 }
798 udelay(10);
799 }
800 if (limit <= 0)
801 return -EBUSY;
802
803 return 0;
804 }
805
806 static int tg3_wait_macro_done(struct tg3 *tp)
807 {
808 int limit = 100;
809
810 while (limit--) {
811 u32 tmp32;
812
813 if (!tg3_readphy(tp, 0x16, &tmp32)) {
814 if ((tmp32 & 0x1000) == 0)
815 break;
816 }
817 }
818 if (limit <= 0)
819 return -EBUSY;
820
821 return 0;
822 }
823
824 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
825 {
826 static const u32 test_pat[4][6] = {
827 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
828 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
829 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
830 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
831 };
832 int chan;
833
834 for (chan = 0; chan < 4; chan++) {
835 int i;
836
837 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
838 (chan * 0x2000) | 0x0200);
839 tg3_writephy(tp, 0x16, 0x0002);
840
841 for (i = 0; i < 6; i++)
842 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
843 test_pat[chan][i]);
844
845 tg3_writephy(tp, 0x16, 0x0202);
846 if (tg3_wait_macro_done(tp)) {
847 *resetp = 1;
848 return -EBUSY;
849 }
850
851 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
852 (chan * 0x2000) | 0x0200);
853 tg3_writephy(tp, 0x16, 0x0082);
854 if (tg3_wait_macro_done(tp)) {
855 *resetp = 1;
856 return -EBUSY;
857 }
858
859 tg3_writephy(tp, 0x16, 0x0802);
860 if (tg3_wait_macro_done(tp)) {
861 *resetp = 1;
862 return -EBUSY;
863 }
864
865 for (i = 0; i < 6; i += 2) {
866 u32 low, high;
867
868 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
869 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
870 tg3_wait_macro_done(tp)) {
871 *resetp = 1;
872 return -EBUSY;
873 }
874 low &= 0x7fff;
875 high &= 0x000f;
876 if (low != test_pat[chan][i] ||
877 high != test_pat[chan][i+1]) {
878 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
879 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
880 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
881
882 return -EBUSY;
883 }
884 }
885 }
886
887 return 0;
888 }
889
890 static int tg3_phy_reset_chanpat(struct tg3 *tp)
891 {
892 int chan;
893
894 for (chan = 0; chan < 4; chan++) {
895 int i;
896
897 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
898 (chan * 0x2000) | 0x0200);
899 tg3_writephy(tp, 0x16, 0x0002);
900 for (i = 0; i < 6; i++)
901 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
902 tg3_writephy(tp, 0x16, 0x0202);
903 if (tg3_wait_macro_done(tp))
904 return -EBUSY;
905 }
906
907 return 0;
908 }
909
910 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
911 {
912 u32 reg32, phy9_orig;
913 int retries, do_phy_reset, err;
914
915 retries = 10;
916 do_phy_reset = 1;
917 do {
918 if (do_phy_reset) {
919 err = tg3_bmcr_reset(tp);
920 if (err)
921 return err;
922 do_phy_reset = 0;
923 }
924
925 /* Disable transmitter and interrupt. */
926 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
927 continue;
928
929 reg32 |= 0x3000;
930 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
931
932 /* Set full-duplex, 1000 mbps. */
933 tg3_writephy(tp, MII_BMCR,
934 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
935
936 /* Set to master mode. */
937 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
938 continue;
939
940 tg3_writephy(tp, MII_TG3_CTRL,
941 (MII_TG3_CTRL_AS_MASTER |
942 MII_TG3_CTRL_ENABLE_AS_MASTER));
943
944 /* Enable SM_DSP_CLOCK and 6dB. */
945 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
946
947 /* Block the PHY control access. */
948 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
949 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
950
951 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
952 if (!err)
953 break;
954 } while (--retries);
955
956 err = tg3_phy_reset_chanpat(tp);
957 if (err)
958 return err;
959
960 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
961 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
962
963 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
964 tg3_writephy(tp, 0x16, 0x0000);
965
966 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
967 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
968 /* Set Extended packet length bit for jumbo frames */
969 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
970 }
971 else {
972 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
973 }
974
975 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
976
977 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
978 reg32 &= ~0x3000;
979 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
980 } else if (!err)
981 err = -EBUSY;
982
983 return err;
984 }
985
986 static void tg3_link_report(struct tg3 *);
987
988 /* This will reset the tigon3 PHY if there is no valid
989 * link unless the FORCE argument is non-zero.
990 */
991 static int tg3_phy_reset(struct tg3 *tp)
992 {
993 u32 phy_status;
994 int err;
995
996 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
997 u32 val;
998
999 val = tr32(GRC_MISC_CFG);
1000 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1001 udelay(40);
1002 }
1003 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1004 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1005 if (err != 0)
1006 return -EBUSY;
1007
1008 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1009 netif_carrier_off(tp->dev);
1010 tg3_link_report(tp);
1011 }
1012
1013 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1014 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1015 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1016 err = tg3_phy_reset_5703_4_5(tp);
1017 if (err)
1018 return err;
1019 goto out;
1020 }
1021
1022 err = tg3_bmcr_reset(tp);
1023 if (err)
1024 return err;
1025
1026 out:
1027 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1028 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1029 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1030 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1031 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1032 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1033 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1034 }
1035 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1036 tg3_writephy(tp, 0x1c, 0x8d68);
1037 tg3_writephy(tp, 0x1c, 0x8d68);
1038 }
1039 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1040 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1041 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1042 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1043 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1044 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1045 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1046 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1047 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1048 }
1049 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1050 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1051 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1052 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1053 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1054 tg3_writephy(tp, MII_TG3_TEST1,
1055 MII_TG3_TEST1_TRIM_EN | 0x4);
1056 } else
1057 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1058 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1059 }
1060 /* Set Extended packet length bit (bit 14) on all chips that */
1061 /* support jumbo frames */
1062 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1063 /* Cannot do read-modify-write on 5401 */
1064 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1065 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1066 u32 phy_reg;
1067
1068 /* Set bit 14 with read-modify-write to preserve other bits */
1069 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1070 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1071 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1072 }
1073
1074 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1075 * jumbo frames transmission.
1076 */
1077 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1078 u32 phy_reg;
1079
1080 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1081 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1082 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1083 }
1084
1085 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1086 /* adjust output voltage */
1087 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1088 }
1089
1090 tg3_phy_toggle_automdix(tp, 1);
1091 tg3_phy_set_wirespeed(tp);
1092 return 0;
1093 }
1094
1095 static void tg3_frob_aux_power(struct tg3 *tp)
1096 {
1097 struct tg3 *tp_peer = tp;
1098
1099 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1100 return;
1101
1102 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1103 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1104 struct net_device *dev_peer;
1105
1106 dev_peer = pci_get_drvdata(tp->pdev_peer);
1107 /* remove_one() may have been run on the peer. */
1108 if (!dev_peer)
1109 tp_peer = tp;
1110 else
1111 tp_peer = netdev_priv(dev_peer);
1112 }
1113
1114 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1115 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1116 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1117 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1118 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1119 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1120 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1121 (GRC_LCLCTRL_GPIO_OE0 |
1122 GRC_LCLCTRL_GPIO_OE1 |
1123 GRC_LCLCTRL_GPIO_OE2 |
1124 GRC_LCLCTRL_GPIO_OUTPUT0 |
1125 GRC_LCLCTRL_GPIO_OUTPUT1),
1126 100);
1127 } else {
1128 u32 no_gpio2;
1129 u32 grc_local_ctrl = 0;
1130
1131 if (tp_peer != tp &&
1132 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1133 return;
1134
1135 /* Workaround to prevent overdrawing Amps. */
1136 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1137 ASIC_REV_5714) {
1138 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1139 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1140 grc_local_ctrl, 100);
1141 }
1142
1143 /* On 5753 and variants, GPIO2 cannot be used. */
1144 no_gpio2 = tp->nic_sram_data_cfg &
1145 NIC_SRAM_DATA_CFG_NO_GPIO2;
1146
1147 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1148 GRC_LCLCTRL_GPIO_OE1 |
1149 GRC_LCLCTRL_GPIO_OE2 |
1150 GRC_LCLCTRL_GPIO_OUTPUT1 |
1151 GRC_LCLCTRL_GPIO_OUTPUT2;
1152 if (no_gpio2) {
1153 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1154 GRC_LCLCTRL_GPIO_OUTPUT2);
1155 }
1156 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1157 grc_local_ctrl, 100);
1158
1159 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1160
1161 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1162 grc_local_ctrl, 100);
1163
1164 if (!no_gpio2) {
1165 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1166 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1167 grc_local_ctrl, 100);
1168 }
1169 }
1170 } else {
1171 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1172 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1173 if (tp_peer != tp &&
1174 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1175 return;
1176
1177 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1178 (GRC_LCLCTRL_GPIO_OE1 |
1179 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1180
1181 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1182 GRC_LCLCTRL_GPIO_OE1, 100);
1183
1184 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1185 (GRC_LCLCTRL_GPIO_OE1 |
1186 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1187 }
1188 }
1189 }
1190
1191 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
1192 {
1193 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
1194 return 1;
1195 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
1196 if (speed != SPEED_10)
1197 return 1;
1198 } else if (speed == SPEED_10)
1199 return 1;
1200
1201 return 0;
1202 }
1203
1204 static int tg3_setup_phy(struct tg3 *, int);
1205
1206 #define RESET_KIND_SHUTDOWN 0
1207 #define RESET_KIND_INIT 1
1208 #define RESET_KIND_SUSPEND 2
1209
1210 static void tg3_write_sig_post_reset(struct tg3 *, int);
1211 static int tg3_halt_cpu(struct tg3 *, u32);
1212 static int tg3_nvram_lock(struct tg3 *);
1213 static void tg3_nvram_unlock(struct tg3 *);
1214
1215 static void tg3_power_down_phy(struct tg3 *tp)
1216 {
1217 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1218 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1219 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
1220 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
1221
1222 sg_dig_ctrl |=
1223 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
1224 tw32(SG_DIG_CTRL, sg_dig_ctrl);
1225 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
1226 }
1227 return;
1228 }
1229
1230 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1231 u32 val;
1232
1233 tg3_bmcr_reset(tp);
1234 val = tr32(GRC_MISC_CFG);
1235 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1236 udelay(40);
1237 return;
1238 } else {
1239 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1240 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1241 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1242 }
1243
1244 /* The PHY should not be powered down on some chips because
1245 * of bugs.
1246 */
1247 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1248 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1249 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1250 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1251 return;
1252 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1253 }
1254
1255 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1256 {
1257 u32 misc_host_ctrl;
1258 u16 power_control, power_caps;
1259 int pm = tp->pm_cap;
1260
1261 /* Make sure register accesses (indirect or otherwise)
1262 * will function correctly.
1263 */
1264 pci_write_config_dword(tp->pdev,
1265 TG3PCI_MISC_HOST_CTRL,
1266 tp->misc_host_ctrl);
1267
1268 pci_read_config_word(tp->pdev,
1269 pm + PCI_PM_CTRL,
1270 &power_control);
1271 power_control |= PCI_PM_CTRL_PME_STATUS;
1272 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1273 switch (state) {
1274 case PCI_D0:
1275 power_control |= 0;
1276 pci_write_config_word(tp->pdev,
1277 pm + PCI_PM_CTRL,
1278 power_control);
1279 udelay(100); /* Delay after power state change */
1280
1281 /* Switch out of Vaux if it is a NIC */
1282 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
1283 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1284
1285 return 0;
1286
1287 case PCI_D1:
1288 power_control |= 1;
1289 break;
1290
1291 case PCI_D2:
1292 power_control |= 2;
1293 break;
1294
1295 case PCI_D3hot:
1296 power_control |= 3;
1297 break;
1298
1299 default:
1300 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1301 "requested.\n",
1302 tp->dev->name, state);
1303 return -EINVAL;
1304 };
1305
1306 power_control |= PCI_PM_CTRL_PME_ENABLE;
1307
1308 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1309 tw32(TG3PCI_MISC_HOST_CTRL,
1310 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1311
1312 if (tp->link_config.phy_is_low_power == 0) {
1313 tp->link_config.phy_is_low_power = 1;
1314 tp->link_config.orig_speed = tp->link_config.speed;
1315 tp->link_config.orig_duplex = tp->link_config.duplex;
1316 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1317 }
1318
1319 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1320 tp->link_config.speed = SPEED_10;
1321 tp->link_config.duplex = DUPLEX_HALF;
1322 tp->link_config.autoneg = AUTONEG_ENABLE;
1323 tg3_setup_phy(tp, 0);
1324 }
1325
1326 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1327 u32 val;
1328
1329 val = tr32(GRC_VCPU_EXT_CTRL);
1330 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1331 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1332 int i;
1333 u32 val;
1334
1335 for (i = 0; i < 200; i++) {
1336 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1337 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1338 break;
1339 msleep(1);
1340 }
1341 }
1342 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
1343 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1344 WOL_DRV_STATE_SHUTDOWN |
1345 WOL_DRV_WOL |
1346 WOL_SET_MAGIC_PKT);
1347
1348 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1349
1350 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1351 u32 mac_mode;
1352
1353 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1354 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1355 udelay(40);
1356
1357 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1358 mac_mode = MAC_MODE_PORT_MODE_GMII;
1359 else
1360 mac_mode = MAC_MODE_PORT_MODE_MII;
1361
1362 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
1363 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1364 ASIC_REV_5700) {
1365 u32 speed = (tp->tg3_flags &
1366 TG3_FLAG_WOL_SPEED_100MB) ?
1367 SPEED_100 : SPEED_10;
1368 if (tg3_5700_link_polarity(tp, speed))
1369 mac_mode |= MAC_MODE_LINK_POLARITY;
1370 else
1371 mac_mode &= ~MAC_MODE_LINK_POLARITY;
1372 }
1373 } else {
1374 mac_mode = MAC_MODE_PORT_MODE_TBI;
1375 }
1376
1377 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1378 tw32(MAC_LED_CTRL, tp->led_ctrl);
1379
1380 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1381 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1382 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1383
1384 tw32_f(MAC_MODE, mac_mode);
1385 udelay(100);
1386
1387 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1388 udelay(10);
1389 }
1390
1391 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1392 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1393 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1394 u32 base_val;
1395
1396 base_val = tp->pci_clock_ctrl;
1397 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1398 CLOCK_CTRL_TXCLK_DISABLE);
1399
1400 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1401 CLOCK_CTRL_PWRDOWN_PLL133, 40);
1402 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1403 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
1404 /* do nothing */
1405 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1406 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1407 u32 newbits1, newbits2;
1408
1409 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1410 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1411 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1412 CLOCK_CTRL_TXCLK_DISABLE |
1413 CLOCK_CTRL_ALTCLK);
1414 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1415 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1416 newbits1 = CLOCK_CTRL_625_CORE;
1417 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1418 } else {
1419 newbits1 = CLOCK_CTRL_ALTCLK;
1420 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1421 }
1422
1423 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1424 40);
1425
1426 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1427 40);
1428
1429 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1430 u32 newbits3;
1431
1432 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1433 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1434 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1435 CLOCK_CTRL_TXCLK_DISABLE |
1436 CLOCK_CTRL_44MHZ_CORE);
1437 } else {
1438 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1439 }
1440
1441 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1442 tp->pci_clock_ctrl | newbits3, 40);
1443 }
1444 }
1445
1446 if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1447 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1448 tg3_power_down_phy(tp);
1449
1450 tg3_frob_aux_power(tp);
1451
1452 /* Workaround for unstable PLL clock */
1453 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1454 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1455 u32 val = tr32(0x7d00);
1456
1457 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1458 tw32(0x7d00, val);
1459 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1460 int err;
1461
1462 err = tg3_nvram_lock(tp);
1463 tg3_halt_cpu(tp, RX_CPU_BASE);
1464 if (!err)
1465 tg3_nvram_unlock(tp);
1466 }
1467 }
1468
1469 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1470
1471 /* Finally, set the new power state. */
1472 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1473 udelay(100); /* Delay after power state change */
1474
1475 return 0;
1476 }
1477
1478 static void tg3_link_report(struct tg3 *tp)
1479 {
1480 if (!netif_carrier_ok(tp->dev)) {
1481 if (netif_msg_link(tp))
1482 printk(KERN_INFO PFX "%s: Link is down.\n",
1483 tp->dev->name);
1484 } else if (netif_msg_link(tp)) {
1485 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1486 tp->dev->name,
1487 (tp->link_config.active_speed == SPEED_1000 ?
1488 1000 :
1489 (tp->link_config.active_speed == SPEED_100 ?
1490 100 : 10)),
1491 (tp->link_config.active_duplex == DUPLEX_FULL ?
1492 "full" : "half"));
1493
1494 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1495 "%s for RX.\n",
1496 tp->dev->name,
1497 (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1498 (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1499 }
1500 }
1501
1502 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1503 {
1504 u32 new_tg3_flags = 0;
1505 u32 old_rx_mode = tp->rx_mode;
1506 u32 old_tx_mode = tp->tx_mode;
1507
1508 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1509
1510 /* Convert 1000BaseX flow control bits to 1000BaseT
1511 * bits before resolving flow control.
1512 */
1513 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1514 local_adv &= ~(ADVERTISE_PAUSE_CAP |
1515 ADVERTISE_PAUSE_ASYM);
1516 remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1517
1518 if (local_adv & ADVERTISE_1000XPAUSE)
1519 local_adv |= ADVERTISE_PAUSE_CAP;
1520 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1521 local_adv |= ADVERTISE_PAUSE_ASYM;
1522 if (remote_adv & LPA_1000XPAUSE)
1523 remote_adv |= LPA_PAUSE_CAP;
1524 if (remote_adv & LPA_1000XPAUSE_ASYM)
1525 remote_adv |= LPA_PAUSE_ASYM;
1526 }
1527
1528 if (local_adv & ADVERTISE_PAUSE_CAP) {
1529 if (local_adv & ADVERTISE_PAUSE_ASYM) {
1530 if (remote_adv & LPA_PAUSE_CAP)
1531 new_tg3_flags |=
1532 (TG3_FLAG_RX_PAUSE |
1533 TG3_FLAG_TX_PAUSE);
1534 else if (remote_adv & LPA_PAUSE_ASYM)
1535 new_tg3_flags |=
1536 (TG3_FLAG_RX_PAUSE);
1537 } else {
1538 if (remote_adv & LPA_PAUSE_CAP)
1539 new_tg3_flags |=
1540 (TG3_FLAG_RX_PAUSE |
1541 TG3_FLAG_TX_PAUSE);
1542 }
1543 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1544 if ((remote_adv & LPA_PAUSE_CAP) &&
1545 (remote_adv & LPA_PAUSE_ASYM))
1546 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1547 }
1548
1549 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1550 tp->tg3_flags |= new_tg3_flags;
1551 } else {
1552 new_tg3_flags = tp->tg3_flags;
1553 }
1554
1555 if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1556 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1557 else
1558 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1559
1560 if (old_rx_mode != tp->rx_mode) {
1561 tw32_f(MAC_RX_MODE, tp->rx_mode);
1562 }
1563
1564 if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1565 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1566 else
1567 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1568
1569 if (old_tx_mode != tp->tx_mode) {
1570 tw32_f(MAC_TX_MODE, tp->tx_mode);
1571 }
1572 }
1573
1574 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1575 {
1576 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1577 case MII_TG3_AUX_STAT_10HALF:
1578 *speed = SPEED_10;
1579 *duplex = DUPLEX_HALF;
1580 break;
1581
1582 case MII_TG3_AUX_STAT_10FULL:
1583 *speed = SPEED_10;
1584 *duplex = DUPLEX_FULL;
1585 break;
1586
1587 case MII_TG3_AUX_STAT_100HALF:
1588 *speed = SPEED_100;
1589 *duplex = DUPLEX_HALF;
1590 break;
1591
1592 case MII_TG3_AUX_STAT_100FULL:
1593 *speed = SPEED_100;
1594 *duplex = DUPLEX_FULL;
1595 break;
1596
1597 case MII_TG3_AUX_STAT_1000HALF:
1598 *speed = SPEED_1000;
1599 *duplex = DUPLEX_HALF;
1600 break;
1601
1602 case MII_TG3_AUX_STAT_1000FULL:
1603 *speed = SPEED_1000;
1604 *duplex = DUPLEX_FULL;
1605 break;
1606
1607 default:
1608 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1609 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1610 SPEED_10;
1611 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1612 DUPLEX_HALF;
1613 break;
1614 }
1615 *speed = SPEED_INVALID;
1616 *duplex = DUPLEX_INVALID;
1617 break;
1618 };
1619 }
1620
1621 static void tg3_phy_copper_begin(struct tg3 *tp)
1622 {
1623 u32 new_adv;
1624 int i;
1625
1626 if (tp->link_config.phy_is_low_power) {
1627 /* Entering low power mode. Disable gigabit and
1628 * 100baseT advertisements.
1629 */
1630 tg3_writephy(tp, MII_TG3_CTRL, 0);
1631
1632 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1633 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1634 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1635 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1636
1637 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1638 } else if (tp->link_config.speed == SPEED_INVALID) {
1639 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1640 tp->link_config.advertising &=
1641 ~(ADVERTISED_1000baseT_Half |
1642 ADVERTISED_1000baseT_Full);
1643
1644 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1645 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1646 new_adv |= ADVERTISE_10HALF;
1647 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1648 new_adv |= ADVERTISE_10FULL;
1649 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1650 new_adv |= ADVERTISE_100HALF;
1651 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1652 new_adv |= ADVERTISE_100FULL;
1653 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1654
1655 if (tp->link_config.advertising &
1656 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1657 new_adv = 0;
1658 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1659 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1660 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1661 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1662 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1663 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1664 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1665 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1666 MII_TG3_CTRL_ENABLE_AS_MASTER);
1667 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1668 } else {
1669 tg3_writephy(tp, MII_TG3_CTRL, 0);
1670 }
1671 } else {
1672 /* Asking for a specific link mode. */
1673 if (tp->link_config.speed == SPEED_1000) {
1674 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1675 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1676
1677 if (tp->link_config.duplex == DUPLEX_FULL)
1678 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1679 else
1680 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1681 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1682 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1683 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1684 MII_TG3_CTRL_ENABLE_AS_MASTER);
1685 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1686 } else {
1687 tg3_writephy(tp, MII_TG3_CTRL, 0);
1688
1689 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1690 if (tp->link_config.speed == SPEED_100) {
1691 if (tp->link_config.duplex == DUPLEX_FULL)
1692 new_adv |= ADVERTISE_100FULL;
1693 else
1694 new_adv |= ADVERTISE_100HALF;
1695 } else {
1696 if (tp->link_config.duplex == DUPLEX_FULL)
1697 new_adv |= ADVERTISE_10FULL;
1698 else
1699 new_adv |= ADVERTISE_10HALF;
1700 }
1701 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1702 }
1703 }
1704
1705 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1706 tp->link_config.speed != SPEED_INVALID) {
1707 u32 bmcr, orig_bmcr;
1708
1709 tp->link_config.active_speed = tp->link_config.speed;
1710 tp->link_config.active_duplex = tp->link_config.duplex;
1711
1712 bmcr = 0;
1713 switch (tp->link_config.speed) {
1714 default:
1715 case SPEED_10:
1716 break;
1717
1718 case SPEED_100:
1719 bmcr |= BMCR_SPEED100;
1720 break;
1721
1722 case SPEED_1000:
1723 bmcr |= TG3_BMCR_SPEED1000;
1724 break;
1725 };
1726
1727 if (tp->link_config.duplex == DUPLEX_FULL)
1728 bmcr |= BMCR_FULLDPLX;
1729
1730 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1731 (bmcr != orig_bmcr)) {
1732 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1733 for (i = 0; i < 1500; i++) {
1734 u32 tmp;
1735
1736 udelay(10);
1737 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1738 tg3_readphy(tp, MII_BMSR, &tmp))
1739 continue;
1740 if (!(tmp & BMSR_LSTATUS)) {
1741 udelay(40);
1742 break;
1743 }
1744 }
1745 tg3_writephy(tp, MII_BMCR, bmcr);
1746 udelay(40);
1747 }
1748 } else {
1749 tg3_writephy(tp, MII_BMCR,
1750 BMCR_ANENABLE | BMCR_ANRESTART);
1751 }
1752 }
1753
1754 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1755 {
1756 int err;
1757
1758 /* Turn off tap power management. */
1759 /* Set Extended packet length bit */
1760 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1761
1762 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1763 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1764
1765 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1766 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1767
1768 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1769 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1770
1771 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1772 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1773
1774 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1775 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1776
1777 udelay(40);
1778
1779 return err;
1780 }
1781
1782 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1783 {
1784 u32 adv_reg, all_mask = 0;
1785
1786 if (mask & ADVERTISED_10baseT_Half)
1787 all_mask |= ADVERTISE_10HALF;
1788 if (mask & ADVERTISED_10baseT_Full)
1789 all_mask |= ADVERTISE_10FULL;
1790 if (mask & ADVERTISED_100baseT_Half)
1791 all_mask |= ADVERTISE_100HALF;
1792 if (mask & ADVERTISED_100baseT_Full)
1793 all_mask |= ADVERTISE_100FULL;
1794
1795 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1796 return 0;
1797
1798 if ((adv_reg & all_mask) != all_mask)
1799 return 0;
1800 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1801 u32 tg3_ctrl;
1802
1803 all_mask = 0;
1804 if (mask & ADVERTISED_1000baseT_Half)
1805 all_mask |= ADVERTISE_1000HALF;
1806 if (mask & ADVERTISED_1000baseT_Full)
1807 all_mask |= ADVERTISE_1000FULL;
1808
1809 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1810 return 0;
1811
1812 if ((tg3_ctrl & all_mask) != all_mask)
1813 return 0;
1814 }
1815 return 1;
1816 }
1817
1818 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1819 {
1820 int current_link_up;
1821 u32 bmsr, dummy;
1822 u16 current_speed;
1823 u8 current_duplex;
1824 int i, err;
1825
1826 tw32(MAC_EVENT, 0);
1827
1828 tw32_f(MAC_STATUS,
1829 (MAC_STATUS_SYNC_CHANGED |
1830 MAC_STATUS_CFG_CHANGED |
1831 MAC_STATUS_MI_COMPLETION |
1832 MAC_STATUS_LNKSTATE_CHANGED));
1833 udelay(40);
1834
1835 tp->mi_mode = MAC_MI_MODE_BASE;
1836 tw32_f(MAC_MI_MODE, tp->mi_mode);
1837 udelay(80);
1838
1839 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1840
1841 /* Some third-party PHYs need to be reset on link going
1842 * down.
1843 */
1844 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1845 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1846 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1847 netif_carrier_ok(tp->dev)) {
1848 tg3_readphy(tp, MII_BMSR, &bmsr);
1849 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1850 !(bmsr & BMSR_LSTATUS))
1851 force_reset = 1;
1852 }
1853 if (force_reset)
1854 tg3_phy_reset(tp);
1855
1856 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1857 tg3_readphy(tp, MII_BMSR, &bmsr);
1858 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1859 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1860 bmsr = 0;
1861
1862 if (!(bmsr & BMSR_LSTATUS)) {
1863 err = tg3_init_5401phy_dsp(tp);
1864 if (err)
1865 return err;
1866
1867 tg3_readphy(tp, MII_BMSR, &bmsr);
1868 for (i = 0; i < 1000; i++) {
1869 udelay(10);
1870 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1871 (bmsr & BMSR_LSTATUS)) {
1872 udelay(40);
1873 break;
1874 }
1875 }
1876
1877 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1878 !(bmsr & BMSR_LSTATUS) &&
1879 tp->link_config.active_speed == SPEED_1000) {
1880 err = tg3_phy_reset(tp);
1881 if (!err)
1882 err = tg3_init_5401phy_dsp(tp);
1883 if (err)
1884 return err;
1885 }
1886 }
1887 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1888 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1889 /* 5701 {A0,B0} CRC bug workaround */
1890 tg3_writephy(tp, 0x15, 0x0a75);
1891 tg3_writephy(tp, 0x1c, 0x8c68);
1892 tg3_writephy(tp, 0x1c, 0x8d68);
1893 tg3_writephy(tp, 0x1c, 0x8c68);
1894 }
1895
1896 /* Clear pending interrupts... */
1897 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1898 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1899
1900 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1901 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1902 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1903 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1904
1905 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1906 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1907 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1908 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1909 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1910 else
1911 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1912 }
1913
1914 current_link_up = 0;
1915 current_speed = SPEED_INVALID;
1916 current_duplex = DUPLEX_INVALID;
1917
1918 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1919 u32 val;
1920
1921 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1922 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1923 if (!(val & (1 << 10))) {
1924 val |= (1 << 10);
1925 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1926 goto relink;
1927 }
1928 }
1929
1930 bmsr = 0;
1931 for (i = 0; i < 100; i++) {
1932 tg3_readphy(tp, MII_BMSR, &bmsr);
1933 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1934 (bmsr & BMSR_LSTATUS))
1935 break;
1936 udelay(40);
1937 }
1938
1939 if (bmsr & BMSR_LSTATUS) {
1940 u32 aux_stat, bmcr;
1941
1942 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1943 for (i = 0; i < 2000; i++) {
1944 udelay(10);
1945 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1946 aux_stat)
1947 break;
1948 }
1949
1950 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1951 &current_speed,
1952 &current_duplex);
1953
1954 bmcr = 0;
1955 for (i = 0; i < 200; i++) {
1956 tg3_readphy(tp, MII_BMCR, &bmcr);
1957 if (tg3_readphy(tp, MII_BMCR, &bmcr))
1958 continue;
1959 if (bmcr && bmcr != 0x7fff)
1960 break;
1961 udelay(10);
1962 }
1963
1964 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1965 if (bmcr & BMCR_ANENABLE) {
1966 current_link_up = 1;
1967
1968 /* Force autoneg restart if we are exiting
1969 * low power mode.
1970 */
1971 if (!tg3_copper_is_advertising_all(tp,
1972 tp->link_config.advertising))
1973 current_link_up = 0;
1974 } else {
1975 current_link_up = 0;
1976 }
1977 } else {
1978 if (!(bmcr & BMCR_ANENABLE) &&
1979 tp->link_config.speed == current_speed &&
1980 tp->link_config.duplex == current_duplex) {
1981 current_link_up = 1;
1982 } else {
1983 current_link_up = 0;
1984 }
1985 }
1986
1987 tp->link_config.active_speed = current_speed;
1988 tp->link_config.active_duplex = current_duplex;
1989 }
1990
1991 if (current_link_up == 1 &&
1992 (tp->link_config.active_duplex == DUPLEX_FULL) &&
1993 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1994 u32 local_adv, remote_adv;
1995
1996 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1997 local_adv = 0;
1998 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1999
2000 if (tg3_readphy(tp, MII_LPA, &remote_adv))
2001 remote_adv = 0;
2002
2003 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
2004
2005 /* If we are not advertising full pause capability,
2006 * something is wrong. Bring the link down and reconfigure.
2007 */
2008 if (local_adv != ADVERTISE_PAUSE_CAP) {
2009 current_link_up = 0;
2010 } else {
2011 tg3_setup_flow_control(tp, local_adv, remote_adv);
2012 }
2013 }
2014 relink:
2015 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
2016 u32 tmp;
2017
2018 tg3_phy_copper_begin(tp);
2019
2020 tg3_readphy(tp, MII_BMSR, &tmp);
2021 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
2022 (tmp & BMSR_LSTATUS))
2023 current_link_up = 1;
2024 }
2025
2026 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
2027 if (current_link_up == 1) {
2028 if (tp->link_config.active_speed == SPEED_100 ||
2029 tp->link_config.active_speed == SPEED_10)
2030 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
2031 else
2032 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2033 } else
2034 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2035
2036 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2037 if (tp->link_config.active_duplex == DUPLEX_HALF)
2038 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2039
2040 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
2041 if (current_link_up == 1 &&
2042 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
2043 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2044 else
2045 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2046 }
2047
2048 /* ??? Without this setting Netgear GA302T PHY does not
2049 * ??? send/receive packets...
2050 */
2051 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2052 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2053 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2054 tw32_f(MAC_MI_MODE, tp->mi_mode);
2055 udelay(80);
2056 }
2057
2058 tw32_f(MAC_MODE, tp->mac_mode);
2059 udelay(40);
2060
2061 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2062 /* Polled via timer. */
2063 tw32_f(MAC_EVENT, 0);
2064 } else {
2065 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2066 }
2067 udelay(40);
2068
2069 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2070 current_link_up == 1 &&
2071 tp->link_config.active_speed == SPEED_1000 &&
2072 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2073 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2074 udelay(120);
2075 tw32_f(MAC_STATUS,
2076 (MAC_STATUS_SYNC_CHANGED |
2077 MAC_STATUS_CFG_CHANGED));
2078 udelay(40);
2079 tg3_write_mem(tp,
2080 NIC_SRAM_FIRMWARE_MBOX,
2081 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2082 }
2083
2084 if (current_link_up != netif_carrier_ok(tp->dev)) {
2085 if (current_link_up)
2086 netif_carrier_on(tp->dev);
2087 else
2088 netif_carrier_off(tp->dev);
2089 tg3_link_report(tp);
2090 }
2091
2092 return 0;
2093 }
2094
2095 struct tg3_fiber_aneginfo {
2096 int state;
2097 #define ANEG_STATE_UNKNOWN 0
2098 #define ANEG_STATE_AN_ENABLE 1
2099 #define ANEG_STATE_RESTART_INIT 2
2100 #define ANEG_STATE_RESTART 3
2101 #define ANEG_STATE_DISABLE_LINK_OK 4
2102 #define ANEG_STATE_ABILITY_DETECT_INIT 5
2103 #define ANEG_STATE_ABILITY_DETECT 6
2104 #define ANEG_STATE_ACK_DETECT_INIT 7
2105 #define ANEG_STATE_ACK_DETECT 8
2106 #define ANEG_STATE_COMPLETE_ACK_INIT 9
2107 #define ANEG_STATE_COMPLETE_ACK 10
2108 #define ANEG_STATE_IDLE_DETECT_INIT 11
2109 #define ANEG_STATE_IDLE_DETECT 12
2110 #define ANEG_STATE_LINK_OK 13
2111 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
2112 #define ANEG_STATE_NEXT_PAGE_WAIT 15
2113
2114 u32 flags;
2115 #define MR_AN_ENABLE 0x00000001
2116 #define MR_RESTART_AN 0x00000002
2117 #define MR_AN_COMPLETE 0x00000004
2118 #define MR_PAGE_RX 0x00000008
2119 #define MR_NP_LOADED 0x00000010
2120 #define MR_TOGGLE_TX 0x00000020
2121 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
2122 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
2123 #define MR_LP_ADV_SYM_PAUSE 0x00000100
2124 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
2125 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2126 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2127 #define MR_LP_ADV_NEXT_PAGE 0x00001000
2128 #define MR_TOGGLE_RX 0x00002000
2129 #define MR_NP_RX 0x00004000
2130
2131 #define MR_LINK_OK 0x80000000
2132
2133 unsigned long link_time, cur_time;
2134
2135 u32 ability_match_cfg;
2136 int ability_match_count;
2137
2138 char ability_match, idle_match, ack_match;
2139
2140 u32 txconfig, rxconfig;
2141 #define ANEG_CFG_NP 0x00000080
2142 #define ANEG_CFG_ACK 0x00000040
2143 #define ANEG_CFG_RF2 0x00000020
2144 #define ANEG_CFG_RF1 0x00000010
2145 #define ANEG_CFG_PS2 0x00000001
2146 #define ANEG_CFG_PS1 0x00008000
2147 #define ANEG_CFG_HD 0x00004000
2148 #define ANEG_CFG_FD 0x00002000
2149 #define ANEG_CFG_INVAL 0x00001f06
2150
2151 };
2152 #define ANEG_OK 0
2153 #define ANEG_DONE 1
2154 #define ANEG_TIMER_ENAB 2
2155 #define ANEG_FAILED -1
2156
2157 #define ANEG_STATE_SETTLE_TIME 10000
2158
2159 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2160 struct tg3_fiber_aneginfo *ap)
2161 {
2162 unsigned long delta;
2163 u32 rx_cfg_reg;
2164 int ret;
2165
2166 if (ap->state == ANEG_STATE_UNKNOWN) {
2167 ap->rxconfig = 0;
2168 ap->link_time = 0;
2169 ap->cur_time = 0;
2170 ap->ability_match_cfg = 0;
2171 ap->ability_match_count = 0;
2172 ap->ability_match = 0;
2173 ap->idle_match = 0;
2174 ap->ack_match = 0;
2175 }
2176 ap->cur_time++;
2177
2178 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2179 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2180
2181 if (rx_cfg_reg != ap->ability_match_cfg) {
2182 ap->ability_match_cfg = rx_cfg_reg;
2183 ap->ability_match = 0;
2184 ap->ability_match_count = 0;
2185 } else {
2186 if (++ap->ability_match_count > 1) {
2187 ap->ability_match = 1;
2188 ap->ability_match_cfg = rx_cfg_reg;
2189 }
2190 }
2191 if (rx_cfg_reg & ANEG_CFG_ACK)
2192 ap->ack_match = 1;
2193 else
2194 ap->ack_match = 0;
2195
2196 ap->idle_match = 0;
2197 } else {
2198 ap->idle_match = 1;
2199 ap->ability_match_cfg = 0;
2200 ap->ability_match_count = 0;
2201 ap->ability_match = 0;
2202 ap->ack_match = 0;
2203
2204 rx_cfg_reg = 0;
2205 }
2206
2207 ap->rxconfig = rx_cfg_reg;
2208 ret = ANEG_OK;
2209
2210 switch(ap->state) {
2211 case ANEG_STATE_UNKNOWN:
2212 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2213 ap->state = ANEG_STATE_AN_ENABLE;
2214
2215 /* fallthru */
2216 case ANEG_STATE_AN_ENABLE:
2217 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2218 if (ap->flags & MR_AN_ENABLE) {
2219 ap->link_time = 0;
2220 ap->cur_time = 0;
2221 ap->ability_match_cfg = 0;
2222 ap->ability_match_count = 0;
2223 ap->ability_match = 0;
2224 ap->idle_match = 0;
2225 ap->ack_match = 0;
2226
2227 ap->state = ANEG_STATE_RESTART_INIT;
2228 } else {
2229 ap->state = ANEG_STATE_DISABLE_LINK_OK;
2230 }
2231 break;
2232
2233 case ANEG_STATE_RESTART_INIT:
2234 ap->link_time = ap->cur_time;
2235 ap->flags &= ~(MR_NP_LOADED);
2236 ap->txconfig = 0;
2237 tw32(MAC_TX_AUTO_NEG, 0);
2238 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2239 tw32_f(MAC_MODE, tp->mac_mode);
2240 udelay(40);
2241
2242 ret = ANEG_TIMER_ENAB;
2243 ap->state = ANEG_STATE_RESTART;
2244
2245 /* fallthru */
2246 case ANEG_STATE_RESTART:
2247 delta = ap->cur_time - ap->link_time;
2248 if (delta > ANEG_STATE_SETTLE_TIME) {
2249 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2250 } else {
2251 ret = ANEG_TIMER_ENAB;
2252 }
2253 break;
2254
2255 case ANEG_STATE_DISABLE_LINK_OK:
2256 ret = ANEG_DONE;
2257 break;
2258
2259 case ANEG_STATE_ABILITY_DETECT_INIT:
2260 ap->flags &= ~(MR_TOGGLE_TX);
2261 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2262 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2263 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2264 tw32_f(MAC_MODE, tp->mac_mode);
2265 udelay(40);
2266
2267 ap->state = ANEG_STATE_ABILITY_DETECT;
2268 break;
2269
2270 case ANEG_STATE_ABILITY_DETECT:
2271 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2272 ap->state = ANEG_STATE_ACK_DETECT_INIT;
2273 }
2274 break;
2275
2276 case ANEG_STATE_ACK_DETECT_INIT:
2277 ap->txconfig |= ANEG_CFG_ACK;
2278 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2279 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2280 tw32_f(MAC_MODE, tp->mac_mode);
2281 udelay(40);
2282
2283 ap->state = ANEG_STATE_ACK_DETECT;
2284
2285 /* fallthru */
2286 case ANEG_STATE_ACK_DETECT:
2287 if (ap->ack_match != 0) {
2288 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2289 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2290 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2291 } else {
2292 ap->state = ANEG_STATE_AN_ENABLE;
2293 }
2294 } else if (ap->ability_match != 0 &&
2295 ap->rxconfig == 0) {
2296 ap->state = ANEG_STATE_AN_ENABLE;
2297 }
2298 break;
2299
2300 case ANEG_STATE_COMPLETE_ACK_INIT:
2301 if (ap->rxconfig & ANEG_CFG_INVAL) {
2302 ret = ANEG_FAILED;
2303 break;
2304 }
2305 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2306 MR_LP_ADV_HALF_DUPLEX |
2307 MR_LP_ADV_SYM_PAUSE |
2308 MR_LP_ADV_ASYM_PAUSE |
2309 MR_LP_ADV_REMOTE_FAULT1 |
2310 MR_LP_ADV_REMOTE_FAULT2 |
2311 MR_LP_ADV_NEXT_PAGE |
2312 MR_TOGGLE_RX |
2313 MR_NP_RX);
2314 if (ap->rxconfig & ANEG_CFG_FD)
2315 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2316 if (ap->rxconfig & ANEG_CFG_HD)
2317 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2318 if (ap->rxconfig & ANEG_CFG_PS1)
2319 ap->flags |= MR_LP_ADV_SYM_PAUSE;
2320 if (ap->rxconfig & ANEG_CFG_PS2)
2321 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2322 if (ap->rxconfig & ANEG_CFG_RF1)
2323 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2324 if (ap->rxconfig & ANEG_CFG_RF2)
2325 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2326 if (ap->rxconfig & ANEG_CFG_NP)
2327 ap->flags |= MR_LP_ADV_NEXT_PAGE;
2328
2329 ap->link_time = ap->cur_time;
2330
2331 ap->flags ^= (MR_TOGGLE_TX);
2332 if (ap->rxconfig & 0x0008)
2333 ap->flags |= MR_TOGGLE_RX;
2334 if (ap->rxconfig & ANEG_CFG_NP)
2335 ap->flags |= MR_NP_RX;
2336 ap->flags |= MR_PAGE_RX;
2337
2338 ap->state = ANEG_STATE_COMPLETE_ACK;
2339 ret = ANEG_TIMER_ENAB;
2340 break;
2341
2342 case ANEG_STATE_COMPLETE_ACK:
2343 if (ap->ability_match != 0 &&
2344 ap->rxconfig == 0) {
2345 ap->state = ANEG_STATE_AN_ENABLE;
2346 break;
2347 }
2348 delta = ap->cur_time - ap->link_time;
2349 if (delta > ANEG_STATE_SETTLE_TIME) {
2350 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2351 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2352 } else {
2353 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2354 !(ap->flags & MR_NP_RX)) {
2355 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2356 } else {
2357 ret = ANEG_FAILED;
2358 }
2359 }
2360 }
2361 break;
2362
2363 case ANEG_STATE_IDLE_DETECT_INIT:
2364 ap->link_time = ap->cur_time;
2365 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2366 tw32_f(MAC_MODE, tp->mac_mode);
2367 udelay(40);
2368
2369 ap->state = ANEG_STATE_IDLE_DETECT;
2370 ret = ANEG_TIMER_ENAB;
2371 break;
2372
2373 case ANEG_STATE_IDLE_DETECT:
2374 if (ap->ability_match != 0 &&
2375 ap->rxconfig == 0) {
2376 ap->state = ANEG_STATE_AN_ENABLE;
2377 break;
2378 }
2379 delta = ap->cur_time - ap->link_time;
2380 if (delta > ANEG_STATE_SETTLE_TIME) {
2381 /* XXX another gem from the Broadcom driver :( */
2382 ap->state = ANEG_STATE_LINK_OK;
2383 }
2384 break;
2385
2386 case ANEG_STATE_LINK_OK:
2387 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2388 ret = ANEG_DONE;
2389 break;
2390
2391 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2392 /* ??? unimplemented */
2393 break;
2394
2395 case ANEG_STATE_NEXT_PAGE_WAIT:
2396 /* ??? unimplemented */
2397 break;
2398
2399 default:
2400 ret = ANEG_FAILED;
2401 break;
2402 };
2403
2404 return ret;
2405 }
2406
2407 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2408 {
2409 int res = 0;
2410 struct tg3_fiber_aneginfo aninfo;
2411 int status = ANEG_FAILED;
2412 unsigned int tick;
2413 u32 tmp;
2414
2415 tw32_f(MAC_TX_AUTO_NEG, 0);
2416
2417 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2418 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2419 udelay(40);
2420
2421 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2422 udelay(40);
2423
2424 memset(&aninfo, 0, sizeof(aninfo));
2425 aninfo.flags |= MR_AN_ENABLE;
2426 aninfo.state = ANEG_STATE_UNKNOWN;
2427 aninfo.cur_time = 0;
2428 tick = 0;
2429 while (++tick < 195000) {
2430 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2431 if (status == ANEG_DONE || status == ANEG_FAILED)
2432 break;
2433
2434 udelay(1);
2435 }
2436
2437 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2438 tw32_f(MAC_MODE, tp->mac_mode);
2439 udelay(40);
2440
2441 *flags = aninfo.flags;
2442
2443 if (status == ANEG_DONE &&
2444 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2445 MR_LP_ADV_FULL_DUPLEX)))
2446 res = 1;
2447
2448 return res;
2449 }
2450
2451 static void tg3_init_bcm8002(struct tg3 *tp)
2452 {
2453 u32 mac_status = tr32(MAC_STATUS);
2454 int i;
2455
2456 /* Reset when initting first time or we have a link. */
2457 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2458 !(mac_status & MAC_STATUS_PCS_SYNCED))
2459 return;
2460
2461 /* Set PLL lock range. */
2462 tg3_writephy(tp, 0x16, 0x8007);
2463
2464 /* SW reset */
2465 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2466
2467 /* Wait for reset to complete. */
2468 /* XXX schedule_timeout() ... */
2469 for (i = 0; i < 500; i++)
2470 udelay(10);
2471
2472 /* Config mode; select PMA/Ch 1 regs. */
2473 tg3_writephy(tp, 0x10, 0x8411);
2474
2475 /* Enable auto-lock and comdet, select txclk for tx. */
2476 tg3_writephy(tp, 0x11, 0x0a10);
2477
2478 tg3_writephy(tp, 0x18, 0x00a0);
2479 tg3_writephy(tp, 0x16, 0x41ff);
2480
2481 /* Assert and deassert POR. */
2482 tg3_writephy(tp, 0x13, 0x0400);
2483 udelay(40);
2484 tg3_writephy(tp, 0x13, 0x0000);
2485
2486 tg3_writephy(tp, 0x11, 0x0a50);
2487 udelay(40);
2488 tg3_writephy(tp, 0x11, 0x0a10);
2489
2490 /* Wait for signal to stabilize */
2491 /* XXX schedule_timeout() ... */
2492 for (i = 0; i < 15000; i++)
2493 udelay(10);
2494
2495 /* Deselect the channel register so we can read the PHYID
2496 * later.
2497 */
2498 tg3_writephy(tp, 0x10, 0x8011);
2499 }
2500
2501 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2502 {
2503 u32 sg_dig_ctrl, sg_dig_status;
2504 u32 serdes_cfg, expected_sg_dig_ctrl;
2505 int workaround, port_a;
2506 int current_link_up;
2507
2508 serdes_cfg = 0;
2509 expected_sg_dig_ctrl = 0;
2510 workaround = 0;
2511 port_a = 1;
2512 current_link_up = 0;
2513
2514 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2515 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2516 workaround = 1;
2517 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2518 port_a = 0;
2519
2520 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2521 /* preserve bits 20-23 for voltage regulator */
2522 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2523 }
2524
2525 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2526
2527 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2528 if (sg_dig_ctrl & (1 << 31)) {
2529 if (workaround) {
2530 u32 val = serdes_cfg;
2531
2532 if (port_a)
2533 val |= 0xc010000;
2534 else
2535 val |= 0x4010000;
2536 tw32_f(MAC_SERDES_CFG, val);
2537 }
2538 tw32_f(SG_DIG_CTRL, 0x01388400);
2539 }
2540 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2541 tg3_setup_flow_control(tp, 0, 0);
2542 current_link_up = 1;
2543 }
2544 goto out;
2545 }
2546
2547 /* Want auto-negotiation. */
2548 expected_sg_dig_ctrl = 0x81388400;
2549
2550 /* Pause capability */
2551 expected_sg_dig_ctrl |= (1 << 11);
2552
2553 /* Asymettric pause */
2554 expected_sg_dig_ctrl |= (1 << 12);
2555
2556 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2557 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2558 tp->serdes_counter &&
2559 ((mac_status & (MAC_STATUS_PCS_SYNCED |
2560 MAC_STATUS_RCVD_CFG)) ==
2561 MAC_STATUS_PCS_SYNCED)) {
2562 tp->serdes_counter--;
2563 current_link_up = 1;
2564 goto out;
2565 }
2566 restart_autoneg:
2567 if (workaround)
2568 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2569 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2570 udelay(5);
2571 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2572
2573 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2574 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2575 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2576 MAC_STATUS_SIGNAL_DET)) {
2577 sg_dig_status = tr32(SG_DIG_STATUS);
2578 mac_status = tr32(MAC_STATUS);
2579
2580 if ((sg_dig_status & (1 << 1)) &&
2581 (mac_status & MAC_STATUS_PCS_SYNCED)) {
2582 u32 local_adv, remote_adv;
2583
2584 local_adv = ADVERTISE_PAUSE_CAP;
2585 remote_adv = 0;
2586 if (sg_dig_status & (1 << 19))
2587 remote_adv |= LPA_PAUSE_CAP;
2588 if (sg_dig_status & (1 << 20))
2589 remote_adv |= LPA_PAUSE_ASYM;
2590
2591 tg3_setup_flow_control(tp, local_adv, remote_adv);
2592 current_link_up = 1;
2593 tp->serdes_counter = 0;
2594 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2595 } else if (!(sg_dig_status & (1 << 1))) {
2596 if (tp->serdes_counter)
2597 tp->serdes_counter--;
2598 else {
2599 if (workaround) {
2600 u32 val = serdes_cfg;
2601
2602 if (port_a)
2603 val |= 0xc010000;
2604 else
2605 val |= 0x4010000;
2606
2607 tw32_f(MAC_SERDES_CFG, val);
2608 }
2609
2610 tw32_f(SG_DIG_CTRL, 0x01388400);
2611 udelay(40);
2612
2613 /* Link parallel detection - link is up */
2614 /* only if we have PCS_SYNC and not */
2615 /* receiving config code words */
2616 mac_status = tr32(MAC_STATUS);
2617 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2618 !(mac_status & MAC_STATUS_RCVD_CFG)) {
2619 tg3_setup_flow_control(tp, 0, 0);
2620 current_link_up = 1;
2621 tp->tg3_flags2 |=
2622 TG3_FLG2_PARALLEL_DETECT;
2623 tp->serdes_counter =
2624 SERDES_PARALLEL_DET_TIMEOUT;
2625 } else
2626 goto restart_autoneg;
2627 }
2628 }
2629 } else {
2630 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2631 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2632 }
2633
2634 out:
2635 return current_link_up;
2636 }
2637
2638 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2639 {
2640 int current_link_up = 0;
2641
2642 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
2643 goto out;
2644
2645 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2646 u32 flags;
2647 int i;
2648
2649 if (fiber_autoneg(tp, &flags)) {
2650 u32 local_adv, remote_adv;
2651
2652 local_adv = ADVERTISE_PAUSE_CAP;
2653 remote_adv = 0;
2654 if (flags & MR_LP_ADV_SYM_PAUSE)
2655 remote_adv |= LPA_PAUSE_CAP;
2656 if (flags & MR_LP_ADV_ASYM_PAUSE)
2657 remote_adv |= LPA_PAUSE_ASYM;
2658
2659 tg3_setup_flow_control(tp, local_adv, remote_adv);
2660
2661 current_link_up = 1;
2662 }
2663 for (i = 0; i < 30; i++) {
2664 udelay(20);
2665 tw32_f(MAC_STATUS,
2666 (MAC_STATUS_SYNC_CHANGED |
2667 MAC_STATUS_CFG_CHANGED));
2668 udelay(40);
2669 if ((tr32(MAC_STATUS) &
2670 (MAC_STATUS_SYNC_CHANGED |
2671 MAC_STATUS_CFG_CHANGED)) == 0)
2672 break;
2673 }
2674
2675 mac_status = tr32(MAC_STATUS);
2676 if (current_link_up == 0 &&
2677 (mac_status & MAC_STATUS_PCS_SYNCED) &&
2678 !(mac_status & MAC_STATUS_RCVD_CFG))
2679 current_link_up = 1;
2680 } else {
2681 /* Forcing 1000FD link up. */
2682 current_link_up = 1;
2683
2684 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2685 udelay(40);
2686
2687 tw32_f(MAC_MODE, tp->mac_mode);
2688 udelay(40);
2689 }
2690
2691 out:
2692 return current_link_up;
2693 }
2694
2695 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2696 {
2697 u32 orig_pause_cfg;
2698 u16 orig_active_speed;
2699 u8 orig_active_duplex;
2700 u32 mac_status;
2701 int current_link_up;
2702 int i;
2703
2704 orig_pause_cfg =
2705 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2706 TG3_FLAG_TX_PAUSE));
2707 orig_active_speed = tp->link_config.active_speed;
2708 orig_active_duplex = tp->link_config.active_duplex;
2709
2710 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2711 netif_carrier_ok(tp->dev) &&
2712 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2713 mac_status = tr32(MAC_STATUS);
2714 mac_status &= (MAC_STATUS_PCS_SYNCED |
2715 MAC_STATUS_SIGNAL_DET |
2716 MAC_STATUS_CFG_CHANGED |
2717 MAC_STATUS_RCVD_CFG);
2718 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2719 MAC_STATUS_SIGNAL_DET)) {
2720 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2721 MAC_STATUS_CFG_CHANGED));
2722 return 0;
2723 }
2724 }
2725
2726 tw32_f(MAC_TX_AUTO_NEG, 0);
2727
2728 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2729 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2730 tw32_f(MAC_MODE, tp->mac_mode);
2731 udelay(40);
2732
2733 if (tp->phy_id == PHY_ID_BCM8002)
2734 tg3_init_bcm8002(tp);
2735
2736 /* Enable link change event even when serdes polling. */
2737 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2738 udelay(40);
2739
2740 current_link_up = 0;
2741 mac_status = tr32(MAC_STATUS);
2742
2743 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2744 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2745 else
2746 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2747
2748 tp->hw_status->status =
2749 (SD_STATUS_UPDATED |
2750 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2751
2752 for (i = 0; i < 100; i++) {
2753 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2754 MAC_STATUS_CFG_CHANGED));
2755 udelay(5);
2756 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2757 MAC_STATUS_CFG_CHANGED |
2758 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
2759 break;
2760 }
2761
2762 mac_status = tr32(MAC_STATUS);
2763 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2764 current_link_up = 0;
2765 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2766 tp->serdes_counter == 0) {
2767 tw32_f(MAC_MODE, (tp->mac_mode |
2768 MAC_MODE_SEND_CONFIGS));
2769 udelay(1);
2770 tw32_f(MAC_MODE, tp->mac_mode);
2771 }
2772 }
2773
2774 if (current_link_up == 1) {
2775 tp->link_config.active_speed = SPEED_1000;
2776 tp->link_config.active_duplex = DUPLEX_FULL;
2777 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2778 LED_CTRL_LNKLED_OVERRIDE |
2779 LED_CTRL_1000MBPS_ON));
2780 } else {
2781 tp->link_config.active_speed = SPEED_INVALID;
2782 tp->link_config.active_duplex = DUPLEX_INVALID;
2783 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2784 LED_CTRL_LNKLED_OVERRIDE |
2785 LED_CTRL_TRAFFIC_OVERRIDE));
2786 }
2787
2788 if (current_link_up != netif_carrier_ok(tp->dev)) {
2789 if (current_link_up)
2790 netif_carrier_on(tp->dev);
2791 else
2792 netif_carrier_off(tp->dev);
2793 tg3_link_report(tp);
2794 } else {
2795 u32 now_pause_cfg =
2796 tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2797 TG3_FLAG_TX_PAUSE);
2798 if (orig_pause_cfg != now_pause_cfg ||
2799 orig_active_speed != tp->link_config.active_speed ||
2800 orig_active_duplex != tp->link_config.active_duplex)
2801 tg3_link_report(tp);
2802 }
2803
2804 return 0;
2805 }
2806
2807 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2808 {
2809 int current_link_up, err = 0;
2810 u32 bmsr, bmcr;
2811 u16 current_speed;
2812 u8 current_duplex;
2813
2814 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2815 tw32_f(MAC_MODE, tp->mac_mode);
2816 udelay(40);
2817
2818 tw32(MAC_EVENT, 0);
2819
2820 tw32_f(MAC_STATUS,
2821 (MAC_STATUS_SYNC_CHANGED |
2822 MAC_STATUS_CFG_CHANGED |
2823 MAC_STATUS_MI_COMPLETION |
2824 MAC_STATUS_LNKSTATE_CHANGED));
2825 udelay(40);
2826
2827 if (force_reset)
2828 tg3_phy_reset(tp);
2829
2830 current_link_up = 0;
2831 current_speed = SPEED_INVALID;
2832 current_duplex = DUPLEX_INVALID;
2833
2834 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2835 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2836 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2837 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2838 bmsr |= BMSR_LSTATUS;
2839 else
2840 bmsr &= ~BMSR_LSTATUS;
2841 }
2842
2843 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2844
2845 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2846 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2847 /* do nothing, just check for link up at the end */
2848 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2849 u32 adv, new_adv;
2850
2851 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2852 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2853 ADVERTISE_1000XPAUSE |
2854 ADVERTISE_1000XPSE_ASYM |
2855 ADVERTISE_SLCT);
2856
2857 /* Always advertise symmetric PAUSE just like copper */
2858 new_adv |= ADVERTISE_1000XPAUSE;
2859
2860 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2861 new_adv |= ADVERTISE_1000XHALF;
2862 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2863 new_adv |= ADVERTISE_1000XFULL;
2864
2865 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2866 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2867 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2868 tg3_writephy(tp, MII_BMCR, bmcr);
2869
2870 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2871 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
2872 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2873
2874 return err;
2875 }
2876 } else {
2877 u32 new_bmcr;
2878
2879 bmcr &= ~BMCR_SPEED1000;
2880 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2881
2882 if (tp->link_config.duplex == DUPLEX_FULL)
2883 new_bmcr |= BMCR_FULLDPLX;
2884
2885 if (new_bmcr != bmcr) {
2886 /* BMCR_SPEED1000 is a reserved bit that needs
2887 * to be set on write.
2888 */
2889 new_bmcr |= BMCR_SPEED1000;
2890
2891 /* Force a linkdown */
2892 if (netif_carrier_ok(tp->dev)) {
2893 u32 adv;
2894
2895 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2896 adv &= ~(ADVERTISE_1000XFULL |
2897 ADVERTISE_1000XHALF |
2898 ADVERTISE_SLCT);
2899 tg3_writephy(tp, MII_ADVERTISE, adv);
2900 tg3_writephy(tp, MII_BMCR, bmcr |
2901 BMCR_ANRESTART |
2902 BMCR_ANENABLE);
2903 udelay(10);
2904 netif_carrier_off(tp->dev);
2905 }
2906 tg3_writephy(tp, MII_BMCR, new_bmcr);
2907 bmcr = new_bmcr;
2908 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2909 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2910 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2911 ASIC_REV_5714) {
2912 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2913 bmsr |= BMSR_LSTATUS;
2914 else
2915 bmsr &= ~BMSR_LSTATUS;
2916 }
2917 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2918 }
2919 }
2920
2921 if (bmsr & BMSR_LSTATUS) {
2922 current_speed = SPEED_1000;
2923 current_link_up = 1;
2924 if (bmcr & BMCR_FULLDPLX)
2925 current_duplex = DUPLEX_FULL;
2926 else
2927 current_duplex = DUPLEX_HALF;
2928
2929 if (bmcr & BMCR_ANENABLE) {
2930 u32 local_adv, remote_adv, common;
2931
2932 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2933 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2934 common = local_adv & remote_adv;
2935 if (common & (ADVERTISE_1000XHALF |
2936 ADVERTISE_1000XFULL)) {
2937 if (common & ADVERTISE_1000XFULL)
2938 current_duplex = DUPLEX_FULL;
2939 else
2940 current_duplex = DUPLEX_HALF;
2941
2942 tg3_setup_flow_control(tp, local_adv,
2943 remote_adv);
2944 }
2945 else
2946 current_link_up = 0;
2947 }
2948 }
2949
2950 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2951 if (tp->link_config.active_duplex == DUPLEX_HALF)
2952 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2953
2954 tw32_f(MAC_MODE, tp->mac_mode);
2955 udelay(40);
2956
2957 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2958
2959 tp->link_config.active_speed = current_speed;
2960 tp->link_config.active_duplex = current_duplex;
2961
2962 if (current_link_up != netif_carrier_ok(tp->dev)) {
2963 if (current_link_up)
2964 netif_carrier_on(tp->dev);
2965 else {
2966 netif_carrier_off(tp->dev);
2967 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2968 }
2969 tg3_link_report(tp);
2970 }
2971 return err;
2972 }
2973
2974 static void tg3_serdes_parallel_detect(struct tg3 *tp)
2975 {
2976 if (tp->serdes_counter) {
2977 /* Give autoneg time to complete. */
2978 tp->serdes_counter--;
2979 return;
2980 }
2981 if (!netif_carrier_ok(tp->dev) &&
2982 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2983 u32 bmcr;
2984
2985 tg3_readphy(tp, MII_BMCR, &bmcr);
2986 if (bmcr & BMCR_ANENABLE) {
2987 u32 phy1, phy2;
2988
2989 /* Select shadow register 0x1f */
2990 tg3_writephy(tp, 0x1c, 0x7c00);
2991 tg3_readphy(tp, 0x1c, &phy1);
2992
2993 /* Select expansion interrupt status register */
2994 tg3_writephy(tp, 0x17, 0x0f01);
2995 tg3_readphy(tp, 0x15, &phy2);
2996 tg3_readphy(tp, 0x15, &phy2);
2997
2998 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2999 /* We have signal detect and not receiving
3000 * config code words, link is up by parallel
3001 * detection.
3002 */
3003
3004 bmcr &= ~BMCR_ANENABLE;
3005 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
3006 tg3_writephy(tp, MII_BMCR, bmcr);
3007 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
3008 }
3009 }
3010 }
3011 else if (netif_carrier_ok(tp->dev) &&
3012 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
3013 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3014 u32 phy2;
3015
3016 /* Select expansion interrupt status register */
3017 tg3_writephy(tp, 0x17, 0x0f01);
3018 tg3_readphy(tp, 0x15, &phy2);
3019 if (phy2 & 0x20) {
3020 u32 bmcr;
3021
3022 /* Config code words received, turn on autoneg. */
3023 tg3_readphy(tp, MII_BMCR, &bmcr);
3024 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
3025
3026 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3027
3028 }
3029 }
3030 }
3031
3032 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
3033 {
3034 int err;
3035
3036 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
3037 err = tg3_setup_fiber_phy(tp, force_reset);
3038 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
3039 err = tg3_setup_fiber_mii_phy(tp, force_reset);
3040 } else {
3041 err = tg3_setup_copper_phy(tp, force_reset);
3042 }
3043
3044 if (tp->link_config.active_speed == SPEED_1000 &&
3045 tp->link_config.active_duplex == DUPLEX_HALF)
3046 tw32(MAC_TX_LENGTHS,
3047 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3048 (6 << TX_LENGTHS_IPG_SHIFT) |
3049 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3050 else
3051 tw32(MAC_TX_LENGTHS,
3052 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3053 (6 << TX_LENGTHS_IPG_SHIFT) |
3054 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3055
3056 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3057 if (netif_carrier_ok(tp->dev)) {
3058 tw32(HOSTCC_STAT_COAL_TICKS,
3059 tp->coal.stats_block_coalesce_usecs);
3060 } else {
3061 tw32(HOSTCC_STAT_COAL_TICKS, 0);
3062 }
3063 }
3064
3065 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
3066 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
3067 if (!netif_carrier_ok(tp->dev))
3068 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
3069 tp->pwrmgmt_thresh;
3070 else
3071 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
3072 tw32(PCIE_PWR_MGMT_THRESH, val);
3073 }
3074
3075 return err;
3076 }
3077
3078 /* This is called whenever we suspect that the system chipset is re-
3079 * ordering the sequence of MMIO to the tx send mailbox. The symptom
3080 * is bogus tx completions. We try to recover by setting the
3081 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3082 * in the workqueue.
3083 */
3084 static void tg3_tx_recover(struct tg3 *tp)
3085 {
3086 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3087 tp->write32_tx_mbox == tg3_write_indirect_mbox);
3088
3089 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3090 "mapped I/O cycles to the network device, attempting to "
3091 "recover. Please report the problem to the driver maintainer "
3092 "and include system chipset information.\n", tp->dev->name);
3093
3094 spin_lock(&tp->lock);
3095 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3096 spin_unlock(&tp->lock);
3097 }
3098
3099 static inline u32 tg3_tx_avail(struct tg3 *tp)
3100 {
3101 smp_mb();
3102 return (tp->tx_pending -
3103 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3104 }
3105
3106 /* Tigon3 never reports partial packet sends. So we do not
3107 * need special logic to handle SKBs that have not had all
3108 * of their frags sent yet, like SunGEM does.
3109 */
3110 static void tg3_tx(struct tg3 *tp)
3111 {
3112 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3113 u32 sw_idx = tp->tx_cons;
3114
3115 while (sw_idx != hw_idx) {
3116 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3117 struct sk_buff *skb = ri->skb;
3118 int i, tx_bug = 0;
3119
3120 if (unlikely(skb == NULL)) {
3121 tg3_tx_recover(tp);
3122 return;
3123 }
3124
3125 pci_unmap_single(tp->pdev,
3126 pci_unmap_addr(ri, mapping),
3127 skb_headlen(skb),
3128 PCI_DMA_TODEVICE);
3129
3130 ri->skb = NULL;
3131
3132 sw_idx = NEXT_TX(sw_idx);
3133
3134 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3135 ri = &tp->tx_buffers[sw_idx];
3136 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3137 tx_bug = 1;
3138
3139 pci_unmap_page(tp->pdev,
3140 pci_unmap_addr(ri, mapping),
3141 skb_shinfo(skb)->frags[i].size,
3142 PCI_DMA_TODEVICE);
3143
3144 sw_idx = NEXT_TX(sw_idx);
3145 }
3146
3147 dev_kfree_skb(skb);
3148
3149 if (unlikely(tx_bug)) {
3150 tg3_tx_recover(tp);
3151 return;
3152 }
3153 }
3154
3155 tp->tx_cons = sw_idx;
3156
3157 /* Need to make the tx_cons update visible to tg3_start_xmit()
3158 * before checking for netif_queue_stopped(). Without the
3159 * memory barrier, there is a small possibility that tg3_start_xmit()
3160 * will miss it and cause the queue to be stopped forever.
3161 */
3162 smp_mb();
3163
3164 if (unlikely(netif_queue_stopped(tp->dev) &&
3165 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3166 netif_tx_lock(tp->dev);
3167 if (netif_queue_stopped(tp->dev) &&
3168 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3169 netif_wake_queue(tp->dev);
3170 netif_tx_unlock(tp->dev);
3171 }
3172 }
3173
3174 /* Returns size of skb allocated or < 0 on error.
3175 *
3176 * We only need to fill in the address because the other members
3177 * of the RX descriptor are invariant, see tg3_init_rings.
3178 *
3179 * Note the purposeful assymetry of cpu vs. chip accesses. For
3180 * posting buffers we only dirty the first cache line of the RX
3181 * descriptor (containing the address). Whereas for the RX status
3182 * buffers the cpu only reads the last cacheline of the RX descriptor
3183 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3184 */
3185 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3186 int src_idx, u32 dest_idx_unmasked)
3187 {
3188 struct tg3_rx_buffer_desc *desc;
3189 struct ring_info *map, *src_map;
3190 struct sk_buff *skb;
3191 dma_addr_t mapping;
3192 int skb_size, dest_idx;
3193
3194 src_map = NULL;
3195 switch (opaque_key) {
3196 case RXD_OPAQUE_RING_STD:
3197 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3198 desc = &tp->rx_std[dest_idx];
3199 map = &tp->rx_std_buffers[dest_idx];
3200 if (src_idx >= 0)
3201 src_map = &tp->rx_std_buffers[src_idx];
3202 skb_size = tp->rx_pkt_buf_sz;
3203 break;
3204
3205 case RXD_OPAQUE_RING_JUMBO:
3206 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3207 desc = &tp->rx_jumbo[dest_idx];
3208 map = &tp->rx_jumbo_buffers[dest_idx];
3209 if (src_idx >= 0)
3210 src_map = &tp->rx_jumbo_buffers[src_idx];
3211 skb_size = RX_JUMBO_PKT_BUF_SZ;
3212 break;
3213
3214 default:
3215 return -EINVAL;
3216 };
3217
3218 /* Do not overwrite any of the map or rp information
3219 * until we are sure we can commit to a new buffer.
3220 *
3221 * Callers depend upon this behavior and assume that
3222 * we leave everything unchanged if we fail.
3223 */
3224 skb = netdev_alloc_skb(tp->dev, skb_size);
3225 if (skb == NULL)
3226 return -ENOMEM;
3227
3228 skb_reserve(skb, tp->rx_offset);
3229
3230 mapping = pci_map_single(tp->pdev, skb->data,
3231 skb_size - tp->rx_offset,
3232 PCI_DMA_FROMDEVICE);
3233
3234 map->skb = skb;
3235 pci_unmap_addr_set(map, mapping, mapping);
3236
3237 if (src_map != NULL)
3238 src_map->skb = NULL;
3239
3240 desc->addr_hi = ((u64)mapping >> 32);
3241 desc->addr_lo = ((u64)mapping & 0xffffffff);
3242
3243 return skb_size;
3244 }
3245
3246 /* We only need to move over in the address because the other
3247 * members of the RX descriptor are invariant. See notes above
3248 * tg3_alloc_rx_skb for full details.
3249 */
3250 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3251 int src_idx, u32 dest_idx_unmasked)
3252 {
3253 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3254 struct ring_info *src_map, *dest_map;
3255 int dest_idx;
3256
3257 switch (opaque_key) {
3258 case RXD_OPAQUE_RING_STD:
3259 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3260 dest_desc = &tp->rx_std[dest_idx];
3261 dest_map = &tp->rx_std_buffers[dest_idx];
3262 src_desc = &tp->rx_std[src_idx];
3263 src_map = &tp->rx_std_buffers[src_idx];
3264 break;
3265
3266 case RXD_OPAQUE_RING_JUMBO:
3267 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3268 dest_desc = &tp->rx_jumbo[dest_idx];
3269 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3270 src_desc = &tp->rx_jumbo[src_idx];
3271 src_map = &tp->rx_jumbo_buffers[src_idx];
3272 break;
3273
3274 default:
3275 return;
3276 };
3277
3278 dest_map->skb = src_map->skb;
3279 pci_unmap_addr_set(dest_map, mapping,
3280 pci_unmap_addr(src_map, mapping));
3281 dest_desc->addr_hi = src_desc->addr_hi;
3282 dest_desc->addr_lo = src_desc->addr_lo;
3283
3284 src_map->skb = NULL;
3285 }
3286
3287 #if TG3_VLAN_TAG_USED
3288 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3289 {
3290 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3291 }
3292 #endif
3293
3294 /* The RX ring scheme is composed of multiple rings which post fresh
3295 * buffers to the chip, and one special ring the chip uses to report
3296 * status back to the host.
3297 *
3298 * The special ring reports the status of received packets to the
3299 * host. The chip does not write into the original descriptor the
3300 * RX buffer was obtained from. The chip simply takes the original
3301 * descriptor as provided by the host, updates the status and length
3302 * field, then writes this into the next status ring entry.
3303 *
3304 * Each ring the host uses to post buffers to the chip is described
3305 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
3306 * it is first placed into the on-chip ram. When the packet's length
3307 * is known, it walks down the TG3_BDINFO entries to select the ring.
3308 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3309 * which is within the range of the new packet's length is chosen.
3310 *
3311 * The "separate ring for rx status" scheme may sound queer, but it makes
3312 * sense from a cache coherency perspective. If only the host writes
3313 * to the buffer post rings, and only the chip writes to the rx status
3314 * rings, then cache lines never move beyond shared-modified state.
3315 * If both the host and chip were to write into the same ring, cache line
3316 * eviction could occur since both entities want it in an exclusive state.
3317 */
3318 static int tg3_rx(struct tg3 *tp, int budget)
3319 {
3320 u32 work_mask, rx_std_posted = 0;
3321 u32 sw_idx = tp->rx_rcb_ptr;
3322 u16 hw_idx;
3323 int received;
3324
3325 hw_idx = tp->hw_status->idx[0].rx_producer;
3326 /*
3327 * We need to order the read of hw_idx and the read of
3328 * the opaque cookie.
3329 */
3330 rmb();
3331 work_mask = 0;
3332 received = 0;
3333 while (sw_idx != hw_idx && budget > 0) {
3334 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3335 unsigned int len;
3336 struct sk_buff *skb;
3337 dma_addr_t dma_addr;
3338 u32 opaque_key, desc_idx, *post_ptr;
3339
3340 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3341 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3342 if (opaque_key == RXD_OPAQUE_RING_STD) {
3343 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3344 mapping);
3345 skb = tp->rx_std_buffers[desc_idx].skb;
3346 post_ptr = &tp->rx_std_ptr;
3347 rx_std_posted++;
3348 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3349 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3350 mapping);
3351 skb = tp->rx_jumbo_buffers[desc_idx].skb;
3352 post_ptr = &tp->rx_jumbo_ptr;
3353 }
3354 else {
3355 goto next_pkt_nopost;
3356 }
3357
3358 work_mask |= opaque_key;
3359
3360 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3361 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3362 drop_it:
3363 tg3_recycle_rx(tp, opaque_key,
3364 desc_idx, *post_ptr);
3365 drop_it_no_recycle:
3366 /* Other statistics kept track of by card. */
3367 tp->net_stats.rx_dropped++;
3368 goto next_pkt;
3369 }
3370
3371 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3372
3373 if (len > RX_COPY_THRESHOLD
3374 && tp->rx_offset == 2
3375 /* rx_offset != 2 iff this is a 5701 card running
3376 * in PCI-X mode [see tg3_get_invariants()] */
3377 ) {
3378 int skb_size;
3379
3380 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3381 desc_idx, *post_ptr);
3382 if (skb_size < 0)
3383 goto drop_it;
3384
3385 pci_unmap_single(tp->pdev, dma_addr,
3386 skb_size - tp->rx_offset,
3387 PCI_DMA_FROMDEVICE);
3388
3389 skb_put(skb, len);
3390 } else {
3391 struct sk_buff *copy_skb;
3392
3393 tg3_recycle_rx(tp, opaque_key,
3394 desc_idx, *post_ptr);
3395
3396 copy_skb = netdev_alloc_skb(tp->dev, len + 2);
3397 if (copy_skb == NULL)
3398 goto drop_it_no_recycle;
3399
3400 skb_reserve(copy_skb, 2);
3401 skb_put(copy_skb, len);
3402 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3403 skb_copy_from_linear_data(skb, copy_skb->data, len);
3404 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3405
3406 /* We'll reuse the original ring buffer. */
3407 skb = copy_skb;
3408 }
3409
3410 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3411 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3412 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3413 >> RXD_TCPCSUM_SHIFT) == 0xffff))
3414 skb->ip_summed = CHECKSUM_UNNECESSARY;
3415 else
3416 skb->ip_summed = CHECKSUM_NONE;
3417
3418 skb->protocol = eth_type_trans(skb, tp->dev);
3419 #if TG3_VLAN_TAG_USED
3420 if (tp->vlgrp != NULL &&
3421 desc->type_flags & RXD_FLAG_VLAN) {
3422 tg3_vlan_rx(tp, skb,
3423 desc->err_vlan & RXD_VLAN_MASK);
3424 } else
3425 #endif
3426 netif_receive_skb(skb);
3427
3428 tp->dev->last_rx = jiffies;
3429 received++;
3430 budget--;
3431
3432 next_pkt:
3433 (*post_ptr)++;
3434
3435 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3436 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3437
3438 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3439 TG3_64BIT_REG_LOW, idx);
3440 work_mask &= ~RXD_OPAQUE_RING_STD;
3441 rx_std_posted = 0;
3442 }
3443 next_pkt_nopost:
3444 sw_idx++;
3445 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
3446
3447 /* Refresh hw_idx to see if there is new work */
3448 if (sw_idx == hw_idx) {
3449 hw_idx = tp->hw_status->idx[0].rx_producer;
3450 rmb();
3451 }
3452 }
3453
3454 /* ACK the status ring. */
3455 tp->rx_rcb_ptr = sw_idx;
3456 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3457
3458 /* Refill RX ring(s). */
3459 if (work_mask & RXD_OPAQUE_RING_STD) {
3460 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3461 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3462 sw_idx);
3463 }
3464 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3465 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3466 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3467 sw_idx);
3468 }
3469 mmiowb();
3470
3471 return received;
3472 }
3473
3474 static int tg3_poll(struct napi_struct *napi, int budget)
3475 {
3476 struct tg3 *tp = container_of(napi, struct tg3, napi);
3477 struct net_device *netdev = tp->dev;
3478 struct tg3_hw_status *sblk = tp->hw_status;
3479 int work_done = 0;
3480
3481 /* handle link change and other phy events */
3482 if (!(tp->tg3_flags &
3483 (TG3_FLAG_USE_LINKCHG_REG |
3484 TG3_FLAG_POLL_SERDES))) {
3485 if (sblk->status & SD_STATUS_LINK_CHG) {
3486 sblk->status = SD_STATUS_UPDATED |
3487 (sblk->status & ~SD_STATUS_LINK_CHG);
3488 spin_lock(&tp->lock);
3489 tg3_setup_phy(tp, 0);
3490 spin_unlock(&tp->lock);
3491 }
3492 }
3493
3494 /* run TX completion thread */
3495 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3496 tg3_tx(tp);
3497 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) {
3498 netif_rx_complete(netdev, napi);
3499 schedule_work(&tp->reset_task);
3500 return 0;
3501 }
3502 }
3503
3504 /* run RX thread, within the bounds set by NAPI.
3505 * All RX "locking" is done by ensuring outside
3506 * code synchronizes with tg3->napi.poll()
3507 */
3508 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
3509 work_done = tg3_rx(tp, budget);
3510
3511 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3512 tp->last_tag = sblk->status_tag;
3513 rmb();
3514 } else
3515 sblk->status &= ~SD_STATUS_UPDATED;
3516
3517 /* if no more work, tell net stack and NIC we're done */
3518 if (!tg3_has_work(tp)) {
3519 netif_rx_complete(netdev, napi);
3520 tg3_restart_ints(tp);
3521 }
3522
3523 return work_done;
3524 }
3525
3526 static void tg3_irq_quiesce(struct tg3 *tp)
3527 {
3528 BUG_ON(tp->irq_sync);
3529
3530 tp->irq_sync = 1;
3531 smp_mb();
3532
3533 synchronize_irq(tp->pdev->irq);
3534 }
3535
3536 static inline int tg3_irq_sync(struct tg3 *tp)
3537 {
3538 return tp->irq_sync;
3539 }
3540
3541 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3542 * If irq_sync is non-zero, then the IRQ handler must be synchronized
3543 * with as well. Most of the time, this is not necessary except when
3544 * shutting down the device.
3545 */
3546 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3547 {
3548 spin_lock_bh(&tp->lock);
3549 if (irq_sync)
3550 tg3_irq_quiesce(tp);
3551 }
3552
3553 static inline void tg3_full_unlock(struct tg3 *tp)
3554 {
3555 spin_unlock_bh(&tp->lock);
3556 }
3557
3558 /* One-shot MSI handler - Chip automatically disables interrupt
3559 * after sending MSI so driver doesn't have to do it.
3560 */
3561 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
3562 {
3563 struct net_device *dev = dev_id;
3564 struct tg3 *tp = netdev_priv(dev);
3565
3566 prefetch(tp->hw_status);
3567 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3568
3569 if (likely(!tg3_irq_sync(tp)))
3570 netif_rx_schedule(dev, &tp->napi);
3571
3572 return IRQ_HANDLED;
3573 }
3574
3575 /* MSI ISR - No need to check for interrupt sharing and no need to
3576 * flush status block and interrupt mailbox. PCI ordering rules
3577 * guarantee that MSI will arrive after the status block.
3578 */
3579 static irqreturn_t tg3_msi(int irq, void *dev_id)
3580 {
3581 struct net_device *dev = dev_id;
3582 struct tg3 *tp = netdev_priv(dev);
3583
3584 prefetch(tp->hw_status);
3585 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3586 /*
3587 * Writing any value to intr-mbox-0 clears PCI INTA# and
3588 * chip-internal interrupt pending events.
3589 * Writing non-zero to intr-mbox-0 additional tells the
3590 * NIC to stop sending us irqs, engaging "in-intr-handler"
3591 * event coalescing.
3592 */
3593 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3594 if (likely(!tg3_irq_sync(tp)))
3595 netif_rx_schedule(dev, &tp->napi);
3596
3597 return IRQ_RETVAL(1);
3598 }
3599
3600 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
3601 {
3602 struct net_device *dev = dev_id;
3603 struct tg3 *tp = netdev_priv(dev);
3604 struct tg3_hw_status *sblk = tp->hw_status;
3605 unsigned int handled = 1;
3606
3607 /* In INTx mode, it is possible for the interrupt to arrive at
3608 * the CPU before the status block posted prior to the interrupt.
3609 * Reading the PCI State register will confirm whether the
3610 * interrupt is ours and will flush the status block.
3611 */
3612 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
3613 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3614 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3615 handled = 0;
3616 goto out;
3617 }
3618 }
3619
3620 /*
3621 * Writing any value to intr-mbox-0 clears PCI INTA# and
3622 * chip-internal interrupt pending events.
3623 * Writing non-zero to intr-mbox-0 additional tells the
3624 * NIC to stop sending us irqs, engaging "in-intr-handler"
3625 * event coalescing.
3626 *
3627 * Flush the mailbox to de-assert the IRQ immediately to prevent
3628 * spurious interrupts. The flush impacts performance but
3629 * excessive spurious interrupts can be worse in some cases.
3630 */
3631 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3632 if (tg3_irq_sync(tp))
3633 goto out;
3634 sblk->status &= ~SD_STATUS_UPDATED;
3635 if (likely(tg3_has_work(tp))) {
3636 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3637 netif_rx_schedule(dev, &tp->napi);
3638 } else {
3639 /* No work, shared interrupt perhaps? re-enable
3640 * interrupts, and flush that PCI write
3641 */
3642 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3643 0x00000000);
3644 }
3645 out:
3646 return IRQ_RETVAL(handled);
3647 }
3648
3649 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
3650 {
3651 struct net_device *dev = dev_id;
3652 struct tg3 *tp = netdev_priv(dev);
3653 struct tg3_hw_status *sblk = tp->hw_status;
3654 unsigned int handled = 1;
3655
3656 /* In INTx mode, it is possible for the interrupt to arrive at
3657 * the CPU before the status block posted prior to the interrupt.
3658 * Reading the PCI State register will confirm whether the
3659 * interrupt is ours and will flush the status block.
3660 */
3661 if (unlikely(sblk->status_tag == tp->last_tag)) {
3662 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3663 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3664 handled = 0;
3665 goto out;
3666 }
3667 }
3668
3669 /*
3670 * writing any value to intr-mbox-0 clears PCI INTA# and
3671 * chip-internal interrupt pending events.
3672 * writing non-zero to intr-mbox-0 additional tells the
3673 * NIC to stop sending us irqs, engaging "in-intr-handler"
3674 * event coalescing.
3675 *
3676 * Flush the mailbox to de-assert the IRQ immediately to prevent
3677 * spurious interrupts. The flush impacts performance but
3678 * excessive spurious interrupts can be worse in some cases.
3679 */
3680 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3681 if (tg3_irq_sync(tp))
3682 goto out;
3683 if (netif_rx_schedule_prep(dev, &tp->napi)) {
3684 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3685 /* Update last_tag to mark that this status has been
3686 * seen. Because interrupt may be shared, we may be
3687 * racing with tg3_poll(), so only update last_tag
3688 * if tg3_poll() is not scheduled.
3689 */
3690 tp->last_tag = sblk->status_tag;
3691 __netif_rx_schedule(dev, &tp->napi);
3692 }
3693 out:
3694 return IRQ_RETVAL(handled);
3695 }
3696
3697 /* ISR for interrupt test */
3698 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
3699 {
3700 struct net_device *dev = dev_id;
3701 struct tg3 *tp = netdev_priv(dev);
3702 struct tg3_hw_status *sblk = tp->hw_status;
3703
3704 if ((sblk->status & SD_STATUS_UPDATED) ||
3705 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3706 tg3_disable_ints(tp);
3707 return IRQ_RETVAL(1);
3708 }
3709 return IRQ_RETVAL(0);
3710 }
3711
3712 static int tg3_init_hw(struct tg3 *, int);
3713 static int tg3_halt(struct tg3 *, int, int);
3714
3715 /* Restart hardware after configuration changes, self-test, etc.
3716 * Invoked with tp->lock held.
3717 */
3718 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
3719 {
3720 int err;
3721
3722 err = tg3_init_hw(tp, reset_phy);
3723 if (err) {
3724 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
3725 "aborting.\n", tp->dev->name);
3726 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3727 tg3_full_unlock(tp);
3728 del_timer_sync(&tp->timer);
3729 tp->irq_sync = 0;
3730 napi_enable(&tp->napi);
3731 dev_close(tp->dev);
3732 tg3_full_lock(tp, 0);
3733 }
3734 return err;
3735 }
3736
3737 #ifdef CONFIG_NET_POLL_CONTROLLER
3738 static void tg3_poll_controller(struct net_device *dev)
3739 {
3740 struct tg3 *tp = netdev_priv(dev);
3741
3742 tg3_interrupt(tp->pdev->irq, dev);
3743 }
3744 #endif
3745
3746 static void tg3_reset_task(struct work_struct *work)
3747 {
3748 struct tg3 *tp = container_of(work, struct tg3, reset_task);
3749 unsigned int restart_timer;
3750
3751 tg3_full_lock(tp, 0);
3752
3753 if (!netif_running(tp->dev)) {
3754 tg3_full_unlock(tp);
3755 return;
3756 }
3757
3758 tg3_full_unlock(tp);
3759
3760 tg3_netif_stop(tp);
3761
3762 tg3_full_lock(tp, 1);
3763
3764 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3765 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3766
3767 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
3768 tp->write32_tx_mbox = tg3_write32_tx_mbox;
3769 tp->write32_rx_mbox = tg3_write_flush_reg32;
3770 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
3771 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
3772 }
3773
3774 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3775 if (tg3_init_hw(tp, 1))
3776 goto out;
3777
3778 tg3_netif_start(tp);
3779
3780 if (restart_timer)
3781 mod_timer(&tp->timer, jiffies + 1);
3782
3783 out:
3784 tg3_full_unlock(tp);
3785 }
3786
3787 static void tg3_dump_short_state(struct tg3 *tp)
3788 {
3789 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
3790 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
3791 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
3792 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
3793 }
3794
3795 static void tg3_tx_timeout(struct net_device *dev)
3796 {
3797 struct tg3 *tp = netdev_priv(dev);
3798
3799 if (netif_msg_tx_err(tp)) {
3800 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3801 dev->name);
3802 tg3_dump_short_state(tp);
3803 }
3804
3805 schedule_work(&tp->reset_task);
3806 }
3807
3808 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3809 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3810 {
3811 u32 base = (u32) mapping & 0xffffffff;
3812
3813 return ((base > 0xffffdcc0) &&
3814 (base + len + 8 < base));
3815 }
3816
3817 /* Test for DMA addresses > 40-bit */
3818 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
3819 int len)
3820 {
3821 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
3822 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
3823 return (((u64) mapping + len) > DMA_40BIT_MASK);
3824 return 0;
3825 #else
3826 return 0;
3827 #endif
3828 }
3829
3830 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3831
3832 /* Workaround 4GB and 40-bit hardware DMA bugs. */
3833 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3834 u32 last_plus_one, u32 *start,
3835 u32 base_flags, u32 mss)
3836 {
3837 struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3838 dma_addr_t new_addr = 0;
3839 u32 entry = *start;
3840 int i, ret = 0;
3841
3842 if (!new_skb) {
3843 ret = -1;
3844 } else {
3845 /* New SKB is guaranteed to be linear. */
3846 entry = *start;
3847 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3848 PCI_DMA_TODEVICE);
3849 /* Make sure new skb does not cross any 4G boundaries.
3850 * Drop the packet if it does.
3851 */
3852 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3853 ret = -1;
3854 dev_kfree_skb(new_skb);
3855 new_skb = NULL;
3856 } else {
3857 tg3_set_txd(tp, entry, new_addr, new_skb->len,
3858 base_flags, 1 | (mss << 1));
3859 *start = NEXT_TX(entry);
3860 }
3861 }
3862
3863 /* Now clean up the sw ring entries. */
3864 i = 0;
3865 while (entry != last_plus_one) {
3866 int len;
3867
3868 if (i == 0)
3869 len = skb_headlen(skb);
3870 else
3871 len = skb_shinfo(skb)->frags[i-1].size;
3872 pci_unmap_single(tp->pdev,
3873 pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3874 len, PCI_DMA_TODEVICE);
3875 if (i == 0) {
3876 tp->tx_buffers[entry].skb = new_skb;
3877 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3878 } else {
3879 tp->tx_buffers[entry].skb = NULL;
3880 }
3881 entry = NEXT_TX(entry);
3882 i++;
3883 }
3884
3885 dev_kfree_skb(skb);
3886
3887 return ret;
3888 }
3889
3890 static void tg3_set_txd(struct tg3 *tp, int entry,
3891 dma_addr_t mapping, int len, u32 flags,
3892 u32 mss_and_is_end)
3893 {
3894 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3895 int is_end = (mss_and_is_end & 0x1);
3896 u32 mss = (mss_and_is_end >> 1);
3897 u32 vlan_tag = 0;
3898
3899 if (is_end)
3900 flags |= TXD_FLAG_END;
3901 if (flags & TXD_FLAG_VLAN) {
3902 vlan_tag = flags >> 16;
3903 flags &= 0xffff;
3904 }
3905 vlan_tag |= (mss << TXD_MSS_SHIFT);
3906
3907 txd->addr_hi = ((u64) mapping >> 32);
3908 txd->addr_lo = ((u64) mapping & 0xffffffff);
3909 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3910 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3911 }
3912
3913 /* hard_start_xmit for devices that don't have any bugs and
3914 * support TG3_FLG2_HW_TSO_2 only.
3915 */
3916 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3917 {
3918 struct tg3 *tp = netdev_priv(dev);
3919 dma_addr_t mapping;
3920 u32 len, entry, base_flags, mss;
3921
3922 len = skb_headlen(skb);
3923
3924 /* We are running in BH disabled context with netif_tx_lock
3925 * and TX reclaim runs via tp->napi.poll inside of a software
3926 * interrupt. Furthermore, IRQ processing runs lockless so we have
3927 * no IRQ context deadlocks to worry about either. Rejoice!
3928 */
3929 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3930 if (!netif_queue_stopped(dev)) {
3931 netif_stop_queue(dev);
3932
3933 /* This is a hard error, log it. */
3934 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3935 "queue awake!\n", dev->name);
3936 }
3937 return NETDEV_TX_BUSY;
3938 }
3939
3940 entry = tp->tx_prod;
3941 base_flags = 0;
3942 mss = 0;
3943 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
3944 int tcp_opt_len, ip_tcp_len;
3945
3946 if (skb_header_cloned(skb) &&
3947 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3948 dev_kfree_skb(skb);
3949 goto out_unlock;
3950 }
3951
3952 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
3953 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
3954 else {
3955 struct iphdr *iph = ip_hdr(skb);
3956
3957 tcp_opt_len = tcp_optlen(skb);
3958 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
3959
3960 iph->check = 0;
3961 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
3962 mss |= (ip_tcp_len + tcp_opt_len) << 9;
3963 }
3964
3965 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3966 TXD_FLAG_CPU_POST_DMA);
3967
3968 tcp_hdr(skb)->check = 0;
3969
3970 }
3971 else if (skb->ip_summed == CHECKSUM_PARTIAL)
3972 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3973 #if TG3_VLAN_TAG_USED
3974 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3975 base_flags |= (TXD_FLAG_VLAN |
3976 (vlan_tx_tag_get(skb) << 16));
3977 #endif
3978
3979 /* Queue skb data, a.k.a. the main skb fragment. */
3980 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3981
3982 tp->tx_buffers[entry].skb = skb;
3983 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3984
3985 tg3_set_txd(tp, entry, mapping, len, base_flags,
3986 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3987
3988 entry = NEXT_TX(entry);
3989
3990 /* Now loop through additional data fragments, and queue them. */
3991 if (skb_shinfo(skb)->nr_frags > 0) {
3992 unsigned int i, last;
3993
3994 last = skb_shinfo(skb)->nr_frags - 1;
3995 for (i = 0; i <= last; i++) {
3996 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3997
3998 len = frag->size;
3999 mapping = pci_map_page(tp->pdev,
4000 frag->page,
4001 frag->page_offset,
4002 len, PCI_DMA_TODEVICE);
4003
4004 tp->tx_buffers[entry].skb = NULL;
4005 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4006
4007 tg3_set_txd(tp, entry, mapping, len,
4008 base_flags, (i == last) | (mss << 1));
4009
4010 entry = NEXT_TX(entry);
4011 }
4012 }
4013
4014 /* Packets are ready, update Tx producer idx local and on card. */
4015 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4016
4017 tp->tx_prod = entry;
4018 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4019 netif_stop_queue(dev);
4020 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4021 netif_wake_queue(tp->dev);
4022 }
4023
4024 out_unlock:
4025 mmiowb();
4026
4027 dev->trans_start = jiffies;
4028
4029 return NETDEV_TX_OK;
4030 }
4031
4032 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
4033
4034 /* Use GSO to workaround a rare TSO bug that may be triggered when the
4035 * TSO header is greater than 80 bytes.
4036 */
4037 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
4038 {
4039 struct sk_buff *segs, *nskb;
4040
4041 /* Estimate the number of fragments in the worst case */
4042 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
4043 netif_stop_queue(tp->dev);
4044 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
4045 return NETDEV_TX_BUSY;
4046
4047 netif_wake_queue(tp->dev);
4048 }
4049
4050 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
4051 if (unlikely(IS_ERR(segs)))
4052 goto tg3_tso_bug_end;
4053
4054 do {
4055 nskb = segs;
4056 segs = segs->next;
4057 nskb->next = NULL;
4058 tg3_start_xmit_dma_bug(nskb, tp->dev);
4059 } while (segs);
4060
4061 tg3_tso_bug_end:
4062 dev_kfree_skb(skb);
4063
4064 return NETDEV_TX_OK;
4065 }
4066
4067 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
4068 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
4069 */
4070 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
4071 {
4072 struct tg3 *tp = netdev_priv(dev);
4073 dma_addr_t mapping;
4074 u32 len, entry, base_flags, mss;
4075 int would_hit_hwbug;
4076
4077 len = skb_headlen(skb);
4078
4079 /* We are running in BH disabled context with netif_tx_lock
4080 * and TX reclaim runs via tp->napi.poll inside of a software
4081 * interrupt. Furthermore, IRQ processing runs lockless so we have
4082 * no IRQ context deadlocks to worry about either. Rejoice!
4083 */
4084 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4085 if (!netif_queue_stopped(dev)) {
4086 netif_stop_queue(dev);
4087
4088 /* This is a hard error, log it. */
4089 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4090 "queue awake!\n", dev->name);
4091 }
4092 return NETDEV_TX_BUSY;
4093 }
4094
4095 entry = tp->tx_prod;
4096 base_flags = 0;
4097 if (skb->ip_summed == CHECKSUM_PARTIAL)
4098 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4099 mss = 0;
4100 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4101 struct iphdr *iph;
4102 int tcp_opt_len, ip_tcp_len, hdr_len;
4103
4104 if (skb_header_cloned(skb) &&
4105 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4106 dev_kfree_skb(skb);
4107 goto out_unlock;
4108 }
4109
4110 tcp_opt_len = tcp_optlen(skb);
4111 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4112
4113 hdr_len = ip_tcp_len + tcp_opt_len;
4114 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4115 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
4116 return (tg3_tso_bug(tp, skb));
4117
4118 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4119 TXD_FLAG_CPU_POST_DMA);
4120
4121 iph = ip_hdr(skb);
4122 iph->check = 0;
4123 iph->tot_len = htons(mss + hdr_len);
4124 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4125 tcp_hdr(skb)->check = 0;
4126 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4127 } else
4128 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4129 iph->daddr, 0,
4130 IPPROTO_TCP,
4131 0);
4132
4133 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4134 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4135 if (tcp_opt_len || iph->ihl > 5) {
4136 int tsflags;
4137
4138 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4139 mss |= (tsflags << 11);
4140 }
4141 } else {
4142 if (tcp_opt_len || iph->ihl > 5) {
4143 int tsflags;
4144
4145 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4146 base_flags |= tsflags << 12;
4147 }
4148 }
4149 }
4150 #if TG3_VLAN_TAG_USED
4151 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4152 base_flags |= (TXD_FLAG_VLAN |
4153 (vlan_tx_tag_get(skb) << 16));
4154 #endif
4155
4156 /* Queue skb data, a.k.a. the main skb fragment. */
4157 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4158
4159 tp->tx_buffers[entry].skb = skb;
4160 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4161
4162 would_hit_hwbug = 0;
4163
4164 if (tg3_4g_overflow_test(mapping, len))
4165 would_hit_hwbug = 1;
4166
4167 tg3_set_txd(tp, entry, mapping, len, base_flags,
4168 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4169
4170 entry = NEXT_TX(entry);
4171
4172 /* Now loop through additional data fragments, and queue them. */
4173 if (skb_shinfo(skb)->nr_frags > 0) {
4174 unsigned int i, last;
4175
4176 last = skb_shinfo(skb)->nr_frags - 1;
4177 for (i = 0; i <= last; i++) {
4178 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4179
4180 len = frag->size;
4181 mapping = pci_map_page(tp->pdev,
4182 frag->page,
4183 frag->page_offset,
4184 len, PCI_DMA_TODEVICE);
4185
4186 tp->tx_buffers[entry].skb = NULL;
4187 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4188
4189 if (tg3_4g_overflow_test(mapping, len))
4190 would_hit_hwbug = 1;
4191
4192 if (tg3_40bit_overflow_test(tp, mapping, len))
4193 would_hit_hwbug = 1;
4194
4195 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4196 tg3_set_txd(tp, entry, mapping, len,
4197 base_flags, (i == last)|(mss << 1));
4198 else
4199 tg3_set_txd(tp, entry, mapping, len,
4200 base_flags, (i == last));
4201
4202 entry = NEXT_TX(entry);
4203 }
4204 }
4205
4206 if (would_hit_hwbug) {
4207 u32 last_plus_one = entry;
4208 u32 start;
4209
4210 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4211 start &= (TG3_TX_RING_SIZE - 1);
4212
4213 /* If the workaround fails due to memory/mapping
4214 * failure, silently drop this packet.
4215 */
4216 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4217 &start, base_flags, mss))
4218 goto out_unlock;
4219
4220 entry = start;
4221 }
4222
4223 /* Packets are ready, update Tx producer idx local and on card. */
4224 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4225
4226 tp->tx_prod = entry;
4227 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4228 netif_stop_queue(dev);
4229 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4230 netif_wake_queue(tp->dev);
4231 }
4232
4233 out_unlock:
4234 mmiowb();
4235
4236 dev->trans_start = jiffies;
4237
4238 return NETDEV_TX_OK;
4239 }
4240
4241 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4242 int new_mtu)
4243 {
4244 dev->mtu = new_mtu;
4245
4246 if (new_mtu > ETH_DATA_LEN) {
4247 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4248 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4249 ethtool_op_set_tso(dev, 0);
4250 }
4251 else
4252 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4253 } else {
4254 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4255 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4256 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4257 }
4258 }
4259
4260 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4261 {
4262 struct tg3 *tp = netdev_priv(dev);
4263 int err;
4264
4265 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4266 return -EINVAL;
4267
4268 if (!netif_running(dev)) {
4269 /* We'll just catch it later when the
4270 * device is up'd.
4271 */
4272 tg3_set_mtu(dev, tp, new_mtu);
4273 return 0;
4274 }
4275
4276 tg3_netif_stop(tp);
4277
4278 tg3_full_lock(tp, 1);
4279
4280 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4281
4282 tg3_set_mtu(dev, tp, new_mtu);
4283
4284 err = tg3_restart_hw(tp, 0);
4285
4286 if (!err)
4287 tg3_netif_start(tp);
4288
4289 tg3_full_unlock(tp);
4290
4291 return err;
4292 }
4293
4294 /* Free up pending packets in all rx/tx rings.
4295 *
4296 * The chip has been shut down and the driver detached from
4297 * the networking, so no interrupts or new tx packets will
4298 * end up in the driver. tp->{tx,}lock is not held and we are not
4299 * in an interrupt context and thus may sleep.
4300 */
4301 static void tg3_free_rings(struct tg3 *tp)
4302 {
4303 struct ring_info *rxp;
4304 int i;
4305
4306 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4307 rxp = &tp->rx_std_buffers[i];
4308
4309 if (rxp->skb == NULL)
4310 continue;
4311 pci_unmap_single(tp->pdev,
4312 pci_unmap_addr(rxp, mapping),
4313 tp->rx_pkt_buf_sz - tp->rx_offset,
4314 PCI_DMA_FROMDEVICE);
4315 dev_kfree_skb_any(rxp->skb);
4316 rxp->skb = NULL;
4317 }
4318
4319 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4320 rxp = &tp->rx_jumbo_buffers[i];
4321
4322 if (rxp->skb == NULL)
4323 continue;
4324 pci_unmap_single(tp->pdev,
4325 pci_unmap_addr(rxp, mapping),
4326 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4327 PCI_DMA_FROMDEVICE);
4328 dev_kfree_skb_any(rxp->skb);
4329 rxp->skb = NULL;
4330 }
4331
4332 for (i = 0; i < TG3_TX_RING_SIZE; ) {
4333 struct tx_ring_info *txp;
4334 struct sk_buff *skb;
4335 int j;
4336
4337 txp = &tp->tx_buffers[i];
4338 skb = txp->skb;
4339
4340 if (skb == NULL) {
4341 i++;
4342 continue;
4343 }
4344
4345 pci_unmap_single(tp->pdev,
4346 pci_unmap_addr(txp, mapping),
4347 skb_headlen(skb),
4348 PCI_DMA_TODEVICE);
4349 txp->skb = NULL;
4350
4351 i++;
4352
4353 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4354 txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4355 pci_unmap_page(tp->pdev,
4356 pci_unmap_addr(txp, mapping),
4357 skb_shinfo(skb)->frags[j].size,
4358 PCI_DMA_TODEVICE);
4359 i++;
4360 }
4361
4362 dev_kfree_skb_any(skb);
4363 }
4364 }
4365
4366 /* Initialize tx/rx rings for packet processing.
4367 *
4368 * The chip has been shut down and the driver detached from
4369 * the networking, so no interrupts or new tx packets will
4370 * end up in the driver. tp->{tx,}lock are held and thus
4371 * we may not sleep.
4372 */
4373 static int tg3_init_rings(struct tg3 *tp)
4374 {
4375 u32 i;
4376
4377 /* Free up all the SKBs. */
4378 tg3_free_rings(tp);
4379
4380 /* Zero out all descriptors. */
4381 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4382 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4383 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4384 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4385
4386 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
4387 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
4388 (tp->dev->mtu > ETH_DATA_LEN))
4389 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4390
4391 /* Initialize invariants of the rings, we only set this
4392 * stuff once. This works because the card does not
4393 * write into the rx buffer posting rings.
4394 */
4395 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4396 struct tg3_rx_buffer_desc *rxd;
4397
4398 rxd = &tp->rx_std[i];
4399 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
4400 << RXD_LEN_SHIFT;
4401 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4402 rxd->opaque = (RXD_OPAQUE_RING_STD |
4403 (i << RXD_OPAQUE_INDEX_SHIFT));
4404 }
4405
4406 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4407 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4408 struct tg3_rx_buffer_desc *rxd;
4409
4410 rxd = &tp->rx_jumbo[i];
4411 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4412 << RXD_LEN_SHIFT;
4413 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4414 RXD_FLAG_JUMBO;
4415 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4416 (i << RXD_OPAQUE_INDEX_SHIFT));
4417 }
4418 }
4419
4420 /* Now allocate fresh SKBs for each rx ring. */
4421 for (i = 0; i < tp->rx_pending; i++) {
4422 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4423 printk(KERN_WARNING PFX
4424 "%s: Using a smaller RX standard ring, "
4425 "only %d out of %d buffers were allocated "
4426 "successfully.\n",
4427 tp->dev->name, i, tp->rx_pending);
4428 if (i == 0)
4429 return -ENOMEM;
4430 tp->rx_pending = i;
4431 break;
4432 }
4433 }
4434
4435 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4436 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4437 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
4438 -1, i) < 0) {
4439 printk(KERN_WARNING PFX
4440 "%s: Using a smaller RX jumbo ring, "
4441 "only %d out of %d buffers were "
4442 "allocated successfully.\n",
4443 tp->dev->name, i, tp->rx_jumbo_pending);
4444 if (i == 0) {
4445 tg3_free_rings(tp);
4446 return -ENOMEM;
4447 }
4448 tp->rx_jumbo_pending = i;
4449 break;
4450 }
4451 }
4452 }
4453 return 0;
4454 }
4455
4456 /*
4457 * Must not be invoked with interrupt sources disabled and
4458 * the hardware shutdown down.
4459 */
4460 static void tg3_free_consistent(struct tg3 *tp)
4461 {
4462 kfree(tp->rx_std_buffers);
4463 tp->rx_std_buffers = NULL;
4464 if (tp->rx_std) {
4465 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4466 tp->rx_std, tp->rx_std_mapping);
4467 tp->rx_std = NULL;
4468 }
4469 if (tp->rx_jumbo) {
4470 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4471 tp->rx_jumbo, tp->rx_jumbo_mapping);
4472 tp->rx_jumbo = NULL;
4473 }
4474 if (tp->rx_rcb) {
4475 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4476 tp->rx_rcb, tp->rx_rcb_mapping);
4477 tp->rx_rcb = NULL;
4478 }
4479 if (tp->tx_ring) {
4480 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4481 tp->tx_ring, tp->tx_desc_mapping);
4482 tp->tx_ring = NULL;
4483 }
4484 if (tp->hw_status) {
4485 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4486 tp->hw_status, tp->status_mapping);
4487 tp->hw_status = NULL;
4488 }
4489 if (tp->hw_stats) {
4490 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4491 tp->hw_stats, tp->stats_mapping);
4492 tp->hw_stats = NULL;
4493 }
4494 }
4495
4496 /*
4497 * Must not be invoked with interrupt sources disabled and
4498 * the hardware shutdown down. Can sleep.
4499 */
4500 static int tg3_alloc_consistent(struct tg3 *tp)
4501 {
4502 tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
4503 (TG3_RX_RING_SIZE +
4504 TG3_RX_JUMBO_RING_SIZE)) +
4505 (sizeof(struct tx_ring_info) *
4506 TG3_TX_RING_SIZE),
4507 GFP_KERNEL);
4508 if (!tp->rx_std_buffers)
4509 return -ENOMEM;
4510
4511 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4512 tp->tx_buffers = (struct tx_ring_info *)
4513 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4514
4515 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4516 &tp->rx_std_mapping);
4517 if (!tp->rx_std)
4518 goto err_out;
4519
4520 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4521 &tp->rx_jumbo_mapping);
4522
4523 if (!tp->rx_jumbo)
4524 goto err_out;
4525
4526 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4527 &tp->rx_rcb_mapping);
4528 if (!tp->rx_rcb)
4529 goto err_out;
4530
4531 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4532 &tp->tx_desc_mapping);
4533 if (!tp->tx_ring)
4534 goto err_out;
4535
4536 tp->hw_status = pci_alloc_consistent(tp->pdev,
4537 TG3_HW_STATUS_SIZE,
4538 &tp->status_mapping);
4539 if (!tp->hw_status)
4540 goto err_out;
4541
4542 tp->hw_stats = pci_alloc_consistent(tp->pdev,
4543 sizeof(struct tg3_hw_stats),
4544 &tp->stats_mapping);
4545 if (!tp->hw_stats)
4546 goto err_out;
4547
4548 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4549 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4550
4551 return 0;
4552
4553 err_out:
4554 tg3_free_consistent(tp);
4555 return -ENOMEM;
4556 }
4557
4558 #define MAX_WAIT_CNT 1000
4559
4560 /* To stop a block, clear the enable bit and poll till it
4561 * clears. tp->lock is held.
4562 */
4563 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4564 {
4565 unsigned int i;
4566 u32 val;
4567
4568 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4569 switch (ofs) {
4570 case RCVLSC_MODE:
4571 case DMAC_MODE:
4572 case MBFREE_MODE:
4573 case BUFMGR_MODE:
4574 case MEMARB_MODE:
4575 /* We can't enable/disable these bits of the
4576 * 5705/5750, just say success.
4577 */
4578 return 0;
4579
4580 default:
4581 break;
4582 };
4583 }
4584
4585 val = tr32(ofs);
4586 val &= ~enable_bit;
4587 tw32_f(ofs, val);
4588
4589 for (i = 0; i < MAX_WAIT_CNT; i++) {
4590 udelay(100);
4591 val = tr32(ofs);
4592 if ((val & enable_bit) == 0)
4593 break;
4594 }
4595
4596 if (i == MAX_WAIT_CNT && !silent) {
4597 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4598 "ofs=%lx enable_bit=%x\n",
4599 ofs, enable_bit);
4600 return -ENODEV;
4601 }
4602
4603 return 0;
4604 }
4605
4606 /* tp->lock is held. */
4607 static int tg3_abort_hw(struct tg3 *tp, int silent)
4608 {
4609 int i, err;
4610
4611 tg3_disable_ints(tp);
4612
4613 tp->rx_mode &= ~RX_MODE_ENABLE;
4614 tw32_f(MAC_RX_MODE, tp->rx_mode);
4615 udelay(10);
4616
4617 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4618 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4619 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4620 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4621 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4622 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4623
4624 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4625 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4626 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4627 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4628 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4629 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4630 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
4631
4632 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4633 tw32_f(MAC_MODE, tp->mac_mode);
4634 udelay(40);
4635
4636 tp->tx_mode &= ~TX_MODE_ENABLE;
4637 tw32_f(MAC_TX_MODE, tp->tx_mode);
4638
4639 for (i = 0; i < MAX_WAIT_CNT; i++) {
4640 udelay(100);
4641 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4642 break;
4643 }
4644 if (i >= MAX_WAIT_CNT) {
4645 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4646 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4647 tp->dev->name, tr32(MAC_TX_MODE));
4648 err |= -ENODEV;
4649 }
4650
4651 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
4652 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4653 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
4654
4655 tw32(FTQ_RESET, 0xffffffff);
4656 tw32(FTQ_RESET, 0x00000000);
4657
4658 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4659 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
4660
4661 if (tp->hw_status)
4662 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4663 if (tp->hw_stats)
4664 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4665
4666 return err;
4667 }
4668
4669 /* tp->lock is held. */
4670 static int tg3_nvram_lock(struct tg3 *tp)
4671 {
4672 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4673 int i;
4674
4675 if (tp->nvram_lock_cnt == 0) {
4676 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4677 for (i = 0; i < 8000; i++) {
4678 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4679 break;
4680 udelay(20);
4681 }
4682 if (i == 8000) {
4683 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4684 return -ENODEV;
4685 }
4686 }
4687 tp->nvram_lock_cnt++;
4688 }
4689 return 0;
4690 }
4691
4692 /* tp->lock is held. */
4693 static void tg3_nvram_unlock(struct tg3 *tp)
4694 {
4695 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4696 if (tp->nvram_lock_cnt > 0)
4697 tp->nvram_lock_cnt--;
4698 if (tp->nvram_lock_cnt == 0)
4699 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4700 }
4701 }
4702
4703 /* tp->lock is held. */
4704 static void tg3_enable_nvram_access(struct tg3 *tp)
4705 {
4706 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4707 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4708 u32 nvaccess = tr32(NVRAM_ACCESS);
4709
4710 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4711 }
4712 }
4713
4714 /* tp->lock is held. */
4715 static void tg3_disable_nvram_access(struct tg3 *tp)
4716 {
4717 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4718 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4719 u32 nvaccess = tr32(NVRAM_ACCESS);
4720
4721 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4722 }
4723 }
4724
4725 /* tp->lock is held. */
4726 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4727 {
4728 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4729 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4730
4731 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4732 switch (kind) {
4733 case RESET_KIND_INIT:
4734 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4735 DRV_STATE_START);
4736 break;
4737
4738 case RESET_KIND_SHUTDOWN:
4739 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4740 DRV_STATE_UNLOAD);
4741 break;
4742
4743 case RESET_KIND_SUSPEND:
4744 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4745 DRV_STATE_SUSPEND);
4746 break;
4747
4748 default:
4749 break;
4750 };
4751 }
4752 }
4753
4754 /* tp->lock is held. */
4755 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4756 {
4757 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4758 switch (kind) {
4759 case RESET_KIND_INIT:
4760 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4761 DRV_STATE_START_DONE);
4762 break;
4763
4764 case RESET_KIND_SHUTDOWN:
4765 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4766 DRV_STATE_UNLOAD_DONE);
4767 break;
4768
4769 default:
4770 break;
4771 };
4772 }
4773 }
4774
4775 /* tp->lock is held. */
4776 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4777 {
4778 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4779 switch (kind) {
4780 case RESET_KIND_INIT:
4781 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4782 DRV_STATE_START);
4783 break;
4784
4785 case RESET_KIND_SHUTDOWN:
4786 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4787 DRV_STATE_UNLOAD);
4788 break;
4789
4790 case RESET_KIND_SUSPEND:
4791 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4792 DRV_STATE_SUSPEND);
4793 break;
4794
4795 default:
4796 break;
4797 };
4798 }
4799 }
4800
4801 static int tg3_poll_fw(struct tg3 *tp)
4802 {
4803 int i;
4804 u32 val;
4805
4806 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4807 /* Wait up to 20ms for init done. */
4808 for (i = 0; i < 200; i++) {
4809 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
4810 return 0;
4811 udelay(100);
4812 }
4813 return -ENODEV;
4814 }
4815
4816 /* Wait for firmware initialization to complete. */
4817 for (i = 0; i < 100000; i++) {
4818 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4819 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4820 break;
4821 udelay(10);
4822 }
4823
4824 /* Chip might not be fitted with firmware. Some Sun onboard
4825 * parts are configured like that. So don't signal the timeout
4826 * of the above loop as an error, but do report the lack of
4827 * running firmware once.
4828 */
4829 if (i >= 100000 &&
4830 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
4831 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
4832
4833 printk(KERN_INFO PFX "%s: No firmware running.\n",
4834 tp->dev->name);
4835 }
4836
4837 return 0;
4838 }
4839
4840 /* Save PCI command register before chip reset */
4841 static void tg3_save_pci_state(struct tg3 *tp)
4842 {
4843 u32 val;
4844
4845 pci_read_config_dword(tp->pdev, TG3PCI_COMMAND, &val);
4846 tp->pci_cmd = val;
4847 }
4848
4849 /* Restore PCI state after chip reset */
4850 static void tg3_restore_pci_state(struct tg3 *tp)
4851 {
4852 u32 val;
4853
4854 /* Re-enable indirect register accesses. */
4855 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4856 tp->misc_host_ctrl);
4857
4858 /* Set MAX PCI retry to zero. */
4859 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4860 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4861 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4862 val |= PCISTATE_RETRY_SAME_DMA;
4863 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4864
4865 pci_write_config_dword(tp->pdev, TG3PCI_COMMAND, tp->pci_cmd);
4866
4867 /* Make sure PCI-X relaxed ordering bit is clear. */
4868 if (tp->pcix_cap) {
4869 u16 pcix_cmd;
4870
4871 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
4872 &pcix_cmd);
4873 pcix_cmd &= ~PCI_X_CMD_ERO;
4874 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
4875 pcix_cmd);
4876 }
4877
4878 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4879
4880 /* Chip reset on 5780 will reset MSI enable bit,
4881 * so need to restore it.
4882 */
4883 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4884 u16 ctrl;
4885
4886 pci_read_config_word(tp->pdev,
4887 tp->msi_cap + PCI_MSI_FLAGS,
4888 &ctrl);
4889 pci_write_config_word(tp->pdev,
4890 tp->msi_cap + PCI_MSI_FLAGS,
4891 ctrl | PCI_MSI_FLAGS_ENABLE);
4892 val = tr32(MSGINT_MODE);
4893 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4894 }
4895 }
4896 }
4897
4898 static void tg3_stop_fw(struct tg3 *);
4899
4900 /* tp->lock is held. */
4901 static int tg3_chip_reset(struct tg3 *tp)
4902 {
4903 u32 val;
4904 void (*write_op)(struct tg3 *, u32, u32);
4905 int err;
4906
4907 tg3_nvram_lock(tp);
4908
4909 /* No matching tg3_nvram_unlock() after this because
4910 * chip reset below will undo the nvram lock.
4911 */
4912 tp->nvram_lock_cnt = 0;
4913
4914 /* GRC_MISC_CFG core clock reset will clear the memory
4915 * enable bit in PCI register 4 and the MSI enable bit
4916 * on some chips, so we save relevant registers here.
4917 */
4918 tg3_save_pci_state(tp);
4919
4920 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
4921 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
4922 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
4923 tw32(GRC_FASTBOOT_PC, 0);
4924
4925 /*
4926 * We must avoid the readl() that normally takes place.
4927 * It locks machines, causes machine checks, and other
4928 * fun things. So, temporarily disable the 5701
4929 * hardware workaround, while we do the reset.
4930 */
4931 write_op = tp->write32;
4932 if (write_op == tg3_write_flush_reg32)
4933 tp->write32 = tg3_write32;
4934
4935 /* Prevent the irq handler from reading or writing PCI registers
4936 * during chip reset when the memory enable bit in the PCI command
4937 * register may be cleared. The chip does not generate interrupt
4938 * at this time, but the irq handler may still be called due to irq
4939 * sharing or irqpoll.
4940 */
4941 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
4942 if (tp->hw_status) {
4943 tp->hw_status->status = 0;
4944 tp->hw_status->status_tag = 0;
4945 }
4946 tp->last_tag = 0;
4947 smp_mb();
4948 synchronize_irq(tp->pdev->irq);
4949
4950 /* do the reset */
4951 val = GRC_MISC_CFG_CORECLK_RESET;
4952
4953 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4954 if (tr32(0x7e2c) == 0x60) {
4955 tw32(0x7e2c, 0x20);
4956 }
4957 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4958 tw32(GRC_MISC_CFG, (1 << 29));
4959 val |= (1 << 29);
4960 }
4961 }
4962
4963 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4964 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
4965 tw32(GRC_VCPU_EXT_CTRL,
4966 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
4967 }
4968
4969 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4970 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4971 tw32(GRC_MISC_CFG, val);
4972
4973 /* restore 5701 hardware bug workaround write method */
4974 tp->write32 = write_op;
4975
4976 /* Unfortunately, we have to delay before the PCI read back.
4977 * Some 575X chips even will not respond to a PCI cfg access
4978 * when the reset command is given to the chip.
4979 *
4980 * How do these hardware designers expect things to work
4981 * properly if the PCI write is posted for a long period
4982 * of time? It is always necessary to have some method by
4983 * which a register read back can occur to push the write
4984 * out which does the reset.
4985 *
4986 * For most tg3 variants the trick below was working.
4987 * Ho hum...
4988 */
4989 udelay(120);
4990
4991 /* Flush PCI posted writes. The normal MMIO registers
4992 * are inaccessible at this time so this is the only
4993 * way to make this reliably (actually, this is no longer
4994 * the case, see above). I tried to use indirect
4995 * register read/write but this upset some 5701 variants.
4996 */
4997 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4998
4999 udelay(120);
5000
5001 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
5002 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
5003 int i;
5004 u32 cfg_val;
5005
5006 /* Wait for link training to complete. */
5007 for (i = 0; i < 5000; i++)
5008 udelay(100);
5009
5010 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
5011 pci_write_config_dword(tp->pdev, 0xc4,
5012 cfg_val | (1 << 15));
5013 }
5014 /* Set PCIE max payload size and clear error status. */
5015 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
5016 }
5017
5018 tg3_restore_pci_state(tp);
5019
5020 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
5021
5022 val = 0;
5023 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5024 val = tr32(MEMARB_MODE);
5025 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
5026
5027 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
5028 tg3_stop_fw(tp);
5029 tw32(0x5000, 0x400);
5030 }
5031
5032 tw32(GRC_MODE, tp->grc_mode);
5033
5034 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
5035 val = tr32(0xc4);
5036
5037 tw32(0xc4, val | (1 << 15));
5038 }
5039
5040 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
5041 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5042 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
5043 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
5044 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
5045 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5046 }
5047
5048 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5049 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
5050 tw32_f(MAC_MODE, tp->mac_mode);
5051 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
5052 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
5053 tw32_f(MAC_MODE, tp->mac_mode);
5054 } else
5055 tw32_f(MAC_MODE, 0);
5056 udelay(40);
5057
5058 err = tg3_poll_fw(tp);
5059 if (err)
5060 return err;
5061
5062 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
5063 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5064 val = tr32(0x7c00);
5065
5066 tw32(0x7c00, val | (1 << 25));
5067 }
5068
5069 /* Reprobe ASF enable state. */
5070 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
5071 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
5072 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
5073 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
5074 u32 nic_cfg;
5075
5076 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
5077 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
5078 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
5079 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
5080 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
5081 }
5082 }
5083
5084 return 0;
5085 }
5086
5087 /* tp->lock is held. */
5088 static void tg3_stop_fw(struct tg3 *tp)
5089 {
5090 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5091 u32 val;
5092 int i;
5093
5094 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
5095 val = tr32(GRC_RX_CPU_EVENT);
5096 val |= (1 << 14);
5097 tw32(GRC_RX_CPU_EVENT, val);
5098
5099 /* Wait for RX cpu to ACK the event. */
5100 for (i = 0; i < 100; i++) {
5101 if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
5102 break;
5103 udelay(1);
5104 }
5105 }
5106 }
5107
5108 /* tp->lock is held. */
5109 static int tg3_halt(struct tg3 *tp, int kind, int silent)
5110 {
5111 int err;
5112
5113 tg3_stop_fw(tp);
5114
5115 tg3_write_sig_pre_reset(tp, kind);
5116
5117 tg3_abort_hw(tp, silent);
5118 err = tg3_chip_reset(tp);
5119
5120 tg3_write_sig_legacy(tp, kind);
5121 tg3_write_sig_post_reset(tp, kind);
5122
5123 if (err)
5124 return err;
5125
5126 return 0;
5127 }
5128
5129 #define TG3_FW_RELEASE_MAJOR 0x0
5130 #define TG3_FW_RELASE_MINOR 0x0
5131 #define TG3_FW_RELEASE_FIX 0x0
5132 #define TG3_FW_START_ADDR 0x08000000
5133 #define TG3_FW_TEXT_ADDR 0x08000000
5134 #define TG3_FW_TEXT_LEN 0x9c0
5135 #define TG3_FW_RODATA_ADDR 0x080009c0
5136 #define TG3_FW_RODATA_LEN 0x60
5137 #define TG3_FW_DATA_ADDR 0x08000a40
5138 #define TG3_FW_DATA_LEN 0x20
5139 #define TG3_FW_SBSS_ADDR 0x08000a60
5140 #define TG3_FW_SBSS_LEN 0xc
5141 #define TG3_FW_BSS_ADDR 0x08000a70
5142 #define TG3_FW_BSS_LEN 0x10
5143
5144 static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
5145 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5146 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5147 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5148 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5149 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5150 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5151 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5152 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5153 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5154 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5155 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5156 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5157 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5158 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5159 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5160 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5161 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5162 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5163 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5164 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5165 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5166 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5167 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5168 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5169 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5170 0, 0, 0, 0, 0, 0,
5171 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5172 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5173 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5174 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5175 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5176 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5177 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5178 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5179 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5180 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5181 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5182 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5183 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5184 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5185 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5186 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5187 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5188 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5189 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5190 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5191 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5192 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5193 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5194 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5195 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5196 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5197 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5198 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5199 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5200 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5201 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5202 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5203 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5204 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5205 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
5206 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
5207 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
5208 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
5209 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
5210 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
5211 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
5212 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
5213 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
5214 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
5215 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
5216 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
5217 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
5218 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
5219 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
5220 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
5221 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
5222 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
5223 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
5224 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
5225 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
5226 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
5227 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
5228 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
5229 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
5230 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
5231 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
5232 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
5233 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
5234 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
5235 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5236 };
5237
5238 static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
5239 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5240 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5241 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5242 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
5243 0x00000000
5244 };
5245
5246 #if 0 /* All zeros, don't eat up space with it. */
5247 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
5248 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5249 0x00000000, 0x00000000, 0x00000000, 0x00000000
5250 };
5251 #endif
5252
5253 #define RX_CPU_SCRATCH_BASE 0x30000
5254 #define RX_CPU_SCRATCH_SIZE 0x04000
5255 #define TX_CPU_SCRATCH_BASE 0x34000
5256 #define TX_CPU_SCRATCH_SIZE 0x04000
5257
5258 /* tp->lock is held. */
5259 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
5260 {
5261 int i;
5262
5263 BUG_ON(offset == TX_CPU_BASE &&
5264 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
5265
5266 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5267 u32 val = tr32(GRC_VCPU_EXT_CTRL);
5268
5269 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
5270 return 0;
5271 }
5272 if (offset == RX_CPU_BASE) {
5273 for (i = 0; i < 10000; i++) {
5274 tw32(offset + CPU_STATE, 0xffffffff);
5275 tw32(offset + CPU_MODE, CPU_MODE_HALT);
5276 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5277 break;
5278 }
5279
5280 tw32(offset + CPU_STATE, 0xffffffff);
5281 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
5282 udelay(10);
5283 } else {
5284 for (i = 0; i < 10000; i++) {
5285 tw32(offset + CPU_STATE, 0xffffffff);
5286 tw32(offset + CPU_MODE, CPU_MODE_HALT);
5287 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5288 break;
5289 }
5290 }
5291
5292 if (i >= 10000) {
5293 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
5294 "and %s CPU\n",
5295 tp->dev->name,
5296 (offset == RX_CPU_BASE ? "RX" : "TX"));
5297 return -ENODEV;
5298 }
5299
5300 /* Clear firmware's nvram arbitration. */
5301 if (tp->tg3_flags & TG3_FLAG_NVRAM)
5302 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
5303 return 0;
5304 }
5305
5306 struct fw_info {
5307 unsigned int text_base;
5308 unsigned int text_len;
5309 const u32 *text_data;
5310 unsigned int rodata_base;
5311 unsigned int rodata_len;
5312 const u32 *rodata_data;
5313 unsigned int data_base;
5314 unsigned int data_len;
5315 const u32 *data_data;
5316 };
5317
5318 /* tp->lock is held. */
5319 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5320 int cpu_scratch_size, struct fw_info *info)
5321 {
5322 int err, lock_err, i;
5323 void (*write_op)(struct tg3 *, u32, u32);
5324
5325 if (cpu_base == TX_CPU_BASE &&
5326 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5327 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5328 "TX cpu firmware on %s which is 5705.\n",
5329 tp->dev->name);
5330 return -EINVAL;
5331 }
5332
5333 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5334 write_op = tg3_write_mem;
5335 else
5336 write_op = tg3_write_indirect_reg32;
5337
5338 /* It is possible that bootcode is still loading at this point.
5339 * Get the nvram lock first before halting the cpu.
5340 */
5341 lock_err = tg3_nvram_lock(tp);
5342 err = tg3_halt_cpu(tp, cpu_base);
5343 if (!lock_err)
5344 tg3_nvram_unlock(tp);
5345 if (err)
5346 goto out;
5347
5348 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5349 write_op(tp, cpu_scratch_base + i, 0);
5350 tw32(cpu_base + CPU_STATE, 0xffffffff);
5351 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5352 for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5353 write_op(tp, (cpu_scratch_base +
5354 (info->text_base & 0xffff) +
5355 (i * sizeof(u32))),
5356 (info->text_data ?
5357 info->text_data[i] : 0));
5358 for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5359 write_op(tp, (cpu_scratch_base +
5360 (info->rodata_base & 0xffff) +
5361 (i * sizeof(u32))),
5362 (info->rodata_data ?
5363 info->rodata_data[i] : 0));
5364 for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5365 write_op(tp, (cpu_scratch_base +
5366 (info->data_base & 0xffff) +
5367 (i * sizeof(u32))),
5368 (info->data_data ?
5369 info->data_data[i] : 0));
5370
5371 err = 0;
5372
5373 out:
5374 return err;
5375 }
5376
5377 /* tp->lock is held. */
5378 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5379 {
5380 struct fw_info info;
5381 int err, i;
5382
5383 info.text_base = TG3_FW_TEXT_ADDR;
5384 info.text_len = TG3_FW_TEXT_LEN;
5385 info.text_data = &tg3FwText[0];
5386 info.rodata_base = TG3_FW_RODATA_ADDR;
5387 info.rodata_len = TG3_FW_RODATA_LEN;
5388 info.rodata_data = &tg3FwRodata[0];
5389 info.data_base = TG3_FW_DATA_ADDR;
5390 info.data_len = TG3_FW_DATA_LEN;
5391 info.data_data = NULL;
5392
5393 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5394 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5395 &info);
5396 if (err)
5397 return err;
5398
5399 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5400 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5401 &info);
5402 if (err)
5403 return err;
5404
5405 /* Now startup only the RX cpu. */
5406 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5407 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5408
5409 for (i = 0; i < 5; i++) {
5410 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5411 break;
5412 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5413 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
5414 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5415 udelay(1000);
5416 }
5417 if (i >= 5) {
5418 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5419 "to set RX CPU PC, is %08x should be %08x\n",
5420 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5421 TG3_FW_TEXT_ADDR);
5422 return -ENODEV;
5423 }
5424 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5425 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
5426
5427 return 0;
5428 }
5429
5430
5431 #define TG3_TSO_FW_RELEASE_MAJOR 0x1
5432 #define TG3_TSO_FW_RELASE_MINOR 0x6
5433 #define TG3_TSO_FW_RELEASE_FIX 0x0
5434 #define TG3_TSO_FW_START_ADDR 0x08000000
5435 #define TG3_TSO_FW_TEXT_ADDR 0x08000000
5436 #define TG3_TSO_FW_TEXT_LEN 0x1aa0
5437 #define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
5438 #define TG3_TSO_FW_RODATA_LEN 0x60
5439 #define TG3_TSO_FW_DATA_ADDR 0x08001b20
5440 #define TG3_TSO_FW_DATA_LEN 0x30
5441 #define TG3_TSO_FW_SBSS_ADDR 0x08001b50
5442 #define TG3_TSO_FW_SBSS_LEN 0x2c
5443 #define TG3_TSO_FW_BSS_ADDR 0x08001b80
5444 #define TG3_TSO_FW_BSS_LEN 0x894
5445
5446 static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
5447 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5448 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5449 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5450 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5451 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5452 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5453 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5454 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5455 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5456 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5457 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5458 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5459 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5460 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5461 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5462 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5463 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5464 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5465 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5466 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5467 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5468 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5469 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5470 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5471 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5472 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5473 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5474 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5475 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5476 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5477 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5478 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5479 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5480 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5481 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5482 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5483 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5484 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5485 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5486 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5487 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5488 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5489 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5490 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5491 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5492 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5493 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5494 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5495 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5496 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5497 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5498 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5499 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5500 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5501 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5502 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5503 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5504 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5505 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5506 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5507 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5508 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5509 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5510 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5511 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5512 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5513 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5514 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5515 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5516 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5517 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5518 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5519 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5520 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5521 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5522 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5523 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5524 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5525 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5526 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5527 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5528 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5529 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5530 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5531 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5532 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5533 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5534 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5535 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5536 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5537 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5538 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5539 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5540 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5541 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5542 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5543 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5544 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5545 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5546 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5547 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5548 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5549 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5550 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5551 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5552 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5553 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5554 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5555 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5556 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5557 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5558 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5559 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5560 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5561 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5562 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5563 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5564 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5565 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5566 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5567 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5568 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5569 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5570 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5571 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5572 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5573 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5574 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5575 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5576 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5577 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5578 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5579 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5580 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5581 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5582 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5583 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5584 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5585 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5586 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5587 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5588 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5589 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5590 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5591 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5592 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5593 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5594 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5595 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5596 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5597 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5598 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5599 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5600 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5601 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5602 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5603 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5604 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5605 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5606 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5607 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5608 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5609 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5610 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5611 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5612 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5613 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5614 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5615 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5616 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5617 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5618 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5619 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5620 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5621 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5622 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5623 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5624 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5625 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5626 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5627 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5628 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5629 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5630 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5631 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5632 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5633 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5634 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5635 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5636 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5637 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5638 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5639 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5640 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5641 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5642 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5643 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5644 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5645 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5646 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5647 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5648 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5649 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5650 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5651 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5652 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5653 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5654 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5655 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5656 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5657 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5658 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5659 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5660 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5661 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5662 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5663 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5664 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5665 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5666 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5667 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5668 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5669 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5670 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5671 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5672 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5673 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5674 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5675 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5676 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5677 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5678 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5679 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5680 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5681 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5682 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5683 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5684 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5685 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5686 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5687 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5688 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5689 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5690 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5691 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5692 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5693 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5694 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5695 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5696 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5697 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5698 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5699 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5700 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5701 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5702 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5703 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5704 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5705 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5706 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5707 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5708 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5709 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5710 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5711 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5712 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5713 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5714 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5715 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5716 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5717 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5718 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5719 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5720 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5721 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5722 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5723 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5724 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5725 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5726 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5727 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5728 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5729 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5730 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5731 };
5732
5733 static const u32 tg3TsoFwRodata[] = {
5734 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5735 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5736 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5737 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5738 0x00000000,
5739 };
5740
5741 static const u32 tg3TsoFwData[] = {
5742 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5743 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5744 0x00000000,
5745 };
5746
5747 /* 5705 needs a special version of the TSO firmware. */
5748 #define TG3_TSO5_FW_RELEASE_MAJOR 0x1
5749 #define TG3_TSO5_FW_RELASE_MINOR 0x2
5750 #define TG3_TSO5_FW_RELEASE_FIX 0x0
5751 #define TG3_TSO5_FW_START_ADDR 0x00010000
5752 #define TG3_TSO5_FW_TEXT_ADDR 0x00010000
5753 #define TG3_TSO5_FW_TEXT_LEN 0xe90
5754 #define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
5755 #define TG3_TSO5_FW_RODATA_LEN 0x50
5756 #define TG3_TSO5_FW_DATA_ADDR 0x00010f00
5757 #define TG3_TSO5_FW_DATA_LEN 0x20
5758 #define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
5759 #define TG3_TSO5_FW_SBSS_LEN 0x28
5760 #define TG3_TSO5_FW_BSS_ADDR 0x00010f50
5761 #define TG3_TSO5_FW_BSS_LEN 0x88
5762
5763 static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
5764 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5765 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5766 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5767 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5768 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5769 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5770 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5771 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5772 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5773 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5774 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5775 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5776 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5777 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5778 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5779 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5780 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5781 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5782 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5783 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5784 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5785 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5786 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5787 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5788 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5789 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5790 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5791 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5792 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5793 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5794 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5795 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5796 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5797 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5798 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5799 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5800 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5801 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5802 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5803 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5804 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5805 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5806 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5807 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5808 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
5809 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
5810 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
5811 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
5812 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
5813 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
5814 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
5815 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
5816 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
5817 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
5818 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
5819 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
5820 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
5821 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
5822 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
5823 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
5824 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
5825 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
5826 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
5827 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
5828 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
5829 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
5830 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5831 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
5832 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
5833 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
5834 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
5835 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
5836 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
5837 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
5838 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
5839 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
5840 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
5841 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
5842 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
5843 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
5844 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
5845 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
5846 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
5847 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
5848 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
5849 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
5850 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
5851 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
5852 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
5853 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
5854 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
5855 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
5856 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
5857 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
5858 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
5859 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
5860 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
5861 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
5862 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
5863 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
5864 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
5865 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
5866 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
5867 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
5868 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
5869 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
5870 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5871 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5872 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
5873 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
5874 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
5875 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
5876 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
5877 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
5878 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
5879 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
5880 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
5881 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5882 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5883 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
5884 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
5885 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
5886 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
5887 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5888 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
5889 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
5890 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
5891 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
5892 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
5893 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
5894 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
5895 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
5896 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
5897 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
5898 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
5899 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
5900 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
5901 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
5902 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
5903 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
5904 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
5905 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
5906 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
5907 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
5908 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
5909 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
5910 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
5911 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5912 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
5913 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5914 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5915 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5916 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5917 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5918 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5919 0x00000000, 0x00000000, 0x00000000,
5920 };
5921
5922 static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
5923 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5924 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5925 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5926 0x00000000, 0x00000000, 0x00000000,
5927 };
5928
5929 static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
5930 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5931 0x00000000, 0x00000000, 0x00000000,
5932 };
5933
5934 /* tp->lock is held. */
5935 static int tg3_load_tso_firmware(struct tg3 *tp)
5936 {
5937 struct fw_info info;
5938 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5939 int err, i;
5940
5941 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5942 return 0;
5943
5944 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5945 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5946 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5947 info.text_data = &tg3Tso5FwText[0];
5948 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5949 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5950 info.rodata_data = &tg3Tso5FwRodata[0];
5951 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5952 info.data_len = TG3_TSO5_FW_DATA_LEN;
5953 info.data_data = &tg3Tso5FwData[0];
5954 cpu_base = RX_CPU_BASE;
5955 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5956 cpu_scratch_size = (info.text_len +
5957 info.rodata_len +
5958 info.data_len +
5959 TG3_TSO5_FW_SBSS_LEN +
5960 TG3_TSO5_FW_BSS_LEN);
5961 } else {
5962 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5963 info.text_len = TG3_TSO_FW_TEXT_LEN;
5964 info.text_data = &tg3TsoFwText[0];
5965 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5966 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5967 info.rodata_data = &tg3TsoFwRodata[0];
5968 info.data_base = TG3_TSO_FW_DATA_ADDR;
5969 info.data_len = TG3_TSO_FW_DATA_LEN;
5970 info.data_data = &tg3TsoFwData[0];
5971 cpu_base = TX_CPU_BASE;
5972 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5973 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5974 }
5975
5976 err = tg3_load_firmware_cpu(tp, cpu_base,
5977 cpu_scratch_base, cpu_scratch_size,
5978 &info);
5979 if (err)
5980 return err;
5981
5982 /* Now startup the cpu. */
5983 tw32(cpu_base + CPU_STATE, 0xffffffff);
5984 tw32_f(cpu_base + CPU_PC, info.text_base);
5985
5986 for (i = 0; i < 5; i++) {
5987 if (tr32(cpu_base + CPU_PC) == info.text_base)
5988 break;
5989 tw32(cpu_base + CPU_STATE, 0xffffffff);
5990 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
5991 tw32_f(cpu_base + CPU_PC, info.text_base);
5992 udelay(1000);
5993 }
5994 if (i >= 5) {
5995 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5996 "to set CPU PC, is %08x should be %08x\n",
5997 tp->dev->name, tr32(cpu_base + CPU_PC),
5998 info.text_base);
5999 return -ENODEV;
6000 }
6001 tw32(cpu_base + CPU_STATE, 0xffffffff);
6002 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6003 return 0;
6004 }
6005
6006
6007 /* tp->lock is held. */
6008 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
6009 {
6010 u32 addr_high, addr_low;
6011 int i;
6012
6013 addr_high = ((tp->dev->dev_addr[0] << 8) |
6014 tp->dev->dev_addr[1]);
6015 addr_low = ((tp->dev->dev_addr[2] << 24) |
6016 (tp->dev->dev_addr[3] << 16) |
6017 (tp->dev->dev_addr[4] << 8) |
6018 (tp->dev->dev_addr[5] << 0));
6019 for (i = 0; i < 4; i++) {
6020 if (i == 1 && skip_mac_1)
6021 continue;
6022 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
6023 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
6024 }
6025
6026 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
6027 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6028 for (i = 0; i < 12; i++) {
6029 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
6030 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
6031 }
6032 }
6033
6034 addr_high = (tp->dev->dev_addr[0] +
6035 tp->dev->dev_addr[1] +
6036 tp->dev->dev_addr[2] +
6037 tp->dev->dev_addr[3] +
6038 tp->dev->dev_addr[4] +
6039 tp->dev->dev_addr[5]) &
6040 TX_BACKOFF_SEED_MASK;
6041 tw32(MAC_TX_BACKOFF_SEED, addr_high);
6042 }
6043
6044 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6045 {
6046 struct tg3 *tp = netdev_priv(dev);
6047 struct sockaddr *addr = p;
6048 int err = 0, skip_mac_1 = 0;
6049
6050 if (!is_valid_ether_addr(addr->sa_data))
6051 return -EINVAL;
6052
6053 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6054
6055 if (!netif_running(dev))
6056 return 0;
6057
6058 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6059 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6060
6061 addr0_high = tr32(MAC_ADDR_0_HIGH);
6062 addr0_low = tr32(MAC_ADDR_0_LOW);
6063 addr1_high = tr32(MAC_ADDR_1_HIGH);
6064 addr1_low = tr32(MAC_ADDR_1_LOW);
6065
6066 /* Skip MAC addr 1 if ASF is using it. */
6067 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6068 !(addr1_high == 0 && addr1_low == 0))
6069 skip_mac_1 = 1;
6070 }
6071 spin_lock_bh(&tp->lock);
6072 __tg3_set_mac_addr(tp, skip_mac_1);
6073 spin_unlock_bh(&tp->lock);
6074
6075 return err;
6076 }
6077
6078 /* tp->lock is held. */
6079 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6080 dma_addr_t mapping, u32 maxlen_flags,
6081 u32 nic_addr)
6082 {
6083 tg3_write_mem(tp,
6084 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6085 ((u64) mapping >> 32));
6086 tg3_write_mem(tp,
6087 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6088 ((u64) mapping & 0xffffffff));
6089 tg3_write_mem(tp,
6090 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6091 maxlen_flags);
6092
6093 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6094 tg3_write_mem(tp,
6095 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6096 nic_addr);
6097 }
6098
6099 static void __tg3_set_rx_mode(struct net_device *);
6100 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6101 {
6102 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6103 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6104 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6105 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6106 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6107 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6108 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6109 }
6110 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6111 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6112 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6113 u32 val = ec->stats_block_coalesce_usecs;
6114
6115 if (!netif_carrier_ok(tp->dev))
6116 val = 0;
6117
6118 tw32(HOSTCC_STAT_COAL_TICKS, val);
6119 }
6120 }
6121
6122 /* tp->lock is held. */
6123 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6124 {
6125 u32 val, rdmac_mode;
6126 int i, err, limit;
6127
6128 tg3_disable_ints(tp);
6129
6130 tg3_stop_fw(tp);
6131
6132 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6133
6134 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6135 tg3_abort_hw(tp, 1);
6136 }
6137
6138 if (reset_phy)
6139 tg3_phy_reset(tp);
6140
6141 err = tg3_chip_reset(tp);
6142 if (err)
6143 return err;
6144
6145 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6146
6147 /* This works around an issue with Athlon chipsets on
6148 * B3 tigon3 silicon. This bit has no effect on any
6149 * other revision. But do not set this on PCI Express
6150 * chips.
6151 */
6152 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6153 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6154 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6155
6156 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6157 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6158 val = tr32(TG3PCI_PCISTATE);
6159 val |= PCISTATE_RETRY_SAME_DMA;
6160 tw32(TG3PCI_PCISTATE, val);
6161 }
6162
6163 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6164 /* Enable some hw fixes. */
6165 val = tr32(TG3PCI_MSI_DATA);
6166 val |= (1 << 26) | (1 << 28) | (1 << 29);
6167 tw32(TG3PCI_MSI_DATA, val);
6168 }
6169
6170 /* Descriptor ring init may make accesses to the
6171 * NIC SRAM area to setup the TX descriptors, so we
6172 * can only do this after the hardware has been
6173 * successfully reset.
6174 */
6175 err = tg3_init_rings(tp);
6176 if (err)
6177 return err;
6178
6179 /* This value is determined during the probe time DMA
6180 * engine test, tg3_test_dma.
6181 */
6182 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6183
6184 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6185 GRC_MODE_4X_NIC_SEND_RINGS |
6186 GRC_MODE_NO_TX_PHDR_CSUM |
6187 GRC_MODE_NO_RX_PHDR_CSUM);
6188 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
6189
6190 /* Pseudo-header checksum is done by hardware logic and not
6191 * the offload processers, so make the chip do the pseudo-
6192 * header checksums on receive. For transmit it is more
6193 * convenient to do the pseudo-header checksum in software
6194 * as Linux does that on transmit for us in all cases.
6195 */
6196 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
6197
6198 tw32(GRC_MODE,
6199 tp->grc_mode |
6200 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6201
6202 /* Setup the timer prescalar register. Clock is always 66Mhz. */
6203 val = tr32(GRC_MISC_CFG);
6204 val &= ~0xff;
6205 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6206 tw32(GRC_MISC_CFG, val);
6207
6208 /* Initialize MBUF/DESC pool. */
6209 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6210 /* Do nothing. */
6211 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6212 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6213 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6214 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6215 else
6216 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6217 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6218 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6219 }
6220 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6221 int fw_len;
6222
6223 fw_len = (TG3_TSO5_FW_TEXT_LEN +
6224 TG3_TSO5_FW_RODATA_LEN +
6225 TG3_TSO5_FW_DATA_LEN +
6226 TG3_TSO5_FW_SBSS_LEN +
6227 TG3_TSO5_FW_BSS_LEN);
6228 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6229 tw32(BUFMGR_MB_POOL_ADDR,
6230 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6231 tw32(BUFMGR_MB_POOL_SIZE,
6232 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6233 }
6234
6235 if (tp->dev->mtu <= ETH_DATA_LEN) {
6236 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6237 tp->bufmgr_config.mbuf_read_dma_low_water);
6238 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6239 tp->bufmgr_config.mbuf_mac_rx_low_water);
6240 tw32(BUFMGR_MB_HIGH_WATER,
6241 tp->bufmgr_config.mbuf_high_water);
6242 } else {
6243 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6244 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6245 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6246 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6247 tw32(BUFMGR_MB_HIGH_WATER,
6248 tp->bufmgr_config.mbuf_high_water_jumbo);
6249 }
6250 tw32(BUFMGR_DMA_LOW_WATER,
6251 tp->bufmgr_config.dma_low_water);
6252 tw32(BUFMGR_DMA_HIGH_WATER,
6253 tp->bufmgr_config.dma_high_water);
6254
6255 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6256 for (i = 0; i < 2000; i++) {
6257 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6258 break;
6259 udelay(10);
6260 }
6261 if (i >= 2000) {
6262 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6263 tp->dev->name);
6264 return -ENODEV;
6265 }
6266
6267 /* Setup replenish threshold. */
6268 val = tp->rx_pending / 8;
6269 if (val == 0)
6270 val = 1;
6271 else if (val > tp->rx_std_max_post)
6272 val = tp->rx_std_max_post;
6273 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6274 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6275 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6276
6277 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6278 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6279 }
6280
6281 tw32(RCVBDI_STD_THRESH, val);
6282
6283 /* Initialize TG3_BDINFO's at:
6284 * RCVDBDI_STD_BD: standard eth size rx ring
6285 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
6286 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
6287 *
6288 * like so:
6289 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
6290 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
6291 * ring attribute flags
6292 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
6293 *
6294 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6295 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6296 *
6297 * The size of each ring is fixed in the firmware, but the location is
6298 * configurable.
6299 */
6300 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6301 ((u64) tp->rx_std_mapping >> 32));
6302 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6303 ((u64) tp->rx_std_mapping & 0xffffffff));
6304 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6305 NIC_SRAM_RX_BUFFER_DESC);
6306
6307 /* Don't even try to program the JUMBO/MINI buffer descriptor
6308 * configs on 5705.
6309 */
6310 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6311 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6312 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6313 } else {
6314 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6315 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6316
6317 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6318 BDINFO_FLAGS_DISABLED);
6319
6320 /* Setup replenish threshold. */
6321 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6322
6323 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6324 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6325 ((u64) tp->rx_jumbo_mapping >> 32));
6326 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6327 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6328 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6329 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6330 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6331 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6332 } else {
6333 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6334 BDINFO_FLAGS_DISABLED);
6335 }
6336
6337 }
6338
6339 /* There is only one send ring on 5705/5750, no need to explicitly
6340 * disable the others.
6341 */
6342 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6343 /* Clear out send RCB ring in SRAM. */
6344 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6345 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6346 BDINFO_FLAGS_DISABLED);
6347 }
6348
6349 tp->tx_prod = 0;
6350 tp->tx_cons = 0;
6351 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6352 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6353
6354 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6355 tp->tx_desc_mapping,
6356 (TG3_TX_RING_SIZE <<
6357 BDINFO_FLAGS_MAXLEN_SHIFT),
6358 NIC_SRAM_TX_BUFFER_DESC);
6359
6360 /* There is only one receive return ring on 5705/5750, no need
6361 * to explicitly disable the others.
6362 */
6363 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6364 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6365 i += TG3_BDINFO_SIZE) {
6366 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6367 BDINFO_FLAGS_DISABLED);
6368 }
6369 }
6370
6371 tp->rx_rcb_ptr = 0;
6372 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6373
6374 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6375 tp->rx_rcb_mapping,
6376 (TG3_RX_RCB_RING_SIZE(tp) <<
6377 BDINFO_FLAGS_MAXLEN_SHIFT),
6378 0);
6379
6380 tp->rx_std_ptr = tp->rx_pending;
6381 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6382 tp->rx_std_ptr);
6383
6384 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
6385 tp->rx_jumbo_pending : 0;
6386 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6387 tp->rx_jumbo_ptr);
6388
6389 /* Initialize MAC address and backoff seed. */
6390 __tg3_set_mac_addr(tp, 0);
6391
6392 /* MTU + ethernet header + FCS + optional VLAN tag */
6393 tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
6394
6395 /* The slot time is changed by tg3_setup_phy if we
6396 * run at gigabit with half duplex.
6397 */
6398 tw32(MAC_TX_LENGTHS,
6399 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6400 (6 << TX_LENGTHS_IPG_SHIFT) |
6401 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6402
6403 /* Receive rules. */
6404 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6405 tw32(RCVLPC_CONFIG, 0x0181);
6406
6407 /* Calculate RDMAC_MODE setting early, we need it to determine
6408 * the RCVLPC_STATE_ENABLE mask.
6409 */
6410 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6411 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6412 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6413 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6414 RDMAC_MODE_LNGREAD_ENAB);
6415
6416 /* If statement applies to 5705 and 5750 PCI devices only */
6417 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6418 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6419 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
6420 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
6421 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6422 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
6423 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6424 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
6425 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6426 }
6427 }
6428
6429 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6430 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6431
6432 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6433 rdmac_mode |= (1 << 27);
6434
6435 /* Receive/send statistics. */
6436 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6437 val = tr32(RCVLPC_STATS_ENABLE);
6438 val &= ~RCVLPC_STATSENAB_DACK_FIX;
6439 tw32(RCVLPC_STATS_ENABLE, val);
6440 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6441 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
6442 val = tr32(RCVLPC_STATS_ENABLE);
6443 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6444 tw32(RCVLPC_STATS_ENABLE, val);
6445 } else {
6446 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
6447 }
6448 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
6449 tw32(SNDDATAI_STATSENAB, 0xffffff);
6450 tw32(SNDDATAI_STATSCTRL,
6451 (SNDDATAI_SCTRL_ENABLE |
6452 SNDDATAI_SCTRL_FASTUPD));
6453
6454 /* Setup host coalescing engine. */
6455 tw32(HOSTCC_MODE, 0);
6456 for (i = 0; i < 2000; i++) {
6457 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
6458 break;
6459 udelay(10);
6460 }
6461
6462 __tg3_set_coalesce(tp, &tp->coal);
6463
6464 /* set status block DMA address */
6465 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6466 ((u64) tp->status_mapping >> 32));
6467 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6468 ((u64) tp->status_mapping & 0xffffffff));
6469
6470 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6471 /* Status/statistics block address. See tg3_timer,
6472 * the tg3_periodic_fetch_stats call there, and
6473 * tg3_get_stats to see how this works for 5705/5750 chips.
6474 */
6475 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6476 ((u64) tp->stats_mapping >> 32));
6477 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6478 ((u64) tp->stats_mapping & 0xffffffff));
6479 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
6480 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
6481 }
6482
6483 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
6484
6485 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
6486 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
6487 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6488 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
6489
6490 /* Clear statistics/status block in chip, and status block in ram. */
6491 for (i = NIC_SRAM_STATS_BLK;
6492 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
6493 i += sizeof(u32)) {
6494 tg3_write_mem(tp, i, 0);
6495 udelay(40);
6496 }
6497 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
6498
6499 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6500 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
6501 /* reset to prevent losing 1st rx packet intermittently */
6502 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6503 udelay(10);
6504 }
6505
6506 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
6507 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
6508 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6509 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6510 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
6511 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
6512 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
6513 udelay(40);
6514
6515 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
6516 * If TG3_FLG2_IS_NIC is zero, we should read the
6517 * register to preserve the GPIO settings for LOMs. The GPIOs,
6518 * whether used as inputs or outputs, are set by boot code after
6519 * reset.
6520 */
6521 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
6522 u32 gpio_mask;
6523
6524 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
6525 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
6526 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
6527
6528 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6529 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
6530 GRC_LCLCTRL_GPIO_OUTPUT3;
6531
6532 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6533 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
6534
6535 tp->grc_local_ctrl &= ~gpio_mask;
6536 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
6537
6538 /* GPIO1 must be driven high for eeprom write protect */
6539 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
6540 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
6541 GRC_LCLCTRL_GPIO_OUTPUT1);
6542 }
6543 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6544 udelay(100);
6545
6546 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
6547 tp->last_tag = 0;
6548
6549 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6550 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
6551 udelay(40);
6552 }
6553
6554 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
6555 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
6556 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
6557 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
6558 WDMAC_MODE_LNGREAD_ENAB);
6559
6560 /* If statement applies to 5705 and 5750 PCI devices only */
6561 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6562 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6563 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
6564 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
6565 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6566 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6567 /* nothing */
6568 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6569 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
6570 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
6571 val |= WDMAC_MODE_RX_ACCEL;
6572 }
6573 }
6574
6575 /* Enable host coalescing bug fix */
6576 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
6577 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787))
6578 val |= (1 << 29);
6579
6580 tw32_f(WDMAC_MODE, val);
6581 udelay(40);
6582
6583 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6584 u16 pcix_cmd;
6585
6586 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6587 &pcix_cmd);
6588 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
6589 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
6590 pcix_cmd |= PCI_X_CMD_READ_2K;
6591 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6592 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
6593 pcix_cmd |= PCI_X_CMD_READ_2K;
6594 }
6595 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6596 pcix_cmd);
6597 }
6598
6599 tw32_f(RDMAC_MODE, rdmac_mode);
6600 udelay(40);
6601
6602 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
6603 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6604 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
6605 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
6606 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
6607 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
6608 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
6609 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
6610 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6611 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
6612 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
6613 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
6614
6615 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
6616 err = tg3_load_5701_a0_firmware_fix(tp);
6617 if (err)
6618 return err;
6619 }
6620
6621 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6622 err = tg3_load_tso_firmware(tp);
6623 if (err)
6624 return err;
6625 }
6626
6627 tp->tx_mode = TX_MODE_ENABLE;
6628 tw32_f(MAC_TX_MODE, tp->tx_mode);
6629 udelay(100);
6630
6631 tp->rx_mode = RX_MODE_ENABLE;
6632 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6633 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
6634
6635 tw32_f(MAC_RX_MODE, tp->rx_mode);
6636 udelay(10);
6637
6638 if (tp->link_config.phy_is_low_power) {
6639 tp->link_config.phy_is_low_power = 0;
6640 tp->link_config.speed = tp->link_config.orig_speed;
6641 tp->link_config.duplex = tp->link_config.orig_duplex;
6642 tp->link_config.autoneg = tp->link_config.orig_autoneg;
6643 }
6644
6645 tp->mi_mode = MAC_MI_MODE_BASE;
6646 tw32_f(MAC_MI_MODE, tp->mi_mode);
6647 udelay(80);
6648
6649 tw32(MAC_LED_CTRL, tp->led_ctrl);
6650
6651 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
6652 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6653 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6654 udelay(10);
6655 }
6656 tw32_f(MAC_RX_MODE, tp->rx_mode);
6657 udelay(10);
6658
6659 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6660 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
6661 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
6662 /* Set drive transmission level to 1.2V */
6663 /* only if the signal pre-emphasis bit is not set */
6664 val = tr32(MAC_SERDES_CFG);
6665 val &= 0xfffff000;
6666 val |= 0x880;
6667 tw32(MAC_SERDES_CFG, val);
6668 }
6669 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
6670 tw32(MAC_SERDES_CFG, 0x616000);
6671 }
6672
6673 /* Prevent chip from dropping frames when flow control
6674 * is enabled.
6675 */
6676 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
6677
6678 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
6679 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6680 /* Use hardware link auto-negotiation */
6681 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
6682 }
6683
6684 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
6685 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
6686 u32 tmp;
6687
6688 tmp = tr32(SERDES_RX_CTRL);
6689 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
6690 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
6691 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
6692 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6693 }
6694
6695 err = tg3_setup_phy(tp, 0);
6696 if (err)
6697 return err;
6698
6699 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6700 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
6701 u32 tmp;
6702
6703 /* Clear CRC stats. */
6704 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
6705 tg3_writephy(tp, MII_TG3_TEST1,
6706 tmp | MII_TG3_TEST1_CRC_EN);
6707 tg3_readphy(tp, 0x14, &tmp);
6708 }
6709 }
6710
6711 __tg3_set_rx_mode(tp->dev);
6712
6713 /* Initialize receive rules. */
6714 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
6715 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6716 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
6717 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6718
6719 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6720 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6721 limit = 8;
6722 else
6723 limit = 16;
6724 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6725 limit -= 4;
6726 switch (limit) {
6727 case 16:
6728 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
6729 case 15:
6730 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
6731 case 14:
6732 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
6733 case 13:
6734 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
6735 case 12:
6736 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
6737 case 11:
6738 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
6739 case 10:
6740 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
6741 case 9:
6742 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
6743 case 8:
6744 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
6745 case 7:
6746 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
6747 case 6:
6748 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
6749 case 5:
6750 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
6751 case 4:
6752 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
6753 case 3:
6754 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
6755 case 2:
6756 case 1:
6757
6758 default:
6759 break;
6760 };
6761
6762 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6763
6764 return 0;
6765 }
6766
6767 /* Called at device open time to get the chip ready for
6768 * packet processing. Invoked with tp->lock held.
6769 */
6770 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
6771 {
6772 int err;
6773
6774 /* Force the chip into D0. */
6775 err = tg3_set_power_state(tp, PCI_D0);
6776 if (err)
6777 goto out;
6778
6779 tg3_switch_clocks(tp);
6780
6781 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6782
6783 err = tg3_reset_hw(tp, reset_phy);
6784
6785 out:
6786 return err;
6787 }
6788
6789 #define TG3_STAT_ADD32(PSTAT, REG) \
6790 do { u32 __val = tr32(REG); \
6791 (PSTAT)->low += __val; \
6792 if ((PSTAT)->low < __val) \
6793 (PSTAT)->high += 1; \
6794 } while (0)
6795
6796 static void tg3_periodic_fetch_stats(struct tg3 *tp)
6797 {
6798 struct tg3_hw_stats *sp = tp->hw_stats;
6799
6800 if (!netif_carrier_ok(tp->dev))
6801 return;
6802
6803 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
6804 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
6805 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
6806 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
6807 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
6808 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
6809 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
6810 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
6811 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
6812 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
6813 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
6814 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
6815 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
6816
6817 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
6818 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
6819 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
6820 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
6821 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
6822 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
6823 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
6824 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
6825 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
6826 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
6827 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
6828 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6829 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6830 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
6831
6832 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
6833 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
6834 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
6835 }
6836
6837 static void tg3_timer(unsigned long __opaque)
6838 {
6839 struct tg3 *tp = (struct tg3 *) __opaque;
6840
6841 if (tp->irq_sync)
6842 goto restart_timer;
6843
6844 spin_lock(&tp->lock);
6845
6846 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6847 /* All of this garbage is because when using non-tagged
6848 * IRQ status the mailbox/status_block protocol the chip
6849 * uses with the cpu is race prone.
6850 */
6851 if (tp->hw_status->status & SD_STATUS_UPDATED) {
6852 tw32(GRC_LOCAL_CTRL,
6853 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
6854 } else {
6855 tw32(HOSTCC_MODE, tp->coalesce_mode |
6856 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
6857 }
6858
6859 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
6860 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
6861 spin_unlock(&tp->lock);
6862 schedule_work(&tp->reset_task);
6863 return;
6864 }
6865 }
6866
6867 /* This part only runs once per second. */
6868 if (!--tp->timer_counter) {
6869 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6870 tg3_periodic_fetch_stats(tp);
6871
6872 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
6873 u32 mac_stat;
6874 int phy_event;
6875
6876 mac_stat = tr32(MAC_STATUS);
6877
6878 phy_event = 0;
6879 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
6880 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
6881 phy_event = 1;
6882 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
6883 phy_event = 1;
6884
6885 if (phy_event)
6886 tg3_setup_phy(tp, 0);
6887 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
6888 u32 mac_stat = tr32(MAC_STATUS);
6889 int need_setup = 0;
6890
6891 if (netif_carrier_ok(tp->dev) &&
6892 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
6893 need_setup = 1;
6894 }
6895 if (! netif_carrier_ok(tp->dev) &&
6896 (mac_stat & (MAC_STATUS_PCS_SYNCED |
6897 MAC_STATUS_SIGNAL_DET))) {
6898 need_setup = 1;
6899 }
6900 if (need_setup) {
6901 if (!tp->serdes_counter) {
6902 tw32_f(MAC_MODE,
6903 (tp->mac_mode &
6904 ~MAC_MODE_PORT_MODE_MASK));
6905 udelay(40);
6906 tw32_f(MAC_MODE, tp->mac_mode);
6907 udelay(40);
6908 }
6909 tg3_setup_phy(tp, 0);
6910 }
6911 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6912 tg3_serdes_parallel_detect(tp);
6913
6914 tp->timer_counter = tp->timer_multiplier;
6915 }
6916
6917 /* Heartbeat is only sent once every 2 seconds.
6918 *
6919 * The heartbeat is to tell the ASF firmware that the host
6920 * driver is still alive. In the event that the OS crashes,
6921 * ASF needs to reset the hardware to free up the FIFO space
6922 * that may be filled with rx packets destined for the host.
6923 * If the FIFO is full, ASF will no longer function properly.
6924 *
6925 * Unintended resets have been reported on real time kernels
6926 * where the timer doesn't run on time. Netpoll will also have
6927 * same problem.
6928 *
6929 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
6930 * to check the ring condition when the heartbeat is expiring
6931 * before doing the reset. This will prevent most unintended
6932 * resets.
6933 */
6934 if (!--tp->asf_counter) {
6935 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6936 u32 val;
6937
6938 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
6939 FWCMD_NICDRV_ALIVE3);
6940 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
6941 /* 5 seconds timeout */
6942 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
6943 val = tr32(GRC_RX_CPU_EVENT);
6944 val |= (1 << 14);
6945 tw32(GRC_RX_CPU_EVENT, val);
6946 }
6947 tp->asf_counter = tp->asf_multiplier;
6948 }
6949
6950 spin_unlock(&tp->lock);
6951
6952 restart_timer:
6953 tp->timer.expires = jiffies + tp->timer_offset;
6954 add_timer(&tp->timer);
6955 }
6956
6957 static int tg3_request_irq(struct tg3 *tp)
6958 {
6959 irq_handler_t fn;
6960 unsigned long flags;
6961 struct net_device *dev = tp->dev;
6962
6963 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6964 fn = tg3_msi;
6965 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
6966 fn = tg3_msi_1shot;
6967 flags = IRQF_SAMPLE_RANDOM;
6968 } else {
6969 fn = tg3_interrupt;
6970 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6971 fn = tg3_interrupt_tagged;
6972 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
6973 }
6974 return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
6975 }
6976
6977 static int tg3_test_interrupt(struct tg3 *tp)
6978 {
6979 struct net_device *dev = tp->dev;
6980 int err, i, intr_ok = 0;
6981
6982 if (!netif_running(dev))
6983 return -ENODEV;
6984
6985 tg3_disable_ints(tp);
6986
6987 free_irq(tp->pdev->irq, dev);
6988
6989 err = request_irq(tp->pdev->irq, tg3_test_isr,
6990 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
6991 if (err)
6992 return err;
6993
6994 tp->hw_status->status &= ~SD_STATUS_UPDATED;
6995 tg3_enable_ints(tp);
6996
6997 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
6998 HOSTCC_MODE_NOW);
6999
7000 for (i = 0; i < 5; i++) {
7001 u32 int_mbox, misc_host_ctrl;
7002
7003 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
7004 TG3_64BIT_REG_LOW);
7005 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7006
7007 if ((int_mbox != 0) ||
7008 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7009 intr_ok = 1;
7010 break;
7011 }
7012
7013 msleep(10);
7014 }
7015
7016 tg3_disable_ints(tp);
7017
7018 free_irq(tp->pdev->irq, dev);
7019
7020 err = tg3_request_irq(tp);
7021
7022 if (err)
7023 return err;
7024
7025 if (intr_ok)
7026 return 0;
7027
7028 return -EIO;
7029 }
7030
7031 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7032 * successfully restored
7033 */
7034 static int tg3_test_msi(struct tg3 *tp)
7035 {
7036 struct net_device *dev = tp->dev;
7037 int err;
7038 u16 pci_cmd;
7039
7040 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7041 return 0;
7042
7043 /* Turn off SERR reporting in case MSI terminates with Master
7044 * Abort.
7045 */
7046 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7047 pci_write_config_word(tp->pdev, PCI_COMMAND,
7048 pci_cmd & ~PCI_COMMAND_SERR);
7049
7050 err = tg3_test_interrupt(tp);
7051
7052 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7053
7054 if (!err)
7055 return 0;
7056
7057 /* other failures */
7058 if (err != -EIO)
7059 return err;
7060
7061 /* MSI test failed, go back to INTx mode */
7062 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7063 "switching to INTx mode. Please report this failure to "
7064 "the PCI maintainer and include system chipset information.\n",
7065 tp->dev->name);
7066
7067 free_irq(tp->pdev->irq, dev);
7068 pci_disable_msi(tp->pdev);
7069
7070 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7071
7072 err = tg3_request_irq(tp);
7073 if (err)
7074 return err;
7075
7076 /* Need to reset the chip because the MSI cycle may have terminated
7077 * with Master Abort.
7078 */
7079 tg3_full_lock(tp, 1);
7080
7081 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7082 err = tg3_init_hw(tp, 1);
7083
7084 tg3_full_unlock(tp);
7085
7086 if (err)
7087 free_irq(tp->pdev->irq, dev);
7088
7089 return err;
7090 }
7091
7092 static int tg3_open(struct net_device *dev)
7093 {
7094 struct tg3 *tp = netdev_priv(dev);
7095 int err;
7096
7097 netif_carrier_off(tp->dev);
7098
7099 tg3_full_lock(tp, 0);
7100
7101 err = tg3_set_power_state(tp, PCI_D0);
7102 if (err) {
7103 tg3_full_unlock(tp);
7104 return err;
7105 }
7106
7107 tg3_disable_ints(tp);
7108 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7109
7110 tg3_full_unlock(tp);
7111
7112 /* The placement of this call is tied
7113 * to the setup and use of Host TX descriptors.
7114 */
7115 err = tg3_alloc_consistent(tp);
7116 if (err)
7117 return err;
7118
7119 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
7120 /* All MSI supporting chips should support tagged
7121 * status. Assert that this is the case.
7122 */
7123 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7124 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7125 "Not using MSI.\n", tp->dev->name);
7126 } else if (pci_enable_msi(tp->pdev) == 0) {
7127 u32 msi_mode;
7128
7129 /* Hardware bug - MSI won't work if INTX disabled. */
7130 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7131 pci_intx(tp->pdev, 1);
7132
7133 msi_mode = tr32(MSGINT_MODE);
7134 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7135 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7136 }
7137 }
7138 err = tg3_request_irq(tp);
7139
7140 if (err) {
7141 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7142 pci_disable_msi(tp->pdev);
7143 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7144 }
7145 tg3_free_consistent(tp);
7146 return err;
7147 }
7148
7149 napi_enable(&tp->napi);
7150
7151 tg3_full_lock(tp, 0);
7152
7153 err = tg3_init_hw(tp, 1);
7154 if (err) {
7155 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7156 tg3_free_rings(tp);
7157 } else {
7158 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7159 tp->timer_offset = HZ;
7160 else
7161 tp->timer_offset = HZ / 10;
7162
7163 BUG_ON(tp->timer_offset > HZ);
7164 tp->timer_counter = tp->timer_multiplier =
7165 (HZ / tp->timer_offset);
7166 tp->asf_counter = tp->asf_multiplier =
7167 ((HZ / tp->timer_offset) * 2);
7168
7169 init_timer(&tp->timer);
7170 tp->timer.expires = jiffies + tp->timer_offset;
7171 tp->timer.data = (unsigned long) tp;
7172 tp->timer.function = tg3_timer;
7173 }
7174
7175 tg3_full_unlock(tp);
7176
7177 if (err) {
7178 napi_disable(&tp->napi);
7179 free_irq(tp->pdev->irq, dev);
7180 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7181 pci_disable_msi(tp->pdev);
7182 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7183 }
7184 tg3_free_consistent(tp);
7185 return err;
7186 }
7187
7188 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7189 err = tg3_test_msi(tp);
7190
7191 if (err) {
7192 tg3_full_lock(tp, 0);
7193
7194 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7195 pci_disable_msi(tp->pdev);
7196 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7197 }
7198 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7199 tg3_free_rings(tp);
7200 tg3_free_consistent(tp);
7201
7202 tg3_full_unlock(tp);
7203
7204 napi_disable(&tp->napi);
7205
7206 return err;
7207 }
7208
7209 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7210 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
7211 u32 val = tr32(PCIE_TRANSACTION_CFG);
7212
7213 tw32(PCIE_TRANSACTION_CFG,
7214 val | PCIE_TRANS_CFG_1SHOT_MSI);
7215 }
7216 }
7217 }
7218
7219 tg3_full_lock(tp, 0);
7220
7221 add_timer(&tp->timer);
7222 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7223 tg3_enable_ints(tp);
7224
7225 tg3_full_unlock(tp);
7226
7227 netif_start_queue(dev);
7228
7229 return 0;
7230 }
7231
7232 #if 0
7233 /*static*/ void tg3_dump_state(struct tg3 *tp)
7234 {
7235 u32 val32, val32_2, val32_3, val32_4, val32_5;
7236 u16 val16;
7237 int i;
7238
7239 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7240 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7241 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7242 val16, val32);
7243
7244 /* MAC block */
7245 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7246 tr32(MAC_MODE), tr32(MAC_STATUS));
7247 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7248 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7249 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7250 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7251 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7252 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7253
7254 /* Send data initiator control block */
7255 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7256 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7257 printk(" SNDDATAI_STATSCTRL[%08x]\n",
7258 tr32(SNDDATAI_STATSCTRL));
7259
7260 /* Send data completion control block */
7261 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7262
7263 /* Send BD ring selector block */
7264 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7265 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7266
7267 /* Send BD initiator control block */
7268 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7269 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7270
7271 /* Send BD completion control block */
7272 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7273
7274 /* Receive list placement control block */
7275 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7276 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7277 printk(" RCVLPC_STATSCTRL[%08x]\n",
7278 tr32(RCVLPC_STATSCTRL));
7279
7280 /* Receive data and receive BD initiator control block */
7281 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7282 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7283
7284 /* Receive data completion control block */
7285 printk("DEBUG: RCVDCC_MODE[%08x]\n",
7286 tr32(RCVDCC_MODE));
7287
7288 /* Receive BD initiator control block */
7289 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7290 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7291
7292 /* Receive BD completion control block */
7293 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7294 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7295
7296 /* Receive list selector control block */
7297 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7298 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7299
7300 /* Mbuf cluster free block */
7301 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7302 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7303
7304 /* Host coalescing control block */
7305 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7306 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7307 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7308 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7309 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7310 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7311 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7312 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7313 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7314 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7315 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7316 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7317
7318 /* Memory arbiter control block */
7319 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7320 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7321
7322 /* Buffer manager control block */
7323 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7324 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7325 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7326 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7327 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7328 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7329 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7330 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7331
7332 /* Read DMA control block */
7333 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7334 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7335
7336 /* Write DMA control block */
7337 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7338 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7339
7340 /* DMA completion block */
7341 printk("DEBUG: DMAC_MODE[%08x]\n",
7342 tr32(DMAC_MODE));
7343
7344 /* GRC block */
7345 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7346 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7347 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7348 tr32(GRC_LOCAL_CTRL));
7349
7350 /* TG3_BDINFOs */
7351 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7352 tr32(RCVDBDI_JUMBO_BD + 0x0),
7353 tr32(RCVDBDI_JUMBO_BD + 0x4),
7354 tr32(RCVDBDI_JUMBO_BD + 0x8),
7355 tr32(RCVDBDI_JUMBO_BD + 0xc));
7356 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7357 tr32(RCVDBDI_STD_BD + 0x0),
7358 tr32(RCVDBDI_STD_BD + 0x4),
7359 tr32(RCVDBDI_STD_BD + 0x8),
7360 tr32(RCVDBDI_STD_BD + 0xc));
7361 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7362 tr32(RCVDBDI_MINI_BD + 0x0),
7363 tr32(RCVDBDI_MINI_BD + 0x4),
7364 tr32(RCVDBDI_MINI_BD + 0x8),
7365 tr32(RCVDBDI_MINI_BD + 0xc));
7366
7367 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
7368 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
7369 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
7370 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
7371 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
7372 val32, val32_2, val32_3, val32_4);
7373
7374 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
7375 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
7376 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
7377 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
7378 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
7379 val32, val32_2, val32_3, val32_4);
7380
7381 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
7382 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
7383 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
7384 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
7385 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
7386 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
7387 val32, val32_2, val32_3, val32_4, val32_5);
7388
7389 /* SW status block */
7390 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
7391 tp->hw_status->status,
7392 tp->hw_status->status_tag,
7393 tp->hw_status->rx_jumbo_consumer,
7394 tp->hw_status->rx_consumer,
7395 tp->hw_status->rx_mini_consumer,
7396 tp->hw_status->idx[0].rx_producer,
7397 tp->hw_status->idx[0].tx_consumer);
7398
7399 /* SW statistics block */
7400 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7401 ((u32 *)tp->hw_stats)[0],
7402 ((u32 *)tp->hw_stats)[1],
7403 ((u32 *)tp->hw_stats)[2],
7404 ((u32 *)tp->hw_stats)[3]);
7405
7406 /* Mailboxes */
7407 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
7408 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
7409 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
7410 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
7411 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
7412
7413 /* NIC side send descriptors. */
7414 for (i = 0; i < 6; i++) {
7415 unsigned long txd;
7416
7417 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
7418 + (i * sizeof(struct tg3_tx_buffer_desc));
7419 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7420 i,
7421 readl(txd + 0x0), readl(txd + 0x4),
7422 readl(txd + 0x8), readl(txd + 0xc));
7423 }
7424
7425 /* NIC side RX descriptors. */
7426 for (i = 0; i < 6; i++) {
7427 unsigned long rxd;
7428
7429 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
7430 + (i * sizeof(struct tg3_rx_buffer_desc));
7431 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7432 i,
7433 readl(rxd + 0x0), readl(rxd + 0x4),
7434 readl(rxd + 0x8), readl(rxd + 0xc));
7435 rxd += (4 * sizeof(u32));
7436 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7437 i,
7438 readl(rxd + 0x0), readl(rxd + 0x4),
7439 readl(rxd + 0x8), readl(rxd + 0xc));
7440 }
7441
7442 for (i = 0; i < 6; i++) {
7443 unsigned long rxd;
7444
7445 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
7446 + (i * sizeof(struct tg3_rx_buffer_desc));
7447 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7448 i,
7449 readl(rxd + 0x0), readl(rxd + 0x4),
7450 readl(rxd + 0x8), readl(rxd + 0xc));
7451 rxd += (4 * sizeof(u32));
7452 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7453 i,
7454 readl(rxd + 0x0), readl(rxd + 0x4),
7455 readl(rxd + 0x8), readl(rxd + 0xc));
7456 }
7457 }
7458 #endif
7459
7460 static struct net_device_stats *tg3_get_stats(struct net_device *);
7461 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
7462
7463 static int tg3_close(struct net_device *dev)
7464 {
7465 struct tg3 *tp = netdev_priv(dev);
7466
7467 napi_disable(&tp->napi);
7468 cancel_work_sync(&tp->reset_task);
7469
7470 netif_stop_queue(dev);
7471
7472 del_timer_sync(&tp->timer);
7473
7474 tg3_full_lock(tp, 1);
7475 #if 0
7476 tg3_dump_state(tp);
7477 #endif
7478
7479 tg3_disable_ints(tp);
7480
7481 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7482 tg3_free_rings(tp);
7483 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7484
7485 tg3_full_unlock(tp);
7486
7487 free_irq(tp->pdev->irq, dev);
7488 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7489 pci_disable_msi(tp->pdev);
7490 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7491 }
7492
7493 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
7494 sizeof(tp->net_stats_prev));
7495 memcpy(&tp->estats_prev, tg3_get_estats(tp),
7496 sizeof(tp->estats_prev));
7497
7498 tg3_free_consistent(tp);
7499
7500 tg3_set_power_state(tp, PCI_D3hot);
7501
7502 netif_carrier_off(tp->dev);
7503
7504 return 0;
7505 }
7506
7507 static inline unsigned long get_stat64(tg3_stat64_t *val)
7508 {
7509 unsigned long ret;
7510
7511 #if (BITS_PER_LONG == 32)
7512 ret = val->low;
7513 #else
7514 ret = ((u64)val->high << 32) | ((u64)val->low);
7515 #endif
7516 return ret;
7517 }
7518
7519 static unsigned long calc_crc_errors(struct tg3 *tp)
7520 {
7521 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7522
7523 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7524 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7525 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
7526 u32 val;
7527
7528 spin_lock_bh(&tp->lock);
7529 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
7530 tg3_writephy(tp, MII_TG3_TEST1,
7531 val | MII_TG3_TEST1_CRC_EN);
7532 tg3_readphy(tp, 0x14, &val);
7533 } else
7534 val = 0;
7535 spin_unlock_bh(&tp->lock);
7536
7537 tp->phy_crc_errors += val;
7538
7539 return tp->phy_crc_errors;
7540 }
7541
7542 return get_stat64(&hw_stats->rx_fcs_errors);
7543 }
7544
7545 #define ESTAT_ADD(member) \
7546 estats->member = old_estats->member + \
7547 get_stat64(&hw_stats->member)
7548
7549 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
7550 {
7551 struct tg3_ethtool_stats *estats = &tp->estats;
7552 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
7553 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7554
7555 if (!hw_stats)
7556 return old_estats;
7557
7558 ESTAT_ADD(rx_octets);
7559 ESTAT_ADD(rx_fragments);
7560 ESTAT_ADD(rx_ucast_packets);
7561 ESTAT_ADD(rx_mcast_packets);
7562 ESTAT_ADD(rx_bcast_packets);
7563 ESTAT_ADD(rx_fcs_errors);
7564 ESTAT_ADD(rx_align_errors);
7565 ESTAT_ADD(rx_xon_pause_rcvd);
7566 ESTAT_ADD(rx_xoff_pause_rcvd);
7567 ESTAT_ADD(rx_mac_ctrl_rcvd);
7568 ESTAT_ADD(rx_xoff_entered);
7569 ESTAT_ADD(rx_frame_too_long_errors);
7570 ESTAT_ADD(rx_jabbers);
7571 ESTAT_ADD(rx_undersize_packets);
7572 ESTAT_ADD(rx_in_length_errors);
7573 ESTAT_ADD(rx_out_length_errors);
7574 ESTAT_ADD(rx_64_or_less_octet_packets);
7575 ESTAT_ADD(rx_65_to_127_octet_packets);
7576 ESTAT_ADD(rx_128_to_255_octet_packets);
7577 ESTAT_ADD(rx_256_to_511_octet_packets);
7578 ESTAT_ADD(rx_512_to_1023_octet_packets);
7579 ESTAT_ADD(rx_1024_to_1522_octet_packets);
7580 ESTAT_ADD(rx_1523_to_2047_octet_packets);
7581 ESTAT_ADD(rx_2048_to_4095_octet_packets);
7582 ESTAT_ADD(rx_4096_to_8191_octet_packets);
7583 ESTAT_ADD(rx_8192_to_9022_octet_packets);
7584
7585 ESTAT_ADD(tx_octets);
7586 ESTAT_ADD(tx_collisions);
7587 ESTAT_ADD(tx_xon_sent);
7588 ESTAT_ADD(tx_xoff_sent);
7589 ESTAT_ADD(tx_flow_control);
7590 ESTAT_ADD(tx_mac_errors);
7591 ESTAT_ADD(tx_single_collisions);
7592 ESTAT_ADD(tx_mult_collisions);
7593 ESTAT_ADD(tx_deferred);
7594 ESTAT_ADD(tx_excessive_collisions);
7595 ESTAT_ADD(tx_late_collisions);
7596 ESTAT_ADD(tx_collide_2times);
7597 ESTAT_ADD(tx_collide_3times);
7598 ESTAT_ADD(tx_collide_4times);
7599 ESTAT_ADD(tx_collide_5times);
7600 ESTAT_ADD(tx_collide_6times);
7601 ESTAT_ADD(tx_collide_7times);
7602 ESTAT_ADD(tx_collide_8times);
7603 ESTAT_ADD(tx_collide_9times);
7604 ESTAT_ADD(tx_collide_10times);
7605 ESTAT_ADD(tx_collide_11times);
7606 ESTAT_ADD(tx_collide_12times);
7607 ESTAT_ADD(tx_collide_13times);
7608 ESTAT_ADD(tx_collide_14times);
7609 ESTAT_ADD(tx_collide_15times);
7610 ESTAT_ADD(tx_ucast_packets);
7611 ESTAT_ADD(tx_mcast_packets);
7612 ESTAT_ADD(tx_bcast_packets);
7613 ESTAT_ADD(tx_carrier_sense_errors);
7614 ESTAT_ADD(tx_discards);
7615 ESTAT_ADD(tx_errors);
7616
7617 ESTAT_ADD(dma_writeq_full);
7618 ESTAT_ADD(dma_write_prioq_full);
7619 ESTAT_ADD(rxbds_empty);
7620 ESTAT_ADD(rx_discards);
7621 ESTAT_ADD(rx_errors);
7622 ESTAT_ADD(rx_threshold_hit);
7623
7624 ESTAT_ADD(dma_readq_full);
7625 ESTAT_ADD(dma_read_prioq_full);
7626 ESTAT_ADD(tx_comp_queue_full);
7627
7628 ESTAT_ADD(ring_set_send_prod_index);
7629 ESTAT_ADD(ring_status_update);
7630 ESTAT_ADD(nic_irqs);
7631 ESTAT_ADD(nic_avoided_irqs);
7632 ESTAT_ADD(nic_tx_threshold_hit);
7633
7634 return estats;
7635 }
7636
7637 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
7638 {
7639 struct tg3 *tp = netdev_priv(dev);
7640 struct net_device_stats *stats = &tp->net_stats;
7641 struct net_device_stats *old_stats = &tp->net_stats_prev;
7642 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7643
7644 if (!hw_stats)
7645 return old_stats;
7646
7647 stats->rx_packets = old_stats->rx_packets +
7648 get_stat64(&hw_stats->rx_ucast_packets) +
7649 get_stat64(&hw_stats->rx_mcast_packets) +
7650 get_stat64(&hw_stats->rx_bcast_packets);
7651
7652 stats->tx_packets = old_stats->tx_packets +
7653 get_stat64(&hw_stats->tx_ucast_packets) +
7654 get_stat64(&hw_stats->tx_mcast_packets) +
7655 get_stat64(&hw_stats->tx_bcast_packets);
7656
7657 stats->rx_bytes = old_stats->rx_bytes +
7658 get_stat64(&hw_stats->rx_octets);
7659 stats->tx_bytes = old_stats->tx_bytes +
7660 get_stat64(&hw_stats->tx_octets);
7661
7662 stats->rx_errors = old_stats->rx_errors +
7663 get_stat64(&hw_stats->rx_errors);
7664 stats->tx_errors = old_stats->tx_errors +
7665 get_stat64(&hw_stats->tx_errors) +
7666 get_stat64(&hw_stats->tx_mac_errors) +
7667 get_stat64(&hw_stats->tx_carrier_sense_errors) +
7668 get_stat64(&hw_stats->tx_discards);
7669
7670 stats->multicast = old_stats->multicast +
7671 get_stat64(&hw_stats->rx_mcast_packets);
7672 stats->collisions = old_stats->collisions +
7673 get_stat64(&hw_stats->tx_collisions);
7674
7675 stats->rx_length_errors = old_stats->rx_length_errors +
7676 get_stat64(&hw_stats->rx_frame_too_long_errors) +
7677 get_stat64(&hw_stats->rx_undersize_packets);
7678
7679 stats->rx_over_errors = old_stats->rx_over_errors +
7680 get_stat64(&hw_stats->rxbds_empty);
7681 stats->rx_frame_errors = old_stats->rx_frame_errors +
7682 get_stat64(&hw_stats->rx_align_errors);
7683 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
7684 get_stat64(&hw_stats->tx_discards);
7685 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
7686 get_stat64(&hw_stats->tx_carrier_sense_errors);
7687
7688 stats->rx_crc_errors = old_stats->rx_crc_errors +
7689 calc_crc_errors(tp);
7690
7691 stats->rx_missed_errors = old_stats->rx_missed_errors +
7692 get_stat64(&hw_stats->rx_discards);
7693
7694 return stats;
7695 }
7696
7697 static inline u32 calc_crc(unsigned char *buf, int len)
7698 {
7699 u32 reg;
7700 u32 tmp;
7701 int j, k;
7702
7703 reg = 0xffffffff;
7704
7705 for (j = 0; j < len; j++) {
7706 reg ^= buf[j];
7707
7708 for (k = 0; k < 8; k++) {
7709 tmp = reg & 0x01;
7710
7711 reg >>= 1;
7712
7713 if (tmp) {
7714 reg ^= 0xedb88320;
7715 }
7716 }
7717 }
7718
7719 return ~reg;
7720 }
7721
7722 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
7723 {
7724 /* accept or reject all multicast frames */
7725 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
7726 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
7727 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
7728 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
7729 }
7730
7731 static void __tg3_set_rx_mode(struct net_device *dev)
7732 {
7733 struct tg3 *tp = netdev_priv(dev);
7734 u32 rx_mode;
7735
7736 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
7737 RX_MODE_KEEP_VLAN_TAG);
7738
7739 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
7740 * flag clear.
7741 */
7742 #if TG3_VLAN_TAG_USED
7743 if (!tp->vlgrp &&
7744 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7745 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7746 #else
7747 /* By definition, VLAN is disabled always in this
7748 * case.
7749 */
7750 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7751 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7752 #endif
7753
7754 if (dev->flags & IFF_PROMISC) {
7755 /* Promiscuous mode. */
7756 rx_mode |= RX_MODE_PROMISC;
7757 } else if (dev->flags & IFF_ALLMULTI) {
7758 /* Accept all multicast. */
7759 tg3_set_multi (tp, 1);
7760 } else if (dev->mc_count < 1) {
7761 /* Reject all multicast. */
7762 tg3_set_multi (tp, 0);
7763 } else {
7764 /* Accept one or more multicast(s). */
7765 struct dev_mc_list *mclist;
7766 unsigned int i;
7767 u32 mc_filter[4] = { 0, };
7768 u32 regidx;
7769 u32 bit;
7770 u32 crc;
7771
7772 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
7773 i++, mclist = mclist->next) {
7774
7775 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
7776 bit = ~crc & 0x7f;
7777 regidx = (bit & 0x60) >> 5;
7778 bit &= 0x1f;
7779 mc_filter[regidx] |= (1 << bit);
7780 }
7781
7782 tw32(MAC_HASH_REG_0, mc_filter[0]);
7783 tw32(MAC_HASH_REG_1, mc_filter[1]);
7784 tw32(MAC_HASH_REG_2, mc_filter[2]);
7785 tw32(MAC_HASH_REG_3, mc_filter[3]);
7786 }
7787
7788 if (rx_mode != tp->rx_mode) {
7789 tp->rx_mode = rx_mode;
7790 tw32_f(MAC_RX_MODE, rx_mode);
7791 udelay(10);
7792 }
7793 }
7794
7795 static void tg3_set_rx_mode(struct net_device *dev)
7796 {
7797 struct tg3 *tp = netdev_priv(dev);
7798
7799 if (!netif_running(dev))
7800 return;
7801
7802 tg3_full_lock(tp, 0);
7803 __tg3_set_rx_mode(dev);
7804 tg3_full_unlock(tp);
7805 }
7806
7807 #define TG3_REGDUMP_LEN (32 * 1024)
7808
7809 static int tg3_get_regs_len(struct net_device *dev)
7810 {
7811 return TG3_REGDUMP_LEN;
7812 }
7813
7814 static void tg3_get_regs(struct net_device *dev,
7815 struct ethtool_regs *regs, void *_p)
7816 {
7817 u32 *p = _p;
7818 struct tg3 *tp = netdev_priv(dev);
7819 u8 *orig_p = _p;
7820 int i;
7821
7822 regs->version = 0;
7823
7824 memset(p, 0, TG3_REGDUMP_LEN);
7825
7826 if (tp->link_config.phy_is_low_power)
7827 return;
7828
7829 tg3_full_lock(tp, 0);
7830
7831 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
7832 #define GET_REG32_LOOP(base,len) \
7833 do { p = (u32 *)(orig_p + (base)); \
7834 for (i = 0; i < len; i += 4) \
7835 __GET_REG32((base) + i); \
7836 } while (0)
7837 #define GET_REG32_1(reg) \
7838 do { p = (u32 *)(orig_p + (reg)); \
7839 __GET_REG32((reg)); \
7840 } while (0)
7841
7842 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
7843 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
7844 GET_REG32_LOOP(MAC_MODE, 0x4f0);
7845 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
7846 GET_REG32_1(SNDDATAC_MODE);
7847 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
7848 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
7849 GET_REG32_1(SNDBDC_MODE);
7850 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
7851 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
7852 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
7853 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
7854 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
7855 GET_REG32_1(RCVDCC_MODE);
7856 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
7857 GET_REG32_LOOP(RCVCC_MODE, 0x14);
7858 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
7859 GET_REG32_1(MBFREE_MODE);
7860 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
7861 GET_REG32_LOOP(MEMARB_MODE, 0x10);
7862 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7863 GET_REG32_LOOP(RDMAC_MODE, 0x08);
7864 GET_REG32_LOOP(WDMAC_MODE, 0x08);
7865 GET_REG32_1(RX_CPU_MODE);
7866 GET_REG32_1(RX_CPU_STATE);
7867 GET_REG32_1(RX_CPU_PGMCTR);
7868 GET_REG32_1(RX_CPU_HWBKPT);
7869 GET_REG32_1(TX_CPU_MODE);
7870 GET_REG32_1(TX_CPU_STATE);
7871 GET_REG32_1(TX_CPU_PGMCTR);
7872 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7873 GET_REG32_LOOP(FTQ_RESET, 0x120);
7874 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
7875 GET_REG32_1(DMAC_MODE);
7876 GET_REG32_LOOP(GRC_MODE, 0x4c);
7877 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7878 GET_REG32_LOOP(NVRAM_CMD, 0x24);
7879
7880 #undef __GET_REG32
7881 #undef GET_REG32_LOOP
7882 #undef GET_REG32_1
7883
7884 tg3_full_unlock(tp);
7885 }
7886
7887 static int tg3_get_eeprom_len(struct net_device *dev)
7888 {
7889 struct tg3 *tp = netdev_priv(dev);
7890
7891 return tp->nvram_size;
7892 }
7893
7894 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
7895 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
7896
7897 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7898 {
7899 struct tg3 *tp = netdev_priv(dev);
7900 int ret;
7901 u8 *pd;
7902 u32 i, offset, len, val, b_offset, b_count;
7903
7904 if (tp->link_config.phy_is_low_power)
7905 return -EAGAIN;
7906
7907 offset = eeprom->offset;
7908 len = eeprom->len;
7909 eeprom->len = 0;
7910
7911 eeprom->magic = TG3_EEPROM_MAGIC;
7912
7913 if (offset & 3) {
7914 /* adjustments to start on required 4 byte boundary */
7915 b_offset = offset & 3;
7916 b_count = 4 - b_offset;
7917 if (b_count > len) {
7918 /* i.e. offset=1 len=2 */
7919 b_count = len;
7920 }
7921 ret = tg3_nvram_read(tp, offset-b_offset, &val);
7922 if (ret)
7923 return ret;
7924 val = cpu_to_le32(val);
7925 memcpy(data, ((char*)&val) + b_offset, b_count);
7926 len -= b_count;
7927 offset += b_count;
7928 eeprom->len += b_count;
7929 }
7930
7931 /* read bytes upto the last 4 byte boundary */
7932 pd = &data[eeprom->len];
7933 for (i = 0; i < (len - (len & 3)); i += 4) {
7934 ret = tg3_nvram_read(tp, offset + i, &val);
7935 if (ret) {
7936 eeprom->len += i;
7937 return ret;
7938 }
7939 val = cpu_to_le32(val);
7940 memcpy(pd + i, &val, 4);
7941 }
7942 eeprom->len += i;
7943
7944 if (len & 3) {
7945 /* read last bytes not ending on 4 byte boundary */
7946 pd = &data[eeprom->len];
7947 b_count = len & 3;
7948 b_offset = offset + len - b_count;
7949 ret = tg3_nvram_read(tp, b_offset, &val);
7950 if (ret)
7951 return ret;
7952 val = cpu_to_le32(val);
7953 memcpy(pd, ((char*)&val), b_count);
7954 eeprom->len += b_count;
7955 }
7956 return 0;
7957 }
7958
7959 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
7960
7961 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7962 {
7963 struct tg3 *tp = netdev_priv(dev);
7964 int ret;
7965 u32 offset, len, b_offset, odd_len, start, end;
7966 u8 *buf;
7967
7968 if (tp->link_config.phy_is_low_power)
7969 return -EAGAIN;
7970
7971 if (eeprom->magic != TG3_EEPROM_MAGIC)
7972 return -EINVAL;
7973
7974 offset = eeprom->offset;
7975 len = eeprom->len;
7976
7977 if ((b_offset = (offset & 3))) {
7978 /* adjustments to start on required 4 byte boundary */
7979 ret = tg3_nvram_read(tp, offset-b_offset, &start);
7980 if (ret)
7981 return ret;
7982 start = cpu_to_le32(start);
7983 len += b_offset;
7984 offset &= ~3;
7985 if (len < 4)
7986 len = 4;
7987 }
7988
7989 odd_len = 0;
7990 if (len & 3) {
7991 /* adjustments to end on required 4 byte boundary */
7992 odd_len = 1;
7993 len = (len + 3) & ~3;
7994 ret = tg3_nvram_read(tp, offset+len-4, &end);
7995 if (ret)
7996 return ret;
7997 end = cpu_to_le32(end);
7998 }
7999
8000 buf = data;
8001 if (b_offset || odd_len) {
8002 buf = kmalloc(len, GFP_KERNEL);
8003 if (!buf)
8004 return -ENOMEM;
8005 if (b_offset)
8006 memcpy(buf, &start, 4);
8007 if (odd_len)
8008 memcpy(buf+len-4, &end, 4);
8009 memcpy(buf + b_offset, data, eeprom->len);
8010 }
8011
8012 ret = tg3_nvram_write_block(tp, offset, len, buf);
8013
8014 if (buf != data)
8015 kfree(buf);
8016
8017 return ret;
8018 }
8019
8020 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8021 {
8022 struct tg3 *tp = netdev_priv(dev);
8023
8024 cmd->supported = (SUPPORTED_Autoneg);
8025
8026 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8027 cmd->supported |= (SUPPORTED_1000baseT_Half |
8028 SUPPORTED_1000baseT_Full);
8029
8030 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
8031 cmd->supported |= (SUPPORTED_100baseT_Half |
8032 SUPPORTED_100baseT_Full |
8033 SUPPORTED_10baseT_Half |
8034 SUPPORTED_10baseT_Full |
8035 SUPPORTED_MII);
8036 cmd->port = PORT_TP;
8037 } else {
8038 cmd->supported |= SUPPORTED_FIBRE;
8039 cmd->port = PORT_FIBRE;
8040 }
8041
8042 cmd->advertising = tp->link_config.advertising;
8043 if (netif_running(dev)) {
8044 cmd->speed = tp->link_config.active_speed;
8045 cmd->duplex = tp->link_config.active_duplex;
8046 }
8047 cmd->phy_address = PHY_ADDR;
8048 cmd->transceiver = 0;
8049 cmd->autoneg = tp->link_config.autoneg;
8050 cmd->maxtxpkt = 0;
8051 cmd->maxrxpkt = 0;
8052 return 0;
8053 }
8054
8055 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8056 {
8057 struct tg3 *tp = netdev_priv(dev);
8058
8059 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8060 /* These are the only valid advertisement bits allowed. */
8061 if (cmd->autoneg == AUTONEG_ENABLE &&
8062 (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
8063 ADVERTISED_1000baseT_Full |
8064 ADVERTISED_Autoneg |
8065 ADVERTISED_FIBRE)))
8066 return -EINVAL;
8067 /* Fiber can only do SPEED_1000. */
8068 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
8069 (cmd->speed != SPEED_1000))
8070 return -EINVAL;
8071 /* Copper cannot force SPEED_1000. */
8072 } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
8073 (cmd->speed == SPEED_1000))
8074 return -EINVAL;
8075 else if ((cmd->speed == SPEED_1000) &&
8076 (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8077 return -EINVAL;
8078
8079 tg3_full_lock(tp, 0);
8080
8081 tp->link_config.autoneg = cmd->autoneg;
8082 if (cmd->autoneg == AUTONEG_ENABLE) {
8083 tp->link_config.advertising = cmd->advertising;
8084 tp->link_config.speed = SPEED_INVALID;
8085 tp->link_config.duplex = DUPLEX_INVALID;
8086 } else {
8087 tp->link_config.advertising = 0;
8088 tp->link_config.speed = cmd->speed;
8089 tp->link_config.duplex = cmd->duplex;
8090 }
8091
8092 tp->link_config.orig_speed = tp->link_config.speed;
8093 tp->link_config.orig_duplex = tp->link_config.duplex;
8094 tp->link_config.orig_autoneg = tp->link_config.autoneg;
8095
8096 if (netif_running(dev))
8097 tg3_setup_phy(tp, 1);
8098
8099 tg3_full_unlock(tp);
8100
8101 return 0;
8102 }
8103
8104 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8105 {
8106 struct tg3 *tp = netdev_priv(dev);
8107
8108 strcpy(info->driver, DRV_MODULE_NAME);
8109 strcpy(info->version, DRV_MODULE_VERSION);
8110 strcpy(info->fw_version, tp->fw_ver);
8111 strcpy(info->bus_info, pci_name(tp->pdev));
8112 }
8113
8114 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8115 {
8116 struct tg3 *tp = netdev_priv(dev);
8117
8118 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
8119 wol->supported = WAKE_MAGIC;
8120 else
8121 wol->supported = 0;
8122 wol->wolopts = 0;
8123 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
8124 wol->wolopts = WAKE_MAGIC;
8125 memset(&wol->sopass, 0, sizeof(wol->sopass));
8126 }
8127
8128 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8129 {
8130 struct tg3 *tp = netdev_priv(dev);
8131
8132 if (wol->wolopts & ~WAKE_MAGIC)
8133 return -EINVAL;
8134 if ((wol->wolopts & WAKE_MAGIC) &&
8135 !(tp->tg3_flags & TG3_FLAG_WOL_CAP))
8136 return -EINVAL;
8137
8138 spin_lock_bh(&tp->lock);
8139 if (wol->wolopts & WAKE_MAGIC)
8140 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8141 else
8142 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8143 spin_unlock_bh(&tp->lock);
8144
8145 return 0;
8146 }
8147
8148 static u32 tg3_get_msglevel(struct net_device *dev)
8149 {
8150 struct tg3 *tp = netdev_priv(dev);
8151 return tp->msg_enable;
8152 }
8153
8154 static void tg3_set_msglevel(struct net_device *dev, u32 value)
8155 {
8156 struct tg3 *tp = netdev_priv(dev);
8157 tp->msg_enable = value;
8158 }
8159
8160 static int tg3_set_tso(struct net_device *dev, u32 value)
8161 {
8162 struct tg3 *tp = netdev_priv(dev);
8163
8164 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8165 if (value)
8166 return -EINVAL;
8167 return 0;
8168 }
8169 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
8170 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
8171 if (value)
8172 dev->features |= NETIF_F_TSO6;
8173 else
8174 dev->features &= ~NETIF_F_TSO6;
8175 }
8176 return ethtool_op_set_tso(dev, value);
8177 }
8178
8179 static int tg3_nway_reset(struct net_device *dev)
8180 {
8181 struct tg3 *tp = netdev_priv(dev);
8182 u32 bmcr;
8183 int r;
8184
8185 if (!netif_running(dev))
8186 return -EAGAIN;
8187
8188 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8189 return -EINVAL;
8190
8191 spin_lock_bh(&tp->lock);
8192 r = -EINVAL;
8193 tg3_readphy(tp, MII_BMCR, &bmcr);
8194 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8195 ((bmcr & BMCR_ANENABLE) ||
8196 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8197 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8198 BMCR_ANENABLE);
8199 r = 0;
8200 }
8201 spin_unlock_bh(&tp->lock);
8202
8203 return r;
8204 }
8205
8206 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8207 {
8208 struct tg3 *tp = netdev_priv(dev);
8209
8210 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8211 ering->rx_mini_max_pending = 0;
8212 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8213 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8214 else
8215 ering->rx_jumbo_max_pending = 0;
8216
8217 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
8218
8219 ering->rx_pending = tp->rx_pending;
8220 ering->rx_mini_pending = 0;
8221 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8222 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8223 else
8224 ering->rx_jumbo_pending = 0;
8225
8226 ering->tx_pending = tp->tx_pending;
8227 }
8228
8229 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8230 {
8231 struct tg3 *tp = netdev_priv(dev);
8232 int irq_sync = 0, err = 0;
8233
8234 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8235 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
8236 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8237 (ering->tx_pending <= MAX_SKB_FRAGS) ||
8238 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
8239 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
8240 return -EINVAL;
8241
8242 if (netif_running(dev)) {
8243 tg3_netif_stop(tp);
8244 irq_sync = 1;
8245 }
8246
8247 tg3_full_lock(tp, irq_sync);
8248
8249 tp->rx_pending = ering->rx_pending;
8250
8251 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8252 tp->rx_pending > 63)
8253 tp->rx_pending = 63;
8254 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8255 tp->tx_pending = ering->tx_pending;
8256
8257 if (netif_running(dev)) {
8258 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8259 err = tg3_restart_hw(tp, 1);
8260 if (!err)
8261 tg3_netif_start(tp);
8262 }
8263
8264 tg3_full_unlock(tp);
8265
8266 return err;
8267 }
8268
8269 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8270 {
8271 struct tg3 *tp = netdev_priv(dev);
8272
8273 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8274 epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
8275 epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
8276 }
8277
8278 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8279 {
8280 struct tg3 *tp = netdev_priv(dev);
8281 int irq_sync = 0, err = 0;
8282
8283 if (netif_running(dev)) {
8284 tg3_netif_stop(tp);
8285 irq_sync = 1;
8286 }
8287
8288 tg3_full_lock(tp, irq_sync);
8289
8290 if (epause->autoneg)
8291 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
8292 else
8293 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
8294 if (epause->rx_pause)
8295 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
8296 else
8297 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
8298 if (epause->tx_pause)
8299 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
8300 else
8301 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
8302
8303 if (netif_running(dev)) {
8304 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8305 err = tg3_restart_hw(tp, 1);
8306 if (!err)
8307 tg3_netif_start(tp);
8308 }
8309
8310 tg3_full_unlock(tp);
8311
8312 return err;
8313 }
8314
8315 static u32 tg3_get_rx_csum(struct net_device *dev)
8316 {
8317 struct tg3 *tp = netdev_priv(dev);
8318 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
8319 }
8320
8321 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
8322 {
8323 struct tg3 *tp = netdev_priv(dev);
8324
8325 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8326 if (data != 0)
8327 return -EINVAL;
8328 return 0;
8329 }
8330
8331 spin_lock_bh(&tp->lock);
8332 if (data)
8333 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
8334 else
8335 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
8336 spin_unlock_bh(&tp->lock);
8337
8338 return 0;
8339 }
8340
8341 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
8342 {
8343 struct tg3 *tp = netdev_priv(dev);
8344
8345 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8346 if (data != 0)
8347 return -EINVAL;
8348 return 0;
8349 }
8350
8351 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8352 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8353 ethtool_op_set_tx_ipv6_csum(dev, data);
8354 else
8355 ethtool_op_set_tx_csum(dev, data);
8356
8357 return 0;
8358 }
8359
8360 static int tg3_get_sset_count (struct net_device *dev, int sset)
8361 {
8362 switch (sset) {
8363 case ETH_SS_TEST:
8364 return TG3_NUM_TEST;
8365 case ETH_SS_STATS:
8366 return TG3_NUM_STATS;
8367 default:
8368 return -EOPNOTSUPP;
8369 }
8370 }
8371
8372 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
8373 {
8374 switch (stringset) {
8375 case ETH_SS_STATS:
8376 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
8377 break;
8378 case ETH_SS_TEST:
8379 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
8380 break;
8381 default:
8382 WARN_ON(1); /* we need a WARN() */
8383 break;
8384 }
8385 }
8386
8387 static int tg3_phys_id(struct net_device *dev, u32 data)
8388 {
8389 struct tg3 *tp = netdev_priv(dev);
8390 int i;
8391
8392 if (!netif_running(tp->dev))
8393 return -EAGAIN;
8394
8395 if (data == 0)
8396 data = 2;
8397
8398 for (i = 0; i < (data * 2); i++) {
8399 if ((i % 2) == 0)
8400 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8401 LED_CTRL_1000MBPS_ON |
8402 LED_CTRL_100MBPS_ON |
8403 LED_CTRL_10MBPS_ON |
8404 LED_CTRL_TRAFFIC_OVERRIDE |
8405 LED_CTRL_TRAFFIC_BLINK |
8406 LED_CTRL_TRAFFIC_LED);
8407
8408 else
8409 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8410 LED_CTRL_TRAFFIC_OVERRIDE);
8411
8412 if (msleep_interruptible(500))
8413 break;
8414 }
8415 tw32(MAC_LED_CTRL, tp->led_ctrl);
8416 return 0;
8417 }
8418
8419 static void tg3_get_ethtool_stats (struct net_device *dev,
8420 struct ethtool_stats *estats, u64 *tmp_stats)
8421 {
8422 struct tg3 *tp = netdev_priv(dev);
8423 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
8424 }
8425
8426 #define NVRAM_TEST_SIZE 0x100
8427 #define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
8428 #define NVRAM_SELFBOOT_HW_SIZE 0x20
8429 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
8430
8431 static int tg3_test_nvram(struct tg3 *tp)
8432 {
8433 u32 *buf, csum, magic;
8434 int i, j, k, err = 0, size;
8435
8436 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
8437 return -EIO;
8438
8439 if (magic == TG3_EEPROM_MAGIC)
8440 size = NVRAM_TEST_SIZE;
8441 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
8442 if ((magic & 0xe00000) == 0x200000)
8443 size = NVRAM_SELFBOOT_FORMAT1_SIZE;
8444 else
8445 return 0;
8446 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
8447 size = NVRAM_SELFBOOT_HW_SIZE;
8448 else
8449 return -EIO;
8450
8451 buf = kmalloc(size, GFP_KERNEL);
8452 if (buf == NULL)
8453 return -ENOMEM;
8454
8455 err = -EIO;
8456 for (i = 0, j = 0; i < size; i += 4, j++) {
8457 u32 val;
8458
8459 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
8460 break;
8461 buf[j] = cpu_to_le32(val);
8462 }
8463 if (i < size)
8464 goto out;
8465
8466 /* Selfboot format */
8467 if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_FW_MSK) ==
8468 TG3_EEPROM_MAGIC_FW) {
8469 u8 *buf8 = (u8 *) buf, csum8 = 0;
8470
8471 for (i = 0; i < size; i++)
8472 csum8 += buf8[i];
8473
8474 if (csum8 == 0) {
8475 err = 0;
8476 goto out;
8477 }
8478
8479 err = -EIO;
8480 goto out;
8481 }
8482
8483 if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_HW_MSK) ==
8484 TG3_EEPROM_MAGIC_HW) {
8485 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
8486 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
8487 u8 *buf8 = (u8 *) buf;
8488
8489 /* Separate the parity bits and the data bytes. */
8490 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
8491 if ((i == 0) || (i == 8)) {
8492 int l;
8493 u8 msk;
8494
8495 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
8496 parity[k++] = buf8[i] & msk;
8497 i++;
8498 }
8499 else if (i == 16) {
8500 int l;
8501 u8 msk;
8502
8503 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
8504 parity[k++] = buf8[i] & msk;
8505 i++;
8506
8507 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
8508 parity[k++] = buf8[i] & msk;
8509 i++;
8510 }
8511 data[j++] = buf8[i];
8512 }
8513
8514 err = -EIO;
8515 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
8516 u8 hw8 = hweight8(data[i]);
8517
8518 if ((hw8 & 0x1) && parity[i])
8519 goto out;
8520 else if (!(hw8 & 0x1) && !parity[i])
8521 goto out;
8522 }
8523 err = 0;
8524 goto out;
8525 }
8526
8527 /* Bootstrap checksum at offset 0x10 */
8528 csum = calc_crc((unsigned char *) buf, 0x10);
8529 if(csum != cpu_to_le32(buf[0x10/4]))
8530 goto out;
8531
8532 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
8533 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
8534 if (csum != cpu_to_le32(buf[0xfc/4]))
8535 goto out;
8536
8537 err = 0;
8538
8539 out:
8540 kfree(buf);
8541 return err;
8542 }
8543
8544 #define TG3_SERDES_TIMEOUT_SEC 2
8545 #define TG3_COPPER_TIMEOUT_SEC 6
8546
8547 static int tg3_test_link(struct tg3 *tp)
8548 {
8549 int i, max;
8550
8551 if (!netif_running(tp->dev))
8552 return -ENODEV;
8553
8554 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
8555 max = TG3_SERDES_TIMEOUT_SEC;
8556 else
8557 max = TG3_COPPER_TIMEOUT_SEC;
8558
8559 for (i = 0; i < max; i++) {
8560 if (netif_carrier_ok(tp->dev))
8561 return 0;
8562
8563 if (msleep_interruptible(1000))
8564 break;
8565 }
8566
8567 return -EIO;
8568 }
8569
8570 /* Only test the commonly used registers */
8571 static int tg3_test_registers(struct tg3 *tp)
8572 {
8573 int i, is_5705, is_5750;
8574 u32 offset, read_mask, write_mask, val, save_val, read_val;
8575 static struct {
8576 u16 offset;
8577 u16 flags;
8578 #define TG3_FL_5705 0x1
8579 #define TG3_FL_NOT_5705 0x2
8580 #define TG3_FL_NOT_5788 0x4
8581 #define TG3_FL_NOT_5750 0x8
8582 u32 read_mask;
8583 u32 write_mask;
8584 } reg_tbl[] = {
8585 /* MAC Control Registers */
8586 { MAC_MODE, TG3_FL_NOT_5705,
8587 0x00000000, 0x00ef6f8c },
8588 { MAC_MODE, TG3_FL_5705,
8589 0x00000000, 0x01ef6b8c },
8590 { MAC_STATUS, TG3_FL_NOT_5705,
8591 0x03800107, 0x00000000 },
8592 { MAC_STATUS, TG3_FL_5705,
8593 0x03800100, 0x00000000 },
8594 { MAC_ADDR_0_HIGH, 0x0000,
8595 0x00000000, 0x0000ffff },
8596 { MAC_ADDR_0_LOW, 0x0000,
8597 0x00000000, 0xffffffff },
8598 { MAC_RX_MTU_SIZE, 0x0000,
8599 0x00000000, 0x0000ffff },
8600 { MAC_TX_MODE, 0x0000,
8601 0x00000000, 0x00000070 },
8602 { MAC_TX_LENGTHS, 0x0000,
8603 0x00000000, 0x00003fff },
8604 { MAC_RX_MODE, TG3_FL_NOT_5705,
8605 0x00000000, 0x000007fc },
8606 { MAC_RX_MODE, TG3_FL_5705,
8607 0x00000000, 0x000007dc },
8608 { MAC_HASH_REG_0, 0x0000,
8609 0x00000000, 0xffffffff },
8610 { MAC_HASH_REG_1, 0x0000,
8611 0x00000000, 0xffffffff },
8612 { MAC_HASH_REG_2, 0x0000,
8613 0x00000000, 0xffffffff },
8614 { MAC_HASH_REG_3, 0x0000,
8615 0x00000000, 0xffffffff },
8616
8617 /* Receive Data and Receive BD Initiator Control Registers. */
8618 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
8619 0x00000000, 0xffffffff },
8620 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
8621 0x00000000, 0xffffffff },
8622 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
8623 0x00000000, 0x00000003 },
8624 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
8625 0x00000000, 0xffffffff },
8626 { RCVDBDI_STD_BD+0, 0x0000,
8627 0x00000000, 0xffffffff },
8628 { RCVDBDI_STD_BD+4, 0x0000,
8629 0x00000000, 0xffffffff },
8630 { RCVDBDI_STD_BD+8, 0x0000,
8631 0x00000000, 0xffff0002 },
8632 { RCVDBDI_STD_BD+0xc, 0x0000,
8633 0x00000000, 0xffffffff },
8634
8635 /* Receive BD Initiator Control Registers. */
8636 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
8637 0x00000000, 0xffffffff },
8638 { RCVBDI_STD_THRESH, TG3_FL_5705,
8639 0x00000000, 0x000003ff },
8640 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
8641 0x00000000, 0xffffffff },
8642
8643 /* Host Coalescing Control Registers. */
8644 { HOSTCC_MODE, TG3_FL_NOT_5705,
8645 0x00000000, 0x00000004 },
8646 { HOSTCC_MODE, TG3_FL_5705,
8647 0x00000000, 0x000000f6 },
8648 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
8649 0x00000000, 0xffffffff },
8650 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
8651 0x00000000, 0x000003ff },
8652 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
8653 0x00000000, 0xffffffff },
8654 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
8655 0x00000000, 0x000003ff },
8656 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
8657 0x00000000, 0xffffffff },
8658 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8659 0x00000000, 0x000000ff },
8660 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
8661 0x00000000, 0xffffffff },
8662 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8663 0x00000000, 0x000000ff },
8664 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
8665 0x00000000, 0xffffffff },
8666 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
8667 0x00000000, 0xffffffff },
8668 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8669 0x00000000, 0xffffffff },
8670 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8671 0x00000000, 0x000000ff },
8672 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8673 0x00000000, 0xffffffff },
8674 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8675 0x00000000, 0x000000ff },
8676 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
8677 0x00000000, 0xffffffff },
8678 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
8679 0x00000000, 0xffffffff },
8680 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
8681 0x00000000, 0xffffffff },
8682 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
8683 0x00000000, 0xffffffff },
8684 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
8685 0x00000000, 0xffffffff },
8686 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
8687 0xffffffff, 0x00000000 },
8688 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
8689 0xffffffff, 0x00000000 },
8690
8691 /* Buffer Manager Control Registers. */
8692 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
8693 0x00000000, 0x007fff80 },
8694 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
8695 0x00000000, 0x007fffff },
8696 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
8697 0x00000000, 0x0000003f },
8698 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
8699 0x00000000, 0x000001ff },
8700 { BUFMGR_MB_HIGH_WATER, 0x0000,
8701 0x00000000, 0x000001ff },
8702 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
8703 0xffffffff, 0x00000000 },
8704 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
8705 0xffffffff, 0x00000000 },
8706
8707 /* Mailbox Registers */
8708 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
8709 0x00000000, 0x000001ff },
8710 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
8711 0x00000000, 0x000001ff },
8712 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
8713 0x00000000, 0x000007ff },
8714 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
8715 0x00000000, 0x000001ff },
8716
8717 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
8718 };
8719
8720 is_5705 = is_5750 = 0;
8721 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8722 is_5705 = 1;
8723 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8724 is_5750 = 1;
8725 }
8726
8727 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
8728 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
8729 continue;
8730
8731 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
8732 continue;
8733
8734 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8735 (reg_tbl[i].flags & TG3_FL_NOT_5788))
8736 continue;
8737
8738 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
8739 continue;
8740
8741 offset = (u32) reg_tbl[i].offset;
8742 read_mask = reg_tbl[i].read_mask;
8743 write_mask = reg_tbl[i].write_mask;
8744
8745 /* Save the original register content */
8746 save_val = tr32(offset);
8747
8748 /* Determine the read-only value. */
8749 read_val = save_val & read_mask;
8750
8751 /* Write zero to the register, then make sure the read-only bits
8752 * are not changed and the read/write bits are all zeros.
8753 */
8754 tw32(offset, 0);
8755
8756 val = tr32(offset);
8757
8758 /* Test the read-only and read/write bits. */
8759 if (((val & read_mask) != read_val) || (val & write_mask))
8760 goto out;
8761
8762 /* Write ones to all the bits defined by RdMask and WrMask, then
8763 * make sure the read-only bits are not changed and the
8764 * read/write bits are all ones.
8765 */
8766 tw32(offset, read_mask | write_mask);
8767
8768 val = tr32(offset);
8769
8770 /* Test the read-only bits. */
8771 if ((val & read_mask) != read_val)
8772 goto out;
8773
8774 /* Test the read/write bits. */
8775 if ((val & write_mask) != write_mask)
8776 goto out;
8777
8778 tw32(offset, save_val);
8779 }
8780
8781 return 0;
8782
8783 out:
8784 if (netif_msg_hw(tp))
8785 printk(KERN_ERR PFX "Register test failed at offset %x\n",
8786 offset);
8787 tw32(offset, save_val);
8788 return -EIO;
8789 }
8790
8791 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
8792 {
8793 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
8794 int i;
8795 u32 j;
8796
8797 for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
8798 for (j = 0; j < len; j += 4) {
8799 u32 val;
8800
8801 tg3_write_mem(tp, offset + j, test_pattern[i]);
8802 tg3_read_mem(tp, offset + j, &val);
8803 if (val != test_pattern[i])
8804 return -EIO;
8805 }
8806 }
8807 return 0;
8808 }
8809
8810 static int tg3_test_memory(struct tg3 *tp)
8811 {
8812 static struct mem_entry {
8813 u32 offset;
8814 u32 len;
8815 } mem_tbl_570x[] = {
8816 { 0x00000000, 0x00b50},
8817 { 0x00002000, 0x1c000},
8818 { 0xffffffff, 0x00000}
8819 }, mem_tbl_5705[] = {
8820 { 0x00000100, 0x0000c},
8821 { 0x00000200, 0x00008},
8822 { 0x00004000, 0x00800},
8823 { 0x00006000, 0x01000},
8824 { 0x00008000, 0x02000},
8825 { 0x00010000, 0x0e000},
8826 { 0xffffffff, 0x00000}
8827 }, mem_tbl_5755[] = {
8828 { 0x00000200, 0x00008},
8829 { 0x00004000, 0x00800},
8830 { 0x00006000, 0x00800},
8831 { 0x00008000, 0x02000},
8832 { 0x00010000, 0x0c000},
8833 { 0xffffffff, 0x00000}
8834 }, mem_tbl_5906[] = {
8835 { 0x00000200, 0x00008},
8836 { 0x00004000, 0x00400},
8837 { 0x00006000, 0x00400},
8838 { 0x00008000, 0x01000},
8839 { 0x00010000, 0x01000},
8840 { 0xffffffff, 0x00000}
8841 };
8842 struct mem_entry *mem_tbl;
8843 int err = 0;
8844 int i;
8845
8846 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8847 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8848 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8849 mem_tbl = mem_tbl_5755;
8850 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8851 mem_tbl = mem_tbl_5906;
8852 else
8853 mem_tbl = mem_tbl_5705;
8854 } else
8855 mem_tbl = mem_tbl_570x;
8856
8857 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
8858 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
8859 mem_tbl[i].len)) != 0)
8860 break;
8861 }
8862
8863 return err;
8864 }
8865
8866 #define TG3_MAC_LOOPBACK 0
8867 #define TG3_PHY_LOOPBACK 1
8868
8869 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
8870 {
8871 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
8872 u32 desc_idx;
8873 struct sk_buff *skb, *rx_skb;
8874 u8 *tx_data;
8875 dma_addr_t map;
8876 int num_pkts, tx_len, rx_len, i, err;
8877 struct tg3_rx_buffer_desc *desc;
8878
8879 if (loopback_mode == TG3_MAC_LOOPBACK) {
8880 /* HW errata - mac loopback fails in some cases on 5780.
8881 * Normal traffic and PHY loopback are not affected by
8882 * errata.
8883 */
8884 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8885 return 0;
8886
8887 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8888 MAC_MODE_PORT_INT_LPBACK;
8889 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8890 mac_mode |= MAC_MODE_LINK_POLARITY;
8891 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8892 mac_mode |= MAC_MODE_PORT_MODE_MII;
8893 else
8894 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8895 tw32(MAC_MODE, mac_mode);
8896 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
8897 u32 val;
8898
8899 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8900 u32 phytest;
8901
8902 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
8903 u32 phy;
8904
8905 tg3_writephy(tp, MII_TG3_EPHY_TEST,
8906 phytest | MII_TG3_EPHY_SHADOW_EN);
8907 if (!tg3_readphy(tp, 0x1b, &phy))
8908 tg3_writephy(tp, 0x1b, phy & ~0x20);
8909 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
8910 }
8911 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
8912 } else
8913 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
8914
8915 tg3_phy_toggle_automdix(tp, 0);
8916
8917 tg3_writephy(tp, MII_BMCR, val);
8918 udelay(40);
8919
8920 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
8921 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8922 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
8923 mac_mode |= MAC_MODE_PORT_MODE_MII;
8924 } else
8925 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8926
8927 /* reset to prevent losing 1st rx packet intermittently */
8928 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8929 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8930 udelay(10);
8931 tw32_f(MAC_RX_MODE, tp->rx_mode);
8932 }
8933 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
8934 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
8935 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8936 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
8937 mac_mode |= MAC_MODE_LINK_POLARITY;
8938 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8939 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8940 }
8941 tw32(MAC_MODE, mac_mode);
8942 }
8943 else
8944 return -EINVAL;
8945
8946 err = -EIO;
8947
8948 tx_len = 1514;
8949 skb = netdev_alloc_skb(tp->dev, tx_len);
8950 if (!skb)
8951 return -ENOMEM;
8952
8953 tx_data = skb_put(skb, tx_len);
8954 memcpy(tx_data, tp->dev->dev_addr, 6);
8955 memset(tx_data + 6, 0x0, 8);
8956
8957 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
8958
8959 for (i = 14; i < tx_len; i++)
8960 tx_data[i] = (u8) (i & 0xff);
8961
8962 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
8963
8964 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8965 HOSTCC_MODE_NOW);
8966
8967 udelay(10);
8968
8969 rx_start_idx = tp->hw_status->idx[0].rx_producer;
8970
8971 num_pkts = 0;
8972
8973 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
8974
8975 tp->tx_prod++;
8976 num_pkts++;
8977
8978 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
8979 tp->tx_prod);
8980 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
8981
8982 udelay(10);
8983
8984 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
8985 for (i = 0; i < 25; i++) {
8986 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8987 HOSTCC_MODE_NOW);
8988
8989 udelay(10);
8990
8991 tx_idx = tp->hw_status->idx[0].tx_consumer;
8992 rx_idx = tp->hw_status->idx[0].rx_producer;
8993 if ((tx_idx == tp->tx_prod) &&
8994 (rx_idx == (rx_start_idx + num_pkts)))
8995 break;
8996 }
8997
8998 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
8999 dev_kfree_skb(skb);
9000
9001 if (tx_idx != tp->tx_prod)
9002 goto out;
9003
9004 if (rx_idx != rx_start_idx + num_pkts)
9005 goto out;
9006
9007 desc = &tp->rx_rcb[rx_start_idx];
9008 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
9009 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
9010 if (opaque_key != RXD_OPAQUE_RING_STD)
9011 goto out;
9012
9013 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
9014 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
9015 goto out;
9016
9017 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
9018 if (rx_len != tx_len)
9019 goto out;
9020
9021 rx_skb = tp->rx_std_buffers[desc_idx].skb;
9022
9023 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
9024 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
9025
9026 for (i = 14; i < tx_len; i++) {
9027 if (*(rx_skb->data + i) != (u8) (i & 0xff))
9028 goto out;
9029 }
9030 err = 0;
9031
9032 /* tg3_free_rings will unmap and free the rx_skb */
9033 out:
9034 return err;
9035 }
9036
9037 #define TG3_MAC_LOOPBACK_FAILED 1
9038 #define TG3_PHY_LOOPBACK_FAILED 2
9039 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
9040 TG3_PHY_LOOPBACK_FAILED)
9041
9042 static int tg3_test_loopback(struct tg3 *tp)
9043 {
9044 int err = 0;
9045
9046 if (!netif_running(tp->dev))
9047 return TG3_LOOPBACK_FAILED;
9048
9049 err = tg3_reset_hw(tp, 1);
9050 if (err)
9051 return TG3_LOOPBACK_FAILED;
9052
9053 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
9054 err |= TG3_MAC_LOOPBACK_FAILED;
9055 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
9056 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
9057 err |= TG3_PHY_LOOPBACK_FAILED;
9058 }
9059
9060 return err;
9061 }
9062
9063 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
9064 u64 *data)
9065 {
9066 struct tg3 *tp = netdev_priv(dev);
9067
9068 if (tp->link_config.phy_is_low_power)
9069 tg3_set_power_state(tp, PCI_D0);
9070
9071 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
9072
9073 if (tg3_test_nvram(tp) != 0) {
9074 etest->flags |= ETH_TEST_FL_FAILED;
9075 data[0] = 1;
9076 }
9077 if (tg3_test_link(tp) != 0) {
9078 etest->flags |= ETH_TEST_FL_FAILED;
9079 data[1] = 1;
9080 }
9081 if (etest->flags & ETH_TEST_FL_OFFLINE) {
9082 int err, irq_sync = 0;
9083
9084 if (netif_running(dev)) {
9085 tg3_netif_stop(tp);
9086 irq_sync = 1;
9087 }
9088
9089 tg3_full_lock(tp, irq_sync);
9090
9091 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
9092 err = tg3_nvram_lock(tp);
9093 tg3_halt_cpu(tp, RX_CPU_BASE);
9094 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9095 tg3_halt_cpu(tp, TX_CPU_BASE);
9096 if (!err)
9097 tg3_nvram_unlock(tp);
9098
9099 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
9100 tg3_phy_reset(tp);
9101
9102 if (tg3_test_registers(tp) != 0) {
9103 etest->flags |= ETH_TEST_FL_FAILED;
9104 data[2] = 1;
9105 }
9106 if (tg3_test_memory(tp) != 0) {
9107 etest->flags |= ETH_TEST_FL_FAILED;
9108 data[3] = 1;
9109 }
9110 if ((data[4] = tg3_test_loopback(tp)) != 0)
9111 etest->flags |= ETH_TEST_FL_FAILED;
9112
9113 tg3_full_unlock(tp);
9114
9115 if (tg3_test_interrupt(tp) != 0) {
9116 etest->flags |= ETH_TEST_FL_FAILED;
9117 data[5] = 1;
9118 }
9119
9120 tg3_full_lock(tp, 0);
9121
9122 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9123 if (netif_running(dev)) {
9124 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9125 if (!tg3_restart_hw(tp, 1))
9126 tg3_netif_start(tp);
9127 }
9128
9129 tg3_full_unlock(tp);
9130 }
9131 if (tp->link_config.phy_is_low_power)
9132 tg3_set_power_state(tp, PCI_D3hot);
9133
9134 }
9135
9136 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9137 {
9138 struct mii_ioctl_data *data = if_mii(ifr);
9139 struct tg3 *tp = netdev_priv(dev);
9140 int err;
9141
9142 switch(cmd) {
9143 case SIOCGMIIPHY:
9144 data->phy_id = PHY_ADDR;
9145
9146 /* fallthru */
9147 case SIOCGMIIREG: {
9148 u32 mii_regval;
9149
9150 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9151 break; /* We have no PHY */
9152
9153 if (tp->link_config.phy_is_low_power)
9154 return -EAGAIN;
9155
9156 spin_lock_bh(&tp->lock);
9157 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
9158 spin_unlock_bh(&tp->lock);
9159
9160 data->val_out = mii_regval;
9161
9162 return err;
9163 }
9164
9165 case SIOCSMIIREG:
9166 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9167 break; /* We have no PHY */
9168
9169 if (!capable(CAP_NET_ADMIN))
9170 return -EPERM;
9171
9172 if (tp->link_config.phy_is_low_power)
9173 return -EAGAIN;
9174
9175 spin_lock_bh(&tp->lock);
9176 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
9177 spin_unlock_bh(&tp->lock);
9178
9179 return err;
9180
9181 default:
9182 /* do nothing */
9183 break;
9184 }
9185 return -EOPNOTSUPP;
9186 }
9187
9188 #if TG3_VLAN_TAG_USED
9189 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
9190 {
9191 struct tg3 *tp = netdev_priv(dev);
9192
9193 if (netif_running(dev))
9194 tg3_netif_stop(tp);
9195
9196 tg3_full_lock(tp, 0);
9197
9198 tp->vlgrp = grp;
9199
9200 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
9201 __tg3_set_rx_mode(dev);
9202
9203 if (netif_running(dev))
9204 tg3_netif_start(tp);
9205
9206 tg3_full_unlock(tp);
9207 }
9208 #endif
9209
9210 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9211 {
9212 struct tg3 *tp = netdev_priv(dev);
9213
9214 memcpy(ec, &tp->coal, sizeof(*ec));
9215 return 0;
9216 }
9217
9218 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9219 {
9220 struct tg3 *tp = netdev_priv(dev);
9221 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
9222 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
9223
9224 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
9225 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
9226 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
9227 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
9228 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
9229 }
9230
9231 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
9232 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
9233 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
9234 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
9235 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
9236 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
9237 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
9238 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
9239 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
9240 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
9241 return -EINVAL;
9242
9243 /* No rx interrupts will be generated if both are zero */
9244 if ((ec->rx_coalesce_usecs == 0) &&
9245 (ec->rx_max_coalesced_frames == 0))
9246 return -EINVAL;
9247
9248 /* No tx interrupts will be generated if both are zero */
9249 if ((ec->tx_coalesce_usecs == 0) &&
9250 (ec->tx_max_coalesced_frames == 0))
9251 return -EINVAL;
9252
9253 /* Only copy relevant parameters, ignore all others. */
9254 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
9255 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
9256 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
9257 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
9258 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
9259 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
9260 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
9261 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
9262 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
9263
9264 if (netif_running(dev)) {
9265 tg3_full_lock(tp, 0);
9266 __tg3_set_coalesce(tp, &tp->coal);
9267 tg3_full_unlock(tp);
9268 }
9269 return 0;
9270 }
9271
9272 static const struct ethtool_ops tg3_ethtool_ops = {
9273 .get_settings = tg3_get_settings,
9274 .set_settings = tg3_set_settings,
9275 .get_drvinfo = tg3_get_drvinfo,
9276 .get_regs_len = tg3_get_regs_len,
9277 .get_regs = tg3_get_regs,
9278 .get_wol = tg3_get_wol,
9279 .set_wol = tg3_set_wol,
9280 .get_msglevel = tg3_get_msglevel,
9281 .set_msglevel = tg3_set_msglevel,
9282 .nway_reset = tg3_nway_reset,
9283 .get_link = ethtool_op_get_link,
9284 .get_eeprom_len = tg3_get_eeprom_len,
9285 .get_eeprom = tg3_get_eeprom,
9286 .set_eeprom = tg3_set_eeprom,
9287 .get_ringparam = tg3_get_ringparam,
9288 .set_ringparam = tg3_set_ringparam,
9289 .get_pauseparam = tg3_get_pauseparam,
9290 .set_pauseparam = tg3_set_pauseparam,
9291 .get_rx_csum = tg3_get_rx_csum,
9292 .set_rx_csum = tg3_set_rx_csum,
9293 .set_tx_csum = tg3_set_tx_csum,
9294 .set_sg = ethtool_op_set_sg,
9295 .set_tso = tg3_set_tso,
9296 .self_test = tg3_self_test,
9297 .get_strings = tg3_get_strings,
9298 .phys_id = tg3_phys_id,
9299 .get_ethtool_stats = tg3_get_ethtool_stats,
9300 .get_coalesce = tg3_get_coalesce,
9301 .set_coalesce = tg3_set_coalesce,
9302 .get_sset_count = tg3_get_sset_count,
9303 };
9304
9305 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
9306 {
9307 u32 cursize, val, magic;
9308
9309 tp->nvram_size = EEPROM_CHIP_SIZE;
9310
9311 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
9312 return;
9313
9314 if ((magic != TG3_EEPROM_MAGIC) &&
9315 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
9316 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
9317 return;
9318
9319 /*
9320 * Size the chip by reading offsets at increasing powers of two.
9321 * When we encounter our validation signature, we know the addressing
9322 * has wrapped around, and thus have our chip size.
9323 */
9324 cursize = 0x10;
9325
9326 while (cursize < tp->nvram_size) {
9327 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
9328 return;
9329
9330 if (val == magic)
9331 break;
9332
9333 cursize <<= 1;
9334 }
9335
9336 tp->nvram_size = cursize;
9337 }
9338
9339 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
9340 {
9341 u32 val;
9342
9343 if (tg3_nvram_read_swab(tp, 0, &val) != 0)
9344 return;
9345
9346 /* Selfboot format */
9347 if (val != TG3_EEPROM_MAGIC) {
9348 tg3_get_eeprom_size(tp);
9349 return;
9350 }
9351
9352 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
9353 if (val != 0) {
9354 tp->nvram_size = (val >> 16) * 1024;
9355 return;
9356 }
9357 }
9358 tp->nvram_size = 0x80000;
9359 }
9360
9361 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
9362 {
9363 u32 nvcfg1;
9364
9365 nvcfg1 = tr32(NVRAM_CFG1);
9366 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
9367 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9368 }
9369 else {
9370 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9371 tw32(NVRAM_CFG1, nvcfg1);
9372 }
9373
9374 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
9375 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
9376 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
9377 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
9378 tp->nvram_jedecnum = JEDEC_ATMEL;
9379 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9380 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9381 break;
9382 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
9383 tp->nvram_jedecnum = JEDEC_ATMEL;
9384 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
9385 break;
9386 case FLASH_VENDOR_ATMEL_EEPROM:
9387 tp->nvram_jedecnum = JEDEC_ATMEL;
9388 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9389 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9390 break;
9391 case FLASH_VENDOR_ST:
9392 tp->nvram_jedecnum = JEDEC_ST;
9393 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
9394 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9395 break;
9396 case FLASH_VENDOR_SAIFUN:
9397 tp->nvram_jedecnum = JEDEC_SAIFUN;
9398 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
9399 break;
9400 case FLASH_VENDOR_SST_SMALL:
9401 case FLASH_VENDOR_SST_LARGE:
9402 tp->nvram_jedecnum = JEDEC_SST;
9403 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
9404 break;
9405 }
9406 }
9407 else {
9408 tp->nvram_jedecnum = JEDEC_ATMEL;
9409 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9410 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9411 }
9412 }
9413
9414 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
9415 {
9416 u32 nvcfg1;
9417
9418 nvcfg1 = tr32(NVRAM_CFG1);
9419
9420 /* NVRAM protection for TPM */
9421 if (nvcfg1 & (1 << 27))
9422 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9423
9424 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9425 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
9426 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
9427 tp->nvram_jedecnum = JEDEC_ATMEL;
9428 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9429 break;
9430 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9431 tp->nvram_jedecnum = JEDEC_ATMEL;
9432 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9433 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9434 break;
9435 case FLASH_5752VENDOR_ST_M45PE10:
9436 case FLASH_5752VENDOR_ST_M45PE20:
9437 case FLASH_5752VENDOR_ST_M45PE40:
9438 tp->nvram_jedecnum = JEDEC_ST;
9439 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9440 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9441 break;
9442 }
9443
9444 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
9445 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
9446 case FLASH_5752PAGE_SIZE_256:
9447 tp->nvram_pagesize = 256;
9448 break;
9449 case FLASH_5752PAGE_SIZE_512:
9450 tp->nvram_pagesize = 512;
9451 break;
9452 case FLASH_5752PAGE_SIZE_1K:
9453 tp->nvram_pagesize = 1024;
9454 break;
9455 case FLASH_5752PAGE_SIZE_2K:
9456 tp->nvram_pagesize = 2048;
9457 break;
9458 case FLASH_5752PAGE_SIZE_4K:
9459 tp->nvram_pagesize = 4096;
9460 break;
9461 case FLASH_5752PAGE_SIZE_264:
9462 tp->nvram_pagesize = 264;
9463 break;
9464 }
9465 }
9466 else {
9467 /* For eeprom, set pagesize to maximum eeprom size */
9468 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9469
9470 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9471 tw32(NVRAM_CFG1, nvcfg1);
9472 }
9473 }
9474
9475 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
9476 {
9477 u32 nvcfg1, protect = 0;
9478
9479 nvcfg1 = tr32(NVRAM_CFG1);
9480
9481 /* NVRAM protection for TPM */
9482 if (nvcfg1 & (1 << 27)) {
9483 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9484 protect = 1;
9485 }
9486
9487 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
9488 switch (nvcfg1) {
9489 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9490 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9491 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9492 case FLASH_5755VENDOR_ATMEL_FLASH_5:
9493 tp->nvram_jedecnum = JEDEC_ATMEL;
9494 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9495 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9496 tp->nvram_pagesize = 264;
9497 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
9498 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
9499 tp->nvram_size = (protect ? 0x3e200 : 0x80000);
9500 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
9501 tp->nvram_size = (protect ? 0x1f200 : 0x40000);
9502 else
9503 tp->nvram_size = (protect ? 0x1f200 : 0x20000);
9504 break;
9505 case FLASH_5752VENDOR_ST_M45PE10:
9506 case FLASH_5752VENDOR_ST_M45PE20:
9507 case FLASH_5752VENDOR_ST_M45PE40:
9508 tp->nvram_jedecnum = JEDEC_ST;
9509 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9510 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9511 tp->nvram_pagesize = 256;
9512 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
9513 tp->nvram_size = (protect ? 0x10000 : 0x20000);
9514 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
9515 tp->nvram_size = (protect ? 0x10000 : 0x40000);
9516 else
9517 tp->nvram_size = (protect ? 0x20000 : 0x80000);
9518 break;
9519 }
9520 }
9521
9522 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
9523 {
9524 u32 nvcfg1;
9525
9526 nvcfg1 = tr32(NVRAM_CFG1);
9527
9528 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9529 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
9530 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
9531 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
9532 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
9533 tp->nvram_jedecnum = JEDEC_ATMEL;
9534 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9535 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9536
9537 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9538 tw32(NVRAM_CFG1, nvcfg1);
9539 break;
9540 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9541 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9542 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9543 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9544 tp->nvram_jedecnum = JEDEC_ATMEL;
9545 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9546 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9547 tp->nvram_pagesize = 264;
9548 break;
9549 case FLASH_5752VENDOR_ST_M45PE10:
9550 case FLASH_5752VENDOR_ST_M45PE20:
9551 case FLASH_5752VENDOR_ST_M45PE40:
9552 tp->nvram_jedecnum = JEDEC_ST;
9553 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9554 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9555 tp->nvram_pagesize = 256;
9556 break;
9557 }
9558 }
9559
9560 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
9561 {
9562 tp->nvram_jedecnum = JEDEC_ATMEL;
9563 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9564 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9565 }
9566
9567 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
9568 static void __devinit tg3_nvram_init(struct tg3 *tp)
9569 {
9570 tw32_f(GRC_EEPROM_ADDR,
9571 (EEPROM_ADDR_FSM_RESET |
9572 (EEPROM_DEFAULT_CLOCK_PERIOD <<
9573 EEPROM_ADDR_CLKPERD_SHIFT)));
9574
9575 msleep(1);
9576
9577 /* Enable seeprom accesses. */
9578 tw32_f(GRC_LOCAL_CTRL,
9579 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
9580 udelay(100);
9581
9582 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9583 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
9584 tp->tg3_flags |= TG3_FLAG_NVRAM;
9585
9586 if (tg3_nvram_lock(tp)) {
9587 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
9588 "tg3_nvram_init failed.\n", tp->dev->name);
9589 return;
9590 }
9591 tg3_enable_nvram_access(tp);
9592
9593 tp->nvram_size = 0;
9594
9595 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9596 tg3_get_5752_nvram_info(tp);
9597 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9598 tg3_get_5755_nvram_info(tp);
9599 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9600 tg3_get_5787_nvram_info(tp);
9601 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9602 tg3_get_5906_nvram_info(tp);
9603 else
9604 tg3_get_nvram_info(tp);
9605
9606 if (tp->nvram_size == 0)
9607 tg3_get_nvram_size(tp);
9608
9609 tg3_disable_nvram_access(tp);
9610 tg3_nvram_unlock(tp);
9611
9612 } else {
9613 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
9614
9615 tg3_get_eeprom_size(tp);
9616 }
9617 }
9618
9619 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
9620 u32 offset, u32 *val)
9621 {
9622 u32 tmp;
9623 int i;
9624
9625 if (offset > EEPROM_ADDR_ADDR_MASK ||
9626 (offset % 4) != 0)
9627 return -EINVAL;
9628
9629 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
9630 EEPROM_ADDR_DEVID_MASK |
9631 EEPROM_ADDR_READ);
9632 tw32(GRC_EEPROM_ADDR,
9633 tmp |
9634 (0 << EEPROM_ADDR_DEVID_SHIFT) |
9635 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
9636 EEPROM_ADDR_ADDR_MASK) |
9637 EEPROM_ADDR_READ | EEPROM_ADDR_START);
9638
9639 for (i = 0; i < 1000; i++) {
9640 tmp = tr32(GRC_EEPROM_ADDR);
9641
9642 if (tmp & EEPROM_ADDR_COMPLETE)
9643 break;
9644 msleep(1);
9645 }
9646 if (!(tmp & EEPROM_ADDR_COMPLETE))
9647 return -EBUSY;
9648
9649 *val = tr32(GRC_EEPROM_DATA);
9650 return 0;
9651 }
9652
9653 #define NVRAM_CMD_TIMEOUT 10000
9654
9655 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
9656 {
9657 int i;
9658
9659 tw32(NVRAM_CMD, nvram_cmd);
9660 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
9661 udelay(10);
9662 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
9663 udelay(10);
9664 break;
9665 }
9666 }
9667 if (i == NVRAM_CMD_TIMEOUT) {
9668 return -EBUSY;
9669 }
9670 return 0;
9671 }
9672
9673 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
9674 {
9675 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9676 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9677 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9678 (tp->nvram_jedecnum == JEDEC_ATMEL))
9679
9680 addr = ((addr / tp->nvram_pagesize) <<
9681 ATMEL_AT45DB0X1B_PAGE_POS) +
9682 (addr % tp->nvram_pagesize);
9683
9684 return addr;
9685 }
9686
9687 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
9688 {
9689 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9690 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9691 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9692 (tp->nvram_jedecnum == JEDEC_ATMEL))
9693
9694 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
9695 tp->nvram_pagesize) +
9696 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
9697
9698 return addr;
9699 }
9700
9701 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
9702 {
9703 int ret;
9704
9705 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
9706 return tg3_nvram_read_using_eeprom(tp, offset, val);
9707
9708 offset = tg3_nvram_phys_addr(tp, offset);
9709
9710 if (offset > NVRAM_ADDR_MSK)
9711 return -EINVAL;
9712
9713 ret = tg3_nvram_lock(tp);
9714 if (ret)
9715 return ret;
9716
9717 tg3_enable_nvram_access(tp);
9718
9719 tw32(NVRAM_ADDR, offset);
9720 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
9721 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
9722
9723 if (ret == 0)
9724 *val = swab32(tr32(NVRAM_RDDATA));
9725
9726 tg3_disable_nvram_access(tp);
9727
9728 tg3_nvram_unlock(tp);
9729
9730 return ret;
9731 }
9732
9733 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
9734 {
9735 int err;
9736 u32 tmp;
9737
9738 err = tg3_nvram_read(tp, offset, &tmp);
9739 *val = swab32(tmp);
9740 return err;
9741 }
9742
9743 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
9744 u32 offset, u32 len, u8 *buf)
9745 {
9746 int i, j, rc = 0;
9747 u32 val;
9748
9749 for (i = 0; i < len; i += 4) {
9750 u32 addr, data;
9751
9752 addr = offset + i;
9753
9754 memcpy(&data, buf + i, 4);
9755
9756 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
9757
9758 val = tr32(GRC_EEPROM_ADDR);
9759 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
9760
9761 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
9762 EEPROM_ADDR_READ);
9763 tw32(GRC_EEPROM_ADDR, val |
9764 (0 << EEPROM_ADDR_DEVID_SHIFT) |
9765 (addr & EEPROM_ADDR_ADDR_MASK) |
9766 EEPROM_ADDR_START |
9767 EEPROM_ADDR_WRITE);
9768
9769 for (j = 0; j < 1000; j++) {
9770 val = tr32(GRC_EEPROM_ADDR);
9771
9772 if (val & EEPROM_ADDR_COMPLETE)
9773 break;
9774 msleep(1);
9775 }
9776 if (!(val & EEPROM_ADDR_COMPLETE)) {
9777 rc = -EBUSY;
9778 break;
9779 }
9780 }
9781
9782 return rc;
9783 }
9784
9785 /* offset and length are dword aligned */
9786 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
9787 u8 *buf)
9788 {
9789 int ret = 0;
9790 u32 pagesize = tp->nvram_pagesize;
9791 u32 pagemask = pagesize - 1;
9792 u32 nvram_cmd;
9793 u8 *tmp;
9794
9795 tmp = kmalloc(pagesize, GFP_KERNEL);
9796 if (tmp == NULL)
9797 return -ENOMEM;
9798
9799 while (len) {
9800 int j;
9801 u32 phy_addr, page_off, size;
9802
9803 phy_addr = offset & ~pagemask;
9804
9805 for (j = 0; j < pagesize; j += 4) {
9806 if ((ret = tg3_nvram_read(tp, phy_addr + j,
9807 (u32 *) (tmp + j))))
9808 break;
9809 }
9810 if (ret)
9811 break;
9812
9813 page_off = offset & pagemask;
9814 size = pagesize;
9815 if (len < size)
9816 size = len;
9817
9818 len -= size;
9819
9820 memcpy(tmp + page_off, buf, size);
9821
9822 offset = offset + (pagesize - page_off);
9823
9824 tg3_enable_nvram_access(tp);
9825
9826 /*
9827 * Before we can erase the flash page, we need
9828 * to issue a special "write enable" command.
9829 */
9830 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9831
9832 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9833 break;
9834
9835 /* Erase the target page */
9836 tw32(NVRAM_ADDR, phy_addr);
9837
9838 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
9839 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
9840
9841 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9842 break;
9843
9844 /* Issue another write enable to start the write. */
9845 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9846
9847 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9848 break;
9849
9850 for (j = 0; j < pagesize; j += 4) {
9851 u32 data;
9852
9853 data = *((u32 *) (tmp + j));
9854 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9855
9856 tw32(NVRAM_ADDR, phy_addr + j);
9857
9858 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
9859 NVRAM_CMD_WR;
9860
9861 if (j == 0)
9862 nvram_cmd |= NVRAM_CMD_FIRST;
9863 else if (j == (pagesize - 4))
9864 nvram_cmd |= NVRAM_CMD_LAST;
9865
9866 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9867 break;
9868 }
9869 if (ret)
9870 break;
9871 }
9872
9873 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9874 tg3_nvram_exec_cmd(tp, nvram_cmd);
9875
9876 kfree(tmp);
9877
9878 return ret;
9879 }
9880
9881 /* offset and length are dword aligned */
9882 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
9883 u8 *buf)
9884 {
9885 int i, ret = 0;
9886
9887 for (i = 0; i < len; i += 4, offset += 4) {
9888 u32 data, page_off, phy_addr, nvram_cmd;
9889
9890 memcpy(&data, buf + i, 4);
9891 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9892
9893 page_off = offset % tp->nvram_pagesize;
9894
9895 phy_addr = tg3_nvram_phys_addr(tp, offset);
9896
9897 tw32(NVRAM_ADDR, phy_addr);
9898
9899 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
9900
9901 if ((page_off == 0) || (i == 0))
9902 nvram_cmd |= NVRAM_CMD_FIRST;
9903 if (page_off == (tp->nvram_pagesize - 4))
9904 nvram_cmd |= NVRAM_CMD_LAST;
9905
9906 if (i == (len - 4))
9907 nvram_cmd |= NVRAM_CMD_LAST;
9908
9909 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
9910 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
9911 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
9912 (tp->nvram_jedecnum == JEDEC_ST) &&
9913 (nvram_cmd & NVRAM_CMD_FIRST)) {
9914
9915 if ((ret = tg3_nvram_exec_cmd(tp,
9916 NVRAM_CMD_WREN | NVRAM_CMD_GO |
9917 NVRAM_CMD_DONE)))
9918
9919 break;
9920 }
9921 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9922 /* We always do complete word writes to eeprom. */
9923 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
9924 }
9925
9926 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9927 break;
9928 }
9929 return ret;
9930 }
9931
9932 /* offset and length are dword aligned */
9933 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
9934 {
9935 int ret;
9936
9937 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9938 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
9939 ~GRC_LCLCTRL_GPIO_OUTPUT1);
9940 udelay(40);
9941 }
9942
9943 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
9944 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
9945 }
9946 else {
9947 u32 grc_mode;
9948
9949 ret = tg3_nvram_lock(tp);
9950 if (ret)
9951 return ret;
9952
9953 tg3_enable_nvram_access(tp);
9954 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
9955 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
9956 tw32(NVRAM_WRITE1, 0x406);
9957
9958 grc_mode = tr32(GRC_MODE);
9959 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
9960
9961 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
9962 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9963
9964 ret = tg3_nvram_write_block_buffered(tp, offset, len,
9965 buf);
9966 }
9967 else {
9968 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
9969 buf);
9970 }
9971
9972 grc_mode = tr32(GRC_MODE);
9973 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
9974
9975 tg3_disable_nvram_access(tp);
9976 tg3_nvram_unlock(tp);
9977 }
9978
9979 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9980 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9981 udelay(40);
9982 }
9983
9984 return ret;
9985 }
9986
9987 struct subsys_tbl_ent {
9988 u16 subsys_vendor, subsys_devid;
9989 u32 phy_id;
9990 };
9991
9992 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
9993 /* Broadcom boards. */
9994 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
9995 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
9996 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
9997 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
9998 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
9999 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
10000 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
10001 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
10002 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
10003 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
10004 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
10005
10006 /* 3com boards. */
10007 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
10008 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
10009 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
10010 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
10011 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
10012
10013 /* DELL boards. */
10014 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
10015 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
10016 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
10017 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
10018
10019 /* Compaq boards. */
10020 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
10021 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
10022 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
10023 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
10024 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
10025
10026 /* IBM boards. */
10027 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
10028 };
10029
10030 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
10031 {
10032 int i;
10033
10034 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
10035 if ((subsys_id_to_phy_id[i].subsys_vendor ==
10036 tp->pdev->subsystem_vendor) &&
10037 (subsys_id_to_phy_id[i].subsys_devid ==
10038 tp->pdev->subsystem_device))
10039 return &subsys_id_to_phy_id[i];
10040 }
10041 return NULL;
10042 }
10043
10044 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
10045 {
10046 u32 val;
10047 u16 pmcsr;
10048
10049 /* On some early chips the SRAM cannot be accessed in D3hot state,
10050 * so need make sure we're in D0.
10051 */
10052 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
10053 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
10054 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
10055 msleep(1);
10056
10057 /* Make sure register accesses (indirect or otherwise)
10058 * will function correctly.
10059 */
10060 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10061 tp->misc_host_ctrl);
10062
10063 /* The memory arbiter has to be enabled in order for SRAM accesses
10064 * to succeed. Normally on powerup the tg3 chip firmware will make
10065 * sure it is enabled, but other entities such as system netboot
10066 * code might disable it.
10067 */
10068 val = tr32(MEMARB_MODE);
10069 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
10070
10071 tp->phy_id = PHY_ID_INVALID;
10072 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10073
10074 /* Assume an onboard device and WOL capable by default. */
10075 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
10076
10077 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10078 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
10079 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10080 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10081 }
10082 if (tr32(VCPU_CFGSHDW) & VCPU_CFGSHDW_ASPM_DBNC)
10083 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
10084 return;
10085 }
10086
10087 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
10088 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
10089 u32 nic_cfg, led_cfg;
10090 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
10091 int eeprom_phy_serdes = 0;
10092
10093 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
10094 tp->nic_sram_data_cfg = nic_cfg;
10095
10096 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
10097 ver >>= NIC_SRAM_DATA_VER_SHIFT;
10098 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
10099 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
10100 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
10101 (ver > 0) && (ver < 0x100))
10102 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
10103
10104 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
10105 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
10106 eeprom_phy_serdes = 1;
10107
10108 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
10109 if (nic_phy_id != 0) {
10110 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
10111 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
10112
10113 eeprom_phy_id = (id1 >> 16) << 10;
10114 eeprom_phy_id |= (id2 & 0xfc00) << 16;
10115 eeprom_phy_id |= (id2 & 0x03ff) << 0;
10116 } else
10117 eeprom_phy_id = 0;
10118
10119 tp->phy_id = eeprom_phy_id;
10120 if (eeprom_phy_serdes) {
10121 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
10122 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
10123 else
10124 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10125 }
10126
10127 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10128 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
10129 SHASTA_EXT_LED_MODE_MASK);
10130 else
10131 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
10132
10133 switch (led_cfg) {
10134 default:
10135 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
10136 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10137 break;
10138
10139 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
10140 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10141 break;
10142
10143 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
10144 tp->led_ctrl = LED_CTRL_MODE_MAC;
10145
10146 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
10147 * read on some older 5700/5701 bootcode.
10148 */
10149 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10150 ASIC_REV_5700 ||
10151 GET_ASIC_REV(tp->pci_chip_rev_id) ==
10152 ASIC_REV_5701)
10153 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10154
10155 break;
10156
10157 case SHASTA_EXT_LED_SHARED:
10158 tp->led_ctrl = LED_CTRL_MODE_SHARED;
10159 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
10160 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
10161 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10162 LED_CTRL_MODE_PHY_2);
10163 break;
10164
10165 case SHASTA_EXT_LED_MAC:
10166 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
10167 break;
10168
10169 case SHASTA_EXT_LED_COMBO:
10170 tp->led_ctrl = LED_CTRL_MODE_COMBO;
10171 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
10172 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10173 LED_CTRL_MODE_PHY_2);
10174 break;
10175
10176 };
10177
10178 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10179 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
10180 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
10181 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10182
10183 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
10184 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
10185 if ((tp->pdev->subsystem_vendor ==
10186 PCI_VENDOR_ID_ARIMA) &&
10187 (tp->pdev->subsystem_device == 0x205a ||
10188 tp->pdev->subsystem_device == 0x2063))
10189 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10190 } else {
10191 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10192 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10193 }
10194
10195 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
10196 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
10197 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10198 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
10199 }
10200 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
10201 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
10202 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
10203
10204 if (cfg2 & (1 << 17))
10205 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
10206
10207 /* serdes signal pre-emphasis in register 0x590 set by */
10208 /* bootcode if bit 18 is set */
10209 if (cfg2 & (1 << 18))
10210 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
10211
10212 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10213 u32 cfg3;
10214
10215 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
10216 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
10217 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
10218 }
10219 }
10220 }
10221
10222 static int __devinit tg3_phy_probe(struct tg3 *tp)
10223 {
10224 u32 hw_phy_id_1, hw_phy_id_2;
10225 u32 hw_phy_id, hw_phy_id_masked;
10226 int err;
10227
10228 /* Reading the PHY ID register can conflict with ASF
10229 * firwmare access to the PHY hardware.
10230 */
10231 err = 0;
10232 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
10233 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
10234 } else {
10235 /* Now read the physical PHY_ID from the chip and verify
10236 * that it is sane. If it doesn't look good, we fall back
10237 * to either the hard-coded table based PHY_ID and failing
10238 * that the value found in the eeprom area.
10239 */
10240 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
10241 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
10242
10243 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
10244 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
10245 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
10246
10247 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
10248 }
10249
10250 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
10251 tp->phy_id = hw_phy_id;
10252 if (hw_phy_id_masked == PHY_ID_BCM8002)
10253 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10254 else
10255 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
10256 } else {
10257 if (tp->phy_id != PHY_ID_INVALID) {
10258 /* Do nothing, phy ID already set up in
10259 * tg3_get_eeprom_hw_cfg().
10260 */
10261 } else {
10262 struct subsys_tbl_ent *p;
10263
10264 /* No eeprom signature? Try the hardcoded
10265 * subsys device table.
10266 */
10267 p = lookup_by_subsys(tp);
10268 if (!p)
10269 return -ENODEV;
10270
10271 tp->phy_id = p->phy_id;
10272 if (!tp->phy_id ||
10273 tp->phy_id == PHY_ID_BCM8002)
10274 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10275 }
10276 }
10277
10278 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
10279 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
10280 u32 bmsr, adv_reg, tg3_ctrl, mask;
10281
10282 tg3_readphy(tp, MII_BMSR, &bmsr);
10283 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
10284 (bmsr & BMSR_LSTATUS))
10285 goto skip_phy_reset;
10286
10287 err = tg3_phy_reset(tp);
10288 if (err)
10289 return err;
10290
10291 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
10292 ADVERTISE_100HALF | ADVERTISE_100FULL |
10293 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
10294 tg3_ctrl = 0;
10295 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
10296 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
10297 MII_TG3_CTRL_ADV_1000_FULL);
10298 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10299 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
10300 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
10301 MII_TG3_CTRL_ENABLE_AS_MASTER);
10302 }
10303
10304 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
10305 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
10306 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
10307 if (!tg3_copper_is_advertising_all(tp, mask)) {
10308 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10309
10310 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10311 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10312
10313 tg3_writephy(tp, MII_BMCR,
10314 BMCR_ANENABLE | BMCR_ANRESTART);
10315 }
10316 tg3_phy_set_wirespeed(tp);
10317
10318 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10319 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10320 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10321 }
10322
10323 skip_phy_reset:
10324 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
10325 err = tg3_init_5401phy_dsp(tp);
10326 if (err)
10327 return err;
10328 }
10329
10330 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
10331 err = tg3_init_5401phy_dsp(tp);
10332 }
10333
10334 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10335 tp->link_config.advertising =
10336 (ADVERTISED_1000baseT_Half |
10337 ADVERTISED_1000baseT_Full |
10338 ADVERTISED_Autoneg |
10339 ADVERTISED_FIBRE);
10340 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10341 tp->link_config.advertising &=
10342 ~(ADVERTISED_1000baseT_Half |
10343 ADVERTISED_1000baseT_Full);
10344
10345 return err;
10346 }
10347
10348 static void __devinit tg3_read_partno(struct tg3 *tp)
10349 {
10350 unsigned char vpd_data[256];
10351 unsigned int i;
10352 u32 magic;
10353
10354 if (tg3_nvram_read_swab(tp, 0x0, &magic))
10355 goto out_not_found;
10356
10357 if (magic == TG3_EEPROM_MAGIC) {
10358 for (i = 0; i < 256; i += 4) {
10359 u32 tmp;
10360
10361 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
10362 goto out_not_found;
10363
10364 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
10365 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
10366 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
10367 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
10368 }
10369 } else {
10370 int vpd_cap;
10371
10372 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
10373 for (i = 0; i < 256; i += 4) {
10374 u32 tmp, j = 0;
10375 u16 tmp16;
10376
10377 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
10378 i);
10379 while (j++ < 100) {
10380 pci_read_config_word(tp->pdev, vpd_cap +
10381 PCI_VPD_ADDR, &tmp16);
10382 if (tmp16 & 0x8000)
10383 break;
10384 msleep(1);
10385 }
10386 if (!(tmp16 & 0x8000))
10387 goto out_not_found;
10388
10389 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
10390 &tmp);
10391 tmp = cpu_to_le32(tmp);
10392 memcpy(&vpd_data[i], &tmp, 4);
10393 }
10394 }
10395
10396 /* Now parse and find the part number. */
10397 for (i = 0; i < 254; ) {
10398 unsigned char val = vpd_data[i];
10399 unsigned int block_end;
10400
10401 if (val == 0x82 || val == 0x91) {
10402 i = (i + 3 +
10403 (vpd_data[i + 1] +
10404 (vpd_data[i + 2] << 8)));
10405 continue;
10406 }
10407
10408 if (val != 0x90)
10409 goto out_not_found;
10410
10411 block_end = (i + 3 +
10412 (vpd_data[i + 1] +
10413 (vpd_data[i + 2] << 8)));
10414 i += 3;
10415
10416 if (block_end > 256)
10417 goto out_not_found;
10418
10419 while (i < (block_end - 2)) {
10420 if (vpd_data[i + 0] == 'P' &&
10421 vpd_data[i + 1] == 'N') {
10422 int partno_len = vpd_data[i + 2];
10423
10424 i += 3;
10425 if (partno_len > 24 || (partno_len + i) > 256)
10426 goto out_not_found;
10427
10428 memcpy(tp->board_part_number,
10429 &vpd_data[i], partno_len);
10430
10431 /* Success. */
10432 return;
10433 }
10434 i += 3 + vpd_data[i + 2];
10435 }
10436
10437 /* Part number not found. */
10438 goto out_not_found;
10439 }
10440
10441 out_not_found:
10442 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10443 strcpy(tp->board_part_number, "BCM95906");
10444 else
10445 strcpy(tp->board_part_number, "none");
10446 }
10447
10448 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
10449 {
10450 u32 val, offset, start;
10451
10452 if (tg3_nvram_read_swab(tp, 0, &val))
10453 return;
10454
10455 if (val != TG3_EEPROM_MAGIC)
10456 return;
10457
10458 if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
10459 tg3_nvram_read_swab(tp, 0x4, &start))
10460 return;
10461
10462 offset = tg3_nvram_logical_addr(tp, offset);
10463 if (tg3_nvram_read_swab(tp, offset, &val))
10464 return;
10465
10466 if ((val & 0xfc000000) == 0x0c000000) {
10467 u32 ver_offset, addr;
10468 int i;
10469
10470 if (tg3_nvram_read_swab(tp, offset + 4, &val) ||
10471 tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
10472 return;
10473
10474 if (val != 0)
10475 return;
10476
10477 addr = offset + ver_offset - start;
10478 for (i = 0; i < 16; i += 4) {
10479 if (tg3_nvram_read(tp, addr + i, &val))
10480 return;
10481
10482 val = cpu_to_le32(val);
10483 memcpy(tp->fw_ver + i, &val, 4);
10484 }
10485 }
10486 }
10487
10488 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
10489
10490 static int __devinit tg3_get_invariants(struct tg3 *tp)
10491 {
10492 static struct pci_device_id write_reorder_chipsets[] = {
10493 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10494 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
10495 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10496 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
10497 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
10498 PCI_DEVICE_ID_VIA_8385_0) },
10499 { },
10500 };
10501 u32 misc_ctrl_reg;
10502 u32 cacheline_sz_reg;
10503 u32 pci_state_reg, grc_misc_cfg;
10504 u32 val;
10505 u16 pci_cmd;
10506 int err, pcie_cap;
10507
10508 /* Force memory write invalidate off. If we leave it on,
10509 * then on 5700_BX chips we have to enable a workaround.
10510 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
10511 * to match the cacheline size. The Broadcom driver have this
10512 * workaround but turns MWI off all the times so never uses
10513 * it. This seems to suggest that the workaround is insufficient.
10514 */
10515 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10516 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
10517 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10518
10519 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
10520 * has the register indirect write enable bit set before
10521 * we try to access any of the MMIO registers. It is also
10522 * critical that the PCI-X hw workaround situation is decided
10523 * before that as well.
10524 */
10525 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10526 &misc_ctrl_reg);
10527
10528 tp->pci_chip_rev_id = (misc_ctrl_reg >>
10529 MISC_HOST_CTRL_CHIPREV_SHIFT);
10530
10531 /* Wrong chip ID in 5752 A0. This code can be removed later
10532 * as A0 is not in production.
10533 */
10534 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
10535 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
10536
10537 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
10538 * we need to disable memory and use config. cycles
10539 * only to access all registers. The 5702/03 chips
10540 * can mistakenly decode the special cycles from the
10541 * ICH chipsets as memory write cycles, causing corruption
10542 * of register and memory space. Only certain ICH bridges
10543 * will drive special cycles with non-zero data during the
10544 * address phase which can fall within the 5703's address
10545 * range. This is not an ICH bug as the PCI spec allows
10546 * non-zero address during special cycles. However, only
10547 * these ICH bridges are known to drive non-zero addresses
10548 * during special cycles.
10549 *
10550 * Since special cycles do not cross PCI bridges, we only
10551 * enable this workaround if the 5703 is on the secondary
10552 * bus of these ICH bridges.
10553 */
10554 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
10555 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
10556 static struct tg3_dev_id {
10557 u32 vendor;
10558 u32 device;
10559 u32 rev;
10560 } ich_chipsets[] = {
10561 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
10562 PCI_ANY_ID },
10563 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
10564 PCI_ANY_ID },
10565 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
10566 0xa },
10567 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
10568 PCI_ANY_ID },
10569 { },
10570 };
10571 struct tg3_dev_id *pci_id = &ich_chipsets[0];
10572 struct pci_dev *bridge = NULL;
10573
10574 while (pci_id->vendor != 0) {
10575 bridge = pci_get_device(pci_id->vendor, pci_id->device,
10576 bridge);
10577 if (!bridge) {
10578 pci_id++;
10579 continue;
10580 }
10581 if (pci_id->rev != PCI_ANY_ID) {
10582 if (bridge->revision > pci_id->rev)
10583 continue;
10584 }
10585 if (bridge->subordinate &&
10586 (bridge->subordinate->number ==
10587 tp->pdev->bus->number)) {
10588
10589 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
10590 pci_dev_put(bridge);
10591 break;
10592 }
10593 }
10594 }
10595
10596 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
10597 * DMA addresses > 40-bit. This bridge may have other additional
10598 * 57xx devices behind it in some 4-port NIC designs for example.
10599 * Any tg3 device found behind the bridge will also need the 40-bit
10600 * DMA workaround.
10601 */
10602 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
10603 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10604 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
10605 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10606 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
10607 }
10608 else {
10609 struct pci_dev *bridge = NULL;
10610
10611 do {
10612 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
10613 PCI_DEVICE_ID_SERVERWORKS_EPB,
10614 bridge);
10615 if (bridge && bridge->subordinate &&
10616 (bridge->subordinate->number <=
10617 tp->pdev->bus->number) &&
10618 (bridge->subordinate->subordinate >=
10619 tp->pdev->bus->number)) {
10620 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10621 pci_dev_put(bridge);
10622 break;
10623 }
10624 } while (bridge);
10625 }
10626
10627 /* Initialize misc host control in PCI block. */
10628 tp->misc_host_ctrl |= (misc_ctrl_reg &
10629 MISC_HOST_CTRL_CHIPREV);
10630 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10631 tp->misc_host_ctrl);
10632
10633 pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10634 &cacheline_sz_reg);
10635
10636 tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
10637 tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
10638 tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
10639 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
10640
10641 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
10642 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
10643 tp->pdev_peer = tg3_find_peer(tp);
10644
10645 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10646 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10647 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10648 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10649 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
10650 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10651 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
10652
10653 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
10654 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
10655 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
10656
10657 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
10658 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
10659 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
10660 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
10661 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
10662 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
10663 tp->pdev_peer == tp->pdev))
10664 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
10665
10666 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10667 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10668 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10669 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
10670 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
10671 } else {
10672 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
10673 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10674 ASIC_REV_5750 &&
10675 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
10676 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
10677 }
10678 }
10679
10680 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
10681 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
10682 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10683 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
10684 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
10685 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10686 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
10687
10688 pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
10689 if (pcie_cap != 0) {
10690 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
10691 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10692 u16 lnkctl;
10693
10694 pci_read_config_word(tp->pdev,
10695 pcie_cap + PCI_EXP_LNKCTL,
10696 &lnkctl);
10697 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
10698 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
10699 }
10700 }
10701
10702 /* If we have an AMD 762 or VIA K8T800 chipset, write
10703 * reordering to the mailbox registers done by the host
10704 * controller can cause major troubles. We read back from
10705 * every mailbox register write to force the writes to be
10706 * posted to the chip in order.
10707 */
10708 if (pci_dev_present(write_reorder_chipsets) &&
10709 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
10710 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
10711
10712 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10713 tp->pci_lat_timer < 64) {
10714 tp->pci_lat_timer = 64;
10715
10716 cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
10717 cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
10718 cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
10719 cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
10720
10721 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10722 cacheline_sz_reg);
10723 }
10724
10725 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
10726 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10727 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
10728 if (!tp->pcix_cap) {
10729 printk(KERN_ERR PFX "Cannot find PCI-X "
10730 "capability, aborting.\n");
10731 return -EIO;
10732 }
10733 }
10734
10735 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10736 &pci_state_reg);
10737
10738 if (tp->pcix_cap && (pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
10739 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
10740
10741 /* If this is a 5700 BX chipset, and we are in PCI-X
10742 * mode, enable register write workaround.
10743 *
10744 * The workaround is to use indirect register accesses
10745 * for all chip writes not to mailbox registers.
10746 */
10747 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
10748 u32 pm_reg;
10749
10750 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10751
10752 /* The chip can have it's power management PCI config
10753 * space registers clobbered due to this bug.
10754 * So explicitly force the chip into D0 here.
10755 */
10756 pci_read_config_dword(tp->pdev,
10757 tp->pm_cap + PCI_PM_CTRL,
10758 &pm_reg);
10759 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
10760 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
10761 pci_write_config_dword(tp->pdev,
10762 tp->pm_cap + PCI_PM_CTRL,
10763 pm_reg);
10764
10765 /* Also, force SERR#/PERR# in PCI command. */
10766 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10767 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
10768 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10769 }
10770 }
10771
10772 /* 5700 BX chips need to have their TX producer index mailboxes
10773 * written twice to workaround a bug.
10774 */
10775 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
10776 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
10777
10778 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
10779 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
10780 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
10781 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
10782
10783 /* Chip-specific fixup from Broadcom driver */
10784 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
10785 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
10786 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
10787 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
10788 }
10789
10790 /* Default fast path register access methods */
10791 tp->read32 = tg3_read32;
10792 tp->write32 = tg3_write32;
10793 tp->read32_mbox = tg3_read32;
10794 tp->write32_mbox = tg3_write32;
10795 tp->write32_tx_mbox = tg3_write32;
10796 tp->write32_rx_mbox = tg3_write32;
10797
10798 /* Various workaround register access methods */
10799 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
10800 tp->write32 = tg3_write_indirect_reg32;
10801 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10802 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
10803 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
10804 /*
10805 * Back to back register writes can cause problems on these
10806 * chips, the workaround is to read back all reg writes
10807 * except those to mailbox regs.
10808 *
10809 * See tg3_write_indirect_reg32().
10810 */
10811 tp->write32 = tg3_write_flush_reg32;
10812 }
10813
10814
10815 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
10816 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
10817 tp->write32_tx_mbox = tg3_write32_tx_mbox;
10818 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
10819 tp->write32_rx_mbox = tg3_write_flush_reg32;
10820 }
10821
10822 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
10823 tp->read32 = tg3_read_indirect_reg32;
10824 tp->write32 = tg3_write_indirect_reg32;
10825 tp->read32_mbox = tg3_read_indirect_mbox;
10826 tp->write32_mbox = tg3_write_indirect_mbox;
10827 tp->write32_tx_mbox = tg3_write_indirect_mbox;
10828 tp->write32_rx_mbox = tg3_write_indirect_mbox;
10829
10830 iounmap(tp->regs);
10831 tp->regs = NULL;
10832
10833 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10834 pci_cmd &= ~PCI_COMMAND_MEMORY;
10835 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10836 }
10837 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10838 tp->read32_mbox = tg3_read32_mbox_5906;
10839 tp->write32_mbox = tg3_write32_mbox_5906;
10840 tp->write32_tx_mbox = tg3_write32_mbox_5906;
10841 tp->write32_rx_mbox = tg3_write32_mbox_5906;
10842 }
10843
10844 if (tp->write32 == tg3_write_indirect_reg32 ||
10845 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10846 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10847 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
10848 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
10849
10850 /* Get eeprom hw config before calling tg3_set_power_state().
10851 * In particular, the TG3_FLG2_IS_NIC flag must be
10852 * determined before calling tg3_set_power_state() so that
10853 * we know whether or not to switch out of Vaux power.
10854 * When the flag is set, it means that GPIO1 is used for eeprom
10855 * write protect and also implies that it is a LOM where GPIOs
10856 * are not used to switch power.
10857 */
10858 tg3_get_eeprom_hw_cfg(tp);
10859
10860 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
10861 * GPIO1 driven high will bring 5700's external PHY out of reset.
10862 * It is also used as eeprom write protect on LOMs.
10863 */
10864 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
10865 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10866 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
10867 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10868 GRC_LCLCTRL_GPIO_OUTPUT1);
10869 /* Unused GPIO3 must be driven as output on 5752 because there
10870 * are no pull-up resistors on unused GPIO pins.
10871 */
10872 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10873 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
10874
10875 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10876 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
10877
10878 /* Force the chip into D0. */
10879 err = tg3_set_power_state(tp, PCI_D0);
10880 if (err) {
10881 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
10882 pci_name(tp->pdev));
10883 return err;
10884 }
10885
10886 /* 5700 B0 chips do not support checksumming correctly due
10887 * to hardware bugs.
10888 */
10889 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
10890 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
10891
10892 /* Derive initial jumbo mode from MTU assigned in
10893 * ether_setup() via the alloc_etherdev() call
10894 */
10895 if (tp->dev->mtu > ETH_DATA_LEN &&
10896 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10897 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
10898
10899 /* Determine WakeOnLan speed to use. */
10900 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10901 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10902 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
10903 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
10904 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
10905 } else {
10906 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
10907 }
10908
10909 /* A few boards don't want Ethernet@WireSpeed phy feature */
10910 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10911 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
10912 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
10913 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
10914 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
10915 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
10916 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
10917
10918 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
10919 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
10920 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
10921 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
10922 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
10923
10924 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10925 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10926 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
10927 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
10928 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
10929 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
10930 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
10931 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
10932 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10933 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
10934 }
10935
10936 tp->coalesce_mode = 0;
10937 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
10938 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
10939 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
10940
10941 /* Initialize MAC MI mode, polling disabled. */
10942 tw32_f(MAC_MI_MODE, tp->mi_mode);
10943 udelay(80);
10944
10945 /* Initialize data/descriptor byte/word swapping. */
10946 val = tr32(GRC_MODE);
10947 val &= GRC_MODE_HOST_STACKUP;
10948 tw32(GRC_MODE, val | tp->grc_mode);
10949
10950 tg3_switch_clocks(tp);
10951
10952 /* Clear this out for sanity. */
10953 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10954
10955 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10956 &pci_state_reg);
10957 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
10958 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
10959 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
10960
10961 if (chiprevid == CHIPREV_ID_5701_A0 ||
10962 chiprevid == CHIPREV_ID_5701_B0 ||
10963 chiprevid == CHIPREV_ID_5701_B2 ||
10964 chiprevid == CHIPREV_ID_5701_B5) {
10965 void __iomem *sram_base;
10966
10967 /* Write some dummy words into the SRAM status block
10968 * area, see if it reads back correctly. If the return
10969 * value is bad, force enable the PCIX workaround.
10970 */
10971 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
10972
10973 writel(0x00000000, sram_base);
10974 writel(0x00000000, sram_base + 4);
10975 writel(0xffffffff, sram_base + 4);
10976 if (readl(sram_base) != 0x00000000)
10977 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10978 }
10979 }
10980
10981 udelay(50);
10982 tg3_nvram_init(tp);
10983
10984 grc_misc_cfg = tr32(GRC_MISC_CFG);
10985 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
10986
10987 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10988 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
10989 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
10990 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
10991
10992 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10993 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
10994 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
10995 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
10996 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
10997 HOSTCC_MODE_CLRTICK_TXBD);
10998
10999 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
11000 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11001 tp->misc_host_ctrl);
11002 }
11003
11004 /* these are limited to 10/100 only */
11005 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
11006 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
11007 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
11008 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
11009 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
11010 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
11011 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
11012 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
11013 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
11014 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
11015 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
11016 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11017 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
11018
11019 err = tg3_phy_probe(tp);
11020 if (err) {
11021 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
11022 pci_name(tp->pdev), err);
11023 /* ... but do not return immediately ... */
11024 }
11025
11026 tg3_read_partno(tp);
11027 tg3_read_fw_ver(tp);
11028
11029 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
11030 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
11031 } else {
11032 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
11033 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
11034 else
11035 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
11036 }
11037
11038 /* 5700 {AX,BX} chips have a broken status block link
11039 * change bit implementation, so we must use the
11040 * status register in those cases.
11041 */
11042 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
11043 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
11044 else
11045 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
11046
11047 /* The led_ctrl is set during tg3_phy_probe, here we might
11048 * have to force the link status polling mechanism based
11049 * upon subsystem IDs.
11050 */
11051 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
11052 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
11053 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
11054 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
11055 TG3_FLAG_USE_LINKCHG_REG);
11056 }
11057
11058 /* For all SERDES we poll the MAC status register. */
11059 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11060 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
11061 else
11062 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
11063
11064 /* All chips before 5787 can get confused if TX buffers
11065 * straddle the 4GB address boundary in some cases.
11066 */
11067 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11068 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11069 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11070 tp->dev->hard_start_xmit = tg3_start_xmit;
11071 else
11072 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
11073
11074 tp->rx_offset = 2;
11075 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
11076 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
11077 tp->rx_offset = 0;
11078
11079 tp->rx_std_max_post = TG3_RX_RING_SIZE;
11080
11081 /* Increment the rx prod index on the rx std ring by at most
11082 * 8 for these chips to workaround hw errata.
11083 */
11084 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
11085 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
11086 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11087 tp->rx_std_max_post = 8;
11088
11089 /* By default, disable wake-on-lan. User can change this
11090 * using ETHTOOL_SWOL.
11091 */
11092 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
11093
11094 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
11095 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
11096 PCIE_PWR_MGMT_L1_THRESH_MSK;
11097
11098 return err;
11099 }
11100
11101 #ifdef CONFIG_SPARC
11102 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
11103 {
11104 struct net_device *dev = tp->dev;
11105 struct pci_dev *pdev = tp->pdev;
11106 struct device_node *dp = pci_device_to_OF_node(pdev);
11107 const unsigned char *addr;
11108 int len;
11109
11110 addr = of_get_property(dp, "local-mac-address", &len);
11111 if (addr && len == 6) {
11112 memcpy(dev->dev_addr, addr, 6);
11113 memcpy(dev->perm_addr, dev->dev_addr, 6);
11114 return 0;
11115 }
11116 return -ENODEV;
11117 }
11118
11119 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
11120 {
11121 struct net_device *dev = tp->dev;
11122
11123 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
11124 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
11125 return 0;
11126 }
11127 #endif
11128
11129 static int __devinit tg3_get_device_address(struct tg3 *tp)
11130 {
11131 struct net_device *dev = tp->dev;
11132 u32 hi, lo, mac_offset;
11133 int addr_ok = 0;
11134
11135 #ifdef CONFIG_SPARC
11136 if (!tg3_get_macaddr_sparc(tp))
11137 return 0;
11138 #endif
11139
11140 mac_offset = 0x7c;
11141 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11142 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11143 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
11144 mac_offset = 0xcc;
11145 if (tg3_nvram_lock(tp))
11146 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
11147 else
11148 tg3_nvram_unlock(tp);
11149 }
11150 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11151 mac_offset = 0x10;
11152
11153 /* First try to get it from MAC address mailbox. */
11154 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
11155 if ((hi >> 16) == 0x484b) {
11156 dev->dev_addr[0] = (hi >> 8) & 0xff;
11157 dev->dev_addr[1] = (hi >> 0) & 0xff;
11158
11159 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
11160 dev->dev_addr[2] = (lo >> 24) & 0xff;
11161 dev->dev_addr[3] = (lo >> 16) & 0xff;
11162 dev->dev_addr[4] = (lo >> 8) & 0xff;
11163 dev->dev_addr[5] = (lo >> 0) & 0xff;
11164
11165 /* Some old bootcode may report a 0 MAC address in SRAM */
11166 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
11167 }
11168 if (!addr_ok) {
11169 /* Next, try NVRAM. */
11170 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
11171 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
11172 dev->dev_addr[0] = ((hi >> 16) & 0xff);
11173 dev->dev_addr[1] = ((hi >> 24) & 0xff);
11174 dev->dev_addr[2] = ((lo >> 0) & 0xff);
11175 dev->dev_addr[3] = ((lo >> 8) & 0xff);
11176 dev->dev_addr[4] = ((lo >> 16) & 0xff);
11177 dev->dev_addr[5] = ((lo >> 24) & 0xff);
11178 }
11179 /* Finally just fetch it out of the MAC control regs. */
11180 else {
11181 hi = tr32(MAC_ADDR_0_HIGH);
11182 lo = tr32(MAC_ADDR_0_LOW);
11183
11184 dev->dev_addr[5] = lo & 0xff;
11185 dev->dev_addr[4] = (lo >> 8) & 0xff;
11186 dev->dev_addr[3] = (lo >> 16) & 0xff;
11187 dev->dev_addr[2] = (lo >> 24) & 0xff;
11188 dev->dev_addr[1] = hi & 0xff;
11189 dev->dev_addr[0] = (hi >> 8) & 0xff;
11190 }
11191 }
11192
11193 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
11194 #ifdef CONFIG_SPARC64
11195 if (!tg3_get_default_macaddr_sparc(tp))
11196 return 0;
11197 #endif
11198 return -EINVAL;
11199 }
11200 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
11201 return 0;
11202 }
11203
11204 #define BOUNDARY_SINGLE_CACHELINE 1
11205 #define BOUNDARY_MULTI_CACHELINE 2
11206
11207 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
11208 {
11209 int cacheline_size;
11210 u8 byte;
11211 int goal;
11212
11213 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
11214 if (byte == 0)
11215 cacheline_size = 1024;
11216 else
11217 cacheline_size = (int) byte * 4;
11218
11219 /* On 5703 and later chips, the boundary bits have no
11220 * effect.
11221 */
11222 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11223 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
11224 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11225 goto out;
11226
11227 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
11228 goal = BOUNDARY_MULTI_CACHELINE;
11229 #else
11230 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
11231 goal = BOUNDARY_SINGLE_CACHELINE;
11232 #else
11233 goal = 0;
11234 #endif
11235 #endif
11236
11237 if (!goal)
11238 goto out;
11239
11240 /* PCI controllers on most RISC systems tend to disconnect
11241 * when a device tries to burst across a cache-line boundary.
11242 * Therefore, letting tg3 do so just wastes PCI bandwidth.
11243 *
11244 * Unfortunately, for PCI-E there are only limited
11245 * write-side controls for this, and thus for reads
11246 * we will still get the disconnects. We'll also waste
11247 * these PCI cycles for both read and write for chips
11248 * other than 5700 and 5701 which do not implement the
11249 * boundary bits.
11250 */
11251 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
11252 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
11253 switch (cacheline_size) {
11254 case 16:
11255 case 32:
11256 case 64:
11257 case 128:
11258 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11259 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
11260 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
11261 } else {
11262 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11263 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11264 }
11265 break;
11266
11267 case 256:
11268 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
11269 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
11270 break;
11271
11272 default:
11273 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11274 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11275 break;
11276 };
11277 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11278 switch (cacheline_size) {
11279 case 16:
11280 case 32:
11281 case 64:
11282 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11283 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11284 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
11285 break;
11286 }
11287 /* fallthrough */
11288 case 128:
11289 default:
11290 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11291 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
11292 break;
11293 };
11294 } else {
11295 switch (cacheline_size) {
11296 case 16:
11297 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11298 val |= (DMA_RWCTRL_READ_BNDRY_16 |
11299 DMA_RWCTRL_WRITE_BNDRY_16);
11300 break;
11301 }
11302 /* fallthrough */
11303 case 32:
11304 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11305 val |= (DMA_RWCTRL_READ_BNDRY_32 |
11306 DMA_RWCTRL_WRITE_BNDRY_32);
11307 break;
11308 }
11309 /* fallthrough */
11310 case 64:
11311 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11312 val |= (DMA_RWCTRL_READ_BNDRY_64 |
11313 DMA_RWCTRL_WRITE_BNDRY_64);
11314 break;
11315 }
11316 /* fallthrough */
11317 case 128:
11318 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11319 val |= (DMA_RWCTRL_READ_BNDRY_128 |
11320 DMA_RWCTRL_WRITE_BNDRY_128);
11321 break;
11322 }
11323 /* fallthrough */
11324 case 256:
11325 val |= (DMA_RWCTRL_READ_BNDRY_256 |
11326 DMA_RWCTRL_WRITE_BNDRY_256);
11327 break;
11328 case 512:
11329 val |= (DMA_RWCTRL_READ_BNDRY_512 |
11330 DMA_RWCTRL_WRITE_BNDRY_512);
11331 break;
11332 case 1024:
11333 default:
11334 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
11335 DMA_RWCTRL_WRITE_BNDRY_1024);
11336 break;
11337 };
11338 }
11339
11340 out:
11341 return val;
11342 }
11343
11344 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
11345 {
11346 struct tg3_internal_buffer_desc test_desc;
11347 u32 sram_dma_descs;
11348 int i, ret;
11349
11350 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
11351
11352 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
11353 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
11354 tw32(RDMAC_STATUS, 0);
11355 tw32(WDMAC_STATUS, 0);
11356
11357 tw32(BUFMGR_MODE, 0);
11358 tw32(FTQ_RESET, 0);
11359
11360 test_desc.addr_hi = ((u64) buf_dma) >> 32;
11361 test_desc.addr_lo = buf_dma & 0xffffffff;
11362 test_desc.nic_mbuf = 0x00002100;
11363 test_desc.len = size;
11364
11365 /*
11366 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
11367 * the *second* time the tg3 driver was getting loaded after an
11368 * initial scan.
11369 *
11370 * Broadcom tells me:
11371 * ...the DMA engine is connected to the GRC block and a DMA
11372 * reset may affect the GRC block in some unpredictable way...
11373 * The behavior of resets to individual blocks has not been tested.
11374 *
11375 * Broadcom noted the GRC reset will also reset all sub-components.
11376 */
11377 if (to_device) {
11378 test_desc.cqid_sqid = (13 << 8) | 2;
11379
11380 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
11381 udelay(40);
11382 } else {
11383 test_desc.cqid_sqid = (16 << 8) | 7;
11384
11385 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
11386 udelay(40);
11387 }
11388 test_desc.flags = 0x00000005;
11389
11390 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
11391 u32 val;
11392
11393 val = *(((u32 *)&test_desc) + i);
11394 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
11395 sram_dma_descs + (i * sizeof(u32)));
11396 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
11397 }
11398 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
11399
11400 if (to_device) {
11401 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
11402 } else {
11403 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
11404 }
11405
11406 ret = -ENODEV;
11407 for (i = 0; i < 40; i++) {
11408 u32 val;
11409
11410 if (to_device)
11411 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
11412 else
11413 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
11414 if ((val & 0xffff) == sram_dma_descs) {
11415 ret = 0;
11416 break;
11417 }
11418
11419 udelay(100);
11420 }
11421
11422 return ret;
11423 }
11424
11425 #define TEST_BUFFER_SIZE 0x2000
11426
11427 static int __devinit tg3_test_dma(struct tg3 *tp)
11428 {
11429 dma_addr_t buf_dma;
11430 u32 *buf, saved_dma_rwctrl;
11431 int ret;
11432
11433 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
11434 if (!buf) {
11435 ret = -ENOMEM;
11436 goto out_nofree;
11437 }
11438
11439 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
11440 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
11441
11442 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
11443
11444 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11445 /* DMA read watermark not used on PCIE */
11446 tp->dma_rwctrl |= 0x00180000;
11447 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
11448 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
11449 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
11450 tp->dma_rwctrl |= 0x003f0000;
11451 else
11452 tp->dma_rwctrl |= 0x003f000f;
11453 } else {
11454 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11455 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
11456 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
11457 u32 read_water = 0x7;
11458
11459 /* If the 5704 is behind the EPB bridge, we can
11460 * do the less restrictive ONE_DMA workaround for
11461 * better performance.
11462 */
11463 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
11464 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11465 tp->dma_rwctrl |= 0x8000;
11466 else if (ccval == 0x6 || ccval == 0x7)
11467 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
11468
11469 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
11470 read_water = 4;
11471 /* Set bit 23 to enable PCIX hw bug fix */
11472 tp->dma_rwctrl |=
11473 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
11474 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
11475 (1 << 23);
11476 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
11477 /* 5780 always in PCIX mode */
11478 tp->dma_rwctrl |= 0x00144000;
11479 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11480 /* 5714 always in PCIX mode */
11481 tp->dma_rwctrl |= 0x00148000;
11482 } else {
11483 tp->dma_rwctrl |= 0x001b000f;
11484 }
11485 }
11486
11487 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11488 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11489 tp->dma_rwctrl &= 0xfffffff0;
11490
11491 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11492 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
11493 /* Remove this if it causes problems for some boards. */
11494 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
11495
11496 /* On 5700/5701 chips, we need to set this bit.
11497 * Otherwise the chip will issue cacheline transactions
11498 * to streamable DMA memory with not all the byte
11499 * enables turned on. This is an error on several
11500 * RISC PCI controllers, in particular sparc64.
11501 *
11502 * On 5703/5704 chips, this bit has been reassigned
11503 * a different meaning. In particular, it is used
11504 * on those chips to enable a PCI-X workaround.
11505 */
11506 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
11507 }
11508
11509 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11510
11511 #if 0
11512 /* Unneeded, already done by tg3_get_invariants. */
11513 tg3_switch_clocks(tp);
11514 #endif
11515
11516 ret = 0;
11517 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11518 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
11519 goto out;
11520
11521 /* It is best to perform DMA test with maximum write burst size
11522 * to expose the 5700/5701 write DMA bug.
11523 */
11524 saved_dma_rwctrl = tp->dma_rwctrl;
11525 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11526 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11527
11528 while (1) {
11529 u32 *p = buf, i;
11530
11531 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
11532 p[i] = i;
11533
11534 /* Send the buffer to the chip. */
11535 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
11536 if (ret) {
11537 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
11538 break;
11539 }
11540
11541 #if 0
11542 /* validate data reached card RAM correctly. */
11543 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11544 u32 val;
11545 tg3_read_mem(tp, 0x2100 + (i*4), &val);
11546 if (le32_to_cpu(val) != p[i]) {
11547 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
11548 /* ret = -ENODEV here? */
11549 }
11550 p[i] = 0;
11551 }
11552 #endif
11553 /* Now read it back. */
11554 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
11555 if (ret) {
11556 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
11557
11558 break;
11559 }
11560
11561 /* Verify it. */
11562 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11563 if (p[i] == i)
11564 continue;
11565
11566 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11567 DMA_RWCTRL_WRITE_BNDRY_16) {
11568 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11569 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11570 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11571 break;
11572 } else {
11573 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
11574 ret = -ENODEV;
11575 goto out;
11576 }
11577 }
11578
11579 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
11580 /* Success. */
11581 ret = 0;
11582 break;
11583 }
11584 }
11585 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11586 DMA_RWCTRL_WRITE_BNDRY_16) {
11587 static struct pci_device_id dma_wait_state_chipsets[] = {
11588 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
11589 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
11590 { },
11591 };
11592
11593 /* DMA test passed without adjusting DMA boundary,
11594 * now look for chipsets that are known to expose the
11595 * DMA bug without failing the test.
11596 */
11597 if (pci_dev_present(dma_wait_state_chipsets)) {
11598 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11599 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11600 }
11601 else
11602 /* Safe to use the calculated DMA boundary. */
11603 tp->dma_rwctrl = saved_dma_rwctrl;
11604
11605 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11606 }
11607
11608 out:
11609 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
11610 out_nofree:
11611 return ret;
11612 }
11613
11614 static void __devinit tg3_init_link_config(struct tg3 *tp)
11615 {
11616 tp->link_config.advertising =
11617 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11618 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11619 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
11620 ADVERTISED_Autoneg | ADVERTISED_MII);
11621 tp->link_config.speed = SPEED_INVALID;
11622 tp->link_config.duplex = DUPLEX_INVALID;
11623 tp->link_config.autoneg = AUTONEG_ENABLE;
11624 tp->link_config.active_speed = SPEED_INVALID;
11625 tp->link_config.active_duplex = DUPLEX_INVALID;
11626 tp->link_config.phy_is_low_power = 0;
11627 tp->link_config.orig_speed = SPEED_INVALID;
11628 tp->link_config.orig_duplex = DUPLEX_INVALID;
11629 tp->link_config.orig_autoneg = AUTONEG_INVALID;
11630 }
11631
11632 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
11633 {
11634 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11635 tp->bufmgr_config.mbuf_read_dma_low_water =
11636 DEFAULT_MB_RDMA_LOW_WATER_5705;
11637 tp->bufmgr_config.mbuf_mac_rx_low_water =
11638 DEFAULT_MB_MACRX_LOW_WATER_5705;
11639 tp->bufmgr_config.mbuf_high_water =
11640 DEFAULT_MB_HIGH_WATER_5705;
11641 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11642 tp->bufmgr_config.mbuf_mac_rx_low_water =
11643 DEFAULT_MB_MACRX_LOW_WATER_5906;
11644 tp->bufmgr_config.mbuf_high_water =
11645 DEFAULT_MB_HIGH_WATER_5906;
11646 }
11647
11648 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11649 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
11650 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11651 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
11652 tp->bufmgr_config.mbuf_high_water_jumbo =
11653 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
11654 } else {
11655 tp->bufmgr_config.mbuf_read_dma_low_water =
11656 DEFAULT_MB_RDMA_LOW_WATER;
11657 tp->bufmgr_config.mbuf_mac_rx_low_water =
11658 DEFAULT_MB_MACRX_LOW_WATER;
11659 tp->bufmgr_config.mbuf_high_water =
11660 DEFAULT_MB_HIGH_WATER;
11661
11662 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11663 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
11664 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11665 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
11666 tp->bufmgr_config.mbuf_high_water_jumbo =
11667 DEFAULT_MB_HIGH_WATER_JUMBO;
11668 }
11669
11670 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
11671 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
11672 }
11673
11674 static char * __devinit tg3_phy_string(struct tg3 *tp)
11675 {
11676 switch (tp->phy_id & PHY_ID_MASK) {
11677 case PHY_ID_BCM5400: return "5400";
11678 case PHY_ID_BCM5401: return "5401";
11679 case PHY_ID_BCM5411: return "5411";
11680 case PHY_ID_BCM5701: return "5701";
11681 case PHY_ID_BCM5703: return "5703";
11682 case PHY_ID_BCM5704: return "5704";
11683 case PHY_ID_BCM5705: return "5705";
11684 case PHY_ID_BCM5750: return "5750";
11685 case PHY_ID_BCM5752: return "5752";
11686 case PHY_ID_BCM5714: return "5714";
11687 case PHY_ID_BCM5780: return "5780";
11688 case PHY_ID_BCM5755: return "5755";
11689 case PHY_ID_BCM5787: return "5787";
11690 case PHY_ID_BCM5756: return "5722/5756";
11691 case PHY_ID_BCM5906: return "5906";
11692 case PHY_ID_BCM8002: return "8002/serdes";
11693 case 0: return "serdes";
11694 default: return "unknown";
11695 };
11696 }
11697
11698 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
11699 {
11700 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11701 strcpy(str, "PCI Express");
11702 return str;
11703 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
11704 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
11705
11706 strcpy(str, "PCIX:");
11707
11708 if ((clock_ctrl == 7) ||
11709 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
11710 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
11711 strcat(str, "133MHz");
11712 else if (clock_ctrl == 0)
11713 strcat(str, "33MHz");
11714 else if (clock_ctrl == 2)
11715 strcat(str, "50MHz");
11716 else if (clock_ctrl == 4)
11717 strcat(str, "66MHz");
11718 else if (clock_ctrl == 6)
11719 strcat(str, "100MHz");
11720 } else {
11721 strcpy(str, "PCI:");
11722 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
11723 strcat(str, "66MHz");
11724 else
11725 strcat(str, "33MHz");
11726 }
11727 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
11728 strcat(str, ":32-bit");
11729 else
11730 strcat(str, ":64-bit");
11731 return str;
11732 }
11733
11734 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
11735 {
11736 struct pci_dev *peer;
11737 unsigned int func, devnr = tp->pdev->devfn & ~7;
11738
11739 for (func = 0; func < 8; func++) {
11740 peer = pci_get_slot(tp->pdev->bus, devnr | func);
11741 if (peer && peer != tp->pdev)
11742 break;
11743 pci_dev_put(peer);
11744 }
11745 /* 5704 can be configured in single-port mode, set peer to
11746 * tp->pdev in that case.
11747 */
11748 if (!peer) {
11749 peer = tp->pdev;
11750 return peer;
11751 }
11752
11753 /*
11754 * We don't need to keep the refcount elevated; there's no way
11755 * to remove one half of this device without removing the other
11756 */
11757 pci_dev_put(peer);
11758
11759 return peer;
11760 }
11761
11762 static void __devinit tg3_init_coal(struct tg3 *tp)
11763 {
11764 struct ethtool_coalesce *ec = &tp->coal;
11765
11766 memset(ec, 0, sizeof(*ec));
11767 ec->cmd = ETHTOOL_GCOALESCE;
11768 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
11769 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
11770 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
11771 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
11772 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
11773 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
11774 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
11775 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
11776 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
11777
11778 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
11779 HOSTCC_MODE_CLRTICK_TXBD)) {
11780 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
11781 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
11782 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
11783 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
11784 }
11785
11786 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11787 ec->rx_coalesce_usecs_irq = 0;
11788 ec->tx_coalesce_usecs_irq = 0;
11789 ec->stats_block_coalesce_usecs = 0;
11790 }
11791 }
11792
11793 static int __devinit tg3_init_one(struct pci_dev *pdev,
11794 const struct pci_device_id *ent)
11795 {
11796 static int tg3_version_printed = 0;
11797 unsigned long tg3reg_base, tg3reg_len;
11798 struct net_device *dev;
11799 struct tg3 *tp;
11800 int i, err, pm_cap;
11801 char str[40];
11802 u64 dma_mask, persist_dma_mask;
11803
11804 if (tg3_version_printed++ == 0)
11805 printk(KERN_INFO "%s", version);
11806
11807 err = pci_enable_device(pdev);
11808 if (err) {
11809 printk(KERN_ERR PFX "Cannot enable PCI device, "
11810 "aborting.\n");
11811 return err;
11812 }
11813
11814 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11815 printk(KERN_ERR PFX "Cannot find proper PCI device "
11816 "base address, aborting.\n");
11817 err = -ENODEV;
11818 goto err_out_disable_pdev;
11819 }
11820
11821 err = pci_request_regions(pdev, DRV_MODULE_NAME);
11822 if (err) {
11823 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
11824 "aborting.\n");
11825 goto err_out_disable_pdev;
11826 }
11827
11828 pci_set_master(pdev);
11829
11830 /* Find power-management capability. */
11831 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11832 if (pm_cap == 0) {
11833 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
11834 "aborting.\n");
11835 err = -EIO;
11836 goto err_out_free_res;
11837 }
11838
11839 tg3reg_base = pci_resource_start(pdev, 0);
11840 tg3reg_len = pci_resource_len(pdev, 0);
11841
11842 dev = alloc_etherdev(sizeof(*tp));
11843 if (!dev) {
11844 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
11845 err = -ENOMEM;
11846 goto err_out_free_res;
11847 }
11848
11849 SET_NETDEV_DEV(dev, &pdev->dev);
11850
11851 #if TG3_VLAN_TAG_USED
11852 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
11853 dev->vlan_rx_register = tg3_vlan_rx_register;
11854 #endif
11855
11856 tp = netdev_priv(dev);
11857 tp->pdev = pdev;
11858 tp->dev = dev;
11859 tp->pm_cap = pm_cap;
11860 tp->mac_mode = TG3_DEF_MAC_MODE;
11861 tp->rx_mode = TG3_DEF_RX_MODE;
11862 tp->tx_mode = TG3_DEF_TX_MODE;
11863 tp->mi_mode = MAC_MI_MODE_BASE;
11864 if (tg3_debug > 0)
11865 tp->msg_enable = tg3_debug;
11866 else
11867 tp->msg_enable = TG3_DEF_MSG_ENABLE;
11868
11869 /* The word/byte swap controls here control register access byte
11870 * swapping. DMA data byte swapping is controlled in the GRC_MODE
11871 * setting below.
11872 */
11873 tp->misc_host_ctrl =
11874 MISC_HOST_CTRL_MASK_PCI_INT |
11875 MISC_HOST_CTRL_WORD_SWAP |
11876 MISC_HOST_CTRL_INDIR_ACCESS |
11877 MISC_HOST_CTRL_PCISTATE_RW;
11878
11879 /* The NONFRM (non-frame) byte/word swap controls take effect
11880 * on descriptor entries, anything which isn't packet data.
11881 *
11882 * The StrongARM chips on the board (one for tx, one for rx)
11883 * are running in big-endian mode.
11884 */
11885 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
11886 GRC_MODE_WSWAP_NONFRM_DATA);
11887 #ifdef __BIG_ENDIAN
11888 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
11889 #endif
11890 spin_lock_init(&tp->lock);
11891 spin_lock_init(&tp->indirect_lock);
11892 INIT_WORK(&tp->reset_task, tg3_reset_task);
11893
11894 tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
11895 if (!tp->regs) {
11896 printk(KERN_ERR PFX "Cannot map device registers, "
11897 "aborting.\n");
11898 err = -ENOMEM;
11899 goto err_out_free_dev;
11900 }
11901
11902 tg3_init_link_config(tp);
11903
11904 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
11905 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
11906 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
11907
11908 dev->open = tg3_open;
11909 dev->stop = tg3_close;
11910 dev->get_stats = tg3_get_stats;
11911 dev->set_multicast_list = tg3_set_rx_mode;
11912 dev->set_mac_address = tg3_set_mac_addr;
11913 dev->do_ioctl = tg3_ioctl;
11914 dev->tx_timeout = tg3_tx_timeout;
11915 netif_napi_add(dev, &tp->napi, tg3_poll, 64);
11916 dev->ethtool_ops = &tg3_ethtool_ops;
11917 dev->watchdog_timeo = TG3_TX_TIMEOUT;
11918 dev->change_mtu = tg3_change_mtu;
11919 dev->irq = pdev->irq;
11920 #ifdef CONFIG_NET_POLL_CONTROLLER
11921 dev->poll_controller = tg3_poll_controller;
11922 #endif
11923
11924 err = tg3_get_invariants(tp);
11925 if (err) {
11926 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
11927 "aborting.\n");
11928 goto err_out_iounmap;
11929 }
11930
11931 /* The EPB bridge inside 5714, 5715, and 5780 and any
11932 * device behind the EPB cannot support DMA addresses > 40-bit.
11933 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
11934 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
11935 * do DMA address check in tg3_start_xmit().
11936 */
11937 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
11938 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
11939 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
11940 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
11941 #ifdef CONFIG_HIGHMEM
11942 dma_mask = DMA_64BIT_MASK;
11943 #endif
11944 } else
11945 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
11946
11947 /* Configure DMA attributes. */
11948 if (dma_mask > DMA_32BIT_MASK) {
11949 err = pci_set_dma_mask(pdev, dma_mask);
11950 if (!err) {
11951 dev->features |= NETIF_F_HIGHDMA;
11952 err = pci_set_consistent_dma_mask(pdev,
11953 persist_dma_mask);
11954 if (err < 0) {
11955 printk(KERN_ERR PFX "Unable to obtain 64 bit "
11956 "DMA for consistent allocations\n");
11957 goto err_out_iounmap;
11958 }
11959 }
11960 }
11961 if (err || dma_mask == DMA_32BIT_MASK) {
11962 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
11963 if (err) {
11964 printk(KERN_ERR PFX "No usable DMA configuration, "
11965 "aborting.\n");
11966 goto err_out_iounmap;
11967 }
11968 }
11969
11970 tg3_init_bufmgr_config(tp);
11971
11972 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11973 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11974 }
11975 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11976 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11977 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
11978 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
11979 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
11980 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
11981 } else {
11982 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
11983 }
11984
11985 /* TSO is on by default on chips that support hardware TSO.
11986 * Firmware TSO on older chips gives lower performance, so it
11987 * is off by default, but can be enabled using ethtool.
11988 */
11989 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11990 dev->features |= NETIF_F_TSO;
11991 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
11992 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
11993 dev->features |= NETIF_F_TSO6;
11994 }
11995
11996
11997 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
11998 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
11999 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
12000 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
12001 tp->rx_pending = 63;
12002 }
12003
12004 err = tg3_get_device_address(tp);
12005 if (err) {
12006 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
12007 "aborting.\n");
12008 goto err_out_iounmap;
12009 }
12010
12011 /*
12012 * Reset chip in case UNDI or EFI driver did not shutdown
12013 * DMA self test will enable WDMAC and we'll see (spurious)
12014 * pending DMA on the PCI bus at that point.
12015 */
12016 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
12017 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
12018 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
12019 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12020 }
12021
12022 err = tg3_test_dma(tp);
12023 if (err) {
12024 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
12025 goto err_out_iounmap;
12026 }
12027
12028 /* Tigon3 can do ipv4 only... and some chips have buggy
12029 * checksumming.
12030 */
12031 if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
12032 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12033 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12034 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
12035 dev->features |= NETIF_F_IPV6_CSUM;
12036
12037 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12038 } else
12039 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
12040
12041 /* flow control autonegotiation is default behavior */
12042 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
12043
12044 tg3_init_coal(tp);
12045
12046 pci_set_drvdata(pdev, dev);
12047
12048 err = register_netdev(dev);
12049 if (err) {
12050 printk(KERN_ERR PFX "Cannot register net device, "
12051 "aborting.\n");
12052 goto err_out_iounmap;
12053 }
12054
12055 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %s Ethernet ",
12056 dev->name,
12057 tp->board_part_number,
12058 tp->pci_chip_rev_id,
12059 tg3_phy_string(tp),
12060 tg3_bus_string(tp, str),
12061 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
12062 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
12063 "10/100/1000Base-T")));
12064
12065 for (i = 0; i < 6; i++)
12066 printk("%2.2x%c", dev->dev_addr[i],
12067 i == 5 ? '\n' : ':');
12068
12069 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
12070 "MIirq[%d] ASF[%d] WireSpeed[%d] TSOcap[%d]\n",
12071 dev->name,
12072 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
12073 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
12074 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
12075 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
12076 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
12077 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
12078 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
12079 dev->name, tp->dma_rwctrl,
12080 (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
12081 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
12082
12083 return 0;
12084
12085 err_out_iounmap:
12086 if (tp->regs) {
12087 iounmap(tp->regs);
12088 tp->regs = NULL;
12089 }
12090
12091 err_out_free_dev:
12092 free_netdev(dev);
12093
12094 err_out_free_res:
12095 pci_release_regions(pdev);
12096
12097 err_out_disable_pdev:
12098 pci_disable_device(pdev);
12099 pci_set_drvdata(pdev, NULL);
12100 return err;
12101 }
12102
12103 static void __devexit tg3_remove_one(struct pci_dev *pdev)
12104 {
12105 struct net_device *dev = pci_get_drvdata(pdev);
12106
12107 if (dev) {
12108 struct tg3 *tp = netdev_priv(dev);
12109
12110 flush_scheduled_work();
12111 unregister_netdev(dev);
12112 if (tp->regs) {
12113 iounmap(tp->regs);
12114 tp->regs = NULL;
12115 }
12116 free_netdev(dev);
12117 pci_release_regions(pdev);
12118 pci_disable_device(pdev);
12119 pci_set_drvdata(pdev, NULL);
12120 }
12121 }
12122
12123 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
12124 {
12125 struct net_device *dev = pci_get_drvdata(pdev);
12126 struct tg3 *tp = netdev_priv(dev);
12127 int err;
12128
12129 /* PCI register 4 needs to be saved whether netif_running() or not.
12130 * MSI address and data need to be saved if using MSI and
12131 * netif_running().
12132 */
12133 pci_save_state(pdev);
12134
12135 if (!netif_running(dev))
12136 return 0;
12137
12138 flush_scheduled_work();
12139 tg3_netif_stop(tp);
12140
12141 del_timer_sync(&tp->timer);
12142
12143 tg3_full_lock(tp, 1);
12144 tg3_disable_ints(tp);
12145 tg3_full_unlock(tp);
12146
12147 netif_device_detach(dev);
12148
12149 tg3_full_lock(tp, 0);
12150 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12151 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
12152 tg3_full_unlock(tp);
12153
12154 err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
12155 if (err) {
12156 tg3_full_lock(tp, 0);
12157
12158 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12159 if (tg3_restart_hw(tp, 1))
12160 goto out;
12161
12162 tp->timer.expires = jiffies + tp->timer_offset;
12163 add_timer(&tp->timer);
12164
12165 netif_device_attach(dev);
12166 tg3_netif_start(tp);
12167
12168 out:
12169 tg3_full_unlock(tp);
12170 }
12171
12172 return err;
12173 }
12174
12175 static int tg3_resume(struct pci_dev *pdev)
12176 {
12177 struct net_device *dev = pci_get_drvdata(pdev);
12178 struct tg3 *tp = netdev_priv(dev);
12179 int err;
12180
12181 pci_restore_state(tp->pdev);
12182
12183 if (!netif_running(dev))
12184 return 0;
12185
12186 err = tg3_set_power_state(tp, PCI_D0);
12187 if (err)
12188 return err;
12189
12190 /* Hardware bug - MSI won't work if INTX disabled. */
12191 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
12192 (tp->tg3_flags2 & TG3_FLG2_USING_MSI))
12193 pci_intx(tp->pdev, 1);
12194
12195 netif_device_attach(dev);
12196
12197 tg3_full_lock(tp, 0);
12198
12199 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12200 err = tg3_restart_hw(tp, 1);
12201 if (err)
12202 goto out;
12203
12204 tp->timer.expires = jiffies + tp->timer_offset;
12205 add_timer(&tp->timer);
12206
12207 tg3_netif_start(tp);
12208
12209 out:
12210 tg3_full_unlock(tp);
12211
12212 return err;
12213 }
12214
12215 static struct pci_driver tg3_driver = {
12216 .name = DRV_MODULE_NAME,
12217 .id_table = tg3_pci_tbl,
12218 .probe = tg3_init_one,
12219 .remove = __devexit_p(tg3_remove_one),
12220 .suspend = tg3_suspend,
12221 .resume = tg3_resume
12222 };
12223
12224 static int __init tg3_init(void)
12225 {
12226 return pci_register_driver(&tg3_driver);
12227 }
12228
12229 static void __exit tg3_cleanup(void)
12230 {
12231 pci_unregister_driver(&tg3_driver);
12232 }
12233
12234 module_init(tg3_init);
12235 module_exit(tg3_cleanup);
Linux kernel - Deliverables
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