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tg3: Add 50610M phy ID for 5785
[deliverable/linux.git] / drivers / net / tg3.c
1 /*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2009 Broadcom Corporation.
8 *
9 * Firmware is:
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
16 */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
26 #include <linux/in.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/phy.h>
36 #include <linux/brcmphy.h>
37 #include <linux/if_vlan.h>
38 #include <linux/ip.h>
39 #include <linux/tcp.h>
40 #include <linux/workqueue.h>
41 #include <linux/prefetch.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/firmware.h>
44
45 #include <net/checksum.h>
46 #include <net/ip.h>
47
48 #include <asm/system.h>
49 #include <asm/io.h>
50 #include <asm/byteorder.h>
51 #include <asm/uaccess.h>
52
53 #ifdef CONFIG_SPARC
54 #include <asm/idprom.h>
55 #include <asm/prom.h>
56 #endif
57
58 #define BAR_0 0
59 #define BAR_2 2
60
61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62 #define TG3_VLAN_TAG_USED 1
63 #else
64 #define TG3_VLAN_TAG_USED 0
65 #endif
66
67 #include "tg3.h"
68
69 #define DRV_MODULE_NAME "tg3"
70 #define PFX DRV_MODULE_NAME ": "
71 #define DRV_MODULE_VERSION "3.102"
72 #define DRV_MODULE_RELDATE "September 1, 2009"
73
74 #define TG3_DEF_MAC_MODE 0
75 #define TG3_DEF_RX_MODE 0
76 #define TG3_DEF_TX_MODE 0
77 #define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87 /* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90 #define TG3_TX_TIMEOUT (5 * HZ)
91
92 /* hardware minimum and maximum for a single frame's data payload */
93 #define TG3_MIN_MTU 60
94 #define TG3_MAX_MTU(tp) \
95 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
96
97 /* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101 #define TG3_RX_RING_SIZE 512
102 #define TG3_DEF_RX_RING_PENDING 200
103 #define TG3_RX_JUMBO_RING_SIZE 256
104 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
105 #define TG3_RSS_INDIR_TBL_SIZE 128
106
107 /* Do not place this n-ring entries value into the tp struct itself,
108 * we really want to expose these constants to GCC so that modulo et
109 * al. operations are done with shifts and masks instead of with
110 * hw multiply/modulo instructions. Another solution would be to
111 * replace things like '% foo' with '& (foo - 1)'.
112 */
113 #define TG3_RX_RCB_RING_SIZE(tp) \
114 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
115 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
116
117 #define TG3_TX_RING_SIZE 512
118 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
119
120 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_RING_SIZE)
122 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
123 TG3_RX_JUMBO_RING_SIZE)
124 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
125 TG3_RX_RCB_RING_SIZE(tp))
126 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
127 TG3_TX_RING_SIZE)
128 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
129
130 #define TG3_DMA_BYTE_ENAB 64
131
132 #define TG3_RX_STD_DMA_SZ 1536
133 #define TG3_RX_JMB_DMA_SZ 9046
134
135 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
136
137 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
138 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
139
140 /* minimum number of free TX descriptors required to wake up TX process */
141 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
142
143 #define TG3_RAW_IP_ALIGN 2
144
145 /* number of ETHTOOL_GSTATS u64's */
146 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
147
148 #define TG3_NUM_TEST 6
149
150 #define FIRMWARE_TG3 "tigon/tg3.bin"
151 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
152 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
153
154 static char version[] __devinitdata =
155 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
156
157 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
158 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
159 MODULE_LICENSE("GPL");
160 MODULE_VERSION(DRV_MODULE_VERSION);
161 MODULE_FIRMWARE(FIRMWARE_TG3);
162 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
163 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
164
165 #define TG3_RSS_MIN_NUM_MSIX_VECS 2
166
167 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
168 module_param(tg3_debug, int, 0);
169 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
170
171 static struct pci_device_id tg3_pci_tbl[] = {
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
238 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
239 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
240 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
241 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
242 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
243 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
244 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
245 {}
246 };
247
248 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
249
250 static const struct {
251 const char string[ETH_GSTRING_LEN];
252 } ethtool_stats_keys[TG3_NUM_STATS] = {
253 { "rx_octets" },
254 { "rx_fragments" },
255 { "rx_ucast_packets" },
256 { "rx_mcast_packets" },
257 { "rx_bcast_packets" },
258 { "rx_fcs_errors" },
259 { "rx_align_errors" },
260 { "rx_xon_pause_rcvd" },
261 { "rx_xoff_pause_rcvd" },
262 { "rx_mac_ctrl_rcvd" },
263 { "rx_xoff_entered" },
264 { "rx_frame_too_long_errors" },
265 { "rx_jabbers" },
266 { "rx_undersize_packets" },
267 { "rx_in_length_errors" },
268 { "rx_out_length_errors" },
269 { "rx_64_or_less_octet_packets" },
270 { "rx_65_to_127_octet_packets" },
271 { "rx_128_to_255_octet_packets" },
272 { "rx_256_to_511_octet_packets" },
273 { "rx_512_to_1023_octet_packets" },
274 { "rx_1024_to_1522_octet_packets" },
275 { "rx_1523_to_2047_octet_packets" },
276 { "rx_2048_to_4095_octet_packets" },
277 { "rx_4096_to_8191_octet_packets" },
278 { "rx_8192_to_9022_octet_packets" },
279
280 { "tx_octets" },
281 { "tx_collisions" },
282
283 { "tx_xon_sent" },
284 { "tx_xoff_sent" },
285 { "tx_flow_control" },
286 { "tx_mac_errors" },
287 { "tx_single_collisions" },
288 { "tx_mult_collisions" },
289 { "tx_deferred" },
290 { "tx_excessive_collisions" },
291 { "tx_late_collisions" },
292 { "tx_collide_2times" },
293 { "tx_collide_3times" },
294 { "tx_collide_4times" },
295 { "tx_collide_5times" },
296 { "tx_collide_6times" },
297 { "tx_collide_7times" },
298 { "tx_collide_8times" },
299 { "tx_collide_9times" },
300 { "tx_collide_10times" },
301 { "tx_collide_11times" },
302 { "tx_collide_12times" },
303 { "tx_collide_13times" },
304 { "tx_collide_14times" },
305 { "tx_collide_15times" },
306 { "tx_ucast_packets" },
307 { "tx_mcast_packets" },
308 { "tx_bcast_packets" },
309 { "tx_carrier_sense_errors" },
310 { "tx_discards" },
311 { "tx_errors" },
312
313 { "dma_writeq_full" },
314 { "dma_write_prioq_full" },
315 { "rxbds_empty" },
316 { "rx_discards" },
317 { "rx_errors" },
318 { "rx_threshold_hit" },
319
320 { "dma_readq_full" },
321 { "dma_read_prioq_full" },
322 { "tx_comp_queue_full" },
323
324 { "ring_set_send_prod_index" },
325 { "ring_status_update" },
326 { "nic_irqs" },
327 { "nic_avoided_irqs" },
328 { "nic_tx_threshold_hit" }
329 };
330
331 static const struct {
332 const char string[ETH_GSTRING_LEN];
333 } ethtool_test_keys[TG3_NUM_TEST] = {
334 { "nvram test (online) " },
335 { "link test (online) " },
336 { "register test (offline)" },
337 { "memory test (offline)" },
338 { "loopback test (offline)" },
339 { "interrupt test (offline)" },
340 };
341
342 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
343 {
344 writel(val, tp->regs + off);
345 }
346
347 static u32 tg3_read32(struct tg3 *tp, u32 off)
348 {
349 return (readl(tp->regs + off));
350 }
351
352 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
353 {
354 writel(val, tp->aperegs + off);
355 }
356
357 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
358 {
359 return (readl(tp->aperegs + off));
360 }
361
362 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
363 {
364 unsigned long flags;
365
366 spin_lock_irqsave(&tp->indirect_lock, flags);
367 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
368 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
369 spin_unlock_irqrestore(&tp->indirect_lock, flags);
370 }
371
372 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
373 {
374 writel(val, tp->regs + off);
375 readl(tp->regs + off);
376 }
377
378 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
379 {
380 unsigned long flags;
381 u32 val;
382
383 spin_lock_irqsave(&tp->indirect_lock, flags);
384 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
385 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
386 spin_unlock_irqrestore(&tp->indirect_lock, flags);
387 return val;
388 }
389
390 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
391 {
392 unsigned long flags;
393
394 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
395 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
396 TG3_64BIT_REG_LOW, val);
397 return;
398 }
399 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
400 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
401 TG3_64BIT_REG_LOW, val);
402 return;
403 }
404
405 spin_lock_irqsave(&tp->indirect_lock, flags);
406 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
407 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
408 spin_unlock_irqrestore(&tp->indirect_lock, flags);
409
410 /* In indirect mode when disabling interrupts, we also need
411 * to clear the interrupt bit in the GRC local ctrl register.
412 */
413 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
414 (val == 0x1)) {
415 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
416 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
417 }
418 }
419
420 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
421 {
422 unsigned long flags;
423 u32 val;
424
425 spin_lock_irqsave(&tp->indirect_lock, flags);
426 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
427 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
428 spin_unlock_irqrestore(&tp->indirect_lock, flags);
429 return val;
430 }
431
432 /* usec_wait specifies the wait time in usec when writing to certain registers
433 * where it is unsafe to read back the register without some delay.
434 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
435 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
436 */
437 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
438 {
439 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
440 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
441 /* Non-posted methods */
442 tp->write32(tp, off, val);
443 else {
444 /* Posted method */
445 tg3_write32(tp, off, val);
446 if (usec_wait)
447 udelay(usec_wait);
448 tp->read32(tp, off);
449 }
450 /* Wait again after the read for the posted method to guarantee that
451 * the wait time is met.
452 */
453 if (usec_wait)
454 udelay(usec_wait);
455 }
456
457 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
458 {
459 tp->write32_mbox(tp, off, val);
460 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
461 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
462 tp->read32_mbox(tp, off);
463 }
464
465 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
466 {
467 void __iomem *mbox = tp->regs + off;
468 writel(val, mbox);
469 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
470 writel(val, mbox);
471 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
472 readl(mbox);
473 }
474
475 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
476 {
477 return (readl(tp->regs + off + GRCMBOX_BASE));
478 }
479
480 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
481 {
482 writel(val, tp->regs + off + GRCMBOX_BASE);
483 }
484
485 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
486 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
487 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
488 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
489 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
490
491 #define tw32(reg,val) tp->write32(tp, reg, val)
492 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
493 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
494 #define tr32(reg) tp->read32(tp, reg)
495
496 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
497 {
498 unsigned long flags;
499
500 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
501 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
502 return;
503
504 spin_lock_irqsave(&tp->indirect_lock, flags);
505 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
506 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
507 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
508
509 /* Always leave this as zero. */
510 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
511 } else {
512 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
513 tw32_f(TG3PCI_MEM_WIN_DATA, val);
514
515 /* Always leave this as zero. */
516 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
517 }
518 spin_unlock_irqrestore(&tp->indirect_lock, flags);
519 }
520
521 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
522 {
523 unsigned long flags;
524
525 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
526 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
527 *val = 0;
528 return;
529 }
530
531 spin_lock_irqsave(&tp->indirect_lock, flags);
532 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
533 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
534 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
535
536 /* Always leave this as zero. */
537 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
538 } else {
539 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
540 *val = tr32(TG3PCI_MEM_WIN_DATA);
541
542 /* Always leave this as zero. */
543 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
544 }
545 spin_unlock_irqrestore(&tp->indirect_lock, flags);
546 }
547
548 static void tg3_ape_lock_init(struct tg3 *tp)
549 {
550 int i;
551
552 /* Make sure the driver hasn't any stale locks. */
553 for (i = 0; i < 8; i++)
554 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
555 APE_LOCK_GRANT_DRIVER);
556 }
557
558 static int tg3_ape_lock(struct tg3 *tp, int locknum)
559 {
560 int i, off;
561 int ret = 0;
562 u32 status;
563
564 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
565 return 0;
566
567 switch (locknum) {
568 case TG3_APE_LOCK_GRC:
569 case TG3_APE_LOCK_MEM:
570 break;
571 default:
572 return -EINVAL;
573 }
574
575 off = 4 * locknum;
576
577 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
578
579 /* Wait for up to 1 millisecond to acquire lock. */
580 for (i = 0; i < 100; i++) {
581 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
582 if (status == APE_LOCK_GRANT_DRIVER)
583 break;
584 udelay(10);
585 }
586
587 if (status != APE_LOCK_GRANT_DRIVER) {
588 /* Revoke the lock request. */
589 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
590 APE_LOCK_GRANT_DRIVER);
591
592 ret = -EBUSY;
593 }
594
595 return ret;
596 }
597
598 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
599 {
600 int off;
601
602 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
603 return;
604
605 switch (locknum) {
606 case TG3_APE_LOCK_GRC:
607 case TG3_APE_LOCK_MEM:
608 break;
609 default:
610 return;
611 }
612
613 off = 4 * locknum;
614 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
615 }
616
617 static void tg3_disable_ints(struct tg3 *tp)
618 {
619 int i;
620
621 tw32(TG3PCI_MISC_HOST_CTRL,
622 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
623 for (i = 0; i < tp->irq_max; i++)
624 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
625 }
626
627 static void tg3_enable_ints(struct tg3 *tp)
628 {
629 int i;
630 u32 coal_now = 0;
631
632 tp->irq_sync = 0;
633 wmb();
634
635 tw32(TG3PCI_MISC_HOST_CTRL,
636 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
637
638 for (i = 0; i < tp->irq_cnt; i++) {
639 struct tg3_napi *tnapi = &tp->napi[i];
640 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
641 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
642 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
643
644 coal_now |= tnapi->coal_now;
645 }
646
647 /* Force an initial interrupt */
648 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
649 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
650 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
651 else
652 tw32(HOSTCC_MODE, tp->coalesce_mode |
653 HOSTCC_MODE_ENABLE | coal_now);
654 }
655
656 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
657 {
658 struct tg3 *tp = tnapi->tp;
659 struct tg3_hw_status *sblk = tnapi->hw_status;
660 unsigned int work_exists = 0;
661
662 /* check for phy events */
663 if (!(tp->tg3_flags &
664 (TG3_FLAG_USE_LINKCHG_REG |
665 TG3_FLAG_POLL_SERDES))) {
666 if (sblk->status & SD_STATUS_LINK_CHG)
667 work_exists = 1;
668 }
669 /* check for RX/TX work to do */
670 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
671 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
672 work_exists = 1;
673
674 return work_exists;
675 }
676
677 /* tg3_int_reenable
678 * similar to tg3_enable_ints, but it accurately determines whether there
679 * is new work pending and can return without flushing the PIO write
680 * which reenables interrupts
681 */
682 static void tg3_int_reenable(struct tg3_napi *tnapi)
683 {
684 struct tg3 *tp = tnapi->tp;
685
686 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
687 mmiowb();
688
689 /* When doing tagged status, this work check is unnecessary.
690 * The last_tag we write above tells the chip which piece of
691 * work we've completed.
692 */
693 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
694 tg3_has_work(tnapi))
695 tw32(HOSTCC_MODE, tp->coalesce_mode |
696 HOSTCC_MODE_ENABLE | tnapi->coal_now);
697 }
698
699 static void tg3_napi_disable(struct tg3 *tp)
700 {
701 int i;
702
703 for (i = tp->irq_cnt - 1; i >= 0; i--)
704 napi_disable(&tp->napi[i].napi);
705 }
706
707 static void tg3_napi_enable(struct tg3 *tp)
708 {
709 int i;
710
711 for (i = 0; i < tp->irq_cnt; i++)
712 napi_enable(&tp->napi[i].napi);
713 }
714
715 static inline void tg3_netif_stop(struct tg3 *tp)
716 {
717 tp->dev->trans_start = jiffies; /* prevent tx timeout */
718 tg3_napi_disable(tp);
719 netif_tx_disable(tp->dev);
720 }
721
722 static inline void tg3_netif_start(struct tg3 *tp)
723 {
724 /* NOTE: unconditional netif_tx_wake_all_queues is only
725 * appropriate so long as all callers are assured to
726 * have free tx slots (such as after tg3_init_hw)
727 */
728 netif_tx_wake_all_queues(tp->dev);
729
730 tg3_napi_enable(tp);
731 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
732 tg3_enable_ints(tp);
733 }
734
735 static void tg3_switch_clocks(struct tg3 *tp)
736 {
737 u32 clock_ctrl;
738 u32 orig_clock_ctrl;
739
740 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
741 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
742 return;
743
744 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
745
746 orig_clock_ctrl = clock_ctrl;
747 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
748 CLOCK_CTRL_CLKRUN_OENABLE |
749 0x1f);
750 tp->pci_clock_ctrl = clock_ctrl;
751
752 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
753 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
754 tw32_wait_f(TG3PCI_CLOCK_CTRL,
755 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
756 }
757 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
758 tw32_wait_f(TG3PCI_CLOCK_CTRL,
759 clock_ctrl |
760 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
761 40);
762 tw32_wait_f(TG3PCI_CLOCK_CTRL,
763 clock_ctrl | (CLOCK_CTRL_ALTCLK),
764 40);
765 }
766 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
767 }
768
769 #define PHY_BUSY_LOOPS 5000
770
771 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
772 {
773 u32 frame_val;
774 unsigned int loops;
775 int ret;
776
777 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
778 tw32_f(MAC_MI_MODE,
779 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
780 udelay(80);
781 }
782
783 *val = 0x0;
784
785 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
786 MI_COM_PHY_ADDR_MASK);
787 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
788 MI_COM_REG_ADDR_MASK);
789 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
790
791 tw32_f(MAC_MI_COM, frame_val);
792
793 loops = PHY_BUSY_LOOPS;
794 while (loops != 0) {
795 udelay(10);
796 frame_val = tr32(MAC_MI_COM);
797
798 if ((frame_val & MI_COM_BUSY) == 0) {
799 udelay(5);
800 frame_val = tr32(MAC_MI_COM);
801 break;
802 }
803 loops -= 1;
804 }
805
806 ret = -EBUSY;
807 if (loops != 0) {
808 *val = frame_val & MI_COM_DATA_MASK;
809 ret = 0;
810 }
811
812 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
813 tw32_f(MAC_MI_MODE, tp->mi_mode);
814 udelay(80);
815 }
816
817 return ret;
818 }
819
820 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
821 {
822 u32 frame_val;
823 unsigned int loops;
824 int ret;
825
826 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
827 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
828 return 0;
829
830 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
831 tw32_f(MAC_MI_MODE,
832 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
833 udelay(80);
834 }
835
836 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
837 MI_COM_PHY_ADDR_MASK);
838 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
839 MI_COM_REG_ADDR_MASK);
840 frame_val |= (val & MI_COM_DATA_MASK);
841 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
842
843 tw32_f(MAC_MI_COM, frame_val);
844
845 loops = PHY_BUSY_LOOPS;
846 while (loops != 0) {
847 udelay(10);
848 frame_val = tr32(MAC_MI_COM);
849 if ((frame_val & MI_COM_BUSY) == 0) {
850 udelay(5);
851 frame_val = tr32(MAC_MI_COM);
852 break;
853 }
854 loops -= 1;
855 }
856
857 ret = -EBUSY;
858 if (loops != 0)
859 ret = 0;
860
861 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
862 tw32_f(MAC_MI_MODE, tp->mi_mode);
863 udelay(80);
864 }
865
866 return ret;
867 }
868
869 static int tg3_bmcr_reset(struct tg3 *tp)
870 {
871 u32 phy_control;
872 int limit, err;
873
874 /* OK, reset it, and poll the BMCR_RESET bit until it
875 * clears or we time out.
876 */
877 phy_control = BMCR_RESET;
878 err = tg3_writephy(tp, MII_BMCR, phy_control);
879 if (err != 0)
880 return -EBUSY;
881
882 limit = 5000;
883 while (limit--) {
884 err = tg3_readphy(tp, MII_BMCR, &phy_control);
885 if (err != 0)
886 return -EBUSY;
887
888 if ((phy_control & BMCR_RESET) == 0) {
889 udelay(40);
890 break;
891 }
892 udelay(10);
893 }
894 if (limit < 0)
895 return -EBUSY;
896
897 return 0;
898 }
899
900 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
901 {
902 struct tg3 *tp = bp->priv;
903 u32 val;
904
905 spin_lock_bh(&tp->lock);
906
907 if (tg3_readphy(tp, reg, &val))
908 val = -EIO;
909
910 spin_unlock_bh(&tp->lock);
911
912 return val;
913 }
914
915 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
916 {
917 struct tg3 *tp = bp->priv;
918 u32 ret = 0;
919
920 spin_lock_bh(&tp->lock);
921
922 if (tg3_writephy(tp, reg, val))
923 ret = -EIO;
924
925 spin_unlock_bh(&tp->lock);
926
927 return ret;
928 }
929
930 static int tg3_mdio_reset(struct mii_bus *bp)
931 {
932 return 0;
933 }
934
935 static void tg3_mdio_config_5785(struct tg3 *tp)
936 {
937 u32 val;
938 struct phy_device *phydev;
939
940 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
941 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
942 case TG3_PHY_ID_BCM50610:
943 case TG3_PHY_ID_BCM50610M:
944 val = MAC_PHYCFG2_50610_LED_MODES;
945 break;
946 case TG3_PHY_ID_BCMAC131:
947 val = MAC_PHYCFG2_AC131_LED_MODES;
948 break;
949 case TG3_PHY_ID_RTL8211C:
950 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
951 break;
952 case TG3_PHY_ID_RTL8201E:
953 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
954 break;
955 default:
956 return;
957 }
958
959 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
960 tw32(MAC_PHYCFG2, val);
961
962 val = tr32(MAC_PHYCFG1);
963 val &= ~(MAC_PHYCFG1_RGMII_INT |
964 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
965 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
966 tw32(MAC_PHYCFG1, val);
967
968 return;
969 }
970
971 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
972 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
973 MAC_PHYCFG2_FMODE_MASK_MASK |
974 MAC_PHYCFG2_GMODE_MASK_MASK |
975 MAC_PHYCFG2_ACT_MASK_MASK |
976 MAC_PHYCFG2_QUAL_MASK_MASK |
977 MAC_PHYCFG2_INBAND_ENABLE;
978
979 tw32(MAC_PHYCFG2, val);
980
981 val = tr32(MAC_PHYCFG1);
982 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
983 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
984 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
985 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
986 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
987 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
988 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
989 }
990 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
991 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
992 tw32(MAC_PHYCFG1, val);
993
994 val = tr32(MAC_EXT_RGMII_MODE);
995 val &= ~(MAC_RGMII_MODE_RX_INT_B |
996 MAC_RGMII_MODE_RX_QUALITY |
997 MAC_RGMII_MODE_RX_ACTIVITY |
998 MAC_RGMII_MODE_RX_ENG_DET |
999 MAC_RGMII_MODE_TX_ENABLE |
1000 MAC_RGMII_MODE_TX_LOWPWR |
1001 MAC_RGMII_MODE_TX_RESET);
1002 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
1003 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1004 val |= MAC_RGMII_MODE_RX_INT_B |
1005 MAC_RGMII_MODE_RX_QUALITY |
1006 MAC_RGMII_MODE_RX_ACTIVITY |
1007 MAC_RGMII_MODE_RX_ENG_DET;
1008 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1009 val |= MAC_RGMII_MODE_TX_ENABLE |
1010 MAC_RGMII_MODE_TX_LOWPWR |
1011 MAC_RGMII_MODE_TX_RESET;
1012 }
1013 tw32(MAC_EXT_RGMII_MODE, val);
1014 }
1015
1016 static void tg3_mdio_start(struct tg3 *tp)
1017 {
1018 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1019 tw32_f(MAC_MI_MODE, tp->mi_mode);
1020 udelay(80);
1021
1022 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1023 u32 funcnum, is_serdes;
1024
1025 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1026 if (funcnum)
1027 tp->phy_addr = 2;
1028 else
1029 tp->phy_addr = 1;
1030
1031 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1032 if (is_serdes)
1033 tp->phy_addr += 7;
1034 } else
1035 tp->phy_addr = TG3_PHY_MII_ADDR;
1036
1037 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1038 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1039 tg3_mdio_config_5785(tp);
1040 }
1041
1042 static int tg3_mdio_init(struct tg3 *tp)
1043 {
1044 int i;
1045 u32 reg;
1046 struct phy_device *phydev;
1047
1048 tg3_mdio_start(tp);
1049
1050 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1051 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1052 return 0;
1053
1054 tp->mdio_bus = mdiobus_alloc();
1055 if (tp->mdio_bus == NULL)
1056 return -ENOMEM;
1057
1058 tp->mdio_bus->name = "tg3 mdio bus";
1059 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1060 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1061 tp->mdio_bus->priv = tp;
1062 tp->mdio_bus->parent = &tp->pdev->dev;
1063 tp->mdio_bus->read = &tg3_mdio_read;
1064 tp->mdio_bus->write = &tg3_mdio_write;
1065 tp->mdio_bus->reset = &tg3_mdio_reset;
1066 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1067 tp->mdio_bus->irq = &tp->mdio_irq[0];
1068
1069 for (i = 0; i < PHY_MAX_ADDR; i++)
1070 tp->mdio_bus->irq[i] = PHY_POLL;
1071
1072 /* The bus registration will look for all the PHYs on the mdio bus.
1073 * Unfortunately, it does not ensure the PHY is powered up before
1074 * accessing the PHY ID registers. A chip reset is the
1075 * quickest way to bring the device back to an operational state..
1076 */
1077 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1078 tg3_bmcr_reset(tp);
1079
1080 i = mdiobus_register(tp->mdio_bus);
1081 if (i) {
1082 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1083 tp->dev->name, i);
1084 mdiobus_free(tp->mdio_bus);
1085 return i;
1086 }
1087
1088 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1089
1090 if (!phydev || !phydev->drv) {
1091 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1092 mdiobus_unregister(tp->mdio_bus);
1093 mdiobus_free(tp->mdio_bus);
1094 return -ENODEV;
1095 }
1096
1097 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1098 case TG3_PHY_ID_BCM57780:
1099 phydev->interface = PHY_INTERFACE_MODE_GMII;
1100 break;
1101 case TG3_PHY_ID_BCM50610:
1102 case TG3_PHY_ID_BCM50610M:
1103 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1104 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1105 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1106 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1107 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1108 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1109 /* fallthru */
1110 case TG3_PHY_ID_RTL8211C:
1111 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1112 break;
1113 case TG3_PHY_ID_RTL8201E:
1114 case TG3_PHY_ID_BCMAC131:
1115 phydev->interface = PHY_INTERFACE_MODE_MII;
1116 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1117 break;
1118 }
1119
1120 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1121
1122 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1123 tg3_mdio_config_5785(tp);
1124
1125 return 0;
1126 }
1127
1128 static void tg3_mdio_fini(struct tg3 *tp)
1129 {
1130 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1131 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1132 mdiobus_unregister(tp->mdio_bus);
1133 mdiobus_free(tp->mdio_bus);
1134 }
1135 }
1136
1137 /* tp->lock is held. */
1138 static inline void tg3_generate_fw_event(struct tg3 *tp)
1139 {
1140 u32 val;
1141
1142 val = tr32(GRC_RX_CPU_EVENT);
1143 val |= GRC_RX_CPU_DRIVER_EVENT;
1144 tw32_f(GRC_RX_CPU_EVENT, val);
1145
1146 tp->last_event_jiffies = jiffies;
1147 }
1148
1149 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1150
1151 /* tp->lock is held. */
1152 static void tg3_wait_for_event_ack(struct tg3 *tp)
1153 {
1154 int i;
1155 unsigned int delay_cnt;
1156 long time_remain;
1157
1158 /* If enough time has passed, no wait is necessary. */
1159 time_remain = (long)(tp->last_event_jiffies + 1 +
1160 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1161 (long)jiffies;
1162 if (time_remain < 0)
1163 return;
1164
1165 /* Check if we can shorten the wait time. */
1166 delay_cnt = jiffies_to_usecs(time_remain);
1167 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1168 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1169 delay_cnt = (delay_cnt >> 3) + 1;
1170
1171 for (i = 0; i < delay_cnt; i++) {
1172 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1173 break;
1174 udelay(8);
1175 }
1176 }
1177
1178 /* tp->lock is held. */
1179 static void tg3_ump_link_report(struct tg3 *tp)
1180 {
1181 u32 reg;
1182 u32 val;
1183
1184 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1185 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1186 return;
1187
1188 tg3_wait_for_event_ack(tp);
1189
1190 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1191
1192 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1193
1194 val = 0;
1195 if (!tg3_readphy(tp, MII_BMCR, &reg))
1196 val = reg << 16;
1197 if (!tg3_readphy(tp, MII_BMSR, &reg))
1198 val |= (reg & 0xffff);
1199 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1200
1201 val = 0;
1202 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1203 val = reg << 16;
1204 if (!tg3_readphy(tp, MII_LPA, &reg))
1205 val |= (reg & 0xffff);
1206 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1207
1208 val = 0;
1209 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1210 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1211 val = reg << 16;
1212 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1213 val |= (reg & 0xffff);
1214 }
1215 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1216
1217 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1218 val = reg << 16;
1219 else
1220 val = 0;
1221 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1222
1223 tg3_generate_fw_event(tp);
1224 }
1225
1226 static void tg3_link_report(struct tg3 *tp)
1227 {
1228 if (!netif_carrier_ok(tp->dev)) {
1229 if (netif_msg_link(tp))
1230 printk(KERN_INFO PFX "%s: Link is down.\n",
1231 tp->dev->name);
1232 tg3_ump_link_report(tp);
1233 } else if (netif_msg_link(tp)) {
1234 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1235 tp->dev->name,
1236 (tp->link_config.active_speed == SPEED_1000 ?
1237 1000 :
1238 (tp->link_config.active_speed == SPEED_100 ?
1239 100 : 10)),
1240 (tp->link_config.active_duplex == DUPLEX_FULL ?
1241 "full" : "half"));
1242
1243 printk(KERN_INFO PFX
1244 "%s: Flow control is %s for TX and %s for RX.\n",
1245 tp->dev->name,
1246 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1247 "on" : "off",
1248 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1249 "on" : "off");
1250 tg3_ump_link_report(tp);
1251 }
1252 }
1253
1254 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1255 {
1256 u16 miireg;
1257
1258 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1259 miireg = ADVERTISE_PAUSE_CAP;
1260 else if (flow_ctrl & FLOW_CTRL_TX)
1261 miireg = ADVERTISE_PAUSE_ASYM;
1262 else if (flow_ctrl & FLOW_CTRL_RX)
1263 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1264 else
1265 miireg = 0;
1266
1267 return miireg;
1268 }
1269
1270 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1271 {
1272 u16 miireg;
1273
1274 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1275 miireg = ADVERTISE_1000XPAUSE;
1276 else if (flow_ctrl & FLOW_CTRL_TX)
1277 miireg = ADVERTISE_1000XPSE_ASYM;
1278 else if (flow_ctrl & FLOW_CTRL_RX)
1279 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1280 else
1281 miireg = 0;
1282
1283 return miireg;
1284 }
1285
1286 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1287 {
1288 u8 cap = 0;
1289
1290 if (lcladv & ADVERTISE_1000XPAUSE) {
1291 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1292 if (rmtadv & LPA_1000XPAUSE)
1293 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1294 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1295 cap = FLOW_CTRL_RX;
1296 } else {
1297 if (rmtadv & LPA_1000XPAUSE)
1298 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1299 }
1300 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1301 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1302 cap = FLOW_CTRL_TX;
1303 }
1304
1305 return cap;
1306 }
1307
1308 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1309 {
1310 u8 autoneg;
1311 u8 flowctrl = 0;
1312 u32 old_rx_mode = tp->rx_mode;
1313 u32 old_tx_mode = tp->tx_mode;
1314
1315 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1316 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1317 else
1318 autoneg = tp->link_config.autoneg;
1319
1320 if (autoneg == AUTONEG_ENABLE &&
1321 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1322 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1323 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1324 else
1325 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1326 } else
1327 flowctrl = tp->link_config.flowctrl;
1328
1329 tp->link_config.active_flowctrl = flowctrl;
1330
1331 if (flowctrl & FLOW_CTRL_RX)
1332 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1333 else
1334 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1335
1336 if (old_rx_mode != tp->rx_mode)
1337 tw32_f(MAC_RX_MODE, tp->rx_mode);
1338
1339 if (flowctrl & FLOW_CTRL_TX)
1340 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1341 else
1342 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1343
1344 if (old_tx_mode != tp->tx_mode)
1345 tw32_f(MAC_TX_MODE, tp->tx_mode);
1346 }
1347
1348 static void tg3_adjust_link(struct net_device *dev)
1349 {
1350 u8 oldflowctrl, linkmesg = 0;
1351 u32 mac_mode, lcl_adv, rmt_adv;
1352 struct tg3 *tp = netdev_priv(dev);
1353 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1354
1355 spin_lock_bh(&tp->lock);
1356
1357 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1358 MAC_MODE_HALF_DUPLEX);
1359
1360 oldflowctrl = tp->link_config.active_flowctrl;
1361
1362 if (phydev->link) {
1363 lcl_adv = 0;
1364 rmt_adv = 0;
1365
1366 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1367 mac_mode |= MAC_MODE_PORT_MODE_MII;
1368 else if (phydev->speed == SPEED_1000 ||
1369 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1370 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1371 else
1372 mac_mode |= MAC_MODE_PORT_MODE_MII;
1373
1374 if (phydev->duplex == DUPLEX_HALF)
1375 mac_mode |= MAC_MODE_HALF_DUPLEX;
1376 else {
1377 lcl_adv = tg3_advert_flowctrl_1000T(
1378 tp->link_config.flowctrl);
1379
1380 if (phydev->pause)
1381 rmt_adv = LPA_PAUSE_CAP;
1382 if (phydev->asym_pause)
1383 rmt_adv |= LPA_PAUSE_ASYM;
1384 }
1385
1386 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1387 } else
1388 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1389
1390 if (mac_mode != tp->mac_mode) {
1391 tp->mac_mode = mac_mode;
1392 tw32_f(MAC_MODE, tp->mac_mode);
1393 udelay(40);
1394 }
1395
1396 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1397 if (phydev->speed == SPEED_10)
1398 tw32(MAC_MI_STAT,
1399 MAC_MI_STAT_10MBPS_MODE |
1400 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1401 else
1402 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1403 }
1404
1405 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1406 tw32(MAC_TX_LENGTHS,
1407 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1408 (6 << TX_LENGTHS_IPG_SHIFT) |
1409 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1410 else
1411 tw32(MAC_TX_LENGTHS,
1412 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1413 (6 << TX_LENGTHS_IPG_SHIFT) |
1414 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1415
1416 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1417 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1418 phydev->speed != tp->link_config.active_speed ||
1419 phydev->duplex != tp->link_config.active_duplex ||
1420 oldflowctrl != tp->link_config.active_flowctrl)
1421 linkmesg = 1;
1422
1423 tp->link_config.active_speed = phydev->speed;
1424 tp->link_config.active_duplex = phydev->duplex;
1425
1426 spin_unlock_bh(&tp->lock);
1427
1428 if (linkmesg)
1429 tg3_link_report(tp);
1430 }
1431
1432 static int tg3_phy_init(struct tg3 *tp)
1433 {
1434 struct phy_device *phydev;
1435
1436 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1437 return 0;
1438
1439 /* Bring the PHY back to a known state. */
1440 tg3_bmcr_reset(tp);
1441
1442 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1443
1444 /* Attach the MAC to the PHY. */
1445 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1446 phydev->dev_flags, phydev->interface);
1447 if (IS_ERR(phydev)) {
1448 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1449 return PTR_ERR(phydev);
1450 }
1451
1452 /* Mask with MAC supported features. */
1453 switch (phydev->interface) {
1454 case PHY_INTERFACE_MODE_GMII:
1455 case PHY_INTERFACE_MODE_RGMII:
1456 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1457 phydev->supported &= (PHY_GBIT_FEATURES |
1458 SUPPORTED_Pause |
1459 SUPPORTED_Asym_Pause);
1460 break;
1461 }
1462 /* fallthru */
1463 case PHY_INTERFACE_MODE_MII:
1464 phydev->supported &= (PHY_BASIC_FEATURES |
1465 SUPPORTED_Pause |
1466 SUPPORTED_Asym_Pause);
1467 break;
1468 default:
1469 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1470 return -EINVAL;
1471 }
1472
1473 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1474
1475 phydev->advertising = phydev->supported;
1476
1477 return 0;
1478 }
1479
1480 static void tg3_phy_start(struct tg3 *tp)
1481 {
1482 struct phy_device *phydev;
1483
1484 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1485 return;
1486
1487 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1488
1489 if (tp->link_config.phy_is_low_power) {
1490 tp->link_config.phy_is_low_power = 0;
1491 phydev->speed = tp->link_config.orig_speed;
1492 phydev->duplex = tp->link_config.orig_duplex;
1493 phydev->autoneg = tp->link_config.orig_autoneg;
1494 phydev->advertising = tp->link_config.orig_advertising;
1495 }
1496
1497 phy_start(phydev);
1498
1499 phy_start_aneg(phydev);
1500 }
1501
1502 static void tg3_phy_stop(struct tg3 *tp)
1503 {
1504 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1505 return;
1506
1507 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1508 }
1509
1510 static void tg3_phy_fini(struct tg3 *tp)
1511 {
1512 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1513 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1514 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1515 }
1516 }
1517
1518 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1519 {
1520 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1521 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1522 }
1523
1524 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1525 {
1526 u32 phytest;
1527
1528 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1529 u32 phy;
1530
1531 tg3_writephy(tp, MII_TG3_FET_TEST,
1532 phytest | MII_TG3_FET_SHADOW_EN);
1533 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1534 if (enable)
1535 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1536 else
1537 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1538 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1539 }
1540 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1541 }
1542 }
1543
1544 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1545 {
1546 u32 reg;
1547
1548 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1549 return;
1550
1551 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1552 tg3_phy_fet_toggle_apd(tp, enable);
1553 return;
1554 }
1555
1556 reg = MII_TG3_MISC_SHDW_WREN |
1557 MII_TG3_MISC_SHDW_SCR5_SEL |
1558 MII_TG3_MISC_SHDW_SCR5_LPED |
1559 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1560 MII_TG3_MISC_SHDW_SCR5_SDTL |
1561 MII_TG3_MISC_SHDW_SCR5_C125OE;
1562 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1563 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1564
1565 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1566
1567
1568 reg = MII_TG3_MISC_SHDW_WREN |
1569 MII_TG3_MISC_SHDW_APD_SEL |
1570 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1571 if (enable)
1572 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1573
1574 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1575 }
1576
1577 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1578 {
1579 u32 phy;
1580
1581 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1582 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1583 return;
1584
1585 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1586 u32 ephy;
1587
1588 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1589 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1590
1591 tg3_writephy(tp, MII_TG3_FET_TEST,
1592 ephy | MII_TG3_FET_SHADOW_EN);
1593 if (!tg3_readphy(tp, reg, &phy)) {
1594 if (enable)
1595 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1596 else
1597 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1598 tg3_writephy(tp, reg, phy);
1599 }
1600 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1601 }
1602 } else {
1603 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1604 MII_TG3_AUXCTL_SHDWSEL_MISC;
1605 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1606 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1607 if (enable)
1608 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1609 else
1610 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1611 phy |= MII_TG3_AUXCTL_MISC_WREN;
1612 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1613 }
1614 }
1615 }
1616
1617 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1618 {
1619 u32 val;
1620
1621 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1622 return;
1623
1624 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1625 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1626 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1627 (val | (1 << 15) | (1 << 4)));
1628 }
1629
1630 static void tg3_phy_apply_otp(struct tg3 *tp)
1631 {
1632 u32 otp, phy;
1633
1634 if (!tp->phy_otp)
1635 return;
1636
1637 otp = tp->phy_otp;
1638
1639 /* Enable SM_DSP clock and tx 6dB coding. */
1640 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1641 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1642 MII_TG3_AUXCTL_ACTL_TX_6DB;
1643 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1644
1645 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1646 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1647 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1648
1649 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1650 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1651 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1652
1653 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1654 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1655 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1656
1657 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1658 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1659
1660 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1661 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1662
1663 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1664 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1665 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1666
1667 /* Turn off SM_DSP clock. */
1668 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1669 MII_TG3_AUXCTL_ACTL_TX_6DB;
1670 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1671 }
1672
1673 static int tg3_wait_macro_done(struct tg3 *tp)
1674 {
1675 int limit = 100;
1676
1677 while (limit--) {
1678 u32 tmp32;
1679
1680 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1681 if ((tmp32 & 0x1000) == 0)
1682 break;
1683 }
1684 }
1685 if (limit < 0)
1686 return -EBUSY;
1687
1688 return 0;
1689 }
1690
1691 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1692 {
1693 static const u32 test_pat[4][6] = {
1694 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1695 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1696 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1697 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1698 };
1699 int chan;
1700
1701 for (chan = 0; chan < 4; chan++) {
1702 int i;
1703
1704 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1705 (chan * 0x2000) | 0x0200);
1706 tg3_writephy(tp, 0x16, 0x0002);
1707
1708 for (i = 0; i < 6; i++)
1709 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1710 test_pat[chan][i]);
1711
1712 tg3_writephy(tp, 0x16, 0x0202);
1713 if (tg3_wait_macro_done(tp)) {
1714 *resetp = 1;
1715 return -EBUSY;
1716 }
1717
1718 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1719 (chan * 0x2000) | 0x0200);
1720 tg3_writephy(tp, 0x16, 0x0082);
1721 if (tg3_wait_macro_done(tp)) {
1722 *resetp = 1;
1723 return -EBUSY;
1724 }
1725
1726 tg3_writephy(tp, 0x16, 0x0802);
1727 if (tg3_wait_macro_done(tp)) {
1728 *resetp = 1;
1729 return -EBUSY;
1730 }
1731
1732 for (i = 0; i < 6; i += 2) {
1733 u32 low, high;
1734
1735 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1736 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1737 tg3_wait_macro_done(tp)) {
1738 *resetp = 1;
1739 return -EBUSY;
1740 }
1741 low &= 0x7fff;
1742 high &= 0x000f;
1743 if (low != test_pat[chan][i] ||
1744 high != test_pat[chan][i+1]) {
1745 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1746 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1747 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1748
1749 return -EBUSY;
1750 }
1751 }
1752 }
1753
1754 return 0;
1755 }
1756
1757 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1758 {
1759 int chan;
1760
1761 for (chan = 0; chan < 4; chan++) {
1762 int i;
1763
1764 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1765 (chan * 0x2000) | 0x0200);
1766 tg3_writephy(tp, 0x16, 0x0002);
1767 for (i = 0; i < 6; i++)
1768 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1769 tg3_writephy(tp, 0x16, 0x0202);
1770 if (tg3_wait_macro_done(tp))
1771 return -EBUSY;
1772 }
1773
1774 return 0;
1775 }
1776
1777 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1778 {
1779 u32 reg32, phy9_orig;
1780 int retries, do_phy_reset, err;
1781
1782 retries = 10;
1783 do_phy_reset = 1;
1784 do {
1785 if (do_phy_reset) {
1786 err = tg3_bmcr_reset(tp);
1787 if (err)
1788 return err;
1789 do_phy_reset = 0;
1790 }
1791
1792 /* Disable transmitter and interrupt. */
1793 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1794 continue;
1795
1796 reg32 |= 0x3000;
1797 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1798
1799 /* Set full-duplex, 1000 mbps. */
1800 tg3_writephy(tp, MII_BMCR,
1801 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1802
1803 /* Set to master mode. */
1804 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1805 continue;
1806
1807 tg3_writephy(tp, MII_TG3_CTRL,
1808 (MII_TG3_CTRL_AS_MASTER |
1809 MII_TG3_CTRL_ENABLE_AS_MASTER));
1810
1811 /* Enable SM_DSP_CLOCK and 6dB. */
1812 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1813
1814 /* Block the PHY control access. */
1815 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1816 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1817
1818 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1819 if (!err)
1820 break;
1821 } while (--retries);
1822
1823 err = tg3_phy_reset_chanpat(tp);
1824 if (err)
1825 return err;
1826
1827 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1828 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1829
1830 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1831 tg3_writephy(tp, 0x16, 0x0000);
1832
1833 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1834 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1835 /* Set Extended packet length bit for jumbo frames */
1836 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1837 }
1838 else {
1839 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1840 }
1841
1842 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1843
1844 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1845 reg32 &= ~0x3000;
1846 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1847 } else if (!err)
1848 err = -EBUSY;
1849
1850 return err;
1851 }
1852
1853 /* This will reset the tigon3 PHY if there is no valid
1854 * link unless the FORCE argument is non-zero.
1855 */
1856 static int tg3_phy_reset(struct tg3 *tp)
1857 {
1858 u32 cpmuctrl;
1859 u32 phy_status;
1860 int err;
1861
1862 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1863 u32 val;
1864
1865 val = tr32(GRC_MISC_CFG);
1866 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1867 udelay(40);
1868 }
1869 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1870 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1871 if (err != 0)
1872 return -EBUSY;
1873
1874 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1875 netif_carrier_off(tp->dev);
1876 tg3_link_report(tp);
1877 }
1878
1879 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1880 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1881 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1882 err = tg3_phy_reset_5703_4_5(tp);
1883 if (err)
1884 return err;
1885 goto out;
1886 }
1887
1888 cpmuctrl = 0;
1889 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1890 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1891 cpmuctrl = tr32(TG3_CPMU_CTRL);
1892 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1893 tw32(TG3_CPMU_CTRL,
1894 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1895 }
1896
1897 err = tg3_bmcr_reset(tp);
1898 if (err)
1899 return err;
1900
1901 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1902 u32 phy;
1903
1904 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1905 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1906
1907 tw32(TG3_CPMU_CTRL, cpmuctrl);
1908 }
1909
1910 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1911 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1912 u32 val;
1913
1914 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1915 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1916 CPMU_LSPD_1000MB_MACCLK_12_5) {
1917 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1918 udelay(40);
1919 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1920 }
1921 }
1922
1923 tg3_phy_apply_otp(tp);
1924
1925 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1926 tg3_phy_toggle_apd(tp, true);
1927 else
1928 tg3_phy_toggle_apd(tp, false);
1929
1930 out:
1931 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1932 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1933 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1934 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1935 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1936 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1937 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1938 }
1939 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1940 tg3_writephy(tp, 0x1c, 0x8d68);
1941 tg3_writephy(tp, 0x1c, 0x8d68);
1942 }
1943 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1944 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1945 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1946 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1947 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1948 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1949 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1950 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1951 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1952 }
1953 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1954 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1955 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1956 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1957 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1958 tg3_writephy(tp, MII_TG3_TEST1,
1959 MII_TG3_TEST1_TRIM_EN | 0x4);
1960 } else
1961 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1962 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1963 }
1964 /* Set Extended packet length bit (bit 14) on all chips that */
1965 /* support jumbo frames */
1966 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1967 /* Cannot do read-modify-write on 5401 */
1968 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1969 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1970 u32 phy_reg;
1971
1972 /* Set bit 14 with read-modify-write to preserve other bits */
1973 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1974 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1975 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1976 }
1977
1978 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1979 * jumbo frames transmission.
1980 */
1981 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1982 u32 phy_reg;
1983
1984 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1985 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1986 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1987 }
1988
1989 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1990 /* adjust output voltage */
1991 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
1992 }
1993
1994 tg3_phy_toggle_automdix(tp, 1);
1995 tg3_phy_set_wirespeed(tp);
1996 return 0;
1997 }
1998
1999 static void tg3_frob_aux_power(struct tg3 *tp)
2000 {
2001 struct tg3 *tp_peer = tp;
2002
2003 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
2004 return;
2005
2006 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2007 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2008 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2009 struct net_device *dev_peer;
2010
2011 dev_peer = pci_get_drvdata(tp->pdev_peer);
2012 /* remove_one() may have been run on the peer. */
2013 if (!dev_peer)
2014 tp_peer = tp;
2015 else
2016 tp_peer = netdev_priv(dev_peer);
2017 }
2018
2019 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2020 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2021 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2022 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2023 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2024 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2025 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2026 (GRC_LCLCTRL_GPIO_OE0 |
2027 GRC_LCLCTRL_GPIO_OE1 |
2028 GRC_LCLCTRL_GPIO_OE2 |
2029 GRC_LCLCTRL_GPIO_OUTPUT0 |
2030 GRC_LCLCTRL_GPIO_OUTPUT1),
2031 100);
2032 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2033 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2034 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2035 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2036 GRC_LCLCTRL_GPIO_OE1 |
2037 GRC_LCLCTRL_GPIO_OE2 |
2038 GRC_LCLCTRL_GPIO_OUTPUT0 |
2039 GRC_LCLCTRL_GPIO_OUTPUT1 |
2040 tp->grc_local_ctrl;
2041 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2042
2043 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2044 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2045
2046 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2047 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2048 } else {
2049 u32 no_gpio2;
2050 u32 grc_local_ctrl = 0;
2051
2052 if (tp_peer != tp &&
2053 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2054 return;
2055
2056 /* Workaround to prevent overdrawing Amps. */
2057 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2058 ASIC_REV_5714) {
2059 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2060 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2061 grc_local_ctrl, 100);
2062 }
2063
2064 /* On 5753 and variants, GPIO2 cannot be used. */
2065 no_gpio2 = tp->nic_sram_data_cfg &
2066 NIC_SRAM_DATA_CFG_NO_GPIO2;
2067
2068 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2069 GRC_LCLCTRL_GPIO_OE1 |
2070 GRC_LCLCTRL_GPIO_OE2 |
2071 GRC_LCLCTRL_GPIO_OUTPUT1 |
2072 GRC_LCLCTRL_GPIO_OUTPUT2;
2073 if (no_gpio2) {
2074 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2075 GRC_LCLCTRL_GPIO_OUTPUT2);
2076 }
2077 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2078 grc_local_ctrl, 100);
2079
2080 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2081
2082 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2083 grc_local_ctrl, 100);
2084
2085 if (!no_gpio2) {
2086 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2087 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2088 grc_local_ctrl, 100);
2089 }
2090 }
2091 } else {
2092 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2093 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2094 if (tp_peer != tp &&
2095 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2096 return;
2097
2098 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2099 (GRC_LCLCTRL_GPIO_OE1 |
2100 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2101
2102 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2103 GRC_LCLCTRL_GPIO_OE1, 100);
2104
2105 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2106 (GRC_LCLCTRL_GPIO_OE1 |
2107 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2108 }
2109 }
2110 }
2111
2112 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2113 {
2114 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2115 return 1;
2116 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2117 if (speed != SPEED_10)
2118 return 1;
2119 } else if (speed == SPEED_10)
2120 return 1;
2121
2122 return 0;
2123 }
2124
2125 static int tg3_setup_phy(struct tg3 *, int);
2126
2127 #define RESET_KIND_SHUTDOWN 0
2128 #define RESET_KIND_INIT 1
2129 #define RESET_KIND_SUSPEND 2
2130
2131 static void tg3_write_sig_post_reset(struct tg3 *, int);
2132 static int tg3_halt_cpu(struct tg3 *, u32);
2133
2134 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2135 {
2136 u32 val;
2137
2138 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2139 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2140 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2141 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2142
2143 sg_dig_ctrl |=
2144 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2145 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2146 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2147 }
2148 return;
2149 }
2150
2151 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2152 tg3_bmcr_reset(tp);
2153 val = tr32(GRC_MISC_CFG);
2154 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2155 udelay(40);
2156 return;
2157 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2158 u32 phytest;
2159 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2160 u32 phy;
2161
2162 tg3_writephy(tp, MII_ADVERTISE, 0);
2163 tg3_writephy(tp, MII_BMCR,
2164 BMCR_ANENABLE | BMCR_ANRESTART);
2165
2166 tg3_writephy(tp, MII_TG3_FET_TEST,
2167 phytest | MII_TG3_FET_SHADOW_EN);
2168 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2169 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2170 tg3_writephy(tp,
2171 MII_TG3_FET_SHDW_AUXMODE4,
2172 phy);
2173 }
2174 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2175 }
2176 return;
2177 } else if (do_low_power) {
2178 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2179 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2180
2181 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2182 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2183 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2184 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2185 MII_TG3_AUXCTL_PCTL_VREG_11V);
2186 }
2187
2188 /* The PHY should not be powered down on some chips because
2189 * of bugs.
2190 */
2191 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2192 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2193 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2194 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2195 return;
2196
2197 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2198 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2199 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2200 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2201 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2202 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2203 }
2204
2205 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2206 }
2207
2208 /* tp->lock is held. */
2209 static int tg3_nvram_lock(struct tg3 *tp)
2210 {
2211 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2212 int i;
2213
2214 if (tp->nvram_lock_cnt == 0) {
2215 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2216 for (i = 0; i < 8000; i++) {
2217 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2218 break;
2219 udelay(20);
2220 }
2221 if (i == 8000) {
2222 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2223 return -ENODEV;
2224 }
2225 }
2226 tp->nvram_lock_cnt++;
2227 }
2228 return 0;
2229 }
2230
2231 /* tp->lock is held. */
2232 static void tg3_nvram_unlock(struct tg3 *tp)
2233 {
2234 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2235 if (tp->nvram_lock_cnt > 0)
2236 tp->nvram_lock_cnt--;
2237 if (tp->nvram_lock_cnt == 0)
2238 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2239 }
2240 }
2241
2242 /* tp->lock is held. */
2243 static void tg3_enable_nvram_access(struct tg3 *tp)
2244 {
2245 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2246 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2247 u32 nvaccess = tr32(NVRAM_ACCESS);
2248
2249 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2250 }
2251 }
2252
2253 /* tp->lock is held. */
2254 static void tg3_disable_nvram_access(struct tg3 *tp)
2255 {
2256 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2257 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2258 u32 nvaccess = tr32(NVRAM_ACCESS);
2259
2260 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2261 }
2262 }
2263
2264 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2265 u32 offset, u32 *val)
2266 {
2267 u32 tmp;
2268 int i;
2269
2270 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2271 return -EINVAL;
2272
2273 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2274 EEPROM_ADDR_DEVID_MASK |
2275 EEPROM_ADDR_READ);
2276 tw32(GRC_EEPROM_ADDR,
2277 tmp |
2278 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2279 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2280 EEPROM_ADDR_ADDR_MASK) |
2281 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2282
2283 for (i = 0; i < 1000; i++) {
2284 tmp = tr32(GRC_EEPROM_ADDR);
2285
2286 if (tmp & EEPROM_ADDR_COMPLETE)
2287 break;
2288 msleep(1);
2289 }
2290 if (!(tmp & EEPROM_ADDR_COMPLETE))
2291 return -EBUSY;
2292
2293 tmp = tr32(GRC_EEPROM_DATA);
2294
2295 /*
2296 * The data will always be opposite the native endian
2297 * format. Perform a blind byteswap to compensate.
2298 */
2299 *val = swab32(tmp);
2300
2301 return 0;
2302 }
2303
2304 #define NVRAM_CMD_TIMEOUT 10000
2305
2306 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2307 {
2308 int i;
2309
2310 tw32(NVRAM_CMD, nvram_cmd);
2311 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2312 udelay(10);
2313 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2314 udelay(10);
2315 break;
2316 }
2317 }
2318
2319 if (i == NVRAM_CMD_TIMEOUT)
2320 return -EBUSY;
2321
2322 return 0;
2323 }
2324
2325 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2326 {
2327 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2328 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2329 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2330 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2331 (tp->nvram_jedecnum == JEDEC_ATMEL))
2332
2333 addr = ((addr / tp->nvram_pagesize) <<
2334 ATMEL_AT45DB0X1B_PAGE_POS) +
2335 (addr % tp->nvram_pagesize);
2336
2337 return addr;
2338 }
2339
2340 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2341 {
2342 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2343 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2344 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2345 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2346 (tp->nvram_jedecnum == JEDEC_ATMEL))
2347
2348 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2349 tp->nvram_pagesize) +
2350 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2351
2352 return addr;
2353 }
2354
2355 /* NOTE: Data read in from NVRAM is byteswapped according to
2356 * the byteswapping settings for all other register accesses.
2357 * tg3 devices are BE devices, so on a BE machine, the data
2358 * returned will be exactly as it is seen in NVRAM. On a LE
2359 * machine, the 32-bit value will be byteswapped.
2360 */
2361 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2362 {
2363 int ret;
2364
2365 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2366 return tg3_nvram_read_using_eeprom(tp, offset, val);
2367
2368 offset = tg3_nvram_phys_addr(tp, offset);
2369
2370 if (offset > NVRAM_ADDR_MSK)
2371 return -EINVAL;
2372
2373 ret = tg3_nvram_lock(tp);
2374 if (ret)
2375 return ret;
2376
2377 tg3_enable_nvram_access(tp);
2378
2379 tw32(NVRAM_ADDR, offset);
2380 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2381 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2382
2383 if (ret == 0)
2384 *val = tr32(NVRAM_RDDATA);
2385
2386 tg3_disable_nvram_access(tp);
2387
2388 tg3_nvram_unlock(tp);
2389
2390 return ret;
2391 }
2392
2393 /* Ensures NVRAM data is in bytestream format. */
2394 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2395 {
2396 u32 v;
2397 int res = tg3_nvram_read(tp, offset, &v);
2398 if (!res)
2399 *val = cpu_to_be32(v);
2400 return res;
2401 }
2402
2403 /* tp->lock is held. */
2404 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2405 {
2406 u32 addr_high, addr_low;
2407 int i;
2408
2409 addr_high = ((tp->dev->dev_addr[0] << 8) |
2410 tp->dev->dev_addr[1]);
2411 addr_low = ((tp->dev->dev_addr[2] << 24) |
2412 (tp->dev->dev_addr[3] << 16) |
2413 (tp->dev->dev_addr[4] << 8) |
2414 (tp->dev->dev_addr[5] << 0));
2415 for (i = 0; i < 4; i++) {
2416 if (i == 1 && skip_mac_1)
2417 continue;
2418 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2419 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2420 }
2421
2422 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2423 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2424 for (i = 0; i < 12; i++) {
2425 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2426 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2427 }
2428 }
2429
2430 addr_high = (tp->dev->dev_addr[0] +
2431 tp->dev->dev_addr[1] +
2432 tp->dev->dev_addr[2] +
2433 tp->dev->dev_addr[3] +
2434 tp->dev->dev_addr[4] +
2435 tp->dev->dev_addr[5]) &
2436 TX_BACKOFF_SEED_MASK;
2437 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2438 }
2439
2440 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2441 {
2442 u32 misc_host_ctrl;
2443 bool device_should_wake, do_low_power;
2444
2445 /* Make sure register accesses (indirect or otherwise)
2446 * will function correctly.
2447 */
2448 pci_write_config_dword(tp->pdev,
2449 TG3PCI_MISC_HOST_CTRL,
2450 tp->misc_host_ctrl);
2451
2452 switch (state) {
2453 case PCI_D0:
2454 pci_enable_wake(tp->pdev, state, false);
2455 pci_set_power_state(tp->pdev, PCI_D0);
2456
2457 /* Switch out of Vaux if it is a NIC */
2458 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2459 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2460
2461 return 0;
2462
2463 case PCI_D1:
2464 case PCI_D2:
2465 case PCI_D3hot:
2466 break;
2467
2468 default:
2469 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2470 tp->dev->name, state);
2471 return -EINVAL;
2472 }
2473
2474 /* Restore the CLKREQ setting. */
2475 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2476 u16 lnkctl;
2477
2478 pci_read_config_word(tp->pdev,
2479 tp->pcie_cap + PCI_EXP_LNKCTL,
2480 &lnkctl);
2481 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2482 pci_write_config_word(tp->pdev,
2483 tp->pcie_cap + PCI_EXP_LNKCTL,
2484 lnkctl);
2485 }
2486
2487 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2488 tw32(TG3PCI_MISC_HOST_CTRL,
2489 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2490
2491 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2492 device_may_wakeup(&tp->pdev->dev) &&
2493 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2494
2495 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2496 do_low_power = false;
2497 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2498 !tp->link_config.phy_is_low_power) {
2499 struct phy_device *phydev;
2500 u32 phyid, advertising;
2501
2502 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2503
2504 tp->link_config.phy_is_low_power = 1;
2505
2506 tp->link_config.orig_speed = phydev->speed;
2507 tp->link_config.orig_duplex = phydev->duplex;
2508 tp->link_config.orig_autoneg = phydev->autoneg;
2509 tp->link_config.orig_advertising = phydev->advertising;
2510
2511 advertising = ADVERTISED_TP |
2512 ADVERTISED_Pause |
2513 ADVERTISED_Autoneg |
2514 ADVERTISED_10baseT_Half;
2515
2516 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2517 device_should_wake) {
2518 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2519 advertising |=
2520 ADVERTISED_100baseT_Half |
2521 ADVERTISED_100baseT_Full |
2522 ADVERTISED_10baseT_Full;
2523 else
2524 advertising |= ADVERTISED_10baseT_Full;
2525 }
2526
2527 phydev->advertising = advertising;
2528
2529 phy_start_aneg(phydev);
2530
2531 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2532 if (phyid != TG3_PHY_ID_BCMAC131) {
2533 phyid &= TG3_PHY_OUI_MASK;
2534 if (phyid == TG3_PHY_OUI_1 ||
2535 phyid == TG3_PHY_OUI_2 ||
2536 phyid == TG3_PHY_OUI_3)
2537 do_low_power = true;
2538 }
2539 }
2540 } else {
2541 do_low_power = true;
2542
2543 if (tp->link_config.phy_is_low_power == 0) {
2544 tp->link_config.phy_is_low_power = 1;
2545 tp->link_config.orig_speed = tp->link_config.speed;
2546 tp->link_config.orig_duplex = tp->link_config.duplex;
2547 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2548 }
2549
2550 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2551 tp->link_config.speed = SPEED_10;
2552 tp->link_config.duplex = DUPLEX_HALF;
2553 tp->link_config.autoneg = AUTONEG_ENABLE;
2554 tg3_setup_phy(tp, 0);
2555 }
2556 }
2557
2558 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2559 u32 val;
2560
2561 val = tr32(GRC_VCPU_EXT_CTRL);
2562 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2563 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2564 int i;
2565 u32 val;
2566
2567 for (i = 0; i < 200; i++) {
2568 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2569 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2570 break;
2571 msleep(1);
2572 }
2573 }
2574 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2575 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2576 WOL_DRV_STATE_SHUTDOWN |
2577 WOL_DRV_WOL |
2578 WOL_SET_MAGIC_PKT);
2579
2580 if (device_should_wake) {
2581 u32 mac_mode;
2582
2583 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2584 if (do_low_power) {
2585 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2586 udelay(40);
2587 }
2588
2589 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2590 mac_mode = MAC_MODE_PORT_MODE_GMII;
2591 else
2592 mac_mode = MAC_MODE_PORT_MODE_MII;
2593
2594 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2595 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2596 ASIC_REV_5700) {
2597 u32 speed = (tp->tg3_flags &
2598 TG3_FLAG_WOL_SPEED_100MB) ?
2599 SPEED_100 : SPEED_10;
2600 if (tg3_5700_link_polarity(tp, speed))
2601 mac_mode |= MAC_MODE_LINK_POLARITY;
2602 else
2603 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2604 }
2605 } else {
2606 mac_mode = MAC_MODE_PORT_MODE_TBI;
2607 }
2608
2609 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2610 tw32(MAC_LED_CTRL, tp->led_ctrl);
2611
2612 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2613 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2614 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2615 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2616 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2617 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2618
2619 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2620 mac_mode |= tp->mac_mode &
2621 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2622 if (mac_mode & MAC_MODE_APE_TX_EN)
2623 mac_mode |= MAC_MODE_TDE_ENABLE;
2624 }
2625
2626 tw32_f(MAC_MODE, mac_mode);
2627 udelay(100);
2628
2629 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2630 udelay(10);
2631 }
2632
2633 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2634 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2635 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2636 u32 base_val;
2637
2638 base_val = tp->pci_clock_ctrl;
2639 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2640 CLOCK_CTRL_TXCLK_DISABLE);
2641
2642 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2643 CLOCK_CTRL_PWRDOWN_PLL133, 40);
2644 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2645 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2646 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2647 /* do nothing */
2648 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2649 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2650 u32 newbits1, newbits2;
2651
2652 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2653 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2654 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2655 CLOCK_CTRL_TXCLK_DISABLE |
2656 CLOCK_CTRL_ALTCLK);
2657 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2658 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2659 newbits1 = CLOCK_CTRL_625_CORE;
2660 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2661 } else {
2662 newbits1 = CLOCK_CTRL_ALTCLK;
2663 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2664 }
2665
2666 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2667 40);
2668
2669 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2670 40);
2671
2672 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2673 u32 newbits3;
2674
2675 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2676 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2677 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2678 CLOCK_CTRL_TXCLK_DISABLE |
2679 CLOCK_CTRL_44MHZ_CORE);
2680 } else {
2681 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2682 }
2683
2684 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2685 tp->pci_clock_ctrl | newbits3, 40);
2686 }
2687 }
2688
2689 if (!(device_should_wake) &&
2690 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2691 tg3_power_down_phy(tp, do_low_power);
2692
2693 tg3_frob_aux_power(tp);
2694
2695 /* Workaround for unstable PLL clock */
2696 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2697 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2698 u32 val = tr32(0x7d00);
2699
2700 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2701 tw32(0x7d00, val);
2702 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2703 int err;
2704
2705 err = tg3_nvram_lock(tp);
2706 tg3_halt_cpu(tp, RX_CPU_BASE);
2707 if (!err)
2708 tg3_nvram_unlock(tp);
2709 }
2710 }
2711
2712 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2713
2714 if (device_should_wake)
2715 pci_enable_wake(tp->pdev, state, true);
2716
2717 /* Finally, set the new power state. */
2718 pci_set_power_state(tp->pdev, state);
2719
2720 return 0;
2721 }
2722
2723 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2724 {
2725 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2726 case MII_TG3_AUX_STAT_10HALF:
2727 *speed = SPEED_10;
2728 *duplex = DUPLEX_HALF;
2729 break;
2730
2731 case MII_TG3_AUX_STAT_10FULL:
2732 *speed = SPEED_10;
2733 *duplex = DUPLEX_FULL;
2734 break;
2735
2736 case MII_TG3_AUX_STAT_100HALF:
2737 *speed = SPEED_100;
2738 *duplex = DUPLEX_HALF;
2739 break;
2740
2741 case MII_TG3_AUX_STAT_100FULL:
2742 *speed = SPEED_100;
2743 *duplex = DUPLEX_FULL;
2744 break;
2745
2746 case MII_TG3_AUX_STAT_1000HALF:
2747 *speed = SPEED_1000;
2748 *duplex = DUPLEX_HALF;
2749 break;
2750
2751 case MII_TG3_AUX_STAT_1000FULL:
2752 *speed = SPEED_1000;
2753 *duplex = DUPLEX_FULL;
2754 break;
2755
2756 default:
2757 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2758 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2759 SPEED_10;
2760 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2761 DUPLEX_HALF;
2762 break;
2763 }
2764 *speed = SPEED_INVALID;
2765 *duplex = DUPLEX_INVALID;
2766 break;
2767 }
2768 }
2769
2770 static void tg3_phy_copper_begin(struct tg3 *tp)
2771 {
2772 u32 new_adv;
2773 int i;
2774
2775 if (tp->link_config.phy_is_low_power) {
2776 /* Entering low power mode. Disable gigabit and
2777 * 100baseT advertisements.
2778 */
2779 tg3_writephy(tp, MII_TG3_CTRL, 0);
2780
2781 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2782 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2783 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2784 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2785
2786 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2787 } else if (tp->link_config.speed == SPEED_INVALID) {
2788 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2789 tp->link_config.advertising &=
2790 ~(ADVERTISED_1000baseT_Half |
2791 ADVERTISED_1000baseT_Full);
2792
2793 new_adv = ADVERTISE_CSMA;
2794 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2795 new_adv |= ADVERTISE_10HALF;
2796 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2797 new_adv |= ADVERTISE_10FULL;
2798 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2799 new_adv |= ADVERTISE_100HALF;
2800 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2801 new_adv |= ADVERTISE_100FULL;
2802
2803 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2804
2805 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2806
2807 if (tp->link_config.advertising &
2808 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2809 new_adv = 0;
2810 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2811 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2812 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2813 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2814 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2815 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2816 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2817 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2818 MII_TG3_CTRL_ENABLE_AS_MASTER);
2819 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2820 } else {
2821 tg3_writephy(tp, MII_TG3_CTRL, 0);
2822 }
2823 } else {
2824 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2825 new_adv |= ADVERTISE_CSMA;
2826
2827 /* Asking for a specific link mode. */
2828 if (tp->link_config.speed == SPEED_1000) {
2829 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2830
2831 if (tp->link_config.duplex == DUPLEX_FULL)
2832 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2833 else
2834 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2835 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2836 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2837 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2838 MII_TG3_CTRL_ENABLE_AS_MASTER);
2839 } else {
2840 if (tp->link_config.speed == SPEED_100) {
2841 if (tp->link_config.duplex == DUPLEX_FULL)
2842 new_adv |= ADVERTISE_100FULL;
2843 else
2844 new_adv |= ADVERTISE_100HALF;
2845 } else {
2846 if (tp->link_config.duplex == DUPLEX_FULL)
2847 new_adv |= ADVERTISE_10FULL;
2848 else
2849 new_adv |= ADVERTISE_10HALF;
2850 }
2851 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2852
2853 new_adv = 0;
2854 }
2855
2856 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2857 }
2858
2859 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2860 tp->link_config.speed != SPEED_INVALID) {
2861 u32 bmcr, orig_bmcr;
2862
2863 tp->link_config.active_speed = tp->link_config.speed;
2864 tp->link_config.active_duplex = tp->link_config.duplex;
2865
2866 bmcr = 0;
2867 switch (tp->link_config.speed) {
2868 default:
2869 case SPEED_10:
2870 break;
2871
2872 case SPEED_100:
2873 bmcr |= BMCR_SPEED100;
2874 break;
2875
2876 case SPEED_1000:
2877 bmcr |= TG3_BMCR_SPEED1000;
2878 break;
2879 }
2880
2881 if (tp->link_config.duplex == DUPLEX_FULL)
2882 bmcr |= BMCR_FULLDPLX;
2883
2884 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2885 (bmcr != orig_bmcr)) {
2886 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2887 for (i = 0; i < 1500; i++) {
2888 u32 tmp;
2889
2890 udelay(10);
2891 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2892 tg3_readphy(tp, MII_BMSR, &tmp))
2893 continue;
2894 if (!(tmp & BMSR_LSTATUS)) {
2895 udelay(40);
2896 break;
2897 }
2898 }
2899 tg3_writephy(tp, MII_BMCR, bmcr);
2900 udelay(40);
2901 }
2902 } else {
2903 tg3_writephy(tp, MII_BMCR,
2904 BMCR_ANENABLE | BMCR_ANRESTART);
2905 }
2906 }
2907
2908 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2909 {
2910 int err;
2911
2912 /* Turn off tap power management. */
2913 /* Set Extended packet length bit */
2914 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2915
2916 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2917 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2918
2919 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2920 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2921
2922 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2923 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2924
2925 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2926 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2927
2928 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2929 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2930
2931 udelay(40);
2932
2933 return err;
2934 }
2935
2936 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2937 {
2938 u32 adv_reg, all_mask = 0;
2939
2940 if (mask & ADVERTISED_10baseT_Half)
2941 all_mask |= ADVERTISE_10HALF;
2942 if (mask & ADVERTISED_10baseT_Full)
2943 all_mask |= ADVERTISE_10FULL;
2944 if (mask & ADVERTISED_100baseT_Half)
2945 all_mask |= ADVERTISE_100HALF;
2946 if (mask & ADVERTISED_100baseT_Full)
2947 all_mask |= ADVERTISE_100FULL;
2948
2949 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2950 return 0;
2951
2952 if ((adv_reg & all_mask) != all_mask)
2953 return 0;
2954 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2955 u32 tg3_ctrl;
2956
2957 all_mask = 0;
2958 if (mask & ADVERTISED_1000baseT_Half)
2959 all_mask |= ADVERTISE_1000HALF;
2960 if (mask & ADVERTISED_1000baseT_Full)
2961 all_mask |= ADVERTISE_1000FULL;
2962
2963 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2964 return 0;
2965
2966 if ((tg3_ctrl & all_mask) != all_mask)
2967 return 0;
2968 }
2969 return 1;
2970 }
2971
2972 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2973 {
2974 u32 curadv, reqadv;
2975
2976 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2977 return 1;
2978
2979 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2980 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2981
2982 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2983 if (curadv != reqadv)
2984 return 0;
2985
2986 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2987 tg3_readphy(tp, MII_LPA, rmtadv);
2988 } else {
2989 /* Reprogram the advertisement register, even if it
2990 * does not affect the current link. If the link
2991 * gets renegotiated in the future, we can save an
2992 * additional renegotiation cycle by advertising
2993 * it correctly in the first place.
2994 */
2995 if (curadv != reqadv) {
2996 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2997 ADVERTISE_PAUSE_ASYM);
2998 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2999 }
3000 }
3001
3002 return 1;
3003 }
3004
3005 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3006 {
3007 int current_link_up;
3008 u32 bmsr, dummy;
3009 u32 lcl_adv, rmt_adv;
3010 u16 current_speed;
3011 u8 current_duplex;
3012 int i, err;
3013
3014 tw32(MAC_EVENT, 0);
3015
3016 tw32_f(MAC_STATUS,
3017 (MAC_STATUS_SYNC_CHANGED |
3018 MAC_STATUS_CFG_CHANGED |
3019 MAC_STATUS_MI_COMPLETION |
3020 MAC_STATUS_LNKSTATE_CHANGED));
3021 udelay(40);
3022
3023 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3024 tw32_f(MAC_MI_MODE,
3025 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3026 udelay(80);
3027 }
3028
3029 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3030
3031 /* Some third-party PHYs need to be reset on link going
3032 * down.
3033 */
3034 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3035 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3036 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3037 netif_carrier_ok(tp->dev)) {
3038 tg3_readphy(tp, MII_BMSR, &bmsr);
3039 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3040 !(bmsr & BMSR_LSTATUS))
3041 force_reset = 1;
3042 }
3043 if (force_reset)
3044 tg3_phy_reset(tp);
3045
3046 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3047 tg3_readphy(tp, MII_BMSR, &bmsr);
3048 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3049 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3050 bmsr = 0;
3051
3052 if (!(bmsr & BMSR_LSTATUS)) {
3053 err = tg3_init_5401phy_dsp(tp);
3054 if (err)
3055 return err;
3056
3057 tg3_readphy(tp, MII_BMSR, &bmsr);
3058 for (i = 0; i < 1000; i++) {
3059 udelay(10);
3060 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3061 (bmsr & BMSR_LSTATUS)) {
3062 udelay(40);
3063 break;
3064 }
3065 }
3066
3067 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3068 !(bmsr & BMSR_LSTATUS) &&
3069 tp->link_config.active_speed == SPEED_1000) {
3070 err = tg3_phy_reset(tp);
3071 if (!err)
3072 err = tg3_init_5401phy_dsp(tp);
3073 if (err)
3074 return err;
3075 }
3076 }
3077 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3078 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3079 /* 5701 {A0,B0} CRC bug workaround */
3080 tg3_writephy(tp, 0x15, 0x0a75);
3081 tg3_writephy(tp, 0x1c, 0x8c68);
3082 tg3_writephy(tp, 0x1c, 0x8d68);
3083 tg3_writephy(tp, 0x1c, 0x8c68);
3084 }
3085
3086 /* Clear pending interrupts... */
3087 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3088 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3089
3090 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3091 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3092 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3093 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3094
3095 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3096 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3097 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3098 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3099 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3100 else
3101 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3102 }
3103
3104 current_link_up = 0;
3105 current_speed = SPEED_INVALID;
3106 current_duplex = DUPLEX_INVALID;
3107
3108 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3109 u32 val;
3110
3111 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3112 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3113 if (!(val & (1 << 10))) {
3114 val |= (1 << 10);
3115 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3116 goto relink;
3117 }
3118 }
3119
3120 bmsr = 0;
3121 for (i = 0; i < 100; i++) {
3122 tg3_readphy(tp, MII_BMSR, &bmsr);
3123 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3124 (bmsr & BMSR_LSTATUS))
3125 break;
3126 udelay(40);
3127 }
3128
3129 if (bmsr & BMSR_LSTATUS) {
3130 u32 aux_stat, bmcr;
3131
3132 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3133 for (i = 0; i < 2000; i++) {
3134 udelay(10);
3135 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3136 aux_stat)
3137 break;
3138 }
3139
3140 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3141 &current_speed,
3142 &current_duplex);
3143
3144 bmcr = 0;
3145 for (i = 0; i < 200; i++) {
3146 tg3_readphy(tp, MII_BMCR, &bmcr);
3147 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3148 continue;
3149 if (bmcr && bmcr != 0x7fff)
3150 break;
3151 udelay(10);
3152 }
3153
3154 lcl_adv = 0;
3155 rmt_adv = 0;
3156
3157 tp->link_config.active_speed = current_speed;
3158 tp->link_config.active_duplex = current_duplex;
3159
3160 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3161 if ((bmcr & BMCR_ANENABLE) &&
3162 tg3_copper_is_advertising_all(tp,
3163 tp->link_config.advertising)) {
3164 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3165 &rmt_adv))
3166 current_link_up = 1;
3167 }
3168 } else {
3169 if (!(bmcr & BMCR_ANENABLE) &&
3170 tp->link_config.speed == current_speed &&
3171 tp->link_config.duplex == current_duplex &&
3172 tp->link_config.flowctrl ==
3173 tp->link_config.active_flowctrl) {
3174 current_link_up = 1;
3175 }
3176 }
3177
3178 if (current_link_up == 1 &&
3179 tp->link_config.active_duplex == DUPLEX_FULL)
3180 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3181 }
3182
3183 relink:
3184 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3185 u32 tmp;
3186
3187 tg3_phy_copper_begin(tp);
3188
3189 tg3_readphy(tp, MII_BMSR, &tmp);
3190 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3191 (tmp & BMSR_LSTATUS))
3192 current_link_up = 1;
3193 }
3194
3195 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3196 if (current_link_up == 1) {
3197 if (tp->link_config.active_speed == SPEED_100 ||
3198 tp->link_config.active_speed == SPEED_10)
3199 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3200 else
3201 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3202 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3203 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3204 else
3205 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3206
3207 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3208 if (tp->link_config.active_duplex == DUPLEX_HALF)
3209 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3210
3211 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3212 if (current_link_up == 1 &&
3213 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3214 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3215 else
3216 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3217 }
3218
3219 /* ??? Without this setting Netgear GA302T PHY does not
3220 * ??? send/receive packets...
3221 */
3222 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3223 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3224 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3225 tw32_f(MAC_MI_MODE, tp->mi_mode);
3226 udelay(80);
3227 }
3228
3229 tw32_f(MAC_MODE, tp->mac_mode);
3230 udelay(40);
3231
3232 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3233 /* Polled via timer. */
3234 tw32_f(MAC_EVENT, 0);
3235 } else {
3236 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3237 }
3238 udelay(40);
3239
3240 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3241 current_link_up == 1 &&
3242 tp->link_config.active_speed == SPEED_1000 &&
3243 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3244 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3245 udelay(120);
3246 tw32_f(MAC_STATUS,
3247 (MAC_STATUS_SYNC_CHANGED |
3248 MAC_STATUS_CFG_CHANGED));
3249 udelay(40);
3250 tg3_write_mem(tp,
3251 NIC_SRAM_FIRMWARE_MBOX,
3252 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3253 }
3254
3255 /* Prevent send BD corruption. */
3256 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3257 u16 oldlnkctl, newlnkctl;
3258
3259 pci_read_config_word(tp->pdev,
3260 tp->pcie_cap + PCI_EXP_LNKCTL,
3261 &oldlnkctl);
3262 if (tp->link_config.active_speed == SPEED_100 ||
3263 tp->link_config.active_speed == SPEED_10)
3264 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3265 else
3266 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3267 if (newlnkctl != oldlnkctl)
3268 pci_write_config_word(tp->pdev,
3269 tp->pcie_cap + PCI_EXP_LNKCTL,
3270 newlnkctl);
3271 }
3272
3273 if (current_link_up != netif_carrier_ok(tp->dev)) {
3274 if (current_link_up)
3275 netif_carrier_on(tp->dev);
3276 else
3277 netif_carrier_off(tp->dev);
3278 tg3_link_report(tp);
3279 }
3280
3281 return 0;
3282 }
3283
3284 struct tg3_fiber_aneginfo {
3285 int state;
3286 #define ANEG_STATE_UNKNOWN 0
3287 #define ANEG_STATE_AN_ENABLE 1
3288 #define ANEG_STATE_RESTART_INIT 2
3289 #define ANEG_STATE_RESTART 3
3290 #define ANEG_STATE_DISABLE_LINK_OK 4
3291 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3292 #define ANEG_STATE_ABILITY_DETECT 6
3293 #define ANEG_STATE_ACK_DETECT_INIT 7
3294 #define ANEG_STATE_ACK_DETECT 8
3295 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3296 #define ANEG_STATE_COMPLETE_ACK 10
3297 #define ANEG_STATE_IDLE_DETECT_INIT 11
3298 #define ANEG_STATE_IDLE_DETECT 12
3299 #define ANEG_STATE_LINK_OK 13
3300 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3301 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3302
3303 u32 flags;
3304 #define MR_AN_ENABLE 0x00000001
3305 #define MR_RESTART_AN 0x00000002
3306 #define MR_AN_COMPLETE 0x00000004
3307 #define MR_PAGE_RX 0x00000008
3308 #define MR_NP_LOADED 0x00000010
3309 #define MR_TOGGLE_TX 0x00000020
3310 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3311 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3312 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3313 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3314 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3315 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3316 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3317 #define MR_TOGGLE_RX 0x00002000
3318 #define MR_NP_RX 0x00004000
3319
3320 #define MR_LINK_OK 0x80000000
3321
3322 unsigned long link_time, cur_time;
3323
3324 u32 ability_match_cfg;
3325 int ability_match_count;
3326
3327 char ability_match, idle_match, ack_match;
3328
3329 u32 txconfig, rxconfig;
3330 #define ANEG_CFG_NP 0x00000080
3331 #define ANEG_CFG_ACK 0x00000040
3332 #define ANEG_CFG_RF2 0x00000020
3333 #define ANEG_CFG_RF1 0x00000010
3334 #define ANEG_CFG_PS2 0x00000001
3335 #define ANEG_CFG_PS1 0x00008000
3336 #define ANEG_CFG_HD 0x00004000
3337 #define ANEG_CFG_FD 0x00002000
3338 #define ANEG_CFG_INVAL 0x00001f06
3339
3340 };
3341 #define ANEG_OK 0
3342 #define ANEG_DONE 1
3343 #define ANEG_TIMER_ENAB 2
3344 #define ANEG_FAILED -1
3345
3346 #define ANEG_STATE_SETTLE_TIME 10000
3347
3348 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3349 struct tg3_fiber_aneginfo *ap)
3350 {
3351 u16 flowctrl;
3352 unsigned long delta;
3353 u32 rx_cfg_reg;
3354 int ret;
3355
3356 if (ap->state == ANEG_STATE_UNKNOWN) {
3357 ap->rxconfig = 0;
3358 ap->link_time = 0;
3359 ap->cur_time = 0;
3360 ap->ability_match_cfg = 0;
3361 ap->ability_match_count = 0;
3362 ap->ability_match = 0;
3363 ap->idle_match = 0;
3364 ap->ack_match = 0;
3365 }
3366 ap->cur_time++;
3367
3368 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3369 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3370
3371 if (rx_cfg_reg != ap->ability_match_cfg) {
3372 ap->ability_match_cfg = rx_cfg_reg;
3373 ap->ability_match = 0;
3374 ap->ability_match_count = 0;
3375 } else {
3376 if (++ap->ability_match_count > 1) {
3377 ap->ability_match = 1;
3378 ap->ability_match_cfg = rx_cfg_reg;
3379 }
3380 }
3381 if (rx_cfg_reg & ANEG_CFG_ACK)
3382 ap->ack_match = 1;
3383 else
3384 ap->ack_match = 0;
3385
3386 ap->idle_match = 0;
3387 } else {
3388 ap->idle_match = 1;
3389 ap->ability_match_cfg = 0;
3390 ap->ability_match_count = 0;
3391 ap->ability_match = 0;
3392 ap->ack_match = 0;
3393
3394 rx_cfg_reg = 0;
3395 }
3396
3397 ap->rxconfig = rx_cfg_reg;
3398 ret = ANEG_OK;
3399
3400 switch(ap->state) {
3401 case ANEG_STATE_UNKNOWN:
3402 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3403 ap->state = ANEG_STATE_AN_ENABLE;
3404
3405 /* fallthru */
3406 case ANEG_STATE_AN_ENABLE:
3407 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3408 if (ap->flags & MR_AN_ENABLE) {
3409 ap->link_time = 0;
3410 ap->cur_time = 0;
3411 ap->ability_match_cfg = 0;
3412 ap->ability_match_count = 0;
3413 ap->ability_match = 0;
3414 ap->idle_match = 0;
3415 ap->ack_match = 0;
3416
3417 ap->state = ANEG_STATE_RESTART_INIT;
3418 } else {
3419 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3420 }
3421 break;
3422
3423 case ANEG_STATE_RESTART_INIT:
3424 ap->link_time = ap->cur_time;
3425 ap->flags &= ~(MR_NP_LOADED);
3426 ap->txconfig = 0;
3427 tw32(MAC_TX_AUTO_NEG, 0);
3428 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3429 tw32_f(MAC_MODE, tp->mac_mode);
3430 udelay(40);
3431
3432 ret = ANEG_TIMER_ENAB;
3433 ap->state = ANEG_STATE_RESTART;
3434
3435 /* fallthru */
3436 case ANEG_STATE_RESTART:
3437 delta = ap->cur_time - ap->link_time;
3438 if (delta > ANEG_STATE_SETTLE_TIME) {
3439 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3440 } else {
3441 ret = ANEG_TIMER_ENAB;
3442 }
3443 break;
3444
3445 case ANEG_STATE_DISABLE_LINK_OK:
3446 ret = ANEG_DONE;
3447 break;
3448
3449 case ANEG_STATE_ABILITY_DETECT_INIT:
3450 ap->flags &= ~(MR_TOGGLE_TX);
3451 ap->txconfig = ANEG_CFG_FD;
3452 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3453 if (flowctrl & ADVERTISE_1000XPAUSE)
3454 ap->txconfig |= ANEG_CFG_PS1;
3455 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3456 ap->txconfig |= ANEG_CFG_PS2;
3457 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3458 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3459 tw32_f(MAC_MODE, tp->mac_mode);
3460 udelay(40);
3461
3462 ap->state = ANEG_STATE_ABILITY_DETECT;
3463 break;
3464
3465 case ANEG_STATE_ABILITY_DETECT:
3466 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3467 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3468 }
3469 break;
3470
3471 case ANEG_STATE_ACK_DETECT_INIT:
3472 ap->txconfig |= ANEG_CFG_ACK;
3473 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3474 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3475 tw32_f(MAC_MODE, tp->mac_mode);
3476 udelay(40);
3477
3478 ap->state = ANEG_STATE_ACK_DETECT;
3479
3480 /* fallthru */
3481 case ANEG_STATE_ACK_DETECT:
3482 if (ap->ack_match != 0) {
3483 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3484 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3485 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3486 } else {
3487 ap->state = ANEG_STATE_AN_ENABLE;
3488 }
3489 } else if (ap->ability_match != 0 &&
3490 ap->rxconfig == 0) {
3491 ap->state = ANEG_STATE_AN_ENABLE;
3492 }
3493 break;
3494
3495 case ANEG_STATE_COMPLETE_ACK_INIT:
3496 if (ap->rxconfig & ANEG_CFG_INVAL) {
3497 ret = ANEG_FAILED;
3498 break;
3499 }
3500 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3501 MR_LP_ADV_HALF_DUPLEX |
3502 MR_LP_ADV_SYM_PAUSE |
3503 MR_LP_ADV_ASYM_PAUSE |
3504 MR_LP_ADV_REMOTE_FAULT1 |
3505 MR_LP_ADV_REMOTE_FAULT2 |
3506 MR_LP_ADV_NEXT_PAGE |
3507 MR_TOGGLE_RX |
3508 MR_NP_RX);
3509 if (ap->rxconfig & ANEG_CFG_FD)
3510 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3511 if (ap->rxconfig & ANEG_CFG_HD)
3512 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3513 if (ap->rxconfig & ANEG_CFG_PS1)
3514 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3515 if (ap->rxconfig & ANEG_CFG_PS2)
3516 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3517 if (ap->rxconfig & ANEG_CFG_RF1)
3518 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3519 if (ap->rxconfig & ANEG_CFG_RF2)
3520 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3521 if (ap->rxconfig & ANEG_CFG_NP)
3522 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3523
3524 ap->link_time = ap->cur_time;
3525
3526 ap->flags ^= (MR_TOGGLE_TX);
3527 if (ap->rxconfig & 0x0008)
3528 ap->flags |= MR_TOGGLE_RX;
3529 if (ap->rxconfig & ANEG_CFG_NP)
3530 ap->flags |= MR_NP_RX;
3531 ap->flags |= MR_PAGE_RX;
3532
3533 ap->state = ANEG_STATE_COMPLETE_ACK;
3534 ret = ANEG_TIMER_ENAB;
3535 break;
3536
3537 case ANEG_STATE_COMPLETE_ACK:
3538 if (ap->ability_match != 0 &&
3539 ap->rxconfig == 0) {
3540 ap->state = ANEG_STATE_AN_ENABLE;
3541 break;
3542 }
3543 delta = ap->cur_time - ap->link_time;
3544 if (delta > ANEG_STATE_SETTLE_TIME) {
3545 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3546 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3547 } else {
3548 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3549 !(ap->flags & MR_NP_RX)) {
3550 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3551 } else {
3552 ret = ANEG_FAILED;
3553 }
3554 }
3555 }
3556 break;
3557
3558 case ANEG_STATE_IDLE_DETECT_INIT:
3559 ap->link_time = ap->cur_time;
3560 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3561 tw32_f(MAC_MODE, tp->mac_mode);
3562 udelay(40);
3563
3564 ap->state = ANEG_STATE_IDLE_DETECT;
3565 ret = ANEG_TIMER_ENAB;
3566 break;
3567
3568 case ANEG_STATE_IDLE_DETECT:
3569 if (ap->ability_match != 0 &&
3570 ap->rxconfig == 0) {
3571 ap->state = ANEG_STATE_AN_ENABLE;
3572 break;
3573 }
3574 delta = ap->cur_time - ap->link_time;
3575 if (delta > ANEG_STATE_SETTLE_TIME) {
3576 /* XXX another gem from the Broadcom driver :( */
3577 ap->state = ANEG_STATE_LINK_OK;
3578 }
3579 break;
3580
3581 case ANEG_STATE_LINK_OK:
3582 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3583 ret = ANEG_DONE;
3584 break;
3585
3586 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3587 /* ??? unimplemented */
3588 break;
3589
3590 case ANEG_STATE_NEXT_PAGE_WAIT:
3591 /* ??? unimplemented */
3592 break;
3593
3594 default:
3595 ret = ANEG_FAILED;
3596 break;
3597 }
3598
3599 return ret;
3600 }
3601
3602 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3603 {
3604 int res = 0;
3605 struct tg3_fiber_aneginfo aninfo;
3606 int status = ANEG_FAILED;
3607 unsigned int tick;
3608 u32 tmp;
3609
3610 tw32_f(MAC_TX_AUTO_NEG, 0);
3611
3612 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3613 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3614 udelay(40);
3615
3616 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3617 udelay(40);
3618
3619 memset(&aninfo, 0, sizeof(aninfo));
3620 aninfo.flags |= MR_AN_ENABLE;
3621 aninfo.state = ANEG_STATE_UNKNOWN;
3622 aninfo.cur_time = 0;
3623 tick = 0;
3624 while (++tick < 195000) {
3625 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3626 if (status == ANEG_DONE || status == ANEG_FAILED)
3627 break;
3628
3629 udelay(1);
3630 }
3631
3632 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3633 tw32_f(MAC_MODE, tp->mac_mode);
3634 udelay(40);
3635
3636 *txflags = aninfo.txconfig;
3637 *rxflags = aninfo.flags;
3638
3639 if (status == ANEG_DONE &&
3640 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3641 MR_LP_ADV_FULL_DUPLEX)))
3642 res = 1;
3643
3644 return res;
3645 }
3646
3647 static void tg3_init_bcm8002(struct tg3 *tp)
3648 {
3649 u32 mac_status = tr32(MAC_STATUS);
3650 int i;
3651
3652 /* Reset when initting first time or we have a link. */
3653 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3654 !(mac_status & MAC_STATUS_PCS_SYNCED))
3655 return;
3656
3657 /* Set PLL lock range. */
3658 tg3_writephy(tp, 0x16, 0x8007);
3659
3660 /* SW reset */
3661 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3662
3663 /* Wait for reset to complete. */
3664 /* XXX schedule_timeout() ... */
3665 for (i = 0; i < 500; i++)
3666 udelay(10);
3667
3668 /* Config mode; select PMA/Ch 1 regs. */
3669 tg3_writephy(tp, 0x10, 0x8411);
3670
3671 /* Enable auto-lock and comdet, select txclk for tx. */
3672 tg3_writephy(tp, 0x11, 0x0a10);
3673
3674 tg3_writephy(tp, 0x18, 0x00a0);
3675 tg3_writephy(tp, 0x16, 0x41ff);
3676
3677 /* Assert and deassert POR. */
3678 tg3_writephy(tp, 0x13, 0x0400);
3679 udelay(40);
3680 tg3_writephy(tp, 0x13, 0x0000);
3681
3682 tg3_writephy(tp, 0x11, 0x0a50);
3683 udelay(40);
3684 tg3_writephy(tp, 0x11, 0x0a10);
3685
3686 /* Wait for signal to stabilize */
3687 /* XXX schedule_timeout() ... */
3688 for (i = 0; i < 15000; i++)
3689 udelay(10);
3690
3691 /* Deselect the channel register so we can read the PHYID
3692 * later.
3693 */
3694 tg3_writephy(tp, 0x10, 0x8011);
3695 }
3696
3697 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3698 {
3699 u16 flowctrl;
3700 u32 sg_dig_ctrl, sg_dig_status;
3701 u32 serdes_cfg, expected_sg_dig_ctrl;
3702 int workaround, port_a;
3703 int current_link_up;
3704
3705 serdes_cfg = 0;
3706 expected_sg_dig_ctrl = 0;
3707 workaround = 0;
3708 port_a = 1;
3709 current_link_up = 0;
3710
3711 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3712 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3713 workaround = 1;
3714 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3715 port_a = 0;
3716
3717 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3718 /* preserve bits 20-23 for voltage regulator */
3719 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3720 }
3721
3722 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3723
3724 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3725 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3726 if (workaround) {
3727 u32 val = serdes_cfg;
3728
3729 if (port_a)
3730 val |= 0xc010000;
3731 else
3732 val |= 0x4010000;
3733 tw32_f(MAC_SERDES_CFG, val);
3734 }
3735
3736 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3737 }
3738 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3739 tg3_setup_flow_control(tp, 0, 0);
3740 current_link_up = 1;
3741 }
3742 goto out;
3743 }
3744
3745 /* Want auto-negotiation. */
3746 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3747
3748 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3749 if (flowctrl & ADVERTISE_1000XPAUSE)
3750 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3751 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3752 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3753
3754 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3755 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3756 tp->serdes_counter &&
3757 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3758 MAC_STATUS_RCVD_CFG)) ==
3759 MAC_STATUS_PCS_SYNCED)) {
3760 tp->serdes_counter--;
3761 current_link_up = 1;
3762 goto out;
3763 }
3764 restart_autoneg:
3765 if (workaround)
3766 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3767 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3768 udelay(5);
3769 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3770
3771 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3772 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3773 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3774 MAC_STATUS_SIGNAL_DET)) {
3775 sg_dig_status = tr32(SG_DIG_STATUS);
3776 mac_status = tr32(MAC_STATUS);
3777
3778 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3779 (mac_status & MAC_STATUS_PCS_SYNCED)) {
3780 u32 local_adv = 0, remote_adv = 0;
3781
3782 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3783 local_adv |= ADVERTISE_1000XPAUSE;
3784 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3785 local_adv |= ADVERTISE_1000XPSE_ASYM;
3786
3787 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3788 remote_adv |= LPA_1000XPAUSE;
3789 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3790 remote_adv |= LPA_1000XPAUSE_ASYM;
3791
3792 tg3_setup_flow_control(tp, local_adv, remote_adv);
3793 current_link_up = 1;
3794 tp->serdes_counter = 0;
3795 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3796 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3797 if (tp->serdes_counter)
3798 tp->serdes_counter--;
3799 else {
3800 if (workaround) {
3801 u32 val = serdes_cfg;
3802
3803 if (port_a)
3804 val |= 0xc010000;
3805 else
3806 val |= 0x4010000;
3807
3808 tw32_f(MAC_SERDES_CFG, val);
3809 }
3810
3811 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3812 udelay(40);
3813
3814 /* Link parallel detection - link is up */
3815 /* only if we have PCS_SYNC and not */
3816 /* receiving config code words */
3817 mac_status = tr32(MAC_STATUS);
3818 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3819 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3820 tg3_setup_flow_control(tp, 0, 0);
3821 current_link_up = 1;
3822 tp->tg3_flags2 |=
3823 TG3_FLG2_PARALLEL_DETECT;
3824 tp->serdes_counter =
3825 SERDES_PARALLEL_DET_TIMEOUT;
3826 } else
3827 goto restart_autoneg;
3828 }
3829 }
3830 } else {
3831 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3832 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3833 }
3834
3835 out:
3836 return current_link_up;
3837 }
3838
3839 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3840 {
3841 int current_link_up = 0;
3842
3843 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3844 goto out;
3845
3846 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3847 u32 txflags, rxflags;
3848 int i;
3849
3850 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3851 u32 local_adv = 0, remote_adv = 0;
3852
3853 if (txflags & ANEG_CFG_PS1)
3854 local_adv |= ADVERTISE_1000XPAUSE;
3855 if (txflags & ANEG_CFG_PS2)
3856 local_adv |= ADVERTISE_1000XPSE_ASYM;
3857
3858 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3859 remote_adv |= LPA_1000XPAUSE;
3860 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3861 remote_adv |= LPA_1000XPAUSE_ASYM;
3862
3863 tg3_setup_flow_control(tp, local_adv, remote_adv);
3864
3865 current_link_up = 1;
3866 }
3867 for (i = 0; i < 30; i++) {
3868 udelay(20);
3869 tw32_f(MAC_STATUS,
3870 (MAC_STATUS_SYNC_CHANGED |
3871 MAC_STATUS_CFG_CHANGED));
3872 udelay(40);
3873 if ((tr32(MAC_STATUS) &
3874 (MAC_STATUS_SYNC_CHANGED |
3875 MAC_STATUS_CFG_CHANGED)) == 0)
3876 break;
3877 }
3878
3879 mac_status = tr32(MAC_STATUS);
3880 if (current_link_up == 0 &&
3881 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3882 !(mac_status & MAC_STATUS_RCVD_CFG))
3883 current_link_up = 1;
3884 } else {
3885 tg3_setup_flow_control(tp, 0, 0);
3886
3887 /* Forcing 1000FD link up. */
3888 current_link_up = 1;
3889
3890 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3891 udelay(40);
3892
3893 tw32_f(MAC_MODE, tp->mac_mode);
3894 udelay(40);
3895 }
3896
3897 out:
3898 return current_link_up;
3899 }
3900
3901 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3902 {
3903 u32 orig_pause_cfg;
3904 u16 orig_active_speed;
3905 u8 orig_active_duplex;
3906 u32 mac_status;
3907 int current_link_up;
3908 int i;
3909
3910 orig_pause_cfg = tp->link_config.active_flowctrl;
3911 orig_active_speed = tp->link_config.active_speed;
3912 orig_active_duplex = tp->link_config.active_duplex;
3913
3914 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3915 netif_carrier_ok(tp->dev) &&
3916 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3917 mac_status = tr32(MAC_STATUS);
3918 mac_status &= (MAC_STATUS_PCS_SYNCED |
3919 MAC_STATUS_SIGNAL_DET |
3920 MAC_STATUS_CFG_CHANGED |
3921 MAC_STATUS_RCVD_CFG);
3922 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3923 MAC_STATUS_SIGNAL_DET)) {
3924 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3925 MAC_STATUS_CFG_CHANGED));
3926 return 0;
3927 }
3928 }
3929
3930 tw32_f(MAC_TX_AUTO_NEG, 0);
3931
3932 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3933 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3934 tw32_f(MAC_MODE, tp->mac_mode);
3935 udelay(40);
3936
3937 if (tp->phy_id == PHY_ID_BCM8002)
3938 tg3_init_bcm8002(tp);
3939
3940 /* Enable link change event even when serdes polling. */
3941 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3942 udelay(40);
3943
3944 current_link_up = 0;
3945 mac_status = tr32(MAC_STATUS);
3946
3947 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3948 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3949 else
3950 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3951
3952 tp->napi[0].hw_status->status =
3953 (SD_STATUS_UPDATED |
3954 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3955
3956 for (i = 0; i < 100; i++) {
3957 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3958 MAC_STATUS_CFG_CHANGED));
3959 udelay(5);
3960 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3961 MAC_STATUS_CFG_CHANGED |
3962 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3963 break;
3964 }
3965
3966 mac_status = tr32(MAC_STATUS);
3967 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3968 current_link_up = 0;
3969 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3970 tp->serdes_counter == 0) {
3971 tw32_f(MAC_MODE, (tp->mac_mode |
3972 MAC_MODE_SEND_CONFIGS));
3973 udelay(1);
3974 tw32_f(MAC_MODE, tp->mac_mode);
3975 }
3976 }
3977
3978 if (current_link_up == 1) {
3979 tp->link_config.active_speed = SPEED_1000;
3980 tp->link_config.active_duplex = DUPLEX_FULL;
3981 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3982 LED_CTRL_LNKLED_OVERRIDE |
3983 LED_CTRL_1000MBPS_ON));
3984 } else {
3985 tp->link_config.active_speed = SPEED_INVALID;
3986 tp->link_config.active_duplex = DUPLEX_INVALID;
3987 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3988 LED_CTRL_LNKLED_OVERRIDE |
3989 LED_CTRL_TRAFFIC_OVERRIDE));
3990 }
3991
3992 if (current_link_up != netif_carrier_ok(tp->dev)) {
3993 if (current_link_up)
3994 netif_carrier_on(tp->dev);
3995 else
3996 netif_carrier_off(tp->dev);
3997 tg3_link_report(tp);
3998 } else {
3999 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4000 if (orig_pause_cfg != now_pause_cfg ||
4001 orig_active_speed != tp->link_config.active_speed ||
4002 orig_active_duplex != tp->link_config.active_duplex)
4003 tg3_link_report(tp);
4004 }
4005
4006 return 0;
4007 }
4008
4009 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4010 {
4011 int current_link_up, err = 0;
4012 u32 bmsr, bmcr;
4013 u16 current_speed;
4014 u8 current_duplex;
4015 u32 local_adv, remote_adv;
4016
4017 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4018 tw32_f(MAC_MODE, tp->mac_mode);
4019 udelay(40);
4020
4021 tw32(MAC_EVENT, 0);
4022
4023 tw32_f(MAC_STATUS,
4024 (MAC_STATUS_SYNC_CHANGED |
4025 MAC_STATUS_CFG_CHANGED |
4026 MAC_STATUS_MI_COMPLETION |
4027 MAC_STATUS_LNKSTATE_CHANGED));
4028 udelay(40);
4029
4030 if (force_reset)
4031 tg3_phy_reset(tp);
4032
4033 current_link_up = 0;
4034 current_speed = SPEED_INVALID;
4035 current_duplex = DUPLEX_INVALID;
4036
4037 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4038 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4039 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4040 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4041 bmsr |= BMSR_LSTATUS;
4042 else
4043 bmsr &= ~BMSR_LSTATUS;
4044 }
4045
4046 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4047
4048 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4049 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4050 /* do nothing, just check for link up at the end */
4051 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4052 u32 adv, new_adv;
4053
4054 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4055 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4056 ADVERTISE_1000XPAUSE |
4057 ADVERTISE_1000XPSE_ASYM |
4058 ADVERTISE_SLCT);
4059
4060 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4061
4062 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4063 new_adv |= ADVERTISE_1000XHALF;
4064 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4065 new_adv |= ADVERTISE_1000XFULL;
4066
4067 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4068 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4069 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4070 tg3_writephy(tp, MII_BMCR, bmcr);
4071
4072 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4073 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4074 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4075
4076 return err;
4077 }
4078 } else {
4079 u32 new_bmcr;
4080
4081 bmcr &= ~BMCR_SPEED1000;
4082 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4083
4084 if (tp->link_config.duplex == DUPLEX_FULL)
4085 new_bmcr |= BMCR_FULLDPLX;
4086
4087 if (new_bmcr != bmcr) {
4088 /* BMCR_SPEED1000 is a reserved bit that needs
4089 * to be set on write.
4090 */
4091 new_bmcr |= BMCR_SPEED1000;
4092
4093 /* Force a linkdown */
4094 if (netif_carrier_ok(tp->dev)) {
4095 u32 adv;
4096
4097 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4098 adv &= ~(ADVERTISE_1000XFULL |
4099 ADVERTISE_1000XHALF |
4100 ADVERTISE_SLCT);
4101 tg3_writephy(tp, MII_ADVERTISE, adv);
4102 tg3_writephy(tp, MII_BMCR, bmcr |
4103 BMCR_ANRESTART |
4104 BMCR_ANENABLE);
4105 udelay(10);
4106 netif_carrier_off(tp->dev);
4107 }
4108 tg3_writephy(tp, MII_BMCR, new_bmcr);
4109 bmcr = new_bmcr;
4110 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4111 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4112 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4113 ASIC_REV_5714) {
4114 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4115 bmsr |= BMSR_LSTATUS;
4116 else
4117 bmsr &= ~BMSR_LSTATUS;
4118 }
4119 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4120 }
4121 }
4122
4123 if (bmsr & BMSR_LSTATUS) {
4124 current_speed = SPEED_1000;
4125 current_link_up = 1;
4126 if (bmcr & BMCR_FULLDPLX)
4127 current_duplex = DUPLEX_FULL;
4128 else
4129 current_duplex = DUPLEX_HALF;
4130
4131 local_adv = 0;
4132 remote_adv = 0;
4133
4134 if (bmcr & BMCR_ANENABLE) {
4135 u32 common;
4136
4137 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4138 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4139 common = local_adv & remote_adv;
4140 if (common & (ADVERTISE_1000XHALF |
4141 ADVERTISE_1000XFULL)) {
4142 if (common & ADVERTISE_1000XFULL)
4143 current_duplex = DUPLEX_FULL;
4144 else
4145 current_duplex = DUPLEX_HALF;
4146 }
4147 else
4148 current_link_up = 0;
4149 }
4150 }
4151
4152 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4153 tg3_setup_flow_control(tp, local_adv, remote_adv);
4154
4155 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4156 if (tp->link_config.active_duplex == DUPLEX_HALF)
4157 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4158
4159 tw32_f(MAC_MODE, tp->mac_mode);
4160 udelay(40);
4161
4162 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4163
4164 tp->link_config.active_speed = current_speed;
4165 tp->link_config.active_duplex = current_duplex;
4166
4167 if (current_link_up != netif_carrier_ok(tp->dev)) {
4168 if (current_link_up)
4169 netif_carrier_on(tp->dev);
4170 else {
4171 netif_carrier_off(tp->dev);
4172 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4173 }
4174 tg3_link_report(tp);
4175 }
4176 return err;
4177 }
4178
4179 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4180 {
4181 if (tp->serdes_counter) {
4182 /* Give autoneg time to complete. */
4183 tp->serdes_counter--;
4184 return;
4185 }
4186 if (!netif_carrier_ok(tp->dev) &&
4187 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4188 u32 bmcr;
4189
4190 tg3_readphy(tp, MII_BMCR, &bmcr);
4191 if (bmcr & BMCR_ANENABLE) {
4192 u32 phy1, phy2;
4193
4194 /* Select shadow register 0x1f */
4195 tg3_writephy(tp, 0x1c, 0x7c00);
4196 tg3_readphy(tp, 0x1c, &phy1);
4197
4198 /* Select expansion interrupt status register */
4199 tg3_writephy(tp, 0x17, 0x0f01);
4200 tg3_readphy(tp, 0x15, &phy2);
4201 tg3_readphy(tp, 0x15, &phy2);
4202
4203 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4204 /* We have signal detect and not receiving
4205 * config code words, link is up by parallel
4206 * detection.
4207 */
4208
4209 bmcr &= ~BMCR_ANENABLE;
4210 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4211 tg3_writephy(tp, MII_BMCR, bmcr);
4212 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4213 }
4214 }
4215 }
4216 else if (netif_carrier_ok(tp->dev) &&
4217 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4218 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4219 u32 phy2;
4220
4221 /* Select expansion interrupt status register */
4222 tg3_writephy(tp, 0x17, 0x0f01);
4223 tg3_readphy(tp, 0x15, &phy2);
4224 if (phy2 & 0x20) {
4225 u32 bmcr;
4226
4227 /* Config code words received, turn on autoneg. */
4228 tg3_readphy(tp, MII_BMCR, &bmcr);
4229 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4230
4231 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4232
4233 }
4234 }
4235 }
4236
4237 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4238 {
4239 int err;
4240
4241 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4242 err = tg3_setup_fiber_phy(tp, force_reset);
4243 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4244 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4245 } else {
4246 err = tg3_setup_copper_phy(tp, force_reset);
4247 }
4248
4249 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4250 u32 val, scale;
4251
4252 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4253 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4254 scale = 65;
4255 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4256 scale = 6;
4257 else
4258 scale = 12;
4259
4260 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4261 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4262 tw32(GRC_MISC_CFG, val);
4263 }
4264
4265 if (tp->link_config.active_speed == SPEED_1000 &&
4266 tp->link_config.active_duplex == DUPLEX_HALF)
4267 tw32(MAC_TX_LENGTHS,
4268 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4269 (6 << TX_LENGTHS_IPG_SHIFT) |
4270 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4271 else
4272 tw32(MAC_TX_LENGTHS,
4273 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4274 (6 << TX_LENGTHS_IPG_SHIFT) |
4275 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4276
4277 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4278 if (netif_carrier_ok(tp->dev)) {
4279 tw32(HOSTCC_STAT_COAL_TICKS,
4280 tp->coal.stats_block_coalesce_usecs);
4281 } else {
4282 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4283 }
4284 }
4285
4286 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4287 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4288 if (!netif_carrier_ok(tp->dev))
4289 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4290 tp->pwrmgmt_thresh;
4291 else
4292 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4293 tw32(PCIE_PWR_MGMT_THRESH, val);
4294 }
4295
4296 return err;
4297 }
4298
4299 /* This is called whenever we suspect that the system chipset is re-
4300 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4301 * is bogus tx completions. We try to recover by setting the
4302 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4303 * in the workqueue.
4304 */
4305 static void tg3_tx_recover(struct tg3 *tp)
4306 {
4307 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4308 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4309
4310 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4311 "mapped I/O cycles to the network device, attempting to "
4312 "recover. Please report the problem to the driver maintainer "
4313 "and include system chipset information.\n", tp->dev->name);
4314
4315 spin_lock(&tp->lock);
4316 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4317 spin_unlock(&tp->lock);
4318 }
4319
4320 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4321 {
4322 smp_mb();
4323 return tnapi->tx_pending -
4324 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4325 }
4326
4327 /* Tigon3 never reports partial packet sends. So we do not
4328 * need special logic to handle SKBs that have not had all
4329 * of their frags sent yet, like SunGEM does.
4330 */
4331 static void tg3_tx(struct tg3_napi *tnapi)
4332 {
4333 struct tg3 *tp = tnapi->tp;
4334 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4335 u32 sw_idx = tnapi->tx_cons;
4336 struct netdev_queue *txq;
4337 int index = tnapi - tp->napi;
4338
4339 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
4340 index--;
4341
4342 txq = netdev_get_tx_queue(tp->dev, index);
4343
4344 while (sw_idx != hw_idx) {
4345 struct tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
4346 struct sk_buff *skb = ri->skb;
4347 int i, tx_bug = 0;
4348
4349 if (unlikely(skb == NULL)) {
4350 tg3_tx_recover(tp);
4351 return;
4352 }
4353
4354 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
4355
4356 ri->skb = NULL;
4357
4358 sw_idx = NEXT_TX(sw_idx);
4359
4360 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4361 ri = &tnapi->tx_buffers[sw_idx];
4362 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4363 tx_bug = 1;
4364 sw_idx = NEXT_TX(sw_idx);
4365 }
4366
4367 dev_kfree_skb(skb);
4368
4369 if (unlikely(tx_bug)) {
4370 tg3_tx_recover(tp);
4371 return;
4372 }
4373 }
4374
4375 tnapi->tx_cons = sw_idx;
4376
4377 /* Need to make the tx_cons update visible to tg3_start_xmit()
4378 * before checking for netif_queue_stopped(). Without the
4379 * memory barrier, there is a small possibility that tg3_start_xmit()
4380 * will miss it and cause the queue to be stopped forever.
4381 */
4382 smp_mb();
4383
4384 if (unlikely(netif_tx_queue_stopped(txq) &&
4385 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4386 __netif_tx_lock(txq, smp_processor_id());
4387 if (netif_tx_queue_stopped(txq) &&
4388 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4389 netif_tx_wake_queue(txq);
4390 __netif_tx_unlock(txq);
4391 }
4392 }
4393
4394 /* Returns size of skb allocated or < 0 on error.
4395 *
4396 * We only need to fill in the address because the other members
4397 * of the RX descriptor are invariant, see tg3_init_rings.
4398 *
4399 * Note the purposeful assymetry of cpu vs. chip accesses. For
4400 * posting buffers we only dirty the first cache line of the RX
4401 * descriptor (containing the address). Whereas for the RX status
4402 * buffers the cpu only reads the last cacheline of the RX descriptor
4403 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4404 */
4405 static int tg3_alloc_rx_skb(struct tg3_napi *tnapi, u32 opaque_key,
4406 int src_idx, u32 dest_idx_unmasked)
4407 {
4408 struct tg3 *tp = tnapi->tp;
4409 struct tg3_rx_buffer_desc *desc;
4410 struct ring_info *map, *src_map;
4411 struct sk_buff *skb;
4412 dma_addr_t mapping;
4413 int skb_size, dest_idx;
4414 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4415
4416 src_map = NULL;
4417 switch (opaque_key) {
4418 case RXD_OPAQUE_RING_STD:
4419 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4420 desc = &tpr->rx_std[dest_idx];
4421 map = &tpr->rx_std_buffers[dest_idx];
4422 if (src_idx >= 0)
4423 src_map = &tpr->rx_std_buffers[src_idx];
4424 skb_size = tp->rx_pkt_map_sz;
4425 break;
4426
4427 case RXD_OPAQUE_RING_JUMBO:
4428 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4429 desc = &tpr->rx_jmb[dest_idx].std;
4430 map = &tpr->rx_jmb_buffers[dest_idx];
4431 if (src_idx >= 0)
4432 src_map = &tpr->rx_jmb_buffers[src_idx];
4433 skb_size = TG3_RX_JMB_MAP_SZ;
4434 break;
4435
4436 default:
4437 return -EINVAL;
4438 }
4439
4440 /* Do not overwrite any of the map or rp information
4441 * until we are sure we can commit to a new buffer.
4442 *
4443 * Callers depend upon this behavior and assume that
4444 * we leave everything unchanged if we fail.
4445 */
4446 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4447 if (skb == NULL)
4448 return -ENOMEM;
4449
4450 skb_reserve(skb, tp->rx_offset);
4451
4452 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4453 PCI_DMA_FROMDEVICE);
4454 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4455 dev_kfree_skb(skb);
4456 return -EIO;
4457 }
4458
4459 map->skb = skb;
4460 pci_unmap_addr_set(map, mapping, mapping);
4461
4462 if (src_map != NULL)
4463 src_map->skb = NULL;
4464
4465 desc->addr_hi = ((u64)mapping >> 32);
4466 desc->addr_lo = ((u64)mapping & 0xffffffff);
4467
4468 return skb_size;
4469 }
4470
4471 /* We only need to move over in the address because the other
4472 * members of the RX descriptor are invariant. See notes above
4473 * tg3_alloc_rx_skb for full details.
4474 */
4475 static void tg3_recycle_rx(struct tg3_napi *tnapi, u32 opaque_key,
4476 int src_idx, u32 dest_idx_unmasked)
4477 {
4478 struct tg3 *tp = tnapi->tp;
4479 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4480 struct ring_info *src_map, *dest_map;
4481 int dest_idx;
4482 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4483
4484 switch (opaque_key) {
4485 case RXD_OPAQUE_RING_STD:
4486 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4487 dest_desc = &tpr->rx_std[dest_idx];
4488 dest_map = &tpr->rx_std_buffers[dest_idx];
4489 src_desc = &tpr->rx_std[src_idx];
4490 src_map = &tpr->rx_std_buffers[src_idx];
4491 break;
4492
4493 case RXD_OPAQUE_RING_JUMBO:
4494 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4495 dest_desc = &tpr->rx_jmb[dest_idx].std;
4496 dest_map = &tpr->rx_jmb_buffers[dest_idx];
4497 src_desc = &tpr->rx_jmb[src_idx].std;
4498 src_map = &tpr->rx_jmb_buffers[src_idx];
4499 break;
4500
4501 default:
4502 return;
4503 }
4504
4505 dest_map->skb = src_map->skb;
4506 pci_unmap_addr_set(dest_map, mapping,
4507 pci_unmap_addr(src_map, mapping));
4508 dest_desc->addr_hi = src_desc->addr_hi;
4509 dest_desc->addr_lo = src_desc->addr_lo;
4510
4511 src_map->skb = NULL;
4512 }
4513
4514 /* The RX ring scheme is composed of multiple rings which post fresh
4515 * buffers to the chip, and one special ring the chip uses to report
4516 * status back to the host.
4517 *
4518 * The special ring reports the status of received packets to the
4519 * host. The chip does not write into the original descriptor the
4520 * RX buffer was obtained from. The chip simply takes the original
4521 * descriptor as provided by the host, updates the status and length
4522 * field, then writes this into the next status ring entry.
4523 *
4524 * Each ring the host uses to post buffers to the chip is described
4525 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4526 * it is first placed into the on-chip ram. When the packet's length
4527 * is known, it walks down the TG3_BDINFO entries to select the ring.
4528 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4529 * which is within the range of the new packet's length is chosen.
4530 *
4531 * The "separate ring for rx status" scheme may sound queer, but it makes
4532 * sense from a cache coherency perspective. If only the host writes
4533 * to the buffer post rings, and only the chip writes to the rx status
4534 * rings, then cache lines never move beyond shared-modified state.
4535 * If both the host and chip were to write into the same ring, cache line
4536 * eviction could occur since both entities want it in an exclusive state.
4537 */
4538 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4539 {
4540 struct tg3 *tp = tnapi->tp;
4541 u32 work_mask, rx_std_posted = 0;
4542 u32 sw_idx = tnapi->rx_rcb_ptr;
4543 u16 hw_idx;
4544 int received;
4545 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4546
4547 hw_idx = *(tnapi->rx_rcb_prod_idx);
4548 /*
4549 * We need to order the read of hw_idx and the read of
4550 * the opaque cookie.
4551 */
4552 rmb();
4553 work_mask = 0;
4554 received = 0;
4555 while (sw_idx != hw_idx && budget > 0) {
4556 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4557 unsigned int len;
4558 struct sk_buff *skb;
4559 dma_addr_t dma_addr;
4560 u32 opaque_key, desc_idx, *post_ptr;
4561
4562 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4563 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4564 if (opaque_key == RXD_OPAQUE_RING_STD) {
4565 struct ring_info *ri = &tpr->rx_std_buffers[desc_idx];
4566 dma_addr = pci_unmap_addr(ri, mapping);
4567 skb = ri->skb;
4568 post_ptr = &tpr->rx_std_ptr;
4569 rx_std_posted++;
4570 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4571 struct ring_info *ri = &tpr->rx_jmb_buffers[desc_idx];
4572 dma_addr = pci_unmap_addr(ri, mapping);
4573 skb = ri->skb;
4574 post_ptr = &tpr->rx_jmb_ptr;
4575 } else
4576 goto next_pkt_nopost;
4577
4578 work_mask |= opaque_key;
4579
4580 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4581 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4582 drop_it:
4583 tg3_recycle_rx(tnapi, opaque_key,
4584 desc_idx, *post_ptr);
4585 drop_it_no_recycle:
4586 /* Other statistics kept track of by card. */
4587 tp->net_stats.rx_dropped++;
4588 goto next_pkt;
4589 }
4590
4591 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4592 ETH_FCS_LEN;
4593
4594 if (len > RX_COPY_THRESHOLD
4595 && tp->rx_offset == NET_IP_ALIGN
4596 /* rx_offset will likely not equal NET_IP_ALIGN
4597 * if this is a 5701 card running in PCI-X mode
4598 * [see tg3_get_invariants()]
4599 */
4600 ) {
4601 int skb_size;
4602
4603 skb_size = tg3_alloc_rx_skb(tnapi, opaque_key,
4604 desc_idx, *post_ptr);
4605 if (skb_size < 0)
4606 goto drop_it;
4607
4608 pci_unmap_single(tp->pdev, dma_addr, skb_size,
4609 PCI_DMA_FROMDEVICE);
4610
4611 skb_put(skb, len);
4612 } else {
4613 struct sk_buff *copy_skb;
4614
4615 tg3_recycle_rx(tnapi, opaque_key,
4616 desc_idx, *post_ptr);
4617
4618 copy_skb = netdev_alloc_skb(tp->dev,
4619 len + TG3_RAW_IP_ALIGN);
4620 if (copy_skb == NULL)
4621 goto drop_it_no_recycle;
4622
4623 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4624 skb_put(copy_skb, len);
4625 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4626 skb_copy_from_linear_data(skb, copy_skb->data, len);
4627 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4628
4629 /* We'll reuse the original ring buffer. */
4630 skb = copy_skb;
4631 }
4632
4633 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4634 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4635 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4636 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4637 skb->ip_summed = CHECKSUM_UNNECESSARY;
4638 else
4639 skb->ip_summed = CHECKSUM_NONE;
4640
4641 skb->protocol = eth_type_trans(skb, tp->dev);
4642
4643 if (len > (tp->dev->mtu + ETH_HLEN) &&
4644 skb->protocol != htons(ETH_P_8021Q)) {
4645 dev_kfree_skb(skb);
4646 goto next_pkt;
4647 }
4648
4649 #if TG3_VLAN_TAG_USED
4650 if (tp->vlgrp != NULL &&
4651 desc->type_flags & RXD_FLAG_VLAN) {
4652 vlan_gro_receive(&tnapi->napi, tp->vlgrp,
4653 desc->err_vlan & RXD_VLAN_MASK, skb);
4654 } else
4655 #endif
4656 napi_gro_receive(&tnapi->napi, skb);
4657
4658 received++;
4659 budget--;
4660
4661 next_pkt:
4662 (*post_ptr)++;
4663
4664 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4665 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4666
4667 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4668 TG3_64BIT_REG_LOW, idx);
4669 work_mask &= ~RXD_OPAQUE_RING_STD;
4670 rx_std_posted = 0;
4671 }
4672 next_pkt_nopost:
4673 sw_idx++;
4674 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4675
4676 /* Refresh hw_idx to see if there is new work */
4677 if (sw_idx == hw_idx) {
4678 hw_idx = *(tnapi->rx_rcb_prod_idx);
4679 rmb();
4680 }
4681 }
4682
4683 /* ACK the status ring. */
4684 tnapi->rx_rcb_ptr = sw_idx;
4685 tw32_rx_mbox(tnapi->consmbox, sw_idx);
4686
4687 /* Refill RX ring(s). */
4688 if (work_mask & RXD_OPAQUE_RING_STD) {
4689 sw_idx = tpr->rx_std_ptr % TG3_RX_RING_SIZE;
4690 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4691 sw_idx);
4692 }
4693 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4694 sw_idx = tpr->rx_jmb_ptr % TG3_RX_JUMBO_RING_SIZE;
4695 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4696 sw_idx);
4697 }
4698 mmiowb();
4699
4700 return received;
4701 }
4702
4703 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4704 {
4705 struct tg3 *tp = tnapi->tp;
4706 struct tg3_hw_status *sblk = tnapi->hw_status;
4707
4708 /* handle link change and other phy events */
4709 if (!(tp->tg3_flags &
4710 (TG3_FLAG_USE_LINKCHG_REG |
4711 TG3_FLAG_POLL_SERDES))) {
4712 if (sblk->status & SD_STATUS_LINK_CHG) {
4713 sblk->status = SD_STATUS_UPDATED |
4714 (sblk->status & ~SD_STATUS_LINK_CHG);
4715 spin_lock(&tp->lock);
4716 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4717 tw32_f(MAC_STATUS,
4718 (MAC_STATUS_SYNC_CHANGED |
4719 MAC_STATUS_CFG_CHANGED |
4720 MAC_STATUS_MI_COMPLETION |
4721 MAC_STATUS_LNKSTATE_CHANGED));
4722 udelay(40);
4723 } else
4724 tg3_setup_phy(tp, 0);
4725 spin_unlock(&tp->lock);
4726 }
4727 }
4728
4729 /* run TX completion thread */
4730 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4731 tg3_tx(tnapi);
4732 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4733 return work_done;
4734 }
4735
4736 /* run RX thread, within the bounds set by NAPI.
4737 * All RX "locking" is done by ensuring outside
4738 * code synchronizes with tg3->napi.poll()
4739 */
4740 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4741 work_done += tg3_rx(tnapi, budget - work_done);
4742
4743 return work_done;
4744 }
4745
4746 static int tg3_poll(struct napi_struct *napi, int budget)
4747 {
4748 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4749 struct tg3 *tp = tnapi->tp;
4750 int work_done = 0;
4751 struct tg3_hw_status *sblk = tnapi->hw_status;
4752
4753 while (1) {
4754 work_done = tg3_poll_work(tnapi, work_done, budget);
4755
4756 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4757 goto tx_recovery;
4758
4759 if (unlikely(work_done >= budget))
4760 break;
4761
4762 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4763 /* tp->last_tag is used in tg3_int_reenable() below
4764 * to tell the hw how much work has been processed,
4765 * so we must read it before checking for more work.
4766 */
4767 tnapi->last_tag = sblk->status_tag;
4768 tnapi->last_irq_tag = tnapi->last_tag;
4769 rmb();
4770 } else
4771 sblk->status &= ~SD_STATUS_UPDATED;
4772
4773 if (likely(!tg3_has_work(tnapi))) {
4774 napi_complete(napi);
4775 tg3_int_reenable(tnapi);
4776 break;
4777 }
4778 }
4779
4780 return work_done;
4781
4782 tx_recovery:
4783 /* work_done is guaranteed to be less than budget. */
4784 napi_complete(napi);
4785 schedule_work(&tp->reset_task);
4786 return work_done;
4787 }
4788
4789 static void tg3_irq_quiesce(struct tg3 *tp)
4790 {
4791 int i;
4792
4793 BUG_ON(tp->irq_sync);
4794
4795 tp->irq_sync = 1;
4796 smp_mb();
4797
4798 for (i = 0; i < tp->irq_cnt; i++)
4799 synchronize_irq(tp->napi[i].irq_vec);
4800 }
4801
4802 static inline int tg3_irq_sync(struct tg3 *tp)
4803 {
4804 return tp->irq_sync;
4805 }
4806
4807 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4808 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4809 * with as well. Most of the time, this is not necessary except when
4810 * shutting down the device.
4811 */
4812 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4813 {
4814 spin_lock_bh(&tp->lock);
4815 if (irq_sync)
4816 tg3_irq_quiesce(tp);
4817 }
4818
4819 static inline void tg3_full_unlock(struct tg3 *tp)
4820 {
4821 spin_unlock_bh(&tp->lock);
4822 }
4823
4824 /* One-shot MSI handler - Chip automatically disables interrupt
4825 * after sending MSI so driver doesn't have to do it.
4826 */
4827 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4828 {
4829 struct tg3_napi *tnapi = dev_id;
4830 struct tg3 *tp = tnapi->tp;
4831
4832 prefetch(tnapi->hw_status);
4833 if (tnapi->rx_rcb)
4834 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4835
4836 if (likely(!tg3_irq_sync(tp)))
4837 napi_schedule(&tnapi->napi);
4838
4839 return IRQ_HANDLED;
4840 }
4841
4842 /* MSI ISR - No need to check for interrupt sharing and no need to
4843 * flush status block and interrupt mailbox. PCI ordering rules
4844 * guarantee that MSI will arrive after the status block.
4845 */
4846 static irqreturn_t tg3_msi(int irq, void *dev_id)
4847 {
4848 struct tg3_napi *tnapi = dev_id;
4849 struct tg3 *tp = tnapi->tp;
4850
4851 prefetch(tnapi->hw_status);
4852 if (tnapi->rx_rcb)
4853 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4854 /*
4855 * Writing any value to intr-mbox-0 clears PCI INTA# and
4856 * chip-internal interrupt pending events.
4857 * Writing non-zero to intr-mbox-0 additional tells the
4858 * NIC to stop sending us irqs, engaging "in-intr-handler"
4859 * event coalescing.
4860 */
4861 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4862 if (likely(!tg3_irq_sync(tp)))
4863 napi_schedule(&tnapi->napi);
4864
4865 return IRQ_RETVAL(1);
4866 }
4867
4868 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4869 {
4870 struct tg3_napi *tnapi = dev_id;
4871 struct tg3 *tp = tnapi->tp;
4872 struct tg3_hw_status *sblk = tnapi->hw_status;
4873 unsigned int handled = 1;
4874
4875 /* In INTx mode, it is possible for the interrupt to arrive at
4876 * the CPU before the status block posted prior to the interrupt.
4877 * Reading the PCI State register will confirm whether the
4878 * interrupt is ours and will flush the status block.
4879 */
4880 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4881 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4882 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4883 handled = 0;
4884 goto out;
4885 }
4886 }
4887
4888 /*
4889 * Writing any value to intr-mbox-0 clears PCI INTA# and
4890 * chip-internal interrupt pending events.
4891 * Writing non-zero to intr-mbox-0 additional tells the
4892 * NIC to stop sending us irqs, engaging "in-intr-handler"
4893 * event coalescing.
4894 *
4895 * Flush the mailbox to de-assert the IRQ immediately to prevent
4896 * spurious interrupts. The flush impacts performance but
4897 * excessive spurious interrupts can be worse in some cases.
4898 */
4899 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4900 if (tg3_irq_sync(tp))
4901 goto out;
4902 sblk->status &= ~SD_STATUS_UPDATED;
4903 if (likely(tg3_has_work(tnapi))) {
4904 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4905 napi_schedule(&tnapi->napi);
4906 } else {
4907 /* No work, shared interrupt perhaps? re-enable
4908 * interrupts, and flush that PCI write
4909 */
4910 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4911 0x00000000);
4912 }
4913 out:
4914 return IRQ_RETVAL(handled);
4915 }
4916
4917 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4918 {
4919 struct tg3_napi *tnapi = dev_id;
4920 struct tg3 *tp = tnapi->tp;
4921 struct tg3_hw_status *sblk = tnapi->hw_status;
4922 unsigned int handled = 1;
4923
4924 /* In INTx mode, it is possible for the interrupt to arrive at
4925 * the CPU before the status block posted prior to the interrupt.
4926 * Reading the PCI State register will confirm whether the
4927 * interrupt is ours and will flush the status block.
4928 */
4929 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
4930 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4931 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4932 handled = 0;
4933 goto out;
4934 }
4935 }
4936
4937 /*
4938 * writing any value to intr-mbox-0 clears PCI INTA# and
4939 * chip-internal interrupt pending events.
4940 * writing non-zero to intr-mbox-0 additional tells the
4941 * NIC to stop sending us irqs, engaging "in-intr-handler"
4942 * event coalescing.
4943 *
4944 * Flush the mailbox to de-assert the IRQ immediately to prevent
4945 * spurious interrupts. The flush impacts performance but
4946 * excessive spurious interrupts can be worse in some cases.
4947 */
4948 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4949
4950 /*
4951 * In a shared interrupt configuration, sometimes other devices'
4952 * interrupts will scream. We record the current status tag here
4953 * so that the above check can report that the screaming interrupts
4954 * are unhandled. Eventually they will be silenced.
4955 */
4956 tnapi->last_irq_tag = sblk->status_tag;
4957
4958 if (tg3_irq_sync(tp))
4959 goto out;
4960
4961 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4962
4963 napi_schedule(&tnapi->napi);
4964
4965 out:
4966 return IRQ_RETVAL(handled);
4967 }
4968
4969 /* ISR for interrupt test */
4970 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4971 {
4972 struct tg3_napi *tnapi = dev_id;
4973 struct tg3 *tp = tnapi->tp;
4974 struct tg3_hw_status *sblk = tnapi->hw_status;
4975
4976 if ((sblk->status & SD_STATUS_UPDATED) ||
4977 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4978 tg3_disable_ints(tp);
4979 return IRQ_RETVAL(1);
4980 }
4981 return IRQ_RETVAL(0);
4982 }
4983
4984 static int tg3_init_hw(struct tg3 *, int);
4985 static int tg3_halt(struct tg3 *, int, int);
4986
4987 /* Restart hardware after configuration changes, self-test, etc.
4988 * Invoked with tp->lock held.
4989 */
4990 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4991 __releases(tp->lock)
4992 __acquires(tp->lock)
4993 {
4994 int err;
4995
4996 err = tg3_init_hw(tp, reset_phy);
4997 if (err) {
4998 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4999 "aborting.\n", tp->dev->name);
5000 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5001 tg3_full_unlock(tp);
5002 del_timer_sync(&tp->timer);
5003 tp->irq_sync = 0;
5004 tg3_napi_enable(tp);
5005 dev_close(tp->dev);
5006 tg3_full_lock(tp, 0);
5007 }
5008 return err;
5009 }
5010
5011 #ifdef CONFIG_NET_POLL_CONTROLLER
5012 static void tg3_poll_controller(struct net_device *dev)
5013 {
5014 int i;
5015 struct tg3 *tp = netdev_priv(dev);
5016
5017 for (i = 0; i < tp->irq_cnt; i++)
5018 tg3_interrupt(tp->napi[i].irq_vec, dev);
5019 }
5020 #endif
5021
5022 static void tg3_reset_task(struct work_struct *work)
5023 {
5024 struct tg3 *tp = container_of(work, struct tg3, reset_task);
5025 int err;
5026 unsigned int restart_timer;
5027
5028 tg3_full_lock(tp, 0);
5029
5030 if (!netif_running(tp->dev)) {
5031 tg3_full_unlock(tp);
5032 return;
5033 }
5034
5035 tg3_full_unlock(tp);
5036
5037 tg3_phy_stop(tp);
5038
5039 tg3_netif_stop(tp);
5040
5041 tg3_full_lock(tp, 1);
5042
5043 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5044 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5045
5046 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5047 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5048 tp->write32_rx_mbox = tg3_write_flush_reg32;
5049 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5050 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5051 }
5052
5053 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5054 err = tg3_init_hw(tp, 1);
5055 if (err)
5056 goto out;
5057
5058 tg3_netif_start(tp);
5059
5060 if (restart_timer)
5061 mod_timer(&tp->timer, jiffies + 1);
5062
5063 out:
5064 tg3_full_unlock(tp);
5065
5066 if (!err)
5067 tg3_phy_start(tp);
5068 }
5069
5070 static void tg3_dump_short_state(struct tg3 *tp)
5071 {
5072 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5073 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5074 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5075 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5076 }
5077
5078 static void tg3_tx_timeout(struct net_device *dev)
5079 {
5080 struct tg3 *tp = netdev_priv(dev);
5081
5082 if (netif_msg_tx_err(tp)) {
5083 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5084 dev->name);
5085 tg3_dump_short_state(tp);
5086 }
5087
5088 schedule_work(&tp->reset_task);
5089 }
5090
5091 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5092 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5093 {
5094 u32 base = (u32) mapping & 0xffffffff;
5095
5096 return ((base > 0xffffdcc0) &&
5097 (base + len + 8 < base));
5098 }
5099
5100 /* Test for DMA addresses > 40-bit */
5101 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5102 int len)
5103 {
5104 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5105 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5106 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5107 return 0;
5108 #else
5109 return 0;
5110 #endif
5111 }
5112
5113 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5114
5115 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5116 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
5117 u32 last_plus_one, u32 *start,
5118 u32 base_flags, u32 mss)
5119 {
5120 struct tg3_napi *tnapi = &tp->napi[0];
5121 struct sk_buff *new_skb;
5122 dma_addr_t new_addr = 0;
5123 u32 entry = *start;
5124 int i, ret = 0;
5125
5126 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5127 new_skb = skb_copy(skb, GFP_ATOMIC);
5128 else {
5129 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5130
5131 new_skb = skb_copy_expand(skb,
5132 skb_headroom(skb) + more_headroom,
5133 skb_tailroom(skb), GFP_ATOMIC);
5134 }
5135
5136 if (!new_skb) {
5137 ret = -1;
5138 } else {
5139 /* New SKB is guaranteed to be linear. */
5140 entry = *start;
5141 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
5142 new_addr = skb_shinfo(new_skb)->dma_head;
5143
5144 /* Make sure new skb does not cross any 4G boundaries.
5145 * Drop the packet if it does.
5146 */
5147 if (ret || ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5148 tg3_4g_overflow_test(new_addr, new_skb->len))) {
5149 if (!ret)
5150 skb_dma_unmap(&tp->pdev->dev, new_skb,
5151 DMA_TO_DEVICE);
5152 ret = -1;
5153 dev_kfree_skb(new_skb);
5154 new_skb = NULL;
5155 } else {
5156 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5157 base_flags, 1 | (mss << 1));
5158 *start = NEXT_TX(entry);
5159 }
5160 }
5161
5162 /* Now clean up the sw ring entries. */
5163 i = 0;
5164 while (entry != last_plus_one) {
5165 if (i == 0)
5166 tnapi->tx_buffers[entry].skb = new_skb;
5167 else
5168 tnapi->tx_buffers[entry].skb = NULL;
5169 entry = NEXT_TX(entry);
5170 i++;
5171 }
5172
5173 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5174 dev_kfree_skb(skb);
5175
5176 return ret;
5177 }
5178
5179 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5180 dma_addr_t mapping, int len, u32 flags,
5181 u32 mss_and_is_end)
5182 {
5183 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5184 int is_end = (mss_and_is_end & 0x1);
5185 u32 mss = (mss_and_is_end >> 1);
5186 u32 vlan_tag = 0;
5187
5188 if (is_end)
5189 flags |= TXD_FLAG_END;
5190 if (flags & TXD_FLAG_VLAN) {
5191 vlan_tag = flags >> 16;
5192 flags &= 0xffff;
5193 }
5194 vlan_tag |= (mss << TXD_MSS_SHIFT);
5195
5196 txd->addr_hi = ((u64) mapping >> 32);
5197 txd->addr_lo = ((u64) mapping & 0xffffffff);
5198 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5199 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5200 }
5201
5202 /* hard_start_xmit for devices that don't have any bugs and
5203 * support TG3_FLG2_HW_TSO_2 only.
5204 */
5205 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5206 struct net_device *dev)
5207 {
5208 struct tg3 *tp = netdev_priv(dev);
5209 u32 len, entry, base_flags, mss;
5210 struct skb_shared_info *sp;
5211 dma_addr_t mapping;
5212 struct tg3_napi *tnapi;
5213 struct netdev_queue *txq;
5214
5215 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5216 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5217 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5218 tnapi++;
5219
5220 /* We are running in BH disabled context with netif_tx_lock
5221 * and TX reclaim runs via tp->napi.poll inside of a software
5222 * interrupt. Furthermore, IRQ processing runs lockless so we have
5223 * no IRQ context deadlocks to worry about either. Rejoice!
5224 */
5225 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5226 if (!netif_tx_queue_stopped(txq)) {
5227 netif_tx_stop_queue(txq);
5228
5229 /* This is a hard error, log it. */
5230 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5231 "queue awake!\n", dev->name);
5232 }
5233 return NETDEV_TX_BUSY;
5234 }
5235
5236 entry = tnapi->tx_prod;
5237 base_flags = 0;
5238 mss = 0;
5239 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5240 int tcp_opt_len, ip_tcp_len;
5241 u32 hdrlen;
5242
5243 if (skb_header_cloned(skb) &&
5244 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5245 dev_kfree_skb(skb);
5246 goto out_unlock;
5247 }
5248
5249 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5250 hdrlen = skb_headlen(skb) - ETH_HLEN;
5251 else {
5252 struct iphdr *iph = ip_hdr(skb);
5253
5254 tcp_opt_len = tcp_optlen(skb);
5255 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5256
5257 iph->check = 0;
5258 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5259 hdrlen = ip_tcp_len + tcp_opt_len;
5260 }
5261
5262 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
5263 mss |= (hdrlen & 0xc) << 12;
5264 if (hdrlen & 0x10)
5265 base_flags |= 0x00000010;
5266 base_flags |= (hdrlen & 0x3e0) << 5;
5267 } else
5268 mss |= hdrlen << 9;
5269
5270 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5271 TXD_FLAG_CPU_POST_DMA);
5272
5273 tcp_hdr(skb)->check = 0;
5274
5275 }
5276 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5277 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5278 #if TG3_VLAN_TAG_USED
5279 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5280 base_flags |= (TXD_FLAG_VLAN |
5281 (vlan_tx_tag_get(skb) << 16));
5282 #endif
5283
5284 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5285 dev_kfree_skb(skb);
5286 goto out_unlock;
5287 }
5288
5289 sp = skb_shinfo(skb);
5290
5291 mapping = sp->dma_head;
5292
5293 tnapi->tx_buffers[entry].skb = skb;
5294
5295 len = skb_headlen(skb);
5296
5297 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
5298 !mss && skb->len > ETH_DATA_LEN)
5299 base_flags |= TXD_FLAG_JMB_PKT;
5300
5301 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5302 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5303
5304 entry = NEXT_TX(entry);
5305
5306 /* Now loop through additional data fragments, and queue them. */
5307 if (skb_shinfo(skb)->nr_frags > 0) {
5308 unsigned int i, last;
5309
5310 last = skb_shinfo(skb)->nr_frags - 1;
5311 for (i = 0; i <= last; i++) {
5312 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5313
5314 len = frag->size;
5315 mapping = sp->dma_maps[i];
5316 tnapi->tx_buffers[entry].skb = NULL;
5317
5318 tg3_set_txd(tnapi, entry, mapping, len,
5319 base_flags, (i == last) | (mss << 1));
5320
5321 entry = NEXT_TX(entry);
5322 }
5323 }
5324
5325 /* Packets are ready, update Tx producer idx local and on card. */
5326 tw32_tx_mbox(tnapi->prodmbox, entry);
5327
5328 tnapi->tx_prod = entry;
5329 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5330 netif_tx_stop_queue(txq);
5331 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5332 netif_tx_wake_queue(txq);
5333 }
5334
5335 out_unlock:
5336 mmiowb();
5337
5338 return NETDEV_TX_OK;
5339 }
5340
5341 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5342 struct net_device *);
5343
5344 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5345 * TSO header is greater than 80 bytes.
5346 */
5347 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5348 {
5349 struct sk_buff *segs, *nskb;
5350 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5351
5352 /* Estimate the number of fragments in the worst case */
5353 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5354 netif_stop_queue(tp->dev);
5355 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5356 return NETDEV_TX_BUSY;
5357
5358 netif_wake_queue(tp->dev);
5359 }
5360
5361 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5362 if (IS_ERR(segs))
5363 goto tg3_tso_bug_end;
5364
5365 do {
5366 nskb = segs;
5367 segs = segs->next;
5368 nskb->next = NULL;
5369 tg3_start_xmit_dma_bug(nskb, tp->dev);
5370 } while (segs);
5371
5372 tg3_tso_bug_end:
5373 dev_kfree_skb(skb);
5374
5375 return NETDEV_TX_OK;
5376 }
5377
5378 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5379 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5380 */
5381 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5382 struct net_device *dev)
5383 {
5384 struct tg3 *tp = netdev_priv(dev);
5385 u32 len, entry, base_flags, mss;
5386 struct skb_shared_info *sp;
5387 int would_hit_hwbug;
5388 dma_addr_t mapping;
5389 struct tg3_napi *tnapi = &tp->napi[0];
5390
5391 len = skb_headlen(skb);
5392
5393 /* We are running in BH disabled context with netif_tx_lock
5394 * and TX reclaim runs via tp->napi.poll inside of a software
5395 * interrupt. Furthermore, IRQ processing runs lockless so we have
5396 * no IRQ context deadlocks to worry about either. Rejoice!
5397 */
5398 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5399 if (!netif_queue_stopped(dev)) {
5400 netif_stop_queue(dev);
5401
5402 /* This is a hard error, log it. */
5403 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5404 "queue awake!\n", dev->name);
5405 }
5406 return NETDEV_TX_BUSY;
5407 }
5408
5409 entry = tnapi->tx_prod;
5410 base_flags = 0;
5411 if (skb->ip_summed == CHECKSUM_PARTIAL)
5412 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5413 mss = 0;
5414 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5415 struct iphdr *iph;
5416 u32 tcp_opt_len, ip_tcp_len, hdr_len;
5417
5418 if (skb_header_cloned(skb) &&
5419 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5420 dev_kfree_skb(skb);
5421 goto out_unlock;
5422 }
5423
5424 tcp_opt_len = tcp_optlen(skb);
5425 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5426
5427 hdr_len = ip_tcp_len + tcp_opt_len;
5428 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5429 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5430 return (tg3_tso_bug(tp, skb));
5431
5432 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5433 TXD_FLAG_CPU_POST_DMA);
5434
5435 iph = ip_hdr(skb);
5436 iph->check = 0;
5437 iph->tot_len = htons(mss + hdr_len);
5438 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5439 tcp_hdr(skb)->check = 0;
5440 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5441 } else
5442 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5443 iph->daddr, 0,
5444 IPPROTO_TCP,
5445 0);
5446
5447 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5448 mss |= hdr_len << 9;
5449 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5450 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5451 if (tcp_opt_len || iph->ihl > 5) {
5452 int tsflags;
5453
5454 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5455 mss |= (tsflags << 11);
5456 }
5457 } else {
5458 if (tcp_opt_len || iph->ihl > 5) {
5459 int tsflags;
5460
5461 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5462 base_flags |= tsflags << 12;
5463 }
5464 }
5465 }
5466 #if TG3_VLAN_TAG_USED
5467 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5468 base_flags |= (TXD_FLAG_VLAN |
5469 (vlan_tx_tag_get(skb) << 16));
5470 #endif
5471
5472 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5473 dev_kfree_skb(skb);
5474 goto out_unlock;
5475 }
5476
5477 sp = skb_shinfo(skb);
5478
5479 mapping = sp->dma_head;
5480
5481 tnapi->tx_buffers[entry].skb = skb;
5482
5483 would_hit_hwbug = 0;
5484
5485 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5486 would_hit_hwbug = 1;
5487
5488 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5489 tg3_4g_overflow_test(mapping, len))
5490 would_hit_hwbug = 1;
5491
5492 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5493 tg3_40bit_overflow_test(tp, mapping, len))
5494 would_hit_hwbug = 1;
5495
5496 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5497 would_hit_hwbug = 1;
5498
5499 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5500 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5501
5502 entry = NEXT_TX(entry);
5503
5504 /* Now loop through additional data fragments, and queue them. */
5505 if (skb_shinfo(skb)->nr_frags > 0) {
5506 unsigned int i, last;
5507
5508 last = skb_shinfo(skb)->nr_frags - 1;
5509 for (i = 0; i <= last; i++) {
5510 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5511
5512 len = frag->size;
5513 mapping = sp->dma_maps[i];
5514
5515 tnapi->tx_buffers[entry].skb = NULL;
5516
5517 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5518 len <= 8)
5519 would_hit_hwbug = 1;
5520
5521 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5522 tg3_4g_overflow_test(mapping, len))
5523 would_hit_hwbug = 1;
5524
5525 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5526 tg3_40bit_overflow_test(tp, mapping, len))
5527 would_hit_hwbug = 1;
5528
5529 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5530 tg3_set_txd(tnapi, entry, mapping, len,
5531 base_flags, (i == last)|(mss << 1));
5532 else
5533 tg3_set_txd(tnapi, entry, mapping, len,
5534 base_flags, (i == last));
5535
5536 entry = NEXT_TX(entry);
5537 }
5538 }
5539
5540 if (would_hit_hwbug) {
5541 u32 last_plus_one = entry;
5542 u32 start;
5543
5544 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5545 start &= (TG3_TX_RING_SIZE - 1);
5546
5547 /* If the workaround fails due to memory/mapping
5548 * failure, silently drop this packet.
5549 */
5550 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
5551 &start, base_flags, mss))
5552 goto out_unlock;
5553
5554 entry = start;
5555 }
5556
5557 /* Packets are ready, update Tx producer idx local and on card. */
5558 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, entry);
5559
5560 tnapi->tx_prod = entry;
5561 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5562 netif_stop_queue(dev);
5563 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5564 netif_wake_queue(tp->dev);
5565 }
5566
5567 out_unlock:
5568 mmiowb();
5569
5570 return NETDEV_TX_OK;
5571 }
5572
5573 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5574 int new_mtu)
5575 {
5576 dev->mtu = new_mtu;
5577
5578 if (new_mtu > ETH_DATA_LEN) {
5579 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5580 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5581 ethtool_op_set_tso(dev, 0);
5582 }
5583 else
5584 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5585 } else {
5586 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5587 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5588 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5589 }
5590 }
5591
5592 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5593 {
5594 struct tg3 *tp = netdev_priv(dev);
5595 int err;
5596
5597 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5598 return -EINVAL;
5599
5600 if (!netif_running(dev)) {
5601 /* We'll just catch it later when the
5602 * device is up'd.
5603 */
5604 tg3_set_mtu(dev, tp, new_mtu);
5605 return 0;
5606 }
5607
5608 tg3_phy_stop(tp);
5609
5610 tg3_netif_stop(tp);
5611
5612 tg3_full_lock(tp, 1);
5613
5614 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5615
5616 tg3_set_mtu(dev, tp, new_mtu);
5617
5618 err = tg3_restart_hw(tp, 0);
5619
5620 if (!err)
5621 tg3_netif_start(tp);
5622
5623 tg3_full_unlock(tp);
5624
5625 if (!err)
5626 tg3_phy_start(tp);
5627
5628 return err;
5629 }
5630
5631 static void tg3_rx_prodring_free(struct tg3 *tp,
5632 struct tg3_rx_prodring_set *tpr)
5633 {
5634 int i;
5635 struct ring_info *rxp;
5636
5637 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5638 rxp = &tpr->rx_std_buffers[i];
5639
5640 if (rxp->skb == NULL)
5641 continue;
5642
5643 pci_unmap_single(tp->pdev,
5644 pci_unmap_addr(rxp, mapping),
5645 tp->rx_pkt_map_sz,
5646 PCI_DMA_FROMDEVICE);
5647 dev_kfree_skb_any(rxp->skb);
5648 rxp->skb = NULL;
5649 }
5650
5651 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5652 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5653 rxp = &tpr->rx_jmb_buffers[i];
5654
5655 if (rxp->skb == NULL)
5656 continue;
5657
5658 pci_unmap_single(tp->pdev,
5659 pci_unmap_addr(rxp, mapping),
5660 TG3_RX_JMB_MAP_SZ,
5661 PCI_DMA_FROMDEVICE);
5662 dev_kfree_skb_any(rxp->skb);
5663 rxp->skb = NULL;
5664 }
5665 }
5666 }
5667
5668 /* Initialize tx/rx rings for packet processing.
5669 *
5670 * The chip has been shut down and the driver detached from
5671 * the networking, so no interrupts or new tx packets will
5672 * end up in the driver. tp->{tx,}lock are held and thus
5673 * we may not sleep.
5674 */
5675 static int tg3_rx_prodring_alloc(struct tg3 *tp,
5676 struct tg3_rx_prodring_set *tpr)
5677 {
5678 u32 i, rx_pkt_dma_sz;
5679 struct tg3_napi *tnapi = &tp->napi[0];
5680
5681 /* Zero out all descriptors. */
5682 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
5683
5684 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
5685 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5686 tp->dev->mtu > ETH_DATA_LEN)
5687 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5688 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
5689
5690 /* Initialize invariants of the rings, we only set this
5691 * stuff once. This works because the card does not
5692 * write into the rx buffer posting rings.
5693 */
5694 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5695 struct tg3_rx_buffer_desc *rxd;
5696
5697 rxd = &tpr->rx_std[i];
5698 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
5699 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5700 rxd->opaque = (RXD_OPAQUE_RING_STD |
5701 (i << RXD_OPAQUE_INDEX_SHIFT));
5702 }
5703
5704 /* Now allocate fresh SKBs for each rx ring. */
5705 for (i = 0; i < tp->rx_pending; i++) {
5706 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5707 printk(KERN_WARNING PFX
5708 "%s: Using a smaller RX standard ring, "
5709 "only %d out of %d buffers were allocated "
5710 "successfully.\n",
5711 tp->dev->name, i, tp->rx_pending);
5712 if (i == 0)
5713 goto initfail;
5714 tp->rx_pending = i;
5715 break;
5716 }
5717 }
5718
5719 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
5720 goto done;
5721
5722 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
5723
5724 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5725 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5726 struct tg3_rx_buffer_desc *rxd;
5727
5728 rxd = &tpr->rx_jmb[i].std;
5729 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
5730 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5731 RXD_FLAG_JUMBO;
5732 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5733 (i << RXD_OPAQUE_INDEX_SHIFT));
5734 }
5735
5736 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5737 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_JUMBO,
5738 -1, i) < 0) {
5739 printk(KERN_WARNING PFX
5740 "%s: Using a smaller RX jumbo ring, "
5741 "only %d out of %d buffers were "
5742 "allocated successfully.\n",
5743 tp->dev->name, i, tp->rx_jumbo_pending);
5744 if (i == 0)
5745 goto initfail;
5746 tp->rx_jumbo_pending = i;
5747 break;
5748 }
5749 }
5750 }
5751
5752 done:
5753 return 0;
5754
5755 initfail:
5756 tg3_rx_prodring_free(tp, tpr);
5757 return -ENOMEM;
5758 }
5759
5760 static void tg3_rx_prodring_fini(struct tg3 *tp,
5761 struct tg3_rx_prodring_set *tpr)
5762 {
5763 kfree(tpr->rx_std_buffers);
5764 tpr->rx_std_buffers = NULL;
5765 kfree(tpr->rx_jmb_buffers);
5766 tpr->rx_jmb_buffers = NULL;
5767 if (tpr->rx_std) {
5768 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5769 tpr->rx_std, tpr->rx_std_mapping);
5770 tpr->rx_std = NULL;
5771 }
5772 if (tpr->rx_jmb) {
5773 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5774 tpr->rx_jmb, tpr->rx_jmb_mapping);
5775 tpr->rx_jmb = NULL;
5776 }
5777 }
5778
5779 static int tg3_rx_prodring_init(struct tg3 *tp,
5780 struct tg3_rx_prodring_set *tpr)
5781 {
5782 tpr->rx_std_buffers = kzalloc(sizeof(struct ring_info) *
5783 TG3_RX_RING_SIZE, GFP_KERNEL);
5784 if (!tpr->rx_std_buffers)
5785 return -ENOMEM;
5786
5787 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5788 &tpr->rx_std_mapping);
5789 if (!tpr->rx_std)
5790 goto err_out;
5791
5792 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5793 tpr->rx_jmb_buffers = kzalloc(sizeof(struct ring_info) *
5794 TG3_RX_JUMBO_RING_SIZE,
5795 GFP_KERNEL);
5796 if (!tpr->rx_jmb_buffers)
5797 goto err_out;
5798
5799 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
5800 TG3_RX_JUMBO_RING_BYTES,
5801 &tpr->rx_jmb_mapping);
5802 if (!tpr->rx_jmb)
5803 goto err_out;
5804 }
5805
5806 return 0;
5807
5808 err_out:
5809 tg3_rx_prodring_fini(tp, tpr);
5810 return -ENOMEM;
5811 }
5812
5813 /* Free up pending packets in all rx/tx rings.
5814 *
5815 * The chip has been shut down and the driver detached from
5816 * the networking, so no interrupts or new tx packets will
5817 * end up in the driver. tp->{tx,}lock is not held and we are not
5818 * in an interrupt context and thus may sleep.
5819 */
5820 static void tg3_free_rings(struct tg3 *tp)
5821 {
5822 int i, j;
5823
5824 for (j = 0; j < tp->irq_cnt; j++) {
5825 struct tg3_napi *tnapi = &tp->napi[j];
5826
5827 if (!tnapi->tx_buffers)
5828 continue;
5829
5830 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5831 struct tx_ring_info *txp;
5832 struct sk_buff *skb;
5833
5834 txp = &tnapi->tx_buffers[i];
5835 skb = txp->skb;
5836
5837 if (skb == NULL) {
5838 i++;
5839 continue;
5840 }
5841
5842 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5843
5844 txp->skb = NULL;
5845
5846 i += skb_shinfo(skb)->nr_frags + 1;
5847
5848 dev_kfree_skb_any(skb);
5849 }
5850 }
5851
5852 tg3_rx_prodring_free(tp, &tp->prodring[0]);
5853 }
5854
5855 /* Initialize tx/rx rings for packet processing.
5856 *
5857 * The chip has been shut down and the driver detached from
5858 * the networking, so no interrupts or new tx packets will
5859 * end up in the driver. tp->{tx,}lock are held and thus
5860 * we may not sleep.
5861 */
5862 static int tg3_init_rings(struct tg3 *tp)
5863 {
5864 int i;
5865
5866 /* Free up all the SKBs. */
5867 tg3_free_rings(tp);
5868
5869 for (i = 0; i < tp->irq_cnt; i++) {
5870 struct tg3_napi *tnapi = &tp->napi[i];
5871
5872 tnapi->last_tag = 0;
5873 tnapi->last_irq_tag = 0;
5874 tnapi->hw_status->status = 0;
5875 tnapi->hw_status->status_tag = 0;
5876 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
5877
5878 tnapi->tx_prod = 0;
5879 tnapi->tx_cons = 0;
5880 if (tnapi->tx_ring)
5881 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
5882
5883 tnapi->rx_rcb_ptr = 0;
5884 if (tnapi->rx_rcb)
5885 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5886 }
5887
5888 return tg3_rx_prodring_alloc(tp, &tp->prodring[0]);
5889 }
5890
5891 /*
5892 * Must not be invoked with interrupt sources disabled and
5893 * the hardware shutdown down.
5894 */
5895 static void tg3_free_consistent(struct tg3 *tp)
5896 {
5897 int i;
5898
5899 for (i = 0; i < tp->irq_cnt; i++) {
5900 struct tg3_napi *tnapi = &tp->napi[i];
5901
5902 if (tnapi->tx_ring) {
5903 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5904 tnapi->tx_ring, tnapi->tx_desc_mapping);
5905 tnapi->tx_ring = NULL;
5906 }
5907
5908 kfree(tnapi->tx_buffers);
5909 tnapi->tx_buffers = NULL;
5910
5911 if (tnapi->rx_rcb) {
5912 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5913 tnapi->rx_rcb,
5914 tnapi->rx_rcb_mapping);
5915 tnapi->rx_rcb = NULL;
5916 }
5917
5918 if (tnapi->hw_status) {
5919 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5920 tnapi->hw_status,
5921 tnapi->status_mapping);
5922 tnapi->hw_status = NULL;
5923 }
5924 }
5925
5926 if (tp->hw_stats) {
5927 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5928 tp->hw_stats, tp->stats_mapping);
5929 tp->hw_stats = NULL;
5930 }
5931
5932 tg3_rx_prodring_fini(tp, &tp->prodring[0]);
5933 }
5934
5935 /*
5936 * Must not be invoked with interrupt sources disabled and
5937 * the hardware shutdown down. Can sleep.
5938 */
5939 static int tg3_alloc_consistent(struct tg3 *tp)
5940 {
5941 int i;
5942
5943 if (tg3_rx_prodring_init(tp, &tp->prodring[0]))
5944 return -ENOMEM;
5945
5946 tp->hw_stats = pci_alloc_consistent(tp->pdev,
5947 sizeof(struct tg3_hw_stats),
5948 &tp->stats_mapping);
5949 if (!tp->hw_stats)
5950 goto err_out;
5951
5952 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5953
5954 for (i = 0; i < tp->irq_cnt; i++) {
5955 struct tg3_napi *tnapi = &tp->napi[i];
5956 struct tg3_hw_status *sblk;
5957
5958 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
5959 TG3_HW_STATUS_SIZE,
5960 &tnapi->status_mapping);
5961 if (!tnapi->hw_status)
5962 goto err_out;
5963
5964 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
5965 sblk = tnapi->hw_status;
5966
5967 /*
5968 * When RSS is enabled, the status block format changes
5969 * slightly. The "rx_jumbo_consumer", "reserved",
5970 * and "rx_mini_consumer" members get mapped to the
5971 * other three rx return ring producer indexes.
5972 */
5973 switch (i) {
5974 default:
5975 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
5976 break;
5977 case 2:
5978 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
5979 break;
5980 case 3:
5981 tnapi->rx_rcb_prod_idx = &sblk->reserved;
5982 break;
5983 case 4:
5984 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
5985 break;
5986 }
5987
5988 /*
5989 * If multivector RSS is enabled, vector 0 does not handle
5990 * rx or tx interrupts. Don't allocate any resources for it.
5991 */
5992 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
5993 continue;
5994
5995 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
5996 TG3_RX_RCB_RING_BYTES(tp),
5997 &tnapi->rx_rcb_mapping);
5998 if (!tnapi->rx_rcb)
5999 goto err_out;
6000
6001 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6002
6003 tnapi->tx_buffers = kzalloc(sizeof(struct tx_ring_info) *
6004 TG3_TX_RING_SIZE, GFP_KERNEL);
6005 if (!tnapi->tx_buffers)
6006 goto err_out;
6007
6008 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6009 TG3_TX_RING_BYTES,
6010 &tnapi->tx_desc_mapping);
6011 if (!tnapi->tx_ring)
6012 goto err_out;
6013 }
6014
6015 return 0;
6016
6017 err_out:
6018 tg3_free_consistent(tp);
6019 return -ENOMEM;
6020 }
6021
6022 #define MAX_WAIT_CNT 1000
6023
6024 /* To stop a block, clear the enable bit and poll till it
6025 * clears. tp->lock is held.
6026 */
6027 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6028 {
6029 unsigned int i;
6030 u32 val;
6031
6032 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6033 switch (ofs) {
6034 case RCVLSC_MODE:
6035 case DMAC_MODE:
6036 case MBFREE_MODE:
6037 case BUFMGR_MODE:
6038 case MEMARB_MODE:
6039 /* We can't enable/disable these bits of the
6040 * 5705/5750, just say success.
6041 */
6042 return 0;
6043
6044 default:
6045 break;
6046 }
6047 }
6048
6049 val = tr32(ofs);
6050 val &= ~enable_bit;
6051 tw32_f(ofs, val);
6052
6053 for (i = 0; i < MAX_WAIT_CNT; i++) {
6054 udelay(100);
6055 val = tr32(ofs);
6056 if ((val & enable_bit) == 0)
6057 break;
6058 }
6059
6060 if (i == MAX_WAIT_CNT && !silent) {
6061 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6062 "ofs=%lx enable_bit=%x\n",
6063 ofs, enable_bit);
6064 return -ENODEV;
6065 }
6066
6067 return 0;
6068 }
6069
6070 /* tp->lock is held. */
6071 static int tg3_abort_hw(struct tg3 *tp, int silent)
6072 {
6073 int i, err;
6074
6075 tg3_disable_ints(tp);
6076
6077 tp->rx_mode &= ~RX_MODE_ENABLE;
6078 tw32_f(MAC_RX_MODE, tp->rx_mode);
6079 udelay(10);
6080
6081 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6082 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6083 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6084 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6085 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6086 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6087
6088 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6089 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6090 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6091 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6092 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6093 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6094 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6095
6096 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6097 tw32_f(MAC_MODE, tp->mac_mode);
6098 udelay(40);
6099
6100 tp->tx_mode &= ~TX_MODE_ENABLE;
6101 tw32_f(MAC_TX_MODE, tp->tx_mode);
6102
6103 for (i = 0; i < MAX_WAIT_CNT; i++) {
6104 udelay(100);
6105 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6106 break;
6107 }
6108 if (i >= MAX_WAIT_CNT) {
6109 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6110 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6111 tp->dev->name, tr32(MAC_TX_MODE));
6112 err |= -ENODEV;
6113 }
6114
6115 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6116 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6117 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6118
6119 tw32(FTQ_RESET, 0xffffffff);
6120 tw32(FTQ_RESET, 0x00000000);
6121
6122 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6123 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6124
6125 for (i = 0; i < tp->irq_cnt; i++) {
6126 struct tg3_napi *tnapi = &tp->napi[i];
6127 if (tnapi->hw_status)
6128 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6129 }
6130 if (tp->hw_stats)
6131 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6132
6133 return err;
6134 }
6135
6136 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6137 {
6138 int i;
6139 u32 apedata;
6140
6141 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6142 if (apedata != APE_SEG_SIG_MAGIC)
6143 return;
6144
6145 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6146 if (!(apedata & APE_FW_STATUS_READY))
6147 return;
6148
6149 /* Wait for up to 1 millisecond for APE to service previous event. */
6150 for (i = 0; i < 10; i++) {
6151 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6152 return;
6153
6154 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6155
6156 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6157 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6158 event | APE_EVENT_STATUS_EVENT_PENDING);
6159
6160 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6161
6162 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6163 break;
6164
6165 udelay(100);
6166 }
6167
6168 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6169 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6170 }
6171
6172 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6173 {
6174 u32 event;
6175 u32 apedata;
6176
6177 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6178 return;
6179
6180 switch (kind) {
6181 case RESET_KIND_INIT:
6182 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6183 APE_HOST_SEG_SIG_MAGIC);
6184 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6185 APE_HOST_SEG_LEN_MAGIC);
6186 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6187 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6188 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6189 APE_HOST_DRIVER_ID_MAGIC);
6190 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6191 APE_HOST_BEHAV_NO_PHYLOCK);
6192
6193 event = APE_EVENT_STATUS_STATE_START;
6194 break;
6195 case RESET_KIND_SHUTDOWN:
6196 /* With the interface we are currently using,
6197 * APE does not track driver state. Wiping
6198 * out the HOST SEGMENT SIGNATURE forces
6199 * the APE to assume OS absent status.
6200 */
6201 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6202
6203 event = APE_EVENT_STATUS_STATE_UNLOAD;
6204 break;
6205 case RESET_KIND_SUSPEND:
6206 event = APE_EVENT_STATUS_STATE_SUSPEND;
6207 break;
6208 default:
6209 return;
6210 }
6211
6212 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6213
6214 tg3_ape_send_event(tp, event);
6215 }
6216
6217 /* tp->lock is held. */
6218 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6219 {
6220 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6221 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6222
6223 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6224 switch (kind) {
6225 case RESET_KIND_INIT:
6226 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6227 DRV_STATE_START);
6228 break;
6229
6230 case RESET_KIND_SHUTDOWN:
6231 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6232 DRV_STATE_UNLOAD);
6233 break;
6234
6235 case RESET_KIND_SUSPEND:
6236 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6237 DRV_STATE_SUSPEND);
6238 break;
6239
6240 default:
6241 break;
6242 }
6243 }
6244
6245 if (kind == RESET_KIND_INIT ||
6246 kind == RESET_KIND_SUSPEND)
6247 tg3_ape_driver_state_change(tp, kind);
6248 }
6249
6250 /* tp->lock is held. */
6251 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6252 {
6253 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6254 switch (kind) {
6255 case RESET_KIND_INIT:
6256 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6257 DRV_STATE_START_DONE);
6258 break;
6259
6260 case RESET_KIND_SHUTDOWN:
6261 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6262 DRV_STATE_UNLOAD_DONE);
6263 break;
6264
6265 default:
6266 break;
6267 }
6268 }
6269
6270 if (kind == RESET_KIND_SHUTDOWN)
6271 tg3_ape_driver_state_change(tp, kind);
6272 }
6273
6274 /* tp->lock is held. */
6275 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6276 {
6277 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6278 switch (kind) {
6279 case RESET_KIND_INIT:
6280 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6281 DRV_STATE_START);
6282 break;
6283
6284 case RESET_KIND_SHUTDOWN:
6285 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6286 DRV_STATE_UNLOAD);
6287 break;
6288
6289 case RESET_KIND_SUSPEND:
6290 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6291 DRV_STATE_SUSPEND);
6292 break;
6293
6294 default:
6295 break;
6296 }
6297 }
6298 }
6299
6300 static int tg3_poll_fw(struct tg3 *tp)
6301 {
6302 int i;
6303 u32 val;
6304
6305 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6306 /* Wait up to 20ms for init done. */
6307 for (i = 0; i < 200; i++) {
6308 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6309 return 0;
6310 udelay(100);
6311 }
6312 return -ENODEV;
6313 }
6314
6315 /* Wait for firmware initialization to complete. */
6316 for (i = 0; i < 100000; i++) {
6317 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6318 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6319 break;
6320 udelay(10);
6321 }
6322
6323 /* Chip might not be fitted with firmware. Some Sun onboard
6324 * parts are configured like that. So don't signal the timeout
6325 * of the above loop as an error, but do report the lack of
6326 * running firmware once.
6327 */
6328 if (i >= 100000 &&
6329 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6330 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6331
6332 printk(KERN_INFO PFX "%s: No firmware running.\n",
6333 tp->dev->name);
6334 }
6335
6336 return 0;
6337 }
6338
6339 /* Save PCI command register before chip reset */
6340 static void tg3_save_pci_state(struct tg3 *tp)
6341 {
6342 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6343 }
6344
6345 /* Restore PCI state after chip reset */
6346 static void tg3_restore_pci_state(struct tg3 *tp)
6347 {
6348 u32 val;
6349
6350 /* Re-enable indirect register accesses. */
6351 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6352 tp->misc_host_ctrl);
6353
6354 /* Set MAX PCI retry to zero. */
6355 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6356 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6357 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6358 val |= PCISTATE_RETRY_SAME_DMA;
6359 /* Allow reads and writes to the APE register and memory space. */
6360 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6361 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6362 PCISTATE_ALLOW_APE_SHMEM_WR;
6363 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6364
6365 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6366
6367 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6368 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6369 pcie_set_readrq(tp->pdev, 4096);
6370 else {
6371 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6372 tp->pci_cacheline_sz);
6373 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6374 tp->pci_lat_timer);
6375 }
6376 }
6377
6378 /* Make sure PCI-X relaxed ordering bit is clear. */
6379 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6380 u16 pcix_cmd;
6381
6382 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6383 &pcix_cmd);
6384 pcix_cmd &= ~PCI_X_CMD_ERO;
6385 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6386 pcix_cmd);
6387 }
6388
6389 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6390
6391 /* Chip reset on 5780 will reset MSI enable bit,
6392 * so need to restore it.
6393 */
6394 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6395 u16 ctrl;
6396
6397 pci_read_config_word(tp->pdev,
6398 tp->msi_cap + PCI_MSI_FLAGS,
6399 &ctrl);
6400 pci_write_config_word(tp->pdev,
6401 tp->msi_cap + PCI_MSI_FLAGS,
6402 ctrl | PCI_MSI_FLAGS_ENABLE);
6403 val = tr32(MSGINT_MODE);
6404 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6405 }
6406 }
6407 }
6408
6409 static void tg3_stop_fw(struct tg3 *);
6410
6411 /* tp->lock is held. */
6412 static int tg3_chip_reset(struct tg3 *tp)
6413 {
6414 u32 val;
6415 void (*write_op)(struct tg3 *, u32, u32);
6416 int i, err;
6417
6418 tg3_nvram_lock(tp);
6419
6420 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6421
6422 /* No matching tg3_nvram_unlock() after this because
6423 * chip reset below will undo the nvram lock.
6424 */
6425 tp->nvram_lock_cnt = 0;
6426
6427 /* GRC_MISC_CFG core clock reset will clear the memory
6428 * enable bit in PCI register 4 and the MSI enable bit
6429 * on some chips, so we save relevant registers here.
6430 */
6431 tg3_save_pci_state(tp);
6432
6433 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6434 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6435 tw32(GRC_FASTBOOT_PC, 0);
6436
6437 /*
6438 * We must avoid the readl() that normally takes place.
6439 * It locks machines, causes machine checks, and other
6440 * fun things. So, temporarily disable the 5701
6441 * hardware workaround, while we do the reset.
6442 */
6443 write_op = tp->write32;
6444 if (write_op == tg3_write_flush_reg32)
6445 tp->write32 = tg3_write32;
6446
6447 /* Prevent the irq handler from reading or writing PCI registers
6448 * during chip reset when the memory enable bit in the PCI command
6449 * register may be cleared. The chip does not generate interrupt
6450 * at this time, but the irq handler may still be called due to irq
6451 * sharing or irqpoll.
6452 */
6453 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6454 for (i = 0; i < tp->irq_cnt; i++) {
6455 struct tg3_napi *tnapi = &tp->napi[i];
6456 if (tnapi->hw_status) {
6457 tnapi->hw_status->status = 0;
6458 tnapi->hw_status->status_tag = 0;
6459 }
6460 tnapi->last_tag = 0;
6461 tnapi->last_irq_tag = 0;
6462 }
6463 smp_mb();
6464
6465 for (i = 0; i < tp->irq_cnt; i++)
6466 synchronize_irq(tp->napi[i].irq_vec);
6467
6468 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6469 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6470 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6471 }
6472
6473 /* do the reset */
6474 val = GRC_MISC_CFG_CORECLK_RESET;
6475
6476 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6477 if (tr32(0x7e2c) == 0x60) {
6478 tw32(0x7e2c, 0x20);
6479 }
6480 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6481 tw32(GRC_MISC_CFG, (1 << 29));
6482 val |= (1 << 29);
6483 }
6484 }
6485
6486 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6487 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6488 tw32(GRC_VCPU_EXT_CTRL,
6489 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6490 }
6491
6492 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6493 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6494 tw32(GRC_MISC_CFG, val);
6495
6496 /* restore 5701 hardware bug workaround write method */
6497 tp->write32 = write_op;
6498
6499 /* Unfortunately, we have to delay before the PCI read back.
6500 * Some 575X chips even will not respond to a PCI cfg access
6501 * when the reset command is given to the chip.
6502 *
6503 * How do these hardware designers expect things to work
6504 * properly if the PCI write is posted for a long period
6505 * of time? It is always necessary to have some method by
6506 * which a register read back can occur to push the write
6507 * out which does the reset.
6508 *
6509 * For most tg3 variants the trick below was working.
6510 * Ho hum...
6511 */
6512 udelay(120);
6513
6514 /* Flush PCI posted writes. The normal MMIO registers
6515 * are inaccessible at this time so this is the only
6516 * way to make this reliably (actually, this is no longer
6517 * the case, see above). I tried to use indirect
6518 * register read/write but this upset some 5701 variants.
6519 */
6520 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6521
6522 udelay(120);
6523
6524 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6525 u16 val16;
6526
6527 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6528 int i;
6529 u32 cfg_val;
6530
6531 /* Wait for link training to complete. */
6532 for (i = 0; i < 5000; i++)
6533 udelay(100);
6534
6535 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6536 pci_write_config_dword(tp->pdev, 0xc4,
6537 cfg_val | (1 << 15));
6538 }
6539
6540 /* Clear the "no snoop" and "relaxed ordering" bits. */
6541 pci_read_config_word(tp->pdev,
6542 tp->pcie_cap + PCI_EXP_DEVCTL,
6543 &val16);
6544 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6545 PCI_EXP_DEVCTL_NOSNOOP_EN);
6546 /*
6547 * Older PCIe devices only support the 128 byte
6548 * MPS setting. Enforce the restriction.
6549 */
6550 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6551 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6552 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6553 pci_write_config_word(tp->pdev,
6554 tp->pcie_cap + PCI_EXP_DEVCTL,
6555 val16);
6556
6557 pcie_set_readrq(tp->pdev, 4096);
6558
6559 /* Clear error status */
6560 pci_write_config_word(tp->pdev,
6561 tp->pcie_cap + PCI_EXP_DEVSTA,
6562 PCI_EXP_DEVSTA_CED |
6563 PCI_EXP_DEVSTA_NFED |
6564 PCI_EXP_DEVSTA_FED |
6565 PCI_EXP_DEVSTA_URD);
6566 }
6567
6568 tg3_restore_pci_state(tp);
6569
6570 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6571
6572 val = 0;
6573 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6574 val = tr32(MEMARB_MODE);
6575 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6576
6577 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6578 tg3_stop_fw(tp);
6579 tw32(0x5000, 0x400);
6580 }
6581
6582 tw32(GRC_MODE, tp->grc_mode);
6583
6584 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6585 val = tr32(0xc4);
6586
6587 tw32(0xc4, val | (1 << 15));
6588 }
6589
6590 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6591 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6592 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6593 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6594 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6595 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6596 }
6597
6598 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6599 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6600 tw32_f(MAC_MODE, tp->mac_mode);
6601 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6602 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6603 tw32_f(MAC_MODE, tp->mac_mode);
6604 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6605 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6606 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6607 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6608 tw32_f(MAC_MODE, tp->mac_mode);
6609 } else
6610 tw32_f(MAC_MODE, 0);
6611 udelay(40);
6612
6613 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6614
6615 err = tg3_poll_fw(tp);
6616 if (err)
6617 return err;
6618
6619 tg3_mdio_start(tp);
6620
6621 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6622 u8 phy_addr;
6623
6624 phy_addr = tp->phy_addr;
6625 tp->phy_addr = TG3_PHY_PCIE_ADDR;
6626
6627 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6628 TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
6629 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
6630 TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
6631 TG3_PCIEPHY_TX0CTRL1_NB_EN;
6632 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
6633 udelay(10);
6634
6635 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6636 TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
6637 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
6638 TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
6639 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
6640 udelay(10);
6641
6642 tp->phy_addr = phy_addr;
6643 }
6644
6645 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6646 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
6647 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6648 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
6649 val = tr32(0x7c00);
6650
6651 tw32(0x7c00, val | (1 << 25));
6652 }
6653
6654 /* Reprobe ASF enable state. */
6655 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6656 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6657 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6658 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6659 u32 nic_cfg;
6660
6661 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6662 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6663 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
6664 tp->last_event_jiffies = jiffies;
6665 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6666 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6667 }
6668 }
6669
6670 return 0;
6671 }
6672
6673 /* tp->lock is held. */
6674 static void tg3_stop_fw(struct tg3 *tp)
6675 {
6676 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6677 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
6678 /* Wait for RX cpu to ACK the previous event. */
6679 tg3_wait_for_event_ack(tp);
6680
6681 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
6682
6683 tg3_generate_fw_event(tp);
6684
6685 /* Wait for RX cpu to ACK this event. */
6686 tg3_wait_for_event_ack(tp);
6687 }
6688 }
6689
6690 /* tp->lock is held. */
6691 static int tg3_halt(struct tg3 *tp, int kind, int silent)
6692 {
6693 int err;
6694
6695 tg3_stop_fw(tp);
6696
6697 tg3_write_sig_pre_reset(tp, kind);
6698
6699 tg3_abort_hw(tp, silent);
6700 err = tg3_chip_reset(tp);
6701
6702 __tg3_set_mac_addr(tp, 0);
6703
6704 tg3_write_sig_legacy(tp, kind);
6705 tg3_write_sig_post_reset(tp, kind);
6706
6707 if (err)
6708 return err;
6709
6710 return 0;
6711 }
6712
6713 #define RX_CPU_SCRATCH_BASE 0x30000
6714 #define RX_CPU_SCRATCH_SIZE 0x04000
6715 #define TX_CPU_SCRATCH_BASE 0x34000
6716 #define TX_CPU_SCRATCH_SIZE 0x04000
6717
6718 /* tp->lock is held. */
6719 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6720 {
6721 int i;
6722
6723 BUG_ON(offset == TX_CPU_BASE &&
6724 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
6725
6726 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6727 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6728
6729 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6730 return 0;
6731 }
6732 if (offset == RX_CPU_BASE) {
6733 for (i = 0; i < 10000; i++) {
6734 tw32(offset + CPU_STATE, 0xffffffff);
6735 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6736 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6737 break;
6738 }
6739
6740 tw32(offset + CPU_STATE, 0xffffffff);
6741 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
6742 udelay(10);
6743 } else {
6744 for (i = 0; i < 10000; i++) {
6745 tw32(offset + CPU_STATE, 0xffffffff);
6746 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6747 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6748 break;
6749 }
6750 }
6751
6752 if (i >= 10000) {
6753 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6754 "and %s CPU\n",
6755 tp->dev->name,
6756 (offset == RX_CPU_BASE ? "RX" : "TX"));
6757 return -ENODEV;
6758 }
6759
6760 /* Clear firmware's nvram arbitration. */
6761 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6762 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
6763 return 0;
6764 }
6765
6766 struct fw_info {
6767 unsigned int fw_base;
6768 unsigned int fw_len;
6769 const __be32 *fw_data;
6770 };
6771
6772 /* tp->lock is held. */
6773 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6774 int cpu_scratch_size, struct fw_info *info)
6775 {
6776 int err, lock_err, i;
6777 void (*write_op)(struct tg3 *, u32, u32);
6778
6779 if (cpu_base == TX_CPU_BASE &&
6780 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6781 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6782 "TX cpu firmware on %s which is 5705.\n",
6783 tp->dev->name);
6784 return -EINVAL;
6785 }
6786
6787 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6788 write_op = tg3_write_mem;
6789 else
6790 write_op = tg3_write_indirect_reg32;
6791
6792 /* It is possible that bootcode is still loading at this point.
6793 * Get the nvram lock first before halting the cpu.
6794 */
6795 lock_err = tg3_nvram_lock(tp);
6796 err = tg3_halt_cpu(tp, cpu_base);
6797 if (!lock_err)
6798 tg3_nvram_unlock(tp);
6799 if (err)
6800 goto out;
6801
6802 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6803 write_op(tp, cpu_scratch_base + i, 0);
6804 tw32(cpu_base + CPU_STATE, 0xffffffff);
6805 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6806 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
6807 write_op(tp, (cpu_scratch_base +
6808 (info->fw_base & 0xffff) +
6809 (i * sizeof(u32))),
6810 be32_to_cpu(info->fw_data[i]));
6811
6812 err = 0;
6813
6814 out:
6815 return err;
6816 }
6817
6818 /* tp->lock is held. */
6819 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6820 {
6821 struct fw_info info;
6822 const __be32 *fw_data;
6823 int err, i;
6824
6825 fw_data = (void *)tp->fw->data;
6826
6827 /* Firmware blob starts with version numbers, followed by
6828 start address and length. We are setting complete length.
6829 length = end_address_of_bss - start_address_of_text.
6830 Remainder is the blob to be loaded contiguously
6831 from start address. */
6832
6833 info.fw_base = be32_to_cpu(fw_data[1]);
6834 info.fw_len = tp->fw->size - 12;
6835 info.fw_data = &fw_data[3];
6836
6837 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6838 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6839 &info);
6840 if (err)
6841 return err;
6842
6843 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6844 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6845 &info);
6846 if (err)
6847 return err;
6848
6849 /* Now startup only the RX cpu. */
6850 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6851 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6852
6853 for (i = 0; i < 5; i++) {
6854 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
6855 break;
6856 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6857 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
6858 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6859 udelay(1000);
6860 }
6861 if (i >= 5) {
6862 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6863 "to set RX CPU PC, is %08x should be %08x\n",
6864 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6865 info.fw_base);
6866 return -ENODEV;
6867 }
6868 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6869 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
6870
6871 return 0;
6872 }
6873
6874 /* 5705 needs a special version of the TSO firmware. */
6875
6876 /* tp->lock is held. */
6877 static int tg3_load_tso_firmware(struct tg3 *tp)
6878 {
6879 struct fw_info info;
6880 const __be32 *fw_data;
6881 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6882 int err, i;
6883
6884 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6885 return 0;
6886
6887 fw_data = (void *)tp->fw->data;
6888
6889 /* Firmware blob starts with version numbers, followed by
6890 start address and length. We are setting complete length.
6891 length = end_address_of_bss - start_address_of_text.
6892 Remainder is the blob to be loaded contiguously
6893 from start address. */
6894
6895 info.fw_base = be32_to_cpu(fw_data[1]);
6896 cpu_scratch_size = tp->fw_len;
6897 info.fw_len = tp->fw->size - 12;
6898 info.fw_data = &fw_data[3];
6899
6900 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6901 cpu_base = RX_CPU_BASE;
6902 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6903 } else {
6904 cpu_base = TX_CPU_BASE;
6905 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6906 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6907 }
6908
6909 err = tg3_load_firmware_cpu(tp, cpu_base,
6910 cpu_scratch_base, cpu_scratch_size,
6911 &info);
6912 if (err)
6913 return err;
6914
6915 /* Now startup the cpu. */
6916 tw32(cpu_base + CPU_STATE, 0xffffffff);
6917 tw32_f(cpu_base + CPU_PC, info.fw_base);
6918
6919 for (i = 0; i < 5; i++) {
6920 if (tr32(cpu_base + CPU_PC) == info.fw_base)
6921 break;
6922 tw32(cpu_base + CPU_STATE, 0xffffffff);
6923 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
6924 tw32_f(cpu_base + CPU_PC, info.fw_base);
6925 udelay(1000);
6926 }
6927 if (i >= 5) {
6928 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6929 "to set CPU PC, is %08x should be %08x\n",
6930 tp->dev->name, tr32(cpu_base + CPU_PC),
6931 info.fw_base);
6932 return -ENODEV;
6933 }
6934 tw32(cpu_base + CPU_STATE, 0xffffffff);
6935 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6936 return 0;
6937 }
6938
6939
6940 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6941 {
6942 struct tg3 *tp = netdev_priv(dev);
6943 struct sockaddr *addr = p;
6944 int err = 0, skip_mac_1 = 0;
6945
6946 if (!is_valid_ether_addr(addr->sa_data))
6947 return -EINVAL;
6948
6949 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6950
6951 if (!netif_running(dev))
6952 return 0;
6953
6954 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6955 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6956
6957 addr0_high = tr32(MAC_ADDR_0_HIGH);
6958 addr0_low = tr32(MAC_ADDR_0_LOW);
6959 addr1_high = tr32(MAC_ADDR_1_HIGH);
6960 addr1_low = tr32(MAC_ADDR_1_LOW);
6961
6962 /* Skip MAC addr 1 if ASF is using it. */
6963 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6964 !(addr1_high == 0 && addr1_low == 0))
6965 skip_mac_1 = 1;
6966 }
6967 spin_lock_bh(&tp->lock);
6968 __tg3_set_mac_addr(tp, skip_mac_1);
6969 spin_unlock_bh(&tp->lock);
6970
6971 return err;
6972 }
6973
6974 /* tp->lock is held. */
6975 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6976 dma_addr_t mapping, u32 maxlen_flags,
6977 u32 nic_addr)
6978 {
6979 tg3_write_mem(tp,
6980 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6981 ((u64) mapping >> 32));
6982 tg3_write_mem(tp,
6983 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6984 ((u64) mapping & 0xffffffff));
6985 tg3_write_mem(tp,
6986 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6987 maxlen_flags);
6988
6989 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6990 tg3_write_mem(tp,
6991 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6992 nic_addr);
6993 }
6994
6995 static void __tg3_set_rx_mode(struct net_device *);
6996 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6997 {
6998 int i;
6999
7000 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7001 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7002 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7003 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7004
7005 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7006 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7007 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7008 } else {
7009 tw32(HOSTCC_TXCOL_TICKS, 0);
7010 tw32(HOSTCC_TXMAX_FRAMES, 0);
7011 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7012
7013 tw32(HOSTCC_RXCOL_TICKS, 0);
7014 tw32(HOSTCC_RXMAX_FRAMES, 0);
7015 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7016 }
7017
7018 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7019 u32 val = ec->stats_block_coalesce_usecs;
7020
7021 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7022 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7023
7024 if (!netif_carrier_ok(tp->dev))
7025 val = 0;
7026
7027 tw32(HOSTCC_STAT_COAL_TICKS, val);
7028 }
7029
7030 for (i = 0; i < tp->irq_cnt - 1; i++) {
7031 u32 reg;
7032
7033 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7034 tw32(reg, ec->rx_coalesce_usecs);
7035 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7036 tw32(reg, ec->tx_coalesce_usecs);
7037 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7038 tw32(reg, ec->rx_max_coalesced_frames);
7039 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7040 tw32(reg, ec->tx_max_coalesced_frames);
7041 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7042 tw32(reg, ec->rx_max_coalesced_frames_irq);
7043 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7044 tw32(reg, ec->tx_max_coalesced_frames_irq);
7045 }
7046
7047 for (; i < tp->irq_max - 1; i++) {
7048 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7049 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7050 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7051 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7052 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7053 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7054 }
7055 }
7056
7057 /* tp->lock is held. */
7058 static void tg3_rings_reset(struct tg3 *tp)
7059 {
7060 int i;
7061 u32 stblk, txrcb, rxrcb, limit;
7062 struct tg3_napi *tnapi = &tp->napi[0];
7063
7064 /* Disable all transmit rings but the first. */
7065 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7066 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7067 else
7068 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7069
7070 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7071 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7072 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7073 BDINFO_FLAGS_DISABLED);
7074
7075
7076 /* Disable all receive return rings but the first. */
7077 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7078 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7079 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7080 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7081 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7082 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7083 else
7084 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7085
7086 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7087 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7088 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7089 BDINFO_FLAGS_DISABLED);
7090
7091 /* Disable interrupts */
7092 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7093
7094 /* Zero mailbox registers. */
7095 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7096 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7097 tp->napi[i].tx_prod = 0;
7098 tp->napi[i].tx_cons = 0;
7099 tw32_mailbox(tp->napi[i].prodmbox, 0);
7100 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7101 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7102 }
7103 } else {
7104 tp->napi[0].tx_prod = 0;
7105 tp->napi[0].tx_cons = 0;
7106 tw32_mailbox(tp->napi[0].prodmbox, 0);
7107 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7108 }
7109
7110 /* Make sure the NIC-based send BD rings are disabled. */
7111 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7112 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7113 for (i = 0; i < 16; i++)
7114 tw32_tx_mbox(mbox + i * 8, 0);
7115 }
7116
7117 txrcb = NIC_SRAM_SEND_RCB;
7118 rxrcb = NIC_SRAM_RCV_RET_RCB;
7119
7120 /* Clear status block in ram. */
7121 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7122
7123 /* Set status block DMA address */
7124 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7125 ((u64) tnapi->status_mapping >> 32));
7126 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7127 ((u64) tnapi->status_mapping & 0xffffffff));
7128
7129 if (tnapi->tx_ring) {
7130 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7131 (TG3_TX_RING_SIZE <<
7132 BDINFO_FLAGS_MAXLEN_SHIFT),
7133 NIC_SRAM_TX_BUFFER_DESC);
7134 txrcb += TG3_BDINFO_SIZE;
7135 }
7136
7137 if (tnapi->rx_rcb) {
7138 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7139 (TG3_RX_RCB_RING_SIZE(tp) <<
7140 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7141 rxrcb += TG3_BDINFO_SIZE;
7142 }
7143
7144 stblk = HOSTCC_STATBLCK_RING1;
7145
7146 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7147 u64 mapping = (u64)tnapi->status_mapping;
7148 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7149 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7150
7151 /* Clear status block in ram. */
7152 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7153
7154 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7155 (TG3_TX_RING_SIZE <<
7156 BDINFO_FLAGS_MAXLEN_SHIFT),
7157 NIC_SRAM_TX_BUFFER_DESC);
7158
7159 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7160 (TG3_RX_RCB_RING_SIZE(tp) <<
7161 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7162
7163 stblk += 8;
7164 txrcb += TG3_BDINFO_SIZE;
7165 rxrcb += TG3_BDINFO_SIZE;
7166 }
7167 }
7168
7169 /* tp->lock is held. */
7170 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7171 {
7172 u32 val, rdmac_mode;
7173 int i, err, limit;
7174 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7175
7176 tg3_disable_ints(tp);
7177
7178 tg3_stop_fw(tp);
7179
7180 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7181
7182 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
7183 tg3_abort_hw(tp, 1);
7184 }
7185
7186 if (reset_phy &&
7187 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
7188 tg3_phy_reset(tp);
7189
7190 err = tg3_chip_reset(tp);
7191 if (err)
7192 return err;
7193
7194 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7195
7196 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7197 val = tr32(TG3_CPMU_CTRL);
7198 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7199 tw32(TG3_CPMU_CTRL, val);
7200
7201 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7202 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7203 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7204 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7205
7206 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7207 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7208 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7209 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7210
7211 val = tr32(TG3_CPMU_HST_ACC);
7212 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7213 val |= CPMU_HST_ACC_MACCLK_6_25;
7214 tw32(TG3_CPMU_HST_ACC, val);
7215 }
7216
7217 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7218 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7219 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7220 PCIE_PWR_MGMT_L1_THRESH_4MS;
7221 tw32(PCIE_PWR_MGMT_THRESH, val);
7222
7223 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7224 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7225
7226 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7227
7228 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7229 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7230 }
7231
7232 /* This works around an issue with Athlon chipsets on
7233 * B3 tigon3 silicon. This bit has no effect on any
7234 * other revision. But do not set this on PCI Express
7235 * chips and don't even touch the clocks if the CPMU is present.
7236 */
7237 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7238 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7239 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7240 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7241 }
7242
7243 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7244 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7245 val = tr32(TG3PCI_PCISTATE);
7246 val |= PCISTATE_RETRY_SAME_DMA;
7247 tw32(TG3PCI_PCISTATE, val);
7248 }
7249
7250 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7251 /* Allow reads and writes to the
7252 * APE register and memory space.
7253 */
7254 val = tr32(TG3PCI_PCISTATE);
7255 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7256 PCISTATE_ALLOW_APE_SHMEM_WR;
7257 tw32(TG3PCI_PCISTATE, val);
7258 }
7259
7260 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7261 /* Enable some hw fixes. */
7262 val = tr32(TG3PCI_MSI_DATA);
7263 val |= (1 << 26) | (1 << 28) | (1 << 29);
7264 tw32(TG3PCI_MSI_DATA, val);
7265 }
7266
7267 /* Descriptor ring init may make accesses to the
7268 * NIC SRAM area to setup the TX descriptors, so we
7269 * can only do this after the hardware has been
7270 * successfully reset.
7271 */
7272 err = tg3_init_rings(tp);
7273 if (err)
7274 return err;
7275
7276 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7277 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 &&
7278 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
7279 /* This value is determined during the probe time DMA
7280 * engine test, tg3_test_dma.
7281 */
7282 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7283 }
7284
7285 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7286 GRC_MODE_4X_NIC_SEND_RINGS |
7287 GRC_MODE_NO_TX_PHDR_CSUM |
7288 GRC_MODE_NO_RX_PHDR_CSUM);
7289 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7290
7291 /* Pseudo-header checksum is done by hardware logic and not
7292 * the offload processers, so make the chip do the pseudo-
7293 * header checksums on receive. For transmit it is more
7294 * convenient to do the pseudo-header checksum in software
7295 * as Linux does that on transmit for us in all cases.
7296 */
7297 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7298
7299 tw32(GRC_MODE,
7300 tp->grc_mode |
7301 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7302
7303 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7304 val = tr32(GRC_MISC_CFG);
7305 val &= ~0xff;
7306 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7307 tw32(GRC_MISC_CFG, val);
7308
7309 /* Initialize MBUF/DESC pool. */
7310 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7311 /* Do nothing. */
7312 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7313 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7314 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7315 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7316 else
7317 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7318 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7319 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7320 }
7321 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7322 int fw_len;
7323
7324 fw_len = tp->fw_len;
7325 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7326 tw32(BUFMGR_MB_POOL_ADDR,
7327 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7328 tw32(BUFMGR_MB_POOL_SIZE,
7329 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7330 }
7331
7332 if (tp->dev->mtu <= ETH_DATA_LEN) {
7333 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7334 tp->bufmgr_config.mbuf_read_dma_low_water);
7335 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7336 tp->bufmgr_config.mbuf_mac_rx_low_water);
7337 tw32(BUFMGR_MB_HIGH_WATER,
7338 tp->bufmgr_config.mbuf_high_water);
7339 } else {
7340 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7341 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7342 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7343 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7344 tw32(BUFMGR_MB_HIGH_WATER,
7345 tp->bufmgr_config.mbuf_high_water_jumbo);
7346 }
7347 tw32(BUFMGR_DMA_LOW_WATER,
7348 tp->bufmgr_config.dma_low_water);
7349 tw32(BUFMGR_DMA_HIGH_WATER,
7350 tp->bufmgr_config.dma_high_water);
7351
7352 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7353 for (i = 0; i < 2000; i++) {
7354 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7355 break;
7356 udelay(10);
7357 }
7358 if (i >= 2000) {
7359 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7360 tp->dev->name);
7361 return -ENODEV;
7362 }
7363
7364 /* Setup replenish threshold. */
7365 val = tp->rx_pending / 8;
7366 if (val == 0)
7367 val = 1;
7368 else if (val > tp->rx_std_max_post)
7369 val = tp->rx_std_max_post;
7370 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7371 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7372 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7373
7374 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7375 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7376 }
7377
7378 tw32(RCVBDI_STD_THRESH, val);
7379
7380 /* Initialize TG3_BDINFO's at:
7381 * RCVDBDI_STD_BD: standard eth size rx ring
7382 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7383 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7384 *
7385 * like so:
7386 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7387 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7388 * ring attribute flags
7389 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7390 *
7391 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7392 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7393 *
7394 * The size of each ring is fixed in the firmware, but the location is
7395 * configurable.
7396 */
7397 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7398 ((u64) tpr->rx_std_mapping >> 32));
7399 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7400 ((u64) tpr->rx_std_mapping & 0xffffffff));
7401 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7402 NIC_SRAM_RX_BUFFER_DESC);
7403
7404 /* Disable the mini ring */
7405 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7406 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7407 BDINFO_FLAGS_DISABLED);
7408
7409 /* Program the jumbo buffer descriptor ring control
7410 * blocks on those devices that have them.
7411 */
7412 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7413 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7414 /* Setup replenish threshold. */
7415 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7416
7417 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7418 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7419 ((u64) tpr->rx_jmb_mapping >> 32));
7420 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7421 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7422 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7423 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7424 BDINFO_FLAGS_USE_EXT_RECV);
7425 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7426 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7427 } else {
7428 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7429 BDINFO_FLAGS_DISABLED);
7430 }
7431
7432 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7433 val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7434 (RX_STD_MAX_SIZE << 2);
7435 else
7436 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7437 } else
7438 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7439
7440 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7441
7442 tpr->rx_std_ptr = tp->rx_pending;
7443 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
7444 tpr->rx_std_ptr);
7445
7446 tpr->rx_jmb_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7447 tp->rx_jumbo_pending : 0;
7448 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
7449 tpr->rx_jmb_ptr);
7450
7451 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
7452 tw32(STD_REPLENISH_LWM, 32);
7453 tw32(JMB_REPLENISH_LWM, 16);
7454 }
7455
7456 tg3_rings_reset(tp);
7457
7458 /* Initialize MAC address and backoff seed. */
7459 __tg3_set_mac_addr(tp, 0);
7460
7461 /* MTU + ethernet header + FCS + optional VLAN tag */
7462 tw32(MAC_RX_MTU_SIZE,
7463 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7464
7465 /* The slot time is changed by tg3_setup_phy if we
7466 * run at gigabit with half duplex.
7467 */
7468 tw32(MAC_TX_LENGTHS,
7469 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7470 (6 << TX_LENGTHS_IPG_SHIFT) |
7471 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7472
7473 /* Receive rules. */
7474 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7475 tw32(RCVLPC_CONFIG, 0x0181);
7476
7477 /* Calculate RDMAC_MODE setting early, we need it to determine
7478 * the RCVLPC_STATE_ENABLE mask.
7479 */
7480 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7481 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7482 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7483 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7484 RDMAC_MODE_LNGREAD_ENAB);
7485
7486 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7487 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7488 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7489 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7490 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7491 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7492
7493 /* If statement applies to 5705 and 5750 PCI devices only */
7494 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7495 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7496 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7497 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7498 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7499 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7500 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7501 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7502 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7503 }
7504 }
7505
7506 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7507 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7508
7509 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7510 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7511
7512 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7513 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7514 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7515
7516 /* Receive/send statistics. */
7517 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7518 val = tr32(RCVLPC_STATS_ENABLE);
7519 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7520 tw32(RCVLPC_STATS_ENABLE, val);
7521 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7522 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7523 val = tr32(RCVLPC_STATS_ENABLE);
7524 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7525 tw32(RCVLPC_STATS_ENABLE, val);
7526 } else {
7527 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7528 }
7529 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7530 tw32(SNDDATAI_STATSENAB, 0xffffff);
7531 tw32(SNDDATAI_STATSCTRL,
7532 (SNDDATAI_SCTRL_ENABLE |
7533 SNDDATAI_SCTRL_FASTUPD));
7534
7535 /* Setup host coalescing engine. */
7536 tw32(HOSTCC_MODE, 0);
7537 for (i = 0; i < 2000; i++) {
7538 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7539 break;
7540 udelay(10);
7541 }
7542
7543 __tg3_set_coalesce(tp, &tp->coal);
7544
7545 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7546 /* Status/statistics block address. See tg3_timer,
7547 * the tg3_periodic_fetch_stats call there, and
7548 * tg3_get_stats to see how this works for 5705/5750 chips.
7549 */
7550 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7551 ((u64) tp->stats_mapping >> 32));
7552 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7553 ((u64) tp->stats_mapping & 0xffffffff));
7554 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7555
7556 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7557
7558 /* Clear statistics and status block memory areas */
7559 for (i = NIC_SRAM_STATS_BLK;
7560 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7561 i += sizeof(u32)) {
7562 tg3_write_mem(tp, i, 0);
7563 udelay(40);
7564 }
7565 }
7566
7567 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7568
7569 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7570 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7571 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7572 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7573
7574 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7575 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7576 /* reset to prevent losing 1st rx packet intermittently */
7577 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7578 udelay(10);
7579 }
7580
7581 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7582 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7583 else
7584 tp->mac_mode = 0;
7585 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7586 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7587 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7588 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7589 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7590 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7591 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7592 udelay(40);
7593
7594 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7595 * If TG3_FLG2_IS_NIC is zero, we should read the
7596 * register to preserve the GPIO settings for LOMs. The GPIOs,
7597 * whether used as inputs or outputs, are set by boot code after
7598 * reset.
7599 */
7600 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7601 u32 gpio_mask;
7602
7603 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7604 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7605 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7606
7607 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7608 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7609 GRC_LCLCTRL_GPIO_OUTPUT3;
7610
7611 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7612 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7613
7614 tp->grc_local_ctrl &= ~gpio_mask;
7615 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7616
7617 /* GPIO1 must be driven high for eeprom write protect */
7618 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7619 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7620 GRC_LCLCTRL_GPIO_OUTPUT1);
7621 }
7622 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7623 udelay(100);
7624
7625 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
7626 val = tr32(MSGINT_MODE);
7627 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
7628 tw32(MSGINT_MODE, val);
7629 }
7630
7631 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7632 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7633 udelay(40);
7634 }
7635
7636 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7637 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7638 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7639 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7640 WDMAC_MODE_LNGREAD_ENAB);
7641
7642 /* If statement applies to 5705 and 5750 PCI devices only */
7643 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7644 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7645 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7646 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
7647 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7648 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7649 /* nothing */
7650 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7651 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7652 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7653 val |= WDMAC_MODE_RX_ACCEL;
7654 }
7655 }
7656
7657 /* Enable host coalescing bug fix */
7658 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7659 val |= WDMAC_MODE_STATUS_TAG_FIX;
7660
7661 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
7662 val |= WDMAC_MODE_BURST_ALL_DATA;
7663
7664 tw32_f(WDMAC_MODE, val);
7665 udelay(40);
7666
7667 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7668 u16 pcix_cmd;
7669
7670 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7671 &pcix_cmd);
7672 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7673 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7674 pcix_cmd |= PCI_X_CMD_READ_2K;
7675 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7676 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7677 pcix_cmd |= PCI_X_CMD_READ_2K;
7678 }
7679 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7680 pcix_cmd);
7681 }
7682
7683 tw32_f(RDMAC_MODE, rdmac_mode);
7684 udelay(40);
7685
7686 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7687 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7688 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7689
7690 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7691 tw32(SNDDATAC_MODE,
7692 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7693 else
7694 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7695
7696 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7697 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7698 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7699 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7700 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7701 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7702 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
7703 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
7704 val |= SNDBDI_MODE_MULTI_TXQ_EN;
7705 tw32(SNDBDI_MODE, val);
7706 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7707
7708 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7709 err = tg3_load_5701_a0_firmware_fix(tp);
7710 if (err)
7711 return err;
7712 }
7713
7714 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7715 err = tg3_load_tso_firmware(tp);
7716 if (err)
7717 return err;
7718 }
7719
7720 tp->tx_mode = TX_MODE_ENABLE;
7721 tw32_f(MAC_TX_MODE, tp->tx_mode);
7722 udelay(100);
7723
7724 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
7725 u32 reg = MAC_RSS_INDIR_TBL_0;
7726 u8 *ent = (u8 *)&val;
7727
7728 /* Setup the indirection table */
7729 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
7730 int idx = i % sizeof(val);
7731
7732 ent[idx] = i % (tp->irq_cnt - 1);
7733 if (idx == sizeof(val) - 1) {
7734 tw32(reg, val);
7735 reg += 4;
7736 }
7737 }
7738
7739 /* Setup the "secret" hash key. */
7740 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
7741 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
7742 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
7743 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
7744 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
7745 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
7746 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
7747 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
7748 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
7749 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
7750 }
7751
7752 tp->rx_mode = RX_MODE_ENABLE;
7753 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7754 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7755
7756 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
7757 tp->rx_mode |= RX_MODE_RSS_ENABLE |
7758 RX_MODE_RSS_ITBL_HASH_BITS_7 |
7759 RX_MODE_RSS_IPV6_HASH_EN |
7760 RX_MODE_RSS_TCP_IPV6_HASH_EN |
7761 RX_MODE_RSS_IPV4_HASH_EN |
7762 RX_MODE_RSS_TCP_IPV4_HASH_EN;
7763
7764 tw32_f(MAC_RX_MODE, tp->rx_mode);
7765 udelay(10);
7766
7767 tw32(MAC_LED_CTRL, tp->led_ctrl);
7768
7769 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7770 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7771 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7772 udelay(10);
7773 }
7774 tw32_f(MAC_RX_MODE, tp->rx_mode);
7775 udelay(10);
7776
7777 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7778 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7779 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7780 /* Set drive transmission level to 1.2V */
7781 /* only if the signal pre-emphasis bit is not set */
7782 val = tr32(MAC_SERDES_CFG);
7783 val &= 0xfffff000;
7784 val |= 0x880;
7785 tw32(MAC_SERDES_CFG, val);
7786 }
7787 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7788 tw32(MAC_SERDES_CFG, 0x616000);
7789 }
7790
7791 /* Prevent chip from dropping frames when flow control
7792 * is enabled.
7793 */
7794 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7795
7796 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7797 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7798 /* Use hardware link auto-negotiation */
7799 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7800 }
7801
7802 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7803 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7804 u32 tmp;
7805
7806 tmp = tr32(SERDES_RX_CTRL);
7807 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7808 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7809 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7810 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7811 }
7812
7813 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7814 if (tp->link_config.phy_is_low_power) {
7815 tp->link_config.phy_is_low_power = 0;
7816 tp->link_config.speed = tp->link_config.orig_speed;
7817 tp->link_config.duplex = tp->link_config.orig_duplex;
7818 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7819 }
7820
7821 err = tg3_setup_phy(tp, 0);
7822 if (err)
7823 return err;
7824
7825 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7826 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
7827 u32 tmp;
7828
7829 /* Clear CRC stats. */
7830 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7831 tg3_writephy(tp, MII_TG3_TEST1,
7832 tmp | MII_TG3_TEST1_CRC_EN);
7833 tg3_readphy(tp, 0x14, &tmp);
7834 }
7835 }
7836 }
7837
7838 __tg3_set_rx_mode(tp->dev);
7839
7840 /* Initialize receive rules. */
7841 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7842 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7843 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7844 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7845
7846 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7847 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7848 limit = 8;
7849 else
7850 limit = 16;
7851 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7852 limit -= 4;
7853 switch (limit) {
7854 case 16:
7855 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7856 case 15:
7857 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7858 case 14:
7859 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7860 case 13:
7861 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7862 case 12:
7863 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7864 case 11:
7865 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7866 case 10:
7867 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7868 case 9:
7869 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7870 case 8:
7871 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7872 case 7:
7873 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7874 case 6:
7875 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7876 case 5:
7877 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7878 case 4:
7879 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7880 case 3:
7881 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7882 case 2:
7883 case 1:
7884
7885 default:
7886 break;
7887 }
7888
7889 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7890 /* Write our heartbeat update interval to APE. */
7891 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7892 APE_HOST_HEARTBEAT_INT_DISABLE);
7893
7894 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7895
7896 return 0;
7897 }
7898
7899 /* Called at device open time to get the chip ready for
7900 * packet processing. Invoked with tp->lock held.
7901 */
7902 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7903 {
7904 tg3_switch_clocks(tp);
7905
7906 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7907
7908 return tg3_reset_hw(tp, reset_phy);
7909 }
7910
7911 #define TG3_STAT_ADD32(PSTAT, REG) \
7912 do { u32 __val = tr32(REG); \
7913 (PSTAT)->low += __val; \
7914 if ((PSTAT)->low < __val) \
7915 (PSTAT)->high += 1; \
7916 } while (0)
7917
7918 static void tg3_periodic_fetch_stats(struct tg3 *tp)
7919 {
7920 struct tg3_hw_stats *sp = tp->hw_stats;
7921
7922 if (!netif_carrier_ok(tp->dev))
7923 return;
7924
7925 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7926 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7927 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7928 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7929 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7930 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7931 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7932 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7933 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7934 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7935 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7936 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7937 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7938
7939 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7940 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7941 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7942 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7943 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7944 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7945 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7946 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7947 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7948 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7949 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7950 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7951 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7952 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
7953
7954 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7955 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7956 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
7957 }
7958
7959 static void tg3_timer(unsigned long __opaque)
7960 {
7961 struct tg3 *tp = (struct tg3 *) __opaque;
7962
7963 if (tp->irq_sync)
7964 goto restart_timer;
7965
7966 spin_lock(&tp->lock);
7967
7968 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7969 /* All of this garbage is because when using non-tagged
7970 * IRQ status the mailbox/status_block protocol the chip
7971 * uses with the cpu is race prone.
7972 */
7973 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
7974 tw32(GRC_LOCAL_CTRL,
7975 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7976 } else {
7977 tw32(HOSTCC_MODE, tp->coalesce_mode |
7978 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
7979 }
7980
7981 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7982 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
7983 spin_unlock(&tp->lock);
7984 schedule_work(&tp->reset_task);
7985 return;
7986 }
7987 }
7988
7989 /* This part only runs once per second. */
7990 if (!--tp->timer_counter) {
7991 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7992 tg3_periodic_fetch_stats(tp);
7993
7994 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7995 u32 mac_stat;
7996 int phy_event;
7997
7998 mac_stat = tr32(MAC_STATUS);
7999
8000 phy_event = 0;
8001 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8002 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8003 phy_event = 1;
8004 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8005 phy_event = 1;
8006
8007 if (phy_event)
8008 tg3_setup_phy(tp, 0);
8009 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8010 u32 mac_stat = tr32(MAC_STATUS);
8011 int need_setup = 0;
8012
8013 if (netif_carrier_ok(tp->dev) &&
8014 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8015 need_setup = 1;
8016 }
8017 if (! netif_carrier_ok(tp->dev) &&
8018 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8019 MAC_STATUS_SIGNAL_DET))) {
8020 need_setup = 1;
8021 }
8022 if (need_setup) {
8023 if (!tp->serdes_counter) {
8024 tw32_f(MAC_MODE,
8025 (tp->mac_mode &
8026 ~MAC_MODE_PORT_MODE_MASK));
8027 udelay(40);
8028 tw32_f(MAC_MODE, tp->mac_mode);
8029 udelay(40);
8030 }
8031 tg3_setup_phy(tp, 0);
8032 }
8033 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8034 tg3_serdes_parallel_detect(tp);
8035
8036 tp->timer_counter = tp->timer_multiplier;
8037 }
8038
8039 /* Heartbeat is only sent once every 2 seconds.
8040 *
8041 * The heartbeat is to tell the ASF firmware that the host
8042 * driver is still alive. In the event that the OS crashes,
8043 * ASF needs to reset the hardware to free up the FIFO space
8044 * that may be filled with rx packets destined for the host.
8045 * If the FIFO is full, ASF will no longer function properly.
8046 *
8047 * Unintended resets have been reported on real time kernels
8048 * where the timer doesn't run on time. Netpoll will also have
8049 * same problem.
8050 *
8051 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8052 * to check the ring condition when the heartbeat is expiring
8053 * before doing the reset. This will prevent most unintended
8054 * resets.
8055 */
8056 if (!--tp->asf_counter) {
8057 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8058 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8059 tg3_wait_for_event_ack(tp);
8060
8061 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8062 FWCMD_NICDRV_ALIVE3);
8063 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8064 /* 5 seconds timeout */
8065 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
8066
8067 tg3_generate_fw_event(tp);
8068 }
8069 tp->asf_counter = tp->asf_multiplier;
8070 }
8071
8072 spin_unlock(&tp->lock);
8073
8074 restart_timer:
8075 tp->timer.expires = jiffies + tp->timer_offset;
8076 add_timer(&tp->timer);
8077 }
8078
8079 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8080 {
8081 irq_handler_t fn;
8082 unsigned long flags;
8083 char *name;
8084 struct tg3_napi *tnapi = &tp->napi[irq_num];
8085
8086 if (tp->irq_cnt == 1)
8087 name = tp->dev->name;
8088 else {
8089 name = &tnapi->irq_lbl[0];
8090 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8091 name[IFNAMSIZ-1] = 0;
8092 }
8093
8094 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8095 fn = tg3_msi;
8096 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8097 fn = tg3_msi_1shot;
8098 flags = IRQF_SAMPLE_RANDOM;
8099 } else {
8100 fn = tg3_interrupt;
8101 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8102 fn = tg3_interrupt_tagged;
8103 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8104 }
8105
8106 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8107 }
8108
8109 static int tg3_test_interrupt(struct tg3 *tp)
8110 {
8111 struct tg3_napi *tnapi = &tp->napi[0];
8112 struct net_device *dev = tp->dev;
8113 int err, i, intr_ok = 0;
8114 u32 val;
8115
8116 if (!netif_running(dev))
8117 return -ENODEV;
8118
8119 tg3_disable_ints(tp);
8120
8121 free_irq(tnapi->irq_vec, tnapi);
8122
8123 /*
8124 * Turn off MSI one shot mode. Otherwise this test has no
8125 * observable way to know whether the interrupt was delivered.
8126 */
8127 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8128 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8129 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8130 tw32(MSGINT_MODE, val);
8131 }
8132
8133 err = request_irq(tnapi->irq_vec, tg3_test_isr,
8134 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8135 if (err)
8136 return err;
8137
8138 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8139 tg3_enable_ints(tp);
8140
8141 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8142 tnapi->coal_now);
8143
8144 for (i = 0; i < 5; i++) {
8145 u32 int_mbox, misc_host_ctrl;
8146
8147 int_mbox = tr32_mailbox(tnapi->int_mbox);
8148 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8149
8150 if ((int_mbox != 0) ||
8151 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8152 intr_ok = 1;
8153 break;
8154 }
8155
8156 msleep(10);
8157 }
8158
8159 tg3_disable_ints(tp);
8160
8161 free_irq(tnapi->irq_vec, tnapi);
8162
8163 err = tg3_request_irq(tp, 0);
8164
8165 if (err)
8166 return err;
8167
8168 if (intr_ok) {
8169 /* Reenable MSI one shot mode. */
8170 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8171 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8172 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8173 tw32(MSGINT_MODE, val);
8174 }
8175 return 0;
8176 }
8177
8178 return -EIO;
8179 }
8180
8181 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8182 * successfully restored
8183 */
8184 static int tg3_test_msi(struct tg3 *tp)
8185 {
8186 int err;
8187 u16 pci_cmd;
8188
8189 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8190 return 0;
8191
8192 /* Turn off SERR reporting in case MSI terminates with Master
8193 * Abort.
8194 */
8195 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8196 pci_write_config_word(tp->pdev, PCI_COMMAND,
8197 pci_cmd & ~PCI_COMMAND_SERR);
8198
8199 err = tg3_test_interrupt(tp);
8200
8201 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8202
8203 if (!err)
8204 return 0;
8205
8206 /* other failures */
8207 if (err != -EIO)
8208 return err;
8209
8210 /* MSI test failed, go back to INTx mode */
8211 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8212 "switching to INTx mode. Please report this failure to "
8213 "the PCI maintainer and include system chipset information.\n",
8214 tp->dev->name);
8215
8216 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8217
8218 pci_disable_msi(tp->pdev);
8219
8220 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8221
8222 err = tg3_request_irq(tp, 0);
8223 if (err)
8224 return err;
8225
8226 /* Need to reset the chip because the MSI cycle may have terminated
8227 * with Master Abort.
8228 */
8229 tg3_full_lock(tp, 1);
8230
8231 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8232 err = tg3_init_hw(tp, 1);
8233
8234 tg3_full_unlock(tp);
8235
8236 if (err)
8237 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8238
8239 return err;
8240 }
8241
8242 static int tg3_request_firmware(struct tg3 *tp)
8243 {
8244 const __be32 *fw_data;
8245
8246 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8247 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8248 tp->dev->name, tp->fw_needed);
8249 return -ENOENT;
8250 }
8251
8252 fw_data = (void *)tp->fw->data;
8253
8254 /* Firmware blob starts with version numbers, followed by
8255 * start address and _full_ length including BSS sections
8256 * (which must be longer than the actual data, of course
8257 */
8258
8259 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
8260 if (tp->fw_len < (tp->fw->size - 12)) {
8261 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8262 tp->dev->name, tp->fw_len, tp->fw_needed);
8263 release_firmware(tp->fw);
8264 tp->fw = NULL;
8265 return -EINVAL;
8266 }
8267
8268 /* We no longer need firmware; we have it. */
8269 tp->fw_needed = NULL;
8270 return 0;
8271 }
8272
8273 static bool tg3_enable_msix(struct tg3 *tp)
8274 {
8275 int i, rc, cpus = num_online_cpus();
8276 struct msix_entry msix_ent[tp->irq_max];
8277
8278 if (cpus == 1)
8279 /* Just fallback to the simpler MSI mode. */
8280 return false;
8281
8282 /*
8283 * We want as many rx rings enabled as there are cpus.
8284 * The first MSIX vector only deals with link interrupts, etc,
8285 * so we add one to the number of vectors we are requesting.
8286 */
8287 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8288
8289 for (i = 0; i < tp->irq_max; i++) {
8290 msix_ent[i].entry = i;
8291 msix_ent[i].vector = 0;
8292 }
8293
8294 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8295 if (rc != 0) {
8296 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8297 return false;
8298 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8299 return false;
8300 printk(KERN_NOTICE
8301 "%s: Requested %d MSI-X vectors, received %d\n",
8302 tp->dev->name, tp->irq_cnt, rc);
8303 tp->irq_cnt = rc;
8304 }
8305
8306 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8307
8308 for (i = 0; i < tp->irq_max; i++)
8309 tp->napi[i].irq_vec = msix_ent[i].vector;
8310
8311 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8312
8313 return true;
8314 }
8315
8316 static void tg3_ints_init(struct tg3 *tp)
8317 {
8318 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8319 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8320 /* All MSI supporting chips should support tagged
8321 * status. Assert that this is the case.
8322 */
8323 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8324 "Not using MSI.\n", tp->dev->name);
8325 goto defcfg;
8326 }
8327
8328 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8329 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8330 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8331 pci_enable_msi(tp->pdev) == 0)
8332 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8333
8334 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8335 u32 msi_mode = tr32(MSGINT_MODE);
8336 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8337 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8338 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8339 }
8340 defcfg:
8341 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8342 tp->irq_cnt = 1;
8343 tp->napi[0].irq_vec = tp->pdev->irq;
8344 tp->dev->real_num_tx_queues = 1;
8345 }
8346 }
8347
8348 static void tg3_ints_fini(struct tg3 *tp)
8349 {
8350 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8351 pci_disable_msix(tp->pdev);
8352 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8353 pci_disable_msi(tp->pdev);
8354 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8355 tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
8356 }
8357
8358 static int tg3_open(struct net_device *dev)
8359 {
8360 struct tg3 *tp = netdev_priv(dev);
8361 int i, err;
8362
8363 if (tp->fw_needed) {
8364 err = tg3_request_firmware(tp);
8365 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8366 if (err)
8367 return err;
8368 } else if (err) {
8369 printk(KERN_WARNING "%s: TSO capability disabled.\n",
8370 tp->dev->name);
8371 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8372 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8373 printk(KERN_NOTICE "%s: TSO capability restored.\n",
8374 tp->dev->name);
8375 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8376 }
8377 }
8378
8379 netif_carrier_off(tp->dev);
8380
8381 err = tg3_set_power_state(tp, PCI_D0);
8382 if (err)
8383 return err;
8384
8385 tg3_full_lock(tp, 0);
8386
8387 tg3_disable_ints(tp);
8388 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8389
8390 tg3_full_unlock(tp);
8391
8392 /*
8393 * Setup interrupts first so we know how
8394 * many NAPI resources to allocate
8395 */
8396 tg3_ints_init(tp);
8397
8398 /* The placement of this call is tied
8399 * to the setup and use of Host TX descriptors.
8400 */
8401 err = tg3_alloc_consistent(tp);
8402 if (err)
8403 goto err_out1;
8404
8405 tg3_napi_enable(tp);
8406
8407 for (i = 0; i < tp->irq_cnt; i++) {
8408 struct tg3_napi *tnapi = &tp->napi[i];
8409 err = tg3_request_irq(tp, i);
8410 if (err) {
8411 for (i--; i >= 0; i--)
8412 free_irq(tnapi->irq_vec, tnapi);
8413 break;
8414 }
8415 }
8416
8417 if (err)
8418 goto err_out2;
8419
8420 tg3_full_lock(tp, 0);
8421
8422 err = tg3_init_hw(tp, 1);
8423 if (err) {
8424 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8425 tg3_free_rings(tp);
8426 } else {
8427 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8428 tp->timer_offset = HZ;
8429 else
8430 tp->timer_offset = HZ / 10;
8431
8432 BUG_ON(tp->timer_offset > HZ);
8433 tp->timer_counter = tp->timer_multiplier =
8434 (HZ / tp->timer_offset);
8435 tp->asf_counter = tp->asf_multiplier =
8436 ((HZ / tp->timer_offset) * 2);
8437
8438 init_timer(&tp->timer);
8439 tp->timer.expires = jiffies + tp->timer_offset;
8440 tp->timer.data = (unsigned long) tp;
8441 tp->timer.function = tg3_timer;
8442 }
8443
8444 tg3_full_unlock(tp);
8445
8446 if (err)
8447 goto err_out3;
8448
8449 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8450 err = tg3_test_msi(tp);
8451
8452 if (err) {
8453 tg3_full_lock(tp, 0);
8454 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8455 tg3_free_rings(tp);
8456 tg3_full_unlock(tp);
8457
8458 goto err_out2;
8459 }
8460
8461 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8462 (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8463 (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8464 u32 val = tr32(PCIE_TRANSACTION_CFG);
8465
8466 tw32(PCIE_TRANSACTION_CFG,
8467 val | PCIE_TRANS_CFG_1SHOT_MSI);
8468 }
8469 }
8470
8471 tg3_phy_start(tp);
8472
8473 tg3_full_lock(tp, 0);
8474
8475 add_timer(&tp->timer);
8476 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8477 tg3_enable_ints(tp);
8478
8479 tg3_full_unlock(tp);
8480
8481 netif_tx_start_all_queues(dev);
8482
8483 return 0;
8484
8485 err_out3:
8486 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8487 struct tg3_napi *tnapi = &tp->napi[i];
8488 free_irq(tnapi->irq_vec, tnapi);
8489 }
8490
8491 err_out2:
8492 tg3_napi_disable(tp);
8493 tg3_free_consistent(tp);
8494
8495 err_out1:
8496 tg3_ints_fini(tp);
8497 return err;
8498 }
8499
8500 #if 0
8501 /*static*/ void tg3_dump_state(struct tg3 *tp)
8502 {
8503 u32 val32, val32_2, val32_3, val32_4, val32_5;
8504 u16 val16;
8505 int i;
8506 struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
8507
8508 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8509 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8510 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8511 val16, val32);
8512
8513 /* MAC block */
8514 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8515 tr32(MAC_MODE), tr32(MAC_STATUS));
8516 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8517 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8518 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8519 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8520 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8521 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8522
8523 /* Send data initiator control block */
8524 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8525 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8526 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8527 tr32(SNDDATAI_STATSCTRL));
8528
8529 /* Send data completion control block */
8530 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8531
8532 /* Send BD ring selector block */
8533 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8534 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8535
8536 /* Send BD initiator control block */
8537 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8538 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8539
8540 /* Send BD completion control block */
8541 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8542
8543 /* Receive list placement control block */
8544 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8545 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8546 printk(" RCVLPC_STATSCTRL[%08x]\n",
8547 tr32(RCVLPC_STATSCTRL));
8548
8549 /* Receive data and receive BD initiator control block */
8550 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8551 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8552
8553 /* Receive data completion control block */
8554 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8555 tr32(RCVDCC_MODE));
8556
8557 /* Receive BD initiator control block */
8558 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8559 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8560
8561 /* Receive BD completion control block */
8562 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8563 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8564
8565 /* Receive list selector control block */
8566 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8567 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8568
8569 /* Mbuf cluster free block */
8570 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8571 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8572
8573 /* Host coalescing control block */
8574 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8575 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8576 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8577 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8578 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8579 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8580 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8581 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8582 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8583 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8584 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8585 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8586
8587 /* Memory arbiter control block */
8588 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8589 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8590
8591 /* Buffer manager control block */
8592 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8593 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8594 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8595 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8596 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8597 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8598 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8599 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8600
8601 /* Read DMA control block */
8602 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8603 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8604
8605 /* Write DMA control block */
8606 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8607 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8608
8609 /* DMA completion block */
8610 printk("DEBUG: DMAC_MODE[%08x]\n",
8611 tr32(DMAC_MODE));
8612
8613 /* GRC block */
8614 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8615 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8616 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8617 tr32(GRC_LOCAL_CTRL));
8618
8619 /* TG3_BDINFOs */
8620 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8621 tr32(RCVDBDI_JUMBO_BD + 0x0),
8622 tr32(RCVDBDI_JUMBO_BD + 0x4),
8623 tr32(RCVDBDI_JUMBO_BD + 0x8),
8624 tr32(RCVDBDI_JUMBO_BD + 0xc));
8625 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8626 tr32(RCVDBDI_STD_BD + 0x0),
8627 tr32(RCVDBDI_STD_BD + 0x4),
8628 tr32(RCVDBDI_STD_BD + 0x8),
8629 tr32(RCVDBDI_STD_BD + 0xc));
8630 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8631 tr32(RCVDBDI_MINI_BD + 0x0),
8632 tr32(RCVDBDI_MINI_BD + 0x4),
8633 tr32(RCVDBDI_MINI_BD + 0x8),
8634 tr32(RCVDBDI_MINI_BD + 0xc));
8635
8636 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8637 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8638 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8639 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8640 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8641 val32, val32_2, val32_3, val32_4);
8642
8643 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8644 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8645 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8646 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8647 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8648 val32, val32_2, val32_3, val32_4);
8649
8650 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8651 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8652 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8653 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8654 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8655 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8656 val32, val32_2, val32_3, val32_4, val32_5);
8657
8658 /* SW status block */
8659 printk(KERN_DEBUG
8660 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8661 sblk->status,
8662 sblk->status_tag,
8663 sblk->rx_jumbo_consumer,
8664 sblk->rx_consumer,
8665 sblk->rx_mini_consumer,
8666 sblk->idx[0].rx_producer,
8667 sblk->idx[0].tx_consumer);
8668
8669 /* SW statistics block */
8670 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8671 ((u32 *)tp->hw_stats)[0],
8672 ((u32 *)tp->hw_stats)[1],
8673 ((u32 *)tp->hw_stats)[2],
8674 ((u32 *)tp->hw_stats)[3]);
8675
8676 /* Mailboxes */
8677 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8678 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8679 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8680 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8681 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
8682
8683 /* NIC side send descriptors. */
8684 for (i = 0; i < 6; i++) {
8685 unsigned long txd;
8686
8687 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8688 + (i * sizeof(struct tg3_tx_buffer_desc));
8689 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8690 i,
8691 readl(txd + 0x0), readl(txd + 0x4),
8692 readl(txd + 0x8), readl(txd + 0xc));
8693 }
8694
8695 /* NIC side RX descriptors. */
8696 for (i = 0; i < 6; i++) {
8697 unsigned long rxd;
8698
8699 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8700 + (i * sizeof(struct tg3_rx_buffer_desc));
8701 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8702 i,
8703 readl(rxd + 0x0), readl(rxd + 0x4),
8704 readl(rxd + 0x8), readl(rxd + 0xc));
8705 rxd += (4 * sizeof(u32));
8706 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8707 i,
8708 readl(rxd + 0x0), readl(rxd + 0x4),
8709 readl(rxd + 0x8), readl(rxd + 0xc));
8710 }
8711
8712 for (i = 0; i < 6; i++) {
8713 unsigned long rxd;
8714
8715 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8716 + (i * sizeof(struct tg3_rx_buffer_desc));
8717 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8718 i,
8719 readl(rxd + 0x0), readl(rxd + 0x4),
8720 readl(rxd + 0x8), readl(rxd + 0xc));
8721 rxd += (4 * sizeof(u32));
8722 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8723 i,
8724 readl(rxd + 0x0), readl(rxd + 0x4),
8725 readl(rxd + 0x8), readl(rxd + 0xc));
8726 }
8727 }
8728 #endif
8729
8730 static struct net_device_stats *tg3_get_stats(struct net_device *);
8731 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8732
8733 static int tg3_close(struct net_device *dev)
8734 {
8735 int i;
8736 struct tg3 *tp = netdev_priv(dev);
8737
8738 tg3_napi_disable(tp);
8739 cancel_work_sync(&tp->reset_task);
8740
8741 netif_tx_stop_all_queues(dev);
8742
8743 del_timer_sync(&tp->timer);
8744
8745 tg3_phy_stop(tp);
8746
8747 tg3_full_lock(tp, 1);
8748 #if 0
8749 tg3_dump_state(tp);
8750 #endif
8751
8752 tg3_disable_ints(tp);
8753
8754 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8755 tg3_free_rings(tp);
8756 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8757
8758 tg3_full_unlock(tp);
8759
8760 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8761 struct tg3_napi *tnapi = &tp->napi[i];
8762 free_irq(tnapi->irq_vec, tnapi);
8763 }
8764
8765 tg3_ints_fini(tp);
8766
8767 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8768 sizeof(tp->net_stats_prev));
8769 memcpy(&tp->estats_prev, tg3_get_estats(tp),
8770 sizeof(tp->estats_prev));
8771
8772 tg3_free_consistent(tp);
8773
8774 tg3_set_power_state(tp, PCI_D3hot);
8775
8776 netif_carrier_off(tp->dev);
8777
8778 return 0;
8779 }
8780
8781 static inline unsigned long get_stat64(tg3_stat64_t *val)
8782 {
8783 unsigned long ret;
8784
8785 #if (BITS_PER_LONG == 32)
8786 ret = val->low;
8787 #else
8788 ret = ((u64)val->high << 32) | ((u64)val->low);
8789 #endif
8790 return ret;
8791 }
8792
8793 static inline u64 get_estat64(tg3_stat64_t *val)
8794 {
8795 return ((u64)val->high << 32) | ((u64)val->low);
8796 }
8797
8798 static unsigned long calc_crc_errors(struct tg3 *tp)
8799 {
8800 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8801
8802 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8803 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8804 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
8805 u32 val;
8806
8807 spin_lock_bh(&tp->lock);
8808 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8809 tg3_writephy(tp, MII_TG3_TEST1,
8810 val | MII_TG3_TEST1_CRC_EN);
8811 tg3_readphy(tp, 0x14, &val);
8812 } else
8813 val = 0;
8814 spin_unlock_bh(&tp->lock);
8815
8816 tp->phy_crc_errors += val;
8817
8818 return tp->phy_crc_errors;
8819 }
8820
8821 return get_stat64(&hw_stats->rx_fcs_errors);
8822 }
8823
8824 #define ESTAT_ADD(member) \
8825 estats->member = old_estats->member + \
8826 get_estat64(&hw_stats->member)
8827
8828 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8829 {
8830 struct tg3_ethtool_stats *estats = &tp->estats;
8831 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8832 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8833
8834 if (!hw_stats)
8835 return old_estats;
8836
8837 ESTAT_ADD(rx_octets);
8838 ESTAT_ADD(rx_fragments);
8839 ESTAT_ADD(rx_ucast_packets);
8840 ESTAT_ADD(rx_mcast_packets);
8841 ESTAT_ADD(rx_bcast_packets);
8842 ESTAT_ADD(rx_fcs_errors);
8843 ESTAT_ADD(rx_align_errors);
8844 ESTAT_ADD(rx_xon_pause_rcvd);
8845 ESTAT_ADD(rx_xoff_pause_rcvd);
8846 ESTAT_ADD(rx_mac_ctrl_rcvd);
8847 ESTAT_ADD(rx_xoff_entered);
8848 ESTAT_ADD(rx_frame_too_long_errors);
8849 ESTAT_ADD(rx_jabbers);
8850 ESTAT_ADD(rx_undersize_packets);
8851 ESTAT_ADD(rx_in_length_errors);
8852 ESTAT_ADD(rx_out_length_errors);
8853 ESTAT_ADD(rx_64_or_less_octet_packets);
8854 ESTAT_ADD(rx_65_to_127_octet_packets);
8855 ESTAT_ADD(rx_128_to_255_octet_packets);
8856 ESTAT_ADD(rx_256_to_511_octet_packets);
8857 ESTAT_ADD(rx_512_to_1023_octet_packets);
8858 ESTAT_ADD(rx_1024_to_1522_octet_packets);
8859 ESTAT_ADD(rx_1523_to_2047_octet_packets);
8860 ESTAT_ADD(rx_2048_to_4095_octet_packets);
8861 ESTAT_ADD(rx_4096_to_8191_octet_packets);
8862 ESTAT_ADD(rx_8192_to_9022_octet_packets);
8863
8864 ESTAT_ADD(tx_octets);
8865 ESTAT_ADD(tx_collisions);
8866 ESTAT_ADD(tx_xon_sent);
8867 ESTAT_ADD(tx_xoff_sent);
8868 ESTAT_ADD(tx_flow_control);
8869 ESTAT_ADD(tx_mac_errors);
8870 ESTAT_ADD(tx_single_collisions);
8871 ESTAT_ADD(tx_mult_collisions);
8872 ESTAT_ADD(tx_deferred);
8873 ESTAT_ADD(tx_excessive_collisions);
8874 ESTAT_ADD(tx_late_collisions);
8875 ESTAT_ADD(tx_collide_2times);
8876 ESTAT_ADD(tx_collide_3times);
8877 ESTAT_ADD(tx_collide_4times);
8878 ESTAT_ADD(tx_collide_5times);
8879 ESTAT_ADD(tx_collide_6times);
8880 ESTAT_ADD(tx_collide_7times);
8881 ESTAT_ADD(tx_collide_8times);
8882 ESTAT_ADD(tx_collide_9times);
8883 ESTAT_ADD(tx_collide_10times);
8884 ESTAT_ADD(tx_collide_11times);
8885 ESTAT_ADD(tx_collide_12times);
8886 ESTAT_ADD(tx_collide_13times);
8887 ESTAT_ADD(tx_collide_14times);
8888 ESTAT_ADD(tx_collide_15times);
8889 ESTAT_ADD(tx_ucast_packets);
8890 ESTAT_ADD(tx_mcast_packets);
8891 ESTAT_ADD(tx_bcast_packets);
8892 ESTAT_ADD(tx_carrier_sense_errors);
8893 ESTAT_ADD(tx_discards);
8894 ESTAT_ADD(tx_errors);
8895
8896 ESTAT_ADD(dma_writeq_full);
8897 ESTAT_ADD(dma_write_prioq_full);
8898 ESTAT_ADD(rxbds_empty);
8899 ESTAT_ADD(rx_discards);
8900 ESTAT_ADD(rx_errors);
8901 ESTAT_ADD(rx_threshold_hit);
8902
8903 ESTAT_ADD(dma_readq_full);
8904 ESTAT_ADD(dma_read_prioq_full);
8905 ESTAT_ADD(tx_comp_queue_full);
8906
8907 ESTAT_ADD(ring_set_send_prod_index);
8908 ESTAT_ADD(ring_status_update);
8909 ESTAT_ADD(nic_irqs);
8910 ESTAT_ADD(nic_avoided_irqs);
8911 ESTAT_ADD(nic_tx_threshold_hit);
8912
8913 return estats;
8914 }
8915
8916 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8917 {
8918 struct tg3 *tp = netdev_priv(dev);
8919 struct net_device_stats *stats = &tp->net_stats;
8920 struct net_device_stats *old_stats = &tp->net_stats_prev;
8921 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8922
8923 if (!hw_stats)
8924 return old_stats;
8925
8926 stats->rx_packets = old_stats->rx_packets +
8927 get_stat64(&hw_stats->rx_ucast_packets) +
8928 get_stat64(&hw_stats->rx_mcast_packets) +
8929 get_stat64(&hw_stats->rx_bcast_packets);
8930
8931 stats->tx_packets = old_stats->tx_packets +
8932 get_stat64(&hw_stats->tx_ucast_packets) +
8933 get_stat64(&hw_stats->tx_mcast_packets) +
8934 get_stat64(&hw_stats->tx_bcast_packets);
8935
8936 stats->rx_bytes = old_stats->rx_bytes +
8937 get_stat64(&hw_stats->rx_octets);
8938 stats->tx_bytes = old_stats->tx_bytes +
8939 get_stat64(&hw_stats->tx_octets);
8940
8941 stats->rx_errors = old_stats->rx_errors +
8942 get_stat64(&hw_stats->rx_errors);
8943 stats->tx_errors = old_stats->tx_errors +
8944 get_stat64(&hw_stats->tx_errors) +
8945 get_stat64(&hw_stats->tx_mac_errors) +
8946 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8947 get_stat64(&hw_stats->tx_discards);
8948
8949 stats->multicast = old_stats->multicast +
8950 get_stat64(&hw_stats->rx_mcast_packets);
8951 stats->collisions = old_stats->collisions +
8952 get_stat64(&hw_stats->tx_collisions);
8953
8954 stats->rx_length_errors = old_stats->rx_length_errors +
8955 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8956 get_stat64(&hw_stats->rx_undersize_packets);
8957
8958 stats->rx_over_errors = old_stats->rx_over_errors +
8959 get_stat64(&hw_stats->rxbds_empty);
8960 stats->rx_frame_errors = old_stats->rx_frame_errors +
8961 get_stat64(&hw_stats->rx_align_errors);
8962 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8963 get_stat64(&hw_stats->tx_discards);
8964 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8965 get_stat64(&hw_stats->tx_carrier_sense_errors);
8966
8967 stats->rx_crc_errors = old_stats->rx_crc_errors +
8968 calc_crc_errors(tp);
8969
8970 stats->rx_missed_errors = old_stats->rx_missed_errors +
8971 get_stat64(&hw_stats->rx_discards);
8972
8973 return stats;
8974 }
8975
8976 static inline u32 calc_crc(unsigned char *buf, int len)
8977 {
8978 u32 reg;
8979 u32 tmp;
8980 int j, k;
8981
8982 reg = 0xffffffff;
8983
8984 for (j = 0; j < len; j++) {
8985 reg ^= buf[j];
8986
8987 for (k = 0; k < 8; k++) {
8988 tmp = reg & 0x01;
8989
8990 reg >>= 1;
8991
8992 if (tmp) {
8993 reg ^= 0xedb88320;
8994 }
8995 }
8996 }
8997
8998 return ~reg;
8999 }
9000
9001 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9002 {
9003 /* accept or reject all multicast frames */
9004 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9005 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9006 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9007 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9008 }
9009
9010 static void __tg3_set_rx_mode(struct net_device *dev)
9011 {
9012 struct tg3 *tp = netdev_priv(dev);
9013 u32 rx_mode;
9014
9015 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9016 RX_MODE_KEEP_VLAN_TAG);
9017
9018 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9019 * flag clear.
9020 */
9021 #if TG3_VLAN_TAG_USED
9022 if (!tp->vlgrp &&
9023 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9024 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9025 #else
9026 /* By definition, VLAN is disabled always in this
9027 * case.
9028 */
9029 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9030 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9031 #endif
9032
9033 if (dev->flags & IFF_PROMISC) {
9034 /* Promiscuous mode. */
9035 rx_mode |= RX_MODE_PROMISC;
9036 } else if (dev->flags & IFF_ALLMULTI) {
9037 /* Accept all multicast. */
9038 tg3_set_multi (tp, 1);
9039 } else if (dev->mc_count < 1) {
9040 /* Reject all multicast. */
9041 tg3_set_multi (tp, 0);
9042 } else {
9043 /* Accept one or more multicast(s). */
9044 struct dev_mc_list *mclist;
9045 unsigned int i;
9046 u32 mc_filter[4] = { 0, };
9047 u32 regidx;
9048 u32 bit;
9049 u32 crc;
9050
9051 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
9052 i++, mclist = mclist->next) {
9053
9054 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9055 bit = ~crc & 0x7f;
9056 regidx = (bit & 0x60) >> 5;
9057 bit &= 0x1f;
9058 mc_filter[regidx] |= (1 << bit);
9059 }
9060
9061 tw32(MAC_HASH_REG_0, mc_filter[0]);
9062 tw32(MAC_HASH_REG_1, mc_filter[1]);
9063 tw32(MAC_HASH_REG_2, mc_filter[2]);
9064 tw32(MAC_HASH_REG_3, mc_filter[3]);
9065 }
9066
9067 if (rx_mode != tp->rx_mode) {
9068 tp->rx_mode = rx_mode;
9069 tw32_f(MAC_RX_MODE, rx_mode);
9070 udelay(10);
9071 }
9072 }
9073
9074 static void tg3_set_rx_mode(struct net_device *dev)
9075 {
9076 struct tg3 *tp = netdev_priv(dev);
9077
9078 if (!netif_running(dev))
9079 return;
9080
9081 tg3_full_lock(tp, 0);
9082 __tg3_set_rx_mode(dev);
9083 tg3_full_unlock(tp);
9084 }
9085
9086 #define TG3_REGDUMP_LEN (32 * 1024)
9087
9088 static int tg3_get_regs_len(struct net_device *dev)
9089 {
9090 return TG3_REGDUMP_LEN;
9091 }
9092
9093 static void tg3_get_regs(struct net_device *dev,
9094 struct ethtool_regs *regs, void *_p)
9095 {
9096 u32 *p = _p;
9097 struct tg3 *tp = netdev_priv(dev);
9098 u8 *orig_p = _p;
9099 int i;
9100
9101 regs->version = 0;
9102
9103 memset(p, 0, TG3_REGDUMP_LEN);
9104
9105 if (tp->link_config.phy_is_low_power)
9106 return;
9107
9108 tg3_full_lock(tp, 0);
9109
9110 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
9111 #define GET_REG32_LOOP(base,len) \
9112 do { p = (u32 *)(orig_p + (base)); \
9113 for (i = 0; i < len; i += 4) \
9114 __GET_REG32((base) + i); \
9115 } while (0)
9116 #define GET_REG32_1(reg) \
9117 do { p = (u32 *)(orig_p + (reg)); \
9118 __GET_REG32((reg)); \
9119 } while (0)
9120
9121 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9122 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9123 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9124 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9125 GET_REG32_1(SNDDATAC_MODE);
9126 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9127 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9128 GET_REG32_1(SNDBDC_MODE);
9129 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9130 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9131 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9132 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9133 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9134 GET_REG32_1(RCVDCC_MODE);
9135 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9136 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9137 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9138 GET_REG32_1(MBFREE_MODE);
9139 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9140 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9141 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9142 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9143 GET_REG32_LOOP(WDMAC_MODE, 0x08);
9144 GET_REG32_1(RX_CPU_MODE);
9145 GET_REG32_1(RX_CPU_STATE);
9146 GET_REG32_1(RX_CPU_PGMCTR);
9147 GET_REG32_1(RX_CPU_HWBKPT);
9148 GET_REG32_1(TX_CPU_MODE);
9149 GET_REG32_1(TX_CPU_STATE);
9150 GET_REG32_1(TX_CPU_PGMCTR);
9151 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9152 GET_REG32_LOOP(FTQ_RESET, 0x120);
9153 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9154 GET_REG32_1(DMAC_MODE);
9155 GET_REG32_LOOP(GRC_MODE, 0x4c);
9156 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9157 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9158
9159 #undef __GET_REG32
9160 #undef GET_REG32_LOOP
9161 #undef GET_REG32_1
9162
9163 tg3_full_unlock(tp);
9164 }
9165
9166 static int tg3_get_eeprom_len(struct net_device *dev)
9167 {
9168 struct tg3 *tp = netdev_priv(dev);
9169
9170 return tp->nvram_size;
9171 }
9172
9173 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9174 {
9175 struct tg3 *tp = netdev_priv(dev);
9176 int ret;
9177 u8 *pd;
9178 u32 i, offset, len, b_offset, b_count;
9179 __be32 val;
9180
9181 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9182 return -EINVAL;
9183
9184 if (tp->link_config.phy_is_low_power)
9185 return -EAGAIN;
9186
9187 offset = eeprom->offset;
9188 len = eeprom->len;
9189 eeprom->len = 0;
9190
9191 eeprom->magic = TG3_EEPROM_MAGIC;
9192
9193 if (offset & 3) {
9194 /* adjustments to start on required 4 byte boundary */
9195 b_offset = offset & 3;
9196 b_count = 4 - b_offset;
9197 if (b_count > len) {
9198 /* i.e. offset=1 len=2 */
9199 b_count = len;
9200 }
9201 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9202 if (ret)
9203 return ret;
9204 memcpy(data, ((char*)&val) + b_offset, b_count);
9205 len -= b_count;
9206 offset += b_count;
9207 eeprom->len += b_count;
9208 }
9209
9210 /* read bytes upto the last 4 byte boundary */
9211 pd = &data[eeprom->len];
9212 for (i = 0; i < (len - (len & 3)); i += 4) {
9213 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9214 if (ret) {
9215 eeprom->len += i;
9216 return ret;
9217 }
9218 memcpy(pd + i, &val, 4);
9219 }
9220 eeprom->len += i;
9221
9222 if (len & 3) {
9223 /* read last bytes not ending on 4 byte boundary */
9224 pd = &data[eeprom->len];
9225 b_count = len & 3;
9226 b_offset = offset + len - b_count;
9227 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9228 if (ret)
9229 return ret;
9230 memcpy(pd, &val, b_count);
9231 eeprom->len += b_count;
9232 }
9233 return 0;
9234 }
9235
9236 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9237
9238 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9239 {
9240 struct tg3 *tp = netdev_priv(dev);
9241 int ret;
9242 u32 offset, len, b_offset, odd_len;
9243 u8 *buf;
9244 __be32 start, end;
9245
9246 if (tp->link_config.phy_is_low_power)
9247 return -EAGAIN;
9248
9249 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9250 eeprom->magic != TG3_EEPROM_MAGIC)
9251 return -EINVAL;
9252
9253 offset = eeprom->offset;
9254 len = eeprom->len;
9255
9256 if ((b_offset = (offset & 3))) {
9257 /* adjustments to start on required 4 byte boundary */
9258 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9259 if (ret)
9260 return ret;
9261 len += b_offset;
9262 offset &= ~3;
9263 if (len < 4)
9264 len = 4;
9265 }
9266
9267 odd_len = 0;
9268 if (len & 3) {
9269 /* adjustments to end on required 4 byte boundary */
9270 odd_len = 1;
9271 len = (len + 3) & ~3;
9272 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9273 if (ret)
9274 return ret;
9275 }
9276
9277 buf = data;
9278 if (b_offset || odd_len) {
9279 buf = kmalloc(len, GFP_KERNEL);
9280 if (!buf)
9281 return -ENOMEM;
9282 if (b_offset)
9283 memcpy(buf, &start, 4);
9284 if (odd_len)
9285 memcpy(buf+len-4, &end, 4);
9286 memcpy(buf + b_offset, data, eeprom->len);
9287 }
9288
9289 ret = tg3_nvram_write_block(tp, offset, len, buf);
9290
9291 if (buf != data)
9292 kfree(buf);
9293
9294 return ret;
9295 }
9296
9297 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9298 {
9299 struct tg3 *tp = netdev_priv(dev);
9300
9301 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9302 struct phy_device *phydev;
9303 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9304 return -EAGAIN;
9305 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9306 return phy_ethtool_gset(phydev, cmd);
9307 }
9308
9309 cmd->supported = (SUPPORTED_Autoneg);
9310
9311 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9312 cmd->supported |= (SUPPORTED_1000baseT_Half |
9313 SUPPORTED_1000baseT_Full);
9314
9315 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9316 cmd->supported |= (SUPPORTED_100baseT_Half |
9317 SUPPORTED_100baseT_Full |
9318 SUPPORTED_10baseT_Half |
9319 SUPPORTED_10baseT_Full |
9320 SUPPORTED_TP);
9321 cmd->port = PORT_TP;
9322 } else {
9323 cmd->supported |= SUPPORTED_FIBRE;
9324 cmd->port = PORT_FIBRE;
9325 }
9326
9327 cmd->advertising = tp->link_config.advertising;
9328 if (netif_running(dev)) {
9329 cmd->speed = tp->link_config.active_speed;
9330 cmd->duplex = tp->link_config.active_duplex;
9331 }
9332 cmd->phy_address = tp->phy_addr;
9333 cmd->transceiver = XCVR_INTERNAL;
9334 cmd->autoneg = tp->link_config.autoneg;
9335 cmd->maxtxpkt = 0;
9336 cmd->maxrxpkt = 0;
9337 return 0;
9338 }
9339
9340 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9341 {
9342 struct tg3 *tp = netdev_priv(dev);
9343
9344 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9345 struct phy_device *phydev;
9346 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9347 return -EAGAIN;
9348 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9349 return phy_ethtool_sset(phydev, cmd);
9350 }
9351
9352 if (cmd->autoneg != AUTONEG_ENABLE &&
9353 cmd->autoneg != AUTONEG_DISABLE)
9354 return -EINVAL;
9355
9356 if (cmd->autoneg == AUTONEG_DISABLE &&
9357 cmd->duplex != DUPLEX_FULL &&
9358 cmd->duplex != DUPLEX_HALF)
9359 return -EINVAL;
9360
9361 if (cmd->autoneg == AUTONEG_ENABLE) {
9362 u32 mask = ADVERTISED_Autoneg |
9363 ADVERTISED_Pause |
9364 ADVERTISED_Asym_Pause;
9365
9366 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9367 mask |= ADVERTISED_1000baseT_Half |
9368 ADVERTISED_1000baseT_Full;
9369
9370 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9371 mask |= ADVERTISED_100baseT_Half |
9372 ADVERTISED_100baseT_Full |
9373 ADVERTISED_10baseT_Half |
9374 ADVERTISED_10baseT_Full |
9375 ADVERTISED_TP;
9376 else
9377 mask |= ADVERTISED_FIBRE;
9378
9379 if (cmd->advertising & ~mask)
9380 return -EINVAL;
9381
9382 mask &= (ADVERTISED_1000baseT_Half |
9383 ADVERTISED_1000baseT_Full |
9384 ADVERTISED_100baseT_Half |
9385 ADVERTISED_100baseT_Full |
9386 ADVERTISED_10baseT_Half |
9387 ADVERTISED_10baseT_Full);
9388
9389 cmd->advertising &= mask;
9390 } else {
9391 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9392 if (cmd->speed != SPEED_1000)
9393 return -EINVAL;
9394
9395 if (cmd->duplex != DUPLEX_FULL)
9396 return -EINVAL;
9397 } else {
9398 if (cmd->speed != SPEED_100 &&
9399 cmd->speed != SPEED_10)
9400 return -EINVAL;
9401 }
9402 }
9403
9404 tg3_full_lock(tp, 0);
9405
9406 tp->link_config.autoneg = cmd->autoneg;
9407 if (cmd->autoneg == AUTONEG_ENABLE) {
9408 tp->link_config.advertising = (cmd->advertising |
9409 ADVERTISED_Autoneg);
9410 tp->link_config.speed = SPEED_INVALID;
9411 tp->link_config.duplex = DUPLEX_INVALID;
9412 } else {
9413 tp->link_config.advertising = 0;
9414 tp->link_config.speed = cmd->speed;
9415 tp->link_config.duplex = cmd->duplex;
9416 }
9417
9418 tp->link_config.orig_speed = tp->link_config.speed;
9419 tp->link_config.orig_duplex = tp->link_config.duplex;
9420 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9421
9422 if (netif_running(dev))
9423 tg3_setup_phy(tp, 1);
9424
9425 tg3_full_unlock(tp);
9426
9427 return 0;
9428 }
9429
9430 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9431 {
9432 struct tg3 *tp = netdev_priv(dev);
9433
9434 strcpy(info->driver, DRV_MODULE_NAME);
9435 strcpy(info->version, DRV_MODULE_VERSION);
9436 strcpy(info->fw_version, tp->fw_ver);
9437 strcpy(info->bus_info, pci_name(tp->pdev));
9438 }
9439
9440 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9441 {
9442 struct tg3 *tp = netdev_priv(dev);
9443
9444 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9445 device_can_wakeup(&tp->pdev->dev))
9446 wol->supported = WAKE_MAGIC;
9447 else
9448 wol->supported = 0;
9449 wol->wolopts = 0;
9450 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9451 device_can_wakeup(&tp->pdev->dev))
9452 wol->wolopts = WAKE_MAGIC;
9453 memset(&wol->sopass, 0, sizeof(wol->sopass));
9454 }
9455
9456 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9457 {
9458 struct tg3 *tp = netdev_priv(dev);
9459 struct device *dp = &tp->pdev->dev;
9460
9461 if (wol->wolopts & ~WAKE_MAGIC)
9462 return -EINVAL;
9463 if ((wol->wolopts & WAKE_MAGIC) &&
9464 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9465 return -EINVAL;
9466
9467 spin_lock_bh(&tp->lock);
9468 if (wol->wolopts & WAKE_MAGIC) {
9469 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9470 device_set_wakeup_enable(dp, true);
9471 } else {
9472 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9473 device_set_wakeup_enable(dp, false);
9474 }
9475 spin_unlock_bh(&tp->lock);
9476
9477 return 0;
9478 }
9479
9480 static u32 tg3_get_msglevel(struct net_device *dev)
9481 {
9482 struct tg3 *tp = netdev_priv(dev);
9483 return tp->msg_enable;
9484 }
9485
9486 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9487 {
9488 struct tg3 *tp = netdev_priv(dev);
9489 tp->msg_enable = value;
9490 }
9491
9492 static int tg3_set_tso(struct net_device *dev, u32 value)
9493 {
9494 struct tg3 *tp = netdev_priv(dev);
9495
9496 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9497 if (value)
9498 return -EINVAL;
9499 return 0;
9500 }
9501 if ((dev->features & NETIF_F_IPV6_CSUM) &&
9502 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
9503 if (value) {
9504 dev->features |= NETIF_F_TSO6;
9505 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9506 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9507 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9508 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9509 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
9510 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
9511 dev->features |= NETIF_F_TSO_ECN;
9512 } else
9513 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9514 }
9515 return ethtool_op_set_tso(dev, value);
9516 }
9517
9518 static int tg3_nway_reset(struct net_device *dev)
9519 {
9520 struct tg3 *tp = netdev_priv(dev);
9521 int r;
9522
9523 if (!netif_running(dev))
9524 return -EAGAIN;
9525
9526 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9527 return -EINVAL;
9528
9529 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9530 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9531 return -EAGAIN;
9532 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9533 } else {
9534 u32 bmcr;
9535
9536 spin_lock_bh(&tp->lock);
9537 r = -EINVAL;
9538 tg3_readphy(tp, MII_BMCR, &bmcr);
9539 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9540 ((bmcr & BMCR_ANENABLE) ||
9541 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9542 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9543 BMCR_ANENABLE);
9544 r = 0;
9545 }
9546 spin_unlock_bh(&tp->lock);
9547 }
9548
9549 return r;
9550 }
9551
9552 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9553 {
9554 struct tg3 *tp = netdev_priv(dev);
9555
9556 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9557 ering->rx_mini_max_pending = 0;
9558 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9559 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9560 else
9561 ering->rx_jumbo_max_pending = 0;
9562
9563 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9564
9565 ering->rx_pending = tp->rx_pending;
9566 ering->rx_mini_pending = 0;
9567 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9568 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9569 else
9570 ering->rx_jumbo_pending = 0;
9571
9572 ering->tx_pending = tp->napi[0].tx_pending;
9573 }
9574
9575 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9576 {
9577 struct tg3 *tp = netdev_priv(dev);
9578 int i, irq_sync = 0, err = 0;
9579
9580 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9581 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9582 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9583 (ering->tx_pending <= MAX_SKB_FRAGS) ||
9584 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9585 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9586 return -EINVAL;
9587
9588 if (netif_running(dev)) {
9589 tg3_phy_stop(tp);
9590 tg3_netif_stop(tp);
9591 irq_sync = 1;
9592 }
9593
9594 tg3_full_lock(tp, irq_sync);
9595
9596 tp->rx_pending = ering->rx_pending;
9597
9598 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9599 tp->rx_pending > 63)
9600 tp->rx_pending = 63;
9601 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9602
9603 for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9604 tp->napi[i].tx_pending = ering->tx_pending;
9605
9606 if (netif_running(dev)) {
9607 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9608 err = tg3_restart_hw(tp, 1);
9609 if (!err)
9610 tg3_netif_start(tp);
9611 }
9612
9613 tg3_full_unlock(tp);
9614
9615 if (irq_sync && !err)
9616 tg3_phy_start(tp);
9617
9618 return err;
9619 }
9620
9621 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9622 {
9623 struct tg3 *tp = netdev_priv(dev);
9624
9625 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9626
9627 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9628 epause->rx_pause = 1;
9629 else
9630 epause->rx_pause = 0;
9631
9632 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9633 epause->tx_pause = 1;
9634 else
9635 epause->tx_pause = 0;
9636 }
9637
9638 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9639 {
9640 struct tg3 *tp = netdev_priv(dev);
9641 int err = 0;
9642
9643 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9644 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9645 return -EAGAIN;
9646
9647 if (epause->autoneg) {
9648 u32 newadv;
9649 struct phy_device *phydev;
9650
9651 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9652
9653 if (epause->rx_pause) {
9654 if (epause->tx_pause)
9655 newadv = ADVERTISED_Pause;
9656 else
9657 newadv = ADVERTISED_Pause |
9658 ADVERTISED_Asym_Pause;
9659 } else if (epause->tx_pause) {
9660 newadv = ADVERTISED_Asym_Pause;
9661 } else
9662 newadv = 0;
9663
9664 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9665 u32 oldadv = phydev->advertising &
9666 (ADVERTISED_Pause |
9667 ADVERTISED_Asym_Pause);
9668 if (oldadv != newadv) {
9669 phydev->advertising &=
9670 ~(ADVERTISED_Pause |
9671 ADVERTISED_Asym_Pause);
9672 phydev->advertising |= newadv;
9673 err = phy_start_aneg(phydev);
9674 }
9675 } else {
9676 tp->link_config.advertising &=
9677 ~(ADVERTISED_Pause |
9678 ADVERTISED_Asym_Pause);
9679 tp->link_config.advertising |= newadv;
9680 }
9681 } else {
9682 if (epause->rx_pause)
9683 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9684 else
9685 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9686
9687 if (epause->tx_pause)
9688 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9689 else
9690 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9691
9692 if (netif_running(dev))
9693 tg3_setup_flow_control(tp, 0, 0);
9694 }
9695 } else {
9696 int irq_sync = 0;
9697
9698 if (netif_running(dev)) {
9699 tg3_netif_stop(tp);
9700 irq_sync = 1;
9701 }
9702
9703 tg3_full_lock(tp, irq_sync);
9704
9705 if (epause->autoneg)
9706 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9707 else
9708 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9709 if (epause->rx_pause)
9710 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9711 else
9712 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9713 if (epause->tx_pause)
9714 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9715 else
9716 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9717
9718 if (netif_running(dev)) {
9719 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9720 err = tg3_restart_hw(tp, 1);
9721 if (!err)
9722 tg3_netif_start(tp);
9723 }
9724
9725 tg3_full_unlock(tp);
9726 }
9727
9728 return err;
9729 }
9730
9731 static u32 tg3_get_rx_csum(struct net_device *dev)
9732 {
9733 struct tg3 *tp = netdev_priv(dev);
9734 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9735 }
9736
9737 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9738 {
9739 struct tg3 *tp = netdev_priv(dev);
9740
9741 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9742 if (data != 0)
9743 return -EINVAL;
9744 return 0;
9745 }
9746
9747 spin_lock_bh(&tp->lock);
9748 if (data)
9749 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9750 else
9751 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9752 spin_unlock_bh(&tp->lock);
9753
9754 return 0;
9755 }
9756
9757 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9758 {
9759 struct tg3 *tp = netdev_priv(dev);
9760
9761 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9762 if (data != 0)
9763 return -EINVAL;
9764 return 0;
9765 }
9766
9767 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9768 ethtool_op_set_tx_ipv6_csum(dev, data);
9769 else
9770 ethtool_op_set_tx_csum(dev, data);
9771
9772 return 0;
9773 }
9774
9775 static int tg3_get_sset_count (struct net_device *dev, int sset)
9776 {
9777 switch (sset) {
9778 case ETH_SS_TEST:
9779 return TG3_NUM_TEST;
9780 case ETH_SS_STATS:
9781 return TG3_NUM_STATS;
9782 default:
9783 return -EOPNOTSUPP;
9784 }
9785 }
9786
9787 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9788 {
9789 switch (stringset) {
9790 case ETH_SS_STATS:
9791 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9792 break;
9793 case ETH_SS_TEST:
9794 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9795 break;
9796 default:
9797 WARN_ON(1); /* we need a WARN() */
9798 break;
9799 }
9800 }
9801
9802 static int tg3_phys_id(struct net_device *dev, u32 data)
9803 {
9804 struct tg3 *tp = netdev_priv(dev);
9805 int i;
9806
9807 if (!netif_running(tp->dev))
9808 return -EAGAIN;
9809
9810 if (data == 0)
9811 data = UINT_MAX / 2;
9812
9813 for (i = 0; i < (data * 2); i++) {
9814 if ((i % 2) == 0)
9815 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9816 LED_CTRL_1000MBPS_ON |
9817 LED_CTRL_100MBPS_ON |
9818 LED_CTRL_10MBPS_ON |
9819 LED_CTRL_TRAFFIC_OVERRIDE |
9820 LED_CTRL_TRAFFIC_BLINK |
9821 LED_CTRL_TRAFFIC_LED);
9822
9823 else
9824 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9825 LED_CTRL_TRAFFIC_OVERRIDE);
9826
9827 if (msleep_interruptible(500))
9828 break;
9829 }
9830 tw32(MAC_LED_CTRL, tp->led_ctrl);
9831 return 0;
9832 }
9833
9834 static void tg3_get_ethtool_stats (struct net_device *dev,
9835 struct ethtool_stats *estats, u64 *tmp_stats)
9836 {
9837 struct tg3 *tp = netdev_priv(dev);
9838 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9839 }
9840
9841 #define NVRAM_TEST_SIZE 0x100
9842 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9843 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9844 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
9845 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9846 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9847
9848 static int tg3_test_nvram(struct tg3 *tp)
9849 {
9850 u32 csum, magic;
9851 __be32 *buf;
9852 int i, j, k, err = 0, size;
9853
9854 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9855 return 0;
9856
9857 if (tg3_nvram_read(tp, 0, &magic) != 0)
9858 return -EIO;
9859
9860 if (magic == TG3_EEPROM_MAGIC)
9861 size = NVRAM_TEST_SIZE;
9862 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
9863 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9864 TG3_EEPROM_SB_FORMAT_1) {
9865 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9866 case TG3_EEPROM_SB_REVISION_0:
9867 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9868 break;
9869 case TG3_EEPROM_SB_REVISION_2:
9870 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9871 break;
9872 case TG3_EEPROM_SB_REVISION_3:
9873 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9874 break;
9875 default:
9876 return 0;
9877 }
9878 } else
9879 return 0;
9880 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9881 size = NVRAM_SELFBOOT_HW_SIZE;
9882 else
9883 return -EIO;
9884
9885 buf = kmalloc(size, GFP_KERNEL);
9886 if (buf == NULL)
9887 return -ENOMEM;
9888
9889 err = -EIO;
9890 for (i = 0, j = 0; i < size; i += 4, j++) {
9891 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9892 if (err)
9893 break;
9894 }
9895 if (i < size)
9896 goto out;
9897
9898 /* Selfboot format */
9899 magic = be32_to_cpu(buf[0]);
9900 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9901 TG3_EEPROM_MAGIC_FW) {
9902 u8 *buf8 = (u8 *) buf, csum8 = 0;
9903
9904 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9905 TG3_EEPROM_SB_REVISION_2) {
9906 /* For rev 2, the csum doesn't include the MBA. */
9907 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9908 csum8 += buf8[i];
9909 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9910 csum8 += buf8[i];
9911 } else {
9912 for (i = 0; i < size; i++)
9913 csum8 += buf8[i];
9914 }
9915
9916 if (csum8 == 0) {
9917 err = 0;
9918 goto out;
9919 }
9920
9921 err = -EIO;
9922 goto out;
9923 }
9924
9925 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
9926 TG3_EEPROM_MAGIC_HW) {
9927 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9928 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9929 u8 *buf8 = (u8 *) buf;
9930
9931 /* Separate the parity bits and the data bytes. */
9932 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9933 if ((i == 0) || (i == 8)) {
9934 int l;
9935 u8 msk;
9936
9937 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9938 parity[k++] = buf8[i] & msk;
9939 i++;
9940 }
9941 else if (i == 16) {
9942 int l;
9943 u8 msk;
9944
9945 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9946 parity[k++] = buf8[i] & msk;
9947 i++;
9948
9949 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9950 parity[k++] = buf8[i] & msk;
9951 i++;
9952 }
9953 data[j++] = buf8[i];
9954 }
9955
9956 err = -EIO;
9957 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9958 u8 hw8 = hweight8(data[i]);
9959
9960 if ((hw8 & 0x1) && parity[i])
9961 goto out;
9962 else if (!(hw8 & 0x1) && !parity[i])
9963 goto out;
9964 }
9965 err = 0;
9966 goto out;
9967 }
9968
9969 /* Bootstrap checksum at offset 0x10 */
9970 csum = calc_crc((unsigned char *) buf, 0x10);
9971 if (csum != be32_to_cpu(buf[0x10/4]))
9972 goto out;
9973
9974 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9975 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
9976 if (csum != be32_to_cpu(buf[0xfc/4]))
9977 goto out;
9978
9979 err = 0;
9980
9981 out:
9982 kfree(buf);
9983 return err;
9984 }
9985
9986 #define TG3_SERDES_TIMEOUT_SEC 2
9987 #define TG3_COPPER_TIMEOUT_SEC 6
9988
9989 static int tg3_test_link(struct tg3 *tp)
9990 {
9991 int i, max;
9992
9993 if (!netif_running(tp->dev))
9994 return -ENODEV;
9995
9996 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9997 max = TG3_SERDES_TIMEOUT_SEC;
9998 else
9999 max = TG3_COPPER_TIMEOUT_SEC;
10000
10001 for (i = 0; i < max; i++) {
10002 if (netif_carrier_ok(tp->dev))
10003 return 0;
10004
10005 if (msleep_interruptible(1000))
10006 break;
10007 }
10008
10009 return -EIO;
10010 }
10011
10012 /* Only test the commonly used registers */
10013 static int tg3_test_registers(struct tg3 *tp)
10014 {
10015 int i, is_5705, is_5750;
10016 u32 offset, read_mask, write_mask, val, save_val, read_val;
10017 static struct {
10018 u16 offset;
10019 u16 flags;
10020 #define TG3_FL_5705 0x1
10021 #define TG3_FL_NOT_5705 0x2
10022 #define TG3_FL_NOT_5788 0x4
10023 #define TG3_FL_NOT_5750 0x8
10024 u32 read_mask;
10025 u32 write_mask;
10026 } reg_tbl[] = {
10027 /* MAC Control Registers */
10028 { MAC_MODE, TG3_FL_NOT_5705,
10029 0x00000000, 0x00ef6f8c },
10030 { MAC_MODE, TG3_FL_5705,
10031 0x00000000, 0x01ef6b8c },
10032 { MAC_STATUS, TG3_FL_NOT_5705,
10033 0x03800107, 0x00000000 },
10034 { MAC_STATUS, TG3_FL_5705,
10035 0x03800100, 0x00000000 },
10036 { MAC_ADDR_0_HIGH, 0x0000,
10037 0x00000000, 0x0000ffff },
10038 { MAC_ADDR_0_LOW, 0x0000,
10039 0x00000000, 0xffffffff },
10040 { MAC_RX_MTU_SIZE, 0x0000,
10041 0x00000000, 0x0000ffff },
10042 { MAC_TX_MODE, 0x0000,
10043 0x00000000, 0x00000070 },
10044 { MAC_TX_LENGTHS, 0x0000,
10045 0x00000000, 0x00003fff },
10046 { MAC_RX_MODE, TG3_FL_NOT_5705,
10047 0x00000000, 0x000007fc },
10048 { MAC_RX_MODE, TG3_FL_5705,
10049 0x00000000, 0x000007dc },
10050 { MAC_HASH_REG_0, 0x0000,
10051 0x00000000, 0xffffffff },
10052 { MAC_HASH_REG_1, 0x0000,
10053 0x00000000, 0xffffffff },
10054 { MAC_HASH_REG_2, 0x0000,
10055 0x00000000, 0xffffffff },
10056 { MAC_HASH_REG_3, 0x0000,
10057 0x00000000, 0xffffffff },
10058
10059 /* Receive Data and Receive BD Initiator Control Registers. */
10060 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10061 0x00000000, 0xffffffff },
10062 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10063 0x00000000, 0xffffffff },
10064 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10065 0x00000000, 0x00000003 },
10066 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10067 0x00000000, 0xffffffff },
10068 { RCVDBDI_STD_BD+0, 0x0000,
10069 0x00000000, 0xffffffff },
10070 { RCVDBDI_STD_BD+4, 0x0000,
10071 0x00000000, 0xffffffff },
10072 { RCVDBDI_STD_BD+8, 0x0000,
10073 0x00000000, 0xffff0002 },
10074 { RCVDBDI_STD_BD+0xc, 0x0000,
10075 0x00000000, 0xffffffff },
10076
10077 /* Receive BD Initiator Control Registers. */
10078 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10079 0x00000000, 0xffffffff },
10080 { RCVBDI_STD_THRESH, TG3_FL_5705,
10081 0x00000000, 0x000003ff },
10082 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10083 0x00000000, 0xffffffff },
10084
10085 /* Host Coalescing Control Registers. */
10086 { HOSTCC_MODE, TG3_FL_NOT_5705,
10087 0x00000000, 0x00000004 },
10088 { HOSTCC_MODE, TG3_FL_5705,
10089 0x00000000, 0x000000f6 },
10090 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10091 0x00000000, 0xffffffff },
10092 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10093 0x00000000, 0x000003ff },
10094 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10095 0x00000000, 0xffffffff },
10096 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10097 0x00000000, 0x000003ff },
10098 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10099 0x00000000, 0xffffffff },
10100 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10101 0x00000000, 0x000000ff },
10102 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10103 0x00000000, 0xffffffff },
10104 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10105 0x00000000, 0x000000ff },
10106 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10107 0x00000000, 0xffffffff },
10108 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10109 0x00000000, 0xffffffff },
10110 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10111 0x00000000, 0xffffffff },
10112 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10113 0x00000000, 0x000000ff },
10114 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10115 0x00000000, 0xffffffff },
10116 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10117 0x00000000, 0x000000ff },
10118 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10119 0x00000000, 0xffffffff },
10120 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10121 0x00000000, 0xffffffff },
10122 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10123 0x00000000, 0xffffffff },
10124 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10125 0x00000000, 0xffffffff },
10126 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10127 0x00000000, 0xffffffff },
10128 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10129 0xffffffff, 0x00000000 },
10130 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10131 0xffffffff, 0x00000000 },
10132
10133 /* Buffer Manager Control Registers. */
10134 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10135 0x00000000, 0x007fff80 },
10136 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10137 0x00000000, 0x007fffff },
10138 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10139 0x00000000, 0x0000003f },
10140 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10141 0x00000000, 0x000001ff },
10142 { BUFMGR_MB_HIGH_WATER, 0x0000,
10143 0x00000000, 0x000001ff },
10144 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10145 0xffffffff, 0x00000000 },
10146 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10147 0xffffffff, 0x00000000 },
10148
10149 /* Mailbox Registers */
10150 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10151 0x00000000, 0x000001ff },
10152 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10153 0x00000000, 0x000001ff },
10154 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10155 0x00000000, 0x000007ff },
10156 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10157 0x00000000, 0x000001ff },
10158
10159 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10160 };
10161
10162 is_5705 = is_5750 = 0;
10163 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10164 is_5705 = 1;
10165 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10166 is_5750 = 1;
10167 }
10168
10169 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10170 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10171 continue;
10172
10173 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10174 continue;
10175
10176 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10177 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10178 continue;
10179
10180 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10181 continue;
10182
10183 offset = (u32) reg_tbl[i].offset;
10184 read_mask = reg_tbl[i].read_mask;
10185 write_mask = reg_tbl[i].write_mask;
10186
10187 /* Save the original register content */
10188 save_val = tr32(offset);
10189
10190 /* Determine the read-only value. */
10191 read_val = save_val & read_mask;
10192
10193 /* Write zero to the register, then make sure the read-only bits
10194 * are not changed and the read/write bits are all zeros.
10195 */
10196 tw32(offset, 0);
10197
10198 val = tr32(offset);
10199
10200 /* Test the read-only and read/write bits. */
10201 if (((val & read_mask) != read_val) || (val & write_mask))
10202 goto out;
10203
10204 /* Write ones to all the bits defined by RdMask and WrMask, then
10205 * make sure the read-only bits are not changed and the
10206 * read/write bits are all ones.
10207 */
10208 tw32(offset, read_mask | write_mask);
10209
10210 val = tr32(offset);
10211
10212 /* Test the read-only bits. */
10213 if ((val & read_mask) != read_val)
10214 goto out;
10215
10216 /* Test the read/write bits. */
10217 if ((val & write_mask) != write_mask)
10218 goto out;
10219
10220 tw32(offset, save_val);
10221 }
10222
10223 return 0;
10224
10225 out:
10226 if (netif_msg_hw(tp))
10227 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10228 offset);
10229 tw32(offset, save_val);
10230 return -EIO;
10231 }
10232
10233 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10234 {
10235 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10236 int i;
10237 u32 j;
10238
10239 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10240 for (j = 0; j < len; j += 4) {
10241 u32 val;
10242
10243 tg3_write_mem(tp, offset + j, test_pattern[i]);
10244 tg3_read_mem(tp, offset + j, &val);
10245 if (val != test_pattern[i])
10246 return -EIO;
10247 }
10248 }
10249 return 0;
10250 }
10251
10252 static int tg3_test_memory(struct tg3 *tp)
10253 {
10254 static struct mem_entry {
10255 u32 offset;
10256 u32 len;
10257 } mem_tbl_570x[] = {
10258 { 0x00000000, 0x00b50},
10259 { 0x00002000, 0x1c000},
10260 { 0xffffffff, 0x00000}
10261 }, mem_tbl_5705[] = {
10262 { 0x00000100, 0x0000c},
10263 { 0x00000200, 0x00008},
10264 { 0x00004000, 0x00800},
10265 { 0x00006000, 0x01000},
10266 { 0x00008000, 0x02000},
10267 { 0x00010000, 0x0e000},
10268 { 0xffffffff, 0x00000}
10269 }, mem_tbl_5755[] = {
10270 { 0x00000200, 0x00008},
10271 { 0x00004000, 0x00800},
10272 { 0x00006000, 0x00800},
10273 { 0x00008000, 0x02000},
10274 { 0x00010000, 0x0c000},
10275 { 0xffffffff, 0x00000}
10276 }, mem_tbl_5906[] = {
10277 { 0x00000200, 0x00008},
10278 { 0x00004000, 0x00400},
10279 { 0x00006000, 0x00400},
10280 { 0x00008000, 0x01000},
10281 { 0x00010000, 0x01000},
10282 { 0xffffffff, 0x00000}
10283 };
10284 struct mem_entry *mem_tbl;
10285 int err = 0;
10286 int i;
10287
10288 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10289 mem_tbl = mem_tbl_5755;
10290 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10291 mem_tbl = mem_tbl_5906;
10292 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10293 mem_tbl = mem_tbl_5705;
10294 else
10295 mem_tbl = mem_tbl_570x;
10296
10297 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10298 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10299 mem_tbl[i].len)) != 0)
10300 break;
10301 }
10302
10303 return err;
10304 }
10305
10306 #define TG3_MAC_LOOPBACK 0
10307 #define TG3_PHY_LOOPBACK 1
10308
10309 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10310 {
10311 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10312 u32 desc_idx, coal_now;
10313 struct sk_buff *skb, *rx_skb;
10314 u8 *tx_data;
10315 dma_addr_t map;
10316 int num_pkts, tx_len, rx_len, i, err;
10317 struct tg3_rx_buffer_desc *desc;
10318 struct tg3_napi *tnapi, *rnapi;
10319 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10320
10321 if (tp->irq_cnt > 1) {
10322 tnapi = &tp->napi[1];
10323 rnapi = &tp->napi[1];
10324 } else {
10325 tnapi = &tp->napi[0];
10326 rnapi = &tp->napi[0];
10327 }
10328 coal_now = tnapi->coal_now | rnapi->coal_now;
10329
10330 if (loopback_mode == TG3_MAC_LOOPBACK) {
10331 /* HW errata - mac loopback fails in some cases on 5780.
10332 * Normal traffic and PHY loopback are not affected by
10333 * errata.
10334 */
10335 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10336 return 0;
10337
10338 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10339 MAC_MODE_PORT_INT_LPBACK;
10340 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10341 mac_mode |= MAC_MODE_LINK_POLARITY;
10342 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10343 mac_mode |= MAC_MODE_PORT_MODE_MII;
10344 else
10345 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10346 tw32(MAC_MODE, mac_mode);
10347 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10348 u32 val;
10349
10350 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10351 tg3_phy_fet_toggle_apd(tp, false);
10352 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10353 } else
10354 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10355
10356 tg3_phy_toggle_automdix(tp, 0);
10357
10358 tg3_writephy(tp, MII_BMCR, val);
10359 udelay(40);
10360
10361 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10362 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10363 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10364 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
10365 mac_mode |= MAC_MODE_PORT_MODE_MII;
10366 } else
10367 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10368
10369 /* reset to prevent losing 1st rx packet intermittently */
10370 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10371 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10372 udelay(10);
10373 tw32_f(MAC_RX_MODE, tp->rx_mode);
10374 }
10375 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10376 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10377 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10378 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10379 mac_mode |= MAC_MODE_LINK_POLARITY;
10380 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10381 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10382 }
10383 tw32(MAC_MODE, mac_mode);
10384 }
10385 else
10386 return -EINVAL;
10387
10388 err = -EIO;
10389
10390 tx_len = 1514;
10391 skb = netdev_alloc_skb(tp->dev, tx_len);
10392 if (!skb)
10393 return -ENOMEM;
10394
10395 tx_data = skb_put(skb, tx_len);
10396 memcpy(tx_data, tp->dev->dev_addr, 6);
10397 memset(tx_data + 6, 0x0, 8);
10398
10399 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10400
10401 for (i = 14; i < tx_len; i++)
10402 tx_data[i] = (u8) (i & 0xff);
10403
10404 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
10405 dev_kfree_skb(skb);
10406 return -EIO;
10407 }
10408
10409 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10410 rnapi->coal_now);
10411
10412 udelay(10);
10413
10414 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10415
10416 num_pkts = 0;
10417
10418 tg3_set_txd(tnapi, tnapi->tx_prod,
10419 skb_shinfo(skb)->dma_head, tx_len, 0, 1);
10420
10421 tnapi->tx_prod++;
10422 num_pkts++;
10423
10424 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10425 tr32_mailbox(tnapi->prodmbox);
10426
10427 udelay(10);
10428
10429 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10430 for (i = 0; i < 35; i++) {
10431 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10432 coal_now);
10433
10434 udelay(10);
10435
10436 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10437 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10438 if ((tx_idx == tnapi->tx_prod) &&
10439 (rx_idx == (rx_start_idx + num_pkts)))
10440 break;
10441 }
10442
10443 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
10444 dev_kfree_skb(skb);
10445
10446 if (tx_idx != tnapi->tx_prod)
10447 goto out;
10448
10449 if (rx_idx != rx_start_idx + num_pkts)
10450 goto out;
10451
10452 desc = &rnapi->rx_rcb[rx_start_idx];
10453 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10454 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10455 if (opaque_key != RXD_OPAQUE_RING_STD)
10456 goto out;
10457
10458 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10459 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10460 goto out;
10461
10462 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10463 if (rx_len != tx_len)
10464 goto out;
10465
10466 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10467
10468 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10469 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10470
10471 for (i = 14; i < tx_len; i++) {
10472 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10473 goto out;
10474 }
10475 err = 0;
10476
10477 /* tg3_free_rings will unmap and free the rx_skb */
10478 out:
10479 return err;
10480 }
10481
10482 #define TG3_MAC_LOOPBACK_FAILED 1
10483 #define TG3_PHY_LOOPBACK_FAILED 2
10484 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10485 TG3_PHY_LOOPBACK_FAILED)
10486
10487 static int tg3_test_loopback(struct tg3 *tp)
10488 {
10489 int err = 0;
10490 u32 cpmuctrl = 0;
10491
10492 if (!netif_running(tp->dev))
10493 return TG3_LOOPBACK_FAILED;
10494
10495 err = tg3_reset_hw(tp, 1);
10496 if (err)
10497 return TG3_LOOPBACK_FAILED;
10498
10499 /* Turn off gphy autopowerdown. */
10500 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10501 tg3_phy_toggle_apd(tp, false);
10502
10503 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10504 int i;
10505 u32 status;
10506
10507 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10508
10509 /* Wait for up to 40 microseconds to acquire lock. */
10510 for (i = 0; i < 4; i++) {
10511 status = tr32(TG3_CPMU_MUTEX_GNT);
10512 if (status == CPMU_MUTEX_GNT_DRIVER)
10513 break;
10514 udelay(10);
10515 }
10516
10517 if (status != CPMU_MUTEX_GNT_DRIVER)
10518 return TG3_LOOPBACK_FAILED;
10519
10520 /* Turn off link-based power management. */
10521 cpmuctrl = tr32(TG3_CPMU_CTRL);
10522 tw32(TG3_CPMU_CTRL,
10523 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10524 CPMU_CTRL_LINK_AWARE_MODE));
10525 }
10526
10527 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10528 err |= TG3_MAC_LOOPBACK_FAILED;
10529
10530 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10531 tw32(TG3_CPMU_CTRL, cpmuctrl);
10532
10533 /* Release the mutex */
10534 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10535 }
10536
10537 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10538 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10539 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10540 err |= TG3_PHY_LOOPBACK_FAILED;
10541 }
10542
10543 /* Re-enable gphy autopowerdown. */
10544 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10545 tg3_phy_toggle_apd(tp, true);
10546
10547 return err;
10548 }
10549
10550 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10551 u64 *data)
10552 {
10553 struct tg3 *tp = netdev_priv(dev);
10554
10555 if (tp->link_config.phy_is_low_power)
10556 tg3_set_power_state(tp, PCI_D0);
10557
10558 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10559
10560 if (tg3_test_nvram(tp) != 0) {
10561 etest->flags |= ETH_TEST_FL_FAILED;
10562 data[0] = 1;
10563 }
10564 if (tg3_test_link(tp) != 0) {
10565 etest->flags |= ETH_TEST_FL_FAILED;
10566 data[1] = 1;
10567 }
10568 if (etest->flags & ETH_TEST_FL_OFFLINE) {
10569 int err, err2 = 0, irq_sync = 0;
10570
10571 if (netif_running(dev)) {
10572 tg3_phy_stop(tp);
10573 tg3_netif_stop(tp);
10574 irq_sync = 1;
10575 }
10576
10577 tg3_full_lock(tp, irq_sync);
10578
10579 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10580 err = tg3_nvram_lock(tp);
10581 tg3_halt_cpu(tp, RX_CPU_BASE);
10582 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10583 tg3_halt_cpu(tp, TX_CPU_BASE);
10584 if (!err)
10585 tg3_nvram_unlock(tp);
10586
10587 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10588 tg3_phy_reset(tp);
10589
10590 if (tg3_test_registers(tp) != 0) {
10591 etest->flags |= ETH_TEST_FL_FAILED;
10592 data[2] = 1;
10593 }
10594 if (tg3_test_memory(tp) != 0) {
10595 etest->flags |= ETH_TEST_FL_FAILED;
10596 data[3] = 1;
10597 }
10598 if ((data[4] = tg3_test_loopback(tp)) != 0)
10599 etest->flags |= ETH_TEST_FL_FAILED;
10600
10601 tg3_full_unlock(tp);
10602
10603 if (tg3_test_interrupt(tp) != 0) {
10604 etest->flags |= ETH_TEST_FL_FAILED;
10605 data[5] = 1;
10606 }
10607
10608 tg3_full_lock(tp, 0);
10609
10610 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10611 if (netif_running(dev)) {
10612 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10613 err2 = tg3_restart_hw(tp, 1);
10614 if (!err2)
10615 tg3_netif_start(tp);
10616 }
10617
10618 tg3_full_unlock(tp);
10619
10620 if (irq_sync && !err2)
10621 tg3_phy_start(tp);
10622 }
10623 if (tp->link_config.phy_is_low_power)
10624 tg3_set_power_state(tp, PCI_D3hot);
10625
10626 }
10627
10628 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10629 {
10630 struct mii_ioctl_data *data = if_mii(ifr);
10631 struct tg3 *tp = netdev_priv(dev);
10632 int err;
10633
10634 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10635 struct phy_device *phydev;
10636 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10637 return -EAGAIN;
10638 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10639 return phy_mii_ioctl(phydev, data, cmd);
10640 }
10641
10642 switch(cmd) {
10643 case SIOCGMIIPHY:
10644 data->phy_id = tp->phy_addr;
10645
10646 /* fallthru */
10647 case SIOCGMIIREG: {
10648 u32 mii_regval;
10649
10650 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10651 break; /* We have no PHY */
10652
10653 if (tp->link_config.phy_is_low_power)
10654 return -EAGAIN;
10655
10656 spin_lock_bh(&tp->lock);
10657 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10658 spin_unlock_bh(&tp->lock);
10659
10660 data->val_out = mii_regval;
10661
10662 return err;
10663 }
10664
10665 case SIOCSMIIREG:
10666 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10667 break; /* We have no PHY */
10668
10669 if (tp->link_config.phy_is_low_power)
10670 return -EAGAIN;
10671
10672 spin_lock_bh(&tp->lock);
10673 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10674 spin_unlock_bh(&tp->lock);
10675
10676 return err;
10677
10678 default:
10679 /* do nothing */
10680 break;
10681 }
10682 return -EOPNOTSUPP;
10683 }
10684
10685 #if TG3_VLAN_TAG_USED
10686 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10687 {
10688 struct tg3 *tp = netdev_priv(dev);
10689
10690 if (!netif_running(dev)) {
10691 tp->vlgrp = grp;
10692 return;
10693 }
10694
10695 tg3_netif_stop(tp);
10696
10697 tg3_full_lock(tp, 0);
10698
10699 tp->vlgrp = grp;
10700
10701 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10702 __tg3_set_rx_mode(dev);
10703
10704 tg3_netif_start(tp);
10705
10706 tg3_full_unlock(tp);
10707 }
10708 #endif
10709
10710 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10711 {
10712 struct tg3 *tp = netdev_priv(dev);
10713
10714 memcpy(ec, &tp->coal, sizeof(*ec));
10715 return 0;
10716 }
10717
10718 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10719 {
10720 struct tg3 *tp = netdev_priv(dev);
10721 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10722 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10723
10724 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10725 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10726 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10727 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10728 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10729 }
10730
10731 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10732 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10733 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10734 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10735 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10736 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10737 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10738 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10739 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10740 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10741 return -EINVAL;
10742
10743 /* No rx interrupts will be generated if both are zero */
10744 if ((ec->rx_coalesce_usecs == 0) &&
10745 (ec->rx_max_coalesced_frames == 0))
10746 return -EINVAL;
10747
10748 /* No tx interrupts will be generated if both are zero */
10749 if ((ec->tx_coalesce_usecs == 0) &&
10750 (ec->tx_max_coalesced_frames == 0))
10751 return -EINVAL;
10752
10753 /* Only copy relevant parameters, ignore all others. */
10754 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10755 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10756 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10757 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10758 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10759 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10760 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10761 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10762 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10763
10764 if (netif_running(dev)) {
10765 tg3_full_lock(tp, 0);
10766 __tg3_set_coalesce(tp, &tp->coal);
10767 tg3_full_unlock(tp);
10768 }
10769 return 0;
10770 }
10771
10772 static const struct ethtool_ops tg3_ethtool_ops = {
10773 .get_settings = tg3_get_settings,
10774 .set_settings = tg3_set_settings,
10775 .get_drvinfo = tg3_get_drvinfo,
10776 .get_regs_len = tg3_get_regs_len,
10777 .get_regs = tg3_get_regs,
10778 .get_wol = tg3_get_wol,
10779 .set_wol = tg3_set_wol,
10780 .get_msglevel = tg3_get_msglevel,
10781 .set_msglevel = tg3_set_msglevel,
10782 .nway_reset = tg3_nway_reset,
10783 .get_link = ethtool_op_get_link,
10784 .get_eeprom_len = tg3_get_eeprom_len,
10785 .get_eeprom = tg3_get_eeprom,
10786 .set_eeprom = tg3_set_eeprom,
10787 .get_ringparam = tg3_get_ringparam,
10788 .set_ringparam = tg3_set_ringparam,
10789 .get_pauseparam = tg3_get_pauseparam,
10790 .set_pauseparam = tg3_set_pauseparam,
10791 .get_rx_csum = tg3_get_rx_csum,
10792 .set_rx_csum = tg3_set_rx_csum,
10793 .set_tx_csum = tg3_set_tx_csum,
10794 .set_sg = ethtool_op_set_sg,
10795 .set_tso = tg3_set_tso,
10796 .self_test = tg3_self_test,
10797 .get_strings = tg3_get_strings,
10798 .phys_id = tg3_phys_id,
10799 .get_ethtool_stats = tg3_get_ethtool_stats,
10800 .get_coalesce = tg3_get_coalesce,
10801 .set_coalesce = tg3_set_coalesce,
10802 .get_sset_count = tg3_get_sset_count,
10803 };
10804
10805 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10806 {
10807 u32 cursize, val, magic;
10808
10809 tp->nvram_size = EEPROM_CHIP_SIZE;
10810
10811 if (tg3_nvram_read(tp, 0, &magic) != 0)
10812 return;
10813
10814 if ((magic != TG3_EEPROM_MAGIC) &&
10815 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10816 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
10817 return;
10818
10819 /*
10820 * Size the chip by reading offsets at increasing powers of two.
10821 * When we encounter our validation signature, we know the addressing
10822 * has wrapped around, and thus have our chip size.
10823 */
10824 cursize = 0x10;
10825
10826 while (cursize < tp->nvram_size) {
10827 if (tg3_nvram_read(tp, cursize, &val) != 0)
10828 return;
10829
10830 if (val == magic)
10831 break;
10832
10833 cursize <<= 1;
10834 }
10835
10836 tp->nvram_size = cursize;
10837 }
10838
10839 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10840 {
10841 u32 val;
10842
10843 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10844 tg3_nvram_read(tp, 0, &val) != 0)
10845 return;
10846
10847 /* Selfboot format */
10848 if (val != TG3_EEPROM_MAGIC) {
10849 tg3_get_eeprom_size(tp);
10850 return;
10851 }
10852
10853 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
10854 if (val != 0) {
10855 /* This is confusing. We want to operate on the
10856 * 16-bit value at offset 0xf2. The tg3_nvram_read()
10857 * call will read from NVRAM and byteswap the data
10858 * according to the byteswapping settings for all
10859 * other register accesses. This ensures the data we
10860 * want will always reside in the lower 16-bits.
10861 * However, the data in NVRAM is in LE format, which
10862 * means the data from the NVRAM read will always be
10863 * opposite the endianness of the CPU. The 16-bit
10864 * byteswap then brings the data to CPU endianness.
10865 */
10866 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
10867 return;
10868 }
10869 }
10870 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10871 }
10872
10873 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10874 {
10875 u32 nvcfg1;
10876
10877 nvcfg1 = tr32(NVRAM_CFG1);
10878 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10879 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10880 } else {
10881 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10882 tw32(NVRAM_CFG1, nvcfg1);
10883 }
10884
10885 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
10886 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10887 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10888 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10889 tp->nvram_jedecnum = JEDEC_ATMEL;
10890 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10891 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10892 break;
10893 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10894 tp->nvram_jedecnum = JEDEC_ATMEL;
10895 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10896 break;
10897 case FLASH_VENDOR_ATMEL_EEPROM:
10898 tp->nvram_jedecnum = JEDEC_ATMEL;
10899 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10900 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10901 break;
10902 case FLASH_VENDOR_ST:
10903 tp->nvram_jedecnum = JEDEC_ST;
10904 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10905 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10906 break;
10907 case FLASH_VENDOR_SAIFUN:
10908 tp->nvram_jedecnum = JEDEC_SAIFUN;
10909 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10910 break;
10911 case FLASH_VENDOR_SST_SMALL:
10912 case FLASH_VENDOR_SST_LARGE:
10913 tp->nvram_jedecnum = JEDEC_SST;
10914 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10915 break;
10916 }
10917 } else {
10918 tp->nvram_jedecnum = JEDEC_ATMEL;
10919 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10920 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10921 }
10922 }
10923
10924 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
10925 {
10926 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10927 case FLASH_5752PAGE_SIZE_256:
10928 tp->nvram_pagesize = 256;
10929 break;
10930 case FLASH_5752PAGE_SIZE_512:
10931 tp->nvram_pagesize = 512;
10932 break;
10933 case FLASH_5752PAGE_SIZE_1K:
10934 tp->nvram_pagesize = 1024;
10935 break;
10936 case FLASH_5752PAGE_SIZE_2K:
10937 tp->nvram_pagesize = 2048;
10938 break;
10939 case FLASH_5752PAGE_SIZE_4K:
10940 tp->nvram_pagesize = 4096;
10941 break;
10942 case FLASH_5752PAGE_SIZE_264:
10943 tp->nvram_pagesize = 264;
10944 break;
10945 case FLASH_5752PAGE_SIZE_528:
10946 tp->nvram_pagesize = 528;
10947 break;
10948 }
10949 }
10950
10951 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10952 {
10953 u32 nvcfg1;
10954
10955 nvcfg1 = tr32(NVRAM_CFG1);
10956
10957 /* NVRAM protection for TPM */
10958 if (nvcfg1 & (1 << 27))
10959 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10960
10961 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10962 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10963 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10964 tp->nvram_jedecnum = JEDEC_ATMEL;
10965 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10966 break;
10967 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10968 tp->nvram_jedecnum = JEDEC_ATMEL;
10969 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10970 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10971 break;
10972 case FLASH_5752VENDOR_ST_M45PE10:
10973 case FLASH_5752VENDOR_ST_M45PE20:
10974 case FLASH_5752VENDOR_ST_M45PE40:
10975 tp->nvram_jedecnum = JEDEC_ST;
10976 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10977 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10978 break;
10979 }
10980
10981 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10982 tg3_nvram_get_pagesize(tp, nvcfg1);
10983 } else {
10984 /* For eeprom, set pagesize to maximum eeprom size */
10985 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10986
10987 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10988 tw32(NVRAM_CFG1, nvcfg1);
10989 }
10990 }
10991
10992 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10993 {
10994 u32 nvcfg1, protect = 0;
10995
10996 nvcfg1 = tr32(NVRAM_CFG1);
10997
10998 /* NVRAM protection for TPM */
10999 if (nvcfg1 & (1 << 27)) {
11000 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
11001 protect = 1;
11002 }
11003
11004 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11005 switch (nvcfg1) {
11006 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11007 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11008 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11009 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11010 tp->nvram_jedecnum = JEDEC_ATMEL;
11011 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11012 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11013 tp->nvram_pagesize = 264;
11014 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11015 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11016 tp->nvram_size = (protect ? 0x3e200 :
11017 TG3_NVRAM_SIZE_512KB);
11018 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11019 tp->nvram_size = (protect ? 0x1f200 :
11020 TG3_NVRAM_SIZE_256KB);
11021 else
11022 tp->nvram_size = (protect ? 0x1f200 :
11023 TG3_NVRAM_SIZE_128KB);
11024 break;
11025 case FLASH_5752VENDOR_ST_M45PE10:
11026 case FLASH_5752VENDOR_ST_M45PE20:
11027 case FLASH_5752VENDOR_ST_M45PE40:
11028 tp->nvram_jedecnum = JEDEC_ST;
11029 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11030 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11031 tp->nvram_pagesize = 256;
11032 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11033 tp->nvram_size = (protect ?
11034 TG3_NVRAM_SIZE_64KB :
11035 TG3_NVRAM_SIZE_128KB);
11036 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11037 tp->nvram_size = (protect ?
11038 TG3_NVRAM_SIZE_64KB :
11039 TG3_NVRAM_SIZE_256KB);
11040 else
11041 tp->nvram_size = (protect ?
11042 TG3_NVRAM_SIZE_128KB :
11043 TG3_NVRAM_SIZE_512KB);
11044 break;
11045 }
11046 }
11047
11048 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11049 {
11050 u32 nvcfg1;
11051
11052 nvcfg1 = tr32(NVRAM_CFG1);
11053
11054 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11055 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11056 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11057 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11058 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11059 tp->nvram_jedecnum = JEDEC_ATMEL;
11060 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11061 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11062
11063 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11064 tw32(NVRAM_CFG1, nvcfg1);
11065 break;
11066 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11067 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11068 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11069 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11070 tp->nvram_jedecnum = JEDEC_ATMEL;
11071 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11072 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11073 tp->nvram_pagesize = 264;
11074 break;
11075 case FLASH_5752VENDOR_ST_M45PE10:
11076 case FLASH_5752VENDOR_ST_M45PE20:
11077 case FLASH_5752VENDOR_ST_M45PE40:
11078 tp->nvram_jedecnum = JEDEC_ST;
11079 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11080 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11081 tp->nvram_pagesize = 256;
11082 break;
11083 }
11084 }
11085
11086 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11087 {
11088 u32 nvcfg1, protect = 0;
11089
11090 nvcfg1 = tr32(NVRAM_CFG1);
11091
11092 /* NVRAM protection for TPM */
11093 if (nvcfg1 & (1 << 27)) {
11094 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
11095 protect = 1;
11096 }
11097
11098 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11099 switch (nvcfg1) {
11100 case FLASH_5761VENDOR_ATMEL_ADB021D:
11101 case FLASH_5761VENDOR_ATMEL_ADB041D:
11102 case FLASH_5761VENDOR_ATMEL_ADB081D:
11103 case FLASH_5761VENDOR_ATMEL_ADB161D:
11104 case FLASH_5761VENDOR_ATMEL_MDB021D:
11105 case FLASH_5761VENDOR_ATMEL_MDB041D:
11106 case FLASH_5761VENDOR_ATMEL_MDB081D:
11107 case FLASH_5761VENDOR_ATMEL_MDB161D:
11108 tp->nvram_jedecnum = JEDEC_ATMEL;
11109 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11110 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11111 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11112 tp->nvram_pagesize = 256;
11113 break;
11114 case FLASH_5761VENDOR_ST_A_M45PE20:
11115 case FLASH_5761VENDOR_ST_A_M45PE40:
11116 case FLASH_5761VENDOR_ST_A_M45PE80:
11117 case FLASH_5761VENDOR_ST_A_M45PE16:
11118 case FLASH_5761VENDOR_ST_M_M45PE20:
11119 case FLASH_5761VENDOR_ST_M_M45PE40:
11120 case FLASH_5761VENDOR_ST_M_M45PE80:
11121 case FLASH_5761VENDOR_ST_M_M45PE16:
11122 tp->nvram_jedecnum = JEDEC_ST;
11123 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11124 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11125 tp->nvram_pagesize = 256;
11126 break;
11127 }
11128
11129 if (protect) {
11130 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11131 } else {
11132 switch (nvcfg1) {
11133 case FLASH_5761VENDOR_ATMEL_ADB161D:
11134 case FLASH_5761VENDOR_ATMEL_MDB161D:
11135 case FLASH_5761VENDOR_ST_A_M45PE16:
11136 case FLASH_5761VENDOR_ST_M_M45PE16:
11137 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11138 break;
11139 case FLASH_5761VENDOR_ATMEL_ADB081D:
11140 case FLASH_5761VENDOR_ATMEL_MDB081D:
11141 case FLASH_5761VENDOR_ST_A_M45PE80:
11142 case FLASH_5761VENDOR_ST_M_M45PE80:
11143 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11144 break;
11145 case FLASH_5761VENDOR_ATMEL_ADB041D:
11146 case FLASH_5761VENDOR_ATMEL_MDB041D:
11147 case FLASH_5761VENDOR_ST_A_M45PE40:
11148 case FLASH_5761VENDOR_ST_M_M45PE40:
11149 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11150 break;
11151 case FLASH_5761VENDOR_ATMEL_ADB021D:
11152 case FLASH_5761VENDOR_ATMEL_MDB021D:
11153 case FLASH_5761VENDOR_ST_A_M45PE20:
11154 case FLASH_5761VENDOR_ST_M_M45PE20:
11155 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11156 break;
11157 }
11158 }
11159 }
11160
11161 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11162 {
11163 tp->nvram_jedecnum = JEDEC_ATMEL;
11164 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11165 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11166 }
11167
11168 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11169 {
11170 u32 nvcfg1;
11171
11172 nvcfg1 = tr32(NVRAM_CFG1);
11173
11174 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11175 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11176 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11177 tp->nvram_jedecnum = JEDEC_ATMEL;
11178 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11179 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11180
11181 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11182 tw32(NVRAM_CFG1, nvcfg1);
11183 return;
11184 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11185 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11186 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11187 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11188 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11189 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11190 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11191 tp->nvram_jedecnum = JEDEC_ATMEL;
11192 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11193 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11194
11195 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11196 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11197 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11198 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11199 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11200 break;
11201 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11202 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11203 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11204 break;
11205 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11206 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11207 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11208 break;
11209 }
11210 break;
11211 case FLASH_5752VENDOR_ST_M45PE10:
11212 case FLASH_5752VENDOR_ST_M45PE20:
11213 case FLASH_5752VENDOR_ST_M45PE40:
11214 tp->nvram_jedecnum = JEDEC_ST;
11215 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11216 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11217
11218 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11219 case FLASH_5752VENDOR_ST_M45PE10:
11220 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11221 break;
11222 case FLASH_5752VENDOR_ST_M45PE20:
11223 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11224 break;
11225 case FLASH_5752VENDOR_ST_M45PE40:
11226 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11227 break;
11228 }
11229 break;
11230 default:
11231 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11232 return;
11233 }
11234
11235 tg3_nvram_get_pagesize(tp, nvcfg1);
11236 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11237 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11238 }
11239
11240
11241 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11242 {
11243 u32 nvcfg1;
11244
11245 nvcfg1 = tr32(NVRAM_CFG1);
11246
11247 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11248 case FLASH_5717VENDOR_ATMEL_EEPROM:
11249 case FLASH_5717VENDOR_MICRO_EEPROM:
11250 tp->nvram_jedecnum = JEDEC_ATMEL;
11251 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11252 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11253
11254 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11255 tw32(NVRAM_CFG1, nvcfg1);
11256 return;
11257 case FLASH_5717VENDOR_ATMEL_MDB011D:
11258 case FLASH_5717VENDOR_ATMEL_ADB011B:
11259 case FLASH_5717VENDOR_ATMEL_ADB011D:
11260 case FLASH_5717VENDOR_ATMEL_MDB021D:
11261 case FLASH_5717VENDOR_ATMEL_ADB021B:
11262 case FLASH_5717VENDOR_ATMEL_ADB021D:
11263 case FLASH_5717VENDOR_ATMEL_45USPT:
11264 tp->nvram_jedecnum = JEDEC_ATMEL;
11265 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11266 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11267
11268 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11269 case FLASH_5717VENDOR_ATMEL_MDB021D:
11270 case FLASH_5717VENDOR_ATMEL_ADB021B:
11271 case FLASH_5717VENDOR_ATMEL_ADB021D:
11272 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11273 break;
11274 default:
11275 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11276 break;
11277 }
11278 break;
11279 case FLASH_5717VENDOR_ST_M_M25PE10:
11280 case FLASH_5717VENDOR_ST_A_M25PE10:
11281 case FLASH_5717VENDOR_ST_M_M45PE10:
11282 case FLASH_5717VENDOR_ST_A_M45PE10:
11283 case FLASH_5717VENDOR_ST_M_M25PE20:
11284 case FLASH_5717VENDOR_ST_A_M25PE20:
11285 case FLASH_5717VENDOR_ST_M_M45PE20:
11286 case FLASH_5717VENDOR_ST_A_M45PE20:
11287 case FLASH_5717VENDOR_ST_25USPT:
11288 case FLASH_5717VENDOR_ST_45USPT:
11289 tp->nvram_jedecnum = JEDEC_ST;
11290 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11291 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11292
11293 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11294 case FLASH_5717VENDOR_ST_M_M25PE20:
11295 case FLASH_5717VENDOR_ST_A_M25PE20:
11296 case FLASH_5717VENDOR_ST_M_M45PE20:
11297 case FLASH_5717VENDOR_ST_A_M45PE20:
11298 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11299 break;
11300 default:
11301 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11302 break;
11303 }
11304 break;
11305 default:
11306 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11307 return;
11308 }
11309
11310 tg3_nvram_get_pagesize(tp, nvcfg1);
11311 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11312 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11313 }
11314
11315 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11316 static void __devinit tg3_nvram_init(struct tg3 *tp)
11317 {
11318 tw32_f(GRC_EEPROM_ADDR,
11319 (EEPROM_ADDR_FSM_RESET |
11320 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11321 EEPROM_ADDR_CLKPERD_SHIFT)));
11322
11323 msleep(1);
11324
11325 /* Enable seeprom accesses. */
11326 tw32_f(GRC_LOCAL_CTRL,
11327 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11328 udelay(100);
11329
11330 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11331 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11332 tp->tg3_flags |= TG3_FLAG_NVRAM;
11333
11334 if (tg3_nvram_lock(tp)) {
11335 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11336 "tg3_nvram_init failed.\n", tp->dev->name);
11337 return;
11338 }
11339 tg3_enable_nvram_access(tp);
11340
11341 tp->nvram_size = 0;
11342
11343 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11344 tg3_get_5752_nvram_info(tp);
11345 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11346 tg3_get_5755_nvram_info(tp);
11347 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11348 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11349 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11350 tg3_get_5787_nvram_info(tp);
11351 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11352 tg3_get_5761_nvram_info(tp);
11353 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11354 tg3_get_5906_nvram_info(tp);
11355 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11356 tg3_get_57780_nvram_info(tp);
11357 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11358 tg3_get_5717_nvram_info(tp);
11359 else
11360 tg3_get_nvram_info(tp);
11361
11362 if (tp->nvram_size == 0)
11363 tg3_get_nvram_size(tp);
11364
11365 tg3_disable_nvram_access(tp);
11366 tg3_nvram_unlock(tp);
11367
11368 } else {
11369 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11370
11371 tg3_get_eeprom_size(tp);
11372 }
11373 }
11374
11375 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11376 u32 offset, u32 len, u8 *buf)
11377 {
11378 int i, j, rc = 0;
11379 u32 val;
11380
11381 for (i = 0; i < len; i += 4) {
11382 u32 addr;
11383 __be32 data;
11384
11385 addr = offset + i;
11386
11387 memcpy(&data, buf + i, 4);
11388
11389 /*
11390 * The SEEPROM interface expects the data to always be opposite
11391 * the native endian format. We accomplish this by reversing
11392 * all the operations that would have been performed on the
11393 * data from a call to tg3_nvram_read_be32().
11394 */
11395 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11396
11397 val = tr32(GRC_EEPROM_ADDR);
11398 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11399
11400 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11401 EEPROM_ADDR_READ);
11402 tw32(GRC_EEPROM_ADDR, val |
11403 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11404 (addr & EEPROM_ADDR_ADDR_MASK) |
11405 EEPROM_ADDR_START |
11406 EEPROM_ADDR_WRITE);
11407
11408 for (j = 0; j < 1000; j++) {
11409 val = tr32(GRC_EEPROM_ADDR);
11410
11411 if (val & EEPROM_ADDR_COMPLETE)
11412 break;
11413 msleep(1);
11414 }
11415 if (!(val & EEPROM_ADDR_COMPLETE)) {
11416 rc = -EBUSY;
11417 break;
11418 }
11419 }
11420
11421 return rc;
11422 }
11423
11424 /* offset and length are dword aligned */
11425 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11426 u8 *buf)
11427 {
11428 int ret = 0;
11429 u32 pagesize = tp->nvram_pagesize;
11430 u32 pagemask = pagesize - 1;
11431 u32 nvram_cmd;
11432 u8 *tmp;
11433
11434 tmp = kmalloc(pagesize, GFP_KERNEL);
11435 if (tmp == NULL)
11436 return -ENOMEM;
11437
11438 while (len) {
11439 int j;
11440 u32 phy_addr, page_off, size;
11441
11442 phy_addr = offset & ~pagemask;
11443
11444 for (j = 0; j < pagesize; j += 4) {
11445 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11446 (__be32 *) (tmp + j));
11447 if (ret)
11448 break;
11449 }
11450 if (ret)
11451 break;
11452
11453 page_off = offset & pagemask;
11454 size = pagesize;
11455 if (len < size)
11456 size = len;
11457
11458 len -= size;
11459
11460 memcpy(tmp + page_off, buf, size);
11461
11462 offset = offset + (pagesize - page_off);
11463
11464 tg3_enable_nvram_access(tp);
11465
11466 /*
11467 * Before we can erase the flash page, we need
11468 * to issue a special "write enable" command.
11469 */
11470 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11471
11472 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11473 break;
11474
11475 /* Erase the target page */
11476 tw32(NVRAM_ADDR, phy_addr);
11477
11478 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11479 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11480
11481 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11482 break;
11483
11484 /* Issue another write enable to start the write. */
11485 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11486
11487 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11488 break;
11489
11490 for (j = 0; j < pagesize; j += 4) {
11491 __be32 data;
11492
11493 data = *((__be32 *) (tmp + j));
11494
11495 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11496
11497 tw32(NVRAM_ADDR, phy_addr + j);
11498
11499 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11500 NVRAM_CMD_WR;
11501
11502 if (j == 0)
11503 nvram_cmd |= NVRAM_CMD_FIRST;
11504 else if (j == (pagesize - 4))
11505 nvram_cmd |= NVRAM_CMD_LAST;
11506
11507 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11508 break;
11509 }
11510 if (ret)
11511 break;
11512 }
11513
11514 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11515 tg3_nvram_exec_cmd(tp, nvram_cmd);
11516
11517 kfree(tmp);
11518
11519 return ret;
11520 }
11521
11522 /* offset and length are dword aligned */
11523 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11524 u8 *buf)
11525 {
11526 int i, ret = 0;
11527
11528 for (i = 0; i < len; i += 4, offset += 4) {
11529 u32 page_off, phy_addr, nvram_cmd;
11530 __be32 data;
11531
11532 memcpy(&data, buf + i, 4);
11533 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11534
11535 page_off = offset % tp->nvram_pagesize;
11536
11537 phy_addr = tg3_nvram_phys_addr(tp, offset);
11538
11539 tw32(NVRAM_ADDR, phy_addr);
11540
11541 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11542
11543 if ((page_off == 0) || (i == 0))
11544 nvram_cmd |= NVRAM_CMD_FIRST;
11545 if (page_off == (tp->nvram_pagesize - 4))
11546 nvram_cmd |= NVRAM_CMD_LAST;
11547
11548 if (i == (len - 4))
11549 nvram_cmd |= NVRAM_CMD_LAST;
11550
11551 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11552 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11553 (tp->nvram_jedecnum == JEDEC_ST) &&
11554 (nvram_cmd & NVRAM_CMD_FIRST)) {
11555
11556 if ((ret = tg3_nvram_exec_cmd(tp,
11557 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11558 NVRAM_CMD_DONE)))
11559
11560 break;
11561 }
11562 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11563 /* We always do complete word writes to eeprom. */
11564 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11565 }
11566
11567 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11568 break;
11569 }
11570 return ret;
11571 }
11572
11573 /* offset and length are dword aligned */
11574 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11575 {
11576 int ret;
11577
11578 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11579 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11580 ~GRC_LCLCTRL_GPIO_OUTPUT1);
11581 udelay(40);
11582 }
11583
11584 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11585 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11586 }
11587 else {
11588 u32 grc_mode;
11589
11590 ret = tg3_nvram_lock(tp);
11591 if (ret)
11592 return ret;
11593
11594 tg3_enable_nvram_access(tp);
11595 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11596 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
11597 tw32(NVRAM_WRITE1, 0x406);
11598
11599 grc_mode = tr32(GRC_MODE);
11600 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11601
11602 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11603 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11604
11605 ret = tg3_nvram_write_block_buffered(tp, offset, len,
11606 buf);
11607 }
11608 else {
11609 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11610 buf);
11611 }
11612
11613 grc_mode = tr32(GRC_MODE);
11614 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11615
11616 tg3_disable_nvram_access(tp);
11617 tg3_nvram_unlock(tp);
11618 }
11619
11620 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11621 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11622 udelay(40);
11623 }
11624
11625 return ret;
11626 }
11627
11628 struct subsys_tbl_ent {
11629 u16 subsys_vendor, subsys_devid;
11630 u32 phy_id;
11631 };
11632
11633 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11634 /* Broadcom boards. */
11635 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11636 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11637 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11638 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
11639 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11640 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11641 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
11642 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11643 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11644 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11645 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11646
11647 /* 3com boards. */
11648 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11649 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11650 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
11651 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11652 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11653
11654 /* DELL boards. */
11655 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11656 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11657 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11658 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11659
11660 /* Compaq boards. */
11661 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11662 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11663 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
11664 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11665 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11666
11667 /* IBM boards. */
11668 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11669 };
11670
11671 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11672 {
11673 int i;
11674
11675 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11676 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11677 tp->pdev->subsystem_vendor) &&
11678 (subsys_id_to_phy_id[i].subsys_devid ==
11679 tp->pdev->subsystem_device))
11680 return &subsys_id_to_phy_id[i];
11681 }
11682 return NULL;
11683 }
11684
11685 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11686 {
11687 u32 val;
11688 u16 pmcsr;
11689
11690 /* On some early chips the SRAM cannot be accessed in D3hot state,
11691 * so need make sure we're in D0.
11692 */
11693 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11694 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11695 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11696 msleep(1);
11697
11698 /* Make sure register accesses (indirect or otherwise)
11699 * will function correctly.
11700 */
11701 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11702 tp->misc_host_ctrl);
11703
11704 /* The memory arbiter has to be enabled in order for SRAM accesses
11705 * to succeed. Normally on powerup the tg3 chip firmware will make
11706 * sure it is enabled, but other entities such as system netboot
11707 * code might disable it.
11708 */
11709 val = tr32(MEMARB_MODE);
11710 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11711
11712 tp->phy_id = PHY_ID_INVALID;
11713 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11714
11715 /* Assume an onboard device and WOL capable by default. */
11716 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
11717
11718 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11719 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
11720 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11721 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11722 }
11723 val = tr32(VCPU_CFGSHDW);
11724 if (val & VCPU_CFGSHDW_ASPM_DBNC)
11725 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11726 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
11727 (val & VCPU_CFGSHDW_WOL_MAGPKT))
11728 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11729 goto done;
11730 }
11731
11732 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11733 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11734 u32 nic_cfg, led_cfg;
11735 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
11736 int eeprom_phy_serdes = 0;
11737
11738 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11739 tp->nic_sram_data_cfg = nic_cfg;
11740
11741 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11742 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11743 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11744 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11745 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11746 (ver > 0) && (ver < 0x100))
11747 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11748
11749 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11750 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11751
11752 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11753 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11754 eeprom_phy_serdes = 1;
11755
11756 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11757 if (nic_phy_id != 0) {
11758 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11759 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11760
11761 eeprom_phy_id = (id1 >> 16) << 10;
11762 eeprom_phy_id |= (id2 & 0xfc00) << 16;
11763 eeprom_phy_id |= (id2 & 0x03ff) << 0;
11764 } else
11765 eeprom_phy_id = 0;
11766
11767 tp->phy_id = eeprom_phy_id;
11768 if (eeprom_phy_serdes) {
11769 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
11770 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11771 else
11772 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11773 }
11774
11775 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11776 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11777 SHASTA_EXT_LED_MODE_MASK);
11778 else
11779 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11780
11781 switch (led_cfg) {
11782 default:
11783 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11784 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11785 break;
11786
11787 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11788 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11789 break;
11790
11791 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11792 tp->led_ctrl = LED_CTRL_MODE_MAC;
11793
11794 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11795 * read on some older 5700/5701 bootcode.
11796 */
11797 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11798 ASIC_REV_5700 ||
11799 GET_ASIC_REV(tp->pci_chip_rev_id) ==
11800 ASIC_REV_5701)
11801 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11802
11803 break;
11804
11805 case SHASTA_EXT_LED_SHARED:
11806 tp->led_ctrl = LED_CTRL_MODE_SHARED;
11807 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11808 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11809 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11810 LED_CTRL_MODE_PHY_2);
11811 break;
11812
11813 case SHASTA_EXT_LED_MAC:
11814 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11815 break;
11816
11817 case SHASTA_EXT_LED_COMBO:
11818 tp->led_ctrl = LED_CTRL_MODE_COMBO;
11819 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11820 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11821 LED_CTRL_MODE_PHY_2);
11822 break;
11823
11824 }
11825
11826 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11827 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11828 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11829 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11830
11831 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11832 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11833
11834 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
11835 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
11836 if ((tp->pdev->subsystem_vendor ==
11837 PCI_VENDOR_ID_ARIMA) &&
11838 (tp->pdev->subsystem_device == 0x205a ||
11839 tp->pdev->subsystem_device == 0x2063))
11840 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11841 } else {
11842 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11843 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11844 }
11845
11846 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11847 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
11848 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11849 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11850 }
11851
11852 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11853 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11854 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
11855
11856 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11857 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11858 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11859
11860 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
11861 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
11862 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11863
11864 if (cfg2 & (1 << 17))
11865 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11866
11867 /* serdes signal pre-emphasis in register 0x590 set by */
11868 /* bootcode if bit 18 is set */
11869 if (cfg2 & (1 << 18))
11870 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
11871
11872 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11873 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
11874 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11875 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11876
11877 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11878 u32 cfg3;
11879
11880 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11881 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11882 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11883 }
11884
11885 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11886 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11887 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11888 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11889 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11890 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
11891 }
11892 done:
11893 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11894 device_set_wakeup_enable(&tp->pdev->dev,
11895 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
11896 }
11897
11898 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11899 {
11900 int i;
11901 u32 val;
11902
11903 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11904 tw32(OTP_CTRL, cmd);
11905
11906 /* Wait for up to 1 ms for command to execute. */
11907 for (i = 0; i < 100; i++) {
11908 val = tr32(OTP_STATUS);
11909 if (val & OTP_STATUS_CMD_DONE)
11910 break;
11911 udelay(10);
11912 }
11913
11914 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11915 }
11916
11917 /* Read the gphy configuration from the OTP region of the chip. The gphy
11918 * configuration is a 32-bit value that straddles the alignment boundary.
11919 * We do two 32-bit reads and then shift and merge the results.
11920 */
11921 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11922 {
11923 u32 bhalf_otp, thalf_otp;
11924
11925 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11926
11927 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11928 return 0;
11929
11930 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11931
11932 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11933 return 0;
11934
11935 thalf_otp = tr32(OTP_READ_DATA);
11936
11937 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11938
11939 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11940 return 0;
11941
11942 bhalf_otp = tr32(OTP_READ_DATA);
11943
11944 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11945 }
11946
11947 static int __devinit tg3_phy_probe(struct tg3 *tp)
11948 {
11949 u32 hw_phy_id_1, hw_phy_id_2;
11950 u32 hw_phy_id, hw_phy_id_masked;
11951 int err;
11952
11953 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11954 return tg3_phy_init(tp);
11955
11956 /* Reading the PHY ID register can conflict with ASF
11957 * firmware access to the PHY hardware.
11958 */
11959 err = 0;
11960 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11961 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
11962 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11963 } else {
11964 /* Now read the physical PHY_ID from the chip and verify
11965 * that it is sane. If it doesn't look good, we fall back
11966 * to either the hard-coded table based PHY_ID and failing
11967 * that the value found in the eeprom area.
11968 */
11969 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11970 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11971
11972 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
11973 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11974 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
11975
11976 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11977 }
11978
11979 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11980 tp->phy_id = hw_phy_id;
11981 if (hw_phy_id_masked == PHY_ID_BCM8002)
11982 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11983 else
11984 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
11985 } else {
11986 if (tp->phy_id != PHY_ID_INVALID) {
11987 /* Do nothing, phy ID already set up in
11988 * tg3_get_eeprom_hw_cfg().
11989 */
11990 } else {
11991 struct subsys_tbl_ent *p;
11992
11993 /* No eeprom signature? Try the hardcoded
11994 * subsys device table.
11995 */
11996 p = lookup_by_subsys(tp);
11997 if (!p)
11998 return -ENODEV;
11999
12000 tp->phy_id = p->phy_id;
12001 if (!tp->phy_id ||
12002 tp->phy_id == PHY_ID_BCM8002)
12003 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12004 }
12005 }
12006
12007 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
12008 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12009 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12010 u32 bmsr, adv_reg, tg3_ctrl, mask;
12011
12012 tg3_readphy(tp, MII_BMSR, &bmsr);
12013 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12014 (bmsr & BMSR_LSTATUS))
12015 goto skip_phy_reset;
12016
12017 err = tg3_phy_reset(tp);
12018 if (err)
12019 return err;
12020
12021 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12022 ADVERTISE_100HALF | ADVERTISE_100FULL |
12023 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12024 tg3_ctrl = 0;
12025 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12026 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12027 MII_TG3_CTRL_ADV_1000_FULL);
12028 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12029 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12030 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12031 MII_TG3_CTRL_ENABLE_AS_MASTER);
12032 }
12033
12034 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12035 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12036 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12037 if (!tg3_copper_is_advertising_all(tp, mask)) {
12038 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12039
12040 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12041 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12042
12043 tg3_writephy(tp, MII_BMCR,
12044 BMCR_ANENABLE | BMCR_ANRESTART);
12045 }
12046 tg3_phy_set_wirespeed(tp);
12047
12048 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12049 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12050 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12051 }
12052
12053 skip_phy_reset:
12054 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12055 err = tg3_init_5401phy_dsp(tp);
12056 if (err)
12057 return err;
12058 }
12059
12060 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12061 err = tg3_init_5401phy_dsp(tp);
12062 }
12063
12064 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
12065 tp->link_config.advertising =
12066 (ADVERTISED_1000baseT_Half |
12067 ADVERTISED_1000baseT_Full |
12068 ADVERTISED_Autoneg |
12069 ADVERTISED_FIBRE);
12070 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12071 tp->link_config.advertising &=
12072 ~(ADVERTISED_1000baseT_Half |
12073 ADVERTISED_1000baseT_Full);
12074
12075 return err;
12076 }
12077
12078 static void __devinit tg3_read_partno(struct tg3 *tp)
12079 {
12080 unsigned char vpd_data[256]; /* in little-endian format */
12081 unsigned int i;
12082 u32 magic;
12083
12084 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12085 tg3_nvram_read(tp, 0x0, &magic))
12086 goto out_not_found;
12087
12088 if (magic == TG3_EEPROM_MAGIC) {
12089 for (i = 0; i < 256; i += 4) {
12090 u32 tmp;
12091
12092 /* The data is in little-endian format in NVRAM.
12093 * Use the big-endian read routines to preserve
12094 * the byte order as it exists in NVRAM.
12095 */
12096 if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
12097 goto out_not_found;
12098
12099 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12100 }
12101 } else {
12102 int vpd_cap;
12103
12104 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
12105 for (i = 0; i < 256; i += 4) {
12106 u32 tmp, j = 0;
12107 __le32 v;
12108 u16 tmp16;
12109
12110 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
12111 i);
12112 while (j++ < 100) {
12113 pci_read_config_word(tp->pdev, vpd_cap +
12114 PCI_VPD_ADDR, &tmp16);
12115 if (tmp16 & 0x8000)
12116 break;
12117 msleep(1);
12118 }
12119 if (!(tmp16 & 0x8000))
12120 goto out_not_found;
12121
12122 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
12123 &tmp);
12124 v = cpu_to_le32(tmp);
12125 memcpy(&vpd_data[i], &v, sizeof(v));
12126 }
12127 }
12128
12129 /* Now parse and find the part number. */
12130 for (i = 0; i < 254; ) {
12131 unsigned char val = vpd_data[i];
12132 unsigned int block_end;
12133
12134 if (val == 0x82 || val == 0x91) {
12135 i = (i + 3 +
12136 (vpd_data[i + 1] +
12137 (vpd_data[i + 2] << 8)));
12138 continue;
12139 }
12140
12141 if (val != 0x90)
12142 goto out_not_found;
12143
12144 block_end = (i + 3 +
12145 (vpd_data[i + 1] +
12146 (vpd_data[i + 2] << 8)));
12147 i += 3;
12148
12149 if (block_end > 256)
12150 goto out_not_found;
12151
12152 while (i < (block_end - 2)) {
12153 if (vpd_data[i + 0] == 'P' &&
12154 vpd_data[i + 1] == 'N') {
12155 int partno_len = vpd_data[i + 2];
12156
12157 i += 3;
12158 if (partno_len > 24 || (partno_len + i) > 256)
12159 goto out_not_found;
12160
12161 memcpy(tp->board_part_number,
12162 &vpd_data[i], partno_len);
12163
12164 /* Success. */
12165 return;
12166 }
12167 i += 3 + vpd_data[i + 2];
12168 }
12169
12170 /* Part number not found. */
12171 goto out_not_found;
12172 }
12173
12174 out_not_found:
12175 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12176 strcpy(tp->board_part_number, "BCM95906");
12177 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12178 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12179 strcpy(tp->board_part_number, "BCM57780");
12180 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12181 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12182 strcpy(tp->board_part_number, "BCM57760");
12183 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12184 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12185 strcpy(tp->board_part_number, "BCM57790");
12186 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12187 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12188 strcpy(tp->board_part_number, "BCM57788");
12189 else
12190 strcpy(tp->board_part_number, "none");
12191 }
12192
12193 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12194 {
12195 u32 val;
12196
12197 if (tg3_nvram_read(tp, offset, &val) ||
12198 (val & 0xfc000000) != 0x0c000000 ||
12199 tg3_nvram_read(tp, offset + 4, &val) ||
12200 val != 0)
12201 return 0;
12202
12203 return 1;
12204 }
12205
12206 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12207 {
12208 u32 val, offset, start, ver_offset;
12209 int i;
12210 bool newver = false;
12211
12212 if (tg3_nvram_read(tp, 0xc, &offset) ||
12213 tg3_nvram_read(tp, 0x4, &start))
12214 return;
12215
12216 offset = tg3_nvram_logical_addr(tp, offset);
12217
12218 if (tg3_nvram_read(tp, offset, &val))
12219 return;
12220
12221 if ((val & 0xfc000000) == 0x0c000000) {
12222 if (tg3_nvram_read(tp, offset + 4, &val))
12223 return;
12224
12225 if (val == 0)
12226 newver = true;
12227 }
12228
12229 if (newver) {
12230 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12231 return;
12232
12233 offset = offset + ver_offset - start;
12234 for (i = 0; i < 16; i += 4) {
12235 __be32 v;
12236 if (tg3_nvram_read_be32(tp, offset + i, &v))
12237 return;
12238
12239 memcpy(tp->fw_ver + i, &v, sizeof(v));
12240 }
12241 } else {
12242 u32 major, minor;
12243
12244 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12245 return;
12246
12247 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12248 TG3_NVM_BCVER_MAJSFT;
12249 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12250 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
12251 }
12252 }
12253
12254 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12255 {
12256 u32 val, major, minor;
12257
12258 /* Use native endian representation */
12259 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12260 return;
12261
12262 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12263 TG3_NVM_HWSB_CFG1_MAJSFT;
12264 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12265 TG3_NVM_HWSB_CFG1_MINSFT;
12266
12267 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12268 }
12269
12270 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12271 {
12272 u32 offset, major, minor, build;
12273
12274 tp->fw_ver[0] = 's';
12275 tp->fw_ver[1] = 'b';
12276 tp->fw_ver[2] = '\0';
12277
12278 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12279 return;
12280
12281 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12282 case TG3_EEPROM_SB_REVISION_0:
12283 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12284 break;
12285 case TG3_EEPROM_SB_REVISION_2:
12286 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12287 break;
12288 case TG3_EEPROM_SB_REVISION_3:
12289 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12290 break;
12291 default:
12292 return;
12293 }
12294
12295 if (tg3_nvram_read(tp, offset, &val))
12296 return;
12297
12298 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12299 TG3_EEPROM_SB_EDH_BLD_SHFT;
12300 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12301 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12302 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12303
12304 if (minor > 99 || build > 26)
12305 return;
12306
12307 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12308
12309 if (build > 0) {
12310 tp->fw_ver[8] = 'a' + build - 1;
12311 tp->fw_ver[9] = '\0';
12312 }
12313 }
12314
12315 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12316 {
12317 u32 val, offset, start;
12318 int i, vlen;
12319
12320 for (offset = TG3_NVM_DIR_START;
12321 offset < TG3_NVM_DIR_END;
12322 offset += TG3_NVM_DIRENT_SIZE) {
12323 if (tg3_nvram_read(tp, offset, &val))
12324 return;
12325
12326 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12327 break;
12328 }
12329
12330 if (offset == TG3_NVM_DIR_END)
12331 return;
12332
12333 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12334 start = 0x08000000;
12335 else if (tg3_nvram_read(tp, offset - 4, &start))
12336 return;
12337
12338 if (tg3_nvram_read(tp, offset + 4, &offset) ||
12339 !tg3_fw_img_is_valid(tp, offset) ||
12340 tg3_nvram_read(tp, offset + 8, &val))
12341 return;
12342
12343 offset += val - start;
12344
12345 vlen = strlen(tp->fw_ver);
12346
12347 tp->fw_ver[vlen++] = ',';
12348 tp->fw_ver[vlen++] = ' ';
12349
12350 for (i = 0; i < 4; i++) {
12351 __be32 v;
12352 if (tg3_nvram_read_be32(tp, offset, &v))
12353 return;
12354
12355 offset += sizeof(v);
12356
12357 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12358 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12359 break;
12360 }
12361
12362 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12363 vlen += sizeof(v);
12364 }
12365 }
12366
12367 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12368 {
12369 int vlen;
12370 u32 apedata;
12371
12372 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12373 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
12374 return;
12375
12376 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12377 if (apedata != APE_SEG_SIG_MAGIC)
12378 return;
12379
12380 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12381 if (!(apedata & APE_FW_STATUS_READY))
12382 return;
12383
12384 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12385
12386 vlen = strlen(tp->fw_ver);
12387
12388 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12389 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12390 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12391 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12392 (apedata & APE_FW_VERSION_BLDMSK));
12393 }
12394
12395 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12396 {
12397 u32 val;
12398
12399 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12400 tp->fw_ver[0] = 's';
12401 tp->fw_ver[1] = 'b';
12402 tp->fw_ver[2] = '\0';
12403
12404 return;
12405 }
12406
12407 if (tg3_nvram_read(tp, 0, &val))
12408 return;
12409
12410 if (val == TG3_EEPROM_MAGIC)
12411 tg3_read_bc_ver(tp);
12412 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12413 tg3_read_sb_ver(tp, val);
12414 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12415 tg3_read_hwsb_ver(tp);
12416 else
12417 return;
12418
12419 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12420 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12421 return;
12422
12423 tg3_read_mgmtfw_ver(tp);
12424
12425 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12426 }
12427
12428 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12429
12430 static int __devinit tg3_get_invariants(struct tg3 *tp)
12431 {
12432 static struct pci_device_id write_reorder_chipsets[] = {
12433 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12434 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12435 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12436 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12437 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12438 PCI_DEVICE_ID_VIA_8385_0) },
12439 { },
12440 };
12441 u32 misc_ctrl_reg;
12442 u32 pci_state_reg, grc_misc_cfg;
12443 u32 val;
12444 u16 pci_cmd;
12445 int err;
12446
12447 /* Force memory write invalidate off. If we leave it on,
12448 * then on 5700_BX chips we have to enable a workaround.
12449 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12450 * to match the cacheline size. The Broadcom driver have this
12451 * workaround but turns MWI off all the times so never uses
12452 * it. This seems to suggest that the workaround is insufficient.
12453 */
12454 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12455 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12456 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12457
12458 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12459 * has the register indirect write enable bit set before
12460 * we try to access any of the MMIO registers. It is also
12461 * critical that the PCI-X hw workaround situation is decided
12462 * before that as well.
12463 */
12464 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12465 &misc_ctrl_reg);
12466
12467 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12468 MISC_HOST_CTRL_CHIPREV_SHIFT);
12469 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12470 u32 prod_id_asic_rev;
12471
12472 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717C ||
12473 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717S ||
12474 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718C ||
12475 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718S)
12476 pci_read_config_dword(tp->pdev,
12477 TG3PCI_GEN2_PRODID_ASICREV,
12478 &prod_id_asic_rev);
12479 else
12480 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12481 &prod_id_asic_rev);
12482
12483 tp->pci_chip_rev_id = prod_id_asic_rev;
12484 }
12485
12486 /* Wrong chip ID in 5752 A0. This code can be removed later
12487 * as A0 is not in production.
12488 */
12489 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12490 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12491
12492 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12493 * we need to disable memory and use config. cycles
12494 * only to access all registers. The 5702/03 chips
12495 * can mistakenly decode the special cycles from the
12496 * ICH chipsets as memory write cycles, causing corruption
12497 * of register and memory space. Only certain ICH bridges
12498 * will drive special cycles with non-zero data during the
12499 * address phase which can fall within the 5703's address
12500 * range. This is not an ICH bug as the PCI spec allows
12501 * non-zero address during special cycles. However, only
12502 * these ICH bridges are known to drive non-zero addresses
12503 * during special cycles.
12504 *
12505 * Since special cycles do not cross PCI bridges, we only
12506 * enable this workaround if the 5703 is on the secondary
12507 * bus of these ICH bridges.
12508 */
12509 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12510 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12511 static struct tg3_dev_id {
12512 u32 vendor;
12513 u32 device;
12514 u32 rev;
12515 } ich_chipsets[] = {
12516 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12517 PCI_ANY_ID },
12518 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12519 PCI_ANY_ID },
12520 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12521 0xa },
12522 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12523 PCI_ANY_ID },
12524 { },
12525 };
12526 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12527 struct pci_dev *bridge = NULL;
12528
12529 while (pci_id->vendor != 0) {
12530 bridge = pci_get_device(pci_id->vendor, pci_id->device,
12531 bridge);
12532 if (!bridge) {
12533 pci_id++;
12534 continue;
12535 }
12536 if (pci_id->rev != PCI_ANY_ID) {
12537 if (bridge->revision > pci_id->rev)
12538 continue;
12539 }
12540 if (bridge->subordinate &&
12541 (bridge->subordinate->number ==
12542 tp->pdev->bus->number)) {
12543
12544 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12545 pci_dev_put(bridge);
12546 break;
12547 }
12548 }
12549 }
12550
12551 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12552 static struct tg3_dev_id {
12553 u32 vendor;
12554 u32 device;
12555 } bridge_chipsets[] = {
12556 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12557 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12558 { },
12559 };
12560 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12561 struct pci_dev *bridge = NULL;
12562
12563 while (pci_id->vendor != 0) {
12564 bridge = pci_get_device(pci_id->vendor,
12565 pci_id->device,
12566 bridge);
12567 if (!bridge) {
12568 pci_id++;
12569 continue;
12570 }
12571 if (bridge->subordinate &&
12572 (bridge->subordinate->number <=
12573 tp->pdev->bus->number) &&
12574 (bridge->subordinate->subordinate >=
12575 tp->pdev->bus->number)) {
12576 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12577 pci_dev_put(bridge);
12578 break;
12579 }
12580 }
12581 }
12582
12583 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12584 * DMA addresses > 40-bit. This bridge may have other additional
12585 * 57xx devices behind it in some 4-port NIC designs for example.
12586 * Any tg3 device found behind the bridge will also need the 40-bit
12587 * DMA workaround.
12588 */
12589 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12590 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12591 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12592 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12593 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12594 }
12595 else {
12596 struct pci_dev *bridge = NULL;
12597
12598 do {
12599 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12600 PCI_DEVICE_ID_SERVERWORKS_EPB,
12601 bridge);
12602 if (bridge && bridge->subordinate &&
12603 (bridge->subordinate->number <=
12604 tp->pdev->bus->number) &&
12605 (bridge->subordinate->subordinate >=
12606 tp->pdev->bus->number)) {
12607 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12608 pci_dev_put(bridge);
12609 break;
12610 }
12611 } while (bridge);
12612 }
12613
12614 /* Initialize misc host control in PCI block. */
12615 tp->misc_host_ctrl |= (misc_ctrl_reg &
12616 MISC_HOST_CTRL_CHIPREV);
12617 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12618 tp->misc_host_ctrl);
12619
12620 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12621 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12622 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12623 tp->pdev_peer = tg3_find_peer(tp);
12624
12625 /* Intentionally exclude ASIC_REV_5906 */
12626 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12627 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12628 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12629 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12630 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12631 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12632 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12633 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12634
12635 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12636 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12637 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
12638 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12639 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12640 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12641
12642 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12643 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12644 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12645
12646 /* 5700 B0 chips do not support checksumming correctly due
12647 * to hardware bugs.
12648 */
12649 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12650 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12651 else {
12652 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12653 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12654 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12655 tp->dev->features |= NETIF_F_IPV6_CSUM;
12656 }
12657
12658 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12659 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12660 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12661 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12662 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12663 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12664 tp->pdev_peer == tp->pdev))
12665 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12666
12667 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12668 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12669 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12670 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
12671 } else {
12672 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12673 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12674 ASIC_REV_5750 &&
12675 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12676 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12677 }
12678 }
12679
12680 tp->irq_max = 1;
12681
12682 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12683 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
12684 tp->irq_max = TG3_IRQ_MAX_VECS;
12685 }
12686
12687 if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
12688 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12689 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
12690 else {
12691 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
12692 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
12693 }
12694 }
12695
12696 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12697 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12698 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12699 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
12700
12701 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12702 &pci_state_reg);
12703
12704 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12705 if (tp->pcie_cap != 0) {
12706 u16 lnkctl;
12707
12708 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12709
12710 pcie_set_readrq(tp->pdev, 4096);
12711
12712 pci_read_config_word(tp->pdev,
12713 tp->pcie_cap + PCI_EXP_LNKCTL,
12714 &lnkctl);
12715 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12716 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12717 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
12718 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12719 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12720 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12721 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
12722 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
12723 }
12724 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
12725 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12726 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12727 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12728 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12729 if (!tp->pcix_cap) {
12730 printk(KERN_ERR PFX "Cannot find PCI-X "
12731 "capability, aborting.\n");
12732 return -EIO;
12733 }
12734
12735 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12736 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12737 }
12738
12739 /* If we have an AMD 762 or VIA K8T800 chipset, write
12740 * reordering to the mailbox registers done by the host
12741 * controller can cause major troubles. We read back from
12742 * every mailbox register write to force the writes to be
12743 * posted to the chip in order.
12744 */
12745 if (pci_dev_present(write_reorder_chipsets) &&
12746 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12747 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12748
12749 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12750 &tp->pci_cacheline_sz);
12751 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12752 &tp->pci_lat_timer);
12753 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12754 tp->pci_lat_timer < 64) {
12755 tp->pci_lat_timer = 64;
12756 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12757 tp->pci_lat_timer);
12758 }
12759
12760 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12761 /* 5700 BX chips need to have their TX producer index
12762 * mailboxes written twice to workaround a bug.
12763 */
12764 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
12765
12766 /* If we are in PCI-X mode, enable register write workaround.
12767 *
12768 * The workaround is to use indirect register accesses
12769 * for all chip writes not to mailbox registers.
12770 */
12771 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12772 u32 pm_reg;
12773
12774 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12775
12776 /* The chip can have it's power management PCI config
12777 * space registers clobbered due to this bug.
12778 * So explicitly force the chip into D0 here.
12779 */
12780 pci_read_config_dword(tp->pdev,
12781 tp->pm_cap + PCI_PM_CTRL,
12782 &pm_reg);
12783 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12784 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
12785 pci_write_config_dword(tp->pdev,
12786 tp->pm_cap + PCI_PM_CTRL,
12787 pm_reg);
12788
12789 /* Also, force SERR#/PERR# in PCI command. */
12790 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12791 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12792 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12793 }
12794 }
12795
12796 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12797 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12798 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12799 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12800
12801 /* Chip-specific fixup from Broadcom driver */
12802 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12803 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12804 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12805 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12806 }
12807
12808 /* Default fast path register access methods */
12809 tp->read32 = tg3_read32;
12810 tp->write32 = tg3_write32;
12811 tp->read32_mbox = tg3_read32;
12812 tp->write32_mbox = tg3_write32;
12813 tp->write32_tx_mbox = tg3_write32;
12814 tp->write32_rx_mbox = tg3_write32;
12815
12816 /* Various workaround register access methods */
12817 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12818 tp->write32 = tg3_write_indirect_reg32;
12819 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12820 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12821 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12822 /*
12823 * Back to back register writes can cause problems on these
12824 * chips, the workaround is to read back all reg writes
12825 * except those to mailbox regs.
12826 *
12827 * See tg3_write_indirect_reg32().
12828 */
12829 tp->write32 = tg3_write_flush_reg32;
12830 }
12831
12832 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12833 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12834 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12835 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12836 tp->write32_rx_mbox = tg3_write_flush_reg32;
12837 }
12838
12839 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12840 tp->read32 = tg3_read_indirect_reg32;
12841 tp->write32 = tg3_write_indirect_reg32;
12842 tp->read32_mbox = tg3_read_indirect_mbox;
12843 tp->write32_mbox = tg3_write_indirect_mbox;
12844 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12845 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12846
12847 iounmap(tp->regs);
12848 tp->regs = NULL;
12849
12850 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12851 pci_cmd &= ~PCI_COMMAND_MEMORY;
12852 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12853 }
12854 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12855 tp->read32_mbox = tg3_read32_mbox_5906;
12856 tp->write32_mbox = tg3_write32_mbox_5906;
12857 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12858 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12859 }
12860
12861 if (tp->write32 == tg3_write_indirect_reg32 ||
12862 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12863 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12864 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
12865 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12866
12867 /* Get eeprom hw config before calling tg3_set_power_state().
12868 * In particular, the TG3_FLG2_IS_NIC flag must be
12869 * determined before calling tg3_set_power_state() so that
12870 * we know whether or not to switch out of Vaux power.
12871 * When the flag is set, it means that GPIO1 is used for eeprom
12872 * write protect and also implies that it is a LOM where GPIOs
12873 * are not used to switch power.
12874 */
12875 tg3_get_eeprom_hw_cfg(tp);
12876
12877 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12878 /* Allow reads and writes to the
12879 * APE register and memory space.
12880 */
12881 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12882 PCISTATE_ALLOW_APE_SHMEM_WR;
12883 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12884 pci_state_reg);
12885 }
12886
12887 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12888 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12889 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12890 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12891 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12892 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12893
12894 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12895 * GPIO1 driven high will bring 5700's external PHY out of reset.
12896 * It is also used as eeprom write protect on LOMs.
12897 */
12898 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12899 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12900 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12901 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12902 GRC_LCLCTRL_GPIO_OUTPUT1);
12903 /* Unused GPIO3 must be driven as output on 5752 because there
12904 * are no pull-up resistors on unused GPIO pins.
12905 */
12906 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12907 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
12908
12909 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12910 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12911 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12912
12913 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12914 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
12915 /* Turn off the debug UART. */
12916 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12917 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12918 /* Keep VMain power. */
12919 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12920 GRC_LCLCTRL_GPIO_OUTPUT0;
12921 }
12922
12923 /* Force the chip into D0. */
12924 err = tg3_set_power_state(tp, PCI_D0);
12925 if (err) {
12926 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12927 pci_name(tp->pdev));
12928 return err;
12929 }
12930
12931 /* Derive initial jumbo mode from MTU assigned in
12932 * ether_setup() via the alloc_etherdev() call
12933 */
12934 if (tp->dev->mtu > ETH_DATA_LEN &&
12935 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12936 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
12937
12938 /* Determine WakeOnLan speed to use. */
12939 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12940 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12941 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12942 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12943 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12944 } else {
12945 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12946 }
12947
12948 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12949 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
12950
12951 /* A few boards don't want Ethernet@WireSpeed phy feature */
12952 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12953 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12954 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
12955 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
12956 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
12957 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
12958 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12959
12960 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12961 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12962 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12963 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12964 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12965
12966 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
12967 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
12968 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12969 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
12970 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
12971 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12972 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12973 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12974 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
12975 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12976 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12977 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
12978 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12979 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
12980 } else
12981 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12982 }
12983
12984 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12985 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12986 tp->phy_otp = tg3_read_otp_phycfg(tp);
12987 if (tp->phy_otp == 0)
12988 tp->phy_otp = TG3_OTP_DEFAULT;
12989 }
12990
12991 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
12992 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12993 else
12994 tp->mi_mode = MAC_MI_MODE_BASE;
12995
12996 tp->coalesce_mode = 0;
12997 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12998 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12999 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13000
13001 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13002 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13003 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13004
13005 err = tg3_mdio_init(tp);
13006 if (err)
13007 return err;
13008
13009 /* Initialize data/descriptor byte/word swapping. */
13010 val = tr32(GRC_MODE);
13011 val &= GRC_MODE_HOST_STACKUP;
13012 tw32(GRC_MODE, val | tp->grc_mode);
13013
13014 tg3_switch_clocks(tp);
13015
13016 /* Clear this out for sanity. */
13017 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13018
13019 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13020 &pci_state_reg);
13021 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13022 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13023 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13024
13025 if (chiprevid == CHIPREV_ID_5701_A0 ||
13026 chiprevid == CHIPREV_ID_5701_B0 ||
13027 chiprevid == CHIPREV_ID_5701_B2 ||
13028 chiprevid == CHIPREV_ID_5701_B5) {
13029 void __iomem *sram_base;
13030
13031 /* Write some dummy words into the SRAM status block
13032 * area, see if it reads back correctly. If the return
13033 * value is bad, force enable the PCIX workaround.
13034 */
13035 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13036
13037 writel(0x00000000, sram_base);
13038 writel(0x00000000, sram_base + 4);
13039 writel(0xffffffff, sram_base + 4);
13040 if (readl(sram_base) != 0x00000000)
13041 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13042 }
13043 }
13044
13045 udelay(50);
13046 tg3_nvram_init(tp);
13047
13048 grc_misc_cfg = tr32(GRC_MISC_CFG);
13049 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13050
13051 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13052 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13053 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13054 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13055
13056 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13057 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13058 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13059 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13060 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13061 HOSTCC_MODE_CLRTICK_TXBD);
13062
13063 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13064 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13065 tp->misc_host_ctrl);
13066 }
13067
13068 /* Preserve the APE MAC_MODE bits */
13069 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13070 tp->mac_mode = tr32(MAC_MODE) |
13071 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13072 else
13073 tp->mac_mode = TG3_DEF_MAC_MODE;
13074
13075 /* these are limited to 10/100 only */
13076 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13077 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13078 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13079 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13080 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13081 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13082 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13083 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13084 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13085 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13086 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13087 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13088 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
13089 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13090
13091 err = tg3_phy_probe(tp);
13092 if (err) {
13093 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13094 pci_name(tp->pdev), err);
13095 /* ... but do not return immediately ... */
13096 tg3_mdio_fini(tp);
13097 }
13098
13099 tg3_read_partno(tp);
13100 tg3_read_fw_ver(tp);
13101
13102 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13103 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13104 } else {
13105 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13106 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13107 else
13108 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13109 }
13110
13111 /* 5700 {AX,BX} chips have a broken status block link
13112 * change bit implementation, so we must use the
13113 * status register in those cases.
13114 */
13115 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13116 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13117 else
13118 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13119
13120 /* The led_ctrl is set during tg3_phy_probe, here we might
13121 * have to force the link status polling mechanism based
13122 * upon subsystem IDs.
13123 */
13124 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13125 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13126 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13127 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13128 TG3_FLAG_USE_LINKCHG_REG);
13129 }
13130
13131 /* For all SERDES we poll the MAC status register. */
13132 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13133 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13134 else
13135 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13136
13137 tp->rx_offset = NET_IP_ALIGN;
13138 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13139 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13140 tp->rx_offset = 0;
13141
13142 tp->rx_std_max_post = TG3_RX_RING_SIZE;
13143
13144 /* Increment the rx prod index on the rx std ring by at most
13145 * 8 for these chips to workaround hw errata.
13146 */
13147 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13148 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13149 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13150 tp->rx_std_max_post = 8;
13151
13152 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13153 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13154 PCIE_PWR_MGMT_L1_THRESH_MSK;
13155
13156 return err;
13157 }
13158
13159 #ifdef CONFIG_SPARC
13160 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13161 {
13162 struct net_device *dev = tp->dev;
13163 struct pci_dev *pdev = tp->pdev;
13164 struct device_node *dp = pci_device_to_OF_node(pdev);
13165 const unsigned char *addr;
13166 int len;
13167
13168 addr = of_get_property(dp, "local-mac-address", &len);
13169 if (addr && len == 6) {
13170 memcpy(dev->dev_addr, addr, 6);
13171 memcpy(dev->perm_addr, dev->dev_addr, 6);
13172 return 0;
13173 }
13174 return -ENODEV;
13175 }
13176
13177 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13178 {
13179 struct net_device *dev = tp->dev;
13180
13181 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13182 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13183 return 0;
13184 }
13185 #endif
13186
13187 static int __devinit tg3_get_device_address(struct tg3 *tp)
13188 {
13189 struct net_device *dev = tp->dev;
13190 u32 hi, lo, mac_offset;
13191 int addr_ok = 0;
13192
13193 #ifdef CONFIG_SPARC
13194 if (!tg3_get_macaddr_sparc(tp))
13195 return 0;
13196 #endif
13197
13198 mac_offset = 0x7c;
13199 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13200 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13201 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13202 mac_offset = 0xcc;
13203 if (tg3_nvram_lock(tp))
13204 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13205 else
13206 tg3_nvram_unlock(tp);
13207 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13208 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13209 mac_offset = 0xcc;
13210 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13211 mac_offset = 0x10;
13212
13213 /* First try to get it from MAC address mailbox. */
13214 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13215 if ((hi >> 16) == 0x484b) {
13216 dev->dev_addr[0] = (hi >> 8) & 0xff;
13217 dev->dev_addr[1] = (hi >> 0) & 0xff;
13218
13219 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13220 dev->dev_addr[2] = (lo >> 24) & 0xff;
13221 dev->dev_addr[3] = (lo >> 16) & 0xff;
13222 dev->dev_addr[4] = (lo >> 8) & 0xff;
13223 dev->dev_addr[5] = (lo >> 0) & 0xff;
13224
13225 /* Some old bootcode may report a 0 MAC address in SRAM */
13226 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13227 }
13228 if (!addr_ok) {
13229 /* Next, try NVRAM. */
13230 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13231 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13232 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13233 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13234 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13235 }
13236 /* Finally just fetch it out of the MAC control regs. */
13237 else {
13238 hi = tr32(MAC_ADDR_0_HIGH);
13239 lo = tr32(MAC_ADDR_0_LOW);
13240
13241 dev->dev_addr[5] = lo & 0xff;
13242 dev->dev_addr[4] = (lo >> 8) & 0xff;
13243 dev->dev_addr[3] = (lo >> 16) & 0xff;
13244 dev->dev_addr[2] = (lo >> 24) & 0xff;
13245 dev->dev_addr[1] = hi & 0xff;
13246 dev->dev_addr[0] = (hi >> 8) & 0xff;
13247 }
13248 }
13249
13250 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13251 #ifdef CONFIG_SPARC
13252 if (!tg3_get_default_macaddr_sparc(tp))
13253 return 0;
13254 #endif
13255 return -EINVAL;
13256 }
13257 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13258 return 0;
13259 }
13260
13261 #define BOUNDARY_SINGLE_CACHELINE 1
13262 #define BOUNDARY_MULTI_CACHELINE 2
13263
13264 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13265 {
13266 int cacheline_size;
13267 u8 byte;
13268 int goal;
13269
13270 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13271 if (byte == 0)
13272 cacheline_size = 1024;
13273 else
13274 cacheline_size = (int) byte * 4;
13275
13276 /* On 5703 and later chips, the boundary bits have no
13277 * effect.
13278 */
13279 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13280 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13281 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13282 goto out;
13283
13284 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13285 goal = BOUNDARY_MULTI_CACHELINE;
13286 #else
13287 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13288 goal = BOUNDARY_SINGLE_CACHELINE;
13289 #else
13290 goal = 0;
13291 #endif
13292 #endif
13293
13294 if (!goal)
13295 goto out;
13296
13297 /* PCI controllers on most RISC systems tend to disconnect
13298 * when a device tries to burst across a cache-line boundary.
13299 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13300 *
13301 * Unfortunately, for PCI-E there are only limited
13302 * write-side controls for this, and thus for reads
13303 * we will still get the disconnects. We'll also waste
13304 * these PCI cycles for both read and write for chips
13305 * other than 5700 and 5701 which do not implement the
13306 * boundary bits.
13307 */
13308 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13309 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13310 switch (cacheline_size) {
13311 case 16:
13312 case 32:
13313 case 64:
13314 case 128:
13315 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13316 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13317 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13318 } else {
13319 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13320 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13321 }
13322 break;
13323
13324 case 256:
13325 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13326 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13327 break;
13328
13329 default:
13330 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13331 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13332 break;
13333 }
13334 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13335 switch (cacheline_size) {
13336 case 16:
13337 case 32:
13338 case 64:
13339 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13340 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13341 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13342 break;
13343 }
13344 /* fallthrough */
13345 case 128:
13346 default:
13347 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13348 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13349 break;
13350 }
13351 } else {
13352 switch (cacheline_size) {
13353 case 16:
13354 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13355 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13356 DMA_RWCTRL_WRITE_BNDRY_16);
13357 break;
13358 }
13359 /* fallthrough */
13360 case 32:
13361 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13362 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13363 DMA_RWCTRL_WRITE_BNDRY_32);
13364 break;
13365 }
13366 /* fallthrough */
13367 case 64:
13368 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13369 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13370 DMA_RWCTRL_WRITE_BNDRY_64);
13371 break;
13372 }
13373 /* fallthrough */
13374 case 128:
13375 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13376 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13377 DMA_RWCTRL_WRITE_BNDRY_128);
13378 break;
13379 }
13380 /* fallthrough */
13381 case 256:
13382 val |= (DMA_RWCTRL_READ_BNDRY_256 |
13383 DMA_RWCTRL_WRITE_BNDRY_256);
13384 break;
13385 case 512:
13386 val |= (DMA_RWCTRL_READ_BNDRY_512 |
13387 DMA_RWCTRL_WRITE_BNDRY_512);
13388 break;
13389 case 1024:
13390 default:
13391 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13392 DMA_RWCTRL_WRITE_BNDRY_1024);
13393 break;
13394 }
13395 }
13396
13397 out:
13398 return val;
13399 }
13400
13401 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13402 {
13403 struct tg3_internal_buffer_desc test_desc;
13404 u32 sram_dma_descs;
13405 int i, ret;
13406
13407 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13408
13409 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13410 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13411 tw32(RDMAC_STATUS, 0);
13412 tw32(WDMAC_STATUS, 0);
13413
13414 tw32(BUFMGR_MODE, 0);
13415 tw32(FTQ_RESET, 0);
13416
13417 test_desc.addr_hi = ((u64) buf_dma) >> 32;
13418 test_desc.addr_lo = buf_dma & 0xffffffff;
13419 test_desc.nic_mbuf = 0x00002100;
13420 test_desc.len = size;
13421
13422 /*
13423 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13424 * the *second* time the tg3 driver was getting loaded after an
13425 * initial scan.
13426 *
13427 * Broadcom tells me:
13428 * ...the DMA engine is connected to the GRC block and a DMA
13429 * reset may affect the GRC block in some unpredictable way...
13430 * The behavior of resets to individual blocks has not been tested.
13431 *
13432 * Broadcom noted the GRC reset will also reset all sub-components.
13433 */
13434 if (to_device) {
13435 test_desc.cqid_sqid = (13 << 8) | 2;
13436
13437 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13438 udelay(40);
13439 } else {
13440 test_desc.cqid_sqid = (16 << 8) | 7;
13441
13442 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13443 udelay(40);
13444 }
13445 test_desc.flags = 0x00000005;
13446
13447 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13448 u32 val;
13449
13450 val = *(((u32 *)&test_desc) + i);
13451 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13452 sram_dma_descs + (i * sizeof(u32)));
13453 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13454 }
13455 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13456
13457 if (to_device) {
13458 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13459 } else {
13460 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13461 }
13462
13463 ret = -ENODEV;
13464 for (i = 0; i < 40; i++) {
13465 u32 val;
13466
13467 if (to_device)
13468 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13469 else
13470 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13471 if ((val & 0xffff) == sram_dma_descs) {
13472 ret = 0;
13473 break;
13474 }
13475
13476 udelay(100);
13477 }
13478
13479 return ret;
13480 }
13481
13482 #define TEST_BUFFER_SIZE 0x2000
13483
13484 static int __devinit tg3_test_dma(struct tg3 *tp)
13485 {
13486 dma_addr_t buf_dma;
13487 u32 *buf, saved_dma_rwctrl;
13488 int ret;
13489
13490 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13491 if (!buf) {
13492 ret = -ENOMEM;
13493 goto out_nofree;
13494 }
13495
13496 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13497 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13498
13499 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13500
13501 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13502 /* DMA read watermark not used on PCIE */
13503 tp->dma_rwctrl |= 0x00180000;
13504 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13505 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13506 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13507 tp->dma_rwctrl |= 0x003f0000;
13508 else
13509 tp->dma_rwctrl |= 0x003f000f;
13510 } else {
13511 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13512 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13513 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13514 u32 read_water = 0x7;
13515
13516 /* If the 5704 is behind the EPB bridge, we can
13517 * do the less restrictive ONE_DMA workaround for
13518 * better performance.
13519 */
13520 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13521 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13522 tp->dma_rwctrl |= 0x8000;
13523 else if (ccval == 0x6 || ccval == 0x7)
13524 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13525
13526 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13527 read_water = 4;
13528 /* Set bit 23 to enable PCIX hw bug fix */
13529 tp->dma_rwctrl |=
13530 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13531 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13532 (1 << 23);
13533 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13534 /* 5780 always in PCIX mode */
13535 tp->dma_rwctrl |= 0x00144000;
13536 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13537 /* 5714 always in PCIX mode */
13538 tp->dma_rwctrl |= 0x00148000;
13539 } else {
13540 tp->dma_rwctrl |= 0x001b000f;
13541 }
13542 }
13543
13544 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13545 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13546 tp->dma_rwctrl &= 0xfffffff0;
13547
13548 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13549 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13550 /* Remove this if it causes problems for some boards. */
13551 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13552
13553 /* On 5700/5701 chips, we need to set this bit.
13554 * Otherwise the chip will issue cacheline transactions
13555 * to streamable DMA memory with not all the byte
13556 * enables turned on. This is an error on several
13557 * RISC PCI controllers, in particular sparc64.
13558 *
13559 * On 5703/5704 chips, this bit has been reassigned
13560 * a different meaning. In particular, it is used
13561 * on those chips to enable a PCI-X workaround.
13562 */
13563 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13564 }
13565
13566 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13567
13568 #if 0
13569 /* Unneeded, already done by tg3_get_invariants. */
13570 tg3_switch_clocks(tp);
13571 #endif
13572
13573 ret = 0;
13574 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13575 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13576 goto out;
13577
13578 /* It is best to perform DMA test with maximum write burst size
13579 * to expose the 5700/5701 write DMA bug.
13580 */
13581 saved_dma_rwctrl = tp->dma_rwctrl;
13582 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13583 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13584
13585 while (1) {
13586 u32 *p = buf, i;
13587
13588 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13589 p[i] = i;
13590
13591 /* Send the buffer to the chip. */
13592 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13593 if (ret) {
13594 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13595 break;
13596 }
13597
13598 #if 0
13599 /* validate data reached card RAM correctly. */
13600 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13601 u32 val;
13602 tg3_read_mem(tp, 0x2100 + (i*4), &val);
13603 if (le32_to_cpu(val) != p[i]) {
13604 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
13605 /* ret = -ENODEV here? */
13606 }
13607 p[i] = 0;
13608 }
13609 #endif
13610 /* Now read it back. */
13611 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13612 if (ret) {
13613 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13614
13615 break;
13616 }
13617
13618 /* Verify it. */
13619 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13620 if (p[i] == i)
13621 continue;
13622
13623 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13624 DMA_RWCTRL_WRITE_BNDRY_16) {
13625 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13626 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13627 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13628 break;
13629 } else {
13630 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13631 ret = -ENODEV;
13632 goto out;
13633 }
13634 }
13635
13636 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13637 /* Success. */
13638 ret = 0;
13639 break;
13640 }
13641 }
13642 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13643 DMA_RWCTRL_WRITE_BNDRY_16) {
13644 static struct pci_device_id dma_wait_state_chipsets[] = {
13645 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13646 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13647 { },
13648 };
13649
13650 /* DMA test passed without adjusting DMA boundary,
13651 * now look for chipsets that are known to expose the
13652 * DMA bug without failing the test.
13653 */
13654 if (pci_dev_present(dma_wait_state_chipsets)) {
13655 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13656 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13657 }
13658 else
13659 /* Safe to use the calculated DMA boundary. */
13660 tp->dma_rwctrl = saved_dma_rwctrl;
13661
13662 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13663 }
13664
13665 out:
13666 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13667 out_nofree:
13668 return ret;
13669 }
13670
13671 static void __devinit tg3_init_link_config(struct tg3 *tp)
13672 {
13673 tp->link_config.advertising =
13674 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13675 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13676 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13677 ADVERTISED_Autoneg | ADVERTISED_MII);
13678 tp->link_config.speed = SPEED_INVALID;
13679 tp->link_config.duplex = DUPLEX_INVALID;
13680 tp->link_config.autoneg = AUTONEG_ENABLE;
13681 tp->link_config.active_speed = SPEED_INVALID;
13682 tp->link_config.active_duplex = DUPLEX_INVALID;
13683 tp->link_config.phy_is_low_power = 0;
13684 tp->link_config.orig_speed = SPEED_INVALID;
13685 tp->link_config.orig_duplex = DUPLEX_INVALID;
13686 tp->link_config.orig_autoneg = AUTONEG_INVALID;
13687 }
13688
13689 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13690 {
13691 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS &&
13692 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
13693 tp->bufmgr_config.mbuf_read_dma_low_water =
13694 DEFAULT_MB_RDMA_LOW_WATER_5705;
13695 tp->bufmgr_config.mbuf_mac_rx_low_water =
13696 DEFAULT_MB_MACRX_LOW_WATER_5705;
13697 tp->bufmgr_config.mbuf_high_water =
13698 DEFAULT_MB_HIGH_WATER_5705;
13699 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13700 tp->bufmgr_config.mbuf_mac_rx_low_water =
13701 DEFAULT_MB_MACRX_LOW_WATER_5906;
13702 tp->bufmgr_config.mbuf_high_water =
13703 DEFAULT_MB_HIGH_WATER_5906;
13704 }
13705
13706 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13707 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13708 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13709 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13710 tp->bufmgr_config.mbuf_high_water_jumbo =
13711 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13712 } else {
13713 tp->bufmgr_config.mbuf_read_dma_low_water =
13714 DEFAULT_MB_RDMA_LOW_WATER;
13715 tp->bufmgr_config.mbuf_mac_rx_low_water =
13716 DEFAULT_MB_MACRX_LOW_WATER;
13717 tp->bufmgr_config.mbuf_high_water =
13718 DEFAULT_MB_HIGH_WATER;
13719
13720 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13721 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13722 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13723 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13724 tp->bufmgr_config.mbuf_high_water_jumbo =
13725 DEFAULT_MB_HIGH_WATER_JUMBO;
13726 }
13727
13728 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13729 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13730 }
13731
13732 static char * __devinit tg3_phy_string(struct tg3 *tp)
13733 {
13734 switch (tp->phy_id & PHY_ID_MASK) {
13735 case PHY_ID_BCM5400: return "5400";
13736 case PHY_ID_BCM5401: return "5401";
13737 case PHY_ID_BCM5411: return "5411";
13738 case PHY_ID_BCM5701: return "5701";
13739 case PHY_ID_BCM5703: return "5703";
13740 case PHY_ID_BCM5704: return "5704";
13741 case PHY_ID_BCM5705: return "5705";
13742 case PHY_ID_BCM5750: return "5750";
13743 case PHY_ID_BCM5752: return "5752";
13744 case PHY_ID_BCM5714: return "5714";
13745 case PHY_ID_BCM5780: return "5780";
13746 case PHY_ID_BCM5755: return "5755";
13747 case PHY_ID_BCM5787: return "5787";
13748 case PHY_ID_BCM5784: return "5784";
13749 case PHY_ID_BCM5756: return "5722/5756";
13750 case PHY_ID_BCM5906: return "5906";
13751 case PHY_ID_BCM5761: return "5761";
13752 case PHY_ID_BCM8002: return "8002/serdes";
13753 case 0: return "serdes";
13754 default: return "unknown";
13755 }
13756 }
13757
13758 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13759 {
13760 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13761 strcpy(str, "PCI Express");
13762 return str;
13763 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13764 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13765
13766 strcpy(str, "PCIX:");
13767
13768 if ((clock_ctrl == 7) ||
13769 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13770 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13771 strcat(str, "133MHz");
13772 else if (clock_ctrl == 0)
13773 strcat(str, "33MHz");
13774 else if (clock_ctrl == 2)
13775 strcat(str, "50MHz");
13776 else if (clock_ctrl == 4)
13777 strcat(str, "66MHz");
13778 else if (clock_ctrl == 6)
13779 strcat(str, "100MHz");
13780 } else {
13781 strcpy(str, "PCI:");
13782 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13783 strcat(str, "66MHz");
13784 else
13785 strcat(str, "33MHz");
13786 }
13787 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13788 strcat(str, ":32-bit");
13789 else
13790 strcat(str, ":64-bit");
13791 return str;
13792 }
13793
13794 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
13795 {
13796 struct pci_dev *peer;
13797 unsigned int func, devnr = tp->pdev->devfn & ~7;
13798
13799 for (func = 0; func < 8; func++) {
13800 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13801 if (peer && peer != tp->pdev)
13802 break;
13803 pci_dev_put(peer);
13804 }
13805 /* 5704 can be configured in single-port mode, set peer to
13806 * tp->pdev in that case.
13807 */
13808 if (!peer) {
13809 peer = tp->pdev;
13810 return peer;
13811 }
13812
13813 /*
13814 * We don't need to keep the refcount elevated; there's no way
13815 * to remove one half of this device without removing the other
13816 */
13817 pci_dev_put(peer);
13818
13819 return peer;
13820 }
13821
13822 static void __devinit tg3_init_coal(struct tg3 *tp)
13823 {
13824 struct ethtool_coalesce *ec = &tp->coal;
13825
13826 memset(ec, 0, sizeof(*ec));
13827 ec->cmd = ETHTOOL_GCOALESCE;
13828 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13829 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13830 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13831 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13832 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13833 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13834 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13835 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13836 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13837
13838 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13839 HOSTCC_MODE_CLRTICK_TXBD)) {
13840 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13841 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13842 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13843 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13844 }
13845
13846 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13847 ec->rx_coalesce_usecs_irq = 0;
13848 ec->tx_coalesce_usecs_irq = 0;
13849 ec->stats_block_coalesce_usecs = 0;
13850 }
13851 }
13852
13853 static const struct net_device_ops tg3_netdev_ops = {
13854 .ndo_open = tg3_open,
13855 .ndo_stop = tg3_close,
13856 .ndo_start_xmit = tg3_start_xmit,
13857 .ndo_get_stats = tg3_get_stats,
13858 .ndo_validate_addr = eth_validate_addr,
13859 .ndo_set_multicast_list = tg3_set_rx_mode,
13860 .ndo_set_mac_address = tg3_set_mac_addr,
13861 .ndo_do_ioctl = tg3_ioctl,
13862 .ndo_tx_timeout = tg3_tx_timeout,
13863 .ndo_change_mtu = tg3_change_mtu,
13864 #if TG3_VLAN_TAG_USED
13865 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13866 #endif
13867 #ifdef CONFIG_NET_POLL_CONTROLLER
13868 .ndo_poll_controller = tg3_poll_controller,
13869 #endif
13870 };
13871
13872 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13873 .ndo_open = tg3_open,
13874 .ndo_stop = tg3_close,
13875 .ndo_start_xmit = tg3_start_xmit_dma_bug,
13876 .ndo_get_stats = tg3_get_stats,
13877 .ndo_validate_addr = eth_validate_addr,
13878 .ndo_set_multicast_list = tg3_set_rx_mode,
13879 .ndo_set_mac_address = tg3_set_mac_addr,
13880 .ndo_do_ioctl = tg3_ioctl,
13881 .ndo_tx_timeout = tg3_tx_timeout,
13882 .ndo_change_mtu = tg3_change_mtu,
13883 #if TG3_VLAN_TAG_USED
13884 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13885 #endif
13886 #ifdef CONFIG_NET_POLL_CONTROLLER
13887 .ndo_poll_controller = tg3_poll_controller,
13888 #endif
13889 };
13890
13891 static int __devinit tg3_init_one(struct pci_dev *pdev,
13892 const struct pci_device_id *ent)
13893 {
13894 static int tg3_version_printed = 0;
13895 struct net_device *dev;
13896 struct tg3 *tp;
13897 int i, err, pm_cap;
13898 u32 sndmbx, rcvmbx, intmbx;
13899 char str[40];
13900 u64 dma_mask, persist_dma_mask;
13901
13902 if (tg3_version_printed++ == 0)
13903 printk(KERN_INFO "%s", version);
13904
13905 err = pci_enable_device(pdev);
13906 if (err) {
13907 printk(KERN_ERR PFX "Cannot enable PCI device, "
13908 "aborting.\n");
13909 return err;
13910 }
13911
13912 err = pci_request_regions(pdev, DRV_MODULE_NAME);
13913 if (err) {
13914 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13915 "aborting.\n");
13916 goto err_out_disable_pdev;
13917 }
13918
13919 pci_set_master(pdev);
13920
13921 /* Find power-management capability. */
13922 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13923 if (pm_cap == 0) {
13924 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13925 "aborting.\n");
13926 err = -EIO;
13927 goto err_out_free_res;
13928 }
13929
13930 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
13931 if (!dev) {
13932 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13933 err = -ENOMEM;
13934 goto err_out_free_res;
13935 }
13936
13937 SET_NETDEV_DEV(dev, &pdev->dev);
13938
13939 #if TG3_VLAN_TAG_USED
13940 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
13941 #endif
13942
13943 tp = netdev_priv(dev);
13944 tp->pdev = pdev;
13945 tp->dev = dev;
13946 tp->pm_cap = pm_cap;
13947 tp->rx_mode = TG3_DEF_RX_MODE;
13948 tp->tx_mode = TG3_DEF_TX_MODE;
13949
13950 if (tg3_debug > 0)
13951 tp->msg_enable = tg3_debug;
13952 else
13953 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13954
13955 /* The word/byte swap controls here control register access byte
13956 * swapping. DMA data byte swapping is controlled in the GRC_MODE
13957 * setting below.
13958 */
13959 tp->misc_host_ctrl =
13960 MISC_HOST_CTRL_MASK_PCI_INT |
13961 MISC_HOST_CTRL_WORD_SWAP |
13962 MISC_HOST_CTRL_INDIR_ACCESS |
13963 MISC_HOST_CTRL_PCISTATE_RW;
13964
13965 /* The NONFRM (non-frame) byte/word swap controls take effect
13966 * on descriptor entries, anything which isn't packet data.
13967 *
13968 * The StrongARM chips on the board (one for tx, one for rx)
13969 * are running in big-endian mode.
13970 */
13971 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13972 GRC_MODE_WSWAP_NONFRM_DATA);
13973 #ifdef __BIG_ENDIAN
13974 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13975 #endif
13976 spin_lock_init(&tp->lock);
13977 spin_lock_init(&tp->indirect_lock);
13978 INIT_WORK(&tp->reset_task, tg3_reset_task);
13979
13980 tp->regs = pci_ioremap_bar(pdev, BAR_0);
13981 if (!tp->regs) {
13982 printk(KERN_ERR PFX "Cannot map device registers, "
13983 "aborting.\n");
13984 err = -ENOMEM;
13985 goto err_out_free_dev;
13986 }
13987
13988 tg3_init_link_config(tp);
13989
13990 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13991 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13992
13993 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
13994 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
13995 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
13996 for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
13997 struct tg3_napi *tnapi = &tp->napi[i];
13998
13999 tnapi->tp = tp;
14000 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14001
14002 tnapi->int_mbox = intmbx;
14003 if (i < 4)
14004 intmbx += 0x8;
14005 else
14006 intmbx += 0x4;
14007
14008 tnapi->consmbox = rcvmbx;
14009 tnapi->prodmbox = sndmbx;
14010
14011 if (i)
14012 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14013 else
14014 tnapi->coal_now = HOSTCC_MODE_NOW;
14015
14016 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14017 break;
14018
14019 /*
14020 * If we support MSIX, we'll be using RSS. If we're using
14021 * RSS, the first vector only handles link interrupts and the
14022 * remaining vectors handle rx and tx interrupts. Reuse the
14023 * mailbox values for the next iteration. The values we setup
14024 * above are still useful for the single vectored mode.
14025 */
14026 if (!i)
14027 continue;
14028
14029 rcvmbx += 0x8;
14030
14031 if (sndmbx & 0x4)
14032 sndmbx -= 0x4;
14033 else
14034 sndmbx += 0xc;
14035 }
14036
14037 netif_napi_add(dev, &tp->napi[0].napi, tg3_poll, 64);
14038 dev->ethtool_ops = &tg3_ethtool_ops;
14039 dev->watchdog_timeo = TG3_TX_TIMEOUT;
14040 dev->irq = pdev->irq;
14041
14042 err = tg3_get_invariants(tp);
14043 if (err) {
14044 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14045 "aborting.\n");
14046 goto err_out_iounmap;
14047 }
14048
14049 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
14050 dev->netdev_ops = &tg3_netdev_ops;
14051 else
14052 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14053
14054
14055 /* The EPB bridge inside 5714, 5715, and 5780 and any
14056 * device behind the EPB cannot support DMA addresses > 40-bit.
14057 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14058 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14059 * do DMA address check in tg3_start_xmit().
14060 */
14061 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14062 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14063 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14064 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14065 #ifdef CONFIG_HIGHMEM
14066 dma_mask = DMA_BIT_MASK(64);
14067 #endif
14068 } else
14069 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14070
14071 /* Configure DMA attributes. */
14072 if (dma_mask > DMA_BIT_MASK(32)) {
14073 err = pci_set_dma_mask(pdev, dma_mask);
14074 if (!err) {
14075 dev->features |= NETIF_F_HIGHDMA;
14076 err = pci_set_consistent_dma_mask(pdev,
14077 persist_dma_mask);
14078 if (err < 0) {
14079 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14080 "DMA for consistent allocations\n");
14081 goto err_out_iounmap;
14082 }
14083 }
14084 }
14085 if (err || dma_mask == DMA_BIT_MASK(32)) {
14086 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14087 if (err) {
14088 printk(KERN_ERR PFX "No usable DMA configuration, "
14089 "aborting.\n");
14090 goto err_out_iounmap;
14091 }
14092 }
14093
14094 tg3_init_bufmgr_config(tp);
14095
14096 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14097 tp->fw_needed = FIRMWARE_TG3;
14098
14099 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
14100 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14101 }
14102 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14103 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
14104 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
14105 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
14106 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
14107 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
14108 } else {
14109 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
14110 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
14111 tp->fw_needed = FIRMWARE_TG3TSO5;
14112 else
14113 tp->fw_needed = FIRMWARE_TG3TSO;
14114 }
14115
14116 /* TSO is on by default on chips that support hardware TSO.
14117 * Firmware TSO on older chips gives lower performance, so it
14118 * is off by default, but can be enabled using ethtool.
14119 */
14120 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
14121 if (dev->features & NETIF_F_IP_CSUM)
14122 dev->features |= NETIF_F_TSO;
14123 if ((dev->features & NETIF_F_IPV6_CSUM) &&
14124 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
14125 dev->features |= NETIF_F_TSO6;
14126 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14127 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14128 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14129 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14130 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14131 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
14132 dev->features |= NETIF_F_TSO_ECN;
14133 }
14134
14135
14136 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14137 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14138 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14139 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14140 tp->rx_pending = 63;
14141 }
14142
14143 err = tg3_get_device_address(tp);
14144 if (err) {
14145 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14146 "aborting.\n");
14147 goto err_out_fw;
14148 }
14149
14150 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14151 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14152 if (!tp->aperegs) {
14153 printk(KERN_ERR PFX "Cannot map APE registers, "
14154 "aborting.\n");
14155 err = -ENOMEM;
14156 goto err_out_fw;
14157 }
14158
14159 tg3_ape_lock_init(tp);
14160
14161 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14162 tg3_read_dash_ver(tp);
14163 }
14164
14165 /*
14166 * Reset chip in case UNDI or EFI driver did not shutdown
14167 * DMA self test will enable WDMAC and we'll see (spurious)
14168 * pending DMA on the PCI bus at that point.
14169 */
14170 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14171 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14172 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14173 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14174 }
14175
14176 err = tg3_test_dma(tp);
14177 if (err) {
14178 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
14179 goto err_out_apeunmap;
14180 }
14181
14182 /* flow control autonegotiation is default behavior */
14183 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14184 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14185
14186 tg3_init_coal(tp);
14187
14188 pci_set_drvdata(pdev, dev);
14189
14190 err = register_netdev(dev);
14191 if (err) {
14192 printk(KERN_ERR PFX "Cannot register net device, "
14193 "aborting.\n");
14194 goto err_out_apeunmap;
14195 }
14196
14197 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14198 dev->name,
14199 tp->board_part_number,
14200 tp->pci_chip_rev_id,
14201 tg3_bus_string(tp, str),
14202 dev->dev_addr);
14203
14204 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14205 struct phy_device *phydev;
14206 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14207 printk(KERN_INFO
14208 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14209 tp->dev->name, phydev->drv->name,
14210 dev_name(&phydev->dev));
14211 } else
14212 printk(KERN_INFO
14213 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14214 tp->dev->name, tg3_phy_string(tp),
14215 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14216 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14217 "10/100/1000Base-T")),
14218 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14219
14220 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14221 dev->name,
14222 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14223 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14224 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14225 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14226 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14227 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14228 dev->name, tp->dma_rwctrl,
14229 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
14230 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
14231
14232 return 0;
14233
14234 err_out_apeunmap:
14235 if (tp->aperegs) {
14236 iounmap(tp->aperegs);
14237 tp->aperegs = NULL;
14238 }
14239
14240 err_out_fw:
14241 if (tp->fw)
14242 release_firmware(tp->fw);
14243
14244 err_out_iounmap:
14245 if (tp->regs) {
14246 iounmap(tp->regs);
14247 tp->regs = NULL;
14248 }
14249
14250 err_out_free_dev:
14251 free_netdev(dev);
14252
14253 err_out_free_res:
14254 pci_release_regions(pdev);
14255
14256 err_out_disable_pdev:
14257 pci_disable_device(pdev);
14258 pci_set_drvdata(pdev, NULL);
14259 return err;
14260 }
14261
14262 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14263 {
14264 struct net_device *dev = pci_get_drvdata(pdev);
14265
14266 if (dev) {
14267 struct tg3 *tp = netdev_priv(dev);
14268
14269 if (tp->fw)
14270 release_firmware(tp->fw);
14271
14272 flush_scheduled_work();
14273
14274 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14275 tg3_phy_fini(tp);
14276 tg3_mdio_fini(tp);
14277 }
14278
14279 unregister_netdev(dev);
14280 if (tp->aperegs) {
14281 iounmap(tp->aperegs);
14282 tp->aperegs = NULL;
14283 }
14284 if (tp->regs) {
14285 iounmap(tp->regs);
14286 tp->regs = NULL;
14287 }
14288 free_netdev(dev);
14289 pci_release_regions(pdev);
14290 pci_disable_device(pdev);
14291 pci_set_drvdata(pdev, NULL);
14292 }
14293 }
14294
14295 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14296 {
14297 struct net_device *dev = pci_get_drvdata(pdev);
14298 struct tg3 *tp = netdev_priv(dev);
14299 pci_power_t target_state;
14300 int err;
14301
14302 /* PCI register 4 needs to be saved whether netif_running() or not.
14303 * MSI address and data need to be saved if using MSI and
14304 * netif_running().
14305 */
14306 pci_save_state(pdev);
14307
14308 if (!netif_running(dev))
14309 return 0;
14310
14311 flush_scheduled_work();
14312 tg3_phy_stop(tp);
14313 tg3_netif_stop(tp);
14314
14315 del_timer_sync(&tp->timer);
14316
14317 tg3_full_lock(tp, 1);
14318 tg3_disable_ints(tp);
14319 tg3_full_unlock(tp);
14320
14321 netif_device_detach(dev);
14322
14323 tg3_full_lock(tp, 0);
14324 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14325 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14326 tg3_full_unlock(tp);
14327
14328 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14329
14330 err = tg3_set_power_state(tp, target_state);
14331 if (err) {
14332 int err2;
14333
14334 tg3_full_lock(tp, 0);
14335
14336 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14337 err2 = tg3_restart_hw(tp, 1);
14338 if (err2)
14339 goto out;
14340
14341 tp->timer.expires = jiffies + tp->timer_offset;
14342 add_timer(&tp->timer);
14343
14344 netif_device_attach(dev);
14345 tg3_netif_start(tp);
14346
14347 out:
14348 tg3_full_unlock(tp);
14349
14350 if (!err2)
14351 tg3_phy_start(tp);
14352 }
14353
14354 return err;
14355 }
14356
14357 static int tg3_resume(struct pci_dev *pdev)
14358 {
14359 struct net_device *dev = pci_get_drvdata(pdev);
14360 struct tg3 *tp = netdev_priv(dev);
14361 int err;
14362
14363 pci_restore_state(tp->pdev);
14364
14365 if (!netif_running(dev))
14366 return 0;
14367
14368 err = tg3_set_power_state(tp, PCI_D0);
14369 if (err)
14370 return err;
14371
14372 netif_device_attach(dev);
14373
14374 tg3_full_lock(tp, 0);
14375
14376 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14377 err = tg3_restart_hw(tp, 1);
14378 if (err)
14379 goto out;
14380
14381 tp->timer.expires = jiffies + tp->timer_offset;
14382 add_timer(&tp->timer);
14383
14384 tg3_netif_start(tp);
14385
14386 out:
14387 tg3_full_unlock(tp);
14388
14389 if (!err)
14390 tg3_phy_start(tp);
14391
14392 return err;
14393 }
14394
14395 static struct pci_driver tg3_driver = {
14396 .name = DRV_MODULE_NAME,
14397 .id_table = tg3_pci_tbl,
14398 .probe = tg3_init_one,
14399 .remove = __devexit_p(tg3_remove_one),
14400 .suspend = tg3_suspend,
14401 .resume = tg3_resume
14402 };
14403
14404 static int __init tg3_init(void)
14405 {
14406 return pci_register_driver(&tg3_driver);
14407 }
14408
14409 static void __exit tg3_cleanup(void)
14410 {
14411 pci_unregister_driver(&tg3_driver);
14412 }
14413
14414 module_init(tg3_init);
14415 module_exit(tg3_cleanup);
Linux kernel - Deliverables
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