1 /* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 davem Exp $
2 * tg3.h: Definitions for Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
12 #define TG3_64BIT_REG_HIGH 0x00UL
13 #define TG3_64BIT_REG_LOW 0x04UL
15 /* Descriptor block info. */
16 #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
17 #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
18 #define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */
19 #define BDINFO_FLAGS_DISABLED 0x00000002
20 #define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000
21 #define BDINFO_FLAGS_MAXLEN_SHIFT 16
22 #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
23 #define TG3_BDINFO_SIZE 0x10UL
25 #define RX_COPY_THRESHOLD 256
27 #define TG3_RX_INTERNAL_RING_SZ_5906 32
29 #define RX_STD_MAX_SIZE 1536
30 #define RX_STD_MAX_SIZE_5705 512
31 #define RX_JUMBO_MAX_SIZE 0xdeadbeef /* XXX */
33 /* First 256 bytes are a mirror of PCI config space. */
34 #define TG3PCI_VENDOR 0x00000000
35 #define TG3PCI_VENDOR_BROADCOM 0x14e4
36 #define TG3PCI_DEVICE 0x00000002
37 #define TG3PCI_DEVICE_TIGON3_1 0x1644 /* BCM5700 */
38 #define TG3PCI_DEVICE_TIGON3_2 0x1645 /* BCM5701 */
39 #define TG3PCI_DEVICE_TIGON3_3 0x1646 /* BCM5702 */
40 #define TG3PCI_DEVICE_TIGON3_4 0x1647 /* BCM5703 */
41 #define TG3PCI_COMMAND 0x00000004
42 #define TG3PCI_STATUS 0x00000006
43 #define TG3PCI_CCREVID 0x00000008
44 #define TG3PCI_CACHELINESZ 0x0000000c
45 #define TG3PCI_LATTIMER 0x0000000d
46 #define TG3PCI_HEADERTYPE 0x0000000e
47 #define TG3PCI_BIST 0x0000000f
48 #define TG3PCI_BASE0_LOW 0x00000010
49 #define TG3PCI_BASE0_HIGH 0x00000014
50 /* 0x18 --> 0x2c unused */
51 #define TG3PCI_SUBSYSVENID 0x0000002c
52 #define TG3PCI_SUBSYSID 0x0000002e
53 #define TG3PCI_ROMADDR 0x00000030
54 #define TG3PCI_CAPLIST 0x00000034
55 /* 0x35 --> 0x3c unused */
56 #define TG3PCI_IRQ_LINE 0x0000003c
57 #define TG3PCI_IRQ_PIN 0x0000003d
58 #define TG3PCI_MIN_GNT 0x0000003e
59 #define TG3PCI_MAX_LAT 0x0000003f
60 /* 0x40 --> 0x64 unused */
61 #define TG3PCI_MSI_DATA 0x00000064
62 /* 0x66 --> 0x68 unused */
63 #define TG3PCI_MISC_HOST_CTRL 0x00000068
64 #define MISC_HOST_CTRL_CLEAR_INT 0x00000001
65 #define MISC_HOST_CTRL_MASK_PCI_INT 0x00000002
66 #define MISC_HOST_CTRL_BYTE_SWAP 0x00000004
67 #define MISC_HOST_CTRL_WORD_SWAP 0x00000008
68 #define MISC_HOST_CTRL_PCISTATE_RW 0x00000010
69 #define MISC_HOST_CTRL_CLKREG_RW 0x00000020
70 #define MISC_HOST_CTRL_REGWORD_SWAP 0x00000040
71 #define MISC_HOST_CTRL_INDIR_ACCESS 0x00000080
72 #define MISC_HOST_CTRL_IRQ_MASK_MODE 0x00000100
73 #define MISC_HOST_CTRL_TAGGED_STATUS 0x00000200
74 #define MISC_HOST_CTRL_CHIPREV 0xffff0000
75 #define MISC_HOST_CTRL_CHIPREV_SHIFT 16
76 #define GET_CHIP_REV_ID(MISC_HOST_CTRL) \
77 (((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \
78 MISC_HOST_CTRL_CHIPREV_SHIFT)
79 #define CHIPREV_ID_5700_A0 0x7000
80 #define CHIPREV_ID_5700_A1 0x7001
81 #define CHIPREV_ID_5700_B0 0x7100
82 #define CHIPREV_ID_5700_B1 0x7101
83 #define CHIPREV_ID_5700_B3 0x7102
84 #define CHIPREV_ID_5700_ALTIMA 0x7104
85 #define CHIPREV_ID_5700_C0 0x7200
86 #define CHIPREV_ID_5701_A0 0x0000
87 #define CHIPREV_ID_5701_B0 0x0100
88 #define CHIPREV_ID_5701_B2 0x0102
89 #define CHIPREV_ID_5701_B5 0x0105
90 #define CHIPREV_ID_5703_A0 0x1000
91 #define CHIPREV_ID_5703_A1 0x1001
92 #define CHIPREV_ID_5703_A2 0x1002
93 #define CHIPREV_ID_5703_A3 0x1003
94 #define CHIPREV_ID_5704_A0 0x2000
95 #define CHIPREV_ID_5704_A1 0x2001
96 #define CHIPREV_ID_5704_A2 0x2002
97 #define CHIPREV_ID_5704_A3 0x2003
98 #define CHIPREV_ID_5705_A0 0x3000
99 #define CHIPREV_ID_5705_A1 0x3001
100 #define CHIPREV_ID_5705_A2 0x3002
101 #define CHIPREV_ID_5705_A3 0x3003
102 #define CHIPREV_ID_5750_A0 0x4000
103 #define CHIPREV_ID_5750_A1 0x4001
104 #define CHIPREV_ID_5750_A3 0x4003
105 #define CHIPREV_ID_5750_C2 0x4202
106 #define CHIPREV_ID_5752_A0_HW 0x5000
107 #define CHIPREV_ID_5752_A0 0x6000
108 #define CHIPREV_ID_5752_A1 0x6001
109 #define CHIPREV_ID_5714_A2 0x9002
110 #define CHIPREV_ID_5906_A1 0xc001
111 #define CHIPREV_ID_5784_A0 0x5784000
112 #define CHIPREV_ID_5761_A0 0x5761000
113 #define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12)
114 #define ASIC_REV_5700 0x07
115 #define ASIC_REV_5701 0x00
116 #define ASIC_REV_5703 0x01
117 #define ASIC_REV_5704 0x02
118 #define ASIC_REV_5705 0x03
119 #define ASIC_REV_5750 0x04
120 #define ASIC_REV_5752 0x06
121 #define ASIC_REV_5780 0x08
122 #define ASIC_REV_5714 0x09
123 #define ASIC_REV_5755 0x0a
124 #define ASIC_REV_5787 0x0b
125 #define ASIC_REV_5906 0x0c
126 #define ASIC_REV_USE_PROD_ID_REG 0x0f
127 #define ASIC_REV_5784 0x5784
128 #define ASIC_REV_5761 0x5761
129 #define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8)
130 #define CHIPREV_5700_AX 0x70
131 #define CHIPREV_5700_BX 0x71
132 #define CHIPREV_5700_CX 0x72
133 #define CHIPREV_5701_AX 0x00
134 #define CHIPREV_5703_AX 0x10
135 #define CHIPREV_5704_AX 0x20
136 #define CHIPREV_5704_BX 0x21
137 #define CHIPREV_5750_AX 0x40
138 #define CHIPREV_5750_BX 0x41
139 #define GET_METAL_REV(CHIP_REV_ID) ((CHIP_REV_ID) & 0xff)
140 #define METAL_REV_A0 0x00
141 #define METAL_REV_A1 0x01
142 #define METAL_REV_B0 0x00
143 #define METAL_REV_B1 0x01
144 #define METAL_REV_B2 0x02
145 #define TG3PCI_DMA_RW_CTRL 0x0000006c
146 #define DMA_RWCTRL_MIN_DMA 0x000000ff
147 #define DMA_RWCTRL_MIN_DMA_SHIFT 0
148 #define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700
149 #define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000
150 #define DMA_RWCTRL_READ_BNDRY_16 0x00000100
151 #define DMA_RWCTRL_READ_BNDRY_128_PCIX 0x00000100
152 #define DMA_RWCTRL_READ_BNDRY_32 0x00000200
153 #define DMA_RWCTRL_READ_BNDRY_256_PCIX 0x00000200
154 #define DMA_RWCTRL_READ_BNDRY_64 0x00000300
155 #define DMA_RWCTRL_READ_BNDRY_384_PCIX 0x00000300
156 #define DMA_RWCTRL_READ_BNDRY_128 0x00000400
157 #define DMA_RWCTRL_READ_BNDRY_256 0x00000500
158 #define DMA_RWCTRL_READ_BNDRY_512 0x00000600
159 #define DMA_RWCTRL_READ_BNDRY_1024 0x00000700
160 #define DMA_RWCTRL_WRITE_BNDRY_MASK 0x00003800
161 #define DMA_RWCTRL_WRITE_BNDRY_DISAB 0x00000000
162 #define DMA_RWCTRL_WRITE_BNDRY_16 0x00000800
163 #define DMA_RWCTRL_WRITE_BNDRY_128_PCIX 0x00000800
164 #define DMA_RWCTRL_WRITE_BNDRY_32 0x00001000
165 #define DMA_RWCTRL_WRITE_BNDRY_256_PCIX 0x00001000
166 #define DMA_RWCTRL_WRITE_BNDRY_64 0x00001800
167 #define DMA_RWCTRL_WRITE_BNDRY_384_PCIX 0x00001800
168 #define DMA_RWCTRL_WRITE_BNDRY_128 0x00002000
169 #define DMA_RWCTRL_WRITE_BNDRY_256 0x00002800
170 #define DMA_RWCTRL_WRITE_BNDRY_512 0x00003000
171 #define DMA_RWCTRL_WRITE_BNDRY_1024 0x00003800
172 #define DMA_RWCTRL_ONE_DMA 0x00004000
173 #define DMA_RWCTRL_READ_WATER 0x00070000
174 #define DMA_RWCTRL_READ_WATER_SHIFT 16
175 #define DMA_RWCTRL_WRITE_WATER 0x00380000
176 #define DMA_RWCTRL_WRITE_WATER_SHIFT 19
177 #define DMA_RWCTRL_USE_MEM_READ_MULT 0x00400000
178 #define DMA_RWCTRL_ASSERT_ALL_BE 0x00800000
179 #define DMA_RWCTRL_PCI_READ_CMD 0x0f000000
180 #define DMA_RWCTRL_PCI_READ_CMD_SHIFT 24
181 #define DMA_RWCTRL_PCI_WRITE_CMD 0xf0000000
182 #define DMA_RWCTRL_PCI_WRITE_CMD_SHIFT 28
183 #define DMA_RWCTRL_WRITE_BNDRY_64_PCIE 0x10000000
184 #define DMA_RWCTRL_WRITE_BNDRY_128_PCIE 0x30000000
185 #define DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE 0x70000000
186 #define TG3PCI_PCISTATE 0x00000070
187 #define PCISTATE_FORCE_RESET 0x00000001
188 #define PCISTATE_INT_NOT_ACTIVE 0x00000002
189 #define PCISTATE_CONV_PCI_MODE 0x00000004
190 #define PCISTATE_BUS_SPEED_HIGH 0x00000008
191 #define PCISTATE_BUS_32BIT 0x00000010
192 #define PCISTATE_ROM_ENABLE 0x00000020
193 #define PCISTATE_ROM_RETRY_ENABLE 0x00000040
194 #define PCISTATE_FLAT_VIEW 0x00000100
195 #define PCISTATE_RETRY_SAME_DMA 0x00002000
196 #define PCISTATE_ALLOW_APE_CTLSPC_WR 0x00010000
197 #define PCISTATE_ALLOW_APE_SHMEM_WR 0x00020000
198 #define TG3PCI_CLOCK_CTRL 0x00000074
199 #define CLOCK_CTRL_CORECLK_DISABLE 0x00000200
200 #define CLOCK_CTRL_RXCLK_DISABLE 0x00000400
201 #define CLOCK_CTRL_TXCLK_DISABLE 0x00000800
202 #define CLOCK_CTRL_ALTCLK 0x00001000
203 #define CLOCK_CTRL_PWRDOWN_PLL133 0x00008000
204 #define CLOCK_CTRL_44MHZ_CORE 0x00040000
205 #define CLOCK_CTRL_625_CORE 0x00100000
206 #define CLOCK_CTRL_FORCE_CLKRUN 0x00200000
207 #define CLOCK_CTRL_CLKRUN_OENABLE 0x00400000
208 #define CLOCK_CTRL_DELAY_PCI_GRANT 0x80000000
209 #define TG3PCI_REG_BASE_ADDR 0x00000078
210 #define TG3PCI_MEM_WIN_BASE_ADDR 0x0000007c
211 #define TG3PCI_REG_DATA 0x00000080
212 #define TG3PCI_MEM_WIN_DATA 0x00000084
213 #define TG3PCI_MODE_CTRL 0x00000088
214 #define TG3PCI_MISC_CFG 0x0000008c
215 #define TG3PCI_MISC_LOCAL_CTRL 0x00000090
216 /* 0x94 --> 0x98 unused */
217 #define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */
218 #define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */
219 #define TG3PCI_SND_PROD_IDX 0x000000a8 /* 64-bit */
220 /* 0xb0 --> 0xb8 unused */
221 #define TG3PCI_DUAL_MAC_CTRL 0x000000b8
222 #define DUAL_MAC_CTRL_CH_MASK 0x00000003
223 #define DUAL_MAC_CTRL_ID 0x00000004
224 #define TG3PCI_PRODID_ASICREV 0x000000bc
225 #define PROD_ID_ASIC_REV_MASK 0x0fffffff
226 /* 0xc0 --> 0x100 unused */
228 /* 0x100 --> 0x200 unused */
230 /* Mailbox registers */
231 #define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */
232 #define MAILBOX_INTERRUPT_1 0x00000208 /* 64-bit */
233 #define MAILBOX_INTERRUPT_2 0x00000210 /* 64-bit */
234 #define MAILBOX_INTERRUPT_3 0x00000218 /* 64-bit */
235 #define MAILBOX_GENERAL_0 0x00000220 /* 64-bit */
236 #define MAILBOX_GENERAL_1 0x00000228 /* 64-bit */
237 #define MAILBOX_GENERAL_2 0x00000230 /* 64-bit */
238 #define MAILBOX_GENERAL_3 0x00000238 /* 64-bit */
239 #define MAILBOX_GENERAL_4 0x00000240 /* 64-bit */
240 #define MAILBOX_GENERAL_5 0x00000248 /* 64-bit */
241 #define MAILBOX_GENERAL_6 0x00000250 /* 64-bit */
242 #define MAILBOX_GENERAL_7 0x00000258 /* 64-bit */
243 #define MAILBOX_RELOAD_STAT 0x00000260 /* 64-bit */
244 #define MAILBOX_RCV_STD_PROD_IDX 0x00000268 /* 64-bit */
245 #define MAILBOX_RCV_JUMBO_PROD_IDX 0x00000270 /* 64-bit */
246 #define MAILBOX_RCV_MINI_PROD_IDX 0x00000278 /* 64-bit */
247 #define MAILBOX_RCVRET_CON_IDX_0 0x00000280 /* 64-bit */
248 #define MAILBOX_RCVRET_CON_IDX_1 0x00000288 /* 64-bit */
249 #define MAILBOX_RCVRET_CON_IDX_2 0x00000290 /* 64-bit */
250 #define MAILBOX_RCVRET_CON_IDX_3 0x00000298 /* 64-bit */
251 #define MAILBOX_RCVRET_CON_IDX_4 0x000002a0 /* 64-bit */
252 #define MAILBOX_RCVRET_CON_IDX_5 0x000002a8 /* 64-bit */
253 #define MAILBOX_RCVRET_CON_IDX_6 0x000002b0 /* 64-bit */
254 #define MAILBOX_RCVRET_CON_IDX_7 0x000002b8 /* 64-bit */
255 #define MAILBOX_RCVRET_CON_IDX_8 0x000002c0 /* 64-bit */
256 #define MAILBOX_RCVRET_CON_IDX_9 0x000002c8 /* 64-bit */
257 #define MAILBOX_RCVRET_CON_IDX_10 0x000002d0 /* 64-bit */
258 #define MAILBOX_RCVRET_CON_IDX_11 0x000002d8 /* 64-bit */
259 #define MAILBOX_RCVRET_CON_IDX_12 0x000002e0 /* 64-bit */
260 #define MAILBOX_RCVRET_CON_IDX_13 0x000002e8 /* 64-bit */
261 #define MAILBOX_RCVRET_CON_IDX_14 0x000002f0 /* 64-bit */
262 #define MAILBOX_RCVRET_CON_IDX_15 0x000002f8 /* 64-bit */
263 #define MAILBOX_SNDHOST_PROD_IDX_0 0x00000300 /* 64-bit */
264 #define MAILBOX_SNDHOST_PROD_IDX_1 0x00000308 /* 64-bit */
265 #define MAILBOX_SNDHOST_PROD_IDX_2 0x00000310 /* 64-bit */
266 #define MAILBOX_SNDHOST_PROD_IDX_3 0x00000318 /* 64-bit */
267 #define MAILBOX_SNDHOST_PROD_IDX_4 0x00000320 /* 64-bit */
268 #define MAILBOX_SNDHOST_PROD_IDX_5 0x00000328 /* 64-bit */
269 #define MAILBOX_SNDHOST_PROD_IDX_6 0x00000330 /* 64-bit */
270 #define MAILBOX_SNDHOST_PROD_IDX_7 0x00000338 /* 64-bit */
271 #define MAILBOX_SNDHOST_PROD_IDX_8 0x00000340 /* 64-bit */
272 #define MAILBOX_SNDHOST_PROD_IDX_9 0x00000348 /* 64-bit */
273 #define MAILBOX_SNDHOST_PROD_IDX_10 0x00000350 /* 64-bit */
274 #define MAILBOX_SNDHOST_PROD_IDX_11 0x00000358 /* 64-bit */
275 #define MAILBOX_SNDHOST_PROD_IDX_12 0x00000360 /* 64-bit */
276 #define MAILBOX_SNDHOST_PROD_IDX_13 0x00000368 /* 64-bit */
277 #define MAILBOX_SNDHOST_PROD_IDX_14 0x00000370 /* 64-bit */
278 #define MAILBOX_SNDHOST_PROD_IDX_15 0x00000378 /* 64-bit */
279 #define MAILBOX_SNDNIC_PROD_IDX_0 0x00000380 /* 64-bit */
280 #define MAILBOX_SNDNIC_PROD_IDX_1 0x00000388 /* 64-bit */
281 #define MAILBOX_SNDNIC_PROD_IDX_2 0x00000390 /* 64-bit */
282 #define MAILBOX_SNDNIC_PROD_IDX_3 0x00000398 /* 64-bit */
283 #define MAILBOX_SNDNIC_PROD_IDX_4 0x000003a0 /* 64-bit */
284 #define MAILBOX_SNDNIC_PROD_IDX_5 0x000003a8 /* 64-bit */
285 #define MAILBOX_SNDNIC_PROD_IDX_6 0x000003b0 /* 64-bit */
286 #define MAILBOX_SNDNIC_PROD_IDX_7 0x000003b8 /* 64-bit */
287 #define MAILBOX_SNDNIC_PROD_IDX_8 0x000003c0 /* 64-bit */
288 #define MAILBOX_SNDNIC_PROD_IDX_9 0x000003c8 /* 64-bit */
289 #define MAILBOX_SNDNIC_PROD_IDX_10 0x000003d0 /* 64-bit */
290 #define MAILBOX_SNDNIC_PROD_IDX_11 0x000003d8 /* 64-bit */
291 #define MAILBOX_SNDNIC_PROD_IDX_12 0x000003e0 /* 64-bit */
292 #define MAILBOX_SNDNIC_PROD_IDX_13 0x000003e8 /* 64-bit */
293 #define MAILBOX_SNDNIC_PROD_IDX_14 0x000003f0 /* 64-bit */
294 #define MAILBOX_SNDNIC_PROD_IDX_15 0x000003f8 /* 64-bit */
296 /* MAC control registers */
297 #define MAC_MODE 0x00000400
298 #define MAC_MODE_RESET 0x00000001
299 #define MAC_MODE_HALF_DUPLEX 0x00000002
300 #define MAC_MODE_PORT_MODE_MASK 0x0000000c
301 #define MAC_MODE_PORT_MODE_TBI 0x0000000c
302 #define MAC_MODE_PORT_MODE_GMII 0x00000008
303 #define MAC_MODE_PORT_MODE_MII 0x00000004
304 #define MAC_MODE_PORT_MODE_NONE 0x00000000
305 #define MAC_MODE_PORT_INT_LPBACK 0x00000010
306 #define MAC_MODE_TAGGED_MAC_CTRL 0x00000080
307 #define MAC_MODE_TX_BURSTING 0x00000100
308 #define MAC_MODE_MAX_DEFER 0x00000200
309 #define MAC_MODE_LINK_POLARITY 0x00000400
310 #define MAC_MODE_RXSTAT_ENABLE 0x00000800
311 #define MAC_MODE_RXSTAT_CLEAR 0x00001000
312 #define MAC_MODE_RXSTAT_FLUSH 0x00002000
313 #define MAC_MODE_TXSTAT_ENABLE 0x00004000
314 #define MAC_MODE_TXSTAT_CLEAR 0x00008000
315 #define MAC_MODE_TXSTAT_FLUSH 0x00010000
316 #define MAC_MODE_SEND_CONFIGS 0x00020000
317 #define MAC_MODE_MAGIC_PKT_ENABLE 0x00040000
318 #define MAC_MODE_ACPI_ENABLE 0x00080000
319 #define MAC_MODE_MIP_ENABLE 0x00100000
320 #define MAC_MODE_TDE_ENABLE 0x00200000
321 #define MAC_MODE_RDE_ENABLE 0x00400000
322 #define MAC_MODE_FHDE_ENABLE 0x00800000
323 #define MAC_STATUS 0x00000404
324 #define MAC_STATUS_PCS_SYNCED 0x00000001
325 #define MAC_STATUS_SIGNAL_DET 0x00000002
326 #define MAC_STATUS_RCVD_CFG 0x00000004
327 #define MAC_STATUS_CFG_CHANGED 0x00000008
328 #define MAC_STATUS_SYNC_CHANGED 0x00000010
329 #define MAC_STATUS_PORT_DEC_ERR 0x00000400
330 #define MAC_STATUS_LNKSTATE_CHANGED 0x00001000
331 #define MAC_STATUS_MI_COMPLETION 0x00400000
332 #define MAC_STATUS_MI_INTERRUPT 0x00800000
333 #define MAC_STATUS_AP_ERROR 0x01000000
334 #define MAC_STATUS_ODI_ERROR 0x02000000
335 #define MAC_STATUS_RXSTAT_OVERRUN 0x04000000
336 #define MAC_STATUS_TXSTAT_OVERRUN 0x08000000
337 #define MAC_EVENT 0x00000408
338 #define MAC_EVENT_PORT_DECODE_ERR 0x00000400
339 #define MAC_EVENT_LNKSTATE_CHANGED 0x00001000
340 #define MAC_EVENT_MI_COMPLETION 0x00400000
341 #define MAC_EVENT_MI_INTERRUPT 0x00800000
342 #define MAC_EVENT_AP_ERROR 0x01000000
343 #define MAC_EVENT_ODI_ERROR 0x02000000
344 #define MAC_EVENT_RXSTAT_OVERRUN 0x04000000
345 #define MAC_EVENT_TXSTAT_OVERRUN 0x08000000
346 #define MAC_LED_CTRL 0x0000040c
347 #define LED_CTRL_LNKLED_OVERRIDE 0x00000001
348 #define LED_CTRL_1000MBPS_ON 0x00000002
349 #define LED_CTRL_100MBPS_ON 0x00000004
350 #define LED_CTRL_10MBPS_ON 0x00000008
351 #define LED_CTRL_TRAFFIC_OVERRIDE 0x00000010
352 #define LED_CTRL_TRAFFIC_BLINK 0x00000020
353 #define LED_CTRL_TRAFFIC_LED 0x00000040
354 #define LED_CTRL_1000MBPS_STATUS 0x00000080
355 #define LED_CTRL_100MBPS_STATUS 0x00000100
356 #define LED_CTRL_10MBPS_STATUS 0x00000200
357 #define LED_CTRL_TRAFFIC_STATUS 0x00000400
358 #define LED_CTRL_MODE_MAC 0x00000000
359 #define LED_CTRL_MODE_PHY_1 0x00000800
360 #define LED_CTRL_MODE_PHY_2 0x00001000
361 #define LED_CTRL_MODE_SHASTA_MAC 0x00002000
362 #define LED_CTRL_MODE_SHARED 0x00004000
363 #define LED_CTRL_MODE_COMBO 0x00008000
364 #define LED_CTRL_BLINK_RATE_MASK 0x7ff80000
365 #define LED_CTRL_BLINK_RATE_SHIFT 19
366 #define LED_CTRL_BLINK_PER_OVERRIDE 0x00080000
367 #define LED_CTRL_BLINK_RATE_OVERRIDE 0x80000000
368 #define MAC_ADDR_0_HIGH 0x00000410 /* upper 2 bytes */
369 #define MAC_ADDR_0_LOW 0x00000414 /* lower 4 bytes */
370 #define MAC_ADDR_1_HIGH 0x00000418 /* upper 2 bytes */
371 #define MAC_ADDR_1_LOW 0x0000041c /* lower 4 bytes */
372 #define MAC_ADDR_2_HIGH 0x00000420 /* upper 2 bytes */
373 #define MAC_ADDR_2_LOW 0x00000424 /* lower 4 bytes */
374 #define MAC_ADDR_3_HIGH 0x00000428 /* upper 2 bytes */
375 #define MAC_ADDR_3_LOW 0x0000042c /* lower 4 bytes */
376 #define MAC_ACPI_MBUF_PTR 0x00000430
377 #define MAC_ACPI_LEN_OFFSET 0x00000434
378 #define ACPI_LENOFF_LEN_MASK 0x0000ffff
379 #define ACPI_LENOFF_LEN_SHIFT 0
380 #define ACPI_LENOFF_OFF_MASK 0x0fff0000
381 #define ACPI_LENOFF_OFF_SHIFT 16
382 #define MAC_TX_BACKOFF_SEED 0x00000438
383 #define TX_BACKOFF_SEED_MASK 0x000003ff
384 #define MAC_RX_MTU_SIZE 0x0000043c
385 #define RX_MTU_SIZE_MASK 0x0000ffff
386 #define MAC_PCS_TEST 0x00000440
387 #define PCS_TEST_PATTERN_MASK 0x000fffff
388 #define PCS_TEST_PATTERN_SHIFT 0
389 #define PCS_TEST_ENABLE 0x00100000
390 #define MAC_TX_AUTO_NEG 0x00000444
391 #define TX_AUTO_NEG_MASK 0x0000ffff
392 #define TX_AUTO_NEG_SHIFT 0
393 #define MAC_RX_AUTO_NEG 0x00000448
394 #define RX_AUTO_NEG_MASK 0x0000ffff
395 #define RX_AUTO_NEG_SHIFT 0
396 #define MAC_MI_COM 0x0000044c
397 #define MI_COM_CMD_MASK 0x0c000000
398 #define MI_COM_CMD_WRITE 0x04000000
399 #define MI_COM_CMD_READ 0x08000000
400 #define MI_COM_READ_FAILED 0x10000000
401 #define MI_COM_START 0x20000000
402 #define MI_COM_BUSY 0x20000000
403 #define MI_COM_PHY_ADDR_MASK 0x03e00000
404 #define MI_COM_PHY_ADDR_SHIFT 21
405 #define MI_COM_REG_ADDR_MASK 0x001f0000
406 #define MI_COM_REG_ADDR_SHIFT 16
407 #define MI_COM_DATA_MASK 0x0000ffff
408 #define MAC_MI_STAT 0x00000450
409 #define MAC_MI_STAT_LNKSTAT_ATTN_ENAB 0x00000001
410 #define MAC_MI_MODE 0x00000454
411 #define MAC_MI_MODE_CLK_10MHZ 0x00000001
412 #define MAC_MI_MODE_SHORT_PREAMBLE 0x00000002
413 #define MAC_MI_MODE_AUTO_POLL 0x00000010
414 #define MAC_MI_MODE_CORE_CLK_62MHZ 0x00008000
415 #define MAC_MI_MODE_BASE 0x000c0000 /* XXX magic values XXX */
416 #define MAC_AUTO_POLL_STATUS 0x00000458
417 #define MAC_AUTO_POLL_ERROR 0x00000001
418 #define MAC_TX_MODE 0x0000045c
419 #define TX_MODE_RESET 0x00000001
420 #define TX_MODE_ENABLE 0x00000002
421 #define TX_MODE_FLOW_CTRL_ENABLE 0x00000010
422 #define TX_MODE_BIG_BCKOFF_ENABLE 0x00000020
423 #define TX_MODE_LONG_PAUSE_ENABLE 0x00000040
424 #define MAC_TX_STATUS 0x00000460
425 #define TX_STATUS_XOFFED 0x00000001
426 #define TX_STATUS_SENT_XOFF 0x00000002
427 #define TX_STATUS_SENT_XON 0x00000004
428 #define TX_STATUS_LINK_UP 0x00000008
429 #define TX_STATUS_ODI_UNDERRUN 0x00000010
430 #define TX_STATUS_ODI_OVERRUN 0x00000020
431 #define MAC_TX_LENGTHS 0x00000464
432 #define TX_LENGTHS_SLOT_TIME_MASK 0x000000ff
433 #define TX_LENGTHS_SLOT_TIME_SHIFT 0
434 #define TX_LENGTHS_IPG_MASK 0x00000f00
435 #define TX_LENGTHS_IPG_SHIFT 8
436 #define TX_LENGTHS_IPG_CRS_MASK 0x00003000
437 #define TX_LENGTHS_IPG_CRS_SHIFT 12
438 #define MAC_RX_MODE 0x00000468
439 #define RX_MODE_RESET 0x00000001
440 #define RX_MODE_ENABLE 0x00000002
441 #define RX_MODE_FLOW_CTRL_ENABLE 0x00000004
442 #define RX_MODE_KEEP_MAC_CTRL 0x00000008
443 #define RX_MODE_KEEP_PAUSE 0x00000010
444 #define RX_MODE_ACCEPT_OVERSIZED 0x00000020
445 #define RX_MODE_ACCEPT_RUNTS 0x00000040
446 #define RX_MODE_LEN_CHECK 0x00000080
447 #define RX_MODE_PROMISC 0x00000100
448 #define RX_MODE_NO_CRC_CHECK 0x00000200
449 #define RX_MODE_KEEP_VLAN_TAG 0x00000400
450 #define RX_MODE_IPV6_CSUM_ENABLE 0x01000000
451 #define MAC_RX_STATUS 0x0000046c
452 #define RX_STATUS_REMOTE_TX_XOFFED 0x00000001
453 #define RX_STATUS_XOFF_RCVD 0x00000002
454 #define RX_STATUS_XON_RCVD 0x00000004
455 #define MAC_HASH_REG_0 0x00000470
456 #define MAC_HASH_REG_1 0x00000474
457 #define MAC_HASH_REG_2 0x00000478
458 #define MAC_HASH_REG_3 0x0000047c
459 #define MAC_RCV_RULE_0 0x00000480
460 #define MAC_RCV_VALUE_0 0x00000484
461 #define MAC_RCV_RULE_1 0x00000488
462 #define MAC_RCV_VALUE_1 0x0000048c
463 #define MAC_RCV_RULE_2 0x00000490
464 #define MAC_RCV_VALUE_2 0x00000494
465 #define MAC_RCV_RULE_3 0x00000498
466 #define MAC_RCV_VALUE_3 0x0000049c
467 #define MAC_RCV_RULE_4 0x000004a0
468 #define MAC_RCV_VALUE_4 0x000004a4
469 #define MAC_RCV_RULE_5 0x000004a8
470 #define MAC_RCV_VALUE_5 0x000004ac
471 #define MAC_RCV_RULE_6 0x000004b0
472 #define MAC_RCV_VALUE_6 0x000004b4
473 #define MAC_RCV_RULE_7 0x000004b8
474 #define MAC_RCV_VALUE_7 0x000004bc
475 #define MAC_RCV_RULE_8 0x000004c0
476 #define MAC_RCV_VALUE_8 0x000004c4
477 #define MAC_RCV_RULE_9 0x000004c8
478 #define MAC_RCV_VALUE_9 0x000004cc
479 #define MAC_RCV_RULE_10 0x000004d0
480 #define MAC_RCV_VALUE_10 0x000004d4
481 #define MAC_RCV_RULE_11 0x000004d8
482 #define MAC_RCV_VALUE_11 0x000004dc
483 #define MAC_RCV_RULE_12 0x000004e0
484 #define MAC_RCV_VALUE_12 0x000004e4
485 #define MAC_RCV_RULE_13 0x000004e8
486 #define MAC_RCV_VALUE_13 0x000004ec
487 #define MAC_RCV_RULE_14 0x000004f0
488 #define MAC_RCV_VALUE_14 0x000004f4
489 #define MAC_RCV_RULE_15 0x000004f8
490 #define MAC_RCV_VALUE_15 0x000004fc
491 #define RCV_RULE_DISABLE_MASK 0x7fffffff
492 #define MAC_RCV_RULE_CFG 0x00000500
493 #define RCV_RULE_CFG_DEFAULT_CLASS 0x00000008
494 #define MAC_LOW_WMARK_MAX_RX_FRAME 0x00000504
495 /* 0x508 --> 0x520 unused */
496 #define MAC_HASHREGU_0 0x00000520
497 #define MAC_HASHREGU_1 0x00000524
498 #define MAC_HASHREGU_2 0x00000528
499 #define MAC_HASHREGU_3 0x0000052c
500 #define MAC_EXTADDR_0_HIGH 0x00000530
501 #define MAC_EXTADDR_0_LOW 0x00000534
502 #define MAC_EXTADDR_1_HIGH 0x00000538
503 #define MAC_EXTADDR_1_LOW 0x0000053c
504 #define MAC_EXTADDR_2_HIGH 0x00000540
505 #define MAC_EXTADDR_2_LOW 0x00000544
506 #define MAC_EXTADDR_3_HIGH 0x00000548
507 #define MAC_EXTADDR_3_LOW 0x0000054c
508 #define MAC_EXTADDR_4_HIGH 0x00000550
509 #define MAC_EXTADDR_4_LOW 0x00000554
510 #define MAC_EXTADDR_5_HIGH 0x00000558
511 #define MAC_EXTADDR_5_LOW 0x0000055c
512 #define MAC_EXTADDR_6_HIGH 0x00000560
513 #define MAC_EXTADDR_6_LOW 0x00000564
514 #define MAC_EXTADDR_7_HIGH 0x00000568
515 #define MAC_EXTADDR_7_LOW 0x0000056c
516 #define MAC_EXTADDR_8_HIGH 0x00000570
517 #define MAC_EXTADDR_8_LOW 0x00000574
518 #define MAC_EXTADDR_9_HIGH 0x00000578
519 #define MAC_EXTADDR_9_LOW 0x0000057c
520 #define MAC_EXTADDR_10_HIGH 0x00000580
521 #define MAC_EXTADDR_10_LOW 0x00000584
522 #define MAC_EXTADDR_11_HIGH 0x00000588
523 #define MAC_EXTADDR_11_LOW 0x0000058c
524 #define MAC_SERDES_CFG 0x00000590
525 #define MAC_SERDES_CFG_EDGE_SELECT 0x00001000
526 #define MAC_SERDES_STAT 0x00000594
527 /* 0x598 --> 0x5b0 unused */
528 #define SERDES_RX_CTRL 0x000005b0 /* 5780/5714 only */
529 #define SERDES_RX_SIG_DETECT 0x00000400
530 #define SG_DIG_CTRL 0x000005b0
531 #define SG_DIG_USING_HW_AUTONEG 0x80000000
532 #define SG_DIG_SOFT_RESET 0x40000000
533 #define SG_DIG_DISABLE_LINKRDY 0x20000000
534 #define SG_DIG_CRC16_CLEAR_N 0x01000000
535 #define SG_DIG_EN10B 0x00800000
536 #define SG_DIG_CLEAR_STATUS 0x00400000
537 #define SG_DIG_LOCAL_DUPLEX_STATUS 0x00200000
538 #define SG_DIG_LOCAL_LINK_STATUS 0x00100000
539 #define SG_DIG_SPEED_STATUS_MASK 0x000c0000
540 #define SG_DIG_SPEED_STATUS_SHIFT 18
541 #define SG_DIG_JUMBO_PACKET_DISABLE 0x00020000
542 #define SG_DIG_RESTART_AUTONEG 0x00010000
543 #define SG_DIG_FIBER_MODE 0x00008000
544 #define SG_DIG_REMOTE_FAULT_MASK 0x00006000
545 #define SG_DIG_PAUSE_MASK 0x00001800
546 #define SG_DIG_GBIC_ENABLE 0x00000400
547 #define SG_DIG_CHECK_END_ENABLE 0x00000200
548 #define SG_DIG_SGMII_AUTONEG_TIMER 0x00000100
549 #define SG_DIG_CLOCK_PHASE_SELECT 0x00000080
550 #define SG_DIG_GMII_INPUT_SELECT 0x00000040
551 #define SG_DIG_MRADV_CRC16_SELECT 0x00000020
552 #define SG_DIG_COMMA_DETECT_ENABLE 0x00000010
553 #define SG_DIG_AUTONEG_TIMER_REDUCE 0x00000008
554 #define SG_DIG_AUTONEG_LOW_ENABLE 0x00000004
555 #define SG_DIG_REMOTE_LOOPBACK 0x00000002
556 #define SG_DIG_LOOPBACK 0x00000001
557 #define SG_DIG_STATUS 0x000005b4
558 #define SG_DIG_CRC16_BUS_MASK 0xffff0000
559 #define SG_DIG_PARTNER_FAULT_MASK 0x00600000 /* If !MRADV_CRC16_SELECT */
560 #define SG_DIG_PARTNER_ASYM_PAUSE 0x00100000 /* If !MRADV_CRC16_SELECT */
561 #define SG_DIG_PARTNER_PAUSE_CAPABLE 0x00080000 /* If !MRADV_CRC16_SELECT */
562 #define SG_DIG_PARTNER_HALF_DUPLEX 0x00040000 /* If !MRADV_CRC16_SELECT */
563 #define SG_DIG_PARTNER_FULL_DUPLEX 0x00020000 /* If !MRADV_CRC16_SELECT */
564 #define SG_DIG_PARTNER_NEXT_PAGE 0x00010000 /* If !MRADV_CRC16_SELECT */
565 #define SG_DIG_AUTONEG_STATE_MASK 0x00000ff0
566 #define SG_DIG_COMMA_DETECTOR 0x00000008
567 #define SG_DIG_MAC_ACK_STATUS 0x00000004
568 #define SG_DIG_AUTONEG_COMPLETE 0x00000002
569 #define SG_DIG_AUTONEG_ERROR 0x00000001
570 /* 0x5b8 --> 0x600 unused */
571 #define MAC_TX_MAC_STATE_BASE 0x00000600 /* 16 bytes */
572 #define MAC_RX_MAC_STATE_BASE 0x00000610 /* 20 bytes */
573 /* 0x624 --> 0x800 unused */
574 #define MAC_TX_STATS_OCTETS 0x00000800
575 #define MAC_TX_STATS_RESV1 0x00000804
576 #define MAC_TX_STATS_COLLISIONS 0x00000808
577 #define MAC_TX_STATS_XON_SENT 0x0000080c
578 #define MAC_TX_STATS_XOFF_SENT 0x00000810
579 #define MAC_TX_STATS_RESV2 0x00000814
580 #define MAC_TX_STATS_MAC_ERRORS 0x00000818
581 #define MAC_TX_STATS_SINGLE_COLLISIONS 0x0000081c
582 #define MAC_TX_STATS_MULT_COLLISIONS 0x00000820
583 #define MAC_TX_STATS_DEFERRED 0x00000824
584 #define MAC_TX_STATS_RESV3 0x00000828
585 #define MAC_TX_STATS_EXCESSIVE_COL 0x0000082c
586 #define MAC_TX_STATS_LATE_COL 0x00000830
587 #define MAC_TX_STATS_RESV4_1 0x00000834
588 #define MAC_TX_STATS_RESV4_2 0x00000838
589 #define MAC_TX_STATS_RESV4_3 0x0000083c
590 #define MAC_TX_STATS_RESV4_4 0x00000840
591 #define MAC_TX_STATS_RESV4_5 0x00000844
592 #define MAC_TX_STATS_RESV4_6 0x00000848
593 #define MAC_TX_STATS_RESV4_7 0x0000084c
594 #define MAC_TX_STATS_RESV4_8 0x00000850
595 #define MAC_TX_STATS_RESV4_9 0x00000854
596 #define MAC_TX_STATS_RESV4_10 0x00000858
597 #define MAC_TX_STATS_RESV4_11 0x0000085c
598 #define MAC_TX_STATS_RESV4_12 0x00000860
599 #define MAC_TX_STATS_RESV4_13 0x00000864
600 #define MAC_TX_STATS_RESV4_14 0x00000868
601 #define MAC_TX_STATS_UCAST 0x0000086c
602 #define MAC_TX_STATS_MCAST 0x00000870
603 #define MAC_TX_STATS_BCAST 0x00000874
604 #define MAC_TX_STATS_RESV5_1 0x00000878
605 #define MAC_TX_STATS_RESV5_2 0x0000087c
606 #define MAC_RX_STATS_OCTETS 0x00000880
607 #define MAC_RX_STATS_RESV1 0x00000884
608 #define MAC_RX_STATS_FRAGMENTS 0x00000888
609 #define MAC_RX_STATS_UCAST 0x0000088c
610 #define MAC_RX_STATS_MCAST 0x00000890
611 #define MAC_RX_STATS_BCAST 0x00000894
612 #define MAC_RX_STATS_FCS_ERRORS 0x00000898
613 #define MAC_RX_STATS_ALIGN_ERRORS 0x0000089c
614 #define MAC_RX_STATS_XON_PAUSE_RECVD 0x000008a0
615 #define MAC_RX_STATS_XOFF_PAUSE_RECVD 0x000008a4
616 #define MAC_RX_STATS_MAC_CTRL_RECVD 0x000008a8
617 #define MAC_RX_STATS_XOFF_ENTERED 0x000008ac
618 #define MAC_RX_STATS_FRAME_TOO_LONG 0x000008b0
619 #define MAC_RX_STATS_JABBERS 0x000008b4
620 #define MAC_RX_STATS_UNDERSIZE 0x000008b8
621 /* 0x8bc --> 0xc00 unused */
623 /* Send data initiator control registers */
624 #define SNDDATAI_MODE 0x00000c00
625 #define SNDDATAI_MODE_RESET 0x00000001
626 #define SNDDATAI_MODE_ENABLE 0x00000002
627 #define SNDDATAI_MODE_STAT_OFLOW_ENAB 0x00000004
628 #define SNDDATAI_STATUS 0x00000c04
629 #define SNDDATAI_STATUS_STAT_OFLOW 0x00000004
630 #define SNDDATAI_STATSCTRL 0x00000c08
631 #define SNDDATAI_SCTRL_ENABLE 0x00000001
632 #define SNDDATAI_SCTRL_FASTUPD 0x00000002
633 #define SNDDATAI_SCTRL_CLEAR 0x00000004
634 #define SNDDATAI_SCTRL_FLUSH 0x00000008
635 #define SNDDATAI_SCTRL_FORCE_ZERO 0x00000010
636 #define SNDDATAI_STATSENAB 0x00000c0c
637 #define SNDDATAI_STATSINCMASK 0x00000c10
638 #define ISO_PKT_TX 0x00000c20
639 /* 0xc24 --> 0xc80 unused */
640 #define SNDDATAI_COS_CNT_0 0x00000c80
641 #define SNDDATAI_COS_CNT_1 0x00000c84
642 #define SNDDATAI_COS_CNT_2 0x00000c88
643 #define SNDDATAI_COS_CNT_3 0x00000c8c
644 #define SNDDATAI_COS_CNT_4 0x00000c90
645 #define SNDDATAI_COS_CNT_5 0x00000c94
646 #define SNDDATAI_COS_CNT_6 0x00000c98
647 #define SNDDATAI_COS_CNT_7 0x00000c9c
648 #define SNDDATAI_COS_CNT_8 0x00000ca0
649 #define SNDDATAI_COS_CNT_9 0x00000ca4
650 #define SNDDATAI_COS_CNT_10 0x00000ca8
651 #define SNDDATAI_COS_CNT_11 0x00000cac
652 #define SNDDATAI_COS_CNT_12 0x00000cb0
653 #define SNDDATAI_COS_CNT_13 0x00000cb4
654 #define SNDDATAI_COS_CNT_14 0x00000cb8
655 #define SNDDATAI_COS_CNT_15 0x00000cbc
656 #define SNDDATAI_DMA_RDQ_FULL_CNT 0x00000cc0
657 #define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT 0x00000cc4
658 #define SNDDATAI_SDCQ_FULL_CNT 0x00000cc8
659 #define SNDDATAI_NICRNG_SSND_PIDX_CNT 0x00000ccc
660 #define SNDDATAI_STATS_UPDATED_CNT 0x00000cd0
661 #define SNDDATAI_INTERRUPTS_CNT 0x00000cd4
662 #define SNDDATAI_AVOID_INTERRUPTS_CNT 0x00000cd8
663 #define SNDDATAI_SND_THRESH_HIT_CNT 0x00000cdc
664 /* 0xce0 --> 0x1000 unused */
666 /* Send data completion control registers */
667 #define SNDDATAC_MODE 0x00001000
668 #define SNDDATAC_MODE_RESET 0x00000001
669 #define SNDDATAC_MODE_ENABLE 0x00000002
670 #define SNDDATAC_MODE_CDELAY 0x00000010
671 /* 0x1004 --> 0x1400 unused */
673 /* Send BD ring selector */
674 #define SNDBDS_MODE 0x00001400
675 #define SNDBDS_MODE_RESET 0x00000001
676 #define SNDBDS_MODE_ENABLE 0x00000002
677 #define SNDBDS_MODE_ATTN_ENABLE 0x00000004
678 #define SNDBDS_STATUS 0x00001404
679 #define SNDBDS_STATUS_ERROR_ATTN 0x00000004
680 #define SNDBDS_HWDIAG 0x00001408
681 /* 0x140c --> 0x1440 */
682 #define SNDBDS_SEL_CON_IDX_0 0x00001440
683 #define SNDBDS_SEL_CON_IDX_1 0x00001444
684 #define SNDBDS_SEL_CON_IDX_2 0x00001448
685 #define SNDBDS_SEL_CON_IDX_3 0x0000144c
686 #define SNDBDS_SEL_CON_IDX_4 0x00001450
687 #define SNDBDS_SEL_CON_IDX_5 0x00001454
688 #define SNDBDS_SEL_CON_IDX_6 0x00001458
689 #define SNDBDS_SEL_CON_IDX_7 0x0000145c
690 #define SNDBDS_SEL_CON_IDX_8 0x00001460
691 #define SNDBDS_SEL_CON_IDX_9 0x00001464
692 #define SNDBDS_SEL_CON_IDX_10 0x00001468
693 #define SNDBDS_SEL_CON_IDX_11 0x0000146c
694 #define SNDBDS_SEL_CON_IDX_12 0x00001470
695 #define SNDBDS_SEL_CON_IDX_13 0x00001474
696 #define SNDBDS_SEL_CON_IDX_14 0x00001478
697 #define SNDBDS_SEL_CON_IDX_15 0x0000147c
698 /* 0x1480 --> 0x1800 unused */
700 /* Send BD initiator control registers */
701 #define SNDBDI_MODE 0x00001800
702 #define SNDBDI_MODE_RESET 0x00000001
703 #define SNDBDI_MODE_ENABLE 0x00000002
704 #define SNDBDI_MODE_ATTN_ENABLE 0x00000004
705 #define SNDBDI_STATUS 0x00001804
706 #define SNDBDI_STATUS_ERROR_ATTN 0x00000004
707 #define SNDBDI_IN_PROD_IDX_0 0x00001808
708 #define SNDBDI_IN_PROD_IDX_1 0x0000180c
709 #define SNDBDI_IN_PROD_IDX_2 0x00001810
710 #define SNDBDI_IN_PROD_IDX_3 0x00001814
711 #define SNDBDI_IN_PROD_IDX_4 0x00001818
712 #define SNDBDI_IN_PROD_IDX_5 0x0000181c
713 #define SNDBDI_IN_PROD_IDX_6 0x00001820
714 #define SNDBDI_IN_PROD_IDX_7 0x00001824
715 #define SNDBDI_IN_PROD_IDX_8 0x00001828
716 #define SNDBDI_IN_PROD_IDX_9 0x0000182c
717 #define SNDBDI_IN_PROD_IDX_10 0x00001830
718 #define SNDBDI_IN_PROD_IDX_11 0x00001834
719 #define SNDBDI_IN_PROD_IDX_12 0x00001838
720 #define SNDBDI_IN_PROD_IDX_13 0x0000183c
721 #define SNDBDI_IN_PROD_IDX_14 0x00001840
722 #define SNDBDI_IN_PROD_IDX_15 0x00001844
723 /* 0x1848 --> 0x1c00 unused */
725 /* Send BD completion control registers */
726 #define SNDBDC_MODE 0x00001c00
727 #define SNDBDC_MODE_RESET 0x00000001
728 #define SNDBDC_MODE_ENABLE 0x00000002
729 #define SNDBDC_MODE_ATTN_ENABLE 0x00000004
730 /* 0x1c04 --> 0x2000 unused */
732 /* Receive list placement control registers */
733 #define RCVLPC_MODE 0x00002000
734 #define RCVLPC_MODE_RESET 0x00000001
735 #define RCVLPC_MODE_ENABLE 0x00000002
736 #define RCVLPC_MODE_CLASS0_ATTN_ENAB 0x00000004
737 #define RCVLPC_MODE_MAPOOR_AATTN_ENAB 0x00000008
738 #define RCVLPC_MODE_STAT_OFLOW_ENAB 0x00000010
739 #define RCVLPC_STATUS 0x00002004
740 #define RCVLPC_STATUS_CLASS0 0x00000004
741 #define RCVLPC_STATUS_MAPOOR 0x00000008
742 #define RCVLPC_STATUS_STAT_OFLOW 0x00000010
743 #define RCVLPC_LOCK 0x00002008
744 #define RCVLPC_LOCK_REQ_MASK 0x0000ffff
745 #define RCVLPC_LOCK_REQ_SHIFT 0
746 #define RCVLPC_LOCK_GRANT_MASK 0xffff0000
747 #define RCVLPC_LOCK_GRANT_SHIFT 16
748 #define RCVLPC_NON_EMPTY_BITS 0x0000200c
749 #define RCVLPC_NON_EMPTY_BITS_MASK 0x0000ffff
750 #define RCVLPC_CONFIG 0x00002010
751 #define RCVLPC_STATSCTRL 0x00002014
752 #define RCVLPC_STATSCTRL_ENABLE 0x00000001
753 #define RCVLPC_STATSCTRL_FASTUPD 0x00000002
754 #define RCVLPC_STATS_ENABLE 0x00002018
755 #define RCVLPC_STATSENAB_DACK_FIX 0x00040000
756 #define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000
757 #define RCVLPC_STATS_INCMASK 0x0000201c
758 /* 0x2020 --> 0x2100 unused */
759 #define RCVLPC_SELLST_BASE 0x00002100 /* 16 16-byte entries */
760 #define SELLST_TAIL 0x00000004
761 #define SELLST_CONT 0x00000008
762 #define SELLST_UNUSED 0x0000000c
763 #define RCVLPC_COS_CNTL_BASE 0x00002200 /* 16 4-byte entries */
764 #define RCVLPC_DROP_FILTER_CNT 0x00002240
765 #define RCVLPC_DMA_WQ_FULL_CNT 0x00002244
766 #define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT 0x00002248
767 #define RCVLPC_NO_RCV_BD_CNT 0x0000224c
768 #define RCVLPC_IN_DISCARDS_CNT 0x00002250
769 #define RCVLPC_IN_ERRORS_CNT 0x00002254
770 #define RCVLPC_RCV_THRESH_HIT_CNT 0x00002258
771 /* 0x225c --> 0x2400 unused */
773 /* Receive Data and Receive BD Initiator Control */
774 #define RCVDBDI_MODE 0x00002400
775 #define RCVDBDI_MODE_RESET 0x00000001
776 #define RCVDBDI_MODE_ENABLE 0x00000002
777 #define RCVDBDI_MODE_JUMBOBD_NEEDED 0x00000004
778 #define RCVDBDI_MODE_FRM_TOO_BIG 0x00000008
779 #define RCVDBDI_MODE_INV_RING_SZ 0x00000010
780 #define RCVDBDI_STATUS 0x00002404
781 #define RCVDBDI_STATUS_JUMBOBD_NEEDED 0x00000004
782 #define RCVDBDI_STATUS_FRM_TOO_BIG 0x00000008
783 #define RCVDBDI_STATUS_INV_RING_SZ 0x00000010
784 #define RCVDBDI_SPLIT_FRAME_MINSZ 0x00002408
785 /* 0x240c --> 0x2440 unused */
786 #define RCVDBDI_JUMBO_BD 0x00002440 /* TG3_BDINFO_... */
787 #define RCVDBDI_STD_BD 0x00002450 /* TG3_BDINFO_... */
788 #define RCVDBDI_MINI_BD 0x00002460 /* TG3_BDINFO_... */
789 #define RCVDBDI_JUMBO_CON_IDX 0x00002470
790 #define RCVDBDI_STD_CON_IDX 0x00002474
791 #define RCVDBDI_MINI_CON_IDX 0x00002478
792 /* 0x247c --> 0x2480 unused */
793 #define RCVDBDI_BD_PROD_IDX_0 0x00002480
794 #define RCVDBDI_BD_PROD_IDX_1 0x00002484
795 #define RCVDBDI_BD_PROD_IDX_2 0x00002488
796 #define RCVDBDI_BD_PROD_IDX_3 0x0000248c
797 #define RCVDBDI_BD_PROD_IDX_4 0x00002490
798 #define RCVDBDI_BD_PROD_IDX_5 0x00002494
799 #define RCVDBDI_BD_PROD_IDX_6 0x00002498
800 #define RCVDBDI_BD_PROD_IDX_7 0x0000249c
801 #define RCVDBDI_BD_PROD_IDX_8 0x000024a0
802 #define RCVDBDI_BD_PROD_IDX_9 0x000024a4
803 #define RCVDBDI_BD_PROD_IDX_10 0x000024a8
804 #define RCVDBDI_BD_PROD_IDX_11 0x000024ac
805 #define RCVDBDI_BD_PROD_IDX_12 0x000024b0
806 #define RCVDBDI_BD_PROD_IDX_13 0x000024b4
807 #define RCVDBDI_BD_PROD_IDX_14 0x000024b8
808 #define RCVDBDI_BD_PROD_IDX_15 0x000024bc
809 #define RCVDBDI_HWDIAG 0x000024c0
810 /* 0x24c4 --> 0x2800 unused */
812 /* Receive Data Completion Control */
813 #define RCVDCC_MODE 0x00002800
814 #define RCVDCC_MODE_RESET 0x00000001
815 #define RCVDCC_MODE_ENABLE 0x00000002
816 #define RCVDCC_MODE_ATTN_ENABLE 0x00000004
817 /* 0x2804 --> 0x2c00 unused */
819 /* Receive BD Initiator Control Registers */
820 #define RCVBDI_MODE 0x00002c00
821 #define RCVBDI_MODE_RESET 0x00000001
822 #define RCVBDI_MODE_ENABLE 0x00000002
823 #define RCVBDI_MODE_RCB_ATTN_ENAB 0x00000004
824 #define RCVBDI_STATUS 0x00002c04
825 #define RCVBDI_STATUS_RCB_ATTN 0x00000004
826 #define RCVBDI_JUMBO_PROD_IDX 0x00002c08
827 #define RCVBDI_STD_PROD_IDX 0x00002c0c
828 #define RCVBDI_MINI_PROD_IDX 0x00002c10
829 #define RCVBDI_MINI_THRESH 0x00002c14
830 #define RCVBDI_STD_THRESH 0x00002c18
831 #define RCVBDI_JUMBO_THRESH 0x00002c1c
832 /* 0x2c20 --> 0x3000 unused */
834 /* Receive BD Completion Control Registers */
835 #define RCVCC_MODE 0x00003000
836 #define RCVCC_MODE_RESET 0x00000001
837 #define RCVCC_MODE_ENABLE 0x00000002
838 #define RCVCC_MODE_ATTN_ENABLE 0x00000004
839 #define RCVCC_STATUS 0x00003004
840 #define RCVCC_STATUS_ERROR_ATTN 0x00000004
841 #define RCVCC_JUMP_PROD_IDX 0x00003008
842 #define RCVCC_STD_PROD_IDX 0x0000300c
843 #define RCVCC_MINI_PROD_IDX 0x00003010
844 /* 0x3014 --> 0x3400 unused */
846 /* Receive list selector control registers */
847 #define RCVLSC_MODE 0x00003400
848 #define RCVLSC_MODE_RESET 0x00000001
849 #define RCVLSC_MODE_ENABLE 0x00000002
850 #define RCVLSC_MODE_ATTN_ENABLE 0x00000004
851 #define RCVLSC_STATUS 0x00003404
852 #define RCVLSC_STATUS_ERROR_ATTN 0x00000004
853 /* 0x3408 --> 0x3600 unused */
856 #define TG3_CPMU_CTRL 0x00003600
857 #define CPMU_CTRL_LINK_IDLE_MODE 0x00000200
858 #define CPMU_CTRL_LINK_AWARE_MODE 0x00000400
859 #define CPMU_CTRL_LINK_SPEED_MODE 0x00004000
860 #define TG3_CPMU_LSPD_10MB_CLK 0x00003604
861 #define CPMU_LSPD_10MB_MACCLK_MASK 0x001f0000
862 #define CPMU_LSPD_10MB_MACCLK_6_25 0x00130000
863 /* 0x3608 --> 0x360c unused */
865 #define TG3_CPMU_LSPD_1000MB_CLK 0x0000360c
866 #define CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000
867 #define CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000
868 #define CPMU_LSPD_1000MB_MACCLK_MASK 0x001f0000
869 #define TG3_CPMU_LNK_AWARE_PWRMD 0x00003610
870 #define CPMU_LNK_AWARE_MACCLK_MASK 0x001f0000
871 #define CPMU_LNK_AWARE_MACCLK_6_25 0x00130000
872 /* 0x3614 --> 0x361c unused */
874 #define TG3_CPMU_HST_ACC 0x0000361c
875 #define CPMU_HST_ACC_MACCLK_MASK 0x001f0000
876 #define CPMU_HST_ACC_MACCLK_6_25 0x00130000
877 /* 0x3620 --> 0x365c unused */
879 #define TG3_CPMU_MUTEX_REQ 0x0000365c
880 #define CPMU_MUTEX_REQ_DRIVER 0x00001000
881 #define TG3_CPMU_MUTEX_GNT 0x00003660
882 #define CPMU_MUTEX_GNT_DRIVER 0x00001000
883 /* 0x3664 --> 0x3800 unused */
885 /* Mbuf cluster free registers */
886 #define MBFREE_MODE 0x00003800
887 #define MBFREE_MODE_RESET 0x00000001
888 #define MBFREE_MODE_ENABLE 0x00000002
889 #define MBFREE_STATUS 0x00003804
890 /* 0x3808 --> 0x3c00 unused */
892 /* Host coalescing control registers */
893 #define HOSTCC_MODE 0x00003c00
894 #define HOSTCC_MODE_RESET 0x00000001
895 #define HOSTCC_MODE_ENABLE 0x00000002
896 #define HOSTCC_MODE_ATTN 0x00000004
897 #define HOSTCC_MODE_NOW 0x00000008
898 #define HOSTCC_MODE_FULL_STATUS 0x00000000
899 #define HOSTCC_MODE_64BYTE 0x00000080
900 #define HOSTCC_MODE_32BYTE 0x00000100
901 #define HOSTCC_MODE_CLRTICK_RXBD 0x00000200
902 #define HOSTCC_MODE_CLRTICK_TXBD 0x00000400
903 #define HOSTCC_MODE_NOINT_ON_NOW 0x00000800
904 #define HOSTCC_MODE_NOINT_ON_FORCE 0x00001000
905 #define HOSTCC_STATUS 0x00003c04
906 #define HOSTCC_STATUS_ERROR_ATTN 0x00000004
907 #define HOSTCC_RXCOL_TICKS 0x00003c08
908 #define LOW_RXCOL_TICKS 0x00000032
909 #define LOW_RXCOL_TICKS_CLRTCKS 0x00000014
910 #define DEFAULT_RXCOL_TICKS 0x00000048
911 #define HIGH_RXCOL_TICKS 0x00000096
912 #define MAX_RXCOL_TICKS 0x000003ff
913 #define HOSTCC_TXCOL_TICKS 0x00003c0c
914 #define LOW_TXCOL_TICKS 0x00000096
915 #define LOW_TXCOL_TICKS_CLRTCKS 0x00000048
916 #define DEFAULT_TXCOL_TICKS 0x0000012c
917 #define HIGH_TXCOL_TICKS 0x00000145
918 #define MAX_TXCOL_TICKS 0x000003ff
919 #define HOSTCC_RXMAX_FRAMES 0x00003c10
920 #define LOW_RXMAX_FRAMES 0x00000005
921 #define DEFAULT_RXMAX_FRAMES 0x00000008
922 #define HIGH_RXMAX_FRAMES 0x00000012
923 #define MAX_RXMAX_FRAMES 0x000000ff
924 #define HOSTCC_TXMAX_FRAMES 0x00003c14
925 #define LOW_TXMAX_FRAMES 0x00000035
926 #define DEFAULT_TXMAX_FRAMES 0x0000004b
927 #define HIGH_TXMAX_FRAMES 0x00000052
928 #define MAX_TXMAX_FRAMES 0x000000ff
929 #define HOSTCC_RXCOAL_TICK_INT 0x00003c18
930 #define DEFAULT_RXCOAL_TICK_INT 0x00000019
931 #define DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014
932 #define MAX_RXCOAL_TICK_INT 0x000003ff
933 #define HOSTCC_TXCOAL_TICK_INT 0x00003c1c
934 #define DEFAULT_TXCOAL_TICK_INT 0x00000019
935 #define DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014
936 #define MAX_TXCOAL_TICK_INT 0x000003ff
937 #define HOSTCC_RXCOAL_MAXF_INT 0x00003c20
938 #define DEFAULT_RXCOAL_MAXF_INT 0x00000005
939 #define MAX_RXCOAL_MAXF_INT 0x000000ff
940 #define HOSTCC_TXCOAL_MAXF_INT 0x00003c24
941 #define DEFAULT_TXCOAL_MAXF_INT 0x00000005
942 #define MAX_TXCOAL_MAXF_INT 0x000000ff
943 #define HOSTCC_STAT_COAL_TICKS 0x00003c28
944 #define DEFAULT_STAT_COAL_TICKS 0x000f4240
945 #define MAX_STAT_COAL_TICKS 0xd693d400
946 #define MIN_STAT_COAL_TICKS 0x00000064
947 /* 0x3c2c --> 0x3c30 unused */
948 #define HOSTCC_STATS_BLK_HOST_ADDR 0x00003c30 /* 64-bit */
949 #define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */
950 #define HOSTCC_STATS_BLK_NIC_ADDR 0x00003c40
951 #define HOSTCC_STATUS_BLK_NIC_ADDR 0x00003c44
952 #define HOSTCC_FLOW_ATTN 0x00003c48
953 /* 0x3c4c --> 0x3c50 unused */
954 #define HOSTCC_JUMBO_CON_IDX 0x00003c50
955 #define HOSTCC_STD_CON_IDX 0x00003c54
956 #define HOSTCC_MINI_CON_IDX 0x00003c58
957 /* 0x3c5c --> 0x3c80 unused */
958 #define HOSTCC_RET_PROD_IDX_0 0x00003c80
959 #define HOSTCC_RET_PROD_IDX_1 0x00003c84
960 #define HOSTCC_RET_PROD_IDX_2 0x00003c88
961 #define HOSTCC_RET_PROD_IDX_3 0x00003c8c
962 #define HOSTCC_RET_PROD_IDX_4 0x00003c90
963 #define HOSTCC_RET_PROD_IDX_5 0x00003c94
964 #define HOSTCC_RET_PROD_IDX_6 0x00003c98
965 #define HOSTCC_RET_PROD_IDX_7 0x00003c9c
966 #define HOSTCC_RET_PROD_IDX_8 0x00003ca0
967 #define HOSTCC_RET_PROD_IDX_9 0x00003ca4
968 #define HOSTCC_RET_PROD_IDX_10 0x00003ca8
969 #define HOSTCC_RET_PROD_IDX_11 0x00003cac
970 #define HOSTCC_RET_PROD_IDX_12 0x00003cb0
971 #define HOSTCC_RET_PROD_IDX_13 0x00003cb4
972 #define HOSTCC_RET_PROD_IDX_14 0x00003cb8
973 #define HOSTCC_RET_PROD_IDX_15 0x00003cbc
974 #define HOSTCC_SND_CON_IDX_0 0x00003cc0
975 #define HOSTCC_SND_CON_IDX_1 0x00003cc4
976 #define HOSTCC_SND_CON_IDX_2 0x00003cc8
977 #define HOSTCC_SND_CON_IDX_3 0x00003ccc
978 #define HOSTCC_SND_CON_IDX_4 0x00003cd0
979 #define HOSTCC_SND_CON_IDX_5 0x00003cd4
980 #define HOSTCC_SND_CON_IDX_6 0x00003cd8
981 #define HOSTCC_SND_CON_IDX_7 0x00003cdc
982 #define HOSTCC_SND_CON_IDX_8 0x00003ce0
983 #define HOSTCC_SND_CON_IDX_9 0x00003ce4
984 #define HOSTCC_SND_CON_IDX_10 0x00003ce8
985 #define HOSTCC_SND_CON_IDX_11 0x00003cec
986 #define HOSTCC_SND_CON_IDX_12 0x00003cf0
987 #define HOSTCC_SND_CON_IDX_13 0x00003cf4
988 #define HOSTCC_SND_CON_IDX_14 0x00003cf8
989 #define HOSTCC_SND_CON_IDX_15 0x00003cfc
990 /* 0x3d00 --> 0x4000 unused */
992 /* Memory arbiter control registers */
993 #define MEMARB_MODE 0x00004000
994 #define MEMARB_MODE_RESET 0x00000001
995 #define MEMARB_MODE_ENABLE 0x00000002
996 #define MEMARB_STATUS 0x00004004
997 #define MEMARB_TRAP_ADDR_LOW 0x00004008
998 #define MEMARB_TRAP_ADDR_HIGH 0x0000400c
999 /* 0x4010 --> 0x4400 unused */
1001 /* Buffer manager control registers */
1002 #define BUFMGR_MODE 0x00004400
1003 #define BUFMGR_MODE_RESET 0x00000001
1004 #define BUFMGR_MODE_ENABLE 0x00000002
1005 #define BUFMGR_MODE_ATTN_ENABLE 0x00000004
1006 #define BUFMGR_MODE_BM_TEST 0x00000008
1007 #define BUFMGR_MODE_MBLOW_ATTN_ENAB 0x00000010
1008 #define BUFMGR_STATUS 0x00004404
1009 #define BUFMGR_STATUS_ERROR 0x00000004
1010 #define BUFMGR_STATUS_MBLOW 0x00000010
1011 #define BUFMGR_MB_POOL_ADDR 0x00004408
1012 #define BUFMGR_MB_POOL_SIZE 0x0000440c
1013 #define BUFMGR_MB_RDMA_LOW_WATER 0x00004410
1014 #define DEFAULT_MB_RDMA_LOW_WATER 0x00000050
1015 #define DEFAULT_MB_RDMA_LOW_WATER_5705 0x00000000
1016 #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130
1017 #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 0x00000000
1018 #define BUFMGR_MB_MACRX_LOW_WATER 0x00004414
1019 #define DEFAULT_MB_MACRX_LOW_WATER 0x00000020
1020 #define DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010
1021 #define DEFAULT_MB_MACRX_LOW_WATER_5906 0x00000004
1022 #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
1023 #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b
1024 #define BUFMGR_MB_HIGH_WATER 0x00004418
1025 #define DEFAULT_MB_HIGH_WATER 0x00000060
1026 #define DEFAULT_MB_HIGH_WATER_5705 0x00000060
1027 #define DEFAULT_MB_HIGH_WATER_5906 0x00000010
1028 #define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c
1029 #define DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096
1030 #define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c
1031 #define BUFMGR_MB_ALLOC_BIT 0x10000000
1032 #define BUFMGR_RX_MB_ALLOC_RESP 0x00004420
1033 #define BUFMGR_TX_MB_ALLOC_REQ 0x00004424
1034 #define BUFMGR_TX_MB_ALLOC_RESP 0x00004428
1035 #define BUFMGR_DMA_DESC_POOL_ADDR 0x0000442c
1036 #define BUFMGR_DMA_DESC_POOL_SIZE 0x00004430
1037 #define BUFMGR_DMA_LOW_WATER 0x00004434
1038 #define DEFAULT_DMA_LOW_WATER 0x00000005
1039 #define BUFMGR_DMA_HIGH_WATER 0x00004438
1040 #define DEFAULT_DMA_HIGH_WATER 0x0000000a
1041 #define BUFMGR_RX_DMA_ALLOC_REQ 0x0000443c
1042 #define BUFMGR_RX_DMA_ALLOC_RESP 0x00004440
1043 #define BUFMGR_TX_DMA_ALLOC_REQ 0x00004444
1044 #define BUFMGR_TX_DMA_ALLOC_RESP 0x00004448
1045 #define BUFMGR_HWDIAG_0 0x0000444c
1046 #define BUFMGR_HWDIAG_1 0x00004450
1047 #define BUFMGR_HWDIAG_2 0x00004454
1048 /* 0x4458 --> 0x4800 unused */
1050 /* Read DMA control registers */
1051 #define RDMAC_MODE 0x00004800
1052 #define RDMAC_MODE_RESET 0x00000001
1053 #define RDMAC_MODE_ENABLE 0x00000002
1054 #define RDMAC_MODE_TGTABORT_ENAB 0x00000004
1055 #define RDMAC_MODE_MSTABORT_ENAB 0x00000008
1056 #define RDMAC_MODE_PARITYERR_ENAB 0x00000010
1057 #define RDMAC_MODE_ADDROFLOW_ENAB 0x00000020
1058 #define RDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
1059 #define RDMAC_MODE_FIFOURUN_ENAB 0x00000080
1060 #define RDMAC_MODE_FIFOOREAD_ENAB 0x00000100
1061 #define RDMAC_MODE_LNGREAD_ENAB 0x00000200
1062 #define RDMAC_MODE_SPLIT_ENABLE 0x00000800
1063 #define RDMAC_MODE_BD_SBD_CRPT_ENAB 0x00000800
1064 #define RDMAC_MODE_SPLIT_RESET 0x00001000
1065 #define RDMAC_MODE_MBUF_RBD_CRPT_ENAB 0x00001000
1066 #define RDMAC_MODE_MBUF_SBD_CRPT_ENAB 0x00002000
1067 #define RDMAC_MODE_FIFO_SIZE_128 0x00020000
1068 #define RDMAC_MODE_FIFO_LONG_BURST 0x00030000
1069 #define RDMAC_STATUS 0x00004804
1070 #define RDMAC_STATUS_TGTABORT 0x00000004
1071 #define RDMAC_STATUS_MSTABORT 0x00000008
1072 #define RDMAC_STATUS_PARITYERR 0x00000010
1073 #define RDMAC_STATUS_ADDROFLOW 0x00000020
1074 #define RDMAC_STATUS_FIFOOFLOW 0x00000040
1075 #define RDMAC_STATUS_FIFOURUN 0x00000080
1076 #define RDMAC_STATUS_FIFOOREAD 0x00000100
1077 #define RDMAC_STATUS_LNGREAD 0x00000200
1078 /* 0x4808 --> 0x4c00 unused */
1080 /* Write DMA control registers */
1081 #define WDMAC_MODE 0x00004c00
1082 #define WDMAC_MODE_RESET 0x00000001
1083 #define WDMAC_MODE_ENABLE 0x00000002
1084 #define WDMAC_MODE_TGTABORT_ENAB 0x00000004
1085 #define WDMAC_MODE_MSTABORT_ENAB 0x00000008
1086 #define WDMAC_MODE_PARITYERR_ENAB 0x00000010
1087 #define WDMAC_MODE_ADDROFLOW_ENAB 0x00000020
1088 #define WDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
1089 #define WDMAC_MODE_FIFOURUN_ENAB 0x00000080
1090 #define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100
1091 #define WDMAC_MODE_LNGREAD_ENAB 0x00000200
1092 #define WDMAC_MODE_RX_ACCEL 0x00000400
1093 #define WDMAC_STATUS 0x00004c04
1094 #define WDMAC_STATUS_TGTABORT 0x00000004
1095 #define WDMAC_STATUS_MSTABORT 0x00000008
1096 #define WDMAC_STATUS_PARITYERR 0x00000010
1097 #define WDMAC_STATUS_ADDROFLOW 0x00000020
1098 #define WDMAC_STATUS_FIFOOFLOW 0x00000040
1099 #define WDMAC_STATUS_FIFOURUN 0x00000080
1100 #define WDMAC_STATUS_FIFOOREAD 0x00000100
1101 #define WDMAC_STATUS_LNGREAD 0x00000200
1102 /* 0x4c08 --> 0x5000 unused */
1104 /* Per-cpu register offsets (arm9) */
1105 #define CPU_MODE 0x00000000
1106 #define CPU_MODE_RESET 0x00000001
1107 #define CPU_MODE_HALT 0x00000400
1108 #define CPU_STATE 0x00000004
1109 #define CPU_EVTMASK 0x00000008
1110 /* 0xc --> 0x1c reserved */
1111 #define CPU_PC 0x0000001c
1112 #define CPU_INSN 0x00000020
1113 #define CPU_SPAD_UFLOW 0x00000024
1114 #define CPU_WDOG_CLEAR 0x00000028
1115 #define CPU_WDOG_VECTOR 0x0000002c
1116 #define CPU_WDOG_PC 0x00000030
1117 #define CPU_HW_BP 0x00000034
1118 /* 0x38 --> 0x44 unused */
1119 #define CPU_WDOG_SAVED_STATE 0x00000044
1120 #define CPU_LAST_BRANCH_ADDR 0x00000048
1121 #define CPU_SPAD_UFLOW_SET 0x0000004c
1122 /* 0x50 --> 0x200 unused */
1123 #define CPU_R0 0x00000200
1124 #define CPU_R1 0x00000204
1125 #define CPU_R2 0x00000208
1126 #define CPU_R3 0x0000020c
1127 #define CPU_R4 0x00000210
1128 #define CPU_R5 0x00000214
1129 #define CPU_R6 0x00000218
1130 #define CPU_R7 0x0000021c
1131 #define CPU_R8 0x00000220
1132 #define CPU_R9 0x00000224
1133 #define CPU_R10 0x00000228
1134 #define CPU_R11 0x0000022c
1135 #define CPU_R12 0x00000230
1136 #define CPU_R13 0x00000234
1137 #define CPU_R14 0x00000238
1138 #define CPU_R15 0x0000023c
1139 #define CPU_R16 0x00000240
1140 #define CPU_R17 0x00000244
1141 #define CPU_R18 0x00000248
1142 #define CPU_R19 0x0000024c
1143 #define CPU_R20 0x00000250
1144 #define CPU_R21 0x00000254
1145 #define CPU_R22 0x00000258
1146 #define CPU_R23 0x0000025c
1147 #define CPU_R24 0x00000260
1148 #define CPU_R25 0x00000264
1149 #define CPU_R26 0x00000268
1150 #define CPU_R27 0x0000026c
1151 #define CPU_R28 0x00000270
1152 #define CPU_R29 0x00000274
1153 #define CPU_R30 0x00000278
1154 #define CPU_R31 0x0000027c
1155 /* 0x280 --> 0x400 unused */
1157 #define RX_CPU_BASE 0x00005000
1158 #define RX_CPU_MODE 0x00005000
1159 #define RX_CPU_STATE 0x00005004
1160 #define RX_CPU_PGMCTR 0x0000501c
1161 #define RX_CPU_HWBKPT 0x00005034
1162 #define TX_CPU_BASE 0x00005400
1163 #define TX_CPU_MODE 0x00005400
1164 #define TX_CPU_STATE 0x00005404
1165 #define TX_CPU_PGMCTR 0x0000541c
1167 #define VCPU_STATUS 0x00005100
1168 #define VCPU_STATUS_INIT_DONE 0x04000000
1169 #define VCPU_STATUS_DRV_RESET 0x08000000
1171 #define VCPU_CFGSHDW 0x00005104
1172 #define VCPU_CFGSHDW_WOL_ENABLE 0x00000001
1173 #define VCPU_CFGSHDW_WOL_MAGPKT 0x00000004
1174 #define VCPU_CFGSHDW_ASPM_DBNC 0x00001000
1177 #define GRCMBOX_BASE 0x00005600
1178 #define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */
1179 #define GRCMBOX_INTERRUPT_1 0x00005808 /* 64-bit */
1180 #define GRCMBOX_INTERRUPT_2 0x00005810 /* 64-bit */
1181 #define GRCMBOX_INTERRUPT_3 0x00005818 /* 64-bit */
1182 #define GRCMBOX_GENERAL_0 0x00005820 /* 64-bit */
1183 #define GRCMBOX_GENERAL_1 0x00005828 /* 64-bit */
1184 #define GRCMBOX_GENERAL_2 0x00005830 /* 64-bit */
1185 #define GRCMBOX_GENERAL_3 0x00005838 /* 64-bit */
1186 #define GRCMBOX_GENERAL_4 0x00005840 /* 64-bit */
1187 #define GRCMBOX_GENERAL_5 0x00005848 /* 64-bit */
1188 #define GRCMBOX_GENERAL_6 0x00005850 /* 64-bit */
1189 #define GRCMBOX_GENERAL_7 0x00005858 /* 64-bit */
1190 #define GRCMBOX_RELOAD_STAT 0x00005860 /* 64-bit */
1191 #define GRCMBOX_RCVSTD_PROD_IDX 0x00005868 /* 64-bit */
1192 #define GRCMBOX_RCVJUMBO_PROD_IDX 0x00005870 /* 64-bit */
1193 #define GRCMBOX_RCVMINI_PROD_IDX 0x00005878 /* 64-bit */
1194 #define GRCMBOX_RCVRET_CON_IDX_0 0x00005880 /* 64-bit */
1195 #define GRCMBOX_RCVRET_CON_IDX_1 0x00005888 /* 64-bit */
1196 #define GRCMBOX_RCVRET_CON_IDX_2 0x00005890 /* 64-bit */
1197 #define GRCMBOX_RCVRET_CON_IDX_3 0x00005898 /* 64-bit */
1198 #define GRCMBOX_RCVRET_CON_IDX_4 0x000058a0 /* 64-bit */
1199 #define GRCMBOX_RCVRET_CON_IDX_5 0x000058a8 /* 64-bit */
1200 #define GRCMBOX_RCVRET_CON_IDX_6 0x000058b0 /* 64-bit */
1201 #define GRCMBOX_RCVRET_CON_IDX_7 0x000058b8 /* 64-bit */
1202 #define GRCMBOX_RCVRET_CON_IDX_8 0x000058c0 /* 64-bit */
1203 #define GRCMBOX_RCVRET_CON_IDX_9 0x000058c8 /* 64-bit */
1204 #define GRCMBOX_RCVRET_CON_IDX_10 0x000058d0 /* 64-bit */
1205 #define GRCMBOX_RCVRET_CON_IDX_11 0x000058d8 /* 64-bit */
1206 #define GRCMBOX_RCVRET_CON_IDX_12 0x000058e0 /* 64-bit */
1207 #define GRCMBOX_RCVRET_CON_IDX_13 0x000058e8 /* 64-bit */
1208 #define GRCMBOX_RCVRET_CON_IDX_14 0x000058f0 /* 64-bit */
1209 #define GRCMBOX_RCVRET_CON_IDX_15 0x000058f8 /* 64-bit */
1210 #define GRCMBOX_SNDHOST_PROD_IDX_0 0x00005900 /* 64-bit */
1211 #define GRCMBOX_SNDHOST_PROD_IDX_1 0x00005908 /* 64-bit */
1212 #define GRCMBOX_SNDHOST_PROD_IDX_2 0x00005910 /* 64-bit */
1213 #define GRCMBOX_SNDHOST_PROD_IDX_3 0x00005918 /* 64-bit */
1214 #define GRCMBOX_SNDHOST_PROD_IDX_4 0x00005920 /* 64-bit */
1215 #define GRCMBOX_SNDHOST_PROD_IDX_5 0x00005928 /* 64-bit */
1216 #define GRCMBOX_SNDHOST_PROD_IDX_6 0x00005930 /* 64-bit */
1217 #define GRCMBOX_SNDHOST_PROD_IDX_7 0x00005938 /* 64-bit */
1218 #define GRCMBOX_SNDHOST_PROD_IDX_8 0x00005940 /* 64-bit */
1219 #define GRCMBOX_SNDHOST_PROD_IDX_9 0x00005948 /* 64-bit */
1220 #define GRCMBOX_SNDHOST_PROD_IDX_10 0x00005950 /* 64-bit */
1221 #define GRCMBOX_SNDHOST_PROD_IDX_11 0x00005958 /* 64-bit */
1222 #define GRCMBOX_SNDHOST_PROD_IDX_12 0x00005960 /* 64-bit */
1223 #define GRCMBOX_SNDHOST_PROD_IDX_13 0x00005968 /* 64-bit */
1224 #define GRCMBOX_SNDHOST_PROD_IDX_14 0x00005970 /* 64-bit */
1225 #define GRCMBOX_SNDHOST_PROD_IDX_15 0x00005978 /* 64-bit */
1226 #define GRCMBOX_SNDNIC_PROD_IDX_0 0x00005980 /* 64-bit */
1227 #define GRCMBOX_SNDNIC_PROD_IDX_1 0x00005988 /* 64-bit */
1228 #define GRCMBOX_SNDNIC_PROD_IDX_2 0x00005990 /* 64-bit */
1229 #define GRCMBOX_SNDNIC_PROD_IDX_3 0x00005998 /* 64-bit */
1230 #define GRCMBOX_SNDNIC_PROD_IDX_4 0x000059a0 /* 64-bit */
1231 #define GRCMBOX_SNDNIC_PROD_IDX_5 0x000059a8 /* 64-bit */
1232 #define GRCMBOX_SNDNIC_PROD_IDX_6 0x000059b0 /* 64-bit */
1233 #define GRCMBOX_SNDNIC_PROD_IDX_7 0x000059b8 /* 64-bit */
1234 #define GRCMBOX_SNDNIC_PROD_IDX_8 0x000059c0 /* 64-bit */
1235 #define GRCMBOX_SNDNIC_PROD_IDX_9 0x000059c8 /* 64-bit */
1236 #define GRCMBOX_SNDNIC_PROD_IDX_10 0x000059d0 /* 64-bit */
1237 #define GRCMBOX_SNDNIC_PROD_IDX_11 0x000059d8 /* 64-bit */
1238 #define GRCMBOX_SNDNIC_PROD_IDX_12 0x000059e0 /* 64-bit */
1239 #define GRCMBOX_SNDNIC_PROD_IDX_13 0x000059e8 /* 64-bit */
1240 #define GRCMBOX_SNDNIC_PROD_IDX_14 0x000059f0 /* 64-bit */
1241 #define GRCMBOX_SNDNIC_PROD_IDX_15 0x000059f8 /* 64-bit */
1242 #define GRCMBOX_HIGH_PRIO_EV_VECTOR 0x00005a00
1243 #define GRCMBOX_HIGH_PRIO_EV_MASK 0x00005a04
1244 #define GRCMBOX_LOW_PRIO_EV_VEC 0x00005a08
1245 #define GRCMBOX_LOW_PRIO_EV_MASK 0x00005a0c
1246 /* 0x5a10 --> 0x5c00 */
1248 /* Flow Through queues */
1249 #define FTQ_RESET 0x00005c00
1250 /* 0x5c04 --> 0x5c10 unused */
1251 #define FTQ_DMA_NORM_READ_CTL 0x00005c10
1252 #define FTQ_DMA_NORM_READ_FULL_CNT 0x00005c14
1253 #define FTQ_DMA_NORM_READ_FIFO_ENQDEQ 0x00005c18
1254 #define FTQ_DMA_NORM_READ_WRITE_PEEK 0x00005c1c
1255 #define FTQ_DMA_HIGH_READ_CTL 0x00005c20
1256 #define FTQ_DMA_HIGH_READ_FULL_CNT 0x00005c24
1257 #define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ 0x00005c28
1258 #define FTQ_DMA_HIGH_READ_WRITE_PEEK 0x00005c2c
1259 #define FTQ_DMA_COMP_DISC_CTL 0x00005c30
1260 #define FTQ_DMA_COMP_DISC_FULL_CNT 0x00005c34
1261 #define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ 0x00005c38
1262 #define FTQ_DMA_COMP_DISC_WRITE_PEEK 0x00005c3c
1263 #define FTQ_SEND_BD_COMP_CTL 0x00005c40
1264 #define FTQ_SEND_BD_COMP_FULL_CNT 0x00005c44
1265 #define FTQ_SEND_BD_COMP_FIFO_ENQDEQ 0x00005c48
1266 #define FTQ_SEND_BD_COMP_WRITE_PEEK 0x00005c4c
1267 #define FTQ_SEND_DATA_INIT_CTL 0x00005c50
1268 #define FTQ_SEND_DATA_INIT_FULL_CNT 0x00005c54
1269 #define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ 0x00005c58
1270 #define FTQ_SEND_DATA_INIT_WRITE_PEEK 0x00005c5c
1271 #define FTQ_DMA_NORM_WRITE_CTL 0x00005c60
1272 #define FTQ_DMA_NORM_WRITE_FULL_CNT 0x00005c64
1273 #define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ 0x00005c68
1274 #define FTQ_DMA_NORM_WRITE_WRITE_PEEK 0x00005c6c
1275 #define FTQ_DMA_HIGH_WRITE_CTL 0x00005c70
1276 #define FTQ_DMA_HIGH_WRITE_FULL_CNT 0x00005c74
1277 #define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ 0x00005c78
1278 #define FTQ_DMA_HIGH_WRITE_WRITE_PEEK 0x00005c7c
1279 #define FTQ_SWTYPE1_CTL 0x00005c80
1280 #define FTQ_SWTYPE1_FULL_CNT 0x00005c84
1281 #define FTQ_SWTYPE1_FIFO_ENQDEQ 0x00005c88
1282 #define FTQ_SWTYPE1_WRITE_PEEK 0x00005c8c
1283 #define FTQ_SEND_DATA_COMP_CTL 0x00005c90
1284 #define FTQ_SEND_DATA_COMP_FULL_CNT 0x00005c94
1285 #define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ 0x00005c98
1286 #define FTQ_SEND_DATA_COMP_WRITE_PEEK 0x00005c9c
1287 #define FTQ_HOST_COAL_CTL 0x00005ca0
1288 #define FTQ_HOST_COAL_FULL_CNT 0x00005ca4
1289 #define FTQ_HOST_COAL_FIFO_ENQDEQ 0x00005ca8
1290 #define FTQ_HOST_COAL_WRITE_PEEK 0x00005cac
1291 #define FTQ_MAC_TX_CTL 0x00005cb0
1292 #define FTQ_MAC_TX_FULL_CNT 0x00005cb4
1293 #define FTQ_MAC_TX_FIFO_ENQDEQ 0x00005cb8
1294 #define FTQ_MAC_TX_WRITE_PEEK 0x00005cbc
1295 #define FTQ_MB_FREE_CTL 0x00005cc0
1296 #define FTQ_MB_FREE_FULL_CNT 0x00005cc4
1297 #define FTQ_MB_FREE_FIFO_ENQDEQ 0x00005cc8
1298 #define FTQ_MB_FREE_WRITE_PEEK 0x00005ccc
1299 #define FTQ_RCVBD_COMP_CTL 0x00005cd0
1300 #define FTQ_RCVBD_COMP_FULL_CNT 0x00005cd4
1301 #define FTQ_RCVBD_COMP_FIFO_ENQDEQ 0x00005cd8
1302 #define FTQ_RCVBD_COMP_WRITE_PEEK 0x00005cdc
1303 #define FTQ_RCVLST_PLMT_CTL 0x00005ce0
1304 #define FTQ_RCVLST_PLMT_FULL_CNT 0x00005ce4
1305 #define FTQ_RCVLST_PLMT_FIFO_ENQDEQ 0x00005ce8
1306 #define FTQ_RCVLST_PLMT_WRITE_PEEK 0x00005cec
1307 #define FTQ_RCVDATA_INI_CTL 0x00005cf0
1308 #define FTQ_RCVDATA_INI_FULL_CNT 0x00005cf4
1309 #define FTQ_RCVDATA_INI_FIFO_ENQDEQ 0x00005cf8
1310 #define FTQ_RCVDATA_INI_WRITE_PEEK 0x00005cfc
1311 #define FTQ_RCVDATA_COMP_CTL 0x00005d00
1312 #define FTQ_RCVDATA_COMP_FULL_CNT 0x00005d04
1313 #define FTQ_RCVDATA_COMP_FIFO_ENQDEQ 0x00005d08
1314 #define FTQ_RCVDATA_COMP_WRITE_PEEK 0x00005d0c
1315 #define FTQ_SWTYPE2_CTL 0x00005d10
1316 #define FTQ_SWTYPE2_FULL_CNT 0x00005d14
1317 #define FTQ_SWTYPE2_FIFO_ENQDEQ 0x00005d18
1318 #define FTQ_SWTYPE2_WRITE_PEEK 0x00005d1c
1319 /* 0x5d20 --> 0x6000 unused */
1321 /* Message signaled interrupt registers */
1322 #define MSGINT_MODE 0x00006000
1323 #define MSGINT_MODE_RESET 0x00000001
1324 #define MSGINT_MODE_ENABLE 0x00000002
1325 #define MSGINT_STATUS 0x00006004
1326 #define MSGINT_FIFO 0x00006008
1327 /* 0x600c --> 0x6400 unused */
1329 /* DMA completion registers */
1330 #define DMAC_MODE 0x00006400
1331 #define DMAC_MODE_RESET 0x00000001
1332 #define DMAC_MODE_ENABLE 0x00000002
1333 /* 0x6404 --> 0x6800 unused */
1336 #define GRC_MODE 0x00006800
1337 #define GRC_MODE_UPD_ON_COAL 0x00000001
1338 #define GRC_MODE_BSWAP_NONFRM_DATA 0x00000002
1339 #define GRC_MODE_WSWAP_NONFRM_DATA 0x00000004
1340 #define GRC_MODE_BSWAP_DATA 0x00000010
1341 #define GRC_MODE_WSWAP_DATA 0x00000020
1342 #define GRC_MODE_SPLITHDR 0x00000100
1343 #define GRC_MODE_NOFRM_CRACKING 0x00000200
1344 #define GRC_MODE_INCL_CRC 0x00000400
1345 #define GRC_MODE_ALLOW_BAD_FRMS 0x00000800
1346 #define GRC_MODE_NOIRQ_ON_SENDS 0x00002000
1347 #define GRC_MODE_NOIRQ_ON_RCV 0x00004000
1348 #define GRC_MODE_FORCE_PCI32BIT 0x00008000
1349 #define GRC_MODE_HOST_STACKUP 0x00010000
1350 #define GRC_MODE_HOST_SENDBDS 0x00020000
1351 #define GRC_MODE_NO_TX_PHDR_CSUM 0x00100000
1352 #define GRC_MODE_NVRAM_WR_ENABLE 0x00200000
1353 #define GRC_MODE_NO_RX_PHDR_CSUM 0x00800000
1354 #define GRC_MODE_IRQ_ON_TX_CPU_ATTN 0x01000000
1355 #define GRC_MODE_IRQ_ON_RX_CPU_ATTN 0x02000000
1356 #define GRC_MODE_IRQ_ON_MAC_ATTN 0x04000000
1357 #define GRC_MODE_IRQ_ON_DMA_ATTN 0x08000000
1358 #define GRC_MODE_IRQ_ON_FLOW_ATTN 0x10000000
1359 #define GRC_MODE_4X_NIC_SEND_RINGS 0x20000000
1360 #define GRC_MODE_MCAST_FRM_ENABLE 0x40000000
1361 #define GRC_MISC_CFG 0x00006804
1362 #define GRC_MISC_CFG_CORECLK_RESET 0x00000001
1363 #define GRC_MISC_CFG_PRESCALAR_MASK 0x000000fe
1364 #define GRC_MISC_CFG_PRESCALAR_SHIFT 1
1365 #define GRC_MISC_CFG_BOARD_ID_MASK 0x0001e000
1366 #define GRC_MISC_CFG_BOARD_ID_5700 0x0001e000
1367 #define GRC_MISC_CFG_BOARD_ID_5701 0x00000000
1368 #define GRC_MISC_CFG_BOARD_ID_5702FE 0x00004000
1369 #define GRC_MISC_CFG_BOARD_ID_5703 0x00000000
1370 #define GRC_MISC_CFG_BOARD_ID_5703S 0x00002000
1371 #define GRC_MISC_CFG_BOARD_ID_5704 0x00000000
1372 #define GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000
1373 #define GRC_MISC_CFG_BOARD_ID_5704_A2 0x00008000
1374 #define GRC_MISC_CFG_BOARD_ID_5788 0x00010000
1375 #define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000
1376 #define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000
1377 #define GRC_MISC_CFG_EPHY_IDDQ 0x00200000
1378 #define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000
1379 #define GRC_LOCAL_CTRL 0x00006808
1380 #define GRC_LCLCTRL_INT_ACTIVE 0x00000001
1381 #define GRC_LCLCTRL_CLEARINT 0x00000002
1382 #define GRC_LCLCTRL_SETINT 0x00000004
1383 #define GRC_LCLCTRL_INT_ON_ATTN 0x00000008
1384 #define GRC_LCLCTRL_GPIO_UART_SEL 0x00000010 /* 5755 only */
1385 #define GRC_LCLCTRL_USE_SIG_DETECT 0x00000010 /* 5714/5780 only */
1386 #define GRC_LCLCTRL_USE_EXT_SIG_DETECT 0x00000020 /* 5714/5780 only */
1387 #define GRC_LCLCTRL_GPIO_INPUT3 0x00000020
1388 #define GRC_LCLCTRL_GPIO_OE3 0x00000040
1389 #define GRC_LCLCTRL_GPIO_OUTPUT3 0x00000080
1390 #define GRC_LCLCTRL_GPIO_INPUT0 0x00000100
1391 #define GRC_LCLCTRL_GPIO_INPUT1 0x00000200
1392 #define GRC_LCLCTRL_GPIO_INPUT2 0x00000400
1393 #define GRC_LCLCTRL_GPIO_OE0 0x00000800
1394 #define GRC_LCLCTRL_GPIO_OE1 0x00001000
1395 #define GRC_LCLCTRL_GPIO_OE2 0x00002000
1396 #define GRC_LCLCTRL_GPIO_OUTPUT0 0x00004000
1397 #define GRC_LCLCTRL_GPIO_OUTPUT1 0x00008000
1398 #define GRC_LCLCTRL_GPIO_OUTPUT2 0x00010000
1399 #define GRC_LCLCTRL_EXTMEM_ENABLE 0x00020000
1400 #define GRC_LCLCTRL_MEMSZ_MASK 0x001c0000
1401 #define GRC_LCLCTRL_MEMSZ_256K 0x00000000
1402 #define GRC_LCLCTRL_MEMSZ_512K 0x00040000
1403 #define GRC_LCLCTRL_MEMSZ_1M 0x00080000
1404 #define GRC_LCLCTRL_MEMSZ_2M 0x000c0000
1405 #define GRC_LCLCTRL_MEMSZ_4M 0x00100000
1406 #define GRC_LCLCTRL_MEMSZ_8M 0x00140000
1407 #define GRC_LCLCTRL_MEMSZ_16M 0x00180000
1408 #define GRC_LCLCTRL_BANK_SELECT 0x00200000
1409 #define GRC_LCLCTRL_SSRAM_TYPE 0x00400000
1410 #define GRC_LCLCTRL_AUTO_SEEPROM 0x01000000
1411 #define GRC_TIMER 0x0000680c
1412 #define GRC_RX_CPU_EVENT 0x00006810
1413 #define GRC_RX_TIMER_REF 0x00006814
1414 #define GRC_RX_CPU_SEM 0x00006818
1415 #define GRC_REMOTE_RX_CPU_ATTN 0x0000681c
1416 #define GRC_TX_CPU_EVENT 0x00006820
1417 #define GRC_TX_TIMER_REF 0x00006824
1418 #define GRC_TX_CPU_SEM 0x00006828
1419 #define GRC_REMOTE_TX_CPU_ATTN 0x0000682c
1420 #define GRC_MEM_POWER_UP 0x00006830 /* 64-bit */
1421 #define GRC_EEPROM_ADDR 0x00006838
1422 #define EEPROM_ADDR_WRITE 0x00000000
1423 #define EEPROM_ADDR_READ 0x80000000
1424 #define EEPROM_ADDR_COMPLETE 0x40000000
1425 #define EEPROM_ADDR_FSM_RESET 0x20000000
1426 #define EEPROM_ADDR_DEVID_MASK 0x1c000000
1427 #define EEPROM_ADDR_DEVID_SHIFT 26
1428 #define EEPROM_ADDR_START 0x02000000
1429 #define EEPROM_ADDR_CLKPERD_SHIFT 16
1430 #define EEPROM_ADDR_ADDR_MASK 0x0000ffff
1431 #define EEPROM_ADDR_ADDR_SHIFT 0
1432 #define EEPROM_DEFAULT_CLOCK_PERIOD 0x60
1433 #define EEPROM_CHIP_SIZE (64 * 1024)
1434 #define GRC_EEPROM_DATA 0x0000683c
1435 #define GRC_EEPROM_CTRL 0x00006840
1436 #define GRC_MDI_CTRL 0x00006844
1437 #define GRC_SEEPROM_DELAY 0x00006848
1438 /* 0x684c --> 0x6890 unused */
1439 #define GRC_VCPU_EXT_CTRL 0x00006890
1440 #define GRC_VCPU_EXT_CTRL_HALT_CPU 0x00400000
1441 #define GRC_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000
1442 #define GRC_FASTBOOT_PC 0x00006894 /* 5752, 5755, 5787 */
1444 /* 0x6c00 --> 0x7000 unused */
1446 /* NVRAM Control registers */
1447 #define NVRAM_CMD 0x00007000
1448 #define NVRAM_CMD_RESET 0x00000001
1449 #define NVRAM_CMD_DONE 0x00000008
1450 #define NVRAM_CMD_GO 0x00000010
1451 #define NVRAM_CMD_WR 0x00000020
1452 #define NVRAM_CMD_RD 0x00000000
1453 #define NVRAM_CMD_ERASE 0x00000040
1454 #define NVRAM_CMD_FIRST 0x00000080
1455 #define NVRAM_CMD_LAST 0x00000100
1456 #define NVRAM_CMD_WREN 0x00010000
1457 #define NVRAM_CMD_WRDI 0x00020000
1458 #define NVRAM_STAT 0x00007004
1459 #define NVRAM_WRDATA 0x00007008
1460 #define NVRAM_ADDR 0x0000700c
1461 #define NVRAM_ADDR_MSK 0x00ffffff
1462 #define NVRAM_RDDATA 0x00007010
1463 #define NVRAM_CFG1 0x00007014
1464 #define NVRAM_CFG1_FLASHIF_ENAB 0x00000001
1465 #define NVRAM_CFG1_BUFFERED_MODE 0x00000002
1466 #define NVRAM_CFG1_PASS_THRU 0x00000004
1467 #define NVRAM_CFG1_STATUS_BITS 0x00000070
1468 #define NVRAM_CFG1_BIT_BANG 0x00000008
1469 #define NVRAM_CFG1_FLASH_SIZE 0x02000000
1470 #define NVRAM_CFG1_COMPAT_BYPASS 0x80000000
1471 #define NVRAM_CFG1_VENDOR_MASK 0x03000003
1472 #define FLASH_VENDOR_ATMEL_EEPROM 0x02000000
1473 #define FLASH_VENDOR_ATMEL_FLASH_BUFFERED 0x02000003
1474 #define FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED 0x00000003
1475 #define FLASH_VENDOR_ST 0x03000001
1476 #define FLASH_VENDOR_SAIFUN 0x01000003
1477 #define FLASH_VENDOR_SST_SMALL 0x00000001
1478 #define FLASH_VENDOR_SST_LARGE 0x02000001
1479 #define NVRAM_CFG1_5752VENDOR_MASK 0x03c00003
1480 #define FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ 0x00000000
1481 #define FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ 0x02000000
1482 #define FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED 0x02000003
1483 #define FLASH_5752VENDOR_ST_M45PE10 0x02400000
1484 #define FLASH_5752VENDOR_ST_M45PE20 0x02400002
1485 #define FLASH_5752VENDOR_ST_M45PE40 0x02400001
1486 #define FLASH_5755VENDOR_ATMEL_FLASH_1 0x03400001
1487 #define FLASH_5755VENDOR_ATMEL_FLASH_2 0x03400002
1488 #define FLASH_5755VENDOR_ATMEL_FLASH_3 0x03400000
1489 #define FLASH_5755VENDOR_ATMEL_FLASH_4 0x00000003
1490 #define FLASH_5755VENDOR_ATMEL_FLASH_5 0x02000003
1491 #define FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ 0x03c00003
1492 #define FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ 0x03c00002
1493 #define FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ 0x03000003
1494 #define FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ 0x03000002
1495 #define FLASH_5787VENDOR_MICRO_EEPROM_64KHZ 0x03000000
1496 #define FLASH_5787VENDOR_MICRO_EEPROM_376KHZ 0x02000000
1497 #define FLASH_5761VENDOR_ATMEL_MDB021D 0x00800003
1498 #define FLASH_5761VENDOR_ATMEL_MDB041D 0x00800000
1499 #define FLASH_5761VENDOR_ATMEL_MDB081D 0x00800002
1500 #define FLASH_5761VENDOR_ATMEL_MDB161D 0x00800001
1501 #define FLASH_5761VENDOR_ATMEL_ADB021D 0x00000003
1502 #define FLASH_5761VENDOR_ATMEL_ADB041D 0x00000000
1503 #define FLASH_5761VENDOR_ATMEL_ADB081D 0x00000002
1504 #define FLASH_5761VENDOR_ATMEL_ADB161D 0x00000001
1505 #define FLASH_5761VENDOR_ST_M_M45PE20 0x02800001
1506 #define FLASH_5761VENDOR_ST_M_M45PE40 0x02800000
1507 #define FLASH_5761VENDOR_ST_M_M45PE80 0x02800002
1508 #define FLASH_5761VENDOR_ST_M_M45PE16 0x02800003
1509 #define FLASH_5761VENDOR_ST_A_M45PE20 0x02000001
1510 #define FLASH_5761VENDOR_ST_A_M45PE40 0x02000000
1511 #define FLASH_5761VENDOR_ST_A_M45PE80 0x02000002
1512 #define FLASH_5761VENDOR_ST_A_M45PE16 0x02000003
1513 #define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000
1514 #define FLASH_5752PAGE_SIZE_256 0x00000000
1515 #define FLASH_5752PAGE_SIZE_512 0x10000000
1516 #define FLASH_5752PAGE_SIZE_1K 0x20000000
1517 #define FLASH_5752PAGE_SIZE_2K 0x30000000
1518 #define FLASH_5752PAGE_SIZE_4K 0x40000000
1519 #define FLASH_5752PAGE_SIZE_264 0x50000000
1520 #define NVRAM_CFG2 0x00007018
1521 #define NVRAM_CFG3 0x0000701c
1522 #define NVRAM_SWARB 0x00007020
1523 #define SWARB_REQ_SET0 0x00000001
1524 #define SWARB_REQ_SET1 0x00000002
1525 #define SWARB_REQ_SET2 0x00000004
1526 #define SWARB_REQ_SET3 0x00000008
1527 #define SWARB_REQ_CLR0 0x00000010
1528 #define SWARB_REQ_CLR1 0x00000020
1529 #define SWARB_REQ_CLR2 0x00000040
1530 #define SWARB_REQ_CLR3 0x00000080
1531 #define SWARB_GNT0 0x00000100
1532 #define SWARB_GNT1 0x00000200
1533 #define SWARB_GNT2 0x00000400
1534 #define SWARB_GNT3 0x00000800
1535 #define SWARB_REQ0 0x00001000
1536 #define SWARB_REQ1 0x00002000
1537 #define SWARB_REQ2 0x00004000
1538 #define SWARB_REQ3 0x00008000
1539 #define NVRAM_ACCESS 0x00007024
1540 #define ACCESS_ENABLE 0x00000001
1541 #define ACCESS_WR_ENABLE 0x00000002
1542 #define NVRAM_WRITE1 0x00007028
1545 #define NVRAM_ADDR_LOCKOUT 0x00007030
1546 /* 0x7034 --> 0x7c00 unused */
1548 #define PCIE_TRANSACTION_CFG 0x00007c04
1549 #define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000
1550 #define PCIE_TRANS_CFG_LOM 0x00000020
1552 #define PCIE_PWR_MGMT_THRESH 0x00007d28
1553 #define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00
1555 #define TG3_EEPROM_MAGIC 0x669955aa
1556 #define TG3_EEPROM_MAGIC_FW 0xa5000000
1557 #define TG3_EEPROM_MAGIC_FW_MSK 0xff000000
1558 #define TG3_EEPROM_MAGIC_HW 0xabcd
1559 #define TG3_EEPROM_MAGIC_HW_MSK 0xffff
1561 #define TG3_NVM_DIR_START 0x18
1562 #define TG3_NVM_DIR_END 0x78
1563 #define TG3_NVM_DIRENT_SIZE 0xc
1564 #define TG3_NVM_DIRTYPE_SHIFT 24
1565 #define TG3_NVM_DIRTYPE_ASFINI 1
1567 /* 32K Window into NIC internal memory */
1568 #define NIC_SRAM_WIN_BASE 0x00008000
1570 /* Offsets into first 32k of NIC internal memory. */
1571 #define NIC_SRAM_PAGE_ZERO 0x00000000
1572 #define NIC_SRAM_SEND_RCB 0x00000100 /* 16 * TG3_BDINFO_... */
1573 #define NIC_SRAM_RCV_RET_RCB 0x00000200 /* 16 * TG3_BDINFO_... */
1574 #define NIC_SRAM_STATS_BLK 0x00000300
1575 #define NIC_SRAM_STATUS_BLK 0x00000b00
1577 #define NIC_SRAM_FIRMWARE_MBOX 0x00000b50
1578 #define NIC_SRAM_FIRMWARE_MBOX_MAGIC1 0x4B657654
1579 #define NIC_SRAM_FIRMWARE_MBOX_MAGIC2 0x4861764b /* !dma on linkchg */
1581 #define NIC_SRAM_DATA_SIG 0x00000b54
1582 #define NIC_SRAM_DATA_SIG_MAGIC 0x4b657654 /* ascii for 'KevT' */
1584 #define NIC_SRAM_DATA_CFG 0x00000b58
1585 #define NIC_SRAM_DATA_CFG_LED_MODE_MASK 0x0000000c
1586 #define NIC_SRAM_DATA_CFG_LED_MODE_MAC 0x00000000
1587 #define NIC_SRAM_DATA_CFG_LED_MODE_PHY_1 0x00000004
1588 #define NIC_SRAM_DATA_CFG_LED_MODE_PHY_2 0x00000008
1589 #define NIC_SRAM_DATA_CFG_PHY_TYPE_MASK 0x00000030
1590 #define NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN 0x00000000
1591 #define NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER 0x00000010
1592 #define NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER 0x00000020
1593 #define NIC_SRAM_DATA_CFG_WOL_ENABLE 0x00000040
1594 #define NIC_SRAM_DATA_CFG_ASF_ENABLE 0x00000080
1595 #define NIC_SRAM_DATA_CFG_EEPROM_WP 0x00000100
1596 #define NIC_SRAM_DATA_CFG_MINI_PCI 0x00001000
1597 #define NIC_SRAM_DATA_CFG_FIBER_WOL 0x00004000
1598 #define NIC_SRAM_DATA_CFG_NO_GPIO2 0x00100000
1599 #define NIC_SRAM_DATA_CFG_APE_ENABLE 0x00200000
1601 #define NIC_SRAM_DATA_VER 0x00000b5c
1602 #define NIC_SRAM_DATA_VER_SHIFT 16
1604 #define NIC_SRAM_DATA_PHY_ID 0x00000b74
1605 #define NIC_SRAM_DATA_PHY_ID1_MASK 0xffff0000
1606 #define NIC_SRAM_DATA_PHY_ID2_MASK 0x0000ffff
1608 #define NIC_SRAM_FW_CMD_MBOX 0x00000b78
1609 #define FWCMD_NICDRV_ALIVE 0x00000001
1610 #define FWCMD_NICDRV_PAUSE_FW 0x00000002
1611 #define FWCMD_NICDRV_IPV4ADDR_CHG 0x00000003
1612 #define FWCMD_NICDRV_IPV6ADDR_CHG 0x00000004
1613 #define FWCMD_NICDRV_FIX_DMAR 0x00000005
1614 #define FWCMD_NICDRV_FIX_DMAW 0x00000006
1615 #define FWCMD_NICDRV_ALIVE2 0x0000000d
1616 #define FWCMD_NICDRV_ALIVE3 0x0000000e
1617 #define NIC_SRAM_FW_CMD_LEN_MBOX 0x00000b7c
1618 #define NIC_SRAM_FW_CMD_DATA_MBOX 0x00000b80
1619 #define NIC_SRAM_FW_ASF_STATUS_MBOX 0x00000c00
1620 #define NIC_SRAM_FW_DRV_STATE_MBOX 0x00000c04
1621 #define DRV_STATE_START 0x00000001
1622 #define DRV_STATE_START_DONE 0x80000001
1623 #define DRV_STATE_UNLOAD 0x00000002
1624 #define DRV_STATE_UNLOAD_DONE 0x80000002
1625 #define DRV_STATE_WOL 0x00000003
1626 #define DRV_STATE_SUSPEND 0x00000004
1628 #define NIC_SRAM_FW_RESET_TYPE_MBOX 0x00000c08
1630 #define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14
1631 #define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18
1633 #define NIC_SRAM_WOL_MBOX 0x00000d30
1634 #define WOL_SIGNATURE 0x474c0000
1635 #define WOL_DRV_STATE_SHUTDOWN 0x00000001
1636 #define WOL_DRV_WOL 0x00000002
1637 #define WOL_SET_MAGIC_PKT 0x00000004
1639 #define NIC_SRAM_DATA_CFG_2 0x00000d38
1641 #define SHASTA_EXT_LED_MODE_MASK 0x00018000
1642 #define SHASTA_EXT_LED_LEGACY 0x00000000
1643 #define SHASTA_EXT_LED_SHARED 0x00008000
1644 #define SHASTA_EXT_LED_MAC 0x00010000
1645 #define SHASTA_EXT_LED_COMBO 0x00018000
1647 #define NIC_SRAM_DATA_CFG_3 0x00000d3c
1648 #define NIC_SRAM_ASPM_DEBOUNCE 0x00000002
1650 #define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
1652 #define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000
1653 #define NIC_SRAM_DMA_DESC_POOL_SIZE 0x00002000
1654 #define NIC_SRAM_TX_BUFFER_DESC 0x00004000 /* 512 entries */
1655 #define NIC_SRAM_RX_BUFFER_DESC 0x00006000 /* 256 entries */
1656 #define NIC_SRAM_RX_JUMBO_BUFFER_DESC 0x00007000 /* 256 entries */
1657 #define NIC_SRAM_MBUF_POOL_BASE 0x00008000
1658 #define NIC_SRAM_MBUF_POOL_SIZE96 0x00018000
1659 #define NIC_SRAM_MBUF_POOL_SIZE64 0x00010000
1660 #define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000
1661 #define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000
1663 /* Currently this is fixed. */
1664 #define PHY_ADDR 0x01
1666 /* Tigon3 specific PHY MII registers. */
1667 #define TG3_BMCR_SPEED1000 0x0040
1669 #define MII_TG3_CTRL 0x09 /* 1000-baseT control register */
1670 #define MII_TG3_CTRL_ADV_1000_HALF 0x0100
1671 #define MII_TG3_CTRL_ADV_1000_FULL 0x0200
1672 #define MII_TG3_CTRL_AS_MASTER 0x0800
1673 #define MII_TG3_CTRL_ENABLE_AS_MASTER 0x1000
1675 #define MII_TG3_EXT_CTRL 0x10 /* Extended control register */
1676 #define MII_TG3_EXT_CTRL_FIFO_ELASTIC 0x0001
1677 #define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002
1678 #define MII_TG3_EXT_CTRL_FORCE_LED_OFF 0x0008
1679 #define MII_TG3_EXT_CTRL_TBI 0x8000
1681 #define MII_TG3_EXT_STAT 0x11 /* Extended status register */
1682 #define MII_TG3_EXT_STAT_LPASS 0x0100
1684 #define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */
1686 #define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */
1687 #define MII_TG3_EPHY_PTEST 0x17 /* 5906 PHY register */
1689 #define MII_TG3_AUX_CTRL 0x18 /* auxilliary control register */
1691 #define MII_TG3_AUXCTL_MISC_WREN 0x8000
1692 #define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200
1693 #define MII_TG3_AUXCTL_MISC_RDSEL_MISC 0x7000
1694 #define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007
1696 #define MII_TG3_AUX_STAT 0x19 /* auxilliary status register */
1697 #define MII_TG3_AUX_STAT_LPASS 0x0004
1698 #define MII_TG3_AUX_STAT_SPDMASK 0x0700
1699 #define MII_TG3_AUX_STAT_10HALF 0x0100
1700 #define MII_TG3_AUX_STAT_10FULL 0x0200
1701 #define MII_TG3_AUX_STAT_100HALF 0x0300
1702 #define MII_TG3_AUX_STAT_100_4 0x0400
1703 #define MII_TG3_AUX_STAT_100FULL 0x0500
1704 #define MII_TG3_AUX_STAT_1000HALF 0x0600
1705 #define MII_TG3_AUX_STAT_1000FULL 0x0700
1706 #define MII_TG3_AUX_STAT_100 0x0008
1707 #define MII_TG3_AUX_STAT_FULL 0x0001
1709 #define MII_TG3_ISTAT 0x1a /* IRQ status register */
1710 #define MII_TG3_IMASK 0x1b /* IRQ mask register */
1712 /* ISTAT/IMASK event bits */
1713 #define MII_TG3_INT_LINKCHG 0x0002
1714 #define MII_TG3_INT_SPEEDCHG 0x0004
1715 #define MII_TG3_INT_DUPLEXCHG 0x0008
1716 #define MII_TG3_INT_ANEG_PAGE_RX 0x0400
1718 #define MII_TG3_EPHY_TEST 0x1f /* 5906 PHY register */
1719 #define MII_TG3_EPHY_SHADOW_EN 0x80
1721 #define MII_TG3_EPHYTST_MISCCTRL 0x10 /* 5906 EPHY misc ctrl shadow register */
1722 #define MII_TG3_EPHYTST_MISCCTRL_MDIX 0x4000
1724 #define MII_TG3_TEST1 0x1e
1725 #define MII_TG3_TEST1_TRIM_EN 0x0010
1726 #define MII_TG3_TEST1_CRC_EN 0x8000
1728 /* APE registers. Accessible through BAR1 */
1729 #define TG3_APE_EVENT 0x000c
1730 #define APE_EVENT_1 0x00000001
1731 #define TG3_APE_LOCK_REQ 0x002c
1732 #define APE_LOCK_REQ_DRIVER 0x00001000
1733 #define TG3_APE_LOCK_GRANT 0x004c
1734 #define APE_LOCK_GRANT_DRIVER 0x00001000
1735 #define TG3_APE_SEG_SIG 0x4000
1736 #define APE_SEG_SIG_MAGIC 0x41504521
1738 /* APE shared memory. Accessible through BAR1 */
1739 #define TG3_APE_FW_STATUS 0x400c
1740 #define APE_FW_STATUS_READY 0x00000100
1741 #define TG3_APE_HOST_SEG_SIG 0x4200
1742 #define APE_HOST_SEG_SIG_MAGIC 0x484f5354
1743 #define TG3_APE_HOST_SEG_LEN 0x4204
1744 #define APE_HOST_SEG_LEN_MAGIC 0x0000001c
1745 #define TG3_APE_HOST_INIT_COUNT 0x4208
1746 #define TG3_APE_HOST_DRIVER_ID 0x420c
1747 #define APE_HOST_DRIVER_ID_MAGIC 0xf0035100
1748 #define TG3_APE_HOST_BEHAVIOR 0x4210
1749 #define APE_HOST_BEHAV_NO_PHYLOCK 0x00000001
1750 #define TG3_APE_HOST_HEARTBEAT_INT_MS 0x4214
1751 #define APE_HOST_HEARTBEAT_INT_DISABLE 0
1752 #define APE_HOST_HEARTBEAT_INT_5SEC 5000
1753 #define TG3_APE_HOST_HEARTBEAT_COUNT 0x4218
1755 #define TG3_APE_EVENT_STATUS 0x4300
1757 #define APE_EVENT_STATUS_DRIVER_EVNT 0x00000010
1758 #define APE_EVENT_STATUS_STATE_CHNGE 0x00000500
1759 #define APE_EVENT_STATUS_STATE_START 0x00010000
1760 #define APE_EVENT_STATUS_STATE_UNLOAD 0x00020000
1761 #define APE_EVENT_STATUS_STATE_WOL 0x00030000
1762 #define APE_EVENT_STATUS_STATE_SUSPEND 0x00040000
1763 #define APE_EVENT_STATUS_EVENT_PENDING 0x80000000
1765 /* APE convenience enumerations. */
1766 #define TG3_APE_LOCK_MEM 4
1769 /* There are two ways to manage the TX descriptors on the tigon3.
1770 * Either the descriptors are in host DMA'able memory, or they
1771 * exist only in the cards on-chip SRAM. All 16 send bds are under
1772 * the same mode, they may not be configured individually.
1774 * This driver always uses host memory TX descriptors.
1776 * To use host memory TX descriptors:
1777 * 1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register.
1778 * Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear.
1779 * 2) Allocate DMA'able memory.
1780 * 3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
1781 * a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory
1782 * obtained in step 2
1783 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC.
1784 * c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number
1785 * of TX descriptors. Leave flags field clear.
1786 * 4) Access TX descriptors via host memory. The chip
1787 * will refetch into local SRAM as needed when producer
1788 * index mailboxes are updated.
1790 * To use on-chip TX descriptors:
1791 * 1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register.
1792 * Make sure GRC_MODE_HOST_SENDBDS is clear.
1793 * 2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
1794 * a) Set TG3_BDINFO_HOST_ADDR to zero.
1795 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC
1796 * c) TG3_BDINFO_MAXLEN_FLAGS is don't care.
1797 * 3) Access TX descriptors directly in on-chip SRAM
1798 * using normal {read,write}l(). (and not using
1799 * pointer dereferencing of ioremap()'d memory like
1800 * the broken Broadcom driver does)
1802 * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of
1803 * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices.
1805 struct tg3_tx_buffer_desc
{
1810 #define TXD_FLAG_TCPUDP_CSUM 0x0001
1811 #define TXD_FLAG_IP_CSUM 0x0002
1812 #define TXD_FLAG_END 0x0004
1813 #define TXD_FLAG_IP_FRAG 0x0008
1814 #define TXD_FLAG_IP_FRAG_END 0x0010
1815 #define TXD_FLAG_VLAN 0x0040
1816 #define TXD_FLAG_COAL_NOW 0x0080
1817 #define TXD_FLAG_CPU_PRE_DMA 0x0100
1818 #define TXD_FLAG_CPU_POST_DMA 0x0200
1819 #define TXD_FLAG_ADD_SRC_ADDR 0x1000
1820 #define TXD_FLAG_CHOOSE_SRC_ADDR 0x6000
1821 #define TXD_FLAG_NO_CRC 0x8000
1822 #define TXD_LEN_SHIFT 16
1825 #define TXD_VLAN_TAG_SHIFT 0
1826 #define TXD_MSS_SHIFT 16
1829 #define TXD_ADDR 0x00UL /* 64-bit */
1830 #define TXD_LEN_FLAGS 0x08UL /* 32-bit (upper 16-bits are len) */
1831 #define TXD_VLAN_TAG 0x0cUL /* 32-bit (upper 16-bits are tag) */
1832 #define TXD_SIZE 0x10UL
1834 struct tg3_rx_buffer_desc
{
1839 #define RXD_IDX_MASK 0xffff0000
1840 #define RXD_IDX_SHIFT 16
1841 #define RXD_LEN_MASK 0x0000ffff
1842 #define RXD_LEN_SHIFT 0
1845 #define RXD_TYPE_SHIFT 16
1846 #define RXD_FLAGS_SHIFT 0
1848 #define RXD_FLAG_END 0x0004
1849 #define RXD_FLAG_MINI 0x0800
1850 #define RXD_FLAG_JUMBO 0x0020
1851 #define RXD_FLAG_VLAN 0x0040
1852 #define RXD_FLAG_ERROR 0x0400
1853 #define RXD_FLAG_IP_CSUM 0x1000
1854 #define RXD_FLAG_TCPUDP_CSUM 0x2000
1855 #define RXD_FLAG_IS_TCP 0x4000
1858 #define RXD_IPCSUM_MASK 0xffff0000
1859 #define RXD_IPCSUM_SHIFT 16
1860 #define RXD_TCPCSUM_MASK 0x0000ffff
1861 #define RXD_TCPCSUM_SHIFT 0
1865 #define RXD_VLAN_MASK 0x0000ffff
1867 #define RXD_ERR_BAD_CRC 0x00010000
1868 #define RXD_ERR_COLLISION 0x00020000
1869 #define RXD_ERR_LINK_LOST 0x00040000
1870 #define RXD_ERR_PHY_DECODE 0x00080000
1871 #define RXD_ERR_ODD_NIBBLE_RCVD_MII 0x00100000
1872 #define RXD_ERR_MAC_ABRT 0x00200000
1873 #define RXD_ERR_TOO_SMALL 0x00400000
1874 #define RXD_ERR_NO_RESOURCES 0x00800000
1875 #define RXD_ERR_HUGE_FRAME 0x01000000
1876 #define RXD_ERR_MASK 0xffff0000
1880 #define RXD_OPAQUE_INDEX_MASK 0x0000ffff
1881 #define RXD_OPAQUE_INDEX_SHIFT 0
1882 #define RXD_OPAQUE_RING_STD 0x00010000
1883 #define RXD_OPAQUE_RING_JUMBO 0x00020000
1884 #define RXD_OPAQUE_RING_MINI 0x00040000
1885 #define RXD_OPAQUE_RING_MASK 0x00070000
1888 struct tg3_ext_rx_buffer_desc
{
1895 struct tg3_rx_buffer_desc std
;
1898 /* We only use this when testing out the DMA engine
1899 * at probe time. This is the internal format of buffer
1900 * descriptors used by the chip at NIC_SRAM_DMA_DESCS.
1902 struct tg3_internal_buffer_desc
{
1920 #define TG3_HW_STATUS_SIZE 0x50
1921 struct tg3_hw_status
{
1923 #define SD_STATUS_UPDATED 0x00000001
1924 #define SD_STATUS_LINK_CHG 0x00000002
1925 #define SD_STATUS_ERROR 0x00000004
1931 u16 rx_jumbo_consumer
;
1933 u16 rx_jumbo_consumer
;
1939 u16 rx_mini_consumer
;
1941 u16 rx_mini_consumer
;
1959 struct tg3_hw_stats
{
1960 u8 __reserved0
[0x400-0x300];
1962 /* Statistics maintained by Receive MAC. */
1963 tg3_stat64_t rx_octets
;
1965 tg3_stat64_t rx_fragments
;
1966 tg3_stat64_t rx_ucast_packets
;
1967 tg3_stat64_t rx_mcast_packets
;
1968 tg3_stat64_t rx_bcast_packets
;
1969 tg3_stat64_t rx_fcs_errors
;
1970 tg3_stat64_t rx_align_errors
;
1971 tg3_stat64_t rx_xon_pause_rcvd
;
1972 tg3_stat64_t rx_xoff_pause_rcvd
;
1973 tg3_stat64_t rx_mac_ctrl_rcvd
;
1974 tg3_stat64_t rx_xoff_entered
;
1975 tg3_stat64_t rx_frame_too_long_errors
;
1976 tg3_stat64_t rx_jabbers
;
1977 tg3_stat64_t rx_undersize_packets
;
1978 tg3_stat64_t rx_in_length_errors
;
1979 tg3_stat64_t rx_out_length_errors
;
1980 tg3_stat64_t rx_64_or_less_octet_packets
;
1981 tg3_stat64_t rx_65_to_127_octet_packets
;
1982 tg3_stat64_t rx_128_to_255_octet_packets
;
1983 tg3_stat64_t rx_256_to_511_octet_packets
;
1984 tg3_stat64_t rx_512_to_1023_octet_packets
;
1985 tg3_stat64_t rx_1024_to_1522_octet_packets
;
1986 tg3_stat64_t rx_1523_to_2047_octet_packets
;
1987 tg3_stat64_t rx_2048_to_4095_octet_packets
;
1988 tg3_stat64_t rx_4096_to_8191_octet_packets
;
1989 tg3_stat64_t rx_8192_to_9022_octet_packets
;
1993 /* Statistics maintained by Transmit MAC. */
1994 tg3_stat64_t tx_octets
;
1996 tg3_stat64_t tx_collisions
;
1997 tg3_stat64_t tx_xon_sent
;
1998 tg3_stat64_t tx_xoff_sent
;
1999 tg3_stat64_t tx_flow_control
;
2000 tg3_stat64_t tx_mac_errors
;
2001 tg3_stat64_t tx_single_collisions
;
2002 tg3_stat64_t tx_mult_collisions
;
2003 tg3_stat64_t tx_deferred
;
2005 tg3_stat64_t tx_excessive_collisions
;
2006 tg3_stat64_t tx_late_collisions
;
2007 tg3_stat64_t tx_collide_2times
;
2008 tg3_stat64_t tx_collide_3times
;
2009 tg3_stat64_t tx_collide_4times
;
2010 tg3_stat64_t tx_collide_5times
;
2011 tg3_stat64_t tx_collide_6times
;
2012 tg3_stat64_t tx_collide_7times
;
2013 tg3_stat64_t tx_collide_8times
;
2014 tg3_stat64_t tx_collide_9times
;
2015 tg3_stat64_t tx_collide_10times
;
2016 tg3_stat64_t tx_collide_11times
;
2017 tg3_stat64_t tx_collide_12times
;
2018 tg3_stat64_t tx_collide_13times
;
2019 tg3_stat64_t tx_collide_14times
;
2020 tg3_stat64_t tx_collide_15times
;
2021 tg3_stat64_t tx_ucast_packets
;
2022 tg3_stat64_t tx_mcast_packets
;
2023 tg3_stat64_t tx_bcast_packets
;
2024 tg3_stat64_t tx_carrier_sense_errors
;
2025 tg3_stat64_t tx_discards
;
2026 tg3_stat64_t tx_errors
;
2030 /* Statistics maintained by Receive List Placement. */
2031 tg3_stat64_t COS_rx_packets
[16];
2032 tg3_stat64_t COS_rx_filter_dropped
;
2033 tg3_stat64_t dma_writeq_full
;
2034 tg3_stat64_t dma_write_prioq_full
;
2035 tg3_stat64_t rxbds_empty
;
2036 tg3_stat64_t rx_discards
;
2037 tg3_stat64_t rx_errors
;
2038 tg3_stat64_t rx_threshold_hit
;
2042 /* Statistics maintained by Send Data Initiator. */
2043 tg3_stat64_t COS_out_packets
[16];
2044 tg3_stat64_t dma_readq_full
;
2045 tg3_stat64_t dma_read_prioq_full
;
2046 tg3_stat64_t tx_comp_queue_full
;
2048 /* Statistics maintained by Host Coalescing. */
2049 tg3_stat64_t ring_set_send_prod_index
;
2050 tg3_stat64_t ring_status_update
;
2051 tg3_stat64_t nic_irqs
;
2052 tg3_stat64_t nic_avoided_irqs
;
2053 tg3_stat64_t nic_tx_threshold_hit
;
2055 u8 __reserved4
[0xb00-0x9c0];
2058 /* 'mapping' is superfluous as the chip does not write into
2059 * the tx/rx post rings so we could just fetch it from there.
2060 * But the cache behavior is better how we are doing it now.
2063 struct sk_buff
*skb
;
2064 DECLARE_PCI_UNMAP_ADDR(mapping
)
2067 struct tx_ring_info
{
2068 struct sk_buff
*skb
;
2069 DECLARE_PCI_UNMAP_ADDR(mapping
)
2073 struct tg3_config_info
{
2077 struct tg3_link_config
{
2078 /* Describes what we're trying to get. */
2084 /* Describes what we actually have. */
2087 #define SPEED_INVALID 0xffff
2088 #define DUPLEX_INVALID 0xff
2089 #define AUTONEG_INVALID 0xff
2091 /* When we go in and out of low power mode we need
2092 * to swap with this state.
2094 int phy_is_low_power
;
2100 struct tg3_bufmgr_config
{
2101 u32 mbuf_read_dma_low_water
;
2102 u32 mbuf_mac_rx_low_water
;
2103 u32 mbuf_high_water
;
2105 u32 mbuf_read_dma_low_water_jumbo
;
2106 u32 mbuf_mac_rx_low_water_jumbo
;
2107 u32 mbuf_high_water_jumbo
;
2113 struct tg3_ethtool_stats
{
2114 /* Statistics maintained by Receive MAC. */
2117 u64 rx_ucast_packets
;
2118 u64 rx_mcast_packets
;
2119 u64 rx_bcast_packets
;
2121 u64 rx_align_errors
;
2122 u64 rx_xon_pause_rcvd
;
2123 u64 rx_xoff_pause_rcvd
;
2124 u64 rx_mac_ctrl_rcvd
;
2125 u64 rx_xoff_entered
;
2126 u64 rx_frame_too_long_errors
;
2128 u64 rx_undersize_packets
;
2129 u64 rx_in_length_errors
;
2130 u64 rx_out_length_errors
;
2131 u64 rx_64_or_less_octet_packets
;
2132 u64 rx_65_to_127_octet_packets
;
2133 u64 rx_128_to_255_octet_packets
;
2134 u64 rx_256_to_511_octet_packets
;
2135 u64 rx_512_to_1023_octet_packets
;
2136 u64 rx_1024_to_1522_octet_packets
;
2137 u64 rx_1523_to_2047_octet_packets
;
2138 u64 rx_2048_to_4095_octet_packets
;
2139 u64 rx_4096_to_8191_octet_packets
;
2140 u64 rx_8192_to_9022_octet_packets
;
2142 /* Statistics maintained by Transmit MAC. */
2147 u64 tx_flow_control
;
2149 u64 tx_single_collisions
;
2150 u64 tx_mult_collisions
;
2152 u64 tx_excessive_collisions
;
2153 u64 tx_late_collisions
;
2154 u64 tx_collide_2times
;
2155 u64 tx_collide_3times
;
2156 u64 tx_collide_4times
;
2157 u64 tx_collide_5times
;
2158 u64 tx_collide_6times
;
2159 u64 tx_collide_7times
;
2160 u64 tx_collide_8times
;
2161 u64 tx_collide_9times
;
2162 u64 tx_collide_10times
;
2163 u64 tx_collide_11times
;
2164 u64 tx_collide_12times
;
2165 u64 tx_collide_13times
;
2166 u64 tx_collide_14times
;
2167 u64 tx_collide_15times
;
2168 u64 tx_ucast_packets
;
2169 u64 tx_mcast_packets
;
2170 u64 tx_bcast_packets
;
2171 u64 tx_carrier_sense_errors
;
2175 /* Statistics maintained by Receive List Placement. */
2176 u64 dma_writeq_full
;
2177 u64 dma_write_prioq_full
;
2181 u64 rx_threshold_hit
;
2183 /* Statistics maintained by Send Data Initiator. */
2185 u64 dma_read_prioq_full
;
2186 u64 tx_comp_queue_full
;
2188 /* Statistics maintained by Host Coalescing. */
2189 u64 ring_set_send_prod_index
;
2190 u64 ring_status_update
;
2192 u64 nic_avoided_irqs
;
2193 u64 nic_tx_threshold_hit
;
2197 /* begin "general, frequently-used members" cacheline section */
2199 /* If the IRQ handler (which runs lockless) needs to be
2200 * quiesced, the following bitmask state is used. The
2201 * SYNC flag is set by non-IRQ context code to initiate
2204 * When the IRQ handler notices that SYNC is set, it
2205 * disables interrupts and returns.
2207 * When all outstanding IRQ handlers have returned after
2208 * the SYNC flag has been set, the setter can be assured
2209 * that interrupts will no longer get run.
2211 * In this way all SMP driver locks are never acquired
2212 * in hw IRQ context, only sw IRQ context or lower.
2214 unsigned int irq_sync
;
2216 /* SMP locking strategy:
2218 * lock: Held during reset, PHY access, timer, and when
2219 * updating tg3_flags and tg3_flags2.
2221 * netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds
2222 * netif_tx_lock when it needs to call
2225 * Both of these locks are to be held with BH safety.
2227 * Because the IRQ handler, tg3_poll, and tg3_start_xmit
2228 * are running lockless, it is necessary to completely
2229 * quiesce the chip with tg3_netif_stop and tg3_full_lock
2230 * before reconfiguring the device.
2232 * indirect_lock: Held when accessing registers indirectly
2233 * with IRQ disabling.
2236 spinlock_t indirect_lock
;
2238 u32 (*read32
) (struct tg3
*, u32
);
2239 void (*write32
) (struct tg3
*, u32
, u32
);
2240 u32 (*read32_mbox
) (struct tg3
*, u32
);
2241 void (*write32_mbox
) (struct tg3
*, u32
,
2244 void __iomem
*aperegs
;
2245 struct net_device
*dev
;
2246 struct pci_dev
*pdev
;
2248 struct tg3_hw_status
*hw_status
;
2249 dma_addr_t status_mapping
;
2254 /* begin "tx thread" cacheline section */
2255 void (*write32_tx_mbox
) (struct tg3
*, u32
,
2261 struct tg3_tx_buffer_desc
*tx_ring
;
2262 struct tx_ring_info
*tx_buffers
;
2263 dma_addr_t tx_desc_mapping
;
2265 /* begin "rx thread" cacheline section */
2266 struct napi_struct napi
;
2267 void (*write32_rx_mbox
) (struct tg3
*, u32
,
2273 u32 rx_jumbo_pending
;
2274 #if TG3_VLAN_TAG_USED
2275 struct vlan_group
*vlgrp
;
2278 struct tg3_rx_buffer_desc
*rx_std
;
2279 struct ring_info
*rx_std_buffers
;
2280 dma_addr_t rx_std_mapping
;
2281 u32 rx_std_max_post
;
2283 struct tg3_rx_buffer_desc
*rx_jumbo
;
2284 struct ring_info
*rx_jumbo_buffers
;
2285 dma_addr_t rx_jumbo_mapping
;
2287 struct tg3_rx_buffer_desc
*rx_rcb
;
2288 dma_addr_t rx_rcb_mapping
;
2292 /* begin "everything else" cacheline(s) section */
2293 struct net_device_stats net_stats
;
2294 struct net_device_stats net_stats_prev
;
2295 struct tg3_ethtool_stats estats
;
2296 struct tg3_ethtool_stats estats_prev
;
2298 unsigned long phy_crc_errors
;
2302 #define TG3_FLAG_TAGGED_STATUS 0x00000001
2303 #define TG3_FLAG_TXD_MBOX_HWBUG 0x00000002
2304 #define TG3_FLAG_RX_CHECKSUMS 0x00000004
2305 #define TG3_FLAG_USE_LINKCHG_REG 0x00000008
2306 #define TG3_FLAG_USE_MI_INTERRUPT 0x00000010
2307 #define TG3_FLAG_ENABLE_ASF 0x00000020
2308 #define TG3_FLAG_ASPM_WORKAROUND 0x00000040
2309 #define TG3_FLAG_POLL_SERDES 0x00000080
2310 #define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100
2311 #define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200
2312 #define TG3_FLAG_WOL_SPEED_100MB 0x00000400
2313 #define TG3_FLAG_WOL_ENABLE 0x00000800
2314 #define TG3_FLAG_EEPROM_WRITE_PROT 0x00001000
2315 #define TG3_FLAG_NVRAM 0x00002000
2316 #define TG3_FLAG_NVRAM_BUFFERED 0x00004000
2317 #define TG3_FLAG_RX_PAUSE 0x00008000
2318 #define TG3_FLAG_TX_PAUSE 0x00010000
2319 #define TG3_FLAG_PCIX_MODE 0x00020000
2320 #define TG3_FLAG_PCI_HIGH_SPEED 0x00040000
2321 #define TG3_FLAG_PCI_32BIT 0x00080000
2322 #define TG3_FLAG_SRAM_USE_CONFIG 0x00100000
2323 #define TG3_FLAG_TX_RECOVERY_PENDING 0x00200000
2324 #define TG3_FLAG_WOL_CAP 0x00400000
2325 #define TG3_FLAG_JUMBO_RING_ENABLE 0x00800000
2326 #define TG3_FLAG_10_100_ONLY 0x01000000
2327 #define TG3_FLAG_PAUSE_AUTONEG 0x02000000
2328 #define TG3_FLAG_CPMU_PRESENT 0x04000000
2329 #define TG3_FLAG_40BIT_DMA_BUG 0x08000000
2330 #define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000
2331 #define TG3_FLAG_SUPPORT_MSI 0x20000000
2332 #define TG3_FLAG_CHIP_RESETTING 0x40000000
2333 #define TG3_FLAG_INIT_COMPLETE 0x80000000
2335 #define TG3_FLG2_RESTART_TIMER 0x00000001
2336 #define TG3_FLG2_TSO_BUG 0x00000002
2337 #define TG3_FLG2_NO_ETH_WIRE_SPEED 0x00000004
2338 #define TG3_FLG2_IS_5788 0x00000008
2339 #define TG3_FLG2_MAX_RXPEND_64 0x00000010
2340 #define TG3_FLG2_TSO_CAPABLE 0x00000020
2341 #define TG3_FLG2_PHY_ADC_BUG 0x00000040
2342 #define TG3_FLG2_PHY_5704_A0_BUG 0x00000080
2343 #define TG3_FLG2_PHY_BER_BUG 0x00000100
2344 #define TG3_FLG2_PCI_EXPRESS 0x00000200
2345 #define TG3_FLG2_ASF_NEW_HANDSHAKE 0x00000400
2346 #define TG3_FLG2_HW_AUTONEG 0x00000800
2347 #define TG3_FLG2_IS_NIC 0x00001000
2348 #define TG3_FLG2_PHY_SERDES 0x00002000
2349 #define TG3_FLG2_CAPACITIVE_COUPLING 0x00004000
2350 #define TG3_FLG2_FLASH 0x00008000
2351 #define TG3_FLG2_HW_TSO_1 0x00010000
2352 #define TG3_FLG2_SERDES_PREEMPHASIS 0x00020000
2353 #define TG3_FLG2_5705_PLUS 0x00040000
2354 #define TG3_FLG2_5750_PLUS 0x00080000
2355 #define TG3_FLG2_PROTECTED_NVRAM 0x00100000
2356 #define TG3_FLG2_USING_MSI 0x00200000
2357 #define TG3_FLG2_JUMBO_CAPABLE 0x00400000
2358 #define TG3_FLG2_MII_SERDES 0x00800000
2359 #define TG3_FLG2_ANY_SERDES (TG3_FLG2_PHY_SERDES | \
2360 TG3_FLG2_MII_SERDES)
2361 #define TG3_FLG2_PARALLEL_DETECT 0x01000000
2362 #define TG3_FLG2_ICH_WORKAROUND 0x02000000
2363 #define TG3_FLG2_5780_CLASS 0x04000000
2364 #define TG3_FLG2_HW_TSO_2 0x08000000
2365 #define TG3_FLG2_HW_TSO (TG3_FLG2_HW_TSO_1 | TG3_FLG2_HW_TSO_2)
2366 #define TG3_FLG2_1SHOT_MSI 0x10000000
2367 #define TG3_FLG2_PHY_JITTER_BUG 0x20000000
2368 #define TG3_FLG2_NO_FWARE_REPORTED 0x40000000
2369 #define TG3_FLG2_PHY_ADJUST_TRIM 0x80000000
2371 #define TG3_FLG3_NO_NVRAM_ADDR_TRANS 0x00000001
2372 #define TG3_FLG3_ENABLE_APE 0x00000002
2374 struct timer_list timer
;
2376 u16 timer_multiplier
;
2381 /* 1 second counter for transient serdes link events */
2383 #define SERDES_AN_TIMEOUT_5704S 2
2384 #define SERDES_PARALLEL_DET_TIMEOUT 1
2385 #define SERDES_AN_TIMEOUT_5714S 1
2387 struct tg3_link_config link_config
;
2388 struct tg3_bufmgr_config bufmgr_config
;
2390 /* cache h/w values, often passed straight to h/w */
2403 u32 pci_chip_rev_id
;
2404 u8 pci_cacheline_sz
;
2415 #define PHY_ID_MASK 0xfffffff0
2416 #define PHY_ID_BCM5400 0x60008040
2417 #define PHY_ID_BCM5401 0x60008050
2418 #define PHY_ID_BCM5411 0x60008070
2419 #define PHY_ID_BCM5701 0x60008110
2420 #define PHY_ID_BCM5703 0x60008160
2421 #define PHY_ID_BCM5704 0x60008190
2422 #define PHY_ID_BCM5705 0x600081a0
2423 #define PHY_ID_BCM5750 0x60008180
2424 #define PHY_ID_BCM5752 0x60008100
2425 #define PHY_ID_BCM5714 0x60008340
2426 #define PHY_ID_BCM5780 0x60008350
2427 #define PHY_ID_BCM5755 0xbc050cc0
2428 #define PHY_ID_BCM5787 0xbc050ce0
2429 #define PHY_ID_BCM5756 0xbc050ed0
2430 #define PHY_ID_BCM5784 0xbc050fa0
2431 #define PHY_ID_BCM5761 0xbc050fd0
2432 #define PHY_ID_BCM5906 0xdc00ac40
2433 #define PHY_ID_BCM8002 0x60010140
2434 #define PHY_ID_INVALID 0xffffffff
2435 #define PHY_ID_REV_MASK 0x0000000f
2436 #define PHY_REV_BCM5401_B0 0x1
2437 #define PHY_REV_BCM5401_B2 0x3
2438 #define PHY_REV_BCM5401_C0 0x6
2439 #define PHY_REV_BCM5411_X0 0x1 /* Found on Netgear GA302T */
2444 char board_part_number
[24];
2445 #define TG3_VER_SIZE 32
2446 char fw_ver
[TG3_VER_SIZE
];
2447 u32 nic_sram_data_cfg
;
2449 struct pci_dev
*pdev_peer
;
2451 /* This macro assumes the passed PHY ID is already masked
2454 #define KNOWN_PHY_ID(X) \
2455 ((X) == PHY_ID_BCM5400 || (X) == PHY_ID_BCM5401 || \
2456 (X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \
2457 (X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \
2458 (X) == PHY_ID_BCM5705 || (X) == PHY_ID_BCM5750 || \
2459 (X) == PHY_ID_BCM5752 || (X) == PHY_ID_BCM5714 || \
2460 (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
2461 (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \
2462 (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM5761 || \
2463 (X) == PHY_ID_BCM8002)
2465 struct tg3_hw_stats
*hw_stats
;
2466 dma_addr_t stats_mapping
;
2467 struct work_struct reset_task
;
2474 #define JEDEC_ATMEL 0x1f
2475 #define JEDEC_ST 0x20
2476 #define JEDEC_SAIFUN 0x4f
2477 #define JEDEC_SST 0xbf
2479 #define ATMEL_AT24C64_CHIP_SIZE (64 * 1024)
2480 #define ATMEL_AT24C64_PAGE_SIZE (32)
2482 #define ATMEL_AT24C512_CHIP_SIZE (512 * 1024)
2483 #define ATMEL_AT24C512_PAGE_SIZE (128)
2485 #define ATMEL_AT45DB0X1B_PAGE_POS 9
2486 #define ATMEL_AT45DB0X1B_PAGE_SIZE 264
2488 #define ATMEL_AT25F512_PAGE_SIZE 256
2490 #define ST_M45PEX0_PAGE_SIZE 256
2492 #define SAIFUN_SA25F0XX_PAGE_SIZE 256
2494 #define SST_25VF0X0_PAGE_SIZE 4098
2496 struct ethtool_coalesce coal
;
2499 #endif /* !(_T3_H) */