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[NET]: Make NAPI polling independent of struct net_device objects.
[deliverable/linux.git] / drivers / net / tulip / tulip_core.c
1 /* tulip_core.c: A DEC 21x4x-family ethernet driver for Linux. */
2
3 /*
4 Maintained by Valerie Henson <val_henson@linux.intel.com>
5 Copyright 2000,2001 The Linux Kernel Team
6 Written/copyright 1994-2001 by Donald Becker.
7
8 This software may be used and distributed according to the terms
9 of the GNU General Public License, incorporated herein by reference.
10
11 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
12 for more information on this driver, or visit the project
13 Web page at http://sourceforge.net/projects/tulip/
14
15 */
16
17
18 #define DRV_NAME "tulip"
19 #ifdef CONFIG_TULIP_NAPI
20 #define DRV_VERSION "1.1.15-NAPI" /* Keep at least for test */
21 #else
22 #define DRV_VERSION "1.1.15"
23 #endif
24 #define DRV_RELDATE "Feb 27, 2007"
25
26
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include "tulip.h"
30 #include <linux/init.h>
31 #include <linux/etherdevice.h>
32 #include <linux/delay.h>
33 #include <linux/mii.h>
34 #include <linux/ethtool.h>
35 #include <linux/crc32.h>
36 #include <asm/unaligned.h>
37 #include <asm/uaccess.h>
38
39 #ifdef CONFIG_SPARC
40 #include <asm/prom.h>
41 #endif
42
43 static char version[] __devinitdata =
44 "Linux Tulip driver version " DRV_VERSION " (" DRV_RELDATE ")\n";
45
46
47 /* A few user-configurable values. */
48
49 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
50 static unsigned int max_interrupt_work = 25;
51
52 #define MAX_UNITS 8
53 /* Used to pass the full-duplex flag, etc. */
54 static int full_duplex[MAX_UNITS];
55 static int options[MAX_UNITS];
56 static int mtu[MAX_UNITS]; /* Jumbo MTU for interfaces. */
57
58 /* The possible media types that can be set in options[] are: */
59 const char * const medianame[32] = {
60 "10baseT", "10base2", "AUI", "100baseTx",
61 "10baseT-FDX", "100baseTx-FDX", "100baseT4", "100baseFx",
62 "100baseFx-FDX", "MII 10baseT", "MII 10baseT-FDX", "MII",
63 "10baseT(forced)", "MII 100baseTx", "MII 100baseTx-FDX", "MII 100baseT4",
64 "MII 100baseFx-HDX", "MII 100baseFx-FDX", "Home-PNA 1Mbps", "Invalid-19",
65 "","","","", "","","","", "","","","Transceiver reset",
66 };
67
68 /* Set the copy breakpoint for the copy-only-tiny-buffer Rx structure. */
69 #if defined(__alpha__) || defined(__arm__) || defined(__hppa__) \
70 || defined(CONFIG_SPARC) || defined(__ia64__) \
71 || defined(__sh__) || defined(__mips__)
72 static int rx_copybreak = 1518;
73 #else
74 static int rx_copybreak = 100;
75 #endif
76
77 /*
78 Set the bus performance register.
79 Typical: Set 16 longword cache alignment, no burst limit.
80 Cache alignment bits 15:14 Burst length 13:8
81 0000 No alignment 0x00000000 unlimited 0800 8 longwords
82 4000 8 longwords 0100 1 longword 1000 16 longwords
83 8000 16 longwords 0200 2 longwords 2000 32 longwords
84 C000 32 longwords 0400 4 longwords
85 Warning: many older 486 systems are broken and require setting 0x00A04800
86 8 longword cache alignment, 8 longword burst.
87 ToDo: Non-Intel setting could be better.
88 */
89
90 #if defined(__alpha__) || defined(__ia64__)
91 static int csr0 = 0x01A00000 | 0xE000;
92 #elif defined(__i386__) || defined(__powerpc__) || defined(__x86_64__)
93 static int csr0 = 0x01A00000 | 0x8000;
94 #elif defined(CONFIG_SPARC) || defined(__hppa__)
95 /* The UltraSparc PCI controllers will disconnect at every 64-byte
96 * crossing anyways so it makes no sense to tell Tulip to burst
97 * any more than that.
98 */
99 static int csr0 = 0x01A00000 | 0x9000;
100 #elif defined(__arm__) || defined(__sh__)
101 static int csr0 = 0x01A00000 | 0x4800;
102 #elif defined(__mips__)
103 static int csr0 = 0x00200000 | 0x4000;
104 #else
105 #warning Processor architecture undefined!
106 static int csr0 = 0x00A00000 | 0x4800;
107 #endif
108
109 /* Operational parameters that usually are not changed. */
110 /* Time in jiffies before concluding the transmitter is hung. */
111 #define TX_TIMEOUT (4*HZ)
112
113
114 MODULE_AUTHOR("The Linux Kernel Team");
115 MODULE_DESCRIPTION("Digital 21*4* Tulip ethernet driver");
116 MODULE_LICENSE("GPL");
117 MODULE_VERSION(DRV_VERSION);
118 module_param(tulip_debug, int, 0);
119 module_param(max_interrupt_work, int, 0);
120 module_param(rx_copybreak, int, 0);
121 module_param(csr0, int, 0);
122 module_param_array(options, int, NULL, 0);
123 module_param_array(full_duplex, int, NULL, 0);
124
125 #define PFX DRV_NAME ": "
126
127 #ifdef TULIP_DEBUG
128 int tulip_debug = TULIP_DEBUG;
129 #else
130 int tulip_debug = 1;
131 #endif
132
133 static void tulip_timer(unsigned long data)
134 {
135 struct net_device *dev = (struct net_device *)data;
136 struct tulip_private *tp = netdev_priv(dev);
137
138 if (netif_running(dev))
139 schedule_work(&tp->media_work);
140 }
141
142 /*
143 * This table use during operation for capabilities and media timer.
144 *
145 * It is indexed via the values in 'enum chips'
146 */
147
148 struct tulip_chip_table tulip_tbl[] = {
149 { }, /* placeholder for array, slot unused currently */
150 { }, /* placeholder for array, slot unused currently */
151
152 /* DC21140 */
153 { "Digital DS21140 Tulip", 128, 0x0001ebef,
154 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_PCI_MWI, tulip_timer,
155 tulip_media_task },
156
157 /* DC21142, DC21143 */
158 { "Digital DS21142/43 Tulip", 128, 0x0801fbff,
159 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI | HAS_NWAY
160 | HAS_INTR_MITIGATION | HAS_PCI_MWI, tulip_timer, t21142_media_task },
161
162 /* LC82C168 */
163 { "Lite-On 82c168 PNIC", 256, 0x0001fbef,
164 HAS_MII | HAS_PNICNWAY, pnic_timer, },
165
166 /* MX98713 */
167 { "Macronix 98713 PMAC", 128, 0x0001ebef,
168 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer, },
169
170 /* MX98715 */
171 { "Macronix 98715 PMAC", 256, 0x0001ebef,
172 HAS_MEDIA_TABLE, mxic_timer, },
173
174 /* MX98725 */
175 { "Macronix 98725 PMAC", 256, 0x0001ebef,
176 HAS_MEDIA_TABLE, mxic_timer, },
177
178 /* AX88140 */
179 { "ASIX AX88140", 128, 0x0001fbff,
180 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | MC_HASH_ONLY
181 | IS_ASIX, tulip_timer, tulip_media_task },
182
183 /* PNIC2 */
184 { "Lite-On PNIC-II", 256, 0x0801fbff,
185 HAS_MII | HAS_NWAY | HAS_8023X | HAS_PCI_MWI, pnic2_timer, },
186
187 /* COMET */
188 { "ADMtek Comet", 256, 0x0001abef,
189 HAS_MII | MC_HASH_ONLY | COMET_MAC_ADDR, comet_timer, },
190
191 /* COMPEX9881 */
192 { "Compex 9881 PMAC", 128, 0x0001ebef,
193 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer, },
194
195 /* I21145 */
196 { "Intel DS21145 Tulip", 128, 0x0801fbff,
197 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI
198 | HAS_NWAY | HAS_PCI_MWI, tulip_timer, tulip_media_task },
199
200 /* DM910X */
201 { "Davicom DM9102/DM9102A", 128, 0x0001ebef,
202 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_ACPI,
203 tulip_timer, tulip_media_task },
204
205 /* RS7112 */
206 { "Conexant LANfinity", 256, 0x0001ebef,
207 HAS_MII | HAS_ACPI, tulip_timer, tulip_media_task },
208
209 };
210
211
212 static struct pci_device_id tulip_pci_tbl[] = {
213 { 0x1011, 0x0009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21140 },
214 { 0x1011, 0x0019, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21143 },
215 { 0x11AD, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, LC82C168 },
216 { 0x10d9, 0x0512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98713 },
217 { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 },
218 /* { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98725 },*/
219 { 0x125B, 0x1400, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AX88140 },
220 { 0x11AD, 0xc115, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PNIC2 },
221 { 0x1317, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
222 { 0x1317, 0x0985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
223 { 0x1317, 0x1985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
224 { 0x1317, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
225 { 0x13D1, 0xAB02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
226 { 0x13D1, 0xAB03, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
227 { 0x13D1, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
228 { 0x104A, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
229 { 0x104A, 0x2774, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
230 { 0x1259, 0xa120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
231 { 0x11F6, 0x9881, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMPEX9881 },
232 { 0x8086, 0x0039, PCI_ANY_ID, PCI_ANY_ID, 0, 0, I21145 },
233 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X },
234 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X },
235 { 0x1113, 0x1216, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
236 { 0x1113, 0x1217, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 },
237 { 0x1113, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
238 { 0x1186, 0x1541, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
239 { 0x1186, 0x1561, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
240 { 0x1186, 0x1591, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
241 { 0x14f1, 0x1803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CONEXANT },
242 { 0x1626, 0x8410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
243 { 0x1737, 0xAB09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
244 { 0x1737, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
245 { 0x17B3, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
246 { 0x10b7, 0x9300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* 3Com 3CSOHO100B-TX */
247 { 0x14ea, 0xab08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* Planex FNW-3602-TX */
248 { 0x1414, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
249 { } /* terminate list */
250 };
251 MODULE_DEVICE_TABLE(pci, tulip_pci_tbl);
252
253
254 /* A full-duplex map for media types. */
255 const char tulip_media_cap[32] =
256 {0,0,0,16, 3,19,16,24, 27,4,7,5, 0,20,23,20, 28,31,0,0, };
257
258 static void tulip_tx_timeout(struct net_device *dev);
259 static void tulip_init_ring(struct net_device *dev);
260 static int tulip_start_xmit(struct sk_buff *skb, struct net_device *dev);
261 static int tulip_open(struct net_device *dev);
262 static int tulip_close(struct net_device *dev);
263 static void tulip_up(struct net_device *dev);
264 static void tulip_down(struct net_device *dev);
265 static struct net_device_stats *tulip_get_stats(struct net_device *dev);
266 static int private_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
267 static void set_rx_mode(struct net_device *dev);
268 #ifdef CONFIG_NET_POLL_CONTROLLER
269 static void poll_tulip(struct net_device *dev);
270 #endif
271
272 static void tulip_set_power_state (struct tulip_private *tp,
273 int sleep, int snooze)
274 {
275 if (tp->flags & HAS_ACPI) {
276 u32 tmp, newtmp;
277 pci_read_config_dword (tp->pdev, CFDD, &tmp);
278 newtmp = tmp & ~(CFDD_Sleep | CFDD_Snooze);
279 if (sleep)
280 newtmp |= CFDD_Sleep;
281 else if (snooze)
282 newtmp |= CFDD_Snooze;
283 if (tmp != newtmp)
284 pci_write_config_dword (tp->pdev, CFDD, newtmp);
285 }
286
287 }
288
289
290 static void tulip_up(struct net_device *dev)
291 {
292 struct tulip_private *tp = netdev_priv(dev);
293 void __iomem *ioaddr = tp->base_addr;
294 int next_tick = 3*HZ;
295 int i;
296
297 #ifdef CONFIG_TULIP_NAPI
298 napi_enable(&tp->napi);
299 #endif
300
301 /* Wake the chip from sleep/snooze mode. */
302 tulip_set_power_state (tp, 0, 0);
303
304 /* On some chip revs we must set the MII/SYM port before the reset!? */
305 if (tp->mii_cnt || (tp->mtable && tp->mtable->has_mii))
306 iowrite32(0x00040000, ioaddr + CSR6);
307
308 /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
309 iowrite32(0x00000001, ioaddr + CSR0);
310 pci_read_config_dword(tp->pdev, PCI_COMMAND, &i); /* flush write */
311 udelay(100);
312
313 /* Deassert reset.
314 Wait the specified 50 PCI cycles after a reset by initializing
315 Tx and Rx queues and the address filter list. */
316 iowrite32(tp->csr0, ioaddr + CSR0);
317 pci_read_config_dword(tp->pdev, PCI_COMMAND, &i); /* flush write */
318 udelay(100);
319
320 if (tulip_debug > 1)
321 printk(KERN_DEBUG "%s: tulip_up(), irq==%d.\n", dev->name, dev->irq);
322
323 iowrite32(tp->rx_ring_dma, ioaddr + CSR3);
324 iowrite32(tp->tx_ring_dma, ioaddr + CSR4);
325 tp->cur_rx = tp->cur_tx = 0;
326 tp->dirty_rx = tp->dirty_tx = 0;
327
328 if (tp->flags & MC_HASH_ONLY) {
329 u32 addr_low = le32_to_cpu(get_unaligned((u32 *)dev->dev_addr));
330 u32 addr_high = le16_to_cpu(get_unaligned((u16 *)(dev->dev_addr+4)));
331 if (tp->chip_id == AX88140) {
332 iowrite32(0, ioaddr + CSR13);
333 iowrite32(addr_low, ioaddr + CSR14);
334 iowrite32(1, ioaddr + CSR13);
335 iowrite32(addr_high, ioaddr + CSR14);
336 } else if (tp->flags & COMET_MAC_ADDR) {
337 iowrite32(addr_low, ioaddr + 0xA4);
338 iowrite32(addr_high, ioaddr + 0xA8);
339 iowrite32(0, ioaddr + 0xAC);
340 iowrite32(0, ioaddr + 0xB0);
341 }
342 } else {
343 /* This is set_rx_mode(), but without starting the transmitter. */
344 u16 *eaddrs = (u16 *)dev->dev_addr;
345 u16 *setup_frm = &tp->setup_frame[15*6];
346 dma_addr_t mapping;
347
348 /* 21140 bug: you must add the broadcast address. */
349 memset(tp->setup_frame, 0xff, sizeof(tp->setup_frame));
350 /* Fill the final entry of the table with our physical address. */
351 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
352 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
353 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
354
355 mapping = pci_map_single(tp->pdev, tp->setup_frame,
356 sizeof(tp->setup_frame),
357 PCI_DMA_TODEVICE);
358 tp->tx_buffers[tp->cur_tx].skb = NULL;
359 tp->tx_buffers[tp->cur_tx].mapping = mapping;
360
361 /* Put the setup frame on the Tx list. */
362 tp->tx_ring[tp->cur_tx].length = cpu_to_le32(0x08000000 | 192);
363 tp->tx_ring[tp->cur_tx].buffer1 = cpu_to_le32(mapping);
364 tp->tx_ring[tp->cur_tx].status = cpu_to_le32(DescOwned);
365
366 tp->cur_tx++;
367 }
368
369 tp->saved_if_port = dev->if_port;
370 if (dev->if_port == 0)
371 dev->if_port = tp->default_port;
372
373 /* Allow selecting a default media. */
374 i = 0;
375 if (tp->mtable == NULL)
376 goto media_picked;
377 if (dev->if_port) {
378 int looking_for = tulip_media_cap[dev->if_port] & MediaIsMII ? 11 :
379 (dev->if_port == 12 ? 0 : dev->if_port);
380 for (i = 0; i < tp->mtable->leafcount; i++)
381 if (tp->mtable->mleaf[i].media == looking_for) {
382 printk(KERN_INFO "%s: Using user-specified media %s.\n",
383 dev->name, medianame[dev->if_port]);
384 goto media_picked;
385 }
386 }
387 if ((tp->mtable->defaultmedia & 0x0800) == 0) {
388 int looking_for = tp->mtable->defaultmedia & MEDIA_MASK;
389 for (i = 0; i < tp->mtable->leafcount; i++)
390 if (tp->mtable->mleaf[i].media == looking_for) {
391 printk(KERN_INFO "%s: Using EEPROM-set media %s.\n",
392 dev->name, medianame[looking_for]);
393 goto media_picked;
394 }
395 }
396 /* Start sensing first non-full-duplex media. */
397 for (i = tp->mtable->leafcount - 1;
398 (tulip_media_cap[tp->mtable->mleaf[i].media] & MediaAlwaysFD) && i > 0; i--)
399 ;
400 media_picked:
401
402 tp->csr6 = 0;
403 tp->cur_index = i;
404 tp->nwayset = 0;
405
406 if (dev->if_port) {
407 if (tp->chip_id == DC21143 &&
408 (tulip_media_cap[dev->if_port] & MediaIsMII)) {
409 /* We must reset the media CSRs when we force-select MII mode. */
410 iowrite32(0x0000, ioaddr + CSR13);
411 iowrite32(0x0000, ioaddr + CSR14);
412 iowrite32(0x0008, ioaddr + CSR15);
413 }
414 tulip_select_media(dev, 1);
415 } else if (tp->chip_id == DC21142) {
416 if (tp->mii_cnt) {
417 tulip_select_media(dev, 1);
418 if (tulip_debug > 1)
419 printk(KERN_INFO "%s: Using MII transceiver %d, status "
420 "%4.4x.\n",
421 dev->name, tp->phys[0], tulip_mdio_read(dev, tp->phys[0], 1));
422 iowrite32(csr6_mask_defstate, ioaddr + CSR6);
423 tp->csr6 = csr6_mask_hdcap;
424 dev->if_port = 11;
425 iowrite32(0x0000, ioaddr + CSR13);
426 iowrite32(0x0000, ioaddr + CSR14);
427 } else
428 t21142_start_nway(dev);
429 } else if (tp->chip_id == PNIC2) {
430 /* for initial startup advertise 10/100 Full and Half */
431 tp->sym_advertise = 0x01E0;
432 /* enable autonegotiate end interrupt */
433 iowrite32(ioread32(ioaddr+CSR5)| 0x00008010, ioaddr + CSR5);
434 iowrite32(ioread32(ioaddr+CSR7)| 0x00008010, ioaddr + CSR7);
435 pnic2_start_nway(dev);
436 } else if (tp->chip_id == LC82C168 && ! tp->medialock) {
437 if (tp->mii_cnt) {
438 dev->if_port = 11;
439 tp->csr6 = 0x814C0000 | (tp->full_duplex ? 0x0200 : 0);
440 iowrite32(0x0001, ioaddr + CSR15);
441 } else if (ioread32(ioaddr + CSR5) & TPLnkPass)
442 pnic_do_nway(dev);
443 else {
444 /* Start with 10mbps to do autonegotiation. */
445 iowrite32(0x32, ioaddr + CSR12);
446 tp->csr6 = 0x00420000;
447 iowrite32(0x0001B078, ioaddr + 0xB8);
448 iowrite32(0x0201B078, ioaddr + 0xB8);
449 next_tick = 1*HZ;
450 }
451 } else if ((tp->chip_id == MX98713 || tp->chip_id == COMPEX9881)
452 && ! tp->medialock) {
453 dev->if_port = 0;
454 tp->csr6 = 0x01880000 | (tp->full_duplex ? 0x0200 : 0);
455 iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80);
456 } else if (tp->chip_id == MX98715 || tp->chip_id == MX98725) {
457 /* Provided by BOLO, Macronix - 12/10/1998. */
458 dev->if_port = 0;
459 tp->csr6 = 0x01a80200;
460 iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80);
461 iowrite32(0x11000 | ioread16(ioaddr + 0xa0), ioaddr + 0xa0);
462 } else if (tp->chip_id == COMET || tp->chip_id == CONEXANT) {
463 /* Enable automatic Tx underrun recovery. */
464 iowrite32(ioread32(ioaddr + 0x88) | 1, ioaddr + 0x88);
465 dev->if_port = tp->mii_cnt ? 11 : 0;
466 tp->csr6 = 0x00040000;
467 } else if (tp->chip_id == AX88140) {
468 tp->csr6 = tp->mii_cnt ? 0x00040100 : 0x00000100;
469 } else
470 tulip_select_media(dev, 1);
471
472 /* Start the chip's Tx to process setup frame. */
473 tulip_stop_rxtx(tp);
474 barrier();
475 udelay(5);
476 iowrite32(tp->csr6 | TxOn, ioaddr + CSR6);
477
478 /* Enable interrupts by setting the interrupt mask. */
479 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR5);
480 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7);
481 tulip_start_rxtx(tp);
482 iowrite32(0, ioaddr + CSR2); /* Rx poll demand */
483
484 if (tulip_debug > 2) {
485 printk(KERN_DEBUG "%s: Done tulip_up(), CSR0 %8.8x, CSR5 %8.8x CSR6 %8.8x.\n",
486 dev->name, ioread32(ioaddr + CSR0), ioread32(ioaddr + CSR5),
487 ioread32(ioaddr + CSR6));
488 }
489
490 /* Set the timer to switch to check for link beat and perhaps switch
491 to an alternate media type. */
492 tp->timer.expires = RUN_AT(next_tick);
493 add_timer(&tp->timer);
494 #ifdef CONFIG_TULIP_NAPI
495 init_timer(&tp->oom_timer);
496 tp->oom_timer.data = (unsigned long)dev;
497 tp->oom_timer.function = oom_timer;
498 #endif
499 }
500
501 static int
502 tulip_open(struct net_device *dev)
503 {
504 int retval;
505
506 if ((retval = request_irq(dev->irq, &tulip_interrupt, IRQF_SHARED, dev->name, dev)))
507 return retval;
508
509 tulip_init_ring (dev);
510
511 tulip_up (dev);
512
513 netif_start_queue (dev);
514
515 return 0;
516 }
517
518
519 static void tulip_tx_timeout(struct net_device *dev)
520 {
521 struct tulip_private *tp = netdev_priv(dev);
522 void __iomem *ioaddr = tp->base_addr;
523 unsigned long flags;
524
525 spin_lock_irqsave (&tp->lock, flags);
526
527 if (tulip_media_cap[dev->if_port] & MediaIsMII) {
528 /* Do nothing -- the media monitor should handle this. */
529 if (tulip_debug > 1)
530 printk(KERN_WARNING "%s: Transmit timeout using MII device.\n",
531 dev->name);
532 } else if (tp->chip_id == DC21140 || tp->chip_id == DC21142
533 || tp->chip_id == MX98713 || tp->chip_id == COMPEX9881
534 || tp->chip_id == DM910X) {
535 printk(KERN_WARNING "%s: 21140 transmit timed out, status %8.8x, "
536 "SIA %8.8x %8.8x %8.8x %8.8x, resetting...\n",
537 dev->name, ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12),
538 ioread32(ioaddr + CSR13), ioread32(ioaddr + CSR14), ioread32(ioaddr + CSR15));
539 tp->timeout_recovery = 1;
540 schedule_work(&tp->media_work);
541 goto out_unlock;
542 } else if (tp->chip_id == PNIC2) {
543 printk(KERN_WARNING "%s: PNIC2 transmit timed out, status %8.8x, "
544 "CSR6/7 %8.8x / %8.8x CSR12 %8.8x, resetting...\n",
545 dev->name, (int)ioread32(ioaddr + CSR5), (int)ioread32(ioaddr + CSR6),
546 (int)ioread32(ioaddr + CSR7), (int)ioread32(ioaddr + CSR12));
547 } else {
548 printk(KERN_WARNING "%s: Transmit timed out, status %8.8x, CSR12 "
549 "%8.8x, resetting...\n",
550 dev->name, ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12));
551 dev->if_port = 0;
552 }
553
554 #if defined(way_too_many_messages)
555 if (tulip_debug > 3) {
556 int i;
557 for (i = 0; i < RX_RING_SIZE; i++) {
558 u8 *buf = (u8 *)(tp->rx_ring[i].buffer1);
559 int j;
560 printk(KERN_DEBUG "%2d: %8.8x %8.8x %8.8x %8.8x "
561 "%2.2x %2.2x %2.2x.\n",
562 i, (unsigned int)tp->rx_ring[i].status,
563 (unsigned int)tp->rx_ring[i].length,
564 (unsigned int)tp->rx_ring[i].buffer1,
565 (unsigned int)tp->rx_ring[i].buffer2,
566 buf[0], buf[1], buf[2]);
567 for (j = 0; buf[j] != 0xee && j < 1600; j++)
568 if (j < 100) printk(" %2.2x", buf[j]);
569 printk(" j=%d.\n", j);
570 }
571 printk(KERN_DEBUG " Rx ring %8.8x: ", (int)tp->rx_ring);
572 for (i = 0; i < RX_RING_SIZE; i++)
573 printk(" %8.8x", (unsigned int)tp->rx_ring[i].status);
574 printk("\n" KERN_DEBUG " Tx ring %8.8x: ", (int)tp->tx_ring);
575 for (i = 0; i < TX_RING_SIZE; i++)
576 printk(" %8.8x", (unsigned int)tp->tx_ring[i].status);
577 printk("\n");
578 }
579 #endif
580
581 tulip_tx_timeout_complete(tp, ioaddr);
582
583 out_unlock:
584 spin_unlock_irqrestore (&tp->lock, flags);
585 dev->trans_start = jiffies;
586 netif_wake_queue (dev);
587 }
588
589
590 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
591 static void tulip_init_ring(struct net_device *dev)
592 {
593 struct tulip_private *tp = netdev_priv(dev);
594 int i;
595
596 tp->susp_rx = 0;
597 tp->ttimer = 0;
598 tp->nir = 0;
599
600 for (i = 0; i < RX_RING_SIZE; i++) {
601 tp->rx_ring[i].status = 0x00000000;
602 tp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ);
603 tp->rx_ring[i].buffer2 = cpu_to_le32(tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * (i + 1));
604 tp->rx_buffers[i].skb = NULL;
605 tp->rx_buffers[i].mapping = 0;
606 }
607 /* Mark the last entry as wrapping the ring. */
608 tp->rx_ring[i-1].length = cpu_to_le32(PKT_BUF_SZ | DESC_RING_WRAP);
609 tp->rx_ring[i-1].buffer2 = cpu_to_le32(tp->rx_ring_dma);
610
611 for (i = 0; i < RX_RING_SIZE; i++) {
612 dma_addr_t mapping;
613
614 /* Note the receive buffer must be longword aligned.
615 dev_alloc_skb() provides 16 byte alignment. But do *not*
616 use skb_reserve() to align the IP header! */
617 struct sk_buff *skb = dev_alloc_skb(PKT_BUF_SZ);
618 tp->rx_buffers[i].skb = skb;
619 if (skb == NULL)
620 break;
621 mapping = pci_map_single(tp->pdev, skb->data,
622 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
623 tp->rx_buffers[i].mapping = mapping;
624 skb->dev = dev; /* Mark as being used by this device. */
625 tp->rx_ring[i].status = cpu_to_le32(DescOwned); /* Owned by Tulip chip */
626 tp->rx_ring[i].buffer1 = cpu_to_le32(mapping);
627 }
628 tp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
629
630 /* The Tx buffer descriptor is filled in as needed, but we
631 do need to clear the ownership bit. */
632 for (i = 0; i < TX_RING_SIZE; i++) {
633 tp->tx_buffers[i].skb = NULL;
634 tp->tx_buffers[i].mapping = 0;
635 tp->tx_ring[i].status = 0x00000000;
636 tp->tx_ring[i].buffer2 = cpu_to_le32(tp->tx_ring_dma + sizeof(struct tulip_tx_desc) * (i + 1));
637 }
638 tp->tx_ring[i-1].buffer2 = cpu_to_le32(tp->tx_ring_dma);
639 }
640
641 static int
642 tulip_start_xmit(struct sk_buff *skb, struct net_device *dev)
643 {
644 struct tulip_private *tp = netdev_priv(dev);
645 int entry;
646 u32 flag;
647 dma_addr_t mapping;
648
649 spin_lock_irq(&tp->lock);
650
651 /* Calculate the next Tx descriptor entry. */
652 entry = tp->cur_tx % TX_RING_SIZE;
653
654 tp->tx_buffers[entry].skb = skb;
655 mapping = pci_map_single(tp->pdev, skb->data,
656 skb->len, PCI_DMA_TODEVICE);
657 tp->tx_buffers[entry].mapping = mapping;
658 tp->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
659
660 if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE/2) {/* Typical path */
661 flag = 0x60000000; /* No interrupt */
662 } else if (tp->cur_tx - tp->dirty_tx == TX_RING_SIZE/2) {
663 flag = 0xe0000000; /* Tx-done intr. */
664 } else if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE - 2) {
665 flag = 0x60000000; /* No Tx-done intr. */
666 } else { /* Leave room for set_rx_mode() to fill entries. */
667 flag = 0xe0000000; /* Tx-done intr. */
668 netif_stop_queue(dev);
669 }
670 if (entry == TX_RING_SIZE-1)
671 flag = 0xe0000000 | DESC_RING_WRAP;
672
673 tp->tx_ring[entry].length = cpu_to_le32(skb->len | flag);
674 /* if we were using Transmit Automatic Polling, we would need a
675 * wmb() here. */
676 tp->tx_ring[entry].status = cpu_to_le32(DescOwned);
677 wmb();
678
679 tp->cur_tx++;
680
681 /* Trigger an immediate transmit demand. */
682 iowrite32(0, tp->base_addr + CSR1);
683
684 spin_unlock_irq(&tp->lock);
685
686 dev->trans_start = jiffies;
687
688 return 0;
689 }
690
691 static void tulip_clean_tx_ring(struct tulip_private *tp)
692 {
693 unsigned int dirty_tx;
694
695 for (dirty_tx = tp->dirty_tx ; tp->cur_tx - dirty_tx > 0;
696 dirty_tx++) {
697 int entry = dirty_tx % TX_RING_SIZE;
698 int status = le32_to_cpu(tp->tx_ring[entry].status);
699
700 if (status < 0) {
701 tp->stats.tx_errors++; /* It wasn't Txed */
702 tp->tx_ring[entry].status = 0;
703 }
704
705 /* Check for Tx filter setup frames. */
706 if (tp->tx_buffers[entry].skb == NULL) {
707 /* test because dummy frames not mapped */
708 if (tp->tx_buffers[entry].mapping)
709 pci_unmap_single(tp->pdev,
710 tp->tx_buffers[entry].mapping,
711 sizeof(tp->setup_frame),
712 PCI_DMA_TODEVICE);
713 continue;
714 }
715
716 pci_unmap_single(tp->pdev, tp->tx_buffers[entry].mapping,
717 tp->tx_buffers[entry].skb->len,
718 PCI_DMA_TODEVICE);
719
720 /* Free the original skb. */
721 dev_kfree_skb_irq(tp->tx_buffers[entry].skb);
722 tp->tx_buffers[entry].skb = NULL;
723 tp->tx_buffers[entry].mapping = 0;
724 }
725 }
726
727 static void tulip_down (struct net_device *dev)
728 {
729 struct tulip_private *tp = netdev_priv(dev);
730 void __iomem *ioaddr = tp->base_addr;
731 unsigned long flags;
732
733 flush_scheduled_work();
734
735 #ifdef CONFIG_TULIP_NAPI
736 napi_disable(&tp->napi);
737 #endif
738
739 del_timer_sync (&tp->timer);
740 #ifdef CONFIG_TULIP_NAPI
741 del_timer_sync (&tp->oom_timer);
742 #endif
743 spin_lock_irqsave (&tp->lock, flags);
744
745 /* Disable interrupts by clearing the interrupt mask. */
746 iowrite32 (0x00000000, ioaddr + CSR7);
747
748 /* Stop the Tx and Rx processes. */
749 tulip_stop_rxtx(tp);
750
751 /* prepare receive buffers */
752 tulip_refill_rx(dev);
753
754 /* release any unconsumed transmit buffers */
755 tulip_clean_tx_ring(tp);
756
757 if (ioread32 (ioaddr + CSR6) != 0xffffffff)
758 tp->stats.rx_missed_errors += ioread32 (ioaddr + CSR8) & 0xffff;
759
760 spin_unlock_irqrestore (&tp->lock, flags);
761
762 init_timer(&tp->timer);
763 tp->timer.data = (unsigned long)dev;
764 tp->timer.function = tulip_tbl[tp->chip_id].media_timer;
765
766 dev->if_port = tp->saved_if_port;
767
768 /* Leave the driver in snooze, not sleep, mode. */
769 tulip_set_power_state (tp, 0, 1);
770 }
771
772
773 static int tulip_close (struct net_device *dev)
774 {
775 struct tulip_private *tp = netdev_priv(dev);
776 void __iomem *ioaddr = tp->base_addr;
777 int i;
778
779 netif_stop_queue (dev);
780
781 tulip_down (dev);
782
783 if (tulip_debug > 1)
784 printk (KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n",
785 dev->name, ioread32 (ioaddr + CSR5));
786
787 free_irq (dev->irq, dev);
788
789 /* Free all the skbuffs in the Rx queue. */
790 for (i = 0; i < RX_RING_SIZE; i++) {
791 struct sk_buff *skb = tp->rx_buffers[i].skb;
792 dma_addr_t mapping = tp->rx_buffers[i].mapping;
793
794 tp->rx_buffers[i].skb = NULL;
795 tp->rx_buffers[i].mapping = 0;
796
797 tp->rx_ring[i].status = 0; /* Not owned by Tulip chip. */
798 tp->rx_ring[i].length = 0;
799 tp->rx_ring[i].buffer1 = 0xBADF00D0; /* An invalid address. */
800 if (skb) {
801 pci_unmap_single(tp->pdev, mapping, PKT_BUF_SZ,
802 PCI_DMA_FROMDEVICE);
803 dev_kfree_skb (skb);
804 }
805 }
806 for (i = 0; i < TX_RING_SIZE; i++) {
807 struct sk_buff *skb = tp->tx_buffers[i].skb;
808
809 if (skb != NULL) {
810 pci_unmap_single(tp->pdev, tp->tx_buffers[i].mapping,
811 skb->len, PCI_DMA_TODEVICE);
812 dev_kfree_skb (skb);
813 }
814 tp->tx_buffers[i].skb = NULL;
815 tp->tx_buffers[i].mapping = 0;
816 }
817
818 return 0;
819 }
820
821 static struct net_device_stats *tulip_get_stats(struct net_device *dev)
822 {
823 struct tulip_private *tp = netdev_priv(dev);
824 void __iomem *ioaddr = tp->base_addr;
825
826 if (netif_running(dev)) {
827 unsigned long flags;
828
829 spin_lock_irqsave (&tp->lock, flags);
830
831 tp->stats.rx_missed_errors += ioread32(ioaddr + CSR8) & 0xffff;
832
833 spin_unlock_irqrestore(&tp->lock, flags);
834 }
835
836 return &tp->stats;
837 }
838
839
840 static void tulip_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
841 {
842 struct tulip_private *np = netdev_priv(dev);
843 strcpy(info->driver, DRV_NAME);
844 strcpy(info->version, DRV_VERSION);
845 strcpy(info->bus_info, pci_name(np->pdev));
846 }
847
848 static const struct ethtool_ops ops = {
849 .get_drvinfo = tulip_get_drvinfo
850 };
851
852 /* Provide ioctl() calls to examine the MII xcvr state. */
853 static int private_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
854 {
855 struct tulip_private *tp = netdev_priv(dev);
856 void __iomem *ioaddr = tp->base_addr;
857 struct mii_ioctl_data *data = if_mii(rq);
858 const unsigned int phy_idx = 0;
859 int phy = tp->phys[phy_idx] & 0x1f;
860 unsigned int regnum = data->reg_num;
861
862 switch (cmd) {
863 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
864 if (tp->mii_cnt)
865 data->phy_id = phy;
866 else if (tp->flags & HAS_NWAY)
867 data->phy_id = 32;
868 else if (tp->chip_id == COMET)
869 data->phy_id = 1;
870 else
871 return -ENODEV;
872
873 case SIOCGMIIREG: /* Read MII PHY register. */
874 if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) {
875 int csr12 = ioread32 (ioaddr + CSR12);
876 int csr14 = ioread32 (ioaddr + CSR14);
877 switch (regnum) {
878 case 0:
879 if (((csr14<<5) & 0x1000) ||
880 (dev->if_port == 5 && tp->nwayset))
881 data->val_out = 0x1000;
882 else
883 data->val_out = (tulip_media_cap[dev->if_port]&MediaIs100 ? 0x2000 : 0)
884 | (tulip_media_cap[dev->if_port]&MediaIsFD ? 0x0100 : 0);
885 break;
886 case 1:
887 data->val_out =
888 0x1848 +
889 ((csr12&0x7000) == 0x5000 ? 0x20 : 0) +
890 ((csr12&0x06) == 6 ? 0 : 4);
891 data->val_out |= 0x6048;
892 break;
893 case 4:
894 /* Advertised value, bogus 10baseTx-FD value from CSR6. */
895 data->val_out =
896 ((ioread32(ioaddr + CSR6) >> 3) & 0x0040) +
897 ((csr14 >> 1) & 0x20) + 1;
898 data->val_out |= ((csr14 >> 9) & 0x03C0);
899 break;
900 case 5: data->val_out = tp->lpar; break;
901 default: data->val_out = 0; break;
902 }
903 } else {
904 data->val_out = tulip_mdio_read (dev, data->phy_id & 0x1f, regnum);
905 }
906 return 0;
907
908 case SIOCSMIIREG: /* Write MII PHY register. */
909 if (!capable (CAP_NET_ADMIN))
910 return -EPERM;
911 if (regnum & ~0x1f)
912 return -EINVAL;
913 if (data->phy_id == phy) {
914 u16 value = data->val_in;
915 switch (regnum) {
916 case 0: /* Check for autonegotiation on or reset. */
917 tp->full_duplex_lock = (value & 0x9000) ? 0 : 1;
918 if (tp->full_duplex_lock)
919 tp->full_duplex = (value & 0x0100) ? 1 : 0;
920 break;
921 case 4:
922 tp->advertising[phy_idx] =
923 tp->mii_advertise = data->val_in;
924 break;
925 }
926 }
927 if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) {
928 u16 value = data->val_in;
929 if (regnum == 0) {
930 if ((value & 0x1200) == 0x1200) {
931 if (tp->chip_id == PNIC2) {
932 pnic2_start_nway (dev);
933 } else {
934 t21142_start_nway (dev);
935 }
936 }
937 } else if (regnum == 4)
938 tp->sym_advertise = value;
939 } else {
940 tulip_mdio_write (dev, data->phy_id & 0x1f, regnum, data->val_in);
941 }
942 return 0;
943 default:
944 return -EOPNOTSUPP;
945 }
946
947 return -EOPNOTSUPP;
948 }
949
950
951 /* Set or clear the multicast filter for this adaptor.
952 Note that we only use exclusion around actually queueing the
953 new frame, not around filling tp->setup_frame. This is non-deterministic
954 when re-entered but still correct. */
955
956 #undef set_bit_le
957 #define set_bit_le(i,p) do { ((char *)(p))[(i)/8] |= (1<<((i)%8)); } while(0)
958
959 static void build_setup_frame_hash(u16 *setup_frm, struct net_device *dev)
960 {
961 struct tulip_private *tp = netdev_priv(dev);
962 u16 hash_table[32];
963 struct dev_mc_list *mclist;
964 int i;
965 u16 *eaddrs;
966
967 memset(hash_table, 0, sizeof(hash_table));
968 set_bit_le(255, hash_table); /* Broadcast entry */
969 /* This should work on big-endian machines as well. */
970 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
971 i++, mclist = mclist->next) {
972 int index = ether_crc_le(ETH_ALEN, mclist->dmi_addr) & 0x1ff;
973
974 set_bit_le(index, hash_table);
975
976 }
977 for (i = 0; i < 32; i++) {
978 *setup_frm++ = hash_table[i];
979 *setup_frm++ = hash_table[i];
980 }
981 setup_frm = &tp->setup_frame[13*6];
982
983 /* Fill the final entry with our physical address. */
984 eaddrs = (u16 *)dev->dev_addr;
985 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
986 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
987 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
988 }
989
990 static void build_setup_frame_perfect(u16 *setup_frm, struct net_device *dev)
991 {
992 struct tulip_private *tp = netdev_priv(dev);
993 struct dev_mc_list *mclist;
994 int i;
995 u16 *eaddrs;
996
997 /* We have <= 14 addresses so we can use the wonderful
998 16 address perfect filtering of the Tulip. */
999 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
1000 i++, mclist = mclist->next) {
1001 eaddrs = (u16 *)mclist->dmi_addr;
1002 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1003 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1004 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1005 }
1006 /* Fill the unused entries with the broadcast address. */
1007 memset(setup_frm, 0xff, (15-i)*12);
1008 setup_frm = &tp->setup_frame[15*6];
1009
1010 /* Fill the final entry with our physical address. */
1011 eaddrs = (u16 *)dev->dev_addr;
1012 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
1013 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
1014 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
1015 }
1016
1017
1018 static void set_rx_mode(struct net_device *dev)
1019 {
1020 struct tulip_private *tp = netdev_priv(dev);
1021 void __iomem *ioaddr = tp->base_addr;
1022 int csr6;
1023
1024 csr6 = ioread32(ioaddr + CSR6) & ~0x00D5;
1025
1026 tp->csr6 &= ~0x00D5;
1027 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1028 tp->csr6 |= AcceptAllMulticast | AcceptAllPhys;
1029 csr6 |= AcceptAllMulticast | AcceptAllPhys;
1030 } else if ((dev->mc_count > 1000) || (dev->flags & IFF_ALLMULTI)) {
1031 /* Too many to filter well -- accept all multicasts. */
1032 tp->csr6 |= AcceptAllMulticast;
1033 csr6 |= AcceptAllMulticast;
1034 } else if (tp->flags & MC_HASH_ONLY) {
1035 /* Some work-alikes have only a 64-entry hash filter table. */
1036 /* Should verify correctness on big-endian/__powerpc__ */
1037 struct dev_mc_list *mclist;
1038 int i;
1039 if (dev->mc_count > 64) { /* Arbitrary non-effective limit. */
1040 tp->csr6 |= AcceptAllMulticast;
1041 csr6 |= AcceptAllMulticast;
1042 } else {
1043 u32 mc_filter[2] = {0, 0}; /* Multicast hash filter */
1044 int filterbit;
1045 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1046 i++, mclist = mclist->next) {
1047 if (tp->flags & COMET_MAC_ADDR)
1048 filterbit = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
1049 else
1050 filterbit = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1051 filterbit &= 0x3f;
1052 mc_filter[filterbit >> 5] |= 1 << (filterbit & 31);
1053 if (tulip_debug > 2) {
1054 printk(KERN_INFO "%s: Added filter for %2.2x:%2.2x:%2.2x:"
1055 "%2.2x:%2.2x:%2.2x %8.8x bit %d.\n", dev->name,
1056 mclist->dmi_addr[0], mclist->dmi_addr[1],
1057 mclist->dmi_addr[2], mclist->dmi_addr[3],
1058 mclist->dmi_addr[4], mclist->dmi_addr[5],
1059 ether_crc(ETH_ALEN, mclist->dmi_addr), filterbit);
1060 }
1061 }
1062 if (mc_filter[0] == tp->mc_filter[0] &&
1063 mc_filter[1] == tp->mc_filter[1])
1064 ; /* No change. */
1065 else if (tp->flags & IS_ASIX) {
1066 iowrite32(2, ioaddr + CSR13);
1067 iowrite32(mc_filter[0], ioaddr + CSR14);
1068 iowrite32(3, ioaddr + CSR13);
1069 iowrite32(mc_filter[1], ioaddr + CSR14);
1070 } else if (tp->flags & COMET_MAC_ADDR) {
1071 iowrite32(mc_filter[0], ioaddr + 0xAC);
1072 iowrite32(mc_filter[1], ioaddr + 0xB0);
1073 }
1074 tp->mc_filter[0] = mc_filter[0];
1075 tp->mc_filter[1] = mc_filter[1];
1076 }
1077 } else {
1078 unsigned long flags;
1079 u32 tx_flags = 0x08000000 | 192;
1080
1081 /* Note that only the low-address shortword of setup_frame is valid!
1082 The values are doubled for big-endian architectures. */
1083 if (dev->mc_count > 14) { /* Must use a multicast hash table. */
1084 build_setup_frame_hash(tp->setup_frame, dev);
1085 tx_flags = 0x08400000 | 192;
1086 } else {
1087 build_setup_frame_perfect(tp->setup_frame, dev);
1088 }
1089
1090 spin_lock_irqsave(&tp->lock, flags);
1091
1092 if (tp->cur_tx - tp->dirty_tx > TX_RING_SIZE - 2) {
1093 /* Same setup recently queued, we need not add it. */
1094 } else {
1095 unsigned int entry;
1096 int dummy = -1;
1097
1098 /* Now add this frame to the Tx list. */
1099
1100 entry = tp->cur_tx++ % TX_RING_SIZE;
1101
1102 if (entry != 0) {
1103 /* Avoid a chip errata by prefixing a dummy entry. */
1104 tp->tx_buffers[entry].skb = NULL;
1105 tp->tx_buffers[entry].mapping = 0;
1106 tp->tx_ring[entry].length =
1107 (entry == TX_RING_SIZE-1) ? cpu_to_le32(DESC_RING_WRAP) : 0;
1108 tp->tx_ring[entry].buffer1 = 0;
1109 /* Must set DescOwned later to avoid race with chip */
1110 dummy = entry;
1111 entry = tp->cur_tx++ % TX_RING_SIZE;
1112
1113 }
1114
1115 tp->tx_buffers[entry].skb = NULL;
1116 tp->tx_buffers[entry].mapping =
1117 pci_map_single(tp->pdev, tp->setup_frame,
1118 sizeof(tp->setup_frame),
1119 PCI_DMA_TODEVICE);
1120 /* Put the setup frame on the Tx list. */
1121 if (entry == TX_RING_SIZE-1)
1122 tx_flags |= DESC_RING_WRAP; /* Wrap ring. */
1123 tp->tx_ring[entry].length = cpu_to_le32(tx_flags);
1124 tp->tx_ring[entry].buffer1 =
1125 cpu_to_le32(tp->tx_buffers[entry].mapping);
1126 tp->tx_ring[entry].status = cpu_to_le32(DescOwned);
1127 if (dummy >= 0)
1128 tp->tx_ring[dummy].status = cpu_to_le32(DescOwned);
1129 if (tp->cur_tx - tp->dirty_tx >= TX_RING_SIZE - 2)
1130 netif_stop_queue(dev);
1131
1132 /* Trigger an immediate transmit demand. */
1133 iowrite32(0, ioaddr + CSR1);
1134 }
1135
1136 spin_unlock_irqrestore(&tp->lock, flags);
1137 }
1138
1139 iowrite32(csr6, ioaddr + CSR6);
1140 }
1141
1142 #ifdef CONFIG_TULIP_MWI
1143 static void __devinit tulip_mwi_config (struct pci_dev *pdev,
1144 struct net_device *dev)
1145 {
1146 struct tulip_private *tp = netdev_priv(dev);
1147 u8 cache;
1148 u16 pci_command;
1149 u32 csr0;
1150
1151 if (tulip_debug > 3)
1152 printk(KERN_DEBUG "%s: tulip_mwi_config()\n", pci_name(pdev));
1153
1154 tp->csr0 = csr0 = 0;
1155
1156 /* if we have any cache line size at all, we can do MRM */
1157 csr0 |= MRM;
1158
1159 /* ...and barring hardware bugs, MWI */
1160 if (!(tp->chip_id == DC21143 && tp->revision == 65))
1161 csr0 |= MWI;
1162
1163 /* set or disable MWI in the standard PCI command bit.
1164 * Check for the case where mwi is desired but not available
1165 */
1166 if (csr0 & MWI) pci_try_set_mwi(pdev);
1167 else pci_clear_mwi(pdev);
1168
1169 /* read result from hardware (in case bit refused to enable) */
1170 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1171 if ((csr0 & MWI) && (!(pci_command & PCI_COMMAND_INVALIDATE)))
1172 csr0 &= ~MWI;
1173
1174 /* if cache line size hardwired to zero, no MWI */
1175 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache);
1176 if ((csr0 & MWI) && (cache == 0)) {
1177 csr0 &= ~MWI;
1178 pci_clear_mwi(pdev);
1179 }
1180
1181 /* assign per-cacheline-size cache alignment and
1182 * burst length values
1183 */
1184 switch (cache) {
1185 case 8:
1186 csr0 |= MRL | (1 << CALShift) | (16 << BurstLenShift);
1187 break;
1188 case 16:
1189 csr0 |= MRL | (2 << CALShift) | (16 << BurstLenShift);
1190 break;
1191 case 32:
1192 csr0 |= MRL | (3 << CALShift) | (32 << BurstLenShift);
1193 break;
1194 default:
1195 cache = 0;
1196 break;
1197 }
1198
1199 /* if we have a good cache line size, we by now have a good
1200 * csr0, so save it and exit
1201 */
1202 if (cache)
1203 goto out;
1204
1205 /* we don't have a good csr0 or cache line size, disable MWI */
1206 if (csr0 & MWI) {
1207 pci_clear_mwi(pdev);
1208 csr0 &= ~MWI;
1209 }
1210
1211 /* sane defaults for burst length and cache alignment
1212 * originally from de4x5 driver
1213 */
1214 csr0 |= (8 << BurstLenShift) | (1 << CALShift);
1215
1216 out:
1217 tp->csr0 = csr0;
1218 if (tulip_debug > 2)
1219 printk(KERN_DEBUG "%s: MWI config cacheline=%d, csr0=%08x\n",
1220 pci_name(pdev), cache, csr0);
1221 }
1222 #endif
1223
1224 /*
1225 * Chips that have the MRM/reserved bit quirk and the burst quirk. That
1226 * is the DM910X and the on chip ULi devices
1227 */
1228
1229 static int tulip_uli_dm_quirk(struct pci_dev *pdev)
1230 {
1231 if (pdev->vendor == 0x1282 && pdev->device == 0x9102)
1232 return 1;
1233 return 0;
1234 }
1235
1236 static int __devinit tulip_init_one (struct pci_dev *pdev,
1237 const struct pci_device_id *ent)
1238 {
1239 struct tulip_private *tp;
1240 /* See note below on the multiport cards. */
1241 static unsigned char last_phys_addr[6] = {0x00, 'L', 'i', 'n', 'u', 'x'};
1242 static struct pci_device_id early_486_chipsets[] = {
1243 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82424) },
1244 { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496) },
1245 { },
1246 };
1247 static int last_irq;
1248 static int multiport_cnt; /* For four-port boards w/one EEPROM */
1249 int i, irq;
1250 unsigned short sum;
1251 unsigned char *ee_data;
1252 struct net_device *dev;
1253 void __iomem *ioaddr;
1254 static int board_idx = -1;
1255 int chip_idx = ent->driver_data;
1256 const char *chip_name = tulip_tbl[chip_idx].chip_name;
1257 unsigned int eeprom_missing = 0;
1258 unsigned int force_csr0 = 0;
1259
1260 #ifndef MODULE
1261 static int did_version; /* Already printed version info. */
1262 if (tulip_debug > 0 && did_version++ == 0)
1263 printk (KERN_INFO "%s", version);
1264 #endif
1265
1266 board_idx++;
1267
1268 /*
1269 * Lan media wire a tulip chip to a wan interface. Needs a very
1270 * different driver (lmc driver)
1271 */
1272
1273 if (pdev->subsystem_vendor == PCI_VENDOR_ID_LMC) {
1274 printk (KERN_ERR PFX "skipping LMC card.\n");
1275 return -ENODEV;
1276 }
1277
1278 /*
1279 * Early DM9100's need software CRC and the DMFE driver
1280 */
1281
1282 if (pdev->vendor == 0x1282 && pdev->device == 0x9100)
1283 {
1284 /* Read Chip revision */
1285 if (pdev->revision < 0x30)
1286 {
1287 printk(KERN_ERR PFX "skipping early DM9100 with Crc bug (use dmfe)\n");
1288 return -ENODEV;
1289 }
1290 }
1291
1292 /*
1293 * Looks for early PCI chipsets where people report hangs
1294 * without the workarounds being on.
1295 */
1296
1297 /* 1. Intel Saturn. Switch to 8 long words burst, 8 long word cache
1298 aligned. Aries might need this too. The Saturn errata are not
1299 pretty reading but thankfully it's an old 486 chipset.
1300
1301 2. The dreaded SiS496 486 chipset. Same workaround as Intel
1302 Saturn.
1303 */
1304
1305 if (pci_dev_present(early_486_chipsets)) {
1306 csr0 = MRL | MRM | (8 << BurstLenShift) | (1 << CALShift);
1307 force_csr0 = 1;
1308 }
1309
1310 /* bugfix: the ASIX must have a burst limit or horrible things happen. */
1311 if (chip_idx == AX88140) {
1312 if ((csr0 & 0x3f00) == 0)
1313 csr0 |= 0x2000;
1314 }
1315
1316 /* PNIC doesn't have MWI/MRL/MRM... */
1317 if (chip_idx == LC82C168)
1318 csr0 &= ~0xfff10000; /* zero reserved bits 31:20, 16 */
1319
1320 /* DM9102A has troubles with MRM & clear reserved bits 24:22, 20, 16, 7:1 */
1321 if (tulip_uli_dm_quirk(pdev)) {
1322 csr0 &= ~0x01f100ff;
1323 #if defined(CONFIG_SPARC)
1324 csr0 = (csr0 & ~0xff00) | 0xe000;
1325 #endif
1326 }
1327 /*
1328 * And back to business
1329 */
1330
1331 i = pci_enable_device(pdev);
1332 if (i) {
1333 printk (KERN_ERR PFX
1334 "Cannot enable tulip board #%d, aborting\n",
1335 board_idx);
1336 return i;
1337 }
1338
1339 irq = pdev->irq;
1340
1341 /* alloc_etherdev ensures aligned and zeroed private structures */
1342 dev = alloc_etherdev (sizeof (*tp));
1343 if (!dev) {
1344 printk (KERN_ERR PFX "ether device alloc failed, aborting\n");
1345 return -ENOMEM;
1346 }
1347
1348 SET_MODULE_OWNER(dev);
1349 SET_NETDEV_DEV(dev, &pdev->dev);
1350 if (pci_resource_len (pdev, 0) < tulip_tbl[chip_idx].io_size) {
1351 printk (KERN_ERR PFX "%s: I/O region (0x%llx@0x%llx) too small, "
1352 "aborting\n", pci_name(pdev),
1353 (unsigned long long)pci_resource_len (pdev, 0),
1354 (unsigned long long)pci_resource_start (pdev, 0));
1355 goto err_out_free_netdev;
1356 }
1357
1358 /* grab all resources from both PIO and MMIO regions, as we
1359 * don't want anyone else messing around with our hardware */
1360 if (pci_request_regions (pdev, "tulip"))
1361 goto err_out_free_netdev;
1362
1363 ioaddr = pci_iomap(pdev, TULIP_BAR, tulip_tbl[chip_idx].io_size);
1364
1365 if (!ioaddr)
1366 goto err_out_free_res;
1367
1368 /*
1369 * initialize private data structure 'tp'
1370 * it is zeroed and aligned in alloc_etherdev
1371 */
1372 tp = netdev_priv(dev);
1373 tp->dev = dev;
1374
1375 tp->rx_ring = pci_alloc_consistent(pdev,
1376 sizeof(struct tulip_rx_desc) * RX_RING_SIZE +
1377 sizeof(struct tulip_tx_desc) * TX_RING_SIZE,
1378 &tp->rx_ring_dma);
1379 if (!tp->rx_ring)
1380 goto err_out_mtable;
1381 tp->tx_ring = (struct tulip_tx_desc *)(tp->rx_ring + RX_RING_SIZE);
1382 tp->tx_ring_dma = tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * RX_RING_SIZE;
1383
1384 tp->chip_id = chip_idx;
1385 tp->flags = tulip_tbl[chip_idx].flags;
1386 tp->pdev = pdev;
1387 tp->base_addr = ioaddr;
1388 tp->revision = pdev->revision;
1389 tp->csr0 = csr0;
1390 spin_lock_init(&tp->lock);
1391 spin_lock_init(&tp->mii_lock);
1392 init_timer(&tp->timer);
1393 tp->timer.data = (unsigned long)dev;
1394 tp->timer.function = tulip_tbl[tp->chip_id].media_timer;
1395
1396 INIT_WORK(&tp->media_work, tulip_tbl[tp->chip_id].media_task);
1397
1398 dev->base_addr = (unsigned long)ioaddr;
1399
1400 #ifdef CONFIG_TULIP_MWI
1401 if (!force_csr0 && (tp->flags & HAS_PCI_MWI))
1402 tulip_mwi_config (pdev, dev);
1403 #else
1404 /* MWI is broken for DC21143 rev 65... */
1405 if (chip_idx == DC21143 && pdev->revision == 65)
1406 tp->csr0 &= ~MWI;
1407 #endif
1408
1409 /* Stop the chip's Tx and Rx processes. */
1410 tulip_stop_rxtx(tp);
1411
1412 pci_set_master(pdev);
1413
1414 #ifdef CONFIG_GSC
1415 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP) {
1416 switch (pdev->subsystem_device) {
1417 default:
1418 break;
1419 case 0x1061:
1420 case 0x1062:
1421 case 0x1063:
1422 case 0x1098:
1423 case 0x1099:
1424 case 0x10EE:
1425 tp->flags |= HAS_SWAPPED_SEEPROM | NEEDS_FAKE_MEDIA_TABLE;
1426 chip_name = "GSC DS21140 Tulip";
1427 }
1428 }
1429 #endif
1430
1431 /* Clear the missed-packet counter. */
1432 ioread32(ioaddr + CSR8);
1433
1434 /* The station address ROM is read byte serially. The register must
1435 be polled, waiting for the value to be read bit serially from the
1436 EEPROM.
1437 */
1438 ee_data = tp->eeprom;
1439 sum = 0;
1440 if (chip_idx == LC82C168) {
1441 for (i = 0; i < 3; i++) {
1442 int value, boguscnt = 100000;
1443 iowrite32(0x600 | i, ioaddr + 0x98);
1444 do
1445 value = ioread32(ioaddr + CSR9);
1446 while (value < 0 && --boguscnt > 0);
1447 put_unaligned(le16_to_cpu(value), ((u16*)dev->dev_addr) + i);
1448 sum += value & 0xffff;
1449 }
1450 } else if (chip_idx == COMET) {
1451 /* No need to read the EEPROM. */
1452 put_unaligned(cpu_to_le32(ioread32(ioaddr + 0xA4)), (u32 *)dev->dev_addr);
1453 put_unaligned(cpu_to_le16(ioread32(ioaddr + 0xA8)), (u16 *)(dev->dev_addr + 4));
1454 for (i = 0; i < 6; i ++)
1455 sum += dev->dev_addr[i];
1456 } else {
1457 /* A serial EEPROM interface, we read now and sort it out later. */
1458 int sa_offset = 0;
1459 int ee_addr_size = tulip_read_eeprom(dev, 0xff, 8) & 0x40000 ? 8 : 6;
1460
1461 for (i = 0; i < sizeof(tp->eeprom); i+=2) {
1462 u16 data = tulip_read_eeprom(dev, i/2, ee_addr_size);
1463 ee_data[i] = data & 0xff;
1464 ee_data[i + 1] = data >> 8;
1465 }
1466
1467 /* DEC now has a specification (see Notes) but early board makers
1468 just put the address in the first EEPROM locations. */
1469 /* This does memcmp(ee_data, ee_data+16, 8) */
1470 for (i = 0; i < 8; i ++)
1471 if (ee_data[i] != ee_data[16+i])
1472 sa_offset = 20;
1473 if (chip_idx == CONEXANT) {
1474 /* Check that the tuple type and length is correct. */
1475 if (ee_data[0x198] == 0x04 && ee_data[0x199] == 6)
1476 sa_offset = 0x19A;
1477 } else if (ee_data[0] == 0xff && ee_data[1] == 0xff &&
1478 ee_data[2] == 0) {
1479 sa_offset = 2; /* Grrr, damn Matrox boards. */
1480 multiport_cnt = 4;
1481 }
1482 #ifdef CONFIG_MIPS_COBALT
1483 if ((pdev->bus->number == 0) &&
1484 ((PCI_SLOT(pdev->devfn) == 7) ||
1485 (PCI_SLOT(pdev->devfn) == 12))) {
1486 /* Cobalt MAC address in first EEPROM locations. */
1487 sa_offset = 0;
1488 /* Ensure our media table fixup get's applied */
1489 memcpy(ee_data + 16, ee_data, 8);
1490 }
1491 #endif
1492 #ifdef CONFIG_GSC
1493 /* Check to see if we have a broken srom */
1494 if (ee_data[0] == 0x61 && ee_data[1] == 0x10) {
1495 /* pci_vendor_id and subsystem_id are swapped */
1496 ee_data[0] = ee_data[2];
1497 ee_data[1] = ee_data[3];
1498 ee_data[2] = 0x61;
1499 ee_data[3] = 0x10;
1500
1501 /* HSC-PCI boards need to be byte-swaped and shifted
1502 * up 1 word. This shift needs to happen at the end
1503 * of the MAC first because of the 2 byte overlap.
1504 */
1505 for (i = 4; i >= 0; i -= 2) {
1506 ee_data[17 + i + 3] = ee_data[17 + i];
1507 ee_data[16 + i + 5] = ee_data[16 + i];
1508 }
1509 }
1510 #endif
1511
1512 for (i = 0; i < 6; i ++) {
1513 dev->dev_addr[i] = ee_data[i + sa_offset];
1514 sum += ee_data[i + sa_offset];
1515 }
1516 }
1517 /* Lite-On boards have the address byte-swapped. */
1518 if ((dev->dev_addr[0] == 0xA0 || dev->dev_addr[0] == 0xC0 || dev->dev_addr[0] == 0x02)
1519 && dev->dev_addr[1] == 0x00)
1520 for (i = 0; i < 6; i+=2) {
1521 char tmp = dev->dev_addr[i];
1522 dev->dev_addr[i] = dev->dev_addr[i+1];
1523 dev->dev_addr[i+1] = tmp;
1524 }
1525 /* On the Zynx 315 Etherarray and other multiport boards only the
1526 first Tulip has an EEPROM.
1527 On Sparc systems the mac address is held in the OBP property
1528 "local-mac-address".
1529 The addresses of the subsequent ports are derived from the first.
1530 Many PCI BIOSes also incorrectly report the IRQ line, so we correct
1531 that here as well. */
1532 if (sum == 0 || sum == 6*0xff) {
1533 #if defined(CONFIG_SPARC)
1534 struct device_node *dp = pci_device_to_OF_node(pdev);
1535 const unsigned char *addr;
1536 int len;
1537 #endif
1538 eeprom_missing = 1;
1539 for (i = 0; i < 5; i++)
1540 dev->dev_addr[i] = last_phys_addr[i];
1541 dev->dev_addr[i] = last_phys_addr[i] + 1;
1542 #if defined(CONFIG_SPARC)
1543 addr = of_get_property(dp, "local-mac-address", &len);
1544 if (addr && len == 6)
1545 memcpy(dev->dev_addr, addr, 6);
1546 #endif
1547 #if defined(__i386__) || defined(__x86_64__) /* Patch up x86 BIOS bug. */
1548 if (last_irq)
1549 irq = last_irq;
1550 #endif
1551 }
1552
1553 for (i = 0; i < 6; i++)
1554 last_phys_addr[i] = dev->dev_addr[i];
1555 last_irq = irq;
1556 dev->irq = irq;
1557
1558 /* The lower four bits are the media type. */
1559 if (board_idx >= 0 && board_idx < MAX_UNITS) {
1560 if (options[board_idx] & MEDIA_MASK)
1561 tp->default_port = options[board_idx] & MEDIA_MASK;
1562 if ((options[board_idx] & FullDuplex) || full_duplex[board_idx] > 0)
1563 tp->full_duplex = 1;
1564 if (mtu[board_idx] > 0)
1565 dev->mtu = mtu[board_idx];
1566 }
1567 if (dev->mem_start & MEDIA_MASK)
1568 tp->default_port = dev->mem_start & MEDIA_MASK;
1569 if (tp->default_port) {
1570 printk(KERN_INFO "tulip%d: Transceiver selection forced to %s.\n",
1571 board_idx, medianame[tp->default_port & MEDIA_MASK]);
1572 tp->medialock = 1;
1573 if (tulip_media_cap[tp->default_port] & MediaAlwaysFD)
1574 tp->full_duplex = 1;
1575 }
1576 if (tp->full_duplex)
1577 tp->full_duplex_lock = 1;
1578
1579 if (tulip_media_cap[tp->default_port] & MediaIsMII) {
1580 u16 media2advert[] = { 0x20, 0x40, 0x03e0, 0x60, 0x80, 0x100, 0x200 };
1581 tp->mii_advertise = media2advert[tp->default_port - 9];
1582 tp->mii_advertise |= (tp->flags & HAS_8023X); /* Matching bits! */
1583 }
1584
1585 if (tp->flags & HAS_MEDIA_TABLE) {
1586 sprintf(dev->name, "tulip%d", board_idx); /* hack */
1587 tulip_parse_eeprom(dev);
1588 strcpy(dev->name, "eth%d"); /* un-hack */
1589 }
1590
1591 if ((tp->flags & ALWAYS_CHECK_MII) ||
1592 (tp->mtable && tp->mtable->has_mii) ||
1593 ( ! tp->mtable && (tp->flags & HAS_MII))) {
1594 if (tp->mtable && tp->mtable->has_mii) {
1595 for (i = 0; i < tp->mtable->leafcount; i++)
1596 if (tp->mtable->mleaf[i].media == 11) {
1597 tp->cur_index = i;
1598 tp->saved_if_port = dev->if_port;
1599 tulip_select_media(dev, 2);
1600 dev->if_port = tp->saved_if_port;
1601 break;
1602 }
1603 }
1604
1605 /* Find the connected MII xcvrs.
1606 Doing this in open() would allow detecting external xcvrs
1607 later, but takes much time. */
1608 tulip_find_mii (dev, board_idx);
1609 }
1610
1611 /* The Tulip-specific entries in the device structure. */
1612 dev->open = tulip_open;
1613 dev->hard_start_xmit = tulip_start_xmit;
1614 dev->tx_timeout = tulip_tx_timeout;
1615 dev->watchdog_timeo = TX_TIMEOUT;
1616 #ifdef CONFIG_TULIP_NAPI
1617 netif_napi_add(dev, &tp->napi, tulip_poll, 16);
1618 #endif
1619 dev->stop = tulip_close;
1620 dev->get_stats = tulip_get_stats;
1621 dev->do_ioctl = private_ioctl;
1622 dev->set_multicast_list = set_rx_mode;
1623 #ifdef CONFIG_NET_POLL_CONTROLLER
1624 dev->poll_controller = &poll_tulip;
1625 #endif
1626 SET_ETHTOOL_OPS(dev, &ops);
1627
1628 if (register_netdev(dev))
1629 goto err_out_free_ring;
1630
1631 printk(KERN_INFO "%s: %s rev %d at "
1632 #ifdef CONFIG_TULIP_MMIO
1633 "MMIO"
1634 #else
1635 "Port"
1636 #endif
1637 " %#llx,", dev->name, chip_name, pdev->revision,
1638 (unsigned long long) pci_resource_start(pdev, TULIP_BAR));
1639 pci_set_drvdata(pdev, dev);
1640
1641 if (eeprom_missing)
1642 printk(" EEPROM not present,");
1643 for (i = 0; i < 6; i++)
1644 printk("%c%2.2X", i ? ':' : ' ', dev->dev_addr[i]);
1645 printk(", IRQ %d.\n", irq);
1646
1647 if (tp->chip_id == PNIC2)
1648 tp->link_change = pnic2_lnk_change;
1649 else if (tp->flags & HAS_NWAY)
1650 tp->link_change = t21142_lnk_change;
1651 else if (tp->flags & HAS_PNICNWAY)
1652 tp->link_change = pnic_lnk_change;
1653
1654 /* Reset the xcvr interface and turn on heartbeat. */
1655 switch (chip_idx) {
1656 case DC21140:
1657 case DM910X:
1658 default:
1659 if (tp->mtable)
1660 iowrite32(tp->mtable->csr12dir | 0x100, ioaddr + CSR12);
1661 break;
1662 case DC21142:
1663 if (tp->mii_cnt || tulip_media_cap[dev->if_port] & MediaIsMII) {
1664 iowrite32(csr6_mask_defstate, ioaddr + CSR6);
1665 iowrite32(0x0000, ioaddr + CSR13);
1666 iowrite32(0x0000, ioaddr + CSR14);
1667 iowrite32(csr6_mask_hdcap, ioaddr + CSR6);
1668 } else
1669 t21142_start_nway(dev);
1670 break;
1671 case PNIC2:
1672 /* just do a reset for sanity sake */
1673 iowrite32(0x0000, ioaddr + CSR13);
1674 iowrite32(0x0000, ioaddr + CSR14);
1675 break;
1676 case LC82C168:
1677 if ( ! tp->mii_cnt) {
1678 tp->nway = 1;
1679 tp->nwayset = 0;
1680 iowrite32(csr6_ttm | csr6_ca, ioaddr + CSR6);
1681 iowrite32(0x30, ioaddr + CSR12);
1682 iowrite32(0x0001F078, ioaddr + CSR6);
1683 iowrite32(0x0201F078, ioaddr + CSR6); /* Turn on autonegotiation. */
1684 }
1685 break;
1686 case MX98713:
1687 case COMPEX9881:
1688 iowrite32(0x00000000, ioaddr + CSR6);
1689 iowrite32(0x000711C0, ioaddr + CSR14); /* Turn on NWay. */
1690 iowrite32(0x00000001, ioaddr + CSR13);
1691 break;
1692 case MX98715:
1693 case MX98725:
1694 iowrite32(0x01a80000, ioaddr + CSR6);
1695 iowrite32(0xFFFFFFFF, ioaddr + CSR14);
1696 iowrite32(0x00001000, ioaddr + CSR12);
1697 break;
1698 case COMET:
1699 /* No initialization necessary. */
1700 break;
1701 }
1702
1703 /* put the chip in snooze mode until opened */
1704 tulip_set_power_state (tp, 0, 1);
1705
1706 return 0;
1707
1708 err_out_free_ring:
1709 pci_free_consistent (pdev,
1710 sizeof (struct tulip_rx_desc) * RX_RING_SIZE +
1711 sizeof (struct tulip_tx_desc) * TX_RING_SIZE,
1712 tp->rx_ring, tp->rx_ring_dma);
1713
1714 err_out_mtable:
1715 kfree (tp->mtable);
1716 pci_iounmap(pdev, ioaddr);
1717
1718 err_out_free_res:
1719 pci_release_regions (pdev);
1720
1721 err_out_free_netdev:
1722 free_netdev (dev);
1723 return -ENODEV;
1724 }
1725
1726
1727 #ifdef CONFIG_PM
1728
1729 static int tulip_suspend (struct pci_dev *pdev, pm_message_t state)
1730 {
1731 struct net_device *dev = pci_get_drvdata(pdev);
1732
1733 if (!dev)
1734 return -EINVAL;
1735
1736 if (netif_running(dev))
1737 tulip_down(dev);
1738
1739 netif_device_detach(dev);
1740 free_irq(dev->irq, dev);
1741
1742 pci_save_state(pdev);
1743 pci_disable_device(pdev);
1744 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1745
1746 return 0;
1747 }
1748
1749
1750 static int tulip_resume(struct pci_dev *pdev)
1751 {
1752 struct net_device *dev = pci_get_drvdata(pdev);
1753 int retval;
1754
1755 if (!dev)
1756 return -EINVAL;
1757
1758 pci_set_power_state(pdev, PCI_D0);
1759 pci_restore_state(pdev);
1760
1761 if ((retval = pci_enable_device(pdev))) {
1762 printk (KERN_ERR "tulip: pci_enable_device failed in resume\n");
1763 return retval;
1764 }
1765
1766 if ((retval = request_irq(dev->irq, &tulip_interrupt, IRQF_SHARED, dev->name, dev))) {
1767 printk (KERN_ERR "tulip: request_irq failed in resume\n");
1768 return retval;
1769 }
1770
1771 netif_device_attach(dev);
1772
1773 if (netif_running(dev))
1774 tulip_up(dev);
1775
1776 return 0;
1777 }
1778
1779 #endif /* CONFIG_PM */
1780
1781
1782 static void __devexit tulip_remove_one (struct pci_dev *pdev)
1783 {
1784 struct net_device *dev = pci_get_drvdata (pdev);
1785 struct tulip_private *tp;
1786
1787 if (!dev)
1788 return;
1789
1790 tp = netdev_priv(dev);
1791 unregister_netdev(dev);
1792 pci_free_consistent (pdev,
1793 sizeof (struct tulip_rx_desc) * RX_RING_SIZE +
1794 sizeof (struct tulip_tx_desc) * TX_RING_SIZE,
1795 tp->rx_ring, tp->rx_ring_dma);
1796 kfree (tp->mtable);
1797 pci_iounmap(pdev, tp->base_addr);
1798 free_netdev (dev);
1799 pci_release_regions (pdev);
1800 pci_set_drvdata (pdev, NULL);
1801
1802 /* pci_power_off (pdev, -1); */
1803 }
1804
1805 #ifdef CONFIG_NET_POLL_CONTROLLER
1806 /*
1807 * Polling 'interrupt' - used by things like netconsole to send skbs
1808 * without having to re-enable interrupts. It's not called while
1809 * the interrupt routine is executing.
1810 */
1811
1812 static void poll_tulip (struct net_device *dev)
1813 {
1814 /* disable_irq here is not very nice, but with the lockless
1815 interrupt handler we have no other choice. */
1816 disable_irq(dev->irq);
1817 tulip_interrupt (dev->irq, dev);
1818 enable_irq(dev->irq);
1819 }
1820 #endif
1821
1822 static struct pci_driver tulip_driver = {
1823 .name = DRV_NAME,
1824 .id_table = tulip_pci_tbl,
1825 .probe = tulip_init_one,
1826 .remove = __devexit_p(tulip_remove_one),
1827 #ifdef CONFIG_PM
1828 .suspend = tulip_suspend,
1829 .resume = tulip_resume,
1830 #endif /* CONFIG_PM */
1831 };
1832
1833
1834 static int __init tulip_init (void)
1835 {
1836 #ifdef MODULE
1837 printk (KERN_INFO "%s", version);
1838 #endif
1839
1840 /* copy module parms into globals */
1841 tulip_rx_copybreak = rx_copybreak;
1842 tulip_max_interrupt_work = max_interrupt_work;
1843
1844 /* probe for and init boards */
1845 return pci_register_driver(&tulip_driver);
1846 }
1847
1848
1849 static void __exit tulip_cleanup (void)
1850 {
1851 pci_unregister_driver (&tulip_driver);
1852 }
1853
1854
1855 module_init(tulip_init);
1856 module_exit(tulip_cleanup);
Linux kernel - Deliverables
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