2 * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
4 * Author: Shlomi Gridish <gridish@freescale.com>
5 * Li Yang <leoli@freescale.com>
8 * QE UCC Gigabit Ethernet Driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/slab.h>
19 #include <linux/stddef.h>
20 #include <linux/interrupt.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/skbuff.h>
24 #include <linux/spinlock.h>
26 #include <linux/ethtool.h>
27 #include <linux/delay.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/fsl_devices.h>
30 #include <linux/ethtool.h>
31 #include <linux/mii.h>
33 #include <asm/of_platform.h>
34 #include <asm/uaccess.h>
37 #include <asm/immap_qe.h>
40 #include <asm/ucc_fast.h>
43 #include "ucc_geth_phy.h"
47 #define DRV_DESC "QE UCC Gigabit Ethernet Controller version:Sept 11, 2006"
48 #define DRV_NAME "ucc_geth"
50 #define ugeth_printk(level, format, arg...) \
51 printk(level format "\n", ## arg)
53 #define ugeth_dbg(format, arg...) \
54 ugeth_printk(KERN_DEBUG , format , ## arg)
55 #define ugeth_err(format, arg...) \
56 ugeth_printk(KERN_ERR , format , ## arg)
57 #define ugeth_info(format, arg...) \
58 ugeth_printk(KERN_INFO , format , ## arg)
59 #define ugeth_warn(format, arg...) \
60 ugeth_printk(KERN_WARNING , format , ## arg)
62 #ifdef UGETH_VERBOSE_DEBUG
63 #define ugeth_vdbg ugeth_dbg
65 #define ugeth_vdbg(fmt, args...) do { } while (0)
66 #endif /* UGETH_VERBOSE_DEBUG */
68 static DEFINE_SPINLOCK(ugeth_lock
);
70 static struct ucc_geth_info ugeth_primary_info
= {
72 .bd_mem_part
= MEM_PART_SYSTEM
,
73 .rtsm
= UCC_FAST_SEND_IDLES_BETWEEN_FRAMES
,
74 .max_rx_buf_length
= 1536,
75 /* FIXME: should be changed in run time for 1G and 100M */
76 #ifdef CONFIG_UGETH_HAS_GIGA
77 .urfs
= UCC_GETH_URFS_GIGA_INIT
,
78 .urfet
= UCC_GETH_URFET_GIGA_INIT
,
79 .urfset
= UCC_GETH_URFSET_GIGA_INIT
,
80 .utfs
= UCC_GETH_UTFS_GIGA_INIT
,
81 .utfet
= UCC_GETH_UTFET_GIGA_INIT
,
82 .utftt
= UCC_GETH_UTFTT_GIGA_INIT
,
84 .urfs
= UCC_GETH_URFS_INIT
,
85 .urfet
= UCC_GETH_URFET_INIT
,
86 .urfset
= UCC_GETH_URFSET_INIT
,
87 .utfs
= UCC_GETH_UTFS_INIT
,
88 .utfet
= UCC_GETH_UTFET_INIT
,
89 .utftt
= UCC_GETH_UTFTT_INIT
,
92 .mode
= UCC_FAST_PROTOCOL_MODE_ETHERNET
,
93 .ttx_trx
= UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL
,
94 .tenc
= UCC_FAST_TX_ENCODING_NRZ
,
95 .renc
= UCC_FAST_RX_ENCODING_NRZ
,
96 .tcrc
= UCC_FAST_16_BIT_CRC
,
97 .synl
= UCC_FAST_SYNC_LEN_NOT_USED
,
101 .extendedFilteringChainPointer
= ((uint32_t) NULL
),
102 .typeorlen
= 3072 /*1536 */ ,
103 .nonBackToBackIfgPart1
= 0x40,
104 .nonBackToBackIfgPart2
= 0x60,
105 .miminumInterFrameGapEnforcement
= 0x50,
106 .backToBackInterFrameGap
= 0x60,
110 .strictpriorityq
= 0xff,
111 .altBebTruncation
= 0xa,
113 .maxRetransmission
= 0xf,
114 .collisionWindow
= 0x37,
115 .receiveFlowControl
= 1,
116 .maxGroupAddrInHash
= 4,
117 .maxIndAddrInHash
= 4,
119 .maxFrameLength
= 1518,
120 .minFrameLength
= 64,
124 .ecamptr
= ((uint32_t) NULL
),
125 .eventRegMask
= UCCE_OTHER
,
126 .pausePeriod
= 0xf000,
127 .interruptcoalescingmaxvalue
= {1, 1, 1, 1, 1, 1, 1, 1},
148 .numStationAddresses
= UCC_GETH_NUM_OF_STATION_ADDRESSES_1
,
149 .largestexternallookupkeysize
=
150 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
,
151 .statisticsMode
= UCC_GETH_STATISTICS_GATHERING_MODE_NONE
,
152 .vlanOperationTagged
= UCC_GETH_VLAN_OPERATION_TAGGED_NOP
,
153 .vlanOperationNonTagged
= UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP
,
154 .rxQoSMode
= UCC_GETH_QOS_MODE_DEFAULT
,
155 .aufc
= UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE
,
156 .padAndCrc
= MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC
,
157 .numThreadsTx
= UCC_GETH_NUM_OF_THREADS_4
,
158 .numThreadsRx
= UCC_GETH_NUM_OF_THREADS_4
,
159 .riscTx
= QE_RISC_ALLOCATION_RISC1_AND_RISC2
,
160 .riscRx
= QE_RISC_ALLOCATION_RISC1_AND_RISC2
,
163 static struct ucc_geth_info ugeth_info
[8];
166 static void mem_disp(u8
*addr
, int size
)
169 int size16Aling
= (size
>> 4) << 4;
170 int size4Aling
= (size
>> 2) << 2;
175 for (i
= addr
; (u32
) i
< (u32
) addr
+ size16Aling
; i
+= 16)
176 printk("0x%08x: %08x %08x %08x %08x\r\n",
180 *((u32
*) (i
+ 8)), *((u32
*) (i
+ 12)));
182 printk("0x%08x: ", (u32
) i
);
183 for (; (u32
) i
< (u32
) addr
+ size4Aling
; i
+= 4)
184 printk("%08x ", *((u32
*) (i
)));
185 for (; (u32
) i
< (u32
) addr
+ size
; i
++)
186 printk("%02x", *((u8
*) (i
)));
192 #ifdef CONFIG_UGETH_FILTERING
193 static void enqueue(struct list_head
*node
, struct list_head
*lh
)
197 spin_lock_irqsave(ugeth_lock
, flags
);
198 list_add_tail(node
, lh
);
199 spin_unlock_irqrestore(ugeth_lock
, flags
);
201 #endif /* CONFIG_UGETH_FILTERING */
203 static struct list_head
*dequeue(struct list_head
*lh
)
207 spin_lock_irqsave(ugeth_lock
, flags
);
208 if (!list_empty(lh
)) {
209 struct list_head
*node
= lh
->next
;
211 spin_unlock_irqrestore(ugeth_lock
, flags
);
214 spin_unlock_irqrestore(ugeth_lock
, flags
);
219 static int get_interface_details(enum enet_interface enet_interface
,
220 enum enet_speed
*speed
,
224 int *tbi
, int *limited_to_full_duplex
)
226 /* Analyze enet_interface according to Interface Mode
227 Configuration table */
228 switch (enet_interface
) {
230 *speed
= ENET_SPEED_10BT
;
233 *speed
= ENET_SPEED_10BT
;
238 *speed
= ENET_SPEED_10BT
;
241 *limited_to_full_duplex
= 1;
244 *speed
= ENET_SPEED_100BT
;
247 *speed
= ENET_SPEED_100BT
;
251 *speed
= ENET_SPEED_100BT
;
253 *limited_to_full_duplex
= 1;
256 *speed
= ENET_SPEED_1000BT
;
257 *limited_to_full_duplex
= 1;
259 case ENET_1000_RGMII
:
260 *speed
= ENET_SPEED_1000BT
;
262 *limited_to_full_duplex
= 1;
265 *speed
= ENET_SPEED_1000BT
;
267 *limited_to_full_duplex
= 1;
270 *speed
= ENET_SPEED_1000BT
;
273 *limited_to_full_duplex
= 1;
283 static struct sk_buff
*get_new_skb(struct ucc_geth_private
*ugeth
, u8
*bd
)
285 struct sk_buff
*skb
= NULL
;
287 skb
= dev_alloc_skb(ugeth
->ug_info
->uf_info
.max_rx_buf_length
+
288 UCC_GETH_RX_DATA_BUF_ALIGNMENT
);
293 /* We need the data buffer to be aligned properly. We will reserve
294 * as many bytes as needed to align the data properly
297 UCC_GETH_RX_DATA_BUF_ALIGNMENT
-
298 (((unsigned)skb
->data
) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT
-
301 skb
->dev
= ugeth
->dev
;
303 out_be32(&((struct qe_bd
*)bd
)->buf
,
306 ugeth
->ug_info
->uf_info
.max_rx_buf_length
+
307 UCC_GETH_RX_DATA_BUF_ALIGNMENT
,
310 out_be32((u32
*)bd
, (R_E
| R_I
| (in_be32((u32
*)bd
) & R_W
)));
315 static int rx_bd_buffer_set(struct ucc_geth_private
*ugeth
, u8 rxQ
)
322 bd
= ugeth
->p_rx_bd_ring
[rxQ
];
326 bd_status
= in_be32((u32
*)bd
);
327 skb
= get_new_skb(ugeth
, bd
);
329 if (!skb
) /* If can not allocate data buffer,
330 abort. Cleanup will be elsewhere */
333 ugeth
->rx_skbuff
[rxQ
][i
] = skb
;
335 /* advance the BD pointer */
336 bd
+= sizeof(struct qe_bd
);
338 } while (!(bd_status
& R_W
));
343 static int fill_init_enet_entries(struct ucc_geth_private
*ugeth
,
344 volatile u32
*p_start
,
347 u32 thread_alignment
,
348 enum qe_risc_allocation risc
,
349 int skip_page_for_first_entry
)
351 u32 init_enet_offset
;
355 for (i
= 0; i
< num_entries
; i
++) {
356 if ((snum
= qe_get_snum()) < 0) {
357 ugeth_err("fill_init_enet_entries: Can not get SNUM.");
360 if ((i
== 0) && skip_page_for_first_entry
)
361 /* First entry of Rx does not have page */
362 init_enet_offset
= 0;
365 qe_muram_alloc(thread_size
, thread_alignment
);
366 if (IS_MURAM_ERR(init_enet_offset
)) {
368 ("fill_init_enet_entries: Can not allocate DPRAM memory.");
369 qe_put_snum((u8
) snum
);
374 ((u8
) snum
<< ENET_INIT_PARAM_SNUM_SHIFT
) | init_enet_offset
381 static int return_init_enet_entries(struct ucc_geth_private
*ugeth
,
382 volatile u32
*p_start
,
384 enum qe_risc_allocation risc
,
385 int skip_page_for_first_entry
)
387 u32 init_enet_offset
;
391 for (i
= 0; i
< num_entries
; i
++) {
392 /* Check that this entry was actually valid --
393 needed in case failed in allocations */
394 if ((*p_start
& ENET_INIT_PARAM_RISC_MASK
) == risc
) {
396 (u32
) (*p_start
& ENET_INIT_PARAM_SNUM_MASK
) >>
397 ENET_INIT_PARAM_SNUM_SHIFT
;
398 qe_put_snum((u8
) snum
);
399 if (!((i
== 0) && skip_page_for_first_entry
)) {
400 /* First entry of Rx does not have page */
403 ENET_INIT_PARAM_PTR_MASK
);
404 qe_muram_free(init_enet_offset
);
406 *(p_start
++) = 0; /* Just for cosmetics */
414 static int dump_init_enet_entries(struct ucc_geth_private
*ugeth
,
415 volatile u32
*p_start
,
418 enum qe_risc_allocation risc
,
419 int skip_page_for_first_entry
)
421 u32 init_enet_offset
;
425 for (i
= 0; i
< num_entries
; i
++) {
426 /* Check that this entry was actually valid --
427 needed in case failed in allocations */
428 if ((*p_start
& ENET_INIT_PARAM_RISC_MASK
) == risc
) {
430 (u32
) (*p_start
& ENET_INIT_PARAM_SNUM_MASK
) >>
431 ENET_INIT_PARAM_SNUM_SHIFT
;
432 qe_put_snum((u8
) snum
);
433 if (!((i
== 0) && skip_page_for_first_entry
)) {
434 /* First entry of Rx does not have page */
437 ENET_INIT_PARAM_PTR_MASK
);
438 ugeth_info("Init enet entry %d:", i
);
439 ugeth_info("Base address: 0x%08x",
441 qe_muram_addr(init_enet_offset
));
442 mem_disp(qe_muram_addr(init_enet_offset
),
453 #ifdef CONFIG_UGETH_FILTERING
454 static struct enet_addr_container
*get_enet_addr_container(void)
456 struct enet_addr_container
*enet_addr_cont
;
458 /* allocate memory */
459 enet_addr_cont
= kmalloc(sizeof(struct enet_addr_container
), GFP_KERNEL
);
460 if (!enet_addr_cont
) {
461 ugeth_err("%s: No memory for enet_addr_container object.",
466 return enet_addr_cont
;
468 #endif /* CONFIG_UGETH_FILTERING */
470 static void put_enet_addr_container(struct enet_addr_container
*enet_addr_cont
)
472 kfree(enet_addr_cont
);
475 static int set_mac_addr(__be16 __iomem
*reg
, u8
*mac
)
477 out_be16(®
[0], ((u16
)mac
[5] << 8) | mac
[4]);
478 out_be16(®
[1], ((u16
)mac
[3] << 8) | mac
[2]);
479 out_be16(®
[2], ((u16
)mac
[1] << 8) | mac
[0]);
482 #ifdef CONFIG_UGETH_FILTERING
483 static int hw_add_addr_in_paddr(struct ucc_geth_private
*ugeth
,
484 u8
*p_enet_addr
, u8 paddr_num
)
486 struct ucc_geth_82xx_address_filtering_pram
*p_82xx_addr_filt
;
488 if (!(paddr_num
< NUM_OF_PADDRS
)) {
489 ugeth_warn("%s: Illegal paddr_num.", __FUNCTION__
);
494 (struct ucc_geth_82xx_address_filtering_pram
*) ugeth
->p_rx_glbl_pram
->
497 /* Ethernet frames are defined in Little Endian mode, */
498 /* therefore to insert the address we reverse the bytes. */
499 set_mac_addr(&p_82xx_addr_filt
->paddr
[paddr_num
].h
, p_enet_addr
);
502 #endif /* CONFIG_UGETH_FILTERING */
504 static int hw_clear_addr_in_paddr(struct ucc_geth_private
*ugeth
, u8 paddr_num
)
506 struct ucc_geth_82xx_address_filtering_pram
*p_82xx_addr_filt
;
508 if (!(paddr_num
< NUM_OF_PADDRS
)) {
509 ugeth_warn("%s: Illagel paddr_num.", __FUNCTION__
);
514 (struct ucc_geth_82xx_address_filtering_pram
*) ugeth
->p_rx_glbl_pram
->
517 /* Writing address ff.ff.ff.ff.ff.ff disables address
518 recognition for this register */
519 out_be16(&p_82xx_addr_filt
->paddr
[paddr_num
].h
, 0xffff);
520 out_be16(&p_82xx_addr_filt
->paddr
[paddr_num
].m
, 0xffff);
521 out_be16(&p_82xx_addr_filt
->paddr
[paddr_num
].l
, 0xffff);
526 static void hw_add_addr_in_hash(struct ucc_geth_private
*ugeth
,
529 struct ucc_geth_82xx_address_filtering_pram
*p_82xx_addr_filt
;
533 (struct ucc_geth_82xx_address_filtering_pram
*) ugeth
->p_rx_glbl_pram
->
537 ucc_fast_get_qe_cr_subblock(ugeth
->ug_info
->uf_info
.ucc_num
);
539 /* Ethernet frames are defined in Little Endian mode,
540 therefor to insert */
541 /* the address to the hash (Big Endian mode), we reverse the bytes.*/
543 set_mac_addr(&p_82xx_addr_filt
->taddr
.h
, p_enet_addr
);
545 qe_issue_cmd(QE_SET_GROUP_ADDRESS
, cecr_subblock
,
546 QE_CR_PROTOCOL_ETHERNET
, 0);
549 #ifdef CONFIG_UGETH_MAGIC_PACKET
550 static void magic_packet_detection_enable(struct ucc_geth_private
*ugeth
)
552 struct ucc_fast_private
*uccf
;
553 struct ucc_geth
*ug_regs
;
557 ug_regs
= ugeth
->ug_regs
;
559 /* Enable interrupts for magic packet detection */
560 uccm
= in_be32(uccf
->p_uccm
);
562 out_be32(uccf
->p_uccm
, uccm
);
564 /* Enable magic packet detection */
565 maccfg2
= in_be32(&ug_regs
->maccfg2
);
566 maccfg2
|= MACCFG2_MPE
;
567 out_be32(&ug_regs
->maccfg2
, maccfg2
);
570 static void magic_packet_detection_disable(struct ucc_geth_private
*ugeth
)
572 struct ucc_fast_private
*uccf
;
573 struct ucc_geth
*ug_regs
;
577 ug_regs
= ugeth
->ug_regs
;
579 /* Disable interrupts for magic packet detection */
580 uccm
= in_be32(uccf
->p_uccm
);
582 out_be32(uccf
->p_uccm
, uccm
);
584 /* Disable magic packet detection */
585 maccfg2
= in_be32(&ug_regs
->maccfg2
);
586 maccfg2
&= ~MACCFG2_MPE
;
587 out_be32(&ug_regs
->maccfg2
, maccfg2
);
589 #endif /* MAGIC_PACKET */
591 static inline int compare_addr(u8
**addr1
, u8
**addr2
)
593 return memcmp(addr1
, addr2
, ENET_NUM_OCTETS_PER_ADDRESS
);
597 static void get_statistics(struct ucc_geth_private
*ugeth
,
598 struct ucc_geth_tx_firmware_statistics
*
599 tx_firmware_statistics
,
600 struct ucc_geth_rx_firmware_statistics
*
601 rx_firmware_statistics
,
602 struct ucc_geth_hardware_statistics
*hardware_statistics
)
604 struct ucc_fast
*uf_regs
;
605 struct ucc_geth
*ug_regs
;
606 struct ucc_geth_tx_firmware_statistics_pram
*p_tx_fw_statistics_pram
;
607 struct ucc_geth_rx_firmware_statistics_pram
*p_rx_fw_statistics_pram
;
609 ug_regs
= ugeth
->ug_regs
;
610 uf_regs
= (struct ucc_fast
*) ug_regs
;
611 p_tx_fw_statistics_pram
= ugeth
->p_tx_fw_statistics_pram
;
612 p_rx_fw_statistics_pram
= ugeth
->p_rx_fw_statistics_pram
;
614 /* Tx firmware only if user handed pointer and driver actually
615 gathers Tx firmware statistics */
616 if (tx_firmware_statistics
&& p_tx_fw_statistics_pram
) {
617 tx_firmware_statistics
->sicoltx
=
618 in_be32(&p_tx_fw_statistics_pram
->sicoltx
);
619 tx_firmware_statistics
->mulcoltx
=
620 in_be32(&p_tx_fw_statistics_pram
->mulcoltx
);
621 tx_firmware_statistics
->latecoltxfr
=
622 in_be32(&p_tx_fw_statistics_pram
->latecoltxfr
);
623 tx_firmware_statistics
->frabortduecol
=
624 in_be32(&p_tx_fw_statistics_pram
->frabortduecol
);
625 tx_firmware_statistics
->frlostinmactxer
=
626 in_be32(&p_tx_fw_statistics_pram
->frlostinmactxer
);
627 tx_firmware_statistics
->carriersenseertx
=
628 in_be32(&p_tx_fw_statistics_pram
->carriersenseertx
);
629 tx_firmware_statistics
->frtxok
=
630 in_be32(&p_tx_fw_statistics_pram
->frtxok
);
631 tx_firmware_statistics
->txfrexcessivedefer
=
632 in_be32(&p_tx_fw_statistics_pram
->txfrexcessivedefer
);
633 tx_firmware_statistics
->txpkts256
=
634 in_be32(&p_tx_fw_statistics_pram
->txpkts256
);
635 tx_firmware_statistics
->txpkts512
=
636 in_be32(&p_tx_fw_statistics_pram
->txpkts512
);
637 tx_firmware_statistics
->txpkts1024
=
638 in_be32(&p_tx_fw_statistics_pram
->txpkts1024
);
639 tx_firmware_statistics
->txpktsjumbo
=
640 in_be32(&p_tx_fw_statistics_pram
->txpktsjumbo
);
643 /* Rx firmware only if user handed pointer and driver actually
644 * gathers Rx firmware statistics */
645 if (rx_firmware_statistics
&& p_rx_fw_statistics_pram
) {
647 rx_firmware_statistics
->frrxfcser
=
648 in_be32(&p_rx_fw_statistics_pram
->frrxfcser
);
649 rx_firmware_statistics
->fraligner
=
650 in_be32(&p_rx_fw_statistics_pram
->fraligner
);
651 rx_firmware_statistics
->inrangelenrxer
=
652 in_be32(&p_rx_fw_statistics_pram
->inrangelenrxer
);
653 rx_firmware_statistics
->outrangelenrxer
=
654 in_be32(&p_rx_fw_statistics_pram
->outrangelenrxer
);
655 rx_firmware_statistics
->frtoolong
=
656 in_be32(&p_rx_fw_statistics_pram
->frtoolong
);
657 rx_firmware_statistics
->runt
=
658 in_be32(&p_rx_fw_statistics_pram
->runt
);
659 rx_firmware_statistics
->verylongevent
=
660 in_be32(&p_rx_fw_statistics_pram
->verylongevent
);
661 rx_firmware_statistics
->symbolerror
=
662 in_be32(&p_rx_fw_statistics_pram
->symbolerror
);
663 rx_firmware_statistics
->dropbsy
=
664 in_be32(&p_rx_fw_statistics_pram
->dropbsy
);
665 for (i
= 0; i
< 0x8; i
++)
666 rx_firmware_statistics
->res0
[i
] =
667 p_rx_fw_statistics_pram
->res0
[i
];
668 rx_firmware_statistics
->mismatchdrop
=
669 in_be32(&p_rx_fw_statistics_pram
->mismatchdrop
);
670 rx_firmware_statistics
->underpkts
=
671 in_be32(&p_rx_fw_statistics_pram
->underpkts
);
672 rx_firmware_statistics
->pkts256
=
673 in_be32(&p_rx_fw_statistics_pram
->pkts256
);
674 rx_firmware_statistics
->pkts512
=
675 in_be32(&p_rx_fw_statistics_pram
->pkts512
);
676 rx_firmware_statistics
->pkts1024
=
677 in_be32(&p_rx_fw_statistics_pram
->pkts1024
);
678 rx_firmware_statistics
->pktsjumbo
=
679 in_be32(&p_rx_fw_statistics_pram
->pktsjumbo
);
680 rx_firmware_statistics
->frlossinmacer
=
681 in_be32(&p_rx_fw_statistics_pram
->frlossinmacer
);
682 rx_firmware_statistics
->pausefr
=
683 in_be32(&p_rx_fw_statistics_pram
->pausefr
);
684 for (i
= 0; i
< 0x4; i
++)
685 rx_firmware_statistics
->res1
[i
] =
686 p_rx_fw_statistics_pram
->res1
[i
];
687 rx_firmware_statistics
->removevlan
=
688 in_be32(&p_rx_fw_statistics_pram
->removevlan
);
689 rx_firmware_statistics
->replacevlan
=
690 in_be32(&p_rx_fw_statistics_pram
->replacevlan
);
691 rx_firmware_statistics
->insertvlan
=
692 in_be32(&p_rx_fw_statistics_pram
->insertvlan
);
695 /* Hardware only if user handed pointer and driver actually
696 gathers hardware statistics */
697 if (hardware_statistics
&& (in_be32(&uf_regs
->upsmr
) & UPSMR_HSE
)) {
698 hardware_statistics
->tx64
= in_be32(&ug_regs
->tx64
);
699 hardware_statistics
->tx127
= in_be32(&ug_regs
->tx127
);
700 hardware_statistics
->tx255
= in_be32(&ug_regs
->tx255
);
701 hardware_statistics
->rx64
= in_be32(&ug_regs
->rx64
);
702 hardware_statistics
->rx127
= in_be32(&ug_regs
->rx127
);
703 hardware_statistics
->rx255
= in_be32(&ug_regs
->rx255
);
704 hardware_statistics
->txok
= in_be32(&ug_regs
->txok
);
705 hardware_statistics
->txcf
= in_be16(&ug_regs
->txcf
);
706 hardware_statistics
->tmca
= in_be32(&ug_regs
->tmca
);
707 hardware_statistics
->tbca
= in_be32(&ug_regs
->tbca
);
708 hardware_statistics
->rxfok
= in_be32(&ug_regs
->rxfok
);
709 hardware_statistics
->rxbok
= in_be32(&ug_regs
->rxbok
);
710 hardware_statistics
->rbyt
= in_be32(&ug_regs
->rbyt
);
711 hardware_statistics
->rmca
= in_be32(&ug_regs
->rmca
);
712 hardware_statistics
->rbca
= in_be32(&ug_regs
->rbca
);
716 static void dump_bds(struct ucc_geth_private
*ugeth
)
721 for (i
= 0; i
< ugeth
->ug_info
->numQueuesTx
; i
++) {
722 if (ugeth
->p_tx_bd_ring
[i
]) {
724 (ugeth
->ug_info
->bdRingLenTx
[i
] *
725 sizeof(struct qe_bd
));
726 ugeth_info("TX BDs[%d]", i
);
727 mem_disp(ugeth
->p_tx_bd_ring
[i
], length
);
730 for (i
= 0; i
< ugeth
->ug_info
->numQueuesRx
; i
++) {
731 if (ugeth
->p_rx_bd_ring
[i
]) {
733 (ugeth
->ug_info
->bdRingLenRx
[i
] *
734 sizeof(struct qe_bd
));
735 ugeth_info("RX BDs[%d]", i
);
736 mem_disp(ugeth
->p_rx_bd_ring
[i
], length
);
741 static void dump_regs(struct ucc_geth_private
*ugeth
)
745 ugeth_info("UCC%d Geth registers:", ugeth
->ug_info
->uf_info
.ucc_num
);
746 ugeth_info("Base address: 0x%08x", (u32
) ugeth
->ug_regs
);
748 ugeth_info("maccfg1 : addr - 0x%08x, val - 0x%08x",
749 (u32
) & ugeth
->ug_regs
->maccfg1
,
750 in_be32(&ugeth
->ug_regs
->maccfg1
));
751 ugeth_info("maccfg2 : addr - 0x%08x, val - 0x%08x",
752 (u32
) & ugeth
->ug_regs
->maccfg2
,
753 in_be32(&ugeth
->ug_regs
->maccfg2
));
754 ugeth_info("ipgifg : addr - 0x%08x, val - 0x%08x",
755 (u32
) & ugeth
->ug_regs
->ipgifg
,
756 in_be32(&ugeth
->ug_regs
->ipgifg
));
757 ugeth_info("hafdup : addr - 0x%08x, val - 0x%08x",
758 (u32
) & ugeth
->ug_regs
->hafdup
,
759 in_be32(&ugeth
->ug_regs
->hafdup
));
760 ugeth_info("miimcfg : addr - 0x%08x, val - 0x%08x",
761 (u32
) & ugeth
->ug_regs
->miimng
.miimcfg
,
762 in_be32(&ugeth
->ug_regs
->miimng
.miimcfg
));
763 ugeth_info("miimcom : addr - 0x%08x, val - 0x%08x",
764 (u32
) & ugeth
->ug_regs
->miimng
.miimcom
,
765 in_be32(&ugeth
->ug_regs
->miimng
.miimcom
));
766 ugeth_info("miimadd : addr - 0x%08x, val - 0x%08x",
767 (u32
) & ugeth
->ug_regs
->miimng
.miimadd
,
768 in_be32(&ugeth
->ug_regs
->miimng
.miimadd
));
769 ugeth_info("miimcon : addr - 0x%08x, val - 0x%08x",
770 (u32
) & ugeth
->ug_regs
->miimng
.miimcon
,
771 in_be32(&ugeth
->ug_regs
->miimng
.miimcon
));
772 ugeth_info("miimstat : addr - 0x%08x, val - 0x%08x",
773 (u32
) & ugeth
->ug_regs
->miimng
.miimstat
,
774 in_be32(&ugeth
->ug_regs
->miimng
.miimstat
));
775 ugeth_info("miimmind : addr - 0x%08x, val - 0x%08x",
776 (u32
) & ugeth
->ug_regs
->miimng
.miimind
,
777 in_be32(&ugeth
->ug_regs
->miimng
.miimind
));
778 ugeth_info("ifctl : addr - 0x%08x, val - 0x%08x",
779 (u32
) & ugeth
->ug_regs
->ifctl
,
780 in_be32(&ugeth
->ug_regs
->ifctl
));
781 ugeth_info("ifstat : addr - 0x%08x, val - 0x%08x",
782 (u32
) & ugeth
->ug_regs
->ifstat
,
783 in_be32(&ugeth
->ug_regs
->ifstat
));
784 ugeth_info("macstnaddr1: addr - 0x%08x, val - 0x%08x",
785 (u32
) & ugeth
->ug_regs
->macstnaddr1
,
786 in_be32(&ugeth
->ug_regs
->macstnaddr1
));
787 ugeth_info("macstnaddr2: addr - 0x%08x, val - 0x%08x",
788 (u32
) & ugeth
->ug_regs
->macstnaddr2
,
789 in_be32(&ugeth
->ug_regs
->macstnaddr2
));
790 ugeth_info("uempr : addr - 0x%08x, val - 0x%08x",
791 (u32
) & ugeth
->ug_regs
->uempr
,
792 in_be32(&ugeth
->ug_regs
->uempr
));
793 ugeth_info("utbipar : addr - 0x%08x, val - 0x%08x",
794 (u32
) & ugeth
->ug_regs
->utbipar
,
795 in_be32(&ugeth
->ug_regs
->utbipar
));
796 ugeth_info("uescr : addr - 0x%08x, val - 0x%04x",
797 (u32
) & ugeth
->ug_regs
->uescr
,
798 in_be16(&ugeth
->ug_regs
->uescr
));
799 ugeth_info("tx64 : addr - 0x%08x, val - 0x%08x",
800 (u32
) & ugeth
->ug_regs
->tx64
,
801 in_be32(&ugeth
->ug_regs
->tx64
));
802 ugeth_info("tx127 : addr - 0x%08x, val - 0x%08x",
803 (u32
) & ugeth
->ug_regs
->tx127
,
804 in_be32(&ugeth
->ug_regs
->tx127
));
805 ugeth_info("tx255 : addr - 0x%08x, val - 0x%08x",
806 (u32
) & ugeth
->ug_regs
->tx255
,
807 in_be32(&ugeth
->ug_regs
->tx255
));
808 ugeth_info("rx64 : addr - 0x%08x, val - 0x%08x",
809 (u32
) & ugeth
->ug_regs
->rx64
,
810 in_be32(&ugeth
->ug_regs
->rx64
));
811 ugeth_info("rx127 : addr - 0x%08x, val - 0x%08x",
812 (u32
) & ugeth
->ug_regs
->rx127
,
813 in_be32(&ugeth
->ug_regs
->rx127
));
814 ugeth_info("rx255 : addr - 0x%08x, val - 0x%08x",
815 (u32
) & ugeth
->ug_regs
->rx255
,
816 in_be32(&ugeth
->ug_regs
->rx255
));
817 ugeth_info("txok : addr - 0x%08x, val - 0x%08x",
818 (u32
) & ugeth
->ug_regs
->txok
,
819 in_be32(&ugeth
->ug_regs
->txok
));
820 ugeth_info("txcf : addr - 0x%08x, val - 0x%04x",
821 (u32
) & ugeth
->ug_regs
->txcf
,
822 in_be16(&ugeth
->ug_regs
->txcf
));
823 ugeth_info("tmca : addr - 0x%08x, val - 0x%08x",
824 (u32
) & ugeth
->ug_regs
->tmca
,
825 in_be32(&ugeth
->ug_regs
->tmca
));
826 ugeth_info("tbca : addr - 0x%08x, val - 0x%08x",
827 (u32
) & ugeth
->ug_regs
->tbca
,
828 in_be32(&ugeth
->ug_regs
->tbca
));
829 ugeth_info("rxfok : addr - 0x%08x, val - 0x%08x",
830 (u32
) & ugeth
->ug_regs
->rxfok
,
831 in_be32(&ugeth
->ug_regs
->rxfok
));
832 ugeth_info("rxbok : addr - 0x%08x, val - 0x%08x",
833 (u32
) & ugeth
->ug_regs
->rxbok
,
834 in_be32(&ugeth
->ug_regs
->rxbok
));
835 ugeth_info("rbyt : addr - 0x%08x, val - 0x%08x",
836 (u32
) & ugeth
->ug_regs
->rbyt
,
837 in_be32(&ugeth
->ug_regs
->rbyt
));
838 ugeth_info("rmca : addr - 0x%08x, val - 0x%08x",
839 (u32
) & ugeth
->ug_regs
->rmca
,
840 in_be32(&ugeth
->ug_regs
->rmca
));
841 ugeth_info("rbca : addr - 0x%08x, val - 0x%08x",
842 (u32
) & ugeth
->ug_regs
->rbca
,
843 in_be32(&ugeth
->ug_regs
->rbca
));
844 ugeth_info("scar : addr - 0x%08x, val - 0x%08x",
845 (u32
) & ugeth
->ug_regs
->scar
,
846 in_be32(&ugeth
->ug_regs
->scar
));
847 ugeth_info("scam : addr - 0x%08x, val - 0x%08x",
848 (u32
) & ugeth
->ug_regs
->scam
,
849 in_be32(&ugeth
->ug_regs
->scam
));
851 if (ugeth
->p_thread_data_tx
) {
852 int numThreadsTxNumerical
;
853 switch (ugeth
->ug_info
->numThreadsTx
) {
854 case UCC_GETH_NUM_OF_THREADS_1
:
855 numThreadsTxNumerical
= 1;
857 case UCC_GETH_NUM_OF_THREADS_2
:
858 numThreadsTxNumerical
= 2;
860 case UCC_GETH_NUM_OF_THREADS_4
:
861 numThreadsTxNumerical
= 4;
863 case UCC_GETH_NUM_OF_THREADS_6
:
864 numThreadsTxNumerical
= 6;
866 case UCC_GETH_NUM_OF_THREADS_8
:
867 numThreadsTxNumerical
= 8;
870 numThreadsTxNumerical
= 0;
874 ugeth_info("Thread data TXs:");
875 ugeth_info("Base address: 0x%08x",
876 (u32
) ugeth
->p_thread_data_tx
);
877 for (i
= 0; i
< numThreadsTxNumerical
; i
++) {
878 ugeth_info("Thread data TX[%d]:", i
);
879 ugeth_info("Base address: 0x%08x",
880 (u32
) & ugeth
->p_thread_data_tx
[i
]);
881 mem_disp((u8
*) & ugeth
->p_thread_data_tx
[i
],
882 sizeof(struct ucc_geth_thread_data_tx
));
885 if (ugeth
->p_thread_data_rx
) {
886 int numThreadsRxNumerical
;
887 switch (ugeth
->ug_info
->numThreadsRx
) {
888 case UCC_GETH_NUM_OF_THREADS_1
:
889 numThreadsRxNumerical
= 1;
891 case UCC_GETH_NUM_OF_THREADS_2
:
892 numThreadsRxNumerical
= 2;
894 case UCC_GETH_NUM_OF_THREADS_4
:
895 numThreadsRxNumerical
= 4;
897 case UCC_GETH_NUM_OF_THREADS_6
:
898 numThreadsRxNumerical
= 6;
900 case UCC_GETH_NUM_OF_THREADS_8
:
901 numThreadsRxNumerical
= 8;
904 numThreadsRxNumerical
= 0;
908 ugeth_info("Thread data RX:");
909 ugeth_info("Base address: 0x%08x",
910 (u32
) ugeth
->p_thread_data_rx
);
911 for (i
= 0; i
< numThreadsRxNumerical
; i
++) {
912 ugeth_info("Thread data RX[%d]:", i
);
913 ugeth_info("Base address: 0x%08x",
914 (u32
) & ugeth
->p_thread_data_rx
[i
]);
915 mem_disp((u8
*) & ugeth
->p_thread_data_rx
[i
],
916 sizeof(struct ucc_geth_thread_data_rx
));
919 if (ugeth
->p_exf_glbl_param
) {
920 ugeth_info("EXF global param:");
921 ugeth_info("Base address: 0x%08x",
922 (u32
) ugeth
->p_exf_glbl_param
);
923 mem_disp((u8
*) ugeth
->p_exf_glbl_param
,
924 sizeof(*ugeth
->p_exf_glbl_param
));
926 if (ugeth
->p_tx_glbl_pram
) {
927 ugeth_info("TX global param:");
928 ugeth_info("Base address: 0x%08x", (u32
) ugeth
->p_tx_glbl_pram
);
929 ugeth_info("temoder : addr - 0x%08x, val - 0x%04x",
930 (u32
) & ugeth
->p_tx_glbl_pram
->temoder
,
931 in_be16(&ugeth
->p_tx_glbl_pram
->temoder
));
932 ugeth_info("sqptr : addr - 0x%08x, val - 0x%08x",
933 (u32
) & ugeth
->p_tx_glbl_pram
->sqptr
,
934 in_be32(&ugeth
->p_tx_glbl_pram
->sqptr
));
935 ugeth_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x",
936 (u32
) & ugeth
->p_tx_glbl_pram
->schedulerbasepointer
,
937 in_be32(&ugeth
->p_tx_glbl_pram
->
938 schedulerbasepointer
));
939 ugeth_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x",
940 (u32
) & ugeth
->p_tx_glbl_pram
->txrmonbaseptr
,
941 in_be32(&ugeth
->p_tx_glbl_pram
->txrmonbaseptr
));
942 ugeth_info("tstate : addr - 0x%08x, val - 0x%08x",
943 (u32
) & ugeth
->p_tx_glbl_pram
->tstate
,
944 in_be32(&ugeth
->p_tx_glbl_pram
->tstate
));
945 ugeth_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x",
946 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[0],
947 ugeth
->p_tx_glbl_pram
->iphoffset
[0]);
948 ugeth_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x",
949 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[1],
950 ugeth
->p_tx_glbl_pram
->iphoffset
[1]);
951 ugeth_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x",
952 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[2],
953 ugeth
->p_tx_glbl_pram
->iphoffset
[2]);
954 ugeth_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x",
955 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[3],
956 ugeth
->p_tx_glbl_pram
->iphoffset
[3]);
957 ugeth_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x",
958 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[4],
959 ugeth
->p_tx_glbl_pram
->iphoffset
[4]);
960 ugeth_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x",
961 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[5],
962 ugeth
->p_tx_glbl_pram
->iphoffset
[5]);
963 ugeth_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x",
964 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[6],
965 ugeth
->p_tx_glbl_pram
->iphoffset
[6]);
966 ugeth_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x",
967 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[7],
968 ugeth
->p_tx_glbl_pram
->iphoffset
[7]);
969 ugeth_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x",
970 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[0],
971 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[0]));
972 ugeth_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x",
973 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[1],
974 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[1]));
975 ugeth_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x",
976 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[2],
977 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[2]));
978 ugeth_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x",
979 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[3],
980 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[3]));
981 ugeth_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x",
982 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[4],
983 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[4]));
984 ugeth_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x",
985 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[5],
986 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[5]));
987 ugeth_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x",
988 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[6],
989 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[6]));
990 ugeth_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x",
991 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[7],
992 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[7]));
993 ugeth_info("tqptr : addr - 0x%08x, val - 0x%08x",
994 (u32
) & ugeth
->p_tx_glbl_pram
->tqptr
,
995 in_be32(&ugeth
->p_tx_glbl_pram
->tqptr
));
997 if (ugeth
->p_rx_glbl_pram
) {
998 ugeth_info("RX global param:");
999 ugeth_info("Base address: 0x%08x", (u32
) ugeth
->p_rx_glbl_pram
);
1000 ugeth_info("remoder : addr - 0x%08x, val - 0x%08x",
1001 (u32
) & ugeth
->p_rx_glbl_pram
->remoder
,
1002 in_be32(&ugeth
->p_rx_glbl_pram
->remoder
));
1003 ugeth_info("rqptr : addr - 0x%08x, val - 0x%08x",
1004 (u32
) & ugeth
->p_rx_glbl_pram
->rqptr
,
1005 in_be32(&ugeth
->p_rx_glbl_pram
->rqptr
));
1006 ugeth_info("typeorlen : addr - 0x%08x, val - 0x%04x",
1007 (u32
) & ugeth
->p_rx_glbl_pram
->typeorlen
,
1008 in_be16(&ugeth
->p_rx_glbl_pram
->typeorlen
));
1009 ugeth_info("rxgstpack : addr - 0x%08x, val - 0x%02x",
1010 (u32
) & ugeth
->p_rx_glbl_pram
->rxgstpack
,
1011 ugeth
->p_rx_glbl_pram
->rxgstpack
);
1012 ugeth_info("rxrmonbaseptr : addr - 0x%08x, val - 0x%08x",
1013 (u32
) & ugeth
->p_rx_glbl_pram
->rxrmonbaseptr
,
1014 in_be32(&ugeth
->p_rx_glbl_pram
->rxrmonbaseptr
));
1015 ugeth_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x",
1016 (u32
) & ugeth
->p_rx_glbl_pram
->intcoalescingptr
,
1017 in_be32(&ugeth
->p_rx_glbl_pram
->intcoalescingptr
));
1018 ugeth_info("rstate : addr - 0x%08x, val - 0x%02x",
1019 (u32
) & ugeth
->p_rx_glbl_pram
->rstate
,
1020 ugeth
->p_rx_glbl_pram
->rstate
);
1021 ugeth_info("mrblr : addr - 0x%08x, val - 0x%04x",
1022 (u32
) & ugeth
->p_rx_glbl_pram
->mrblr
,
1023 in_be16(&ugeth
->p_rx_glbl_pram
->mrblr
));
1024 ugeth_info("rbdqptr : addr - 0x%08x, val - 0x%08x",
1025 (u32
) & ugeth
->p_rx_glbl_pram
->rbdqptr
,
1026 in_be32(&ugeth
->p_rx_glbl_pram
->rbdqptr
));
1027 ugeth_info("mflr : addr - 0x%08x, val - 0x%04x",
1028 (u32
) & ugeth
->p_rx_glbl_pram
->mflr
,
1029 in_be16(&ugeth
->p_rx_glbl_pram
->mflr
));
1030 ugeth_info("minflr : addr - 0x%08x, val - 0x%04x",
1031 (u32
) & ugeth
->p_rx_glbl_pram
->minflr
,
1032 in_be16(&ugeth
->p_rx_glbl_pram
->minflr
));
1033 ugeth_info("maxd1 : addr - 0x%08x, val - 0x%04x",
1034 (u32
) & ugeth
->p_rx_glbl_pram
->maxd1
,
1035 in_be16(&ugeth
->p_rx_glbl_pram
->maxd1
));
1036 ugeth_info("maxd2 : addr - 0x%08x, val - 0x%04x",
1037 (u32
) & ugeth
->p_rx_glbl_pram
->maxd2
,
1038 in_be16(&ugeth
->p_rx_glbl_pram
->maxd2
));
1039 ugeth_info("ecamptr : addr - 0x%08x, val - 0x%08x",
1040 (u32
) & ugeth
->p_rx_glbl_pram
->ecamptr
,
1041 in_be32(&ugeth
->p_rx_glbl_pram
->ecamptr
));
1042 ugeth_info("l2qt : addr - 0x%08x, val - 0x%08x",
1043 (u32
) & ugeth
->p_rx_glbl_pram
->l2qt
,
1044 in_be32(&ugeth
->p_rx_glbl_pram
->l2qt
));
1045 ugeth_info("l3qt[0] : addr - 0x%08x, val - 0x%08x",
1046 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[0],
1047 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[0]));
1048 ugeth_info("l3qt[1] : addr - 0x%08x, val - 0x%08x",
1049 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[1],
1050 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[1]));
1051 ugeth_info("l3qt[2] : addr - 0x%08x, val - 0x%08x",
1052 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[2],
1053 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[2]));
1054 ugeth_info("l3qt[3] : addr - 0x%08x, val - 0x%08x",
1055 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[3],
1056 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[3]));
1057 ugeth_info("l3qt[4] : addr - 0x%08x, val - 0x%08x",
1058 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[4],
1059 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[4]));
1060 ugeth_info("l3qt[5] : addr - 0x%08x, val - 0x%08x",
1061 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[5],
1062 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[5]));
1063 ugeth_info("l3qt[6] : addr - 0x%08x, val - 0x%08x",
1064 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[6],
1065 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[6]));
1066 ugeth_info("l3qt[7] : addr - 0x%08x, val - 0x%08x",
1067 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[7],
1068 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[7]));
1069 ugeth_info("vlantype : addr - 0x%08x, val - 0x%04x",
1070 (u32
) & ugeth
->p_rx_glbl_pram
->vlantype
,
1071 in_be16(&ugeth
->p_rx_glbl_pram
->vlantype
));
1072 ugeth_info("vlantci : addr - 0x%08x, val - 0x%04x",
1073 (u32
) & ugeth
->p_rx_glbl_pram
->vlantci
,
1074 in_be16(&ugeth
->p_rx_glbl_pram
->vlantci
));
1075 for (i
= 0; i
< 64; i
++)
1077 ("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x",
1079 (u32
) & ugeth
->p_rx_glbl_pram
->addressfiltering
[i
],
1080 ugeth
->p_rx_glbl_pram
->addressfiltering
[i
]);
1081 ugeth_info("exfGlobalParam : addr - 0x%08x, val - 0x%08x",
1082 (u32
) & ugeth
->p_rx_glbl_pram
->exfGlobalParam
,
1083 in_be32(&ugeth
->p_rx_glbl_pram
->exfGlobalParam
));
1085 if (ugeth
->p_send_q_mem_reg
) {
1086 ugeth_info("Send Q memory registers:");
1087 ugeth_info("Base address: 0x%08x",
1088 (u32
) ugeth
->p_send_q_mem_reg
);
1089 for (i
= 0; i
< ugeth
->ug_info
->numQueuesTx
; i
++) {
1090 ugeth_info("SQQD[%d]:", i
);
1091 ugeth_info("Base address: 0x%08x",
1092 (u32
) & ugeth
->p_send_q_mem_reg
->sqqd
[i
]);
1093 mem_disp((u8
*) & ugeth
->p_send_q_mem_reg
->sqqd
[i
],
1094 sizeof(struct ucc_geth_send_queue_qd
));
1097 if (ugeth
->p_scheduler
) {
1098 ugeth_info("Scheduler:");
1099 ugeth_info("Base address: 0x%08x", (u32
) ugeth
->p_scheduler
);
1100 mem_disp((u8
*) ugeth
->p_scheduler
,
1101 sizeof(*ugeth
->p_scheduler
));
1103 if (ugeth
->p_tx_fw_statistics_pram
) {
1104 ugeth_info("TX FW statistics pram:");
1105 ugeth_info("Base address: 0x%08x",
1106 (u32
) ugeth
->p_tx_fw_statistics_pram
);
1107 mem_disp((u8
*) ugeth
->p_tx_fw_statistics_pram
,
1108 sizeof(*ugeth
->p_tx_fw_statistics_pram
));
1110 if (ugeth
->p_rx_fw_statistics_pram
) {
1111 ugeth_info("RX FW statistics pram:");
1112 ugeth_info("Base address: 0x%08x",
1113 (u32
) ugeth
->p_rx_fw_statistics_pram
);
1114 mem_disp((u8
*) ugeth
->p_rx_fw_statistics_pram
,
1115 sizeof(*ugeth
->p_rx_fw_statistics_pram
));
1117 if (ugeth
->p_rx_irq_coalescing_tbl
) {
1118 ugeth_info("RX IRQ coalescing tables:");
1119 ugeth_info("Base address: 0x%08x",
1120 (u32
) ugeth
->p_rx_irq_coalescing_tbl
);
1121 for (i
= 0; i
< ugeth
->ug_info
->numQueuesRx
; i
++) {
1122 ugeth_info("RX IRQ coalescing table entry[%d]:", i
);
1123 ugeth_info("Base address: 0x%08x",
1124 (u32
) & ugeth
->p_rx_irq_coalescing_tbl
->
1125 coalescingentry
[i
]);
1127 ("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x",
1128 (u32
) & ugeth
->p_rx_irq_coalescing_tbl
->
1129 coalescingentry
[i
].interruptcoalescingmaxvalue
,
1130 in_be32(&ugeth
->p_rx_irq_coalescing_tbl
->
1132 interruptcoalescingmaxvalue
));
1134 ("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x",
1135 (u32
) & ugeth
->p_rx_irq_coalescing_tbl
->
1136 coalescingentry
[i
].interruptcoalescingcounter
,
1137 in_be32(&ugeth
->p_rx_irq_coalescing_tbl
->
1139 interruptcoalescingcounter
));
1142 if (ugeth
->p_rx_bd_qs_tbl
) {
1143 ugeth_info("RX BD QS tables:");
1144 ugeth_info("Base address: 0x%08x", (u32
) ugeth
->p_rx_bd_qs_tbl
);
1145 for (i
= 0; i
< ugeth
->ug_info
->numQueuesRx
; i
++) {
1146 ugeth_info("RX BD QS table[%d]:", i
);
1147 ugeth_info("Base address: 0x%08x",
1148 (u32
) & ugeth
->p_rx_bd_qs_tbl
[i
]);
1150 ("bdbaseptr : addr - 0x%08x, val - 0x%08x",
1151 (u32
) & ugeth
->p_rx_bd_qs_tbl
[i
].bdbaseptr
,
1152 in_be32(&ugeth
->p_rx_bd_qs_tbl
[i
].bdbaseptr
));
1154 ("bdptr : addr - 0x%08x, val - 0x%08x",
1155 (u32
) & ugeth
->p_rx_bd_qs_tbl
[i
].bdptr
,
1156 in_be32(&ugeth
->p_rx_bd_qs_tbl
[i
].bdptr
));
1158 ("externalbdbaseptr: addr - 0x%08x, val - 0x%08x",
1159 (u32
) & ugeth
->p_rx_bd_qs_tbl
[i
].externalbdbaseptr
,
1160 in_be32(&ugeth
->p_rx_bd_qs_tbl
[i
].
1161 externalbdbaseptr
));
1163 ("externalbdptr : addr - 0x%08x, val - 0x%08x",
1164 (u32
) & ugeth
->p_rx_bd_qs_tbl
[i
].externalbdptr
,
1165 in_be32(&ugeth
->p_rx_bd_qs_tbl
[i
].externalbdptr
));
1166 ugeth_info("ucode RX Prefetched BDs:");
1167 ugeth_info("Base address: 0x%08x",
1169 qe_muram_addr(in_be32
1170 (&ugeth
->p_rx_bd_qs_tbl
[i
].
1173 qe_muram_addr(in_be32
1174 (&ugeth
->p_rx_bd_qs_tbl
[i
].
1176 sizeof(struct ucc_geth_rx_prefetched_bds
));
1179 if (ugeth
->p_init_enet_param_shadow
) {
1181 ugeth_info("Init enet param shadow:");
1182 ugeth_info("Base address: 0x%08x",
1183 (u32
) ugeth
->p_init_enet_param_shadow
);
1184 mem_disp((u8
*) ugeth
->p_init_enet_param_shadow
,
1185 sizeof(*ugeth
->p_init_enet_param_shadow
));
1187 size
= sizeof(struct ucc_geth_thread_rx_pram
);
1188 if (ugeth
->ug_info
->rxExtendedFiltering
) {
1190 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING
;
1191 if (ugeth
->ug_info
->largestexternallookupkeysize
==
1192 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
)
1194 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8
;
1195 if (ugeth
->ug_info
->largestexternallookupkeysize
==
1196 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
)
1198 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16
;
1201 dump_init_enet_entries(ugeth
,
1202 &(ugeth
->p_init_enet_param_shadow
->
1204 ENET_INIT_PARAM_MAX_ENTRIES_TX
,
1205 sizeof(struct ucc_geth_thread_tx_pram
),
1206 ugeth
->ug_info
->riscTx
, 0);
1207 dump_init_enet_entries(ugeth
,
1208 &(ugeth
->p_init_enet_param_shadow
->
1210 ENET_INIT_PARAM_MAX_ENTRIES_RX
, size
,
1211 ugeth
->ug_info
->riscRx
, 1);
1216 static void init_default_reg_vals(volatile u32
*upsmr_register
,
1217 volatile u32
*maccfg1_register
,
1218 volatile u32
*maccfg2_register
)
1220 out_be32(upsmr_register
, UCC_GETH_UPSMR_INIT
);
1221 out_be32(maccfg1_register
, UCC_GETH_MACCFG1_INIT
);
1222 out_be32(maccfg2_register
, UCC_GETH_MACCFG2_INIT
);
1225 static int init_half_duplex_params(int alt_beb
,
1226 int back_pressure_no_backoff
,
1229 u8 alt_beb_truncation
,
1230 u8 max_retransmissions
,
1231 u8 collision_window
,
1232 volatile u32
*hafdup_register
)
1236 if ((alt_beb_truncation
> HALFDUP_ALT_BEB_TRUNCATION_MAX
) ||
1237 (max_retransmissions
> HALFDUP_MAX_RETRANSMISSION_MAX
) ||
1238 (collision_window
> HALFDUP_COLLISION_WINDOW_MAX
))
1241 value
= (u32
) (alt_beb_truncation
<< HALFDUP_ALT_BEB_TRUNCATION_SHIFT
);
1244 value
|= HALFDUP_ALT_BEB
;
1245 if (back_pressure_no_backoff
)
1246 value
|= HALFDUP_BACK_PRESSURE_NO_BACKOFF
;
1248 value
|= HALFDUP_NO_BACKOFF
;
1250 value
|= HALFDUP_EXCESSIVE_DEFER
;
1252 value
|= (max_retransmissions
<< HALFDUP_MAX_RETRANSMISSION_SHIFT
);
1254 value
|= collision_window
;
1256 out_be32(hafdup_register
, value
);
1260 static int init_inter_frame_gap_params(u8 non_btb_cs_ipg
,
1264 volatile u32
*ipgifg_register
)
1268 /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back
1270 if (non_btb_cs_ipg
> non_btb_ipg
)
1273 if ((non_btb_cs_ipg
> IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX
) ||
1274 (non_btb_ipg
> IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX
) ||
1275 /*(min_ifg > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */
1276 (btb_ipg
> IPGIFG_BACK_TO_BACK_IFG_MAX
))
1280 ((non_btb_cs_ipg
<< IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT
) &
1281 IPGIFG_NBTB_CS_IPG_MASK
);
1283 ((non_btb_ipg
<< IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT
) &
1284 IPGIFG_NBTB_IPG_MASK
);
1286 ((min_ifg
<< IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT
) &
1287 IPGIFG_MIN_IFG_MASK
);
1288 value
|= (btb_ipg
& IPGIFG_BTB_IPG_MASK
);
1290 out_be32(ipgifg_register
, value
);
1294 static int init_flow_control_params(u32 automatic_flow_control_mode
,
1295 int rx_flow_control_enable
,
1296 int tx_flow_control_enable
,
1298 u16 extension_field
,
1299 volatile u32
*upsmr_register
,
1300 volatile u32
*uempr_register
,
1301 volatile u32
*maccfg1_register
)
1305 /* Set UEMPR register */
1306 value
= (u32
) pause_period
<< UEMPR_PAUSE_TIME_VALUE_SHIFT
;
1307 value
|= (u32
) extension_field
<< UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT
;
1308 out_be32(uempr_register
, value
);
1310 /* Set UPSMR register */
1311 value
= in_be32(upsmr_register
);
1312 value
|= automatic_flow_control_mode
;
1313 out_be32(upsmr_register
, value
);
1315 value
= in_be32(maccfg1_register
);
1316 if (rx_flow_control_enable
)
1317 value
|= MACCFG1_FLOW_RX
;
1318 if (tx_flow_control_enable
)
1319 value
|= MACCFG1_FLOW_TX
;
1320 out_be32(maccfg1_register
, value
);
1325 static int init_hw_statistics_gathering_mode(int enable_hardware_statistics
,
1326 int auto_zero_hardware_statistics
,
1327 volatile u32
*upsmr_register
,
1328 volatile u16
*uescr_register
)
1330 u32 upsmr_value
= 0;
1331 u16 uescr_value
= 0;
1332 /* Enable hardware statistics gathering if requested */
1333 if (enable_hardware_statistics
) {
1334 upsmr_value
= in_be32(upsmr_register
);
1335 upsmr_value
|= UPSMR_HSE
;
1336 out_be32(upsmr_register
, upsmr_value
);
1339 /* Clear hardware statistics counters */
1340 uescr_value
= in_be16(uescr_register
);
1341 uescr_value
|= UESCR_CLRCNT
;
1342 /* Automatically zero hardware statistics counters on read,
1344 if (auto_zero_hardware_statistics
)
1345 uescr_value
|= UESCR_AUTOZ
;
1346 out_be16(uescr_register
, uescr_value
);
1351 static int init_firmware_statistics_gathering_mode(int
1352 enable_tx_firmware_statistics
,
1353 int enable_rx_firmware_statistics
,
1354 volatile u32
*tx_rmon_base_ptr
,
1355 u32 tx_firmware_statistics_structure_address
,
1356 volatile u32
*rx_rmon_base_ptr
,
1357 u32 rx_firmware_statistics_structure_address
,
1358 volatile u16
*temoder_register
,
1359 volatile u32
*remoder_register
)
1361 /* Note: this function does not check if */
1362 /* the parameters it receives are NULL */
1366 if (enable_tx_firmware_statistics
) {
1367 out_be32(tx_rmon_base_ptr
,
1368 tx_firmware_statistics_structure_address
);
1369 temoder_value
= in_be16(temoder_register
);
1370 temoder_value
|= TEMODER_TX_RMON_STATISTICS_ENABLE
;
1371 out_be16(temoder_register
, temoder_value
);
1374 if (enable_rx_firmware_statistics
) {
1375 out_be32(rx_rmon_base_ptr
,
1376 rx_firmware_statistics_structure_address
);
1377 remoder_value
= in_be32(remoder_register
);
1378 remoder_value
|= REMODER_RX_RMON_STATISTICS_ENABLE
;
1379 out_be32(remoder_register
, remoder_value
);
1385 static int init_mac_station_addr_regs(u8 address_byte_0
,
1391 volatile u32
*macstnaddr1_register
,
1392 volatile u32
*macstnaddr2_register
)
1396 /* Example: for a station address of 0x12345678ABCD, */
1397 /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */
1399 /* MACSTNADDR1 Register: */
1402 /* station address byte 5 station address byte 4 */
1404 /* station address byte 3 station address byte 2 */
1405 value
|= (u32
) ((address_byte_2
<< 0) & 0x000000FF);
1406 value
|= (u32
) ((address_byte_3
<< 8) & 0x0000FF00);
1407 value
|= (u32
) ((address_byte_4
<< 16) & 0x00FF0000);
1408 value
|= (u32
) ((address_byte_5
<< 24) & 0xFF000000);
1410 out_be32(macstnaddr1_register
, value
);
1412 /* MACSTNADDR2 Register: */
1415 /* station address byte 1 station address byte 0 */
1417 /* reserved reserved */
1419 value
|= (u32
) ((address_byte_0
<< 16) & 0x00FF0000);
1420 value
|= (u32
) ((address_byte_1
<< 24) & 0xFF000000);
1422 out_be32(macstnaddr2_register
, value
);
1427 static int init_mac_duplex_mode(int full_duplex
,
1428 int limited_to_full_duplex
,
1429 volatile u32
*maccfg2_register
)
1433 /* some interfaces must work in full duplex mode */
1434 if ((full_duplex
== 0) && (limited_to_full_duplex
== 1))
1437 value
= in_be32(maccfg2_register
);
1440 value
|= MACCFG2_FDX
;
1442 value
&= ~MACCFG2_FDX
;
1444 out_be32(maccfg2_register
, value
);
1448 static int init_check_frame_length_mode(int length_check
,
1449 volatile u32
*maccfg2_register
)
1453 value
= in_be32(maccfg2_register
);
1456 value
|= MACCFG2_LC
;
1458 value
&= ~MACCFG2_LC
;
1460 out_be32(maccfg2_register
, value
);
1464 static int init_preamble_length(u8 preamble_length
,
1465 volatile u32
*maccfg2_register
)
1469 if ((preamble_length
< 3) || (preamble_length
> 7))
1472 value
= in_be32(maccfg2_register
);
1473 value
&= ~MACCFG2_PREL_MASK
;
1474 value
|= (preamble_length
<< MACCFG2_PREL_SHIFT
);
1475 out_be32(maccfg2_register
, value
);
1479 static int init_mii_management_configuration(int reset_mgmt
,
1480 int preamble_supress
,
1481 volatile u32
*miimcfg_register
,
1482 volatile u32
*miimind_register
)
1484 unsigned int timeout
= PHY_INIT_TIMEOUT
;
1487 value
= in_be32(miimcfg_register
);
1489 value
|= MIIMCFG_RESET_MANAGEMENT
;
1490 out_be32(miimcfg_register
, value
);
1495 if (preamble_supress
)
1496 value
|= MIIMCFG_NO_PREAMBLE
;
1498 value
|= UCC_GETH_MIIMCFG_MNGMNT_CLC_DIV_INIT
;
1499 out_be32(miimcfg_register
, value
);
1501 /* Wait until the bus is free */
1502 while ((in_be32(miimind_register
) & MIIMIND_BUSY
) && timeout
--)
1506 ugeth_err("%s: The MII Bus is stuck!", __FUNCTION__
);
1513 static int init_rx_parameters(int reject_broadcast
,
1514 int receive_short_frames
,
1515 int promiscuous
, volatile u32
*upsmr_register
)
1519 value
= in_be32(upsmr_register
);
1521 if (reject_broadcast
)
1524 value
&= ~UPSMR_BRO
;
1526 if (receive_short_frames
)
1529 value
&= ~UPSMR_RSH
;
1534 value
&= ~UPSMR_PRO
;
1536 out_be32(upsmr_register
, value
);
1541 static int init_max_rx_buff_len(u16 max_rx_buf_len
,
1542 volatile u16
*mrblr_register
)
1544 /* max_rx_buf_len value must be a multiple of 128 */
1545 if ((max_rx_buf_len
== 0)
1546 || (max_rx_buf_len
% UCC_GETH_MRBLR_ALIGNMENT
))
1549 out_be16(mrblr_register
, max_rx_buf_len
);
1553 static int init_min_frame_len(u16 min_frame_length
,
1554 volatile u16
*minflr_register
,
1555 volatile u16
*mrblr_register
)
1557 u16 mrblr_value
= 0;
1559 mrblr_value
= in_be16(mrblr_register
);
1560 if (min_frame_length
>= (mrblr_value
- 4))
1563 out_be16(minflr_register
, min_frame_length
);
1567 static int adjust_enet_interface(struct ucc_geth_private
*ugeth
)
1569 struct ucc_geth_info
*ug_info
;
1570 struct ucc_geth
*ug_regs
;
1571 struct ucc_fast
*uf_regs
;
1572 enum enet_speed speed
;
1573 int ret_val
, rpm
= 0, tbi
= 0, r10m
= 0, rmm
=
1574 0, limited_to_full_duplex
= 0;
1575 u32 upsmr
, maccfg2
, utbipar
, tbiBaseAddress
;
1578 ugeth_vdbg("%s: IN", __FUNCTION__
);
1580 ug_info
= ugeth
->ug_info
;
1581 ug_regs
= ugeth
->ug_regs
;
1582 uf_regs
= ugeth
->uccf
->uf_regs
;
1584 /* Analyze enet_interface according to Interface Mode Configuration
1587 get_interface_details(ug_info
->enet_interface
, &speed
, &r10m
, &rmm
,
1588 &rpm
, &tbi
, &limited_to_full_duplex
);
1591 ("%s: half duplex not supported in requested configuration.",
1597 maccfg2
= in_be32(&ug_regs
->maccfg2
);
1598 maccfg2
&= ~MACCFG2_INTERFACE_MODE_MASK
;
1599 if ((speed
== ENET_SPEED_10BT
) || (speed
== ENET_SPEED_100BT
))
1600 maccfg2
|= MACCFG2_INTERFACE_MODE_NIBBLE
;
1601 else if (speed
== ENET_SPEED_1000BT
)
1602 maccfg2
|= MACCFG2_INTERFACE_MODE_BYTE
;
1603 maccfg2
|= ug_info
->padAndCrc
;
1604 out_be32(&ug_regs
->maccfg2
, maccfg2
);
1607 upsmr
= in_be32(&uf_regs
->upsmr
);
1608 upsmr
&= ~(UPSMR_RPM
| UPSMR_R10M
| UPSMR_TBIM
| UPSMR_RMM
);
1612 upsmr
|= UPSMR_R10M
;
1614 upsmr
|= UPSMR_TBIM
;
1617 out_be32(&uf_regs
->upsmr
, upsmr
);
1620 utbipar
= in_be32(&ug_regs
->utbipar
);
1621 utbipar
&= ~UTBIPAR_PHY_ADDRESS_MASK
;
1624 (ug_info
->phy_address
+
1625 ugeth
->ug_info
->uf_info
.
1626 ucc_num
) << UTBIPAR_PHY_ADDRESS_SHIFT
;
1630 ugeth
->ug_info
->uf_info
.
1631 ucc_num
) << UTBIPAR_PHY_ADDRESS_SHIFT
;
1632 out_be32(&ug_regs
->utbipar
, utbipar
);
1634 /* Disable autonegotiation in tbi mode, because by default it
1635 comes up in autonegotiation mode. */
1636 /* Note that this depends on proper setting in utbipar register. */
1638 tbiBaseAddress
= in_be32(&ug_regs
->utbipar
);
1639 tbiBaseAddress
&= UTBIPAR_PHY_ADDRESS_MASK
;
1640 tbiBaseAddress
>>= UTBIPAR_PHY_ADDRESS_SHIFT
;
1642 ugeth
->mii_info
->mdio_read(ugeth
->dev
, (u8
) tbiBaseAddress
,
1644 value
&= ~0x1000; /* Turn off autonegotiation */
1645 ugeth
->mii_info
->mdio_write(ugeth
->dev
, (u8
) tbiBaseAddress
,
1646 ENET_TBI_MII_CR
, value
);
1649 ret_val
= init_mac_duplex_mode(1,
1650 limited_to_full_duplex
,
1654 ("%s: half duplex not supported in requested configuration.",
1659 init_check_frame_length_mode(ug_info
->lengthCheckRx
, &ug_regs
->maccfg2
);
1661 ret_val
= init_preamble_length(ug_info
->prel
, &ug_regs
->maccfg2
);
1664 ("%s: Preamble length must be between 3 and 7 inclusive.",
1672 /* Called every time the controller might need to be made
1673 * aware of new link state. The PHY code conveys this
1674 * information through variables in the ugeth structure, and this
1675 * function converts those variables into the appropriate
1676 * register values, and can bring down the device if needed.
1678 static void adjust_link(struct net_device
*dev
)
1680 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
1681 struct ucc_geth
*ug_regs
;
1683 struct ugeth_mii_info
*mii_info
= ugeth
->mii_info
;
1685 ug_regs
= ugeth
->ug_regs
;
1687 if (mii_info
->link
) {
1688 /* Now we make sure that we can be in full duplex mode.
1689 * If not, we operate in half-duplex mode. */
1690 if (mii_info
->duplex
!= ugeth
->oldduplex
) {
1691 if (!(mii_info
->duplex
)) {
1692 tempval
= in_be32(&ug_regs
->maccfg2
);
1693 tempval
&= ~(MACCFG2_FDX
);
1694 out_be32(&ug_regs
->maccfg2
, tempval
);
1696 ugeth_info("%s: Half Duplex", dev
->name
);
1698 tempval
= in_be32(&ug_regs
->maccfg2
);
1699 tempval
|= MACCFG2_FDX
;
1700 out_be32(&ug_regs
->maccfg2
, tempval
);
1702 ugeth_info("%s: Full Duplex", dev
->name
);
1705 ugeth
->oldduplex
= mii_info
->duplex
;
1708 if (mii_info
->speed
!= ugeth
->oldspeed
) {
1709 switch (mii_info
->speed
) {
1711 #ifdef CONFIG_PPC_MPC836x
1712 /* FIXME: This code is for 100Mbs BUG fixing,
1713 remove this when it is fixed!!! */
1714 if (ugeth
->ug_info
->enet_interface
==
1716 /* Run the commands which initialize the PHY */
1719 (u32
) mii_info
->mdio_read(ugeth
->
1720 dev
, mii_info
->mii_id
, 0x1b);
1722 mii_info
->mdio_write(ugeth
->dev
,
1723 mii_info
->mii_id
, 0x1b,
1726 (u32
) mii_info
->mdio_read(ugeth
->
1727 dev
, mii_info
->mii_id
,
1729 mii_info
->mdio_write(ugeth
->dev
,
1730 mii_info
->mii_id
, MII_BMCR
,
1731 (u16
) (tempval
| BMCR_RESET
));
1732 } else if (ugeth
->ug_info
->enet_interface
==
1734 /* Run the commands which initialize the PHY */
1737 (u32
) mii_info
->mdio_read(ugeth
->
1738 dev
, mii_info
->mii_id
, 0x1b);
1739 tempval
= (tempval
& ~0x000f) | 0x000b;
1740 mii_info
->mdio_write(ugeth
->dev
,
1741 mii_info
->mii_id
, 0x1b,
1744 (u32
) mii_info
->mdio_read(ugeth
->
1745 dev
, mii_info
->mii_id
,
1747 mii_info
->mdio_write(ugeth
->dev
,
1748 mii_info
->mii_id
, MII_BMCR
,
1749 (u16
) (tempval
| BMCR_RESET
));
1752 #endif /* CONFIG_MPC8360 */
1753 adjust_enet_interface(ugeth
);
1757 #ifdef CONFIG_PPC_MPC836x
1758 /* FIXME: This code is for 100Mbs BUG fixing,
1759 remove this lines when it will be fixed!!! */
1760 ugeth
->ug_info
->enet_interface
= ENET_100_RGMII
;
1762 (u32
) mii_info
->mdio_read(ugeth
->dev
,
1765 tempval
= (tempval
& ~0x000f) | 0x000b;
1766 mii_info
->mdio_write(ugeth
->dev
,
1767 mii_info
->mii_id
, 0x1b,
1770 (u32
) mii_info
->mdio_read(ugeth
->dev
,
1773 mii_info
->mdio_write(ugeth
->dev
,
1774 mii_info
->mii_id
, MII_BMCR
,
1778 #endif /* CONFIG_MPC8360 */
1779 adjust_enet_interface(ugeth
);
1783 ("%s: Ack! Speed (%d) is not 10/100/1000!",
1784 dev
->name
, mii_info
->speed
);
1788 ugeth_info("%s: Speed %dBT", dev
->name
,
1791 ugeth
->oldspeed
= mii_info
->speed
;
1794 if (!ugeth
->oldlink
) {
1795 ugeth_info("%s: Link is up", dev
->name
);
1797 netif_carrier_on(dev
);
1798 netif_schedule(dev
);
1801 if (ugeth
->oldlink
) {
1802 ugeth_info("%s: Link is down", dev
->name
);
1804 ugeth
->oldspeed
= 0;
1805 ugeth
->oldduplex
= -1;
1806 netif_carrier_off(dev
);
1811 /* Configure the PHY for dev.
1812 * returns 0 if success. -1 if failure
1814 static int init_phy(struct net_device
*dev
)
1816 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
1817 struct phy_info
*curphy
;
1818 struct ucc_mii_mng
*mii_regs
;
1819 struct ugeth_mii_info
*mii_info
;
1822 mii_regs
= &ugeth
->ug_regs
->miimng
;
1825 ugeth
->oldspeed
= 0;
1826 ugeth
->oldduplex
= -1;
1828 mii_info
= kmalloc(sizeof(struct ugeth_mii_info
), GFP_KERNEL
);
1830 if (NULL
== mii_info
) {
1831 ugeth_err("%s: Could not allocate mii_info", dev
->name
);
1835 mii_info
->mii_regs
= mii_regs
;
1836 mii_info
->speed
= SPEED_1000
;
1837 mii_info
->duplex
= DUPLEX_FULL
;
1838 mii_info
->pause
= 0;
1841 mii_info
->advertising
= (ADVERTISED_10baseT_Half
|
1842 ADVERTISED_10baseT_Full
|
1843 ADVERTISED_100baseT_Half
|
1844 ADVERTISED_100baseT_Full
|
1845 ADVERTISED_1000baseT_Full
);
1846 mii_info
->autoneg
= 1;
1848 mii_info
->mii_id
= ugeth
->ug_info
->phy_address
;
1850 mii_info
->dev
= dev
;
1852 mii_info
->mdio_read
= &read_phy_reg
;
1853 mii_info
->mdio_write
= &write_phy_reg
;
1855 ugeth
->mii_info
= mii_info
;
1857 spin_lock_irq(&ugeth
->lock
);
1859 /* Set this UCC to be the master of the MII managment */
1860 ucc_set_qe_mux_mii_mng(ugeth
->ug_info
->uf_info
.ucc_num
);
1862 if (init_mii_management_configuration(1,
1866 &mii_regs
->miimind
)) {
1867 ugeth_err("%s: The MII Bus is stuck!", dev
->name
);
1872 spin_unlock_irq(&ugeth
->lock
);
1874 /* get info for this PHY */
1875 curphy
= get_phy_info(ugeth
->mii_info
);
1877 if (curphy
== NULL
) {
1878 ugeth_err("%s: No PHY found", dev
->name
);
1883 mii_info
->phyinfo
= curphy
;
1885 /* Run the commands which initialize the PHY */
1887 err
= curphy
->init(ugeth
->mii_info
);
1902 #ifdef CONFIG_UGETH_TX_ON_DEMOND
1903 static int ugeth_transmit_on_demand(struct ucc_geth_private
*ugeth
)
1905 struct ucc_fastransmit_on_demand(ugeth
->uccf
);
1911 static int ugeth_graceful_stop_tx(struct ucc_geth_private
*ugeth
)
1913 struct ucc_fast_private
*uccf
;
1919 /* Mask GRACEFUL STOP TX interrupt bit and clear it */
1920 temp
= in_be32(uccf
->p_uccm
);
1922 out_be32(uccf
->p_uccm
, temp
);
1923 out_be32(uccf
->p_ucce
, UCCE_GRA
); /* clear by writing 1 */
1925 /* Issue host command */
1927 ucc_fast_get_qe_cr_subblock(ugeth
->ug_info
->uf_info
.ucc_num
);
1928 qe_issue_cmd(QE_GRACEFUL_STOP_TX
, cecr_subblock
,
1929 QE_CR_PROTOCOL_ETHERNET
, 0);
1931 /* Wait for command to complete */
1933 temp
= in_be32(uccf
->p_ucce
);
1934 } while (!(temp
& UCCE_GRA
));
1936 uccf
->stopped_tx
= 1;
1941 static int ugeth_graceful_stop_rx(struct ucc_geth_private
* ugeth
)
1943 struct ucc_fast_private
*uccf
;
1949 /* Clear acknowledge bit */
1950 temp
= ugeth
->p_rx_glbl_pram
->rxgstpack
;
1951 temp
&= ~GRACEFUL_STOP_ACKNOWLEDGE_RX
;
1952 ugeth
->p_rx_glbl_pram
->rxgstpack
= temp
;
1954 /* Keep issuing command and checking acknowledge bit until
1955 it is asserted, according to spec */
1957 /* Issue host command */
1959 ucc_fast_get_qe_cr_subblock(ugeth
->ug_info
->uf_info
.
1961 qe_issue_cmd(QE_GRACEFUL_STOP_RX
, cecr_subblock
,
1962 QE_CR_PROTOCOL_ETHERNET
, 0);
1964 temp
= ugeth
->p_rx_glbl_pram
->rxgstpack
;
1965 } while (!(temp
& GRACEFUL_STOP_ACKNOWLEDGE_RX
));
1967 uccf
->stopped_rx
= 1;
1972 static int ugeth_restart_tx(struct ucc_geth_private
*ugeth
)
1974 struct ucc_fast_private
*uccf
;
1980 ucc_fast_get_qe_cr_subblock(ugeth
->ug_info
->uf_info
.ucc_num
);
1981 qe_issue_cmd(QE_RESTART_TX
, cecr_subblock
, QE_CR_PROTOCOL_ETHERNET
, 0);
1982 uccf
->stopped_tx
= 0;
1987 static int ugeth_restart_rx(struct ucc_geth_private
*ugeth
)
1989 struct ucc_fast_private
*uccf
;
1995 ucc_fast_get_qe_cr_subblock(ugeth
->ug_info
->uf_info
.ucc_num
);
1996 qe_issue_cmd(QE_RESTART_RX
, cecr_subblock
, QE_CR_PROTOCOL_ETHERNET
,
1998 uccf
->stopped_rx
= 0;
2003 static int ugeth_enable(struct ucc_geth_private
*ugeth
, enum comm_dir mode
)
2005 struct ucc_fast_private
*uccf
;
2006 int enabled_tx
, enabled_rx
;
2010 /* check if the UCC number is in range. */
2011 if (ugeth
->ug_info
->uf_info
.ucc_num
>= UCC_MAX_NUM
) {
2012 ugeth_err("%s: ucc_num out of range.", __FUNCTION__
);
2016 enabled_tx
= uccf
->enabled_tx
;
2017 enabled_rx
= uccf
->enabled_rx
;
2019 /* Get Tx and Rx going again, in case this channel was actively
2021 if ((mode
& COMM_DIR_TX
) && (!enabled_tx
) && uccf
->stopped_tx
)
2022 ugeth_restart_tx(ugeth
);
2023 if ((mode
& COMM_DIR_RX
) && (!enabled_rx
) && uccf
->stopped_rx
)
2024 ugeth_restart_rx(ugeth
);
2026 ucc_fast_enable(uccf
, mode
); /* OK to do even if not disabled */
2032 static int ugeth_disable(struct ucc_geth_private
* ugeth
, enum comm_dir mode
)
2034 struct ucc_fast_private
*uccf
;
2038 /* check if the UCC number is in range. */
2039 if (ugeth
->ug_info
->uf_info
.ucc_num
>= UCC_MAX_NUM
) {
2040 ugeth_err("%s: ucc_num out of range.", __FUNCTION__
);
2044 /* Stop any transmissions */
2045 if ((mode
& COMM_DIR_TX
) && uccf
->enabled_tx
&& !uccf
->stopped_tx
)
2046 ugeth_graceful_stop_tx(ugeth
);
2048 /* Stop any receptions */
2049 if ((mode
& COMM_DIR_RX
) && uccf
->enabled_rx
&& !uccf
->stopped_rx
)
2050 ugeth_graceful_stop_rx(ugeth
);
2052 ucc_fast_disable(ugeth
->uccf
, mode
); /* OK to do even if not enabled */
2057 static void ugeth_dump_regs(struct ucc_geth_private
*ugeth
)
2060 ucc_fast_dump_regs(ugeth
->uccf
);
2066 #ifdef CONFIG_UGETH_FILTERING
2067 static int ugeth_ext_filtering_serialize_tad(struct ucc_geth_tad_params
*
2069 struct qe_fltr_tad
*qe_fltr_tad
)
2073 /* Zero serialized TAD */
2074 memset(qe_fltr_tad
, 0, QE_FLTR_TAD_SIZE
);
2076 qe_fltr_tad
->serialized
[0] |= UCC_GETH_TAD_V
; /* Must have this */
2077 if (p_UccGethTadParams
->rx_non_dynamic_extended_features_mode
||
2078 (p_UccGethTadParams
->vtag_op
!= UCC_GETH_VLAN_OPERATION_TAGGED_NOP
)
2079 || (p_UccGethTadParams
->vnontag_op
!=
2080 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP
)
2082 qe_fltr_tad
->serialized
[0] |= UCC_GETH_TAD_EF
;
2083 if (p_UccGethTadParams
->reject_frame
)
2084 qe_fltr_tad
->serialized
[0] |= UCC_GETH_TAD_REJ
;
2086 (u16
) (((u16
) p_UccGethTadParams
->
2087 vtag_op
) << UCC_GETH_TAD_VTAG_OP_SHIFT
);
2088 qe_fltr_tad
->serialized
[0] |= (u8
) (temp
>> 8); /* upper bits */
2090 qe_fltr_tad
->serialized
[1] |= (u8
) (temp
& 0x00ff); /* lower bits */
2091 if (p_UccGethTadParams
->vnontag_op
==
2092 UCC_GETH_VLAN_OPERATION_NON_TAGGED_Q_TAG_INSERT
)
2093 qe_fltr_tad
->serialized
[1] |= UCC_GETH_TAD_V_NON_VTAG_OP
;
2094 qe_fltr_tad
->serialized
[1] |=
2095 p_UccGethTadParams
->rqos
<< UCC_GETH_TAD_RQOS_SHIFT
;
2097 qe_fltr_tad
->serialized
[2] |=
2098 p_UccGethTadParams
->vpri
<< UCC_GETH_TAD_V_PRIORITY_SHIFT
;
2100 qe_fltr_tad
->serialized
[2] |= (u8
) (p_UccGethTadParams
->vid
>> 8);
2102 qe_fltr_tad
->serialized
[3] |= (u8
) (p_UccGethTadParams
->vid
& 0x00ff);
2107 static struct enet_addr_container_t
2108 *ugeth_82xx_filtering_get_match_addr_in_hash(struct ucc_geth_private
*ugeth
,
2109 struct enet_addr
*p_enet_addr
)
2111 struct enet_addr_container
*enet_addr_cont
;
2112 struct list_head
*p_lh
;
2117 if ((*p_enet_addr
)[0] & ENET_GROUP_ADDR
) {
2118 p_lh
= &ugeth
->group_hash_q
;
2119 p_counter
= &(ugeth
->numGroupAddrInHash
);
2121 p_lh
= &ugeth
->ind_hash_q
;
2122 p_counter
= &(ugeth
->numIndAddrInHash
);
2130 for (i
= 0; i
< num
; i
++) {
2132 (struct enet_addr_container
*)
2133 ENET_ADDR_CONT_ENTRY(dequeue(p_lh
));
2134 for (j
= ENET_NUM_OCTETS_PER_ADDRESS
- 1; j
>= 0; j
--) {
2135 if ((*p_enet_addr
)[j
] != (enet_addr_cont
->address
)[j
])
2138 return enet_addr_cont
; /* Found */
2140 enqueue(p_lh
, &enet_addr_cont
->node
); /* Put it back */
2145 static int ugeth_82xx_filtering_add_addr_in_hash(struct ucc_geth_private
*ugeth
,
2146 struct enet_addr
*p_enet_addr
)
2148 enum ucc_geth_enet_address_recognition_location location
;
2149 struct enet_addr_container
*enet_addr_cont
;
2150 struct list_head
*p_lh
;
2155 if ((*p_enet_addr
)[0] & ENET_GROUP_ADDR
) {
2156 p_lh
= &ugeth
->group_hash_q
;
2157 limit
= ugeth
->ug_info
->maxGroupAddrInHash
;
2159 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_GROUP_HASH
;
2160 p_counter
= &(ugeth
->numGroupAddrInHash
);
2162 p_lh
= &ugeth
->ind_hash_q
;
2163 limit
= ugeth
->ug_info
->maxIndAddrInHash
;
2165 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_INDIVIDUAL_HASH
;
2166 p_counter
= &(ugeth
->numIndAddrInHash
);
2169 if ((enet_addr_cont
=
2170 ugeth_82xx_filtering_get_match_addr_in_hash(ugeth
, p_enet_addr
))) {
2171 list_add(p_lh
, &enet_addr_cont
->node
); /* Put it back */
2174 if ((!p_lh
) || (!(*p_counter
< limit
)))
2176 if (!(enet_addr_cont
= get_enet_addr_container()))
2178 for (i
= 0; i
< ENET_NUM_OCTETS_PER_ADDRESS
; i
++)
2179 (enet_addr_cont
->address
)[i
] = (*p_enet_addr
)[i
];
2180 enet_addr_cont
->location
= location
;
2181 enqueue(p_lh
, &enet_addr_cont
->node
); /* Put it back */
2184 hw_add_addr_in_hash(ugeth
, enet_addr_cont
->address
);
2188 static int ugeth_82xx_filtering_clear_addr_in_hash(struct ucc_geth_private
*ugeth
,
2189 struct enet_addr
*p_enet_addr
)
2191 struct ucc_geth_82xx_address_filtering_pram
*p_82xx_addr_filt
;
2192 struct enet_addr_container
*enet_addr_cont
;
2193 struct ucc_fast_private
*uccf
;
2194 enum comm_dir comm_dir
;
2196 struct list_head
*p_lh
;
2197 u32
*addr_h
, *addr_l
;
2203 (struct ucc_geth_82xx_address_filtering_pram
*) ugeth
->p_rx_glbl_pram
->
2208 ugeth_82xx_filtering_get_match_addr_in_hash(ugeth
, p_enet_addr
)))
2211 /* It's been found and removed from the CQ. */
2212 /* Now destroy its container */
2213 put_enet_addr_container(enet_addr_cont
);
2215 if ((*p_enet_addr
)[0] & ENET_GROUP_ADDR
) {
2216 addr_h
= &(p_82xx_addr_filt
->gaddr_h
);
2217 addr_l
= &(p_82xx_addr_filt
->gaddr_l
);
2218 p_lh
= &ugeth
->group_hash_q
;
2219 p_counter
= &(ugeth
->numGroupAddrInHash
);
2221 addr_h
= &(p_82xx_addr_filt
->iaddr_h
);
2222 addr_l
= &(p_82xx_addr_filt
->iaddr_l
);
2223 p_lh
= &ugeth
->ind_hash_q
;
2224 p_counter
= &(ugeth
->numIndAddrInHash
);
2228 if (uccf
->enabled_tx
)
2229 comm_dir
|= COMM_DIR_TX
;
2230 if (uccf
->enabled_rx
)
2231 comm_dir
|= COMM_DIR_RX
;
2233 ugeth_disable(ugeth
, comm_dir
);
2235 /* Clear the hash table. */
2236 out_be32(addr_h
, 0x00000000);
2237 out_be32(addr_l
, 0x00000000);
2239 /* Add all remaining CQ elements back into hash */
2240 num
= --(*p_counter
);
2241 for (i
= 0; i
< num
; i
++) {
2243 (struct enet_addr_container
*)
2244 ENET_ADDR_CONT_ENTRY(dequeue(p_lh
));
2245 hw_add_addr_in_hash(ugeth
, enet_addr_cont
->address
);
2246 enqueue(p_lh
, &enet_addr_cont
->node
); /* Put it back */
2250 ugeth_enable(ugeth
, comm_dir
);
2254 #endif /* CONFIG_UGETH_FILTERING */
2256 static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private
*
2261 struct ucc_geth_82xx_address_filtering_pram
*p_82xx_addr_filt
;
2262 struct ucc_fast_private
*uccf
;
2263 enum comm_dir comm_dir
;
2264 struct list_head
*p_lh
;
2266 u32
*addr_h
, *addr_l
;
2272 (struct ucc_geth_82xx_address_filtering_pram
*) ugeth
->p_rx_glbl_pram
->
2275 if (enet_addr_type
== ENET_ADDR_TYPE_GROUP
) {
2276 addr_h
= &(p_82xx_addr_filt
->gaddr_h
);
2277 addr_l
= &(p_82xx_addr_filt
->gaddr_l
);
2278 p_lh
= &ugeth
->group_hash_q
;
2279 p_counter
= &(ugeth
->numGroupAddrInHash
);
2280 } else if (enet_addr_type
== ENET_ADDR_TYPE_INDIVIDUAL
) {
2281 addr_h
= &(p_82xx_addr_filt
->iaddr_h
);
2282 addr_l
= &(p_82xx_addr_filt
->iaddr_l
);
2283 p_lh
= &ugeth
->ind_hash_q
;
2284 p_counter
= &(ugeth
->numIndAddrInHash
);
2289 if (uccf
->enabled_tx
)
2290 comm_dir
|= COMM_DIR_TX
;
2291 if (uccf
->enabled_rx
)
2292 comm_dir
|= COMM_DIR_RX
;
2294 ugeth_disable(ugeth
, comm_dir
);
2296 /* Clear the hash table. */
2297 out_be32(addr_h
, 0x00000000);
2298 out_be32(addr_l
, 0x00000000);
2305 /* Delete all remaining CQ elements */
2306 for (i
= 0; i
< num
; i
++)
2307 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh
)));
2312 ugeth_enable(ugeth
, comm_dir
);
2317 #ifdef CONFIG_UGETH_FILTERING
2318 static int ugeth_82xx_filtering_add_addr_in_paddr(struct ucc_geth_private
*ugeth
,
2319 struct enet_addr
*p_enet_addr
,
2324 if ((*p_enet_addr
)[0] & ENET_GROUP_ADDR
)
2326 ("%s: multicast address added to paddr will have no "
2327 "effect - is this what you wanted?",
2330 ugeth
->indAddrRegUsed
[paddr_num
] = 1; /* mark this paddr as used */
2331 /* store address in our database */
2332 for (i
= 0; i
< ENET_NUM_OCTETS_PER_ADDRESS
; i
++)
2333 ugeth
->paddr
[paddr_num
][i
] = (*p_enet_addr
)[i
];
2334 /* put in hardware */
2335 return hw_add_addr_in_paddr(ugeth
, p_enet_addr
, paddr_num
);
2337 #endif /* CONFIG_UGETH_FILTERING */
2339 static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private
*ugeth
,
2342 ugeth
->indAddrRegUsed
[paddr_num
] = 0; /* mark this paddr as not used */
2343 return hw_clear_addr_in_paddr(ugeth
, paddr_num
);/* clear in hardware */
2346 static void ucc_geth_memclean(struct ucc_geth_private
*ugeth
)
2355 ucc_fast_free(ugeth
->uccf
);
2357 if (ugeth
->p_thread_data_tx
) {
2358 qe_muram_free(ugeth
->thread_dat_tx_offset
);
2359 ugeth
->p_thread_data_tx
= NULL
;
2361 if (ugeth
->p_thread_data_rx
) {
2362 qe_muram_free(ugeth
->thread_dat_rx_offset
);
2363 ugeth
->p_thread_data_rx
= NULL
;
2365 if (ugeth
->p_exf_glbl_param
) {
2366 qe_muram_free(ugeth
->exf_glbl_param_offset
);
2367 ugeth
->p_exf_glbl_param
= NULL
;
2369 if (ugeth
->p_rx_glbl_pram
) {
2370 qe_muram_free(ugeth
->rx_glbl_pram_offset
);
2371 ugeth
->p_rx_glbl_pram
= NULL
;
2373 if (ugeth
->p_tx_glbl_pram
) {
2374 qe_muram_free(ugeth
->tx_glbl_pram_offset
);
2375 ugeth
->p_tx_glbl_pram
= NULL
;
2377 if (ugeth
->p_send_q_mem_reg
) {
2378 qe_muram_free(ugeth
->send_q_mem_reg_offset
);
2379 ugeth
->p_send_q_mem_reg
= NULL
;
2381 if (ugeth
->p_scheduler
) {
2382 qe_muram_free(ugeth
->scheduler_offset
);
2383 ugeth
->p_scheduler
= NULL
;
2385 if (ugeth
->p_tx_fw_statistics_pram
) {
2386 qe_muram_free(ugeth
->tx_fw_statistics_pram_offset
);
2387 ugeth
->p_tx_fw_statistics_pram
= NULL
;
2389 if (ugeth
->p_rx_fw_statistics_pram
) {
2390 qe_muram_free(ugeth
->rx_fw_statistics_pram_offset
);
2391 ugeth
->p_rx_fw_statistics_pram
= NULL
;
2393 if (ugeth
->p_rx_irq_coalescing_tbl
) {
2394 qe_muram_free(ugeth
->rx_irq_coalescing_tbl_offset
);
2395 ugeth
->p_rx_irq_coalescing_tbl
= NULL
;
2397 if (ugeth
->p_rx_bd_qs_tbl
) {
2398 qe_muram_free(ugeth
->rx_bd_qs_tbl_offset
);
2399 ugeth
->p_rx_bd_qs_tbl
= NULL
;
2401 if (ugeth
->p_init_enet_param_shadow
) {
2402 return_init_enet_entries(ugeth
,
2403 &(ugeth
->p_init_enet_param_shadow
->
2405 ENET_INIT_PARAM_MAX_ENTRIES_RX
,
2406 ugeth
->ug_info
->riscRx
, 1);
2407 return_init_enet_entries(ugeth
,
2408 &(ugeth
->p_init_enet_param_shadow
->
2410 ENET_INIT_PARAM_MAX_ENTRIES_TX
,
2411 ugeth
->ug_info
->riscTx
, 0);
2412 kfree(ugeth
->p_init_enet_param_shadow
);
2413 ugeth
->p_init_enet_param_shadow
= NULL
;
2415 for (i
= 0; i
< ugeth
->ug_info
->numQueuesTx
; i
++) {
2416 bd
= ugeth
->p_tx_bd_ring
[i
];
2417 for (j
= 0; j
< ugeth
->ug_info
->bdRingLenTx
[i
]; j
++) {
2418 if (ugeth
->tx_skbuff
[i
][j
]) {
2419 dma_unmap_single(NULL
,
2420 ((qe_bd_t
*)bd
)->buf
,
2421 (in_be32((u32
*)bd
) &
2424 dev_kfree_skb_any(ugeth
->tx_skbuff
[i
][j
]);
2425 ugeth
->tx_skbuff
[i
][j
] = NULL
;
2429 kfree(ugeth
->tx_skbuff
[i
]);
2431 if (ugeth
->p_tx_bd_ring
[i
]) {
2432 if (ugeth
->ug_info
->uf_info
.bd_mem_part
==
2434 kfree((void *)ugeth
->tx_bd_ring_offset
[i
]);
2435 else if (ugeth
->ug_info
->uf_info
.bd_mem_part
==
2437 qe_muram_free(ugeth
->tx_bd_ring_offset
[i
]);
2438 ugeth
->p_tx_bd_ring
[i
] = NULL
;
2441 for (i
= 0; i
< ugeth
->ug_info
->numQueuesRx
; i
++) {
2442 if (ugeth
->p_rx_bd_ring
[i
]) {
2443 /* Return existing data buffers in ring */
2444 bd
= ugeth
->p_rx_bd_ring
[i
];
2445 for (j
= 0; j
< ugeth
->ug_info
->bdRingLenRx
[i
]; j
++) {
2446 if (ugeth
->rx_skbuff
[i
][j
]) {
2447 dma_unmap_single(NULL
,
2448 ((struct qe_bd
*)bd
)->buf
,
2450 uf_info
.max_rx_buf_length
+
2451 UCC_GETH_RX_DATA_BUF_ALIGNMENT
,
2454 ugeth
->rx_skbuff
[i
][j
]);
2455 ugeth
->rx_skbuff
[i
][j
] = NULL
;
2457 bd
+= sizeof(struct qe_bd
);
2460 kfree(ugeth
->rx_skbuff
[i
]);
2462 if (ugeth
->ug_info
->uf_info
.bd_mem_part
==
2464 kfree((void *)ugeth
->rx_bd_ring_offset
[i
]);
2465 else if (ugeth
->ug_info
->uf_info
.bd_mem_part
==
2467 qe_muram_free(ugeth
->rx_bd_ring_offset
[i
]);
2468 ugeth
->p_rx_bd_ring
[i
] = NULL
;
2471 while (!list_empty(&ugeth
->group_hash_q
))
2472 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
2473 (dequeue(&ugeth
->group_hash_q
)));
2474 while (!list_empty(&ugeth
->ind_hash_q
))
2475 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
2476 (dequeue(&ugeth
->ind_hash_q
)));
2480 static void ucc_geth_set_multi(struct net_device
*dev
)
2482 struct ucc_geth_private
*ugeth
;
2483 struct dev_mc_list
*dmi
;
2484 struct ucc_fast
*uf_regs
;
2485 struct ucc_geth_82xx_address_filtering_pram
*p_82xx_addr_filt
;
2490 ugeth
= netdev_priv(dev
);
2492 uf_regs
= ugeth
->uccf
->uf_regs
;
2494 if (dev
->flags
& IFF_PROMISC
) {
2496 uf_regs
->upsmr
|= UPSMR_PRO
;
2500 uf_regs
->upsmr
&= ~UPSMR_PRO
;
2503 (struct ucc_geth_82xx_address_filtering_pram
*) ugeth
->
2504 p_rx_glbl_pram
->addressfiltering
;
2506 if (dev
->flags
& IFF_ALLMULTI
) {
2507 /* Catch all multicast addresses, so set the
2508 * filter to all 1's.
2510 out_be32(&p_82xx_addr_filt
->gaddr_h
, 0xffffffff);
2511 out_be32(&p_82xx_addr_filt
->gaddr_l
, 0xffffffff);
2513 /* Clear filter and add the addresses in the list.
2515 out_be32(&p_82xx_addr_filt
->gaddr_h
, 0x0);
2516 out_be32(&p_82xx_addr_filt
->gaddr_l
, 0x0);
2520 for (i
= 0; i
< dev
->mc_count
; i
++, dmi
= dmi
->next
) {
2522 /* Only support group multicast for now.
2524 if (!(dmi
->dmi_addr
[0] & 1))
2527 /* The address in dmi_addr is LSB first,
2528 * and taddr is MSB first. We have to
2529 * copy bytes MSB first from dmi_addr.
2531 mcptr
= (u8
*) dmi
->dmi_addr
+ 5;
2532 tdptr
= (u8
*) tempaddr
;
2533 for (j
= 0; j
< 6; j
++)
2534 *tdptr
++ = *mcptr
--;
2536 /* Ask CPM to run CRC and set bit in
2539 hw_add_addr_in_hash(ugeth
, tempaddr
);
2545 static void ucc_geth_stop(struct ucc_geth_private
*ugeth
)
2547 struct ucc_geth
*ug_regs
= ugeth
->ug_regs
;
2550 ugeth_vdbg("%s: IN", __FUNCTION__
);
2552 /* Disable the controller */
2553 ugeth_disable(ugeth
, COMM_DIR_RX_AND_TX
);
2555 /* Tell the kernel the link is down */
2556 ugeth
->mii_info
->link
= 0;
2557 adjust_link(ugeth
->dev
);
2559 /* Mask all interrupts */
2560 out_be32(ugeth
->uccf
->p_ucce
, 0x00000000);
2562 /* Clear all interrupts */
2563 out_be32(ugeth
->uccf
->p_ucce
, 0xffffffff);
2565 /* Disable Rx and Tx */
2566 tempval
= in_be32(&ug_regs
->maccfg1
);
2567 tempval
&= ~(MACCFG1_ENABLE_RX
| MACCFG1_ENABLE_TX
);
2568 out_be32(&ug_regs
->maccfg1
, tempval
);
2570 if (ugeth
->ug_info
->board_flags
& FSL_UGETH_BRD_HAS_PHY_INTR
) {
2571 /* Clear any pending interrupts */
2572 mii_clear_phy_interrupt(ugeth
->mii_info
);
2574 /* Disable PHY Interrupts */
2575 mii_configure_phy_interrupt(ugeth
->mii_info
,
2576 MII_INTERRUPT_DISABLED
);
2579 free_irq(ugeth
->ug_info
->uf_info
.irq
, ugeth
->dev
);
2581 if (ugeth
->ug_info
->board_flags
& FSL_UGETH_BRD_HAS_PHY_INTR
) {
2582 free_irq(ugeth
->ug_info
->phy_interrupt
, ugeth
->dev
);
2584 del_timer_sync(&ugeth
->phy_info_timer
);
2587 ucc_geth_memclean(ugeth
);
2590 static int ucc_geth_startup(struct ucc_geth_private
*ugeth
)
2592 struct ucc_geth_82xx_address_filtering_pram
*p_82xx_addr_filt
;
2593 struct ucc_geth_init_pram
*p_init_enet_pram
;
2594 struct ucc_fast_private
*uccf
;
2595 struct ucc_geth_info
*ug_info
;
2596 struct ucc_fast_info
*uf_info
;
2597 struct ucc_fast
*uf_regs
;
2598 struct ucc_geth
*ug_regs
;
2599 int ret_val
= -EINVAL
;
2600 u32 remoder
= UCC_GETH_REMODER_INIT
;
2601 u32 init_enet_pram_offset
, cecr_subblock
, command
, maccfg1
;
2602 u32 ifstat
, i
, j
, size
, l2qt
, l3qt
, length
;
2603 u16 temoder
= UCC_GETH_TEMODER_INIT
;
2605 u8 function_code
= 0;
2607 u8 numThreadsRxNumerical
, numThreadsTxNumerical
;
2609 ugeth_vdbg("%s: IN", __FUNCTION__
);
2611 ug_info
= ugeth
->ug_info
;
2612 uf_info
= &ug_info
->uf_info
;
2614 if (!((uf_info
->bd_mem_part
== MEM_PART_SYSTEM
) ||
2615 (uf_info
->bd_mem_part
== MEM_PART_MURAM
))) {
2616 ugeth_err("%s: Bad memory partition value.", __FUNCTION__
);
2621 for (i
= 0; i
< ug_info
->numQueuesRx
; i
++) {
2622 if ((ug_info
->bdRingLenRx
[i
] < UCC_GETH_RX_BD_RING_SIZE_MIN
) ||
2623 (ug_info
->bdRingLenRx
[i
] %
2624 UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT
)) {
2626 ("%s: Rx BD ring length must be multiple of 4,"
2627 " no smaller than 8.", __FUNCTION__
);
2633 for (i
= 0; i
< ug_info
->numQueuesTx
; i
++) {
2634 if (ug_info
->bdRingLenTx
[i
] < UCC_GETH_TX_BD_RING_SIZE_MIN
) {
2636 ("%s: Tx BD ring length must be no smaller than 2.",
2643 if ((uf_info
->max_rx_buf_length
== 0) ||
2644 (uf_info
->max_rx_buf_length
% UCC_GETH_MRBLR_ALIGNMENT
)) {
2646 ("%s: max_rx_buf_length must be non-zero multiple of 128.",
2652 if (ug_info
->numQueuesTx
> NUM_TX_QUEUES
) {
2653 ugeth_err("%s: number of tx queues too large.", __FUNCTION__
);
2658 if (ug_info
->numQueuesRx
> NUM_RX_QUEUES
) {
2659 ugeth_err("%s: number of rx queues too large.", __FUNCTION__
);
2664 for (i
= 0; i
< UCC_GETH_VLAN_PRIORITY_MAX
; i
++) {
2665 if (ug_info
->l2qt
[i
] >= ug_info
->numQueuesRx
) {
2667 ("%s: VLAN priority table entry must not be"
2668 " larger than number of Rx queues.",
2675 for (i
= 0; i
< UCC_GETH_IP_PRIORITY_MAX
; i
++) {
2676 if (ug_info
->l3qt
[i
] >= ug_info
->numQueuesRx
) {
2678 ("%s: IP priority table entry must not be"
2679 " larger than number of Rx queues.",
2685 if (ug_info
->cam
&& !ug_info
->ecamptr
) {
2686 ugeth_err("%s: If cam mode is chosen, must supply cam ptr.",
2691 if ((ug_info
->numStationAddresses
!=
2692 UCC_GETH_NUM_OF_STATION_ADDRESSES_1
)
2693 && ug_info
->rxExtendedFiltering
) {
2694 ugeth_err("%s: Number of station addresses greater than 1 "
2695 "not allowed in extended parsing mode.",
2700 /* Generate uccm_mask for receive */
2701 uf_info
->uccm_mask
= ug_info
->eventRegMask
& UCCE_OTHER
;/* Errors */
2702 for (i
= 0; i
< ug_info
->numQueuesRx
; i
++)
2703 uf_info
->uccm_mask
|= (UCCE_RXBF_SINGLE_MASK
<< i
);
2705 for (i
= 0; i
< ug_info
->numQueuesTx
; i
++)
2706 uf_info
->uccm_mask
|= (UCCE_TXBF_SINGLE_MASK
<< i
);
2707 /* Initialize the general fast UCC block. */
2708 if (ucc_fast_init(uf_info
, &uccf
)) {
2709 ugeth_err("%s: Failed to init uccf.", __FUNCTION__
);
2710 ucc_geth_memclean(ugeth
);
2715 switch (ug_info
->numThreadsRx
) {
2716 case UCC_GETH_NUM_OF_THREADS_1
:
2717 numThreadsRxNumerical
= 1;
2719 case UCC_GETH_NUM_OF_THREADS_2
:
2720 numThreadsRxNumerical
= 2;
2722 case UCC_GETH_NUM_OF_THREADS_4
:
2723 numThreadsRxNumerical
= 4;
2725 case UCC_GETH_NUM_OF_THREADS_6
:
2726 numThreadsRxNumerical
= 6;
2728 case UCC_GETH_NUM_OF_THREADS_8
:
2729 numThreadsRxNumerical
= 8;
2732 ugeth_err("%s: Bad number of Rx threads value.", __FUNCTION__
);
2733 ucc_geth_memclean(ugeth
);
2738 switch (ug_info
->numThreadsTx
) {
2739 case UCC_GETH_NUM_OF_THREADS_1
:
2740 numThreadsTxNumerical
= 1;
2742 case UCC_GETH_NUM_OF_THREADS_2
:
2743 numThreadsTxNumerical
= 2;
2745 case UCC_GETH_NUM_OF_THREADS_4
:
2746 numThreadsTxNumerical
= 4;
2748 case UCC_GETH_NUM_OF_THREADS_6
:
2749 numThreadsTxNumerical
= 6;
2751 case UCC_GETH_NUM_OF_THREADS_8
:
2752 numThreadsTxNumerical
= 8;
2755 ugeth_err("%s: Bad number of Tx threads value.", __FUNCTION__
);
2756 ucc_geth_memclean(ugeth
);
2761 /* Calculate rx_extended_features */
2762 ugeth
->rx_non_dynamic_extended_features
= ug_info
->ipCheckSumCheck
||
2763 ug_info
->ipAddressAlignment
||
2764 (ug_info
->numStationAddresses
!=
2765 UCC_GETH_NUM_OF_STATION_ADDRESSES_1
);
2767 ugeth
->rx_extended_features
= ugeth
->rx_non_dynamic_extended_features
||
2768 (ug_info
->vlanOperationTagged
!= UCC_GETH_VLAN_OPERATION_TAGGED_NOP
)
2769 || (ug_info
->vlanOperationNonTagged
!=
2770 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP
);
2772 uf_regs
= uccf
->uf_regs
;
2773 ug_regs
= (struct ucc_geth
*) (uccf
->uf_regs
);
2774 ugeth
->ug_regs
= ug_regs
;
2776 init_default_reg_vals(&uf_regs
->upsmr
,
2777 &ug_regs
->maccfg1
, &ug_regs
->maccfg2
);
2780 /* For more details see the hardware spec. */
2781 init_rx_parameters(ug_info
->bro
,
2782 ug_info
->rsh
, ug_info
->pro
, &uf_regs
->upsmr
);
2784 /* We're going to ignore other registers for now, */
2785 /* except as needed to get up and running */
2788 /* For more details see the hardware spec. */
2789 init_flow_control_params(ug_info
->aufc
,
2790 ug_info
->receiveFlowControl
,
2792 ug_info
->pausePeriod
,
2793 ug_info
->extensionField
,
2795 &ug_regs
->uempr
, &ug_regs
->maccfg1
);
2797 maccfg1
= in_be32(&ug_regs
->maccfg1
);
2798 maccfg1
|= MACCFG1_ENABLE_RX
;
2799 maccfg1
|= MACCFG1_ENABLE_TX
;
2800 out_be32(&ug_regs
->maccfg1
, maccfg1
);
2803 /* For more details see the hardware spec. */
2804 ret_val
= init_inter_frame_gap_params(ug_info
->nonBackToBackIfgPart1
,
2805 ug_info
->nonBackToBackIfgPart2
,
2807 miminumInterFrameGapEnforcement
,
2808 ug_info
->backToBackInterFrameGap
,
2811 ugeth_err("%s: IPGIFG initialization parameter too large.",
2813 ucc_geth_memclean(ugeth
);
2818 /* For more details see the hardware spec. */
2819 ret_val
= init_half_duplex_params(ug_info
->altBeb
,
2820 ug_info
->backPressureNoBackoff
,
2822 ug_info
->excessDefer
,
2823 ug_info
->altBebTruncation
,
2824 ug_info
->maxRetransmission
,
2825 ug_info
->collisionWindow
,
2828 ugeth_err("%s: Half Duplex initialization parameter too large.",
2830 ucc_geth_memclean(ugeth
);
2835 /* For more details see the hardware spec. */
2836 /* Read only - resets upon read */
2837 ifstat
= in_be32(&ug_regs
->ifstat
);
2840 /* For more details see the hardware spec. */
2841 out_be32(&ug_regs
->uempr
, 0);
2844 /* For more details see the hardware spec. */
2845 init_hw_statistics_gathering_mode((ug_info
->statisticsMode
&
2846 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE
),
2847 0, &uf_regs
->upsmr
, &ug_regs
->uescr
);
2849 /* Allocate Tx bds */
2850 for (j
= 0; j
< ug_info
->numQueuesTx
; j
++) {
2851 /* Allocate in multiple of
2852 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT,
2853 according to spec */
2854 length
= ((ug_info
->bdRingLenTx
[j
] * sizeof(struct qe_bd
))
2855 / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT
)
2856 * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT
;
2857 if ((ug_info
->bdRingLenTx
[j
] * sizeof(struct qe_bd
)) %
2858 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT
)
2859 length
+= UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT
;
2860 if (uf_info
->bd_mem_part
== MEM_PART_SYSTEM
) {
2862 if (UCC_GETH_TX_BD_RING_ALIGNMENT
> 4)
2863 align
= UCC_GETH_TX_BD_RING_ALIGNMENT
;
2864 ugeth
->tx_bd_ring_offset
[j
] =
2865 (u32
) (kmalloc((u32
) (length
+ align
),
2867 if (ugeth
->tx_bd_ring_offset
[j
] != 0)
2868 ugeth
->p_tx_bd_ring
[j
] =
2869 (void*)((ugeth
->tx_bd_ring_offset
[j
] +
2870 align
) & ~(align
- 1));
2871 } else if (uf_info
->bd_mem_part
== MEM_PART_MURAM
) {
2872 ugeth
->tx_bd_ring_offset
[j
] =
2873 qe_muram_alloc(length
,
2874 UCC_GETH_TX_BD_RING_ALIGNMENT
);
2875 if (!IS_MURAM_ERR(ugeth
->tx_bd_ring_offset
[j
]))
2876 ugeth
->p_tx_bd_ring
[j
] =
2877 (u8
*) qe_muram_addr(ugeth
->
2878 tx_bd_ring_offset
[j
]);
2880 if (!ugeth
->p_tx_bd_ring
[j
]) {
2882 ("%s: Can not allocate memory for Tx bd rings.",
2884 ucc_geth_memclean(ugeth
);
2887 /* Zero unused end of bd ring, according to spec */
2888 memset(ugeth
->p_tx_bd_ring
[j
] +
2889 ug_info
->bdRingLenTx
[j
] * sizeof(struct qe_bd
), 0,
2890 length
- ug_info
->bdRingLenTx
[j
] * sizeof(struct qe_bd
));
2893 /* Allocate Rx bds */
2894 for (j
= 0; j
< ug_info
->numQueuesRx
; j
++) {
2895 length
= ug_info
->bdRingLenRx
[j
] * sizeof(struct qe_bd
);
2896 if (uf_info
->bd_mem_part
== MEM_PART_SYSTEM
) {
2898 if (UCC_GETH_RX_BD_RING_ALIGNMENT
> 4)
2899 align
= UCC_GETH_RX_BD_RING_ALIGNMENT
;
2900 ugeth
->rx_bd_ring_offset
[j
] =
2901 (u32
) (kmalloc((u32
) (length
+ align
), GFP_KERNEL
));
2902 if (ugeth
->rx_bd_ring_offset
[j
] != 0)
2903 ugeth
->p_rx_bd_ring
[j
] =
2904 (void*)((ugeth
->rx_bd_ring_offset
[j
] +
2905 align
) & ~(align
- 1));
2906 } else if (uf_info
->bd_mem_part
== MEM_PART_MURAM
) {
2907 ugeth
->rx_bd_ring_offset
[j
] =
2908 qe_muram_alloc(length
,
2909 UCC_GETH_RX_BD_RING_ALIGNMENT
);
2910 if (!IS_MURAM_ERR(ugeth
->rx_bd_ring_offset
[j
]))
2911 ugeth
->p_rx_bd_ring
[j
] =
2912 (u8
*) qe_muram_addr(ugeth
->
2913 rx_bd_ring_offset
[j
]);
2915 if (!ugeth
->p_rx_bd_ring
[j
]) {
2917 ("%s: Can not allocate memory for Rx bd rings.",
2919 ucc_geth_memclean(ugeth
);
2925 for (j
= 0; j
< ug_info
->numQueuesTx
; j
++) {
2926 /* Setup the skbuff rings */
2927 ugeth
->tx_skbuff
[j
] =
2928 (struct sk_buff
**)kmalloc(sizeof(struct sk_buff
*) *
2929 ugeth
->ug_info
->bdRingLenTx
[j
],
2932 if (ugeth
->tx_skbuff
[j
] == NULL
) {
2933 ugeth_err("%s: Could not allocate tx_skbuff",
2935 ucc_geth_memclean(ugeth
);
2939 for (i
= 0; i
< ugeth
->ug_info
->bdRingLenTx
[j
]; i
++)
2940 ugeth
->tx_skbuff
[j
][i
] = NULL
;
2942 ugeth
->skb_curtx
[j
] = ugeth
->skb_dirtytx
[j
] = 0;
2943 bd
= ugeth
->confBd
[j
] = ugeth
->txBd
[j
] = ugeth
->p_tx_bd_ring
[j
];
2944 for (i
= 0; i
< ug_info
->bdRingLenTx
[j
]; i
++) {
2945 /* clear bd buffer */
2946 out_be32(&((struct qe_bd
*)bd
)->buf
, 0);
2947 /* set bd status and length */
2948 out_be32((u32
*)bd
, 0);
2949 bd
+= sizeof(struct qe_bd
);
2951 bd
-= sizeof(struct qe_bd
);
2952 /* set bd status and length */
2953 out_be32((u32
*)bd
, T_W
); /* for last BD set Wrap bit */
2957 for (j
= 0; j
< ug_info
->numQueuesRx
; j
++) {
2958 /* Setup the skbuff rings */
2959 ugeth
->rx_skbuff
[j
] =
2960 (struct sk_buff
**)kmalloc(sizeof(struct sk_buff
*) *
2961 ugeth
->ug_info
->bdRingLenRx
[j
],
2964 if (ugeth
->rx_skbuff
[j
] == NULL
) {
2965 ugeth_err("%s: Could not allocate rx_skbuff",
2967 ucc_geth_memclean(ugeth
);
2971 for (i
= 0; i
< ugeth
->ug_info
->bdRingLenRx
[j
]; i
++)
2972 ugeth
->rx_skbuff
[j
][i
] = NULL
;
2974 ugeth
->skb_currx
[j
] = 0;
2975 bd
= ugeth
->rxBd
[j
] = ugeth
->p_rx_bd_ring
[j
];
2976 for (i
= 0; i
< ug_info
->bdRingLenRx
[j
]; i
++) {
2977 /* set bd status and length */
2978 out_be32((u32
*)bd
, R_I
);
2979 /* clear bd buffer */
2980 out_be32(&((struct qe_bd
*)bd
)->buf
, 0);
2981 bd
+= sizeof(struct qe_bd
);
2983 bd
-= sizeof(struct qe_bd
);
2984 /* set bd status and length */
2985 out_be32((u32
*)bd
, R_W
); /* for last BD set Wrap bit */
2991 /* Tx global PRAM */
2992 /* Allocate global tx parameter RAM page */
2993 ugeth
->tx_glbl_pram_offset
=
2994 qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram
),
2995 UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT
);
2996 if (IS_MURAM_ERR(ugeth
->tx_glbl_pram_offset
)) {
2998 ("%s: Can not allocate DPRAM memory for p_tx_glbl_pram.",
3000 ucc_geth_memclean(ugeth
);
3003 ugeth
->p_tx_glbl_pram
=
3004 (struct ucc_geth_tx_global_pram
*) qe_muram_addr(ugeth
->
3005 tx_glbl_pram_offset
);
3006 /* Zero out p_tx_glbl_pram */
3007 memset(ugeth
->p_tx_glbl_pram
, 0, sizeof(struct ucc_geth_tx_global_pram
));
3009 /* Fill global PRAM */
3012 /* Size varies with number of Tx threads */
3013 ugeth
->thread_dat_tx_offset
=
3014 qe_muram_alloc(numThreadsTxNumerical
*
3015 sizeof(struct ucc_geth_thread_data_tx
) +
3016 32 * (numThreadsTxNumerical
== 1),
3017 UCC_GETH_THREAD_DATA_ALIGNMENT
);
3018 if (IS_MURAM_ERR(ugeth
->thread_dat_tx_offset
)) {
3020 ("%s: Can not allocate DPRAM memory for p_thread_data_tx.",
3022 ucc_geth_memclean(ugeth
);
3026 ugeth
->p_thread_data_tx
=
3027 (struct ucc_geth_thread_data_tx
*) qe_muram_addr(ugeth
->
3028 thread_dat_tx_offset
);
3029 out_be32(&ugeth
->p_tx_glbl_pram
->tqptr
, ugeth
->thread_dat_tx_offset
);
3032 for (i
= 0; i
< UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX
; i
++)
3033 out_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[i
],
3034 ug_info
->vtagtable
[i
]);
3037 for (i
= 0; i
< TX_IP_OFFSET_ENTRY_MAX
; i
++)
3038 ugeth
->p_tx_glbl_pram
->iphoffset
[i
] = ug_info
->iphoffset
[i
];
3041 /* Size varies with number of Tx queues */
3042 ugeth
->send_q_mem_reg_offset
=
3043 qe_muram_alloc(ug_info
->numQueuesTx
*
3044 sizeof(struct ucc_geth_send_queue_qd
),
3045 UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT
);
3046 if (IS_MURAM_ERR(ugeth
->send_q_mem_reg_offset
)) {
3048 ("%s: Can not allocate DPRAM memory for p_send_q_mem_reg.",
3050 ucc_geth_memclean(ugeth
);
3054 ugeth
->p_send_q_mem_reg
=
3055 (struct ucc_geth_send_queue_mem_region
*) qe_muram_addr(ugeth
->
3056 send_q_mem_reg_offset
);
3057 out_be32(&ugeth
->p_tx_glbl_pram
->sqptr
, ugeth
->send_q_mem_reg_offset
);
3059 /* Setup the table */
3060 /* Assume BD rings are already established */
3061 for (i
= 0; i
< ug_info
->numQueuesTx
; i
++) {
3063 ugeth
->p_tx_bd_ring
[i
] + (ug_info
->bdRingLenTx
[i
] -
3064 1) * sizeof(struct qe_bd
);
3065 if (ugeth
->ug_info
->uf_info
.bd_mem_part
== MEM_PART_SYSTEM
) {
3066 out_be32(&ugeth
->p_send_q_mem_reg
->sqqd
[i
].bd_ring_base
,
3067 (u32
) virt_to_phys(ugeth
->p_tx_bd_ring
[i
]));
3068 out_be32(&ugeth
->p_send_q_mem_reg
->sqqd
[i
].
3069 last_bd_completed_address
,
3070 (u32
) virt_to_phys(endOfRing
));
3071 } else if (ugeth
->ug_info
->uf_info
.bd_mem_part
==
3073 out_be32(&ugeth
->p_send_q_mem_reg
->sqqd
[i
].bd_ring_base
,
3074 (u32
) immrbar_virt_to_phys(ugeth
->
3076 out_be32(&ugeth
->p_send_q_mem_reg
->sqqd
[i
].
3077 last_bd_completed_address
,
3078 (u32
) immrbar_virt_to_phys(endOfRing
));
3082 /* schedulerbasepointer */
3084 if (ug_info
->numQueuesTx
> 1) {
3085 /* scheduler exists only if more than 1 tx queue */
3086 ugeth
->scheduler_offset
=
3087 qe_muram_alloc(sizeof(struct ucc_geth_scheduler
),
3088 UCC_GETH_SCHEDULER_ALIGNMENT
);
3089 if (IS_MURAM_ERR(ugeth
->scheduler_offset
)) {
3091 ("%s: Can not allocate DPRAM memory for p_scheduler.",
3093 ucc_geth_memclean(ugeth
);
3097 ugeth
->p_scheduler
=
3098 (struct ucc_geth_scheduler
*) qe_muram_addr(ugeth
->
3100 out_be32(&ugeth
->p_tx_glbl_pram
->schedulerbasepointer
,
3101 ugeth
->scheduler_offset
);
3102 /* Zero out p_scheduler */
3103 memset(ugeth
->p_scheduler
, 0, sizeof(struct ucc_geth_scheduler
));
3105 /* Set values in scheduler */
3106 out_be32(&ugeth
->p_scheduler
->mblinterval
,
3107 ug_info
->mblinterval
);
3108 out_be16(&ugeth
->p_scheduler
->nortsrbytetime
,
3109 ug_info
->nortsrbytetime
);
3110 ugeth
->p_scheduler
->fracsiz
= ug_info
->fracsiz
;
3111 ugeth
->p_scheduler
->strictpriorityq
= ug_info
->strictpriorityq
;
3112 ugeth
->p_scheduler
->txasap
= ug_info
->txasap
;
3113 ugeth
->p_scheduler
->extrabw
= ug_info
->extrabw
;
3114 for (i
= 0; i
< NUM_TX_QUEUES
; i
++)
3115 ugeth
->p_scheduler
->weightfactor
[i
] =
3116 ug_info
->weightfactor
[i
];
3118 /* Set pointers to cpucount registers in scheduler */
3119 ugeth
->p_cpucount
[0] = &(ugeth
->p_scheduler
->cpucount0
);
3120 ugeth
->p_cpucount
[1] = &(ugeth
->p_scheduler
->cpucount1
);
3121 ugeth
->p_cpucount
[2] = &(ugeth
->p_scheduler
->cpucount2
);
3122 ugeth
->p_cpucount
[3] = &(ugeth
->p_scheduler
->cpucount3
);
3123 ugeth
->p_cpucount
[4] = &(ugeth
->p_scheduler
->cpucount4
);
3124 ugeth
->p_cpucount
[5] = &(ugeth
->p_scheduler
->cpucount5
);
3125 ugeth
->p_cpucount
[6] = &(ugeth
->p_scheduler
->cpucount6
);
3126 ugeth
->p_cpucount
[7] = &(ugeth
->p_scheduler
->cpucount7
);
3129 /* schedulerbasepointer */
3130 /* TxRMON_PTR (statistics) */
3132 statisticsMode
& UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX
) {
3133 ugeth
->tx_fw_statistics_pram_offset
=
3134 qe_muram_alloc(sizeof
3135 (struct ucc_geth_tx_firmware_statistics_pram
),
3136 UCC_GETH_TX_STATISTICS_ALIGNMENT
);
3137 if (IS_MURAM_ERR(ugeth
->tx_fw_statistics_pram_offset
)) {
3139 ("%s: Can not allocate DPRAM memory for"
3140 " p_tx_fw_statistics_pram.", __FUNCTION__
);
3141 ucc_geth_memclean(ugeth
);
3144 ugeth
->p_tx_fw_statistics_pram
=
3145 (struct ucc_geth_tx_firmware_statistics_pram
*)
3146 qe_muram_addr(ugeth
->tx_fw_statistics_pram_offset
);
3147 /* Zero out p_tx_fw_statistics_pram */
3148 memset(ugeth
->p_tx_fw_statistics_pram
,
3149 0, sizeof(struct ucc_geth_tx_firmware_statistics_pram
));
3153 /* Already has speed set */
3155 if (ug_info
->numQueuesTx
> 1)
3156 temoder
|= TEMODER_SCHEDULER_ENABLE
;
3157 if (ug_info
->ipCheckSumGenerate
)
3158 temoder
|= TEMODER_IP_CHECKSUM_GENERATE
;
3159 temoder
|= ((ug_info
->numQueuesTx
- 1) << TEMODER_NUM_OF_QUEUES_SHIFT
);
3160 out_be16(&ugeth
->p_tx_glbl_pram
->temoder
, temoder
);
3162 test
= in_be16(&ugeth
->p_tx_glbl_pram
->temoder
);
3164 /* Function code register value to be used later */
3165 function_code
= QE_BMR_BYTE_ORDER_BO_MOT
| UCC_FAST_FUNCTION_CODE_GBL
;
3166 /* Required for QE */
3168 /* function code register */
3169 out_be32(&ugeth
->p_tx_glbl_pram
->tstate
, ((u32
) function_code
) << 24);
3171 /* Rx global PRAM */
3172 /* Allocate global rx parameter RAM page */
3173 ugeth
->rx_glbl_pram_offset
=
3174 qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram
),
3175 UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT
);
3176 if (IS_MURAM_ERR(ugeth
->rx_glbl_pram_offset
)) {
3178 ("%s: Can not allocate DPRAM memory for p_rx_glbl_pram.",
3180 ucc_geth_memclean(ugeth
);
3183 ugeth
->p_rx_glbl_pram
=
3184 (struct ucc_geth_rx_global_pram
*) qe_muram_addr(ugeth
->
3185 rx_glbl_pram_offset
);
3186 /* Zero out p_rx_glbl_pram */
3187 memset(ugeth
->p_rx_glbl_pram
, 0, sizeof(struct ucc_geth_rx_global_pram
));
3189 /* Fill global PRAM */
3192 /* Size varies with number of Rx threads */
3193 ugeth
->thread_dat_rx_offset
=
3194 qe_muram_alloc(numThreadsRxNumerical
*
3195 sizeof(struct ucc_geth_thread_data_rx
),
3196 UCC_GETH_THREAD_DATA_ALIGNMENT
);
3197 if (IS_MURAM_ERR(ugeth
->thread_dat_rx_offset
)) {
3199 ("%s: Can not allocate DPRAM memory for p_thread_data_rx.",
3201 ucc_geth_memclean(ugeth
);
3205 ugeth
->p_thread_data_rx
=
3206 (struct ucc_geth_thread_data_rx
*) qe_muram_addr(ugeth
->
3207 thread_dat_rx_offset
);
3208 out_be32(&ugeth
->p_rx_glbl_pram
->rqptr
, ugeth
->thread_dat_rx_offset
);
3211 out_be16(&ugeth
->p_rx_glbl_pram
->typeorlen
, ug_info
->typeorlen
);
3213 /* rxrmonbaseptr (statistics) */
3215 statisticsMode
& UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX
) {
3216 ugeth
->rx_fw_statistics_pram_offset
=
3217 qe_muram_alloc(sizeof
3218 (struct ucc_geth_rx_firmware_statistics_pram
),
3219 UCC_GETH_RX_STATISTICS_ALIGNMENT
);
3220 if (IS_MURAM_ERR(ugeth
->rx_fw_statistics_pram_offset
)) {
3222 ("%s: Can not allocate DPRAM memory for"
3223 " p_rx_fw_statistics_pram.", __FUNCTION__
);
3224 ucc_geth_memclean(ugeth
);
3227 ugeth
->p_rx_fw_statistics_pram
=
3228 (struct ucc_geth_rx_firmware_statistics_pram
*)
3229 qe_muram_addr(ugeth
->rx_fw_statistics_pram_offset
);
3230 /* Zero out p_rx_fw_statistics_pram */
3231 memset(ugeth
->p_rx_fw_statistics_pram
, 0,
3232 sizeof(struct ucc_geth_rx_firmware_statistics_pram
));
3235 /* intCoalescingPtr */
3237 /* Size varies with number of Rx queues */
3238 ugeth
->rx_irq_coalescing_tbl_offset
=
3239 qe_muram_alloc(ug_info
->numQueuesRx
*
3240 sizeof(struct ucc_geth_rx_interrupt_coalescing_entry
),
3241 UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT
);
3242 if (IS_MURAM_ERR(ugeth
->rx_irq_coalescing_tbl_offset
)) {
3244 ("%s: Can not allocate DPRAM memory for"
3245 " p_rx_irq_coalescing_tbl.", __FUNCTION__
);
3246 ucc_geth_memclean(ugeth
);
3250 ugeth
->p_rx_irq_coalescing_tbl
=
3251 (struct ucc_geth_rx_interrupt_coalescing_table
*)
3252 qe_muram_addr(ugeth
->rx_irq_coalescing_tbl_offset
);
3253 out_be32(&ugeth
->p_rx_glbl_pram
->intcoalescingptr
,
3254 ugeth
->rx_irq_coalescing_tbl_offset
);
3256 /* Fill interrupt coalescing table */
3257 for (i
= 0; i
< ug_info
->numQueuesRx
; i
++) {
3258 out_be32(&ugeth
->p_rx_irq_coalescing_tbl
->coalescingentry
[i
].
3259 interruptcoalescingmaxvalue
,
3260 ug_info
->interruptcoalescingmaxvalue
[i
]);
3261 out_be32(&ugeth
->p_rx_irq_coalescing_tbl
->coalescingentry
[i
].
3262 interruptcoalescingcounter
,
3263 ug_info
->interruptcoalescingmaxvalue
[i
]);
3267 init_max_rx_buff_len(uf_info
->max_rx_buf_length
,
3268 &ugeth
->p_rx_glbl_pram
->mrblr
);
3270 out_be16(&ugeth
->p_rx_glbl_pram
->mflr
, ug_info
->maxFrameLength
);
3272 init_min_frame_len(ug_info
->minFrameLength
,
3273 &ugeth
->p_rx_glbl_pram
->minflr
,
3274 &ugeth
->p_rx_glbl_pram
->mrblr
);
3276 out_be16(&ugeth
->p_rx_glbl_pram
->maxd1
, ug_info
->maxD1Length
);
3278 out_be16(&ugeth
->p_rx_glbl_pram
->maxd2
, ug_info
->maxD2Length
);
3282 for (i
= 0; i
< UCC_GETH_VLAN_PRIORITY_MAX
; i
++)
3283 l2qt
|= (ug_info
->l2qt
[i
] << (28 - 4 * i
));
3284 out_be32(&ugeth
->p_rx_glbl_pram
->l2qt
, l2qt
);
3287 for (j
= 0; j
< UCC_GETH_IP_PRIORITY_MAX
; j
+= 8) {
3289 for (i
= 0; i
< 8; i
++)
3290 l3qt
|= (ug_info
->l3qt
[j
+ i
] << (28 - 4 * i
));
3291 out_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[j
/8], l3qt
);
3295 out_be16(&ugeth
->p_rx_glbl_pram
->vlantype
, ug_info
->vlantype
);
3298 out_be16(&ugeth
->p_rx_glbl_pram
->vlantci
, ug_info
->vlantci
);
3301 out_be32(&ugeth
->p_rx_glbl_pram
->ecamptr
, ug_info
->ecamptr
);
3304 /* Size varies with number of Rx queues */
3305 ugeth
->rx_bd_qs_tbl_offset
=
3306 qe_muram_alloc(ug_info
->numQueuesRx
*
3307 (sizeof(struct ucc_geth_rx_bd_queues_entry
) +
3308 sizeof(struct ucc_geth_rx_prefetched_bds
)),
3309 UCC_GETH_RX_BD_QUEUES_ALIGNMENT
);
3310 if (IS_MURAM_ERR(ugeth
->rx_bd_qs_tbl_offset
)) {
3312 ("%s: Can not allocate DPRAM memory for p_rx_bd_qs_tbl.",
3314 ucc_geth_memclean(ugeth
);
3318 ugeth
->p_rx_bd_qs_tbl
=
3319 (struct ucc_geth_rx_bd_queues_entry
*) qe_muram_addr(ugeth
->
3320 rx_bd_qs_tbl_offset
);
3321 out_be32(&ugeth
->p_rx_glbl_pram
->rbdqptr
, ugeth
->rx_bd_qs_tbl_offset
);
3322 /* Zero out p_rx_bd_qs_tbl */
3323 memset(ugeth
->p_rx_bd_qs_tbl
,
3325 ug_info
->numQueuesRx
* (sizeof(struct ucc_geth_rx_bd_queues_entry
) +
3326 sizeof(struct ucc_geth_rx_prefetched_bds
)));
3328 /* Setup the table */
3329 /* Assume BD rings are already established */
3330 for (i
= 0; i
< ug_info
->numQueuesRx
; i
++) {
3331 if (ugeth
->ug_info
->uf_info
.bd_mem_part
== MEM_PART_SYSTEM
) {
3332 out_be32(&ugeth
->p_rx_bd_qs_tbl
[i
].externalbdbaseptr
,
3333 (u32
) virt_to_phys(ugeth
->p_rx_bd_ring
[i
]));
3334 } else if (ugeth
->ug_info
->uf_info
.bd_mem_part
==
3336 out_be32(&ugeth
->p_rx_bd_qs_tbl
[i
].externalbdbaseptr
,
3337 (u32
) immrbar_virt_to_phys(ugeth
->
3340 /* rest of fields handled by QE */
3344 /* Already has speed set */
3346 if (ugeth
->rx_extended_features
)
3347 remoder
|= REMODER_RX_EXTENDED_FEATURES
;
3348 if (ug_info
->rxExtendedFiltering
)
3349 remoder
|= REMODER_RX_EXTENDED_FILTERING
;
3350 if (ug_info
->dynamicMaxFrameLength
)
3351 remoder
|= REMODER_DYNAMIC_MAX_FRAME_LENGTH
;
3352 if (ug_info
->dynamicMinFrameLength
)
3353 remoder
|= REMODER_DYNAMIC_MIN_FRAME_LENGTH
;
3355 ug_info
->vlanOperationTagged
<< REMODER_VLAN_OPERATION_TAGGED_SHIFT
;
3358 vlanOperationNonTagged
<< REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT
;
3359 remoder
|= ug_info
->rxQoSMode
<< REMODER_RX_QOS_MODE_SHIFT
;
3360 remoder
|= ((ug_info
->numQueuesRx
- 1) << REMODER_NUM_OF_QUEUES_SHIFT
);
3361 if (ug_info
->ipCheckSumCheck
)
3362 remoder
|= REMODER_IP_CHECKSUM_CHECK
;
3363 if (ug_info
->ipAddressAlignment
)
3364 remoder
|= REMODER_IP_ADDRESS_ALIGNMENT
;
3365 out_be32(&ugeth
->p_rx_glbl_pram
->remoder
, remoder
);
3367 /* Note that this function must be called */
3368 /* ONLY AFTER p_tx_fw_statistics_pram */
3369 /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */
3370 init_firmware_statistics_gathering_mode((ug_info
->
3372 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX
),
3373 (ug_info
->statisticsMode
&
3374 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX
),
3375 &ugeth
->p_tx_glbl_pram
->txrmonbaseptr
,
3376 ugeth
->tx_fw_statistics_pram_offset
,
3377 &ugeth
->p_rx_glbl_pram
->rxrmonbaseptr
,
3378 ugeth
->rx_fw_statistics_pram_offset
,
3379 &ugeth
->p_tx_glbl_pram
->temoder
,
3380 &ugeth
->p_rx_glbl_pram
->remoder
);
3382 /* function code register */
3383 ugeth
->p_rx_glbl_pram
->rstate
= function_code
;
3385 /* initialize extended filtering */
3386 if (ug_info
->rxExtendedFiltering
) {
3387 if (!ug_info
->extendedFilteringChainPointer
) {
3388 ugeth_err("%s: Null Extended Filtering Chain Pointer.",
3390 ucc_geth_memclean(ugeth
);
3394 /* Allocate memory for extended filtering Mode Global
3396 ugeth
->exf_glbl_param_offset
=
3397 qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram
),
3398 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT
);
3399 if (IS_MURAM_ERR(ugeth
->exf_glbl_param_offset
)) {
3401 ("%s: Can not allocate DPRAM memory for"
3402 " p_exf_glbl_param.", __FUNCTION__
);
3403 ucc_geth_memclean(ugeth
);
3407 ugeth
->p_exf_glbl_param
=
3408 (struct ucc_geth_exf_global_pram
*) qe_muram_addr(ugeth
->
3409 exf_glbl_param_offset
);
3410 out_be32(&ugeth
->p_rx_glbl_pram
->exfGlobalParam
,
3411 ugeth
->exf_glbl_param_offset
);
3412 out_be32(&ugeth
->p_exf_glbl_param
->l2pcdptr
,
3413 (u32
) ug_info
->extendedFilteringChainPointer
);
3415 } else { /* initialize 82xx style address filtering */
3417 /* Init individual address recognition registers to disabled */
3419 for (j
= 0; j
< NUM_OF_PADDRS
; j
++)
3420 ugeth_82xx_filtering_clear_addr_in_paddr(ugeth
, (u8
) j
);
3422 /* Create CQs for hash tables */
3423 if (ug_info
->maxGroupAddrInHash
> 0) {
3424 INIT_LIST_HEAD(&ugeth
->group_hash_q
);
3426 if (ug_info
->maxIndAddrInHash
> 0) {
3427 INIT_LIST_HEAD(&ugeth
->ind_hash_q
);
3430 (struct ucc_geth_82xx_address_filtering_pram
*) ugeth
->
3431 p_rx_glbl_pram
->addressfiltering
;
3433 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth
,
3434 ENET_ADDR_TYPE_GROUP
);
3435 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth
,
3436 ENET_ADDR_TYPE_INDIVIDUAL
);
3440 * Initialize UCC at QE level
3443 command
= QE_INIT_TX_RX
;
3445 /* Allocate shadow InitEnet command parameter structure.
3446 * This is needed because after the InitEnet command is executed,
3447 * the structure in DPRAM is released, because DPRAM is a premium
3449 * This shadow structure keeps a copy of what was done so that the
3450 * allocated resources can be released when the channel is freed.
3452 if (!(ugeth
->p_init_enet_param_shadow
=
3453 (struct ucc_geth_init_pram
*) kmalloc(sizeof(struct ucc_geth_init_pram
),
3456 ("%s: Can not allocate memory for"
3457 " p_UccInitEnetParamShadows.", __FUNCTION__
);
3458 ucc_geth_memclean(ugeth
);
3461 /* Zero out *p_init_enet_param_shadow */
3462 memset((char *)ugeth
->p_init_enet_param_shadow
,
3463 0, sizeof(struct ucc_geth_init_pram
));
3465 /* Fill shadow InitEnet command parameter structure */
3467 ugeth
->p_init_enet_param_shadow
->resinit1
=
3468 ENET_INIT_PARAM_MAGIC_RES_INIT1
;
3469 ugeth
->p_init_enet_param_shadow
->resinit2
=
3470 ENET_INIT_PARAM_MAGIC_RES_INIT2
;
3471 ugeth
->p_init_enet_param_shadow
->resinit3
=
3472 ENET_INIT_PARAM_MAGIC_RES_INIT3
;
3473 ugeth
->p_init_enet_param_shadow
->resinit4
=
3474 ENET_INIT_PARAM_MAGIC_RES_INIT4
;
3475 ugeth
->p_init_enet_param_shadow
->resinit5
=
3476 ENET_INIT_PARAM_MAGIC_RES_INIT5
;
3477 ugeth
->p_init_enet_param_shadow
->rgftgfrxglobal
|=
3478 ((u32
) ug_info
->numThreadsRx
) << ENET_INIT_PARAM_RGF_SHIFT
;
3479 ugeth
->p_init_enet_param_shadow
->rgftgfrxglobal
|=
3480 ((u32
) ug_info
->numThreadsTx
) << ENET_INIT_PARAM_TGF_SHIFT
;
3482 ugeth
->p_init_enet_param_shadow
->rgftgfrxglobal
|=
3483 ugeth
->rx_glbl_pram_offset
| ug_info
->riscRx
;
3484 if ((ug_info
->largestexternallookupkeysize
!=
3485 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
)
3486 && (ug_info
->largestexternallookupkeysize
!=
3487 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES
)
3488 && (ug_info
->largestexternallookupkeysize
!=
3489 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES
)) {
3490 ugeth_err("%s: Invalid largest External Lookup Key Size.",
3492 ucc_geth_memclean(ugeth
);
3495 ugeth
->p_init_enet_param_shadow
->largestexternallookupkeysize
=
3496 ug_info
->largestexternallookupkeysize
;
3497 size
= sizeof(struct ucc_geth_thread_rx_pram
);
3498 if (ug_info
->rxExtendedFiltering
) {
3499 size
+= THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING
;
3500 if (ug_info
->largestexternallookupkeysize
==
3501 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
)
3503 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8
;
3504 if (ug_info
->largestexternallookupkeysize
==
3505 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
)
3507 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16
;
3510 if ((ret_val
= fill_init_enet_entries(ugeth
, &(ugeth
->
3511 p_init_enet_param_shadow
->rxthread
[0]),
3512 (u8
) (numThreadsRxNumerical
+ 1)
3513 /* Rx needs one extra for terminator */
3514 , size
, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT
,
3515 ug_info
->riscRx
, 1)) != 0) {
3516 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
3518 ucc_geth_memclean(ugeth
);
3522 ugeth
->p_init_enet_param_shadow
->txglobal
=
3523 ugeth
->tx_glbl_pram_offset
| ug_info
->riscTx
;
3525 fill_init_enet_entries(ugeth
,
3526 &(ugeth
->p_init_enet_param_shadow
->
3527 txthread
[0]), numThreadsTxNumerical
,
3528 sizeof(struct ucc_geth_thread_tx_pram
),
3529 UCC_GETH_THREAD_TX_PRAM_ALIGNMENT
,
3530 ug_info
->riscTx
, 0)) != 0) {
3531 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
3533 ucc_geth_memclean(ugeth
);
3537 /* Load Rx bds with buffers */
3538 for (i
= 0; i
< ug_info
->numQueuesRx
; i
++) {
3539 if ((ret_val
= rx_bd_buffer_set(ugeth
, (u8
) i
)) != 0) {
3540 ugeth_err("%s: Can not fill Rx bds with buffers.",
3542 ucc_geth_memclean(ugeth
);
3547 /* Allocate InitEnet command parameter structure */
3548 init_enet_pram_offset
= qe_muram_alloc(sizeof(struct ucc_geth_init_pram
), 4);
3549 if (IS_MURAM_ERR(init_enet_pram_offset
)) {
3551 ("%s: Can not allocate DPRAM memory for p_init_enet_pram.",
3553 ucc_geth_memclean(ugeth
);
3557 (struct ucc_geth_init_pram
*) qe_muram_addr(init_enet_pram_offset
);
3559 /* Copy shadow InitEnet command parameter structure into PRAM */
3560 p_init_enet_pram
->resinit1
= ugeth
->p_init_enet_param_shadow
->resinit1
;
3561 p_init_enet_pram
->resinit2
= ugeth
->p_init_enet_param_shadow
->resinit2
;
3562 p_init_enet_pram
->resinit3
= ugeth
->p_init_enet_param_shadow
->resinit3
;
3563 p_init_enet_pram
->resinit4
= ugeth
->p_init_enet_param_shadow
->resinit4
;
3564 out_be16(&p_init_enet_pram
->resinit5
,
3565 ugeth
->p_init_enet_param_shadow
->resinit5
);
3566 p_init_enet_pram
->largestexternallookupkeysize
=
3567 ugeth
->p_init_enet_param_shadow
->largestexternallookupkeysize
;
3568 out_be32(&p_init_enet_pram
->rgftgfrxglobal
,
3569 ugeth
->p_init_enet_param_shadow
->rgftgfrxglobal
);
3570 for (i
= 0; i
< ENET_INIT_PARAM_MAX_ENTRIES_RX
; i
++)
3571 out_be32(&p_init_enet_pram
->rxthread
[i
],
3572 ugeth
->p_init_enet_param_shadow
->rxthread
[i
]);
3573 out_be32(&p_init_enet_pram
->txglobal
,
3574 ugeth
->p_init_enet_param_shadow
->txglobal
);
3575 for (i
= 0; i
< ENET_INIT_PARAM_MAX_ENTRIES_TX
; i
++)
3576 out_be32(&p_init_enet_pram
->txthread
[i
],
3577 ugeth
->p_init_enet_param_shadow
->txthread
[i
]);
3579 /* Issue QE command */
3581 ucc_fast_get_qe_cr_subblock(ugeth
->ug_info
->uf_info
.ucc_num
);
3582 qe_issue_cmd(command
, cecr_subblock
, QE_CR_PROTOCOL_ETHERNET
,
3583 init_enet_pram_offset
);
3585 /* Free InitEnet command parameter */
3586 qe_muram_free(init_enet_pram_offset
);
3591 /* returns a net_device_stats structure pointer */
3592 static struct net_device_stats
*ucc_geth_get_stats(struct net_device
*dev
)
3594 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3596 return &(ugeth
->stats
);
3599 /* ucc_geth_timeout gets called when a packet has not been
3600 * transmitted after a set amount of time.
3601 * For now, assume that clearing out all the structures, and
3602 * starting over will fix the problem. */
3603 static void ucc_geth_timeout(struct net_device
*dev
)
3605 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3607 ugeth_vdbg("%s: IN", __FUNCTION__
);
3609 ugeth
->stats
.tx_errors
++;
3611 ugeth_dump_regs(ugeth
);
3613 if (dev
->flags
& IFF_UP
) {
3614 ucc_geth_stop(ugeth
);
3615 ucc_geth_startup(ugeth
);
3618 netif_schedule(dev
);
3621 /* This is called by the kernel when a frame is ready for transmission. */
3622 /* It is pointed to by the dev->hard_start_xmit function pointer */
3623 static int ucc_geth_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
3625 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3626 u8
*bd
; /* BD pointer */
3630 ugeth_vdbg("%s: IN", __FUNCTION__
);
3632 spin_lock_irq(&ugeth
->lock
);
3634 ugeth
->stats
.tx_bytes
+= skb
->len
;
3636 /* Start from the next BD that should be filled */
3637 bd
= ugeth
->txBd
[txQ
];
3638 bd_status
= in_be32((u32
*)bd
);
3639 /* Save the skb pointer so we can free it later */
3640 ugeth
->tx_skbuff
[txQ
][ugeth
->skb_curtx
[txQ
]] = skb
;
3642 /* Update the current skb pointer (wrapping if this was the last) */
3643 ugeth
->skb_curtx
[txQ
] =
3644 (ugeth
->skb_curtx
[txQ
] +
3645 1) & TX_RING_MOD_MASK(ugeth
->ug_info
->bdRingLenTx
[txQ
]);
3647 /* set up the buffer descriptor */
3648 out_be32(&((struct qe_bd
*)bd
)->buf
,
3649 dma_map_single(NULL
, skb
->data
, skb
->len
, DMA_TO_DEVICE
));
3651 /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */
3653 bd_status
= (bd_status
& T_W
) | T_R
| T_I
| T_L
| skb
->len
;
3655 /* set bd status and length */
3656 out_be32((u32
*)bd
, bd_status
);
3658 dev
->trans_start
= jiffies
;
3660 /* Move to next BD in the ring */
3661 if (!(bd_status
& T_W
))
3662 ugeth
->txBd
[txQ
] = bd
+ sizeof(struct qe_bd
);
3664 ugeth
->txBd
[txQ
] = ugeth
->p_tx_bd_ring
[txQ
];
3666 /* If the next BD still needs to be cleaned up, then the bds
3667 are full. We need to tell the kernel to stop sending us stuff. */
3668 if (bd
== ugeth
->confBd
[txQ
]) {
3669 if (!netif_queue_stopped(dev
))
3670 netif_stop_queue(dev
);
3673 if (ugeth
->p_scheduler
) {
3674 ugeth
->cpucount
[txQ
]++;
3675 /* Indicate to QE that there are more Tx bds ready for
3677 /* This is done by writing a running counter of the bd
3678 count to the scheduler PRAM. */
3679 out_be16(ugeth
->p_cpucount
[txQ
], ugeth
->cpucount
[txQ
]);
3682 spin_unlock_irq(&ugeth
->lock
);
3687 static int ucc_geth_rx(struct ucc_geth_private
*ugeth
, u8 rxQ
, int rx_work_limit
)
3689 struct sk_buff
*skb
;
3691 u16 length
, howmany
= 0;
3695 ugeth_vdbg("%s: IN", __FUNCTION__
);
3697 spin_lock(&ugeth
->lock
);
3698 /* collect received buffers */
3699 bd
= ugeth
->rxBd
[rxQ
];
3701 bd_status
= in_be32((u32
*)bd
);
3703 /* while there are received buffers and BD is full (~R_E) */
3704 while (!((bd_status
& (R_E
)) || (--rx_work_limit
< 0))) {
3705 bdBuffer
= (u8
*) in_be32(&((struct qe_bd
*)bd
)->buf
);
3706 length
= (u16
) ((bd_status
& BD_LENGTH_MASK
) - 4);
3707 skb
= ugeth
->rx_skbuff
[rxQ
][ugeth
->skb_currx
[rxQ
]];
3709 /* determine whether buffer is first, last, first and last
3710 (single buffer frame) or middle (not first and not last) */
3712 (!(bd_status
& (R_F
| R_L
))) ||
3713 (bd_status
& R_ERRORS_FATAL
)) {
3714 ugeth_vdbg("%s, %d: ERROR!!! skb - 0x%08x",
3715 __FUNCTION__
, __LINE__
, (u32
) skb
);
3717 dev_kfree_skb_any(skb
);
3719 ugeth
->rx_skbuff
[rxQ
][ugeth
->skb_currx
[rxQ
]] = NULL
;
3720 ugeth
->stats
.rx_dropped
++;
3722 ugeth
->stats
.rx_packets
++;
3725 /* Prep the skb for the packet */
3726 skb_put(skb
, length
);
3728 /* Tell the skb what kind of packet this is */
3729 skb
->protocol
= eth_type_trans(skb
, ugeth
->dev
);
3731 ugeth
->stats
.rx_bytes
+= length
;
3732 /* Send the packet up the stack */
3733 #ifdef CONFIG_UGETH_NAPI
3734 netif_receive_skb(skb
);
3737 #endif /* CONFIG_UGETH_NAPI */
3740 ugeth
->dev
->last_rx
= jiffies
;
3742 skb
= get_new_skb(ugeth
, bd
);
3744 ugeth_warn("%s: No Rx Data Buffer", __FUNCTION__
);
3745 spin_unlock(&ugeth
->lock
);
3746 ugeth
->stats
.rx_dropped
++;
3750 ugeth
->rx_skbuff
[rxQ
][ugeth
->skb_currx
[rxQ
]] = skb
;
3752 /* update to point at the next skb */
3753 ugeth
->skb_currx
[rxQ
] =
3754 (ugeth
->skb_currx
[rxQ
] +
3755 1) & RX_RING_MOD_MASK(ugeth
->ug_info
->bdRingLenRx
[rxQ
]);
3757 if (bd_status
& R_W
)
3758 bd
= ugeth
->p_rx_bd_ring
[rxQ
];
3760 bd
+= sizeof(struct qe_bd
);
3762 bd_status
= in_be32((u32
*)bd
);
3765 ugeth
->rxBd
[rxQ
] = bd
;
3766 spin_unlock(&ugeth
->lock
);
3770 static int ucc_geth_tx(struct net_device
*dev
, u8 txQ
)
3772 /* Start from the next BD that should be filled */
3773 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3774 u8
*bd
; /* BD pointer */
3777 bd
= ugeth
->confBd
[txQ
];
3778 bd_status
= in_be32((u32
*)bd
);
3780 /* Normal processing. */
3781 while ((bd_status
& T_R
) == 0) {
3782 /* BD contains already transmitted buffer. */
3783 /* Handle the transmitted buffer and release */
3784 /* the BD to be used with the current frame */
3786 if ((bd
= ugeth
->txBd
[txQ
]) && (netif_queue_stopped(dev
) == 0))
3789 ugeth
->stats
.tx_packets
++;
3791 /* Free the sk buffer associated with this TxBD */
3792 dev_kfree_skb_irq(ugeth
->
3793 tx_skbuff
[txQ
][ugeth
->skb_dirtytx
[txQ
]]);
3794 ugeth
->tx_skbuff
[txQ
][ugeth
->skb_dirtytx
[txQ
]] = NULL
;
3795 ugeth
->skb_dirtytx
[txQ
] =
3796 (ugeth
->skb_dirtytx
[txQ
] +
3797 1) & TX_RING_MOD_MASK(ugeth
->ug_info
->bdRingLenTx
[txQ
]);
3799 /* We freed a buffer, so now we can restart transmission */
3800 if (netif_queue_stopped(dev
))
3801 netif_wake_queue(dev
);
3803 /* Advance the confirmation BD pointer */
3804 if (!(bd_status
& T_W
))
3805 ugeth
->confBd
[txQ
] += sizeof(struct qe_bd
);
3807 ugeth
->confBd
[txQ
] = ugeth
->p_tx_bd_ring
[txQ
];
3812 #ifdef CONFIG_UGETH_NAPI
3813 static int ucc_geth_poll(struct net_device
*dev
, int *budget
)
3815 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3817 int rx_work_limit
= *budget
;
3820 if (rx_work_limit
> dev
->quota
)
3821 rx_work_limit
= dev
->quota
;
3823 howmany
= ucc_geth_rx(ugeth
, rxQ
, rx_work_limit
);
3825 dev
->quota
-= howmany
;
3826 rx_work_limit
-= howmany
;
3829 if (rx_work_limit
>= 0)
3830 netif_rx_complete(dev
);
3832 return (rx_work_limit
< 0) ? 1 : 0;
3834 #endif /* CONFIG_UGETH_NAPI */
3836 static irqreturn_t
ucc_geth_irq_handler(int irq
, void *info
)
3838 struct net_device
*dev
= (struct net_device
*)info
;
3839 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3840 struct ucc_fast_private
*uccf
;
3841 struct ucc_geth_info
*ug_info
;
3842 register u32 ucce
= 0;
3843 register u32 bit_mask
= UCCE_RXBF_SINGLE_MASK
;
3844 register u32 tx_mask
= UCCE_TXBF_SINGLE_MASK
;
3847 ugeth_vdbg("%s: IN", __FUNCTION__
);
3853 ug_info
= ugeth
->ug_info
;
3856 ucce
|= (u32
) (in_be32(uccf
->p_ucce
) & in_be32(uccf
->p_uccm
));
3858 /* clear event bits for next time */
3859 /* Side effect here is to mask ucce variable
3860 for future processing below. */
3861 out_be32(uccf
->p_ucce
, ucce
); /* Clear with ones,
3862 but only bits in UCCM */
3864 /* We ignore Tx interrupts because Tx confirmation is
3865 done inside Tx routine */
3867 for (i
= 0; i
< ug_info
->numQueuesRx
; i
++) {
3868 if (ucce
& bit_mask
)
3869 ucc_geth_rx(ugeth
, i
,
3870 (int)ugeth
->ug_info
->
3876 for (i
= 0; i
< ug_info
->numQueuesTx
; i
++) {
3878 ucc_geth_tx(dev
, i
);
3884 if (ucce
& UCCE_BSY
) {
3885 ugeth_vdbg("Got BUSY irq!!!!");
3886 ugeth
->stats
.rx_errors
++;
3889 if (ucce
& UCCE_OTHER
) {
3890 ugeth_vdbg("Got frame with error (ucce - 0x%08x)!!!!",
3892 ugeth
->stats
.rx_errors
++;
3901 static irqreturn_t
phy_interrupt(int irq
, void *dev_id
)
3903 struct net_device
*dev
= (struct net_device
*)dev_id
;
3904 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3906 ugeth_vdbg("%s: IN", __FUNCTION__
);
3908 /* Clear the interrupt */
3909 mii_clear_phy_interrupt(ugeth
->mii_info
);
3911 /* Disable PHY interrupts */
3912 mii_configure_phy_interrupt(ugeth
->mii_info
, MII_INTERRUPT_DISABLED
);
3914 /* Schedule the phy change */
3915 schedule_work(&ugeth
->tq
);
3920 /* Scheduled by the phy_interrupt/timer to handle PHY changes */
3921 static void ugeth_phy_change(void *data
)
3923 struct net_device
*dev
= (struct net_device
*)data
;
3924 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3925 struct ucc_geth
*ug_regs
;
3928 ugeth_vdbg("%s: IN", __FUNCTION__
);
3930 ug_regs
= ugeth
->ug_regs
;
3932 /* Delay to give the PHY a chance to change the
3936 /* Update the link, speed, duplex */
3937 result
= ugeth
->mii_info
->phyinfo
->read_status(ugeth
->mii_info
);
3939 /* Adjust the known status as long as the link
3940 * isn't still coming up */
3941 if ((0 == result
) || (ugeth
->mii_info
->link
== 0))
3944 /* Reenable interrupts, if needed */
3945 if (ugeth
->ug_info
->board_flags
& FSL_UGETH_BRD_HAS_PHY_INTR
)
3946 mii_configure_phy_interrupt(ugeth
->mii_info
,
3947 MII_INTERRUPT_ENABLED
);
3950 /* Called every so often on systems that don't interrupt
3951 * the core for PHY changes */
3952 static void ugeth_phy_timer(unsigned long data
)
3954 struct net_device
*dev
= (struct net_device
*)data
;
3955 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3957 schedule_work(&ugeth
->tq
);
3959 mod_timer(&ugeth
->phy_info_timer
, jiffies
+ PHY_CHANGE_TIME
* HZ
);
3962 /* Keep trying aneg for some time
3963 * If, after GFAR_AN_TIMEOUT seconds, it has not
3964 * finished, we switch to forced.
3965 * Either way, once the process has completed, we either
3966 * request the interrupt, or switch the timer over to
3967 * using ugeth_phy_timer to check status */
3968 static void ugeth_phy_startup_timer(unsigned long data
)
3970 struct ugeth_mii_info
*mii_info
= (struct ugeth_mii_info
*)data
;
3971 struct ucc_geth_private
*ugeth
= netdev_priv(mii_info
->dev
);
3972 static int secondary
= UGETH_AN_TIMEOUT
;
3975 /* Configure the Auto-negotiation */
3976 result
= mii_info
->phyinfo
->config_aneg(mii_info
);
3978 /* If autonegotiation failed to start, and
3979 * we haven't timed out, reset the timer, and return */
3980 if (result
&& secondary
--) {
3981 mod_timer(&ugeth
->phy_info_timer
, jiffies
+ HZ
);
3983 } else if (result
) {
3984 /* Couldn't start autonegotiation.
3985 * Try switching to forced */
3986 mii_info
->autoneg
= 0;
3987 result
= mii_info
->phyinfo
->config_aneg(mii_info
);
3989 /* Forcing failed! Give up */
3991 ugeth_err("%s: Forcing failed!", mii_info
->dev
->name
);
3996 /* Kill the timer so it can be restarted */
3997 del_timer_sync(&ugeth
->phy_info_timer
);
3999 /* Grab the PHY interrupt, if necessary/possible */
4000 if (ugeth
->ug_info
->board_flags
& FSL_UGETH_BRD_HAS_PHY_INTR
) {
4001 if (request_irq(ugeth
->ug_info
->phy_interrupt
,
4003 SA_SHIRQ
, "phy_interrupt", mii_info
->dev
) < 0) {
4004 ugeth_err("%s: Can't get IRQ %d (PHY)",
4005 mii_info
->dev
->name
,
4006 ugeth
->ug_info
->phy_interrupt
);
4008 mii_configure_phy_interrupt(ugeth
->mii_info
,
4009 MII_INTERRUPT_ENABLED
);
4014 /* Start the timer again, this time in order to
4015 * handle a change in status */
4016 init_timer(&ugeth
->phy_info_timer
);
4017 ugeth
->phy_info_timer
.function
= &ugeth_phy_timer
;
4018 ugeth
->phy_info_timer
.data
= (unsigned long)mii_info
->dev
;
4019 mod_timer(&ugeth
->phy_info_timer
, jiffies
+ PHY_CHANGE_TIME
* HZ
);
4022 /* Called when something needs to use the ethernet device */
4023 /* Returns 0 for success. */
4024 static int ucc_geth_open(struct net_device
*dev
)
4026 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
4029 ugeth_vdbg("%s: IN", __FUNCTION__
);
4031 /* Test station address */
4032 if (dev
->dev_addr
[0] & ENET_GROUP_ADDR
) {
4033 ugeth_err("%s: Multicast address used for station address"
4034 " - is this what you wanted?", __FUNCTION__
);
4038 err
= ucc_geth_startup(ugeth
);
4040 ugeth_err("%s: Cannot configure net device, aborting.",
4045 err
= adjust_enet_interface(ugeth
);
4047 ugeth_err("%s: Cannot configure net device, aborting.",
4052 /* Set MACSTNADDR1, MACSTNADDR2 */
4053 /* For more details see the hardware spec. */
4054 init_mac_station_addr_regs(dev
->dev_addr
[0],
4060 &ugeth
->ug_regs
->macstnaddr1
,
4061 &ugeth
->ug_regs
->macstnaddr2
);
4063 err
= init_phy(dev
);
4065 ugeth_err("%s: Cannot initialzie PHY, aborting.", dev
->name
);
4068 #ifndef CONFIG_UGETH_NAPI
4070 request_irq(ugeth
->ug_info
->uf_info
.irq
, ucc_geth_irq_handler
, 0,
4073 ugeth_err("%s: Cannot get IRQ for net device, aborting.",
4075 ucc_geth_stop(ugeth
);
4078 #endif /* CONFIG_UGETH_NAPI */
4080 /* Set up the PHY change work queue */
4081 INIT_WORK(&ugeth
->tq
, ugeth_phy_change
, dev
);
4083 init_timer(&ugeth
->phy_info_timer
);
4084 ugeth
->phy_info_timer
.function
= &ugeth_phy_startup_timer
;
4085 ugeth
->phy_info_timer
.data
= (unsigned long)ugeth
->mii_info
;
4086 mod_timer(&ugeth
->phy_info_timer
, jiffies
+ HZ
);
4088 err
= ugeth_enable(ugeth
, COMM_DIR_RX_AND_TX
);
4090 ugeth_err("%s: Cannot enable net device, aborting.", dev
->name
);
4091 ucc_geth_stop(ugeth
);
4095 netif_start_queue(dev
);
4100 /* Stops the kernel queue, and halts the controller */
4101 static int ucc_geth_close(struct net_device
*dev
)
4103 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
4105 ugeth_vdbg("%s: IN", __FUNCTION__
);
4107 ucc_geth_stop(ugeth
);
4109 /* Shutdown the PHY */
4110 if (ugeth
->mii_info
->phyinfo
->close
)
4111 ugeth
->mii_info
->phyinfo
->close(ugeth
->mii_info
);
4113 kfree(ugeth
->mii_info
);
4115 netif_stop_queue(dev
);
4120 const struct ethtool_ops ucc_geth_ethtool_ops
= { };
4122 static int ucc_geth_probe(struct of_device
* ofdev
, const struct of_device_id
*match
)
4124 struct device
*device
= &ofdev
->dev
;
4125 struct device_node
*np
= ofdev
->node
;
4126 struct net_device
*dev
= NULL
;
4127 struct ucc_geth_private
*ugeth
= NULL
;
4128 struct ucc_geth_info
*ug_info
;
4129 struct resource res
;
4130 struct device_node
*phy
;
4131 int err
, ucc_num
, phy_interface
;
4132 static int mii_mng_configured
= 0;
4134 const unsigned int *prop
;
4136 ugeth_vdbg("%s: IN", __FUNCTION__
);
4138 prop
= get_property(np
, "device-id", NULL
);
4139 ucc_num
= *prop
- 1;
4140 if ((ucc_num
< 0) || (ucc_num
> 7))
4143 ug_info
= &ugeth_info
[ucc_num
];
4144 ug_info
->uf_info
.ucc_num
= ucc_num
;
4145 prop
= get_property(np
, "rx-clock", NULL
);
4146 ug_info
->uf_info
.rx_clock
= *prop
;
4147 prop
= get_property(np
, "tx-clock", NULL
);
4148 ug_info
->uf_info
.tx_clock
= *prop
;
4149 err
= of_address_to_resource(np
, 0, &res
);
4153 ug_info
->uf_info
.regs
= res
.start
;
4154 ug_info
->uf_info
.irq
= irq_of_parse_and_map(np
, 0);
4156 ph
= get_property(np
, "phy-handle", NULL
);
4157 phy
= of_find_node_by_phandle(*ph
);
4162 prop
= get_property(phy
, "reg", NULL
);
4163 ug_info
->phy_address
= *prop
;
4164 prop
= get_property(phy
, "interface", NULL
);
4165 ug_info
->enet_interface
= *prop
;
4166 ug_info
->phy_interrupt
= irq_of_parse_and_map(phy
, 0);
4167 ug_info
->board_flags
= (ug_info
->phy_interrupt
== NO_IRQ
)?
4168 0:FSL_UGETH_BRD_HAS_PHY_INTR
;
4170 printk(KERN_INFO
"ucc_geth: UCC%1d at 0x%8x (irq = %d) \n",
4171 ug_info
->uf_info
.ucc_num
+ 1, ug_info
->uf_info
.regs
,
4172 ug_info
->uf_info
.irq
);
4174 if (ug_info
== NULL
) {
4175 ugeth_err("%s: [%d] Missing additional data!", __FUNCTION__
,
4180 /* FIXME: Work around for early chip rev. */
4181 /* There's a bug in initial chip rev(s) in the RGMII ac */
4183 /* The following compensates by writing to the reserved */
4184 /* QE Port Output Hold Registers (CPOH1?). */
4185 prop
= get_property(phy
, "interface", NULL
);
4186 phy_interface
= *prop
;
4187 if ((phy_interface
== ENET_1000_RGMII
) ||
4188 (phy_interface
== ENET_100_RGMII
) ||
4189 (phy_interface
== ENET_10_RGMII
)) {
4190 struct device_node
*soc
;
4191 phys_addr_t immrbase
= -1;
4195 soc
= of_find_node_by_type(NULL
, "soc");
4198 const void *prop
= get_property(soc
, "reg", &size
);
4199 immrbase
= of_translate_address(soc
, prop
);
4203 tmp_reg
= (u32
*) ioremap(immrbase
+ 0x14A8, 0x4);
4204 tmp_val
= in_be32(tmp_reg
);
4206 out_be32(tmp_reg
, tmp_val
| 0x00003000);
4207 else if (ucc_num
== 2)
4208 out_be32(tmp_reg
, tmp_val
| 0x0c000000);
4212 if (!mii_mng_configured
) {
4213 ucc_set_qe_mux_mii_mng(ucc_num
);
4214 mii_mng_configured
= 1;
4217 /* Create an ethernet device instance */
4218 dev
= alloc_etherdev(sizeof(*ugeth
));
4223 ugeth
= netdev_priv(dev
);
4224 spin_lock_init(&ugeth
->lock
);
4226 dev_set_drvdata(device
, dev
);
4228 /* Set the dev->base_addr to the gfar reg region */
4229 dev
->base_addr
= (unsigned long)(ug_info
->uf_info
.regs
);
4231 SET_MODULE_OWNER(dev
);
4232 SET_NETDEV_DEV(dev
, device
);
4234 /* Fill in the dev structure */
4235 dev
->open
= ucc_geth_open
;
4236 dev
->hard_start_xmit
= ucc_geth_start_xmit
;
4237 dev
->tx_timeout
= ucc_geth_timeout
;
4238 dev
->watchdog_timeo
= TX_TIMEOUT
;
4239 #ifdef CONFIG_UGETH_NAPI
4240 dev
->poll
= ucc_geth_poll
;
4241 dev
->weight
= UCC_GETH_DEV_WEIGHT
;
4242 #endif /* CONFIG_UGETH_NAPI */
4243 dev
->stop
= ucc_geth_close
;
4244 dev
->get_stats
= ucc_geth_get_stats
;
4245 // dev->change_mtu = ucc_geth_change_mtu;
4247 dev
->set_multicast_list
= ucc_geth_set_multi
;
4248 dev
->ethtool_ops
= &ucc_geth_ethtool_ops
;
4250 err
= register_netdev(dev
);
4252 ugeth_err("%s: Cannot register net device, aborting.",
4258 ugeth
->ug_info
= ug_info
;
4260 memcpy(dev
->dev_addr
, get_property(np
, "mac-address", NULL
), 6);
4265 static int ucc_geth_remove(struct of_device
* ofdev
)
4267 struct device
*device
= &ofdev
->dev
;
4268 struct net_device
*dev
= dev_get_drvdata(device
);
4269 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
4271 dev_set_drvdata(device
, NULL
);
4272 ucc_geth_memclean(ugeth
);
4278 static struct of_device_id ucc_geth_match
[] = {
4281 .compatible
= "ucc_geth",
4286 MODULE_DEVICE_TABLE(of
, ucc_geth_match
);
4288 static struct of_platform_driver ucc_geth_driver
= {
4290 .match_table
= ucc_geth_match
,
4291 .probe
= ucc_geth_probe
,
4292 .remove
= ucc_geth_remove
,
4295 static int __init
ucc_geth_init(void)
4299 printk(KERN_INFO
"ucc_geth: " DRV_DESC
"\n");
4300 for (i
= 0; i
< 8; i
++)
4301 memcpy(&(ugeth_info
[i
]), &ugeth_primary_info
,
4302 sizeof(ugeth_primary_info
));
4304 return of_register_platform_driver(&ucc_geth_driver
);
4307 static void __exit
ucc_geth_exit(void)
4309 of_unregister_platform_driver(&ucc_geth_driver
);
4312 module_init(ucc_geth_init
);
4313 module_exit(ucc_geth_exit
);
4315 MODULE_AUTHOR("Freescale Semiconductor, Inc");
4316 MODULE_DESCRIPTION(DRV_DESC
);
4317 MODULE_LICENSE("GPL");