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WAN: rework HD64572 interrupts a bit.
[deliverable/linux.git] / drivers / net / wan / hd64572.c
1 /*
2 * Hitachi (now Renesas) SCA-II HD64572 driver for Linux
3 *
4 * Copyright (C) 1998-2008 Krzysztof Halasa <khc@pm.waw.pl>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License
8 * as published by the Free Software Foundation.
9 *
10 * Source of information: HD64572 SCA-II User's Manual
11 *
12 * We use the following SCA memory map:
13 *
14 * Packet buffer descriptor rings - starting from winbase or win0base:
15 * rx_ring_buffers * sizeof(pkt_desc) = logical channel #0 RX ring
16 * tx_ring_buffers * sizeof(pkt_desc) = logical channel #0 TX ring
17 * rx_ring_buffers * sizeof(pkt_desc) = logical channel #1 RX ring (if used)
18 * tx_ring_buffers * sizeof(pkt_desc) = logical channel #1 TX ring (if used)
19 *
20 * Packet data buffers - starting from winbase + buff_offset:
21 * rx_ring_buffers * HDLC_MAX_MRU = logical channel #0 RX buffers
22 * tx_ring_buffers * HDLC_MAX_MRU = logical channel #0 TX buffers
23 * rx_ring_buffers * HDLC_MAX_MRU = logical channel #0 RX buffers (if used)
24 * tx_ring_buffers * HDLC_MAX_MRU = logical channel #0 TX buffers (if used)
25 */
26
27 #include <linux/bitops.h>
28 #include <linux/errno.h>
29 #include <linux/fcntl.h>
30 #include <linux/hdlc.h>
31 #include <linux/in.h>
32 #include <linux/init.h>
33 #include <linux/interrupt.h>
34 #include <linux/ioport.h>
35 #include <linux/jiffies.h>
36 #include <linux/kernel.h>
37 #include <linux/module.h>
38 #include <linux/netdevice.h>
39 #include <linux/skbuff.h>
40 #include <linux/slab.h>
41 #include <linux/string.h>
42 #include <linux/types.h>
43 #include <asm/io.h>
44 #include <asm/system.h>
45 #include <asm/uaccess.h>
46 #include "hd64572.h"
47
48 #define NAPI_WEIGHT 16
49
50 #define get_msci(port) (phy_node(port) ? MSCI1_OFFSET : MSCI0_OFFSET)
51 #define get_dmac_rx(port) (phy_node(port) ? DMAC1RX_OFFSET : DMAC0RX_OFFSET)
52 #define get_dmac_tx(port) (phy_node(port) ? DMAC1TX_OFFSET : DMAC0TX_OFFSET)
53
54 #define SCA_INTR_MSCI(node) (node ? 0x10 : 0x01)
55 #define SCA_INTR_DMAC_RX(node) (node ? 0x20 : 0x02)
56 #define SCA_INTR_DMAC_TX(node) (node ? 0x40 : 0x04)
57
58 static int sca_poll(struct napi_struct *napi, int budget);
59
60 static inline struct net_device *port_to_dev(port_t *port)
61 {
62 return port->dev;
63 }
64
65 static inline int sca_intr_status(card_t *card)
66 {
67 u8 result = 0;
68 u32 isr0 = sca_inl(ISR0, card);
69
70 if (isr0 & 0x00000002) result |= SCA_INTR_DMAC_RX(0);
71 if (isr0 & 0x00000020) result |= SCA_INTR_DMAC_TX(0);
72 if (isr0 & 0x00000200) result |= SCA_INTR_DMAC_RX(1);
73 if (isr0 & 0x00002000) result |= SCA_INTR_DMAC_TX(1);
74 if (isr0 & 0x00080000) result |= SCA_INTR_MSCI(0);
75 if (isr0 & 0x08000000) result |= SCA_INTR_MSCI(1);
76
77 return result;
78 }
79
80 static inline port_t* dev_to_port(struct net_device *dev)
81 {
82 return dev_to_hdlc(dev)->priv;
83 }
84
85 static inline void enable_intr(port_t *port)
86 {
87 /* enable DMIB and MSCI RXINTA interrupts */
88 sca_outl(sca_inl(IER0, port->card) |
89 (phy_node(port) ? 0x08002200 : 0x00080022), IER0, port->card);
90 }
91
92 static inline void disable_intr(port_t *port)
93 {
94 sca_outl(sca_inl(IER0, port->card) &
95 (phy_node(port) ? 0x00FF00FF : 0xFF00FF00), IER0, port->card);
96 }
97
98 static inline u16 next_desc(port_t *port, u16 desc, int transmit)
99 {
100 return (desc + 1) % (transmit ? port_to_card(port)->tx_ring_buffers
101 : port_to_card(port)->rx_ring_buffers);
102 }
103
104
105 static inline u16 desc_abs_number(port_t *port, u16 desc, int transmit)
106 {
107 u16 rx_buffs = port_to_card(port)->rx_ring_buffers;
108 u16 tx_buffs = port_to_card(port)->tx_ring_buffers;
109
110 desc %= (transmit ? tx_buffs : rx_buffs); // called with "X + 1" etc.
111 return log_node(port) * (rx_buffs + tx_buffs) +
112 transmit * rx_buffs + desc;
113 }
114
115
116 static inline u16 desc_offset(port_t *port, u16 desc, int transmit)
117 {
118 /* Descriptor offset always fits in 16 bytes */
119 return desc_abs_number(port, desc, transmit) * sizeof(pkt_desc);
120 }
121
122
123 static inline pkt_desc __iomem *desc_address(port_t *port, u16 desc,
124 int transmit)
125 {
126 return (pkt_desc __iomem *)(winbase(port_to_card(port))
127 + desc_offset(port, desc, transmit));
128 }
129
130
131 static inline u32 buffer_offset(port_t *port, u16 desc, int transmit)
132 {
133 return port_to_card(port)->buff_offset +
134 desc_abs_number(port, desc, transmit) * (u32)HDLC_MAX_MRU;
135 }
136
137
138 static inline void sca_set_carrier(port_t *port)
139 {
140 if (!(sca_in(get_msci(port) + ST3, port_to_card(port)) & ST3_DCD)) {
141 #ifdef DEBUG_LINK
142 printk(KERN_DEBUG "%s: sca_set_carrier on\n",
143 port_to_dev(port)->name);
144 #endif
145 netif_carrier_on(port_to_dev(port));
146 } else {
147 #ifdef DEBUG_LINK
148 printk(KERN_DEBUG "%s: sca_set_carrier off\n",
149 port_to_dev(port)->name);
150 #endif
151 netif_carrier_off(port_to_dev(port));
152 }
153 }
154
155
156 static void sca_init_port(port_t *port)
157 {
158 card_t *card = port_to_card(port);
159 int transmit, i;
160
161 port->rxin = 0;
162 port->txin = 0;
163 port->txlast = 0;
164
165 for (transmit = 0; transmit < 2; transmit++) {
166 u16 dmac = transmit ? get_dmac_tx(port) : get_dmac_rx(port);
167 u16 buffs = transmit ? card->tx_ring_buffers
168 : card->rx_ring_buffers;
169
170 for (i = 0; i < buffs; i++) {
171 pkt_desc __iomem *desc = desc_address(port, i, transmit);
172 u16 chain_off = desc_offset(port, i + 1, transmit);
173 u32 buff_off = buffer_offset(port, i, transmit);
174
175 writel(chain_off, &desc->cp);
176 writel(buff_off, &desc->bp);
177 writew(0, &desc->len);
178 writeb(0, &desc->stat);
179 }
180
181 /* DMA disable - to halt state */
182 sca_out(0, transmit ? DSR_TX(phy_node(port)) :
183 DSR_RX(phy_node(port)), card);
184 /* software ABORT - to initial state */
185 sca_out(DCR_ABORT, transmit ? DCR_TX(phy_node(port)) :
186 DCR_RX(phy_node(port)), card);
187
188 /* current desc addr */
189 sca_outl(desc_offset(port, 0, transmit), dmac + CDAL, card);
190 if (!transmit)
191 sca_outl(desc_offset(port, buffs - 1, transmit),
192 dmac + EDAL, card);
193 else
194 sca_outl(desc_offset(port, 0, transmit), dmac + EDAL,
195 card);
196
197 /* clear frame end interrupt counter */
198 sca_out(DCR_CLEAR_EOF, transmit ? DCR_TX(phy_node(port)) :
199 DCR_RX(phy_node(port)), card);
200
201 if (!transmit) { /* Receive */
202 /* set buffer length */
203 sca_outw(HDLC_MAX_MRU, dmac + BFLL, card);
204 /* Chain mode, Multi-frame */
205 sca_out(0x14, DMR_RX(phy_node(port)), card);
206 sca_out(DIR_EOME, DIR_RX(phy_node(port)), card);
207 /* DMA enable */
208 sca_out(DSR_DE, DSR_RX(phy_node(port)), card);
209 } else { /* Transmit */
210 /* Chain mode, Multi-frame */
211 sca_out(0x14, DMR_TX(phy_node(port)), card);
212 /* enable underflow interrupts */
213 sca_out(DIR_EOME, DIR_TX(phy_node(port)), card);
214 }
215 }
216 sca_set_carrier(port);
217 netif_napi_add(port_to_dev(port), &port->napi, sca_poll, NAPI_WEIGHT);
218 }
219
220
221 /* MSCI interrupt service */
222 static inline void sca_msci_intr(port_t *port)
223 {
224 u16 msci = get_msci(port);
225 card_t* card = port_to_card(port);
226
227 if (sca_in(msci + ST1, card) & ST1_CDCD) {
228 /* Reset MSCI CDCD status bit */
229 sca_out(ST1_CDCD, msci + ST1, card);
230 sca_set_carrier(port);
231 }
232 }
233
234
235 static inline void sca_rx(card_t *card, port_t *port, pkt_desc __iomem *desc,
236 u16 rxin)
237 {
238 struct net_device *dev = port_to_dev(port);
239 struct sk_buff *skb;
240 u16 len;
241 u32 buff;
242
243 len = readw(&desc->len);
244 skb = dev_alloc_skb(len);
245 if (!skb) {
246 dev->stats.rx_dropped++;
247 return;
248 }
249
250 buff = buffer_offset(port, rxin, 0);
251 memcpy_fromio(skb->data, winbase(card) + buff, len);
252
253 skb_put(skb, len);
254 #ifdef DEBUG_PKT
255 printk(KERN_DEBUG "%s RX(%i):", dev->name, skb->len);
256 debug_frame(skb);
257 #endif
258 dev->stats.rx_packets++;
259 dev->stats.rx_bytes += skb->len;
260 skb->protocol = hdlc_type_trans(skb, dev);
261 netif_receive_skb(skb);
262 }
263
264
265 /* Receive DMA service */
266 static inline int sca_rx_done(port_t *port, int budget)
267 {
268 struct net_device *dev = port_to_dev(port);
269 u16 dmac = get_dmac_rx(port);
270 card_t *card = port_to_card(port);
271 u8 stat = sca_in(DSR_RX(phy_node(port)), card); /* read DMA Status */
272 int received = 0;
273
274 /* Reset DSR status bits */
275 sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
276 DSR_RX(phy_node(port)), card);
277
278 if (stat & DSR_BOF)
279 /* Dropped one or more frames */
280 dev->stats.rx_over_errors++;
281
282 while (received < budget) {
283 u32 desc_off = desc_offset(port, port->rxin, 0);
284 pkt_desc __iomem *desc;
285 u32 cda = sca_inl(dmac + CDAL, card);
286
287 if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc)))
288 break; /* No frame received */
289
290 desc = desc_address(port, port->rxin, 0);
291 stat = readb(&desc->stat);
292 if (!(stat & ST_RX_EOM))
293 port->rxpart = 1; /* partial frame received */
294 else if ((stat & ST_ERROR_MASK) || port->rxpart) {
295 dev->stats.rx_errors++;
296 if (stat & ST_RX_OVERRUN)
297 dev->stats.rx_fifo_errors++;
298 else if ((stat & (ST_RX_SHORT | ST_RX_ABORT |
299 ST_RX_RESBIT)) || port->rxpart)
300 dev->stats.rx_frame_errors++;
301 else if (stat & ST_RX_CRC)
302 dev->stats.rx_crc_errors++;
303 if (stat & ST_RX_EOM)
304 port->rxpart = 0; /* received last fragment */
305 } else {
306 sca_rx(card, port, desc, port->rxin);
307 received++;
308 }
309
310 /* Set new error descriptor address */
311 sca_outl(desc_off, dmac + EDAL, card);
312 port->rxin = next_desc(port, port->rxin, 0);
313 }
314
315 /* make sure RX DMA is enabled */
316 sca_out(DSR_DE, DSR_RX(phy_node(port)), card);
317 return received;
318 }
319
320
321 /* Transmit DMA service */
322 static inline void sca_tx_done(port_t *port)
323 {
324 struct net_device *dev = port_to_dev(port);
325 card_t* card = port_to_card(port);
326 u8 stat;
327
328 spin_lock(&port->lock);
329
330 stat = sca_in(DSR_TX(phy_node(port)), card); /* read DMA Status */
331
332 /* Reset DSR status bits */
333 sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
334 DSR_TX(phy_node(port)), card);
335
336 while (1) {
337 pkt_desc __iomem *desc = desc_address(port, port->txlast, 1);
338 u8 stat = readb(&desc->stat);
339
340 if (!(stat & ST_TX_OWNRSHP))
341 break; /* not yet transmitted */
342 if (stat & ST_TX_UNDRRUN) {
343 dev->stats.tx_errors++;
344 dev->stats.tx_fifo_errors++;
345 } else {
346 dev->stats.tx_packets++;
347 dev->stats.tx_bytes += readw(&desc->len);
348 }
349 writeb(0, &desc->stat); /* Free descriptor */
350 port->txlast = next_desc(port, port->txlast, 1);
351 }
352
353 netif_wake_queue(dev);
354 spin_unlock(&port->lock);
355 }
356
357
358 static int sca_poll(struct napi_struct *napi, int budget)
359 {
360 port_t *port = container_of(napi, port_t, napi);
361 u8 stat = sca_intr_status(port->card);
362 int received = 0;
363
364 if (stat & SCA_INTR_MSCI(port->phy_node))
365 sca_msci_intr(port);
366
367 if (stat & SCA_INTR_DMAC_TX(port->phy_node))
368 sca_tx_done(port);
369
370 if (stat & SCA_INTR_DMAC_RX(port->phy_node))
371 received = sca_rx_done(port, budget);
372
373 if (received < budget) {
374 netif_rx_complete(port->dev, napi);
375 enable_intr(port);
376 }
377
378 return received;
379 }
380
381 static irqreturn_t sca_intr(int irq, void* dev_id)
382 {
383 card_t *card = dev_id;
384 int i;
385 u8 stat = sca_intr_status(card);
386 int handled = 0;
387
388 for (i = 0; i < 2; i++) {
389 port_t *port = get_port(card, i);
390 if (port && (stat & (SCA_INTR_MSCI(i) | SCA_INTR_DMAC_RX(i) |
391 SCA_INTR_DMAC_TX(i)))) {
392 handled = 1;
393 disable_intr(port);
394 netif_rx_schedule(port->dev, &port->napi);
395 }
396 }
397
398 return IRQ_RETVAL(handled);
399 }
400
401
402 static void sca_set_port(port_t *port)
403 {
404 card_t* card = port_to_card(port);
405 u16 msci = get_msci(port);
406 u8 md2 = sca_in(msci + MD2, card);
407 unsigned int tmc, br = 10, brv = 1024;
408
409
410 if (port->settings.clock_rate > 0) {
411 /* Try lower br for better accuracy*/
412 do {
413 br--;
414 brv >>= 1; /* brv = 2^9 = 512 max in specs */
415
416 /* Baud Rate = CLOCK_BASE / TMC / 2^BR */
417 tmc = CLOCK_BASE / brv / port->settings.clock_rate;
418 }while (br > 1 && tmc <= 128);
419
420 if (tmc < 1) {
421 tmc = 1;
422 br = 0; /* For baud=CLOCK_BASE we use tmc=1 br=0 */
423 brv = 1;
424 } else if (tmc > 255)
425 tmc = 256; /* tmc=0 means 256 - low baud rates */
426
427 port->settings.clock_rate = CLOCK_BASE / brv / tmc;
428 } else {
429 br = 9; /* Minimum clock rate */
430 tmc = 256; /* 8bit = 0 */
431 port->settings.clock_rate = CLOCK_BASE / (256 * 512);
432 }
433
434 port->rxs = (port->rxs & ~CLK_BRG_MASK) | br;
435 port->txs = (port->txs & ~CLK_BRG_MASK) | br;
436 port->tmc = tmc;
437
438 /* baud divisor - time constant*/
439 sca_out(port->tmc, msci + TMCR, card);
440 sca_out(port->tmc, msci + TMCT, card);
441
442 /* Set BRG bits */
443 sca_out(port->rxs, msci + RXS, card);
444 sca_out(port->txs, msci + TXS, card);
445
446 if (port->settings.loopback)
447 md2 |= MD2_LOOPBACK;
448 else
449 md2 &= ~MD2_LOOPBACK;
450
451 sca_out(md2, msci + MD2, card);
452
453 }
454
455
456 static void sca_open(struct net_device *dev)
457 {
458 port_t *port = dev_to_port(dev);
459 card_t* card = port_to_card(port);
460 u16 msci = get_msci(port);
461 u8 md0, md2;
462
463 switch(port->encoding) {
464 case ENCODING_NRZ: md2 = MD2_NRZ; break;
465 case ENCODING_NRZI: md2 = MD2_NRZI; break;
466 case ENCODING_FM_MARK: md2 = MD2_FM_MARK; break;
467 case ENCODING_FM_SPACE: md2 = MD2_FM_SPACE; break;
468 default: md2 = MD2_MANCHESTER;
469 }
470
471 if (port->settings.loopback)
472 md2 |= MD2_LOOPBACK;
473
474 switch(port->parity) {
475 case PARITY_CRC16_PR0: md0 = MD0_HDLC | MD0_CRC_16_0; break;
476 case PARITY_CRC16_PR1: md0 = MD0_HDLC | MD0_CRC_16; break;
477 case PARITY_CRC32_PR1_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU32; break;
478 case PARITY_CRC16_PR1_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU; break;
479 default: md0 = MD0_HDLC | MD0_CRC_NONE;
480 }
481
482 sca_out(CMD_RESET, msci + CMD, card);
483 sca_out(md0, msci + MD0, card);
484 sca_out(0x00, msci + MD1, card); /* no address field check */
485 sca_out(md2, msci + MD2, card);
486 sca_out(0x7E, msci + IDL, card); /* flag character 0x7E */
487 /* Skip the rest of underrun frame */
488 sca_out(CTL_IDLE | CTL_URCT | CTL_URSKP, msci + CTL, card);
489 sca_out(0x0F, msci + RNR, card); /* +1=RX DMA activation condition */
490 sca_out(0x3C, msci + TFS, card); /* +1 = TX start */
491 sca_out(0x38, msci + TCR, card); /* =Critical TX DMA activ condition */
492 sca_out(0x38, msci + TNR0, card); /* =TX DMA activation condition */
493 sca_out(0x3F, msci + TNR1, card); /* +1=TX DMA deactivation condition*/
494
495 /* We're using the following interrupts:
496 - RXINTA (DCD changes only)
497 - DMIB (EOM - single frame transfer complete)
498 */
499 sca_outl(IE0_RXINTA | IE0_CDCD, msci + IE0, card);
500
501 sca_out(port->tmc, msci + TMCR, card);
502 sca_out(port->tmc, msci + TMCT, card);
503 sca_out(port->rxs, msci + RXS, card);
504 sca_out(port->txs, msci + TXS, card);
505 sca_out(CMD_TX_ENABLE, msci + CMD, card);
506 sca_out(CMD_RX_ENABLE, msci + CMD, card);
507
508 sca_set_carrier(port);
509 enable_intr(port);
510 napi_enable(&port->napi);
511 netif_start_queue(dev);
512 }
513
514
515 static void sca_close(struct net_device *dev)
516 {
517 port_t *port = dev_to_port(dev);
518
519 /* reset channel */
520 sca_out(CMD_RESET, get_msci(port) + CMD, port_to_card(port));
521 disable_intr(port);
522 napi_disable(&port->napi);
523 netif_stop_queue(dev);
524 }
525
526
527 static int sca_attach(struct net_device *dev, unsigned short encoding,
528 unsigned short parity)
529 {
530 if (encoding != ENCODING_NRZ &&
531 encoding != ENCODING_NRZI &&
532 encoding != ENCODING_FM_MARK &&
533 encoding != ENCODING_FM_SPACE &&
534 encoding != ENCODING_MANCHESTER)
535 return -EINVAL;
536
537 if (parity != PARITY_NONE &&
538 parity != PARITY_CRC16_PR0 &&
539 parity != PARITY_CRC16_PR1 &&
540 parity != PARITY_CRC32_PR1_CCITT &&
541 parity != PARITY_CRC16_PR1_CCITT)
542 return -EINVAL;
543
544 dev_to_port(dev)->encoding = encoding;
545 dev_to_port(dev)->parity = parity;
546 return 0;
547 }
548
549
550 #ifdef DEBUG_RINGS
551 static void sca_dump_rings(struct net_device *dev)
552 {
553 port_t *port = dev_to_port(dev);
554 card_t *card = port_to_card(port);
555 u16 cnt;
556
557 printk(KERN_DEBUG "RX ring: CDA=%u EDA=%u DSR=%02X in=%u %sactive",
558 sca_inl(get_dmac_rx(port) + CDAL, card),
559 sca_inl(get_dmac_rx(port) + EDAL, card),
560 sca_in(DSR_RX(phy_node(port)), card), port->rxin,
561 sca_in(DSR_RX(phy_node(port)), card) & DSR_DE ? "" : "in");
562 for (cnt = 0; cnt < port_to_card(port)->rx_ring_buffers; cnt++)
563 printk(" %02X", readb(&(desc_address(port, cnt, 0)->stat)));
564
565 printk("\n" KERN_DEBUG "TX ring: CDA=%u EDA=%u DSR=%02X in=%u "
566 "last=%u %sactive",
567 sca_inl(get_dmac_tx(port) + CDAL, card),
568 sca_inl(get_dmac_tx(port) + EDAL, card),
569 sca_in(DSR_TX(phy_node(port)), card), port->txin, port->txlast,
570 sca_in(DSR_TX(phy_node(port)), card) & DSR_DE ? "" : "in");
571
572 for (cnt = 0; cnt < port_to_card(port)->tx_ring_buffers; cnt++)
573 printk(" %02X", readb(&(desc_address(port, cnt, 1)->stat)));
574 printk("\n");
575
576 printk(KERN_DEBUG "MSCI: MD: %02x %02x %02x,"
577 " ST: %02x %02x %02x %02x %02x, FST: %02x CST: %02x %02x\n",
578 sca_in(get_msci(port) + MD0, card),
579 sca_in(get_msci(port) + MD1, card),
580 sca_in(get_msci(port) + MD2, card),
581 sca_in(get_msci(port) + ST0, card),
582 sca_in(get_msci(port) + ST1, card),
583 sca_in(get_msci(port) + ST2, card),
584 sca_in(get_msci(port) + ST3, card),
585 sca_in(get_msci(port) + ST4, card),
586 sca_in(get_msci(port) + FST, card),
587 sca_in(get_msci(port) + CST0, card),
588 sca_in(get_msci(port) + CST1, card));
589
590 printk(KERN_DEBUG "ILAR: %02x ISR: %08x %08x\n", sca_in(ILAR, card),
591 sca_inl(ISR0, card), sca_inl(ISR1, card));
592 }
593 #endif /* DEBUG_RINGS */
594
595
596 static int sca_xmit(struct sk_buff *skb, struct net_device *dev)
597 {
598 port_t *port = dev_to_port(dev);
599 card_t *card = port_to_card(port);
600 pkt_desc __iomem *desc;
601 u32 buff, len;
602
603 spin_lock_irq(&port->lock);
604
605 desc = desc_address(port, port->txin + 1, 1);
606 BUG_ON(readb(&desc->stat)); /* previous xmit should stop queue */
607
608 #ifdef DEBUG_PKT
609 printk(KERN_DEBUG "%s TX(%i):", dev->name, skb->len);
610 debug_frame(skb);
611 #endif
612
613 desc = desc_address(port, port->txin, 1);
614 buff = buffer_offset(port, port->txin, 1);
615 len = skb->len;
616 memcpy_toio(winbase(card) + buff, skb->data, len);
617
618 writew(len, &desc->len);
619 writeb(ST_TX_EOM, &desc->stat);
620 dev->trans_start = jiffies;
621
622 port->txin = next_desc(port, port->txin, 1);
623 sca_outl(desc_offset(port, port->txin, 1),
624 get_dmac_tx(port) + EDAL, card);
625
626 sca_out(DSR_DE, DSR_TX(phy_node(port)), card); /* Enable TX DMA */
627
628 desc = desc_address(port, port->txin + 1, 1);
629 if (readb(&desc->stat)) /* allow 1 packet gap */
630 netif_stop_queue(dev);
631
632 spin_unlock_irq(&port->lock);
633
634 dev_kfree_skb(skb);
635 return 0;
636 }
637
638
639 static u32 __devinit sca_detect_ram(card_t *card, u8 __iomem *rambase,
640 u32 ramsize)
641 {
642 /* Round RAM size to 32 bits, fill from end to start */
643 u32 i = ramsize &= ~3;
644
645 do {
646 i -= 4;
647 writel(i ^ 0x12345678, rambase + i);
648 } while (i > 0);
649
650 for (i = 0; i < ramsize ; i += 4) {
651 if (readl(rambase + i) != (i ^ 0x12345678))
652 break;
653 }
654
655 return i;
656 }
657
658
659 static void __devinit sca_init(card_t *card, int wait_states)
660 {
661 sca_out(wait_states, WCRL, card); /* Wait Control */
662 sca_out(wait_states, WCRM, card);
663 sca_out(wait_states, WCRH, card);
664
665 sca_out(0, DMER, card); /* DMA Master disable */
666 sca_out(0x03, PCR, card); /* DMA priority */
667 sca_out(0, DSR_RX(0), card); /* DMA disable - to halt state */
668 sca_out(0, DSR_TX(0), card);
669 sca_out(0, DSR_RX(1), card);
670 sca_out(0, DSR_TX(1), card);
671 sca_out(DMER_DME, DMER, card); /* DMA Master enable */
672 }
Linux kernel - Deliverables
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