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WAN: Correct comments in hd6457[02].c
[deliverable/linux.git] / drivers / net / wan / hd64572.c
1 /*
2 * Hitachi (now Renesas) SCA-II HD64572 driver for Linux
3 *
4 * Copyright (C) 1998-2008 Krzysztof Halasa <khc@pm.waw.pl>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License
8 * as published by the Free Software Foundation.
9 *
10 * Source of information: HD64572 SCA-II User's Manual
11 *
12 * We use the following SCA memory map:
13 *
14 * Packet buffer descriptor rings - starting from card->rambase:
15 * rx_ring_buffers * sizeof(pkt_desc) = logical channel #0 RX ring
16 * tx_ring_buffers * sizeof(pkt_desc) = logical channel #0 TX ring
17 * rx_ring_buffers * sizeof(pkt_desc) = logical channel #1 RX ring (if used)
18 * tx_ring_buffers * sizeof(pkt_desc) = logical channel #1 TX ring (if used)
19 *
20 * Packet data buffers - starting from card->rambase + buff_offset:
21 * rx_ring_buffers * HDLC_MAX_MRU = logical channel #0 RX buffers
22 * tx_ring_buffers * HDLC_MAX_MRU = logical channel #0 TX buffers
23 * rx_ring_buffers * HDLC_MAX_MRU = logical channel #0 RX buffers (if used)
24 * tx_ring_buffers * HDLC_MAX_MRU = logical channel #0 TX buffers (if used)
25 */
26
27 #include <linux/bitops.h>
28 #include <linux/errno.h>
29 #include <linux/fcntl.h>
30 #include <linux/hdlc.h>
31 #include <linux/in.h>
32 #include <linux/init.h>
33 #include <linux/interrupt.h>
34 #include <linux/ioport.h>
35 #include <linux/jiffies.h>
36 #include <linux/kernel.h>
37 #include <linux/module.h>
38 #include <linux/netdevice.h>
39 #include <linux/skbuff.h>
40 #include <linux/slab.h>
41 #include <linux/string.h>
42 #include <linux/types.h>
43 #include <asm/io.h>
44 #include <asm/system.h>
45 #include <asm/uaccess.h>
46 #include "hd64572.h"
47
48 #define NAPI_WEIGHT 16
49
50 #define get_msci(port) (port->chan ? MSCI1_OFFSET : MSCI0_OFFSET)
51 #define get_dmac_rx(port) (port->chan ? DMAC1RX_OFFSET : DMAC0RX_OFFSET)
52 #define get_dmac_tx(port) (port->chan ? DMAC1TX_OFFSET : DMAC0TX_OFFSET)
53
54 #define sca_in(reg, card) readb(card->scabase + (reg))
55 #define sca_out(value, reg, card) writeb(value, card->scabase + (reg))
56 #define sca_inw(reg, card) readw(card->scabase + (reg))
57 #define sca_outw(value, reg, card) writew(value, card->scabase + (reg))
58 #define sca_inl(reg, card) readl(card->scabase + (reg))
59 #define sca_outl(value, reg, card) writel(value, card->scabase + (reg))
60
61 static int sca_poll(struct napi_struct *napi, int budget);
62
63 static inline port_t* dev_to_port(struct net_device *dev)
64 {
65 return dev_to_hdlc(dev)->priv;
66 }
67
68 static inline void enable_intr(port_t *port)
69 {
70 /* enable DMIB and MSCI RXINTA interrupts */
71 sca_outl(sca_inl(IER0, port->card) |
72 (port->chan ? 0x08002200 : 0x00080022), IER0, port->card);
73 }
74
75 static inline void disable_intr(port_t *port)
76 {
77 sca_outl(sca_inl(IER0, port->card) &
78 (port->chan ? 0x00FF00FF : 0xFF00FF00), IER0, port->card);
79 }
80
81 static inline u16 desc_abs_number(port_t *port, u16 desc, int transmit)
82 {
83 u16 rx_buffs = port->card->rx_ring_buffers;
84 u16 tx_buffs = port->card->tx_ring_buffers;
85
86 desc %= (transmit ? tx_buffs : rx_buffs); // called with "X + 1" etc.
87 return port->chan * (rx_buffs + tx_buffs) + transmit * rx_buffs + desc;
88 }
89
90
91 static inline u16 desc_offset(port_t *port, u16 desc, int transmit)
92 {
93 /* Descriptor offset always fits in 16 bits */
94 return desc_abs_number(port, desc, transmit) * sizeof(pkt_desc);
95 }
96
97
98 static inline pkt_desc __iomem *desc_address(port_t *port, u16 desc,
99 int transmit)
100 {
101 return (pkt_desc __iomem *)(port->card->rambase +
102 desc_offset(port, desc, transmit));
103 }
104
105
106 static inline u32 buffer_offset(port_t *port, u16 desc, int transmit)
107 {
108 return port->card->buff_offset +
109 desc_abs_number(port, desc, transmit) * (u32)HDLC_MAX_MRU;
110 }
111
112
113 static inline void sca_set_carrier(port_t *port)
114 {
115 if (!(sca_in(get_msci(port) + ST3, port->card) & ST3_DCD)) {
116 #ifdef DEBUG_LINK
117 printk(KERN_DEBUG "%s: sca_set_carrier on\n",
118 port->netdev.name);
119 #endif
120 netif_carrier_on(port->netdev);
121 } else {
122 #ifdef DEBUG_LINK
123 printk(KERN_DEBUG "%s: sca_set_carrier off\n",
124 port->netdev.name);
125 #endif
126 netif_carrier_off(port->netdev);
127 }
128 }
129
130
131 static void sca_init_port(port_t *port)
132 {
133 card_t *card = port->card;
134 int transmit, i;
135
136 port->rxin = 0;
137 port->txin = 0;
138 port->txlast = 0;
139
140 for (transmit = 0; transmit < 2; transmit++) {
141 u16 dmac = transmit ? get_dmac_tx(port) : get_dmac_rx(port);
142 u16 buffs = transmit ? card->tx_ring_buffers
143 : card->rx_ring_buffers;
144
145 for (i = 0; i < buffs; i++) {
146 pkt_desc __iomem *desc = desc_address(port, i, transmit);
147 u16 chain_off = desc_offset(port, i + 1, transmit);
148 u32 buff_off = buffer_offset(port, i, transmit);
149
150 writel(chain_off, &desc->cp);
151 writel(buff_off, &desc->bp);
152 writew(0, &desc->len);
153 writeb(0, &desc->stat);
154 }
155
156 /* DMA disable - to halt state */
157 sca_out(0, transmit ? DSR_TX(port->chan) :
158 DSR_RX(port->chan), card);
159 /* software ABORT - to initial state */
160 sca_out(DCR_ABORT, transmit ? DCR_TX(port->chan) :
161 DCR_RX(port->chan), card);
162
163 /* current desc addr */
164 sca_outl(desc_offset(port, 0, transmit), dmac + CDAL, card);
165 if (!transmit)
166 sca_outl(desc_offset(port, buffs - 1, transmit),
167 dmac + EDAL, card);
168 else
169 sca_outl(desc_offset(port, 0, transmit), dmac + EDAL,
170 card);
171
172 /* clear frame end interrupt counter */
173 sca_out(DCR_CLEAR_EOF, transmit ? DCR_TX(port->chan) :
174 DCR_RX(port->chan), card);
175
176 if (!transmit) { /* Receive */
177 /* set buffer length */
178 sca_outw(HDLC_MAX_MRU, dmac + BFLL, card);
179 /* Chain mode, Multi-frame */
180 sca_out(0x14, DMR_RX(port->chan), card);
181 sca_out(DIR_EOME, DIR_RX(port->chan), card);
182 /* DMA enable */
183 sca_out(DSR_DE, DSR_RX(port->chan), card);
184 } else { /* Transmit */
185 /* Chain mode, Multi-frame */
186 sca_out(0x14, DMR_TX(port->chan), card);
187 /* enable underflow interrupts */
188 sca_out(DIR_EOME, DIR_TX(port->chan), card);
189 }
190 }
191 sca_set_carrier(port);
192 netif_napi_add(port->netdev, &port->napi, sca_poll, NAPI_WEIGHT);
193 }
194
195
196 /* MSCI interrupt service */
197 static inline void sca_msci_intr(port_t *port)
198 {
199 u16 msci = get_msci(port);
200 card_t* card = port->card;
201
202 if (sca_in(msci + ST1, card) & ST1_CDCD) {
203 /* Reset MSCI CDCD status bit */
204 sca_out(ST1_CDCD, msci + ST1, card);
205 sca_set_carrier(port);
206 }
207 }
208
209
210 static inline void sca_rx(card_t *card, port_t *port, pkt_desc __iomem *desc,
211 u16 rxin)
212 {
213 struct net_device *dev = port->netdev;
214 struct sk_buff *skb;
215 u16 len;
216 u32 buff;
217
218 len = readw(&desc->len);
219 skb = dev_alloc_skb(len);
220 if (!skb) {
221 dev->stats.rx_dropped++;
222 return;
223 }
224
225 buff = buffer_offset(port, rxin, 0);
226 memcpy_fromio(skb->data, card->rambase + buff, len);
227
228 skb_put(skb, len);
229 #ifdef DEBUG_PKT
230 printk(KERN_DEBUG "%s RX(%i):", dev->name, skb->len);
231 debug_frame(skb);
232 #endif
233 dev->stats.rx_packets++;
234 dev->stats.rx_bytes += skb->len;
235 skb->protocol = hdlc_type_trans(skb, dev);
236 netif_receive_skb(skb);
237 }
238
239
240 /* Receive DMA service */
241 static inline int sca_rx_done(port_t *port, int budget)
242 {
243 struct net_device *dev = port->netdev;
244 u16 dmac = get_dmac_rx(port);
245 card_t *card = port->card;
246 u8 stat = sca_in(DSR_RX(port->chan), card); /* read DMA Status */
247 int received = 0;
248
249 /* Reset DSR status bits */
250 sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
251 DSR_RX(port->chan), card);
252
253 if (stat & DSR_BOF)
254 /* Dropped one or more frames */
255 dev->stats.rx_over_errors++;
256
257 while (received < budget) {
258 u32 desc_off = desc_offset(port, port->rxin, 0);
259 pkt_desc __iomem *desc;
260 u32 cda = sca_inl(dmac + CDAL, card);
261
262 if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc)))
263 break; /* No frame received */
264
265 desc = desc_address(port, port->rxin, 0);
266 stat = readb(&desc->stat);
267 if (!(stat & ST_RX_EOM))
268 port->rxpart = 1; /* partial frame received */
269 else if ((stat & ST_ERROR_MASK) || port->rxpart) {
270 dev->stats.rx_errors++;
271 if (stat & ST_RX_OVERRUN)
272 dev->stats.rx_fifo_errors++;
273 else if ((stat & (ST_RX_SHORT | ST_RX_ABORT |
274 ST_RX_RESBIT)) || port->rxpart)
275 dev->stats.rx_frame_errors++;
276 else if (stat & ST_RX_CRC)
277 dev->stats.rx_crc_errors++;
278 if (stat & ST_RX_EOM)
279 port->rxpart = 0; /* received last fragment */
280 } else {
281 sca_rx(card, port, desc, port->rxin);
282 received++;
283 }
284
285 /* Set new error descriptor address */
286 sca_outl(desc_off, dmac + EDAL, card);
287 port->rxin = (port->rxin + 1) % card->rx_ring_buffers;
288 }
289
290 /* make sure RX DMA is enabled */
291 sca_out(DSR_DE, DSR_RX(port->chan), card);
292 return received;
293 }
294
295
296 /* Transmit DMA service */
297 static inline void sca_tx_done(port_t *port)
298 {
299 struct net_device *dev = port->netdev;
300 card_t* card = port->card;
301 u8 stat;
302
303 spin_lock(&port->lock);
304
305 stat = sca_in(DSR_TX(port->chan), card); /* read DMA Status */
306
307 /* Reset DSR status bits */
308 sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
309 DSR_TX(port->chan), card);
310
311 while (1) {
312 pkt_desc __iomem *desc = desc_address(port, port->txlast, 1);
313 u8 stat = readb(&desc->stat);
314
315 if (!(stat & ST_TX_OWNRSHP))
316 break; /* not yet transmitted */
317 if (stat & ST_TX_UNDRRUN) {
318 dev->stats.tx_errors++;
319 dev->stats.tx_fifo_errors++;
320 } else {
321 dev->stats.tx_packets++;
322 dev->stats.tx_bytes += readw(&desc->len);
323 }
324 writeb(0, &desc->stat); /* Free descriptor */
325 port->txlast = (port->txlast + 1) % card->tx_ring_buffers;
326 }
327
328 netif_wake_queue(dev);
329 spin_unlock(&port->lock);
330 }
331
332
333 static int sca_poll(struct napi_struct *napi, int budget)
334 {
335 port_t *port = container_of(napi, port_t, napi);
336 u32 isr0 = sca_inl(ISR0, port->card);
337 int received = 0;
338
339 if (isr0 & (port->chan ? 0x08000000 : 0x00080000))
340 sca_msci_intr(port);
341
342 if (isr0 & (port->chan ? 0x00002000 : 0x00000020))
343 sca_tx_done(port);
344
345 if (isr0 & (port->chan ? 0x00000200 : 0x00000002))
346 received = sca_rx_done(port, budget);
347
348 if (received < budget) {
349 netif_rx_complete(port->netdev, napi);
350 enable_intr(port);
351 }
352
353 return received;
354 }
355
356 static irqreturn_t sca_intr(int irq, void *dev_id)
357 {
358 card_t *card = dev_id;
359 u32 isr0 = sca_inl(ISR0, card);
360 int i, handled = 0;
361
362 for (i = 0; i < 2; i++) {
363 port_t *port = get_port(card, i);
364 if (port && (isr0 & (i ? 0x08002200 : 0x00080022))) {
365 handled = 1;
366 disable_intr(port);
367 netif_rx_schedule(port->netdev, &port->napi);
368 }
369 }
370
371 return IRQ_RETVAL(handled);
372 }
373
374
375 static void sca_set_port(port_t *port)
376 {
377 card_t* card = port->card;
378 u16 msci = get_msci(port);
379 u8 md2 = sca_in(msci + MD2, card);
380 unsigned int tmc, br = 10, brv = 1024;
381
382
383 if (port->settings.clock_rate > 0) {
384 /* Try lower br for better accuracy*/
385 do {
386 br--;
387 brv >>= 1; /* brv = 2^9 = 512 max in specs */
388
389 /* Baud Rate = CLOCK_BASE / TMC / 2^BR */
390 tmc = CLOCK_BASE / brv / port->settings.clock_rate;
391 }while (br > 1 && tmc <= 128);
392
393 if (tmc < 1) {
394 tmc = 1;
395 br = 0; /* For baud=CLOCK_BASE we use tmc=1 br=0 */
396 brv = 1;
397 } else if (tmc > 255)
398 tmc = 256; /* tmc=0 means 256 - low baud rates */
399
400 port->settings.clock_rate = CLOCK_BASE / brv / tmc;
401 } else {
402 br = 9; /* Minimum clock rate */
403 tmc = 256; /* 8bit = 0 */
404 port->settings.clock_rate = CLOCK_BASE / (256 * 512);
405 }
406
407 port->rxs = (port->rxs & ~CLK_BRG_MASK) | br;
408 port->txs = (port->txs & ~CLK_BRG_MASK) | br;
409 port->tmc = tmc;
410
411 /* baud divisor - time constant*/
412 sca_out(port->tmc, msci + TMCR, card);
413 sca_out(port->tmc, msci + TMCT, card);
414
415 /* Set BRG bits */
416 sca_out(port->rxs, msci + RXS, card);
417 sca_out(port->txs, msci + TXS, card);
418
419 if (port->settings.loopback)
420 md2 |= MD2_LOOPBACK;
421 else
422 md2 &= ~MD2_LOOPBACK;
423
424 sca_out(md2, msci + MD2, card);
425
426 }
427
428
429 static void sca_open(struct net_device *dev)
430 {
431 port_t *port = dev_to_port(dev);
432 card_t* card = port->card;
433 u16 msci = get_msci(port);
434 u8 md0, md2;
435
436 switch(port->encoding) {
437 case ENCODING_NRZ: md2 = MD2_NRZ; break;
438 case ENCODING_NRZI: md2 = MD2_NRZI; break;
439 case ENCODING_FM_MARK: md2 = MD2_FM_MARK; break;
440 case ENCODING_FM_SPACE: md2 = MD2_FM_SPACE; break;
441 default: md2 = MD2_MANCHESTER;
442 }
443
444 if (port->settings.loopback)
445 md2 |= MD2_LOOPBACK;
446
447 switch(port->parity) {
448 case PARITY_CRC16_PR0: md0 = MD0_HDLC | MD0_CRC_16_0; break;
449 case PARITY_CRC16_PR1: md0 = MD0_HDLC | MD0_CRC_16; break;
450 case PARITY_CRC32_PR1_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU32; break;
451 case PARITY_CRC16_PR1_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU; break;
452 default: md0 = MD0_HDLC | MD0_CRC_NONE;
453 }
454
455 sca_out(CMD_RESET, msci + CMD, card);
456 sca_out(md0, msci + MD0, card);
457 sca_out(0x00, msci + MD1, card); /* no address field check */
458 sca_out(md2, msci + MD2, card);
459 sca_out(0x7E, msci + IDL, card); /* flag character 0x7E */
460 /* Skip the rest of underrun frame */
461 sca_out(CTL_IDLE | CTL_URCT | CTL_URSKP, msci + CTL, card);
462 sca_out(0x0F, msci + RNR, card); /* +1=RX DMA activation condition */
463 sca_out(0x3C, msci + TFS, card); /* +1 = TX start */
464 sca_out(0x38, msci + TCR, card); /* =Critical TX DMA activ condition */
465 sca_out(0x38, msci + TNR0, card); /* =TX DMA activation condition */
466 sca_out(0x3F, msci + TNR1, card); /* +1=TX DMA deactivation condition*/
467
468 /* We're using the following interrupts:
469 - RXINTA (DCD changes only)
470 - DMIB (EOM - single frame transfer complete)
471 */
472 sca_outl(IE0_RXINTA | IE0_CDCD, msci + IE0, card);
473
474 sca_out(port->tmc, msci + TMCR, card);
475 sca_out(port->tmc, msci + TMCT, card);
476 sca_out(port->rxs, msci + RXS, card);
477 sca_out(port->txs, msci + TXS, card);
478 sca_out(CMD_TX_ENABLE, msci + CMD, card);
479 sca_out(CMD_RX_ENABLE, msci + CMD, card);
480
481 sca_set_carrier(port);
482 enable_intr(port);
483 napi_enable(&port->napi);
484 netif_start_queue(dev);
485 }
486
487
488 static void sca_close(struct net_device *dev)
489 {
490 port_t *port = dev_to_port(dev);
491
492 /* reset channel */
493 sca_out(CMD_RESET, get_msci(port) + CMD, port->card);
494 disable_intr(port);
495 napi_disable(&port->napi);
496 netif_stop_queue(dev);
497 }
498
499
500 static int sca_attach(struct net_device *dev, unsigned short encoding,
501 unsigned short parity)
502 {
503 if (encoding != ENCODING_NRZ &&
504 encoding != ENCODING_NRZI &&
505 encoding != ENCODING_FM_MARK &&
506 encoding != ENCODING_FM_SPACE &&
507 encoding != ENCODING_MANCHESTER)
508 return -EINVAL;
509
510 if (parity != PARITY_NONE &&
511 parity != PARITY_CRC16_PR0 &&
512 parity != PARITY_CRC16_PR1 &&
513 parity != PARITY_CRC32_PR1_CCITT &&
514 parity != PARITY_CRC16_PR1_CCITT)
515 return -EINVAL;
516
517 dev_to_port(dev)->encoding = encoding;
518 dev_to_port(dev)->parity = parity;
519 return 0;
520 }
521
522
523 #ifdef DEBUG_RINGS
524 static void sca_dump_rings(struct net_device *dev)
525 {
526 port_t *port = dev_to_port(dev);
527 card_t *card = port->card;
528 u16 cnt;
529
530 printk(KERN_DEBUG "RX ring: CDA=%u EDA=%u DSR=%02X in=%u %sactive",
531 sca_inl(get_dmac_rx(port) + CDAL, card),
532 sca_inl(get_dmac_rx(port) + EDAL, card),
533 sca_in(DSR_RX(port->chan), card), port->rxin,
534 sca_in(DSR_RX(port->chan), card) & DSR_DE ? "" : "in");
535 for (cnt = 0; cnt < port->card->rx_ring_buffers; cnt++)
536 printk(" %02X", readb(&(desc_address(port, cnt, 0)->stat)));
537
538 printk("\n" KERN_DEBUG "TX ring: CDA=%u EDA=%u DSR=%02X in=%u "
539 "last=%u %sactive",
540 sca_inl(get_dmac_tx(port) + CDAL, card),
541 sca_inl(get_dmac_tx(port) + EDAL, card),
542 sca_in(DSR_TX(port->chan), card), port->txin, port->txlast,
543 sca_in(DSR_TX(port->chan), card) & DSR_DE ? "" : "in");
544
545 for (cnt = 0; cnt < port->card->tx_ring_buffers; cnt++)
546 printk(" %02X", readb(&(desc_address(port, cnt, 1)->stat)));
547 printk("\n");
548
549 printk(KERN_DEBUG "MSCI: MD: %02x %02x %02x,"
550 " ST: %02x %02x %02x %02x %02x, FST: %02x CST: %02x %02x\n",
551 sca_in(get_msci(port) + MD0, card),
552 sca_in(get_msci(port) + MD1, card),
553 sca_in(get_msci(port) + MD2, card),
554 sca_in(get_msci(port) + ST0, card),
555 sca_in(get_msci(port) + ST1, card),
556 sca_in(get_msci(port) + ST2, card),
557 sca_in(get_msci(port) + ST3, card),
558 sca_in(get_msci(port) + ST4, card),
559 sca_in(get_msci(port) + FST, card),
560 sca_in(get_msci(port) + CST0, card),
561 sca_in(get_msci(port) + CST1, card));
562
563 printk(KERN_DEBUG "ILAR: %02x ISR: %08x %08x\n", sca_in(ILAR, card),
564 sca_inl(ISR0, card), sca_inl(ISR1, card));
565 }
566 #endif /* DEBUG_RINGS */
567
568
569 static int sca_xmit(struct sk_buff *skb, struct net_device *dev)
570 {
571 port_t *port = dev_to_port(dev);
572 card_t *card = port->card;
573 pkt_desc __iomem *desc;
574 u32 buff, len;
575
576 spin_lock_irq(&port->lock);
577
578 desc = desc_address(port, port->txin + 1, 1);
579 BUG_ON(readb(&desc->stat)); /* previous xmit should stop queue */
580
581 #ifdef DEBUG_PKT
582 printk(KERN_DEBUG "%s TX(%i):", dev->name, skb->len);
583 debug_frame(skb);
584 #endif
585
586 desc = desc_address(port, port->txin, 1);
587 buff = buffer_offset(port, port->txin, 1);
588 len = skb->len;
589 memcpy_toio(card->rambase + buff, skb->data, len);
590
591 writew(len, &desc->len);
592 writeb(ST_TX_EOM, &desc->stat);
593 dev->trans_start = jiffies;
594
595 port->txin = (port->txin + 1) % card->tx_ring_buffers;
596 sca_outl(desc_offset(port, port->txin, 1),
597 get_dmac_tx(port) + EDAL, card);
598
599 sca_out(DSR_DE, DSR_TX(port->chan), card); /* Enable TX DMA */
600
601 desc = desc_address(port, port->txin + 1, 1);
602 if (readb(&desc->stat)) /* allow 1 packet gap */
603 netif_stop_queue(dev);
604
605 spin_unlock_irq(&port->lock);
606
607 dev_kfree_skb(skb);
608 return 0;
609 }
610
611
612 static u32 __devinit sca_detect_ram(card_t *card, u8 __iomem *rambase,
613 u32 ramsize)
614 {
615 /* Round RAM size to 32 bits, fill from end to start */
616 u32 i = ramsize &= ~3;
617
618 do {
619 i -= 4;
620 writel(i ^ 0x12345678, rambase + i);
621 } while (i > 0);
622
623 for (i = 0; i < ramsize ; i += 4) {
624 if (readl(rambase + i) != (i ^ 0x12345678))
625 break;
626 }
627
628 return i;
629 }
630
631
632 static void __devinit sca_init(card_t *card, int wait_states)
633 {
634 sca_out(wait_states, WCRL, card); /* Wait Control */
635 sca_out(wait_states, WCRM, card);
636 sca_out(wait_states, WCRH, card);
637
638 sca_out(0, DMER, card); /* DMA Master disable */
639 sca_out(0x03, PCR, card); /* DMA priority */
640 sca_out(0, DSR_RX(0), card); /* DMA disable - to halt state */
641 sca_out(0, DSR_TX(0), card);
642 sca_out(0, DSR_RX(1), card);
643 sca_out(0, DSR_TX(1), card);
644 sca_out(DMER_DME, DMER, card); /* DMA Master enable */
645 }
Linux kernel - Deliverables
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