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iwlwifi: don't include iwl-dev.h from iwl-devtrace.h
[deliverable/linux.git] / drivers / net / wireless / ath / ar9170 / phy.c
1 /*
2 * Atheros AR9170 driver
3 *
4 * PHY and RF code
5 *
6 * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, see
20 * http://www.gnu.org/licenses/.
21 *
22 * This file incorporates work covered by the following copyright and
23 * permission notice:
24 * Copyright (c) 2007-2008 Atheros Communications, Inc.
25 *
26 * Permission to use, copy, modify, and/or distribute this software for any
27 * purpose with or without fee is hereby granted, provided that the above
28 * copyright notice and this permission notice appear in all copies.
29 *
30 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
31 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
32 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
33 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
34 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
35 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
36 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
37 */
38
39 #include <linux/bitrev.h>
40 #include "ar9170.h"
41 #include "cmd.h"
42
43 static int ar9170_init_power_cal(struct ar9170 *ar)
44 {
45 ar9170_regwrite_begin(ar);
46
47 ar9170_regwrite(0x1bc000 + 0x993c, 0x7f);
48 ar9170_regwrite(0x1bc000 + 0x9934, 0x3f3f3f3f);
49 ar9170_regwrite(0x1bc000 + 0x9938, 0x3f3f3f3f);
50 ar9170_regwrite(0x1bc000 + 0xa234, 0x3f3f3f3f);
51 ar9170_regwrite(0x1bc000 + 0xa238, 0x3f3f3f3f);
52 ar9170_regwrite(0x1bc000 + 0xa38c, 0x3f3f3f3f);
53 ar9170_regwrite(0x1bc000 + 0xa390, 0x3f3f3f3f);
54 ar9170_regwrite(0x1bc000 + 0xa3cc, 0x3f3f3f3f);
55 ar9170_regwrite(0x1bc000 + 0xa3d0, 0x3f3f3f3f);
56 ar9170_regwrite(0x1bc000 + 0xa3d4, 0x3f3f3f3f);
57
58 ar9170_regwrite_finish();
59 return ar9170_regwrite_result();
60 }
61
62 struct ar9170_phy_init {
63 u32 reg, _5ghz_20, _5ghz_40, _2ghz_40, _2ghz_20;
64 };
65
66 static struct ar9170_phy_init ar5416_phy_init[] = {
67 { 0x1c5800, 0x00000007, 0x00000007, 0x00000007, 0x00000007, },
68 { 0x1c5804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, },
69 { 0x1c5808, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
70 { 0x1c580c, 0xad848e19, 0xad848e19, 0xad848e19, 0xad848e19, },
71 { 0x1c5810, 0x7d14e000, 0x7d14e000, 0x7d14e000, 0x7d14e000, },
72 { 0x1c5814, 0x9c0a9f6b, 0x9c0a9f6b, 0x9c0a9f6b, 0x9c0a9f6b, },
73 { 0x1c5818, 0x00000090, 0x00000090, 0x00000090, 0x00000090, },
74 { 0x1c581c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
75 { 0x1c5820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, },
76 { 0x1c5824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, },
77 { 0x1c5828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, },
78 { 0x1c582c, 0x0000a000, 0x0000a000, 0x0000a000, 0x0000a000, },
79 { 0x1c5830, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
80 { 0x1c5834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, },
81 { 0x1c5838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, },
82 { 0x1c583c, 0x00200400, 0x00200400, 0x00200400, 0x00200400, },
83 { 0x1c5840, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e, },
84 { 0x1c5844, 0x1372161e, 0x13721c1e, 0x13721c24, 0x137216a4, },
85 { 0x1c5848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, },
86 { 0x1c584c, 0x1284233c, 0x1284233c, 0x1284233c, 0x1284233c, },
87 { 0x1c5850, 0x6c48b4e4, 0x6c48b4e4, 0x6c48b0e4, 0x6c48b0e4, },
88 { 0x1c5854, 0x00000859, 0x00000859, 0x00000859, 0x00000859, },
89 { 0x1c5858, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, },
90 { 0x1c585c, 0x31395c5e, 0x31395c5e, 0x31395c5e, 0x31395c5e, },
91 { 0x1c5860, 0x0004dd10, 0x0004dd10, 0x0004dd20, 0x0004dd20, },
92 { 0x1c5868, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, },
93 { 0x1c586c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, },
94 { 0x1c5900, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
95 { 0x1c5904, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
96 { 0x1c5908, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
97 { 0x1c590c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
98 { 0x1c5914, 0x000007d0, 0x000007d0, 0x00000898, 0x00000898, },
99 { 0x1c5918, 0x00000118, 0x00000230, 0x00000268, 0x00000134, },
100 { 0x1c591c, 0x10000fff, 0x10000fff, 0x10000fff, 0x10000fff, },
101 { 0x1c5920, 0x0510081c, 0x0510081c, 0x0510001c, 0x0510001c, },
102 { 0x1c5924, 0xd0058a15, 0xd0058a15, 0xd0058a15, 0xd0058a15, },
103 { 0x1c5928, 0x00000001, 0x00000001, 0x00000001, 0x00000001, },
104 { 0x1c592c, 0x00000004, 0x00000004, 0x00000004, 0x00000004, },
105 { 0x1c5934, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, },
106 { 0x1c5938, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, },
107 { 0x1c593c, 0x0000007f, 0x0000007f, 0x0000007f, 0x0000007f, },
108 { 0x1c5944, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020, },
109 { 0x1c5948, 0x9280b212, 0x9280b212, 0x9280b212, 0x9280b212, },
110 { 0x1c594c, 0x00020028, 0x00020028, 0x00020028, 0x00020028, },
111 { 0x1c5954, 0x5d50e188, 0x5d50e188, 0x5d50e188, 0x5d50e188, },
112 { 0x1c5958, 0x00081fff, 0x00081fff, 0x00081fff, 0x00081fff, },
113 { 0x1c5960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, },
114 { 0x1c5964, 0x00001120, 0x00001120, 0x00001120, 0x00001120, },
115 { 0x1c5970, 0x190fb515, 0x190fb515, 0x190fb515, 0x190fb515, },
116 { 0x1c5974, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
117 { 0x1c5978, 0x00000001, 0x00000001, 0x00000001, 0x00000001, },
118 { 0x1c597c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
119 { 0x1c5980, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
120 { 0x1c5984, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
121 { 0x1c5988, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
122 { 0x1c598c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
123 { 0x1c5990, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
124 { 0x1c5994, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
125 { 0x1c5998, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
126 { 0x1c599c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
127 { 0x1c59a0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
128 { 0x1c59a4, 0x00000007, 0x00000007, 0x00000007, 0x00000007, },
129 { 0x1c59a8, 0x001fff00, 0x001fff00, 0x001fff00, 0x001fff00, },
130 { 0x1c59ac, 0x006f00c4, 0x006f00c4, 0x006f00c4, 0x006f00c4, },
131 { 0x1c59b0, 0x03051000, 0x03051000, 0x03051000, 0x03051000, },
132 { 0x1c59b4, 0x00000820, 0x00000820, 0x00000820, 0x00000820, },
133 { 0x1c59c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, },
134 { 0x1c59c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, },
135 { 0x1c59c8, 0x60f6532c, 0x60f6532c, 0x60f6532c, 0x60f6532c, },
136 { 0x1c59cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, },
137 { 0x1c59d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, },
138 { 0x1c59d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
139 { 0x1c59d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
140 { 0x1c59dc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
141 { 0x1c59e0, 0x00000200, 0x00000200, 0x00000200, 0x00000200, },
142 { 0x1c59e4, 0x64646464, 0x64646464, 0x64646464, 0x64646464, },
143 { 0x1c59e8, 0x3c787878, 0x3c787878, 0x3c787878, 0x3c787878, },
144 { 0x1c59ec, 0x000000aa, 0x000000aa, 0x000000aa, 0x000000aa, },
145 { 0x1c59f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
146 { 0x1c59fc, 0x00001042, 0x00001042, 0x00001042, 0x00001042, },
147 { 0x1c5a00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
148 { 0x1c5a04, 0x00000040, 0x00000040, 0x00000040, 0x00000040, },
149 { 0x1c5a08, 0x00000080, 0x00000080, 0x00000080, 0x00000080, },
150 { 0x1c5a0c, 0x000001a1, 0x000001a1, 0x00000141, 0x00000141, },
151 { 0x1c5a10, 0x000001e1, 0x000001e1, 0x00000181, 0x00000181, },
152 { 0x1c5a14, 0x00000021, 0x00000021, 0x000001c1, 0x000001c1, },
153 { 0x1c5a18, 0x00000061, 0x00000061, 0x00000001, 0x00000001, },
154 { 0x1c5a1c, 0x00000168, 0x00000168, 0x00000041, 0x00000041, },
155 { 0x1c5a20, 0x000001a8, 0x000001a8, 0x000001a8, 0x000001a8, },
156 { 0x1c5a24, 0x000001e8, 0x000001e8, 0x000001e8, 0x000001e8, },
157 { 0x1c5a28, 0x00000028, 0x00000028, 0x00000028, 0x00000028, },
158 { 0x1c5a2c, 0x00000068, 0x00000068, 0x00000068, 0x00000068, },
159 { 0x1c5a30, 0x00000189, 0x00000189, 0x000000a8, 0x000000a8, },
160 { 0x1c5a34, 0x000001c9, 0x000001c9, 0x00000169, 0x00000169, },
161 { 0x1c5a38, 0x00000009, 0x00000009, 0x000001a9, 0x000001a9, },
162 { 0x1c5a3c, 0x00000049, 0x00000049, 0x000001e9, 0x000001e9, },
163 { 0x1c5a40, 0x00000089, 0x00000089, 0x00000029, 0x00000029, },
164 { 0x1c5a44, 0x00000170, 0x00000170, 0x00000069, 0x00000069, },
165 { 0x1c5a48, 0x000001b0, 0x000001b0, 0x00000190, 0x00000190, },
166 { 0x1c5a4c, 0x000001f0, 0x000001f0, 0x000001d0, 0x000001d0, },
167 { 0x1c5a50, 0x00000030, 0x00000030, 0x00000010, 0x00000010, },
168 { 0x1c5a54, 0x00000070, 0x00000070, 0x00000050, 0x00000050, },
169 { 0x1c5a58, 0x00000191, 0x00000191, 0x00000090, 0x00000090, },
170 { 0x1c5a5c, 0x000001d1, 0x000001d1, 0x00000151, 0x00000151, },
171 { 0x1c5a60, 0x00000011, 0x00000011, 0x00000191, 0x00000191, },
172 { 0x1c5a64, 0x00000051, 0x00000051, 0x000001d1, 0x000001d1, },
173 { 0x1c5a68, 0x00000091, 0x00000091, 0x00000011, 0x00000011, },
174 { 0x1c5a6c, 0x000001b8, 0x000001b8, 0x00000051, 0x00000051, },
175 { 0x1c5a70, 0x000001f8, 0x000001f8, 0x00000198, 0x00000198, },
176 { 0x1c5a74, 0x00000038, 0x00000038, 0x000001d8, 0x000001d8, },
177 { 0x1c5a78, 0x00000078, 0x00000078, 0x00000018, 0x00000018, },
178 { 0x1c5a7c, 0x00000199, 0x00000199, 0x00000058, 0x00000058, },
179 { 0x1c5a80, 0x000001d9, 0x000001d9, 0x00000098, 0x00000098, },
180 { 0x1c5a84, 0x00000019, 0x00000019, 0x00000159, 0x00000159, },
181 { 0x1c5a88, 0x00000059, 0x00000059, 0x00000199, 0x00000199, },
182 { 0x1c5a8c, 0x00000099, 0x00000099, 0x000001d9, 0x000001d9, },
183 { 0x1c5a90, 0x000000d9, 0x000000d9, 0x00000019, 0x00000019, },
184 { 0x1c5a94, 0x000000f9, 0x000000f9, 0x00000059, 0x00000059, },
185 { 0x1c5a98, 0x000000f9, 0x000000f9, 0x00000099, 0x00000099, },
186 { 0x1c5a9c, 0x000000f9, 0x000000f9, 0x000000d9, 0x000000d9, },
187 { 0x1c5aa0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
188 { 0x1c5aa4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
189 { 0x1c5aa8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
190 { 0x1c5aac, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
191 { 0x1c5ab0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
192 { 0x1c5ab4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
193 { 0x1c5ab8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
194 { 0x1c5abc, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
195 { 0x1c5ac0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
196 { 0x1c5ac4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
197 { 0x1c5ac8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
198 { 0x1c5acc, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
199 { 0x1c5ad0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
200 { 0x1c5ad4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
201 { 0x1c5ad8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
202 { 0x1c5adc, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
203 { 0x1c5ae0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
204 { 0x1c5ae4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
205 { 0x1c5ae8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
206 { 0x1c5aec, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
207 { 0x1c5af0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
208 { 0x1c5af4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
209 { 0x1c5af8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
210 { 0x1c5afc, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
211 { 0x1c5b00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
212 { 0x1c5b04, 0x00000001, 0x00000001, 0x00000001, 0x00000001, },
213 { 0x1c5b08, 0x00000002, 0x00000002, 0x00000002, 0x00000002, },
214 { 0x1c5b0c, 0x00000003, 0x00000003, 0x00000003, 0x00000003, },
215 { 0x1c5b10, 0x00000004, 0x00000004, 0x00000004, 0x00000004, },
216 { 0x1c5b14, 0x00000005, 0x00000005, 0x00000005, 0x00000005, },
217 { 0x1c5b18, 0x00000008, 0x00000008, 0x00000008, 0x00000008, },
218 { 0x1c5b1c, 0x00000009, 0x00000009, 0x00000009, 0x00000009, },
219 { 0x1c5b20, 0x0000000a, 0x0000000a, 0x0000000a, 0x0000000a, },
220 { 0x1c5b24, 0x0000000b, 0x0000000b, 0x0000000b, 0x0000000b, },
221 { 0x1c5b28, 0x0000000c, 0x0000000c, 0x0000000c, 0x0000000c, },
222 { 0x1c5b2c, 0x0000000d, 0x0000000d, 0x0000000d, 0x0000000d, },
223 { 0x1c5b30, 0x00000010, 0x00000010, 0x00000010, 0x00000010, },
224 { 0x1c5b34, 0x00000011, 0x00000011, 0x00000011, 0x00000011, },
225 { 0x1c5b38, 0x00000012, 0x00000012, 0x00000012, 0x00000012, },
226 { 0x1c5b3c, 0x00000013, 0x00000013, 0x00000013, 0x00000013, },
227 { 0x1c5b40, 0x00000014, 0x00000014, 0x00000014, 0x00000014, },
228 { 0x1c5b44, 0x00000015, 0x00000015, 0x00000015, 0x00000015, },
229 { 0x1c5b48, 0x00000018, 0x00000018, 0x00000018, 0x00000018, },
230 { 0x1c5b4c, 0x00000019, 0x00000019, 0x00000019, 0x00000019, },
231 { 0x1c5b50, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, },
232 { 0x1c5b54, 0x0000001b, 0x0000001b, 0x0000001b, 0x0000001b, },
233 { 0x1c5b58, 0x0000001c, 0x0000001c, 0x0000001c, 0x0000001c, },
234 { 0x1c5b5c, 0x0000001d, 0x0000001d, 0x0000001d, 0x0000001d, },
235 { 0x1c5b60, 0x00000020, 0x00000020, 0x00000020, 0x00000020, },
236 { 0x1c5b64, 0x00000021, 0x00000021, 0x00000021, 0x00000021, },
237 { 0x1c5b68, 0x00000022, 0x00000022, 0x00000022, 0x00000022, },
238 { 0x1c5b6c, 0x00000023, 0x00000023, 0x00000023, 0x00000023, },
239 { 0x1c5b70, 0x00000024, 0x00000024, 0x00000024, 0x00000024, },
240 { 0x1c5b74, 0x00000025, 0x00000025, 0x00000025, 0x00000025, },
241 { 0x1c5b78, 0x00000028, 0x00000028, 0x00000028, 0x00000028, },
242 { 0x1c5b7c, 0x00000029, 0x00000029, 0x00000029, 0x00000029, },
243 { 0x1c5b80, 0x0000002a, 0x0000002a, 0x0000002a, 0x0000002a, },
244 { 0x1c5b84, 0x0000002b, 0x0000002b, 0x0000002b, 0x0000002b, },
245 { 0x1c5b88, 0x0000002c, 0x0000002c, 0x0000002c, 0x0000002c, },
246 { 0x1c5b8c, 0x0000002d, 0x0000002d, 0x0000002d, 0x0000002d, },
247 { 0x1c5b90, 0x00000030, 0x00000030, 0x00000030, 0x00000030, },
248 { 0x1c5b94, 0x00000031, 0x00000031, 0x00000031, 0x00000031, },
249 { 0x1c5b98, 0x00000032, 0x00000032, 0x00000032, 0x00000032, },
250 { 0x1c5b9c, 0x00000033, 0x00000033, 0x00000033, 0x00000033, },
251 { 0x1c5ba0, 0x00000034, 0x00000034, 0x00000034, 0x00000034, },
252 { 0x1c5ba4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
253 { 0x1c5ba8, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
254 { 0x1c5bac, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
255 { 0x1c5bb0, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
256 { 0x1c5bb4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
257 { 0x1c5bb8, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
258 { 0x1c5bbc, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
259 { 0x1c5bc0, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
260 { 0x1c5bc4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
261 { 0x1c5bc8, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
262 { 0x1c5bcc, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
263 { 0x1c5bd0, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
264 { 0x1c5bd4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
265 { 0x1c5bd8, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
266 { 0x1c5bdc, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
267 { 0x1c5be0, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
268 { 0x1c5be4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
269 { 0x1c5be8, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
270 { 0x1c5bec, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
271 { 0x1c5bf0, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
272 { 0x1c5bf4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
273 { 0x1c5bf8, 0x00000010, 0x00000010, 0x00000010, 0x00000010, },
274 { 0x1c5bfc, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, },
275 { 0x1c5c00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
276 { 0x1c5c0c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
277 { 0x1c5c10, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
278 { 0x1c5c14, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
279 { 0x1c5c18, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
280 { 0x1c5c1c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
281 { 0x1c5c20, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
282 { 0x1c5c24, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
283 { 0x1c5c28, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
284 { 0x1c5c2c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
285 { 0x1c5c30, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
286 { 0x1c5c34, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
287 { 0x1c5c38, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
288 { 0x1c5c3c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
289 { 0x1c5cf0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
290 { 0x1c5cf4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
291 { 0x1c5cf8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
292 { 0x1c5cfc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
293 { 0x1c6200, 0x00000008, 0x00000008, 0x0000000e, 0x0000000e, },
294 { 0x1c6204, 0x00000440, 0x00000440, 0x00000440, 0x00000440, },
295 { 0x1c6208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, },
296 { 0x1c620c, 0x012e8160, 0x012e8160, 0x012a8160, 0x012a8160, },
297 { 0x1c6210, 0x40806333, 0x40806333, 0x40806333, 0x40806333, },
298 { 0x1c6214, 0x00106c10, 0x00106c10, 0x00106c10, 0x00106c10, },
299 { 0x1c6218, 0x009c4060, 0x009c4060, 0x009c4060, 0x009c4060, },
300 { 0x1c621c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, },
301 { 0x1c6220, 0x018830c6, 0x018830c6, 0x018830c6, 0x018830c6, },
302 { 0x1c6224, 0x00000400, 0x00000400, 0x00000400, 0x00000400, },
303 { 0x1c6228, 0x000009b5, 0x000009b5, 0x000009b5, 0x000009b5, },
304 { 0x1c622c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
305 { 0x1c6230, 0x00000108, 0x00000210, 0x00000210, 0x00000108, },
306 { 0x1c6234, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, },
307 { 0x1c6238, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, },
308 { 0x1c623c, 0x13c889af, 0x13c889af, 0x13c889af, 0x13c889af, },
309 { 0x1c6240, 0x38490a20, 0x38490a20, 0x38490a20, 0x38490a20, },
310 { 0x1c6244, 0x00007bb6, 0x00007bb6, 0x00007bb6, 0x00007bb6, },
311 { 0x1c6248, 0x0fff3ffc, 0x0fff3ffc, 0x0fff3ffc, 0x0fff3ffc, },
312 { 0x1c624c, 0x00000001, 0x00000001, 0x00000001, 0x00000001, },
313 { 0x1c6250, 0x0000a000, 0x0000a000, 0x0000a000, 0x0000a000, },
314 { 0x1c6254, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
315 { 0x1c6258, 0x0cc75380, 0x0cc75380, 0x0cc75380, 0x0cc75380, },
316 { 0x1c625c, 0x0f0f0f01, 0x0f0f0f01, 0x0f0f0f01, 0x0f0f0f01, },
317 { 0x1c6260, 0xdfa91f01, 0xdfa91f01, 0xdfa91f01, 0xdfa91f01, },
318 { 0x1c6264, 0x00418a11, 0x00418a11, 0x00418a11, 0x00418a11, },
319 { 0x1c6268, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
320 { 0x1c626c, 0x09249126, 0x09249126, 0x09249126, 0x09249126, },
321 { 0x1c6274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, },
322 { 0x1c6278, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, },
323 { 0x1c627c, 0x051701ce, 0x051701ce, 0x051701ce, 0x051701ce, },
324 { 0x1c6300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, },
325 { 0x1c6304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, },
326 { 0x1c6308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, },
327 { 0x1c630c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, },
328 { 0x1c6310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, },
329 { 0x1c6314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, },
330 { 0x1c6318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, },
331 { 0x1c631c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, },
332 { 0x1c6320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, },
333 { 0x1c6324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, },
334 { 0x1c6328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, },
335 { 0x1c632c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
336 { 0x1c6330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
337 { 0x1c6334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
338 { 0x1c6338, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
339 { 0x1c633c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
340 { 0x1c6340, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
341 { 0x1c6344, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
342 { 0x1c6348, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff, },
343 { 0x1c634c, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff, },
344 { 0x1c6350, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff, },
345 { 0x1c6354, 0x0003ffff, 0x0003ffff, 0x0003ffff, 0x0003ffff, },
346 { 0x1c6358, 0x79a8aa1f, 0x79a8aa1f, 0x79a8aa1f, 0x79a8aa1f, },
347 { 0x1c6388, 0x08000000, 0x08000000, 0x08000000, 0x08000000, },
348 { 0x1c638c, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, },
349 { 0x1c6390, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, },
350 { 0x1c6394, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, },
351 { 0x1c6398, 0x000001ce, 0x000001ce, 0x000001ce, 0x000001ce, },
352 { 0x1c639c, 0x00000007, 0x00000007, 0x00000007, 0x00000007, },
353 { 0x1c63a0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
354 { 0x1c63a4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
355 { 0x1c63a8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
356 { 0x1c63ac, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
357 { 0x1c63b0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
358 { 0x1c63b4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
359 { 0x1c63b8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
360 { 0x1c63bc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
361 { 0x1c63c0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
362 { 0x1c63c4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
363 { 0x1c63c8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
364 { 0x1c63cc, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, },
365 { 0x1c63d0, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, },
366 { 0x1c63d4, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, },
367 { 0x1c63d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
368 { 0x1c63dc, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, },
369 { 0x1c63e0, 0x000000c0, 0x000000c0, 0x000000c0, 0x000000c0, },
370 { 0x1c6848, 0x00180a65, 0x00180a65, 0x00180a68, 0x00180a68, },
371 { 0x1c6920, 0x0510001c, 0x0510001c, 0x0510001c, 0x0510001c, },
372 { 0x1c6960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, },
373 { 0x1c720c, 0x012e8160, 0x012e8160, 0x012a8160, 0x012a8160, },
374 { 0x1c726c, 0x09249126, 0x09249126, 0x09249126, 0x09249126, },
375 { 0x1c7848, 0x00180a65, 0x00180a65, 0x00180a68, 0x00180a68, },
376 { 0x1c7920, 0x0510001c, 0x0510001c, 0x0510001c, 0x0510001c, },
377 { 0x1c7960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, },
378 { 0x1c820c, 0x012e8160, 0x012e8160, 0x012a8160, 0x012a8160, },
379 { 0x1c826c, 0x09249126, 0x09249126, 0x09249126, 0x09249126, },
380 /* { 0x1c8864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, }, */
381 { 0x1c8864, 0x0001c600, 0x0001c600, 0x0001c600, 0x0001c600, },
382 { 0x1c895c, 0x004b6a8e, 0x004b6a8e, 0x004b6a8e, 0x004b6a8e, },
383 { 0x1c8968, 0x000003ce, 0x000003ce, 0x000003ce, 0x000003ce, },
384 { 0x1c89bc, 0x00181400, 0x00181400, 0x00181400, 0x00181400, },
385 { 0x1c9270, 0x00820820, 0x00820820, 0x00820820, 0x00820820, },
386 { 0x1c935c, 0x066c420f, 0x066c420f, 0x066c420f, 0x066c420f, },
387 { 0x1c9360, 0x0f282207, 0x0f282207, 0x0f282207, 0x0f282207, },
388 { 0x1c9364, 0x17601685, 0x17601685, 0x17601685, 0x17601685, },
389 { 0x1c9368, 0x1f801104, 0x1f801104, 0x1f801104, 0x1f801104, },
390 { 0x1c936c, 0x37a00c03, 0x37a00c03, 0x37a00c03, 0x37a00c03, },
391 { 0x1c9370, 0x3fc40883, 0x3fc40883, 0x3fc40883, 0x3fc40883, },
392 { 0x1c9374, 0x57c00803, 0x57c00803, 0x57c00803, 0x57c00803, },
393 { 0x1c9378, 0x5fd80682, 0x5fd80682, 0x5fd80682, 0x5fd80682, },
394 { 0x1c937c, 0x7fe00482, 0x7fe00482, 0x7fe00482, 0x7fe00482, },
395 { 0x1c9380, 0x7f3c7bba, 0x7f3c7bba, 0x7f3c7bba, 0x7f3c7bba, },
396 { 0x1c9384, 0xf3307ff0, 0xf3307ff0, 0xf3307ff0, 0xf3307ff0, }
397 };
398
399 /*
400 * look up a certain register in ar5416_phy_init[] and return the init. value
401 * for the band and bandwidth given. Return 0 if register address not found.
402 */
403 static u32 ar9170_get_default_phy_reg_val(u32 reg, bool is_2ghz, bool is_40mhz)
404 {
405 unsigned int i;
406 for (i = 0; i < ARRAY_SIZE(ar5416_phy_init); i++) {
407 if (ar5416_phy_init[i].reg != reg)
408 continue;
409
410 if (is_2ghz) {
411 if (is_40mhz)
412 return ar5416_phy_init[i]._2ghz_40;
413 else
414 return ar5416_phy_init[i]._2ghz_20;
415 } else {
416 if (is_40mhz)
417 return ar5416_phy_init[i]._5ghz_40;
418 else
419 return ar5416_phy_init[i]._5ghz_20;
420 }
421 }
422 return 0;
423 }
424
425 /*
426 * initialize some phy regs from eeprom values in modal_header[]
427 * acc. to band and bandwith
428 */
429 static int ar9170_init_phy_from_eeprom(struct ar9170 *ar,
430 bool is_2ghz, bool is_40mhz)
431 {
432 static const u8 xpd2pd[16] = {
433 0x2, 0x2, 0x2, 0x1, 0x2, 0x2, 0x6, 0x2,
434 0x2, 0x3, 0x7, 0x2, 0xB, 0x2, 0x2, 0x2
435 };
436 u32 defval, newval;
437 /* pointer to the modal_header acc. to band */
438 struct ar9170_eeprom_modal *m = &ar->eeprom.modal_header[is_2ghz];
439
440 ar9170_regwrite_begin(ar);
441
442 /* ant common control (index 0) */
443 newval = le32_to_cpu(m->antCtrlCommon);
444 ar9170_regwrite(0x1c5964, newval);
445
446 /* ant control chain 0 (index 1) */
447 newval = le32_to_cpu(m->antCtrlChain[0]);
448 ar9170_regwrite(0x1c5960, newval);
449
450 /* ant control chain 2 (index 2) */
451 newval = le32_to_cpu(m->antCtrlChain[1]);
452 ar9170_regwrite(0x1c7960, newval);
453
454 /* SwSettle (index 3) */
455 if (!is_40mhz) {
456 defval = ar9170_get_default_phy_reg_val(0x1c5844,
457 is_2ghz, is_40mhz);
458 newval = (defval & ~0x3f80) |
459 ((m->switchSettling & 0x7f) << 7);
460 ar9170_regwrite(0x1c5844, newval);
461 }
462
463 /* adcDesired, pdaDesired (index 4) */
464 defval = ar9170_get_default_phy_reg_val(0x1c5850, is_2ghz, is_40mhz);
465 newval = (defval & ~0xffff) | ((u8)m->pgaDesiredSize << 8) |
466 ((u8)m->adcDesiredSize);
467 ar9170_regwrite(0x1c5850, newval);
468
469 /* TxEndToXpaOff, TxFrameToXpaOn (index 5) */
470 defval = ar9170_get_default_phy_reg_val(0x1c5834, is_2ghz, is_40mhz);
471 newval = (m->txEndToXpaOff << 24) | (m->txEndToXpaOff << 16) |
472 (m->txFrameToXpaOn << 8) | m->txFrameToXpaOn;
473 ar9170_regwrite(0x1c5834, newval);
474
475 /* TxEndToRxOn (index 6) */
476 defval = ar9170_get_default_phy_reg_val(0x1c5828, is_2ghz, is_40mhz);
477 newval = (defval & ~0xff0000) | (m->txEndToRxOn << 16);
478 ar9170_regwrite(0x1c5828, newval);
479
480 /* thresh62 (index 7) */
481 defval = ar9170_get_default_phy_reg_val(0x1c8864, is_2ghz, is_40mhz);
482 newval = (defval & ~0x7f000) | (m->thresh62 << 12);
483 ar9170_regwrite(0x1c8864, newval);
484
485 /* tx/rx attenuation chain 0 (index 8) */
486 defval = ar9170_get_default_phy_reg_val(0x1c5848, is_2ghz, is_40mhz);
487 newval = (defval & ~0x3f000) | ((m->txRxAttenCh[0] & 0x3f) << 12);
488 ar9170_regwrite(0x1c5848, newval);
489
490 /* tx/rx attenuation chain 2 (index 9) */
491 defval = ar9170_get_default_phy_reg_val(0x1c7848, is_2ghz, is_40mhz);
492 newval = (defval & ~0x3f000) | ((m->txRxAttenCh[1] & 0x3f) << 12);
493 ar9170_regwrite(0x1c7848, newval);
494
495 /* tx/rx margin chain 0 (index 10) */
496 defval = ar9170_get_default_phy_reg_val(0x1c620c, is_2ghz, is_40mhz);
497 newval = (defval & ~0xfc0000) | ((m->rxTxMarginCh[0] & 0x3f) << 18);
498 /* bsw margin chain 0 for 5GHz only */
499 if (!is_2ghz)
500 newval = (newval & ~0x3c00) | ((m->bswMargin[0] & 0xf) << 10);
501 ar9170_regwrite(0x1c620c, newval);
502
503 /* tx/rx margin chain 2 (index 11) */
504 defval = ar9170_get_default_phy_reg_val(0x1c820c, is_2ghz, is_40mhz);
505 newval = (defval & ~0xfc0000) | ((m->rxTxMarginCh[1] & 0x3f) << 18);
506 ar9170_regwrite(0x1c820c, newval);
507
508 /* iqCall, iqCallq chain 0 (index 12) */
509 defval = ar9170_get_default_phy_reg_val(0x1c5920, is_2ghz, is_40mhz);
510 newval = (defval & ~0x7ff) | (((u8)m->iqCalICh[0] & 0x3f) << 5) |
511 ((u8)m->iqCalQCh[0] & 0x1f);
512 ar9170_regwrite(0x1c5920, newval);
513
514 /* iqCall, iqCallq chain 2 (index 13) */
515 defval = ar9170_get_default_phy_reg_val(0x1c7920, is_2ghz, is_40mhz);
516 newval = (defval & ~0x7ff) | (((u8)m->iqCalICh[1] & 0x3f) << 5) |
517 ((u8)m->iqCalQCh[1] & 0x1f);
518 ar9170_regwrite(0x1c7920, newval);
519
520 /* xpd gain mask (index 14) */
521 defval = ar9170_get_default_phy_reg_val(0x1c6258, is_2ghz, is_40mhz);
522 newval = (defval & ~0xf0000) | (xpd2pd[m->xpdGain & 0xf] << 16);
523 ar9170_regwrite(0x1c6258, newval);
524 ar9170_regwrite_finish();
525
526 return ar9170_regwrite_result();
527 }
528
529 int ar9170_init_phy(struct ar9170 *ar, enum ieee80211_band band)
530 {
531 int i, err;
532 u32 val;
533 bool is_2ghz = band == IEEE80211_BAND_2GHZ;
534 bool is_40mhz = conf_is_ht40(&ar->hw->conf);
535
536 ar9170_regwrite_begin(ar);
537
538 for (i = 0; i < ARRAY_SIZE(ar5416_phy_init); i++) {
539 if (is_40mhz) {
540 if (is_2ghz)
541 val = ar5416_phy_init[i]._2ghz_40;
542 else
543 val = ar5416_phy_init[i]._5ghz_40;
544 } else {
545 if (is_2ghz)
546 val = ar5416_phy_init[i]._2ghz_20;
547 else
548 val = ar5416_phy_init[i]._5ghz_20;
549 }
550
551 ar9170_regwrite(ar5416_phy_init[i].reg, val);
552 }
553
554 ar9170_regwrite_finish();
555 err = ar9170_regwrite_result();
556 if (err)
557 return err;
558
559 err = ar9170_init_phy_from_eeprom(ar, is_2ghz, is_40mhz);
560 if (err)
561 return err;
562
563 err = ar9170_init_power_cal(ar);
564 if (err)
565 return err;
566
567 /* XXX: remove magic! */
568 if (is_2ghz)
569 err = ar9170_write_reg(ar, 0x1d4014, 0x5163);
570 else
571 err = ar9170_write_reg(ar, 0x1d4014, 0x5143);
572
573 return err;
574 }
575
576 struct ar9170_rf_init {
577 u32 reg, _5ghz, _2ghz;
578 };
579
580 static struct ar9170_rf_init ar9170_rf_init[] = {
581 /* bank 0 */
582 { 0x1c58b0, 0x1e5795e5, 0x1e5795e5},
583 { 0x1c58e0, 0x02008020, 0x02008020},
584 /* bank 1 */
585 { 0x1c58b0, 0x02108421, 0x02108421},
586 { 0x1c58ec, 0x00000008, 0x00000008},
587 /* bank 2 */
588 { 0x1c58b0, 0x0e73ff17, 0x0e73ff17},
589 { 0x1c58e0, 0x00000420, 0x00000420},
590 /* bank 3 */
591 { 0x1c58f0, 0x01400018, 0x01c00018},
592 /* bank 4 */
593 { 0x1c58b0, 0x000001a1, 0x000001a1},
594 { 0x1c58e8, 0x00000001, 0x00000001},
595 /* bank 5 */
596 { 0x1c58b0, 0x00000013, 0x00000013},
597 { 0x1c58e4, 0x00000002, 0x00000002},
598 /* bank 6 */
599 { 0x1c58b0, 0x00000000, 0x00000000},
600 { 0x1c58b0, 0x00000000, 0x00000000},
601 { 0x1c58b0, 0x00000000, 0x00000000},
602 { 0x1c58b0, 0x00000000, 0x00000000},
603 { 0x1c58b0, 0x00000000, 0x00000000},
604 { 0x1c58b0, 0x00004000, 0x00004000},
605 { 0x1c58b0, 0x00006c00, 0x00006c00},
606 { 0x1c58b0, 0x00002c00, 0x00002c00},
607 { 0x1c58b0, 0x00004800, 0x00004800},
608 { 0x1c58b0, 0x00004000, 0x00004000},
609 { 0x1c58b0, 0x00006000, 0x00006000},
610 { 0x1c58b0, 0x00001000, 0x00001000},
611 { 0x1c58b0, 0x00004000, 0x00004000},
612 { 0x1c58b0, 0x00007c00, 0x00007c00},
613 { 0x1c58b0, 0x00007c00, 0x00007c00},
614 { 0x1c58b0, 0x00007c00, 0x00007c00},
615 { 0x1c58b0, 0x00007c00, 0x00007c00},
616 { 0x1c58b0, 0x00007c00, 0x00007c00},
617 { 0x1c58b0, 0x00087c00, 0x00087c00},
618 { 0x1c58b0, 0x00007c00, 0x00007c00},
619 { 0x1c58b0, 0x00005400, 0x00005400},
620 { 0x1c58b0, 0x00000c00, 0x00000c00},
621 { 0x1c58b0, 0x00001800, 0x00001800},
622 { 0x1c58b0, 0x00007c00, 0x00007c00},
623 { 0x1c58b0, 0x00006c00, 0x00006c00},
624 { 0x1c58b0, 0x00006c00, 0x00006c00},
625 { 0x1c58b0, 0x00007c00, 0x00007c00},
626 { 0x1c58b0, 0x00002c00, 0x00002c00},
627 { 0x1c58b0, 0x00003c00, 0x00003c00},
628 { 0x1c58b0, 0x00003800, 0x00003800},
629 { 0x1c58b0, 0x00001c00, 0x00001c00},
630 { 0x1c58b0, 0x00000800, 0x00000800},
631 { 0x1c58b0, 0x00000408, 0x00000408},
632 { 0x1c58b0, 0x00004c15, 0x00004c15},
633 { 0x1c58b0, 0x00004188, 0x00004188},
634 { 0x1c58b0, 0x0000201e, 0x0000201e},
635 { 0x1c58b0, 0x00010408, 0x00010408},
636 { 0x1c58b0, 0x00000801, 0x00000801},
637 { 0x1c58b0, 0x00000c08, 0x00000c08},
638 { 0x1c58b0, 0x0000181e, 0x0000181e},
639 { 0x1c58b0, 0x00001016, 0x00001016},
640 { 0x1c58b0, 0x00002800, 0x00002800},
641 { 0x1c58b0, 0x00004010, 0x00004010},
642 { 0x1c58b0, 0x0000081c, 0x0000081c},
643 { 0x1c58b0, 0x00000115, 0x00000115},
644 { 0x1c58b0, 0x00000015, 0x00000015},
645 { 0x1c58b0, 0x00000066, 0x00000066},
646 { 0x1c58b0, 0x0000001c, 0x0000001c},
647 { 0x1c58b0, 0x00000000, 0x00000000},
648 { 0x1c58b0, 0x00000004, 0x00000004},
649 { 0x1c58b0, 0x00000015, 0x00000015},
650 { 0x1c58b0, 0x0000001f, 0x0000001f},
651 { 0x1c58e0, 0x00000000, 0x00000400},
652 /* bank 7 */
653 { 0x1c58b0, 0x000000a0, 0x000000a0},
654 { 0x1c58b0, 0x00000000, 0x00000000},
655 { 0x1c58b0, 0x00000040, 0x00000040},
656 { 0x1c58f0, 0x0000001c, 0x0000001c},
657 };
658
659 static int ar9170_init_rf_banks_0_7(struct ar9170 *ar, bool band5ghz)
660 {
661 int err, i;
662
663 ar9170_regwrite_begin(ar);
664
665 for (i = 0; i < ARRAY_SIZE(ar9170_rf_init); i++)
666 ar9170_regwrite(ar9170_rf_init[i].reg,
667 band5ghz ? ar9170_rf_init[i]._5ghz
668 : ar9170_rf_init[i]._2ghz);
669
670 ar9170_regwrite_finish();
671 err = ar9170_regwrite_result();
672 if (err)
673 printk(KERN_ERR "%s: rf init failed\n",
674 wiphy_name(ar->hw->wiphy));
675 return err;
676 }
677
678 static int ar9170_init_rf_bank4_pwr(struct ar9170 *ar, bool band5ghz,
679 u32 freq, enum ar9170_bw bw)
680 {
681 int err;
682 u32 d0, d1, td0, td1, fd0, fd1;
683 u8 chansel;
684 u8 refsel0 = 1, refsel1 = 0;
685 u8 lf_synth = 0;
686
687 switch (bw) {
688 case AR9170_BW_40_ABOVE:
689 freq += 10;
690 break;
691 case AR9170_BW_40_BELOW:
692 freq -= 10;
693 break;
694 case AR9170_BW_20:
695 break;
696 case __AR9170_NUM_BW:
697 BUG();
698 }
699
700 if (band5ghz) {
701 if (freq % 10) {
702 chansel = (freq - 4800) / 5;
703 } else {
704 chansel = ((freq - 4800) / 10) * 2;
705 refsel0 = 0;
706 refsel1 = 1;
707 }
708 chansel = byte_rev_table[chansel];
709 } else {
710 if (freq == 2484) {
711 chansel = 10 + (freq - 2274) / 5;
712 lf_synth = 1;
713 } else
714 chansel = 16 + (freq - 2272) / 5;
715 chansel *= 4;
716 chansel = byte_rev_table[chansel];
717 }
718
719 d1 = chansel;
720 d0 = 0x21 |
721 refsel0 << 3 |
722 refsel1 << 2 |
723 lf_synth << 1;
724 td0 = d0 & 0x1f;
725 td1 = d1 & 0x1f;
726 fd0 = td1 << 5 | td0;
727
728 td0 = (d0 >> 5) & 0x7;
729 td1 = (d1 >> 5) & 0x7;
730 fd1 = td1 << 5 | td0;
731
732 ar9170_regwrite_begin(ar);
733
734 ar9170_regwrite(0x1c58b0, fd0);
735 ar9170_regwrite(0x1c58e8, fd1);
736
737 ar9170_regwrite_finish();
738 err = ar9170_regwrite_result();
739 if (err)
740 return err;
741
742 msleep(10);
743
744 return 0;
745 }
746
747 struct ar9170_phy_freq_params {
748 u8 coeff_exp;
749 u16 coeff_man;
750 u8 coeff_exp_shgi;
751 u16 coeff_man_shgi;
752 };
753
754 struct ar9170_phy_freq_entry {
755 u16 freq;
756 struct ar9170_phy_freq_params params[__AR9170_NUM_BW];
757 };
758
759 /* NB: must be in sync with channel tables in main! */
760 static const struct ar9170_phy_freq_entry ar9170_phy_freq_params[] = {
761 /*
762 * freq,
763 * 20MHz,
764 * 40MHz (below),
765 * 40Mhz (above),
766 */
767 { 2412, {
768 { 3, 21737, 3, 19563, },
769 { 3, 21827, 3, 19644, },
770 { 3, 21647, 3, 19482, },
771 } },
772 { 2417, {
773 { 3, 21692, 3, 19523, },
774 { 3, 21782, 3, 19604, },
775 { 3, 21602, 3, 19442, },
776 } },
777 { 2422, {
778 { 3, 21647, 3, 19482, },
779 { 3, 21737, 3, 19563, },
780 { 3, 21558, 3, 19402, },
781 } },
782 { 2427, {
783 { 3, 21602, 3, 19442, },
784 { 3, 21692, 3, 19523, },
785 { 3, 21514, 3, 19362, },
786 } },
787 { 2432, {
788 { 3, 21558, 3, 19402, },
789 { 3, 21647, 3, 19482, },
790 { 3, 21470, 3, 19323, },
791 } },
792 { 2437, {
793 { 3, 21514, 3, 19362, },
794 { 3, 21602, 3, 19442, },
795 { 3, 21426, 3, 19283, },
796 } },
797 { 2442, {
798 { 3, 21470, 3, 19323, },
799 { 3, 21558, 3, 19402, },
800 { 3, 21382, 3, 19244, },
801 } },
802 { 2447, {
803 { 3, 21426, 3, 19283, },
804 { 3, 21514, 3, 19362, },
805 { 3, 21339, 3, 19205, },
806 } },
807 { 2452, {
808 { 3, 21382, 3, 19244, },
809 { 3, 21470, 3, 19323, },
810 { 3, 21295, 3, 19166, },
811 } },
812 { 2457, {
813 { 3, 21339, 3, 19205, },
814 { 3, 21426, 3, 19283, },
815 { 3, 21252, 3, 19127, },
816 } },
817 { 2462, {
818 { 3, 21295, 3, 19166, },
819 { 3, 21382, 3, 19244, },
820 { 3, 21209, 3, 19088, },
821 } },
822 { 2467, {
823 { 3, 21252, 3, 19127, },
824 { 3, 21339, 3, 19205, },
825 { 3, 21166, 3, 19050, },
826 } },
827 { 2472, {
828 { 3, 21209, 3, 19088, },
829 { 3, 21295, 3, 19166, },
830 { 3, 21124, 3, 19011, },
831 } },
832 { 2484, {
833 { 3, 21107, 3, 18996, },
834 { 3, 21192, 3, 19073, },
835 { 3, 21022, 3, 18920, },
836 } },
837 { 4920, {
838 { 4, 21313, 4, 19181, },
839 { 4, 21356, 4, 19220, },
840 { 4, 21269, 4, 19142, },
841 } },
842 { 4940, {
843 { 4, 21226, 4, 19104, },
844 { 4, 21269, 4, 19142, },
845 { 4, 21183, 4, 19065, },
846 } },
847 { 4960, {
848 { 4, 21141, 4, 19027, },
849 { 4, 21183, 4, 19065, },
850 { 4, 21098, 4, 18988, },
851 } },
852 { 4980, {
853 { 4, 21056, 4, 18950, },
854 { 4, 21098, 4, 18988, },
855 { 4, 21014, 4, 18912, },
856 } },
857 { 5040, {
858 { 4, 20805, 4, 18725, },
859 { 4, 20846, 4, 18762, },
860 { 4, 20764, 4, 18687, },
861 } },
862 { 5060, {
863 { 4, 20723, 4, 18651, },
864 { 4, 20764, 4, 18687, },
865 { 4, 20682, 4, 18614, },
866 } },
867 { 5080, {
868 { 4, 20641, 4, 18577, },
869 { 4, 20682, 4, 18614, },
870 { 4, 20601, 4, 18541, },
871 } },
872 { 5180, {
873 { 4, 20243, 4, 18219, },
874 { 4, 20282, 4, 18254, },
875 { 4, 20204, 4, 18183, },
876 } },
877 { 5200, {
878 { 4, 20165, 4, 18148, },
879 { 4, 20204, 4, 18183, },
880 { 4, 20126, 4, 18114, },
881 } },
882 { 5220, {
883 { 4, 20088, 4, 18079, },
884 { 4, 20126, 4, 18114, },
885 { 4, 20049, 4, 18044, },
886 } },
887 { 5240, {
888 { 4, 20011, 4, 18010, },
889 { 4, 20049, 4, 18044, },
890 { 4, 19973, 4, 17976, },
891 } },
892 { 5260, {
893 { 4, 19935, 4, 17941, },
894 { 4, 19973, 4, 17976, },
895 { 4, 19897, 4, 17907, },
896 } },
897 { 5280, {
898 { 4, 19859, 4, 17873, },
899 { 4, 19897, 4, 17907, },
900 { 4, 19822, 4, 17840, },
901 } },
902 { 5300, {
903 { 4, 19784, 4, 17806, },
904 { 4, 19822, 4, 17840, },
905 { 4, 19747, 4, 17772, },
906 } },
907 { 5320, {
908 { 4, 19710, 4, 17739, },
909 { 4, 19747, 4, 17772, },
910 { 4, 19673, 4, 17706, },
911 } },
912 { 5500, {
913 { 4, 19065, 4, 17159, },
914 { 4, 19100, 4, 17190, },
915 { 4, 19030, 4, 17127, },
916 } },
917 { 5520, {
918 { 4, 18996, 4, 17096, },
919 { 4, 19030, 4, 17127, },
920 { 4, 18962, 4, 17065, },
921 } },
922 { 5540, {
923 { 4, 18927, 4, 17035, },
924 { 4, 18962, 4, 17065, },
925 { 4, 18893, 4, 17004, },
926 } },
927 { 5560, {
928 { 4, 18859, 4, 16973, },
929 { 4, 18893, 4, 17004, },
930 { 4, 18825, 4, 16943, },
931 } },
932 { 5580, {
933 { 4, 18792, 4, 16913, },
934 { 4, 18825, 4, 16943, },
935 { 4, 18758, 4, 16882, },
936 } },
937 { 5600, {
938 { 4, 18725, 4, 16852, },
939 { 4, 18758, 4, 16882, },
940 { 4, 18691, 4, 16822, },
941 } },
942 { 5620, {
943 { 4, 18658, 4, 16792, },
944 { 4, 18691, 4, 16822, },
945 { 4, 18625, 4, 16762, },
946 } },
947 { 5640, {
948 { 4, 18592, 4, 16733, },
949 { 4, 18625, 4, 16762, },
950 { 4, 18559, 4, 16703, },
951 } },
952 { 5660, {
953 { 4, 18526, 4, 16673, },
954 { 4, 18559, 4, 16703, },
955 { 4, 18493, 4, 16644, },
956 } },
957 { 5680, {
958 { 4, 18461, 4, 16615, },
959 { 4, 18493, 4, 16644, },
960 { 4, 18428, 4, 16586, },
961 } },
962 { 5700, {
963 { 4, 18396, 4, 16556, },
964 { 4, 18428, 4, 16586, },
965 { 4, 18364, 4, 16527, },
966 } },
967 { 5745, {
968 { 4, 18252, 4, 16427, },
969 { 4, 18284, 4, 16455, },
970 { 4, 18220, 4, 16398, },
971 } },
972 { 5765, {
973 { 4, 18189, 5, 32740, },
974 { 4, 18220, 4, 16398, },
975 { 4, 18157, 5, 32683, },
976 } },
977 { 5785, {
978 { 4, 18126, 5, 32626, },
979 { 4, 18157, 5, 32683, },
980 { 4, 18094, 5, 32570, },
981 } },
982 { 5805, {
983 { 4, 18063, 5, 32514, },
984 { 4, 18094, 5, 32570, },
985 { 4, 18032, 5, 32458, },
986 } },
987 { 5825, {
988 { 4, 18001, 5, 32402, },
989 { 4, 18032, 5, 32458, },
990 { 4, 17970, 5, 32347, },
991 } },
992 { 5170, {
993 { 4, 20282, 4, 18254, },
994 { 4, 20321, 4, 18289, },
995 { 4, 20243, 4, 18219, },
996 } },
997 { 5190, {
998 { 4, 20204, 4, 18183, },
999 { 4, 20243, 4, 18219, },
1000 { 4, 20165, 4, 18148, },
1001 } },
1002 { 5210, {
1003 { 4, 20126, 4, 18114, },
1004 { 4, 20165, 4, 18148, },
1005 { 4, 20088, 4, 18079, },
1006 } },
1007 { 5230, {
1008 { 4, 20049, 4, 18044, },
1009 { 4, 20088, 4, 18079, },
1010 { 4, 20011, 4, 18010, },
1011 } },
1012 };
1013
1014 static const struct ar9170_phy_freq_params *
1015 ar9170_get_hw_dyn_params(struct ieee80211_channel *channel,
1016 enum ar9170_bw bw)
1017 {
1018 unsigned int chanidx = 0;
1019 u16 freq = 2412;
1020
1021 if (channel) {
1022 chanidx = channel->hw_value;
1023 freq = channel->center_freq;
1024 }
1025
1026 BUG_ON(chanidx >= ARRAY_SIZE(ar9170_phy_freq_params));
1027
1028 BUILD_BUG_ON(__AR9170_NUM_BW != 3);
1029
1030 WARN_ON(ar9170_phy_freq_params[chanidx].freq != freq);
1031
1032 return &ar9170_phy_freq_params[chanidx].params[bw];
1033 }
1034
1035
1036 int ar9170_init_rf(struct ar9170 *ar)
1037 {
1038 const struct ar9170_phy_freq_params *freqpar;
1039 __le32 cmd[7];
1040 int err;
1041
1042 err = ar9170_init_rf_banks_0_7(ar, false);
1043 if (err)
1044 return err;
1045
1046 err = ar9170_init_rf_bank4_pwr(ar, false, 2412, AR9170_BW_20);
1047 if (err)
1048 return err;
1049
1050 freqpar = ar9170_get_hw_dyn_params(NULL, AR9170_BW_20);
1051
1052 cmd[0] = cpu_to_le32(2412 * 1000);
1053 cmd[1] = cpu_to_le32(0);
1054 cmd[2] = cpu_to_le32(1);
1055 cmd[3] = cpu_to_le32(freqpar->coeff_exp);
1056 cmd[4] = cpu_to_le32(freqpar->coeff_man);
1057 cmd[5] = cpu_to_le32(freqpar->coeff_exp_shgi);
1058 cmd[6] = cpu_to_le32(freqpar->coeff_man_shgi);
1059
1060 /* RF_INIT echoes the command back to us */
1061 err = ar->exec_cmd(ar, AR9170_CMD_RF_INIT,
1062 sizeof(cmd), (u8 *)cmd,
1063 sizeof(cmd), (u8 *)cmd);
1064 if (err)
1065 return err;
1066
1067 msleep(1000);
1068
1069 return ar9170_echo_test(ar, 0xaabbccdd);
1070 }
1071
1072 static int ar9170_find_freq_idx(int nfreqs, u8 *freqs, u8 f)
1073 {
1074 int idx = nfreqs - 2;
1075
1076 while (idx >= 0) {
1077 if (f >= freqs[idx])
1078 return idx;
1079 idx--;
1080 }
1081
1082 return 0;
1083 }
1084
1085 static s32 ar9170_interpolate_s32(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
1086 {
1087 /* nothing to interpolate, it's horizontal */
1088 if (y2 == y1)
1089 return y1;
1090
1091 /* check if we hit one of the edges */
1092 if (x == x1)
1093 return y1;
1094 if (x == x2)
1095 return y2;
1096
1097 /* x1 == x2 is bad, hopefully == x */
1098 if (x2 == x1)
1099 return y1;
1100
1101 return y1 + (((y2 - y1) * (x - x1)) / (x2 - x1));
1102 }
1103
1104 static u8 ar9170_interpolate_u8(u8 x, u8 x1, u8 y1, u8 x2, u8 y2)
1105 {
1106 #define SHIFT 8
1107 s32 y;
1108
1109 y = ar9170_interpolate_s32(x << SHIFT,
1110 x1 << SHIFT, y1 << SHIFT,
1111 x2 << SHIFT, y2 << SHIFT);
1112
1113 /*
1114 * XXX: unwrap this expression
1115 * Isn't it just DIV_ROUND_UP(y, 1<<SHIFT)?
1116 * Can we rely on the compiler to optimise away the div?
1117 */
1118 return (y >> SHIFT) + ((y & (1<<(SHIFT-1))) >> (SHIFT - 1));
1119 #undef SHIFT
1120 }
1121
1122 static u8 ar9170_interpolate_val(u8 x, u8 *x_array, u8 *y_array)
1123 {
1124 int i;
1125
1126 for (i = 0; i < 3; i++)
1127 if (x <= x_array[i + 1])
1128 break;
1129
1130 return ar9170_interpolate_u8(x,
1131 x_array[i],
1132 y_array[i],
1133 x_array[i + 1],
1134 y_array[i + 1]);
1135 }
1136
1137 static int ar9170_set_freq_cal_data(struct ar9170 *ar,
1138 struct ieee80211_channel *channel)
1139 {
1140 u8 *cal_freq_pier;
1141 u8 vpds[2][AR5416_PD_GAIN_ICEPTS];
1142 u8 pwrs[2][AR5416_PD_GAIN_ICEPTS];
1143 int chain, idx, i;
1144 u32 phy_data = 0;
1145 u8 f, tmp;
1146
1147 switch (channel->band) {
1148 case IEEE80211_BAND_2GHZ:
1149 f = channel->center_freq - 2300;
1150 cal_freq_pier = ar->eeprom.cal_freq_pier_2G;
1151 i = AR5416_NUM_2G_CAL_PIERS - 1;
1152 break;
1153
1154 case IEEE80211_BAND_5GHZ:
1155 f = (channel->center_freq - 4800) / 5;
1156 cal_freq_pier = ar->eeprom.cal_freq_pier_5G;
1157 i = AR5416_NUM_5G_CAL_PIERS - 1;
1158 break;
1159
1160 default:
1161 return -EINVAL;
1162 break;
1163 }
1164
1165 for (; i >= 0; i--) {
1166 if (cal_freq_pier[i] != 0xff)
1167 break;
1168 }
1169 if (i < 0)
1170 return -EINVAL;
1171
1172 idx = ar9170_find_freq_idx(i, cal_freq_pier, f);
1173
1174 ar9170_regwrite_begin(ar);
1175
1176 for (chain = 0; chain < AR5416_MAX_CHAINS; chain++) {
1177 for (i = 0; i < AR5416_PD_GAIN_ICEPTS; i++) {
1178 struct ar9170_calibration_data_per_freq *cal_pier_data;
1179 int j;
1180
1181 switch (channel->band) {
1182 case IEEE80211_BAND_2GHZ:
1183 cal_pier_data = &ar->eeprom.
1184 cal_pier_data_2G[chain][idx];
1185 break;
1186
1187 case IEEE80211_BAND_5GHZ:
1188 cal_pier_data = &ar->eeprom.
1189 cal_pier_data_5G[chain][idx];
1190 break;
1191
1192 default:
1193 return -EINVAL;
1194 }
1195
1196 for (j = 0; j < 2; j++) {
1197 vpds[j][i] = ar9170_interpolate_u8(f,
1198 cal_freq_pier[idx],
1199 cal_pier_data->vpd_pdg[j][i],
1200 cal_freq_pier[idx + 1],
1201 cal_pier_data[1].vpd_pdg[j][i]);
1202
1203 pwrs[j][i] = ar9170_interpolate_u8(f,
1204 cal_freq_pier[idx],
1205 cal_pier_data->pwr_pdg[j][i],
1206 cal_freq_pier[idx + 1],
1207 cal_pier_data[1].pwr_pdg[j][i]) / 2;
1208 }
1209 }
1210
1211 for (i = 0; i < 76; i++) {
1212 if (i < 25) {
1213 tmp = ar9170_interpolate_val(i, &pwrs[0][0],
1214 &vpds[0][0]);
1215 } else {
1216 tmp = ar9170_interpolate_val(i - 12,
1217 &pwrs[1][0],
1218 &vpds[1][0]);
1219 }
1220
1221 phy_data |= tmp << ((i & 3) << 3);
1222 if ((i & 3) == 3) {
1223 ar9170_regwrite(0x1c6280 + chain * 0x1000 +
1224 (i & ~3), phy_data);
1225 phy_data = 0;
1226 }
1227 }
1228
1229 for (i = 19; i < 32; i++)
1230 ar9170_regwrite(0x1c6280 + chain * 0x1000 + (i << 2),
1231 0x0);
1232 }
1233
1234 ar9170_regwrite_finish();
1235 return ar9170_regwrite_result();
1236 }
1237
1238 static u8 ar9170_get_max_edge_power(struct ar9170 *ar,
1239 struct ar9170_calctl_edges edges[],
1240 u32 freq)
1241 {
1242 int i;
1243 u8 rc = AR5416_MAX_RATE_POWER;
1244 u8 f;
1245 if (freq < 3000)
1246 f = freq - 2300;
1247 else
1248 f = (freq - 4800) / 5;
1249
1250 for (i = 0; i < AR5416_NUM_BAND_EDGES; i++) {
1251 if (edges[i].channel == 0xff)
1252 break;
1253 if (f == edges[i].channel) {
1254 /* exact freq match */
1255 rc = edges[i].power_flags & ~AR9170_CALCTL_EDGE_FLAGS;
1256 break;
1257 }
1258 if (i > 0 && f < edges[i].channel) {
1259 if (f > edges[i - 1].channel &&
1260 edges[i - 1].power_flags &
1261 AR9170_CALCTL_EDGE_FLAGS) {
1262 /* lower channel has the inband flag set */
1263 rc = edges[i - 1].power_flags &
1264 ~AR9170_CALCTL_EDGE_FLAGS;
1265 }
1266 break;
1267 }
1268 }
1269
1270 if (i == AR5416_NUM_BAND_EDGES) {
1271 if (f > edges[i - 1].channel &&
1272 edges[i - 1].power_flags & AR9170_CALCTL_EDGE_FLAGS) {
1273 /* lower channel has the inband flag set */
1274 rc = edges[i - 1].power_flags &
1275 ~AR9170_CALCTL_EDGE_FLAGS;
1276 }
1277 }
1278 return rc;
1279 }
1280
1281 static u8 ar9170_get_heavy_clip(struct ar9170 *ar,
1282 struct ar9170_calctl_edges edges[],
1283 u32 freq, enum ar9170_bw bw)
1284 {
1285 u8 f;
1286 int i;
1287 u8 rc = 0;
1288
1289 if (freq < 3000)
1290 f = freq - 2300;
1291 else
1292 f = (freq - 4800) / 5;
1293
1294 if (bw == AR9170_BW_40_BELOW || bw == AR9170_BW_40_ABOVE)
1295 rc |= 0xf0;
1296
1297 for (i = 0; i < AR5416_NUM_BAND_EDGES; i++) {
1298 if (edges[i].channel == 0xff)
1299 break;
1300 if (f == edges[i].channel) {
1301 if (!(edges[i].power_flags & AR9170_CALCTL_EDGE_FLAGS))
1302 rc |= 0x0f;
1303 break;
1304 }
1305 }
1306
1307 return rc;
1308 }
1309
1310 /*
1311 * calculate the conformance test limits and the heavy clip parameter
1312 * and apply them to ar->power* (derived from otus hal/hpmain.c, line 3706)
1313 */
1314 static void ar9170_calc_ctl(struct ar9170 *ar, u32 freq, enum ar9170_bw bw)
1315 {
1316 u8 ctl_grp; /* CTL group */
1317 u8 ctl_idx; /* CTL index */
1318 int i, j;
1319 struct ctl_modes {
1320 u8 ctl_mode;
1321 u8 max_power;
1322 u8 *pwr_cal_data;
1323 int pwr_cal_len;
1324 } *modes;
1325
1326 /*
1327 * order is relevant in the mode_list_*: we fall back to the
1328 * lower indices if any mode is missed in the EEPROM.
1329 */
1330 struct ctl_modes mode_list_2ghz[] = {
1331 { CTL_11B, 0, ar->power_2G_cck, 4 },
1332 { CTL_11G, 0, ar->power_2G_ofdm, 4 },
1333 { CTL_2GHT20, 0, ar->power_2G_ht20, 8 },
1334 { CTL_2GHT40, 0, ar->power_2G_ht40, 8 },
1335 };
1336 struct ctl_modes mode_list_5ghz[] = {
1337 { CTL_11A, 0, ar->power_5G_leg, 4 },
1338 { CTL_5GHT20, 0, ar->power_5G_ht20, 8 },
1339 { CTL_5GHT40, 0, ar->power_5G_ht40, 8 },
1340 };
1341 int nr_modes;
1342
1343 #define EDGES(c, n) (ar->eeprom.ctl_data[c].control_edges[n])
1344
1345 ar->phy_heavy_clip = 0;
1346
1347 /*
1348 * TODO: investigate the differences between OTUS'
1349 * hpreg.c::zfHpGetRegulatoryDomain() and
1350 * ath/regd.c::ath_regd_get_band_ctl() -
1351 * e.g. for FCC3_WORLD the OTUS procedure
1352 * always returns CTL_FCC, while the one in ath/ delivers
1353 * CTL_ETSI for 2GHz and CTL_FCC for 5GHz.
1354 */
1355 ctl_grp = ath_regd_get_band_ctl(&ar->common.regulatory,
1356 ar->hw->conf.channel->band);
1357
1358 /* ctl group not found - either invalid band (NO_CTL) or ww roaming */
1359 if (ctl_grp == NO_CTL || ctl_grp == SD_NO_CTL)
1360 ctl_grp = CTL_FCC;
1361
1362 if (ctl_grp != CTL_FCC)
1363 /* skip CTL and heavy clip for CTL_MKK and CTL_ETSI */
1364 return;
1365
1366 if (ar->hw->conf.channel->band == IEEE80211_BAND_2GHZ) {
1367 modes = mode_list_2ghz;
1368 nr_modes = ARRAY_SIZE(mode_list_2ghz);
1369 } else {
1370 modes = mode_list_5ghz;
1371 nr_modes = ARRAY_SIZE(mode_list_5ghz);
1372 }
1373
1374 for (i = 0; i < nr_modes; i++) {
1375 u8 c = ctl_grp | modes[i].ctl_mode;
1376 for (ctl_idx = 0; ctl_idx < AR5416_NUM_CTLS; ctl_idx++)
1377 if (c == ar->eeprom.ctl_index[ctl_idx])
1378 break;
1379 if (ctl_idx < AR5416_NUM_CTLS) {
1380 int f_off = 0;
1381
1382 /* determine heav clip parameter from
1383 the 11G edges array */
1384 if (modes[i].ctl_mode == CTL_11G) {
1385 ar->phy_heavy_clip =
1386 ar9170_get_heavy_clip(ar,
1387 EDGES(ctl_idx, 1),
1388 freq, bw);
1389 }
1390
1391 /* adjust freq for 40MHz */
1392 if (modes[i].ctl_mode == CTL_2GHT40 ||
1393 modes[i].ctl_mode == CTL_5GHT40) {
1394 if (bw == AR9170_BW_40_BELOW)
1395 f_off = -10;
1396 else
1397 f_off = 10;
1398 }
1399
1400 modes[i].max_power =
1401 ar9170_get_max_edge_power(ar, EDGES(ctl_idx, 1),
1402 freq+f_off);
1403
1404 /*
1405 * TODO: check if the regulatory max. power is
1406 * controlled by cfg80211 for DFS
1407 * (hpmain applies it to max_power itself for DFS freq)
1408 */
1409
1410 } else {
1411 /*
1412 * Workaround in otus driver, hpmain.c, line 3906:
1413 * if no data for 5GHT20 are found, take the
1414 * legacy 5G value.
1415 * We extend this here to fallback from any other *HT or
1416 * 11G, too.
1417 */
1418 int k = i;
1419
1420 modes[i].max_power = AR5416_MAX_RATE_POWER;
1421 while (k-- > 0) {
1422 if (modes[k].max_power !=
1423 AR5416_MAX_RATE_POWER) {
1424 modes[i].max_power = modes[k].max_power;
1425 break;
1426 }
1427 }
1428 }
1429
1430 /* apply max power to pwr_cal_data (ar->power_*) */
1431 for (j = 0; j < modes[i].pwr_cal_len; j++) {
1432 modes[i].pwr_cal_data[j] = min(modes[i].pwr_cal_data[j],
1433 modes[i].max_power);
1434 }
1435 }
1436
1437 if (ar->phy_heavy_clip & 0xf0) {
1438 ar->power_2G_ht40[0]--;
1439 ar->power_2G_ht40[1]--;
1440 ar->power_2G_ht40[2]--;
1441 }
1442 if (ar->phy_heavy_clip & 0xf) {
1443 ar->power_2G_ht20[0]++;
1444 ar->power_2G_ht20[1]++;
1445 ar->power_2G_ht20[2]++;
1446 }
1447
1448
1449 #undef EDGES
1450 }
1451
1452 static int ar9170_set_power_cal(struct ar9170 *ar, u32 freq, enum ar9170_bw bw)
1453 {
1454 struct ar9170_calibration_target_power_legacy *ctpl;
1455 struct ar9170_calibration_target_power_ht *ctph;
1456 u8 *ctpres;
1457 int ntargets;
1458 int idx, i, n;
1459 u8 ackpower, ackchains, f;
1460 u8 pwr_freqs[AR5416_MAX_NUM_TGT_PWRS];
1461
1462 if (freq < 3000)
1463 f = freq - 2300;
1464 else
1465 f = (freq - 4800)/5;
1466
1467 /*
1468 * cycle through the various modes
1469 *
1470 * legacy modes first: 5G, 2G CCK, 2G OFDM
1471 */
1472 for (i = 0; i < 3; i++) {
1473 switch (i) {
1474 case 0: /* 5 GHz legacy */
1475 ctpl = &ar->eeprom.cal_tgt_pwr_5G[0];
1476 ntargets = AR5416_NUM_5G_TARGET_PWRS;
1477 ctpres = ar->power_5G_leg;
1478 break;
1479 case 1: /* 2.4 GHz CCK */
1480 ctpl = &ar->eeprom.cal_tgt_pwr_2G_cck[0];
1481 ntargets = AR5416_NUM_2G_CCK_TARGET_PWRS;
1482 ctpres = ar->power_2G_cck;
1483 break;
1484 case 2: /* 2.4 GHz OFDM */
1485 ctpl = &ar->eeprom.cal_tgt_pwr_2G_ofdm[0];
1486 ntargets = AR5416_NUM_2G_OFDM_TARGET_PWRS;
1487 ctpres = ar->power_2G_ofdm;
1488 break;
1489 default:
1490 BUG();
1491 }
1492
1493 for (n = 0; n < ntargets; n++) {
1494 if (ctpl[n].freq == 0xff)
1495 break;
1496 pwr_freqs[n] = ctpl[n].freq;
1497 }
1498 ntargets = n;
1499 idx = ar9170_find_freq_idx(ntargets, pwr_freqs, f);
1500 for (n = 0; n < 4; n++)
1501 ctpres[n] = ar9170_interpolate_u8(
1502 f,
1503 ctpl[idx + 0].freq,
1504 ctpl[idx + 0].power[n],
1505 ctpl[idx + 1].freq,
1506 ctpl[idx + 1].power[n]);
1507 }
1508
1509 /*
1510 * HT modes now: 5G HT20, 5G HT40, 2G CCK, 2G OFDM, 2G HT20, 2G HT40
1511 */
1512 for (i = 0; i < 4; i++) {
1513 switch (i) {
1514 case 0: /* 5 GHz HT 20 */
1515 ctph = &ar->eeprom.cal_tgt_pwr_5G_ht20[0];
1516 ntargets = AR5416_NUM_5G_TARGET_PWRS;
1517 ctpres = ar->power_5G_ht20;
1518 break;
1519 case 1: /* 5 GHz HT 40 */
1520 ctph = &ar->eeprom.cal_tgt_pwr_5G_ht40[0];
1521 ntargets = AR5416_NUM_5G_TARGET_PWRS;
1522 ctpres = ar->power_5G_ht40;
1523 break;
1524 case 2: /* 2.4 GHz HT 20 */
1525 ctph = &ar->eeprom.cal_tgt_pwr_2G_ht20[0];
1526 ntargets = AR5416_NUM_2G_OFDM_TARGET_PWRS;
1527 ctpres = ar->power_2G_ht20;
1528 break;
1529 case 3: /* 2.4 GHz HT 40 */
1530 ctph = &ar->eeprom.cal_tgt_pwr_2G_ht40[0];
1531 ntargets = AR5416_NUM_2G_OFDM_TARGET_PWRS;
1532 ctpres = ar->power_2G_ht40;
1533 break;
1534 default:
1535 BUG();
1536 }
1537
1538 for (n = 0; n < ntargets; n++) {
1539 if (ctph[n].freq == 0xff)
1540 break;
1541 pwr_freqs[n] = ctph[n].freq;
1542 }
1543 ntargets = n;
1544 idx = ar9170_find_freq_idx(ntargets, pwr_freqs, f);
1545 for (n = 0; n < 8; n++)
1546 ctpres[n] = ar9170_interpolate_u8(
1547 f,
1548 ctph[idx + 0].freq,
1549 ctph[idx + 0].power[n],
1550 ctph[idx + 1].freq,
1551 ctph[idx + 1].power[n]);
1552 }
1553
1554
1555 /* calc. conformance test limits and apply to ar->power*[] */
1556 ar9170_calc_ctl(ar, freq, bw);
1557
1558 /* set ACK/CTS TX power */
1559 ar9170_regwrite_begin(ar);
1560
1561 if (ar->eeprom.tx_mask != 1)
1562 ackchains = AR9170_TX_PHY_TXCHAIN_2;
1563 else
1564 ackchains = AR9170_TX_PHY_TXCHAIN_1;
1565
1566 if (freq < 3000)
1567 ackpower = ar->power_2G_ofdm[0] & 0x3f;
1568 else
1569 ackpower = ar->power_5G_leg[0] & 0x3f;
1570
1571 ar9170_regwrite(0x1c3694, ackpower << 20 | ackchains << 26);
1572 ar9170_regwrite(0x1c3bb4, ackpower << 5 | ackchains << 11 |
1573 ackpower << 21 | ackchains << 27);
1574
1575 ar9170_regwrite_finish();
1576 return ar9170_regwrite_result();
1577 }
1578
1579 static int ar9170_calc_noise_dbm(u32 raw_noise)
1580 {
1581 if (raw_noise & 0x100)
1582 return ~((raw_noise & 0x0ff) >> 1);
1583 else
1584 return (raw_noise & 0xff) >> 1;
1585 }
1586
1587 int ar9170_set_channel(struct ar9170 *ar, struct ieee80211_channel *channel,
1588 enum ar9170_rf_init_mode rfi, enum ar9170_bw bw)
1589 {
1590 const struct ar9170_phy_freq_params *freqpar;
1591 u32 cmd, tmp, offs;
1592 __le32 vals[8];
1593 int i, err;
1594 bool bandswitch;
1595
1596 /* clear BB heavy clip enable */
1597 err = ar9170_write_reg(ar, 0x1c59e0, 0x200);
1598 if (err)
1599 return err;
1600
1601 /* may be NULL at first setup */
1602 if (ar->channel)
1603 bandswitch = ar->channel->band != channel->band;
1604 else
1605 bandswitch = true;
1606
1607 /* HW workaround */
1608 if (!ar->hw->wiphy->bands[IEEE80211_BAND_5GHZ] &&
1609 channel->center_freq <= 2417)
1610 bandswitch = true;
1611
1612 err = ar->exec_cmd(ar, AR9170_CMD_FREQ_START, 0, NULL, 0, NULL);
1613 if (err)
1614 return err;
1615
1616 if (rfi != AR9170_RFI_NONE || bandswitch) {
1617 u32 val = 0x400;
1618
1619 if (rfi == AR9170_RFI_COLD)
1620 val = 0x800;
1621
1622 /* warm/cold reset BB/ADDA */
1623 err = ar9170_write_reg(ar, 0x1d4004, val);
1624 if (err)
1625 return err;
1626
1627 err = ar9170_write_reg(ar, 0x1d4004, 0x0);
1628 if (err)
1629 return err;
1630
1631 err = ar9170_init_phy(ar, channel->band);
1632 if (err)
1633 return err;
1634
1635 err = ar9170_init_rf_banks_0_7(ar,
1636 channel->band == IEEE80211_BAND_5GHZ);
1637 if (err)
1638 return err;
1639
1640 cmd = AR9170_CMD_RF_INIT;
1641 } else {
1642 cmd = AR9170_CMD_FREQUENCY;
1643 }
1644
1645 err = ar9170_init_rf_bank4_pwr(ar,
1646 channel->band == IEEE80211_BAND_5GHZ,
1647 channel->center_freq, bw);
1648 if (err)
1649 return err;
1650
1651 switch (bw) {
1652 case AR9170_BW_20:
1653 tmp = 0x240;
1654 offs = 0;
1655 break;
1656 case AR9170_BW_40_BELOW:
1657 tmp = 0x2c4;
1658 offs = 3;
1659 break;
1660 case AR9170_BW_40_ABOVE:
1661 tmp = 0x2d4;
1662 offs = 1;
1663 break;
1664 default:
1665 BUG();
1666 return -ENOSYS;
1667 }
1668
1669 if (ar->eeprom.tx_mask != 1)
1670 tmp |= 0x100;
1671
1672 err = ar9170_write_reg(ar, 0x1c5804, tmp);
1673 if (err)
1674 return err;
1675
1676 err = ar9170_set_freq_cal_data(ar, channel);
1677 if (err)
1678 return err;
1679
1680 err = ar9170_set_power_cal(ar, channel->center_freq, bw);
1681 if (err)
1682 return err;
1683
1684 freqpar = ar9170_get_hw_dyn_params(channel, bw);
1685
1686 vals[0] = cpu_to_le32(channel->center_freq * 1000);
1687 vals[1] = cpu_to_le32(conf_is_ht40(&ar->hw->conf));
1688 vals[2] = cpu_to_le32(offs << 2 | 1);
1689 vals[3] = cpu_to_le32(freqpar->coeff_exp);
1690 vals[4] = cpu_to_le32(freqpar->coeff_man);
1691 vals[5] = cpu_to_le32(freqpar->coeff_exp_shgi);
1692 vals[6] = cpu_to_le32(freqpar->coeff_man_shgi);
1693 vals[7] = cpu_to_le32(1000);
1694
1695 err = ar->exec_cmd(ar, cmd, sizeof(vals), (u8 *)vals,
1696 sizeof(vals), (u8 *)vals);
1697 if (err)
1698 return err;
1699
1700 if (ar->phy_heavy_clip) {
1701 err = ar9170_write_reg(ar, 0x1c59e0,
1702 0x200 | ar->phy_heavy_clip);
1703 if (err) {
1704 if (ar9170_nag_limiter(ar))
1705 printk(KERN_ERR "%s: failed to set "
1706 "heavy clip\n",
1707 wiphy_name(ar->hw->wiphy));
1708 }
1709 }
1710
1711 for (i = 0; i < 2; i++) {
1712 ar->noise[i] = ar9170_calc_noise_dbm(
1713 (le32_to_cpu(vals[2 + i]) >> 19) & 0x1ff);
1714
1715 ar->noise[i + 2] = ar9170_calc_noise_dbm(
1716 (le32_to_cpu(vals[5 + i]) >> 23) & 0x1ff);
1717 }
1718
1719 ar->channel = channel;
1720 return 0;
1721 }
Linux kernel - Deliverables
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