2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 #include <linux/bug.h>
22 #include <linux/interrupt.h>
23 #include <linux/dmapool.h>
24 #include <linux/hashtable.h>
25 #include <linux/kfifo.h>
26 #include <net/mac80211.h>
33 enum htt_dbg_stats_type
{
34 HTT_DBG_STATS_WAL_PDEV_TXRX
= 1 << 0,
35 HTT_DBG_STATS_RX_REORDER
= 1 << 1,
36 HTT_DBG_STATS_RX_RATE_INFO
= 1 << 2,
37 HTT_DBG_STATS_TX_PPDU_LOG
= 1 << 3,
38 HTT_DBG_STATS_TX_RATE_INFO
= 1 << 4,
39 /* bits 5-23 currently reserved */
41 HTT_DBG_NUM_STATS
/* keep this last */
44 enum htt_h2t_msg_type
{ /* host-to-target */
45 HTT_H2T_MSG_TYPE_VERSION_REQ
= 0,
46 HTT_H2T_MSG_TYPE_TX_FRM
= 1,
47 HTT_H2T_MSG_TYPE_RX_RING_CFG
= 2,
48 HTT_H2T_MSG_TYPE_STATS_REQ
= 3,
49 HTT_H2T_MSG_TYPE_SYNC
= 4,
50 HTT_H2T_MSG_TYPE_AGGR_CFG
= 5,
51 HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG
= 6,
53 /* This command is used for sending management frames in HTT < 3.0.
54 * HTT >= 3.0 uses TX_FRM for everything. */
55 HTT_H2T_MSG_TYPE_MGMT_TX
= 7,
56 HTT_H2T_MSG_TYPE_TX_FETCH_RESP
= 11,
58 HTT_H2T_NUM_MSGS
/* keep this last */
66 u8 pad
[sizeof(u32
) - sizeof(struct htt_cmd_hdr
)];
70 * HTT tx MSDU descriptor
72 * The HTT tx MSDU descriptor is created by the host HTT SW for each
73 * tx MSDU. The HTT tx MSDU descriptor contains the information that
74 * the target firmware needs for the FW's tx processing, particularly
75 * for creating the HW msdu descriptor.
76 * The same HTT tx descriptor is used for HL and LL systems, though
77 * a few fields within the tx descriptor are used only by LL or
79 * The HTT tx descriptor is defined in two manners: by a struct with
80 * bitfields, and by a series of [dword offset, bit mask, bit shift]
82 * The target should use the struct def, for simplicitly and clarity,
83 * but the host shall use the bit-mast + bit-shift defs, to be endian-
84 * neutral. Specifically, the host shall use the get/set macros built
85 * around the mask + shift defs.
87 struct htt_data_tx_desc_frag
{
89 struct double_word_addr
{
92 } __packed dword_addr
;
93 struct triple_word_addr
{
97 } __packed tword_addr
;
101 struct htt_msdu_ext_desc
{
103 __le16 ip_identification
;
106 struct htt_data_tx_desc_frag frags
[6];
109 #define HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE BIT(0)
110 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE BIT(1)
111 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE BIT(2)
112 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE BIT(3)
113 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE BIT(4)
115 #define HTT_MSDU_CHECKSUM_ENABLE (HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE \
116 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE \
117 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE \
118 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE \
119 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE)
121 enum htt_data_tx_desc_flags0
{
122 HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT
= 1 << 0,
123 HTT_DATA_TX_DESC_FLAGS0_NO_AGGR
= 1 << 1,
124 HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT
= 1 << 2,
125 HTT_DATA_TX_DESC_FLAGS0_NO_CLASSIFY
= 1 << 3,
126 HTT_DATA_TX_DESC_FLAGS0_RSVD0
= 1 << 4
127 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_MASK 0xE0
128 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_LSB 5
131 enum htt_data_tx_desc_flags1
{
132 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_BITS 6
133 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_MASK 0x003F
134 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_LSB 0
135 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_BITS 5
136 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_MASK 0x07C0
137 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_LSB 6
138 HTT_DATA_TX_DESC_FLAGS1_POSTPONED
= 1 << 11,
139 HTT_DATA_TX_DESC_FLAGS1_MORE_IN_BATCH
= 1 << 12,
140 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD
= 1 << 13,
141 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD
= 1 << 14,
142 HTT_DATA_TX_DESC_FLAGS1_RSVD1
= 1 << 15
145 enum htt_data_tx_ext_tid
{
146 HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST
= 16,
147 HTT_DATA_TX_EXT_TID_MGMT
= 17,
148 HTT_DATA_TX_EXT_TID_INVALID
= 31
151 #define HTT_INVALID_PEERID 0xFFFF
154 * htt_data_tx_desc - used for data tx path
156 * Note: vdev_id irrelevant for pkt_type == raw and no_classify == 1.
157 * ext_tid: for qos-data frames (0-15), see %HTT_DATA_TX_EXT_TID_
158 * for special kinds of tids
159 * postponed: only for HL hosts. indicates if this is a resend
160 * (HL hosts manage queues on the host )
161 * more_in_batch: only for HL hosts. indicates if more packets are
162 * pending. this allows target to wait and aggregate
163 * freq: 0 means home channel of given vdev. intended for offchannel
165 struct htt_data_tx_desc
{
166 u8 flags0
; /* %HTT_DATA_TX_DESC_FLAGS0_ */
167 __le16 flags1
; /* %HTT_DATA_TX_DESC_FLAGS1_ */
176 } __packed offchan_tx
;
178 u8 prefetch
[0]; /* start of frame, for FW classification engine */
181 enum htt_rx_ring_flags
{
182 HTT_RX_RING_FLAGS_MAC80211_HDR
= 1 << 0,
183 HTT_RX_RING_FLAGS_MSDU_PAYLOAD
= 1 << 1,
184 HTT_RX_RING_FLAGS_PPDU_START
= 1 << 2,
185 HTT_RX_RING_FLAGS_PPDU_END
= 1 << 3,
186 HTT_RX_RING_FLAGS_MPDU_START
= 1 << 4,
187 HTT_RX_RING_FLAGS_MPDU_END
= 1 << 5,
188 HTT_RX_RING_FLAGS_MSDU_START
= 1 << 6,
189 HTT_RX_RING_FLAGS_MSDU_END
= 1 << 7,
190 HTT_RX_RING_FLAGS_RX_ATTENTION
= 1 << 8,
191 HTT_RX_RING_FLAGS_FRAG_INFO
= 1 << 9,
192 HTT_RX_RING_FLAGS_UNICAST_RX
= 1 << 10,
193 HTT_RX_RING_FLAGS_MULTICAST_RX
= 1 << 11,
194 HTT_RX_RING_FLAGS_CTRL_RX
= 1 << 12,
195 HTT_RX_RING_FLAGS_MGMT_RX
= 1 << 13,
196 HTT_RX_RING_FLAGS_NULL_RX
= 1 << 14,
197 HTT_RX_RING_FLAGS_PHY_DATA_RX
= 1 << 15
200 #define HTT_RX_RING_SIZE_MIN 128
201 #define HTT_RX_RING_SIZE_MAX 2048
203 struct htt_rx_ring_setup_ring
{
204 __le32 fw_idx_shadow_reg_paddr
;
205 __le32 rx_ring_base_paddr
;
206 __le16 rx_ring_len
; /* in 4-byte words */
207 __le16 rx_ring_bufsize
; /* rx skb size - in bytes */
208 __le16 flags
; /* %HTT_RX_RING_FLAGS_ */
209 __le16 fw_idx_init_val
;
211 /* the following offsets are in 4-byte units */
212 __le16 mac80211_hdr_offset
;
213 __le16 msdu_payload_offset
;
214 __le16 ppdu_start_offset
;
215 __le16 ppdu_end_offset
;
216 __le16 mpdu_start_offset
;
217 __le16 mpdu_end_offset
;
218 __le16 msdu_start_offset
;
219 __le16 msdu_end_offset
;
220 __le16 rx_attention_offset
;
221 __le16 frag_info_offset
;
224 struct htt_rx_ring_setup_hdr
{
225 u8 num_rings
; /* supported values: 1, 2 */
229 struct htt_rx_ring_setup
{
230 struct htt_rx_ring_setup_hdr hdr
;
231 struct htt_rx_ring_setup_ring rings
[0];
235 * htt_stats_req - request target to send specified statistics
237 * @msg_type: hardcoded %HTT_H2T_MSG_TYPE_STATS_REQ
238 * @upload_types: see %htt_dbg_stats_type. this is 24bit field actually
239 * so make sure its little-endian.
240 * @reset_types: see %htt_dbg_stats_type. this is 24bit field actually
241 * so make sure its little-endian.
242 * @cfg_val: stat_type specific configuration
243 * @stat_type: see %htt_dbg_stats_type
244 * @cookie_lsb: used for confirmation message from target->host
245 * @cookie_msb: ditto as %cookie
247 struct htt_stats_req
{
261 #define HTT_STATS_REQ_CFG_STAT_TYPE_INVALID 0xff
264 * htt_oob_sync_req - request out-of-band sync
266 * The HTT SYNC tells the target to suspend processing of subsequent
267 * HTT host-to-target messages until some other target agent locally
268 * informs the target HTT FW that the current sync counter is equal to
269 * or greater than (in a modulo sense) the sync counter specified in
272 * This allows other host-target components to synchronize their operation
273 * with HTT, e.g. to ensure that tx frames don't get transmitted until a
274 * security key has been downloaded to and activated by the target.
275 * In the absence of any explicit synchronization counter value
276 * specification, the target HTT FW will use zero as the default current
279 * The HTT target FW will suspend its host->target message processing as long
280 * as 0 < (in-band sync counter - out-of-band sync counter) & 0xff < 128.
282 struct htt_oob_sync_req
{
287 struct htt_aggr_conf
{
288 u8 max_num_ampdu_subframes
;
289 /* amsdu_subframes is limited by 0x1F mask */
290 u8 max_num_amsdu_subframes
;
293 #define HTT_MGMT_FRM_HDR_DOWNLOAD_LEN 32
294 struct htt_mgmt_tx_desc_qca99x0
{
298 struct htt_mgmt_tx_desc
{
299 u8 pad
[sizeof(u32
) - sizeof(struct htt_cmd_hdr
)];
304 u8 hdr
[HTT_MGMT_FRM_HDR_DOWNLOAD_LEN
];
306 struct htt_mgmt_tx_desc_qca99x0 qca99x0
;
310 enum htt_mgmt_tx_status
{
311 HTT_MGMT_TX_STATUS_OK
= 0,
312 HTT_MGMT_TX_STATUS_RETRY
= 1,
313 HTT_MGMT_TX_STATUS_DROP
= 2
316 /*=== target -> host messages ===============================================*/
318 enum htt_main_t2h_msg_type
{
319 HTT_MAIN_T2H_MSG_TYPE_VERSION_CONF
= 0x0,
320 HTT_MAIN_T2H_MSG_TYPE_RX_IND
= 0x1,
321 HTT_MAIN_T2H_MSG_TYPE_RX_FLUSH
= 0x2,
322 HTT_MAIN_T2H_MSG_TYPE_PEER_MAP
= 0x3,
323 HTT_MAIN_T2H_MSG_TYPE_PEER_UNMAP
= 0x4,
324 HTT_MAIN_T2H_MSG_TYPE_RX_ADDBA
= 0x5,
325 HTT_MAIN_T2H_MSG_TYPE_RX_DELBA
= 0x6,
326 HTT_MAIN_T2H_MSG_TYPE_TX_COMPL_IND
= 0x7,
327 HTT_MAIN_T2H_MSG_TYPE_PKTLOG
= 0x8,
328 HTT_MAIN_T2H_MSG_TYPE_STATS_CONF
= 0x9,
329 HTT_MAIN_T2H_MSG_TYPE_RX_FRAG_IND
= 0xa,
330 HTT_MAIN_T2H_MSG_TYPE_SEC_IND
= 0xb,
331 HTT_MAIN_T2H_MSG_TYPE_TX_INSPECT_IND
= 0xd,
332 HTT_MAIN_T2H_MSG_TYPE_MGMT_TX_COMPL_IND
= 0xe,
333 HTT_MAIN_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND
= 0xf,
334 HTT_MAIN_T2H_MSG_TYPE_RX_PN_IND
= 0x10,
335 HTT_MAIN_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND
= 0x11,
336 HTT_MAIN_T2H_MSG_TYPE_TEST
,
338 HTT_MAIN_T2H_NUM_MSGS
341 enum htt_10x_t2h_msg_type
{
342 HTT_10X_T2H_MSG_TYPE_VERSION_CONF
= 0x0,
343 HTT_10X_T2H_MSG_TYPE_RX_IND
= 0x1,
344 HTT_10X_T2H_MSG_TYPE_RX_FLUSH
= 0x2,
345 HTT_10X_T2H_MSG_TYPE_PEER_MAP
= 0x3,
346 HTT_10X_T2H_MSG_TYPE_PEER_UNMAP
= 0x4,
347 HTT_10X_T2H_MSG_TYPE_RX_ADDBA
= 0x5,
348 HTT_10X_T2H_MSG_TYPE_RX_DELBA
= 0x6,
349 HTT_10X_T2H_MSG_TYPE_TX_COMPL_IND
= 0x7,
350 HTT_10X_T2H_MSG_TYPE_PKTLOG
= 0x8,
351 HTT_10X_T2H_MSG_TYPE_STATS_CONF
= 0x9,
352 HTT_10X_T2H_MSG_TYPE_RX_FRAG_IND
= 0xa,
353 HTT_10X_T2H_MSG_TYPE_SEC_IND
= 0xb,
354 HTT_10X_T2H_MSG_TYPE_RC_UPDATE_IND
= 0xc,
355 HTT_10X_T2H_MSG_TYPE_TX_INSPECT_IND
= 0xd,
356 HTT_10X_T2H_MSG_TYPE_TEST
= 0xe,
357 HTT_10X_T2H_MSG_TYPE_CHAN_CHANGE
= 0xf,
358 HTT_10X_T2H_MSG_TYPE_AGGR_CONF
= 0x11,
359 HTT_10X_T2H_MSG_TYPE_STATS_NOUPLOAD
= 0x12,
360 HTT_10X_T2H_MSG_TYPE_MGMT_TX_COMPL_IND
= 0x13,
365 enum htt_tlv_t2h_msg_type
{
366 HTT_TLV_T2H_MSG_TYPE_VERSION_CONF
= 0x0,
367 HTT_TLV_T2H_MSG_TYPE_RX_IND
= 0x1,
368 HTT_TLV_T2H_MSG_TYPE_RX_FLUSH
= 0x2,
369 HTT_TLV_T2H_MSG_TYPE_PEER_MAP
= 0x3,
370 HTT_TLV_T2H_MSG_TYPE_PEER_UNMAP
= 0x4,
371 HTT_TLV_T2H_MSG_TYPE_RX_ADDBA
= 0x5,
372 HTT_TLV_T2H_MSG_TYPE_RX_DELBA
= 0x6,
373 HTT_TLV_T2H_MSG_TYPE_TX_COMPL_IND
= 0x7,
374 HTT_TLV_T2H_MSG_TYPE_PKTLOG
= 0x8,
375 HTT_TLV_T2H_MSG_TYPE_STATS_CONF
= 0x9,
376 HTT_TLV_T2H_MSG_TYPE_RX_FRAG_IND
= 0xa,
377 HTT_TLV_T2H_MSG_TYPE_SEC_IND
= 0xb,
378 HTT_TLV_T2H_MSG_TYPE_RC_UPDATE_IND
= 0xc, /* deprecated */
379 HTT_TLV_T2H_MSG_TYPE_TX_INSPECT_IND
= 0xd,
380 HTT_TLV_T2H_MSG_TYPE_MGMT_TX_COMPL_IND
= 0xe,
381 HTT_TLV_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND
= 0xf,
382 HTT_TLV_T2H_MSG_TYPE_RX_PN_IND
= 0x10,
383 HTT_TLV_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND
= 0x11,
384 HTT_TLV_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND
= 0x12,
386 HTT_TLV_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE
= 0x14,
387 HTT_TLV_T2H_MSG_TYPE_CHAN_CHANGE
= 0x15,
388 HTT_TLV_T2H_MSG_TYPE_RX_OFLD_PKT_ERR
= 0x16,
389 HTT_TLV_T2H_MSG_TYPE_TEST
,
394 enum htt_10_4_t2h_msg_type
{
395 HTT_10_4_T2H_MSG_TYPE_VERSION_CONF
= 0x0,
396 HTT_10_4_T2H_MSG_TYPE_RX_IND
= 0x1,
397 HTT_10_4_T2H_MSG_TYPE_RX_FLUSH
= 0x2,
398 HTT_10_4_T2H_MSG_TYPE_PEER_MAP
= 0x3,
399 HTT_10_4_T2H_MSG_TYPE_PEER_UNMAP
= 0x4,
400 HTT_10_4_T2H_MSG_TYPE_RX_ADDBA
= 0x5,
401 HTT_10_4_T2H_MSG_TYPE_RX_DELBA
= 0x6,
402 HTT_10_4_T2H_MSG_TYPE_TX_COMPL_IND
= 0x7,
403 HTT_10_4_T2H_MSG_TYPE_PKTLOG
= 0x8,
404 HTT_10_4_T2H_MSG_TYPE_STATS_CONF
= 0x9,
405 HTT_10_4_T2H_MSG_TYPE_RX_FRAG_IND
= 0xa,
406 HTT_10_4_T2H_MSG_TYPE_SEC_IND
= 0xb,
407 HTT_10_4_T2H_MSG_TYPE_RC_UPDATE_IND
= 0xc,
408 HTT_10_4_T2H_MSG_TYPE_TX_INSPECT_IND
= 0xd,
409 HTT_10_4_T2H_MSG_TYPE_MGMT_TX_COMPL_IND
= 0xe,
410 HTT_10_4_T2H_MSG_TYPE_CHAN_CHANGE
= 0xf,
411 HTT_10_4_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND
= 0x10,
412 HTT_10_4_T2H_MSG_TYPE_RX_PN_IND
= 0x11,
413 HTT_10_4_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND
= 0x12,
414 HTT_10_4_T2H_MSG_TYPE_TEST
= 0x13,
415 HTT_10_4_T2H_MSG_TYPE_EN_STATS
= 0x14,
416 HTT_10_4_T2H_MSG_TYPE_AGGR_CONF
= 0x15,
417 HTT_10_4_T2H_MSG_TYPE_TX_FETCH_IND
= 0x16,
418 HTT_10_4_T2H_MSG_TYPE_TX_FETCH_CONFIRM
= 0x17,
419 HTT_10_4_T2H_MSG_TYPE_STATS_NOUPLOAD
= 0x18,
420 /* 0x19 to 0x2f are reserved */
421 HTT_10_4_T2H_MSG_TYPE_TX_MODE_SWITCH_IND
= 0x30,
423 HTT_10_4_T2H_NUM_MSGS
426 enum htt_t2h_msg_type
{
427 HTT_T2H_MSG_TYPE_VERSION_CONF
,
428 HTT_T2H_MSG_TYPE_RX_IND
,
429 HTT_T2H_MSG_TYPE_RX_FLUSH
,
430 HTT_T2H_MSG_TYPE_PEER_MAP
,
431 HTT_T2H_MSG_TYPE_PEER_UNMAP
,
432 HTT_T2H_MSG_TYPE_RX_ADDBA
,
433 HTT_T2H_MSG_TYPE_RX_DELBA
,
434 HTT_T2H_MSG_TYPE_TX_COMPL_IND
,
435 HTT_T2H_MSG_TYPE_PKTLOG
,
436 HTT_T2H_MSG_TYPE_STATS_CONF
,
437 HTT_T2H_MSG_TYPE_RX_FRAG_IND
,
438 HTT_T2H_MSG_TYPE_SEC_IND
,
439 HTT_T2H_MSG_TYPE_RC_UPDATE_IND
,
440 HTT_T2H_MSG_TYPE_TX_INSPECT_IND
,
441 HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION
,
442 HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND
,
443 HTT_T2H_MSG_TYPE_RX_PN_IND
,
444 HTT_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND
,
445 HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND
,
446 HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE
,
447 HTT_T2H_MSG_TYPE_CHAN_CHANGE
,
448 HTT_T2H_MSG_TYPE_RX_OFLD_PKT_ERR
,
449 HTT_T2H_MSG_TYPE_AGGR_CONF
,
450 HTT_T2H_MSG_TYPE_STATS_NOUPLOAD
,
451 HTT_T2H_MSG_TYPE_TEST
,
452 HTT_T2H_MSG_TYPE_EN_STATS
,
453 HTT_T2H_MSG_TYPE_TX_FETCH_IND
,
454 HTT_T2H_MSG_TYPE_TX_FETCH_CONFIRM
,
455 HTT_T2H_MSG_TYPE_TX_MODE_SWITCH_IND
,
461 * htt_resp_hdr - header for target-to-host messages
463 * msg_type: see htt_t2h_msg_type
465 struct htt_resp_hdr
{
469 #define HTT_RESP_HDR_MSG_TYPE_OFFSET 0
470 #define HTT_RESP_HDR_MSG_TYPE_MASK 0xff
471 #define HTT_RESP_HDR_MSG_TYPE_LSB 0
473 /* htt_ver_resp - response sent for htt_ver_req */
474 struct htt_ver_resp
{
480 struct htt_mgmt_tx_completion
{
488 #define HTT_RX_INDICATION_INFO0_EXT_TID_MASK (0x1F)
489 #define HTT_RX_INDICATION_INFO0_EXT_TID_LSB (0)
490 #define HTT_RX_INDICATION_INFO0_FLUSH_VALID (1 << 5)
491 #define HTT_RX_INDICATION_INFO0_RELEASE_VALID (1 << 6)
493 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_MASK 0x0000003F
494 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_LSB 0
495 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_MASK 0x00000FC0
496 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_LSB 6
497 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_MASK 0x0003F000
498 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_LSB 12
499 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_MASK 0x00FC0000
500 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_LSB 18
501 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_MASK 0xFF000000
502 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_LSB 24
504 struct htt_rx_indication_hdr
{
505 u8 info0
; /* %HTT_RX_INDICATION_INFO0_ */
507 __le32 info1
; /* %HTT_RX_INDICATION_INFO1_ */
510 #define HTT_RX_INDICATION_INFO0_PHY_ERR_VALID (1 << 0)
511 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_MASK (0x1E)
512 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_LSB (1)
513 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_CCK (1 << 5)
514 #define HTT_RX_INDICATION_INFO0_END_VALID (1 << 6)
515 #define HTT_RX_INDICATION_INFO0_START_VALID (1 << 7)
517 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_MASK 0x00FFFFFF
518 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_LSB 0
519 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_MASK 0xFF000000
520 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_LSB 24
522 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_MASK 0x00FFFFFF
523 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_LSB 0
524 #define HTT_RX_INDICATION_INFO2_SERVICE_MASK 0xFF000000
525 #define HTT_RX_INDICATION_INFO2_SERVICE_LSB 24
527 enum htt_rx_legacy_rate
{
538 HTT_RX_CCK_11_LP
= 0,
539 HTT_RX_CCK_5_5_LP
= 1,
548 enum htt_rx_legacy_rate_type
{
549 HTT_RX_LEGACY_RATE_OFDM
= 0,
550 HTT_RX_LEGACY_RATE_CCK
553 enum htt_rx_preamble_type
{
556 HTT_RX_HT_WITH_TXBF
= 0x9,
558 HTT_RX_VHT_WITH_TXBF
= 0xD,
562 * Fields: phy_err_valid, phy_err_code, tsf,
563 * usec_timestamp, sub_usec_timestamp
564 * ..are valid only if end_valid == 1.
566 * Fields: rssi_chains, legacy_rate_type,
567 * legacy_rate_cck, preamble_type, service,
569 * ..are valid only if start_valid == 1;
571 struct htt_rx_indication_ppdu
{
573 u8 sub_usec_timestamp
;
575 u8 info0
; /* HTT_RX_INDICATION_INFO0_ */
581 } __packed rssi_chains
[4];
583 __le32 usec_timestamp
;
584 __le32 info1
; /* HTT_RX_INDICATION_INFO1_ */
585 __le32 info2
; /* HTT_RX_INDICATION_INFO2_ */
588 enum htt_rx_mpdu_status
{
589 HTT_RX_IND_MPDU_STATUS_UNKNOWN
= 0x0,
590 HTT_RX_IND_MPDU_STATUS_OK
,
591 HTT_RX_IND_MPDU_STATUS_ERR_FCS
,
592 HTT_RX_IND_MPDU_STATUS_ERR_DUP
,
593 HTT_RX_IND_MPDU_STATUS_ERR_REPLAY
,
594 HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER
,
595 /* only accept EAPOL frames */
596 HTT_RX_IND_MPDU_STATUS_UNAUTH_PEER
,
597 HTT_RX_IND_MPDU_STATUS_OUT_OF_SYNC
,
598 /* Non-data in promiscous mode */
599 HTT_RX_IND_MPDU_STATUS_MGMT_CTRL
,
600 HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR
,
601 HTT_RX_IND_MPDU_STATUS_DECRYPT_ERR
,
602 HTT_RX_IND_MPDU_STATUS_MPDU_LENGTH_ERR
,
603 HTT_RX_IND_MPDU_STATUS_ENCRYPT_REQUIRED_ERR
,
604 HTT_RX_IND_MPDU_STATUS_PRIVACY_ERR
,
607 * MISC: discard for unspecified reasons.
608 * Leave this enum value last.
610 HTT_RX_IND_MPDU_STATUS_ERR_MISC
= 0xFF
613 struct htt_rx_indication_mpdu_range
{
615 u8 mpdu_range_status
; /* %htt_rx_mpdu_status */
620 struct htt_rx_indication_prefix
{
621 __le16 fw_rx_desc_bytes
;
626 struct htt_rx_indication
{
627 struct htt_rx_indication_hdr hdr
;
628 struct htt_rx_indication_ppdu ppdu
;
629 struct htt_rx_indication_prefix prefix
;
632 * the following fields are both dynamically sized, so
633 * take care addressing them
636 /* the size of this is %fw_rx_desc_bytes */
637 struct fw_rx_desc_base fw_desc
;
640 * %mpdu_ranges starts after &%prefix + roundup(%fw_rx_desc_bytes, 4)
641 * and has %num_mpdu_ranges elements.
643 struct htt_rx_indication_mpdu_range mpdu_ranges
[0];
646 static inline struct htt_rx_indication_mpdu_range
*
647 htt_rx_ind_get_mpdu_ranges(struct htt_rx_indication
*rx_ind
)
651 ptr
+= sizeof(rx_ind
->hdr
)
652 + sizeof(rx_ind
->ppdu
)
653 + sizeof(rx_ind
->prefix
)
654 + roundup(__le16_to_cpu(rx_ind
->prefix
.fw_rx_desc_bytes
), 4);
658 enum htt_rx_flush_mpdu_status
{
659 HTT_RX_FLUSH_MPDU_DISCARD
= 0,
660 HTT_RX_FLUSH_MPDU_REORDER
= 1,
664 * htt_rx_flush - discard or reorder given range of mpdus
666 * Note: host must check if all sequence numbers between
667 * [seq_num_start, seq_num_end-1] are valid.
669 struct htt_rx_flush
{
673 u8 mpdu_status
; /* %htt_rx_flush_mpdu_status */
674 u8 seq_num_start
; /* it is 6 LSBs of 802.11 seq no */
675 u8 seq_num_end
; /* it is 6 LSBs of 802.11 seq no */
678 struct htt_rx_peer_map
{
686 struct htt_rx_peer_unmap
{
691 enum htt_security_types
{
697 HTT_SECURITY_TKIP_NOMIC
,
698 HTT_SECURITY_AES_CCMP
,
701 HTT_NUM_SECURITY_TYPES
/* keep this last! */
704 enum htt_security_flags
{
705 #define HTT_SECURITY_TYPE_MASK 0x7F
706 #define HTT_SECURITY_TYPE_LSB 0
707 HTT_SECURITY_IS_UNICAST
= 1 << 7
710 struct htt_security_indication
{
712 /* dont use bitfields; undefined behaviour */
713 u8 flags
; /* %htt_security_flags */
715 u8 security_type
:7, /* %htt_security_types */
724 #define HTT_RX_BA_INFO0_TID_MASK 0x000F
725 #define HTT_RX_BA_INFO0_TID_LSB 0
726 #define HTT_RX_BA_INFO0_PEER_ID_MASK 0xFFF0
727 #define HTT_RX_BA_INFO0_PEER_ID_LSB 4
729 struct htt_rx_addba
{
731 __le16 info0
; /* %HTT_RX_BA_INFO0_ */
734 struct htt_rx_delba
{
736 __le16 info0
; /* %HTT_RX_BA_INFO0_ */
739 enum htt_data_tx_status
{
740 HTT_DATA_TX_STATUS_OK
= 0,
741 HTT_DATA_TX_STATUS_DISCARD
= 1,
742 HTT_DATA_TX_STATUS_NO_ACK
= 2,
743 HTT_DATA_TX_STATUS_POSTPONE
= 3, /* HL only */
744 HTT_DATA_TX_STATUS_DOWNLOAD_FAIL
= 128
747 enum htt_data_tx_flags
{
748 #define HTT_DATA_TX_STATUS_MASK 0x07
749 #define HTT_DATA_TX_STATUS_LSB 0
750 #define HTT_DATA_TX_TID_MASK 0x78
751 #define HTT_DATA_TX_TID_LSB 3
752 HTT_DATA_TX_TID_INVALID
= 1 << 7
755 #define HTT_TX_COMPL_INV_MSDU_ID 0xFFFF
757 struct htt_data_tx_completion
{
768 __le16 msdus
[0]; /* variable length based on %num_msdus */
771 struct htt_tx_compl_ind_base
{
773 u16 payload
[1/*or more*/];
776 struct htt_rc_tx_done_params
{
780 u32 num_enqued
; /* 1 for non-AMPDU */
782 u32 num_failed
; /* for AMPDU */
788 struct htt_rc_update
{
794 struct htt_rc_tx_done_params params
[0]; /* variable length %num_elems */
797 /* see htt_rx_indication for similar fields and descriptions */
798 struct htt_rx_fragment_indication
{
800 u8 info0
; /* %HTT_RX_FRAG_IND_INFO0_ */
807 __le32 info1
; /* %HTT_RX_FRAG_IND_INFO1_ */
808 __le16 fw_rx_desc_bytes
;
811 u8 fw_msdu_rx_desc
[0];
814 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_MASK 0x1F
815 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_LSB 0
816 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_MASK 0x20
817 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_LSB 5
819 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_MASK 0x0000003F
820 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_LSB 0
821 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_MASK 0x00000FC0
822 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_LSB 6
824 struct htt_rx_pn_ind
{
834 struct htt_rx_offload_msdu
{
843 struct htt_rx_offload_ind
{
848 struct htt_rx_in_ord_msdu_desc
{
855 struct htt_rx_in_ord_ind
{
861 struct htt_rx_in_ord_msdu_desc msdu_descs
[0];
864 #define HTT_RX_IN_ORD_IND_INFO_TID_MASK 0x0000001f
865 #define HTT_RX_IN_ORD_IND_INFO_TID_LSB 0
866 #define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_MASK 0x00000020
867 #define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_LSB 5
868 #define HTT_RX_IN_ORD_IND_INFO_FRAG_MASK 0x00000040
869 #define HTT_RX_IN_ORD_IND_INFO_FRAG_LSB 6
872 * target -> host test message definition
874 * The following field definitions describe the format of the test
875 * message sent from the target to the host.
876 * The message consists of a 4-octet header, followed by a variable
877 * number of 32-bit integer values, followed by a variable number
878 * of 8-bit character values.
881 * |-----------------------------------------------------------|
882 * | num chars | num ints | msg type |
883 * |-----------------------------------------------------------|
885 * |-----------------------------------------------------------|
887 * |-----------------------------------------------------------|
889 * |-----------------------------------------------------------|
890 * | char 3 | char 2 | char 1 | char 0 |
891 * |-----------------------------------------------------------|
892 * | | | ... | char 4 |
893 * |-----------------------------------------------------------|
896 * Purpose: identifies this as a test message
897 * Value: HTT_MSG_TYPE_TEST
900 * Purpose: indicate how many 32-bit integers follow the message header
903 * Purpose: indicate how many 8-bit charaters follow the series of integers
909 /* payload consists of 2 lists:
910 * a) num_ints * sizeof(__le32)
911 * b) num_chars * sizeof(u8) aligned to 4bytes */
915 static inline __le32
*htt_rx_test_get_ints(struct htt_rx_test
*rx_test
)
917 return (__le32
*)rx_test
->payload
;
920 static inline u8
*htt_rx_test_get_chars(struct htt_rx_test
*rx_test
)
922 return rx_test
->payload
+ (rx_test
->num_ints
* sizeof(__le32
));
926 * target -> host packet log message
928 * The following field definitions describe the format of the packet log
929 * message sent from the target to the host.
930 * The message consists of a 4-octet header,followed by a variable number
931 * of 32-bit character values.
933 * |31 24|23 16|15 8|7 0|
934 * |-----------------------------------------------------------|
936 * |-----------------------------------------------------------|
938 * |-----------------------------------------------------------|
941 * Purpose: identifies this as a test message
942 * Value: HTT_MSG_TYPE_PACKETLOG
944 struct htt_pktlog_msg
{
949 struct htt_dbg_stats_rx_reorder_stats
{
950 /* Non QoS MPDUs received */
951 __le32 deliver_non_qos
;
953 /* MPDUs received in-order */
954 __le32 deliver_in_order
;
956 /* Flush due to reorder timer expired */
957 __le32 deliver_flush_timeout
;
959 /* Flush due to move out of window */
960 __le32 deliver_flush_oow
;
962 /* Flush due to DELBA */
963 __le32 deliver_flush_delba
;
965 /* MPDUs dropped due to FCS error */
968 /* MPDUs dropped due to monitor mode non-data packet */
971 /* MPDUs dropped due to invalid peer */
974 /* MPDUs dropped due to duplication (non aggregation) */
977 /* MPDUs dropped due to processed before */
980 /* MPDUs dropped due to duplicate in reorder queue */
981 __le32 dup_in_reorder
;
983 /* Reorder timeout happened */
984 __le32 reorder_timeout
;
986 /* invalid bar ssn */
987 __le32 invalid_bar_ssn
;
989 /* reorder reset due to bar ssn */
993 struct htt_dbg_stats_wal_tx_stats
{
994 /* Num HTT cookies queued to dispatch list */
997 /* Num HTT cookies dispatched */
998 __le32 comp_delivered
;
1000 /* Num MSDU queued to WAL */
1003 /* Num MPDU queue to WAL */
1006 /* Num MSDUs dropped by WMM limit */
1009 /* Num Local frames queued */
1010 __le32 local_enqued
;
1012 /* Num Local frames done */
1015 /* Num queued to HW */
1018 /* Num PPDU reaped from HW */
1024 /* Num PPDUs cleaned up in TX abort */
1027 /* Num MPDUs requed by SW */
1028 __le32 mpdus_requed
;
1030 /* excessive retries */
1033 /* data hw rate code */
1036 /* Scheduler self triggers */
1037 __le32 self_triggers
;
1039 /* frames dropped due to excessive sw retries */
1040 __le32 sw_retry_failure
;
1042 /* illegal rate phy errors */
1043 __le32 illgl_rate_phy_err
;
1045 /* wal pdev continous xretry */
1046 __le32 pdev_cont_xretry
;
1048 /* wal pdev continous xretry */
1049 __le32 pdev_tx_timeout
;
1051 /* wal pdev resets */
1054 __le32 phy_underrun
;
1056 /* MPDU is more than txop limit */
1060 struct htt_dbg_stats_wal_rx_stats
{
1061 /* Cnts any change in ring routing mid-ppdu */
1062 __le32 mid_ppdu_route_change
;
1064 /* Total number of statuses processed */
1067 /* Extra frags on rings 0-3 */
1073 /* MSDUs / MPDUs delivered to HTT */
1077 /* MSDUs / MPDUs delivered to local stack */
1081 /* AMSDUs that have more MSDUs than the status ring size */
1082 __le32 oversize_amsdu
;
1084 /* Number of PHY errors */
1087 /* Number of PHY errors drops */
1088 __le32 phy_err_drop
;
1090 /* Number of mpdu errors - FCS, MIC, ENC etc. */
1094 struct htt_dbg_stats_wal_peer_stats
{
1095 __le32 dummy
; /* REMOVE THIS ONCE REAL PEER STAT COUNTERS ARE ADDED */
1098 struct htt_dbg_stats_wal_pdev_txrx
{
1099 struct htt_dbg_stats_wal_tx_stats tx_stats
;
1100 struct htt_dbg_stats_wal_rx_stats rx_stats
;
1101 struct htt_dbg_stats_wal_peer_stats peer_stats
;
1104 struct htt_dbg_stats_rx_rate_info
{
1116 * htt_dbg_stats_status -
1117 * present - The requested stats have been delivered in full.
1118 * This indicates that either the stats information was contained
1119 * in its entirety within this message, or else this message
1120 * completes the delivery of the requested stats info that was
1121 * partially delivered through earlier STATS_CONF messages.
1122 * partial - The requested stats have been delivered in part.
1123 * One or more subsequent STATS_CONF messages with the same
1124 * cookie value will be sent to deliver the remainder of the
1126 * error - The requested stats could not be delivered, for example due
1127 * to a shortage of memory to construct a message holding the
1129 * invalid - The requested stat type is either not recognized, or the
1130 * target is configured to not gather the stats type in question.
1131 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1132 * series_done - This special value indicates that no further stats info
1133 * elements are present within a series of stats info elems
1134 * (within a stats upload confirmation message).
1136 enum htt_dbg_stats_status
{
1137 HTT_DBG_STATS_STATUS_PRESENT
= 0,
1138 HTT_DBG_STATS_STATUS_PARTIAL
= 1,
1139 HTT_DBG_STATS_STATUS_ERROR
= 2,
1140 HTT_DBG_STATS_STATUS_INVALID
= 3,
1141 HTT_DBG_STATS_STATUS_SERIES_DONE
= 7
1145 * target -> host statistics upload
1147 * The following field definitions describe the format of the HTT target
1148 * to host stats upload confirmation message.
1149 * The message contains a cookie echoed from the HTT host->target stats
1150 * upload request, which identifies which request the confirmation is
1151 * for, and a series of tag-length-value stats information elements.
1152 * The tag-length header for each stats info element also includes a
1153 * status field, to indicate whether the request for the stat type in
1154 * question was fully met, partially met, unable to be met, or invalid
1155 * (if the stat type in question is disabled in the target).
1156 * A special value of all 1's in this status field is used to indicate
1157 * the end of the series of stats info elements.
1160 * |31 16|15 8|7 5|4 0|
1161 * |------------------------------------------------------------|
1162 * | reserved | msg type |
1163 * |------------------------------------------------------------|
1165 * |------------------------------------------------------------|
1167 * |------------------------------------------------------------|
1168 * | stats entry length | reserved | S |stat type|
1169 * |------------------------------------------------------------|
1171 * | type-specific stats info |
1173 * |------------------------------------------------------------|
1174 * | stats entry length | reserved | S |stat type|
1175 * |------------------------------------------------------------|
1177 * | type-specific stats info |
1179 * |------------------------------------------------------------|
1180 * | n/a | reserved | 111 | n/a |
1181 * |------------------------------------------------------------|
1185 * Purpose: identifies this is a statistics upload confirmation message
1189 * Purpose: Provide a mechanism to match a target->host stats confirmation
1190 * message with its preceding host->target stats request message.
1191 * Value: LSBs of the opaque cookie specified by the host-side requestor
1194 * Purpose: Provide a mechanism to match a target->host stats confirmation
1195 * message with its preceding host->target stats request message.
1196 * Value: MSBs of the opaque cookie specified by the host-side requestor
1198 * Stats Information Element tag-length header fields:
1201 * Purpose: identifies the type of statistics info held in the
1202 * following information element
1203 * Value: htt_dbg_stats_type
1206 * Purpose: indicate whether the requested stats are present
1207 * Value: htt_dbg_stats_status, including a special value (0x7) to mark
1208 * the completion of the stats entry series
1211 * Purpose: indicate the stats information size
1212 * Value: This field specifies the number of bytes of stats information
1213 * that follows the element tag-length header.
1214 * It is expected but not required that this length is a multiple of
1215 * 4 bytes. Even if the length is not an integer multiple of 4, the
1216 * subsequent stats entry header will begin on a 4-byte aligned
1220 #define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_MASK 0x1F
1221 #define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_LSB 0
1222 #define HTT_STATS_CONF_ITEM_INFO_STATUS_MASK 0xE0
1223 #define HTT_STATS_CONF_ITEM_INFO_STATUS_LSB 5
1225 struct htt_stats_conf_item
{
1229 u8 stat_type
:5; /* %HTT_DBG_STATS_ */
1230 u8 status
:3; /* %HTT_DBG_STATS_STATUS_ */
1235 u8 payload
[0]; /* roundup(length, 4) long */
1238 struct htt_stats_conf
{
1243 /* each item has variable length! */
1244 struct htt_stats_conf_item items
[0];
1247 static inline struct htt_stats_conf_item
*htt_stats_conf_next_item(
1248 const struct htt_stats_conf_item
*item
)
1250 return (void *)item
+ sizeof(*item
) + roundup(item
->length
, 4);
1254 * host -> target FRAG DESCRIPTOR/MSDU_EXT DESC bank
1256 * The following field definitions describe the format of the HTT host
1257 * to target frag_desc/msdu_ext bank configuration message.
1258 * The message contains the based address and the min and max id of the
1259 * MSDU_EXT/FRAG_DESC that will be used by the HTT to map MSDU DESC and
1260 * MSDU_EXT/FRAG_DESC.
1261 * HTT will use id in HTT descriptor instead sending the frag_desc_ptr.
1262 * For QCA988X HW the firmware will use fragment_desc_ptr but in WIFI2.0
1263 * the hardware does the mapping/translation.
1265 * Total banks that can be configured is configured to 16.
1267 * This should be called before any TX has be initiated by the HTT
1269 * |31 16|15 8|7 5|4 0|
1270 * |------------------------------------------------------------|
1271 * | DESC_SIZE | NUM_BANKS | RES |SWP|pdev| msg type |
1272 * |------------------------------------------------------------|
1273 * | BANK0_BASE_ADDRESS |
1274 * |------------------------------------------------------------|
1276 * |------------------------------------------------------------|
1277 * | BANK15_BASE_ADDRESS |
1278 * |------------------------------------------------------------|
1279 * | BANK0_MAX_ID | BANK0_MIN_ID |
1280 * |------------------------------------------------------------|
1282 * |------------------------------------------------------------|
1283 * | BANK15_MAX_ID | BANK15_MIN_ID |
1284 * |------------------------------------------------------------|
1289 * - BANKx_BASE_ADDRESS
1291 * Purpose: Provide a mechanism to specify the base address of the MSDU_EXT
1292 * bank physical/bus address.
1295 * Purpose: Provide a mechanism to specify the min index that needs to
1299 * Purpose: Provide a mechanism to specify the max index that needs to
1302 struct htt_frag_desc_bank_id
{
1307 /* real is 16 but it wouldn't fit in the max htt message size
1308 * so we use a conservatively safe value for now */
1309 #define HTT_FRAG_DESC_BANK_MAX 4
1311 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_MASK 0x03
1312 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_LSB 0
1313 #define HTT_FRAG_DESC_BANK_CFG_INFO_SWAP BIT(2)
1314 #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID BIT(3)
1315 #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE_MASK BIT(4)
1316 #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE_LSB 4
1318 enum htt_q_depth_type
{
1319 HTT_Q_DEPTH_TYPE_BYTES
= 0,
1320 HTT_Q_DEPTH_TYPE_MSDUS
= 1,
1323 #define HTT_TX_Q_STATE_NUM_PEERS (TARGET_10_4_NUM_QCACHE_PEERS_MAX + \
1324 TARGET_10_4_NUM_VDEVS)
1325 #define HTT_TX_Q_STATE_NUM_TIDS 8
1326 #define HTT_TX_Q_STATE_ENTRY_SIZE 1
1327 #define HTT_TX_Q_STATE_ENTRY_MULTIPLIER 0
1330 * htt_q_state_conf - part of htt_frag_desc_bank_cfg for host q state config
1332 * Defines host q state format and behavior. See htt_q_state.
1334 * @record_size: Defines the size of each host q entry in bytes. In practice
1335 * however firmware (at least 10.4.3-00191) ignores this host
1336 * configuration value and uses hardcoded value of 1.
1337 * @record_multiplier: This is valid only when q depth type is MSDUs. It
1338 * defines the exponent for the power of 2 multiplication.
1340 struct htt_q_state_conf
{
1345 u8 record_multiplier
;
1349 struct htt_frag_desc_bank_cfg
{
1350 u8 info
; /* HTT_FRAG_DESC_BANK_CFG_INFO_ */
1353 __le32 bank_base_addrs
[HTT_FRAG_DESC_BANK_MAX
];
1354 struct htt_frag_desc_bank_id bank_id
[HTT_FRAG_DESC_BANK_MAX
];
1355 struct htt_q_state_conf q_state
;
1358 #define HTT_TX_Q_STATE_ENTRY_COEFFICIENT 128
1359 #define HTT_TX_Q_STATE_ENTRY_FACTOR_MASK 0x3f
1360 #define HTT_TX_Q_STATE_ENTRY_FACTOR_LSB 0
1361 #define HTT_TX_Q_STATE_ENTRY_EXP_MASK 0xc0
1362 #define HTT_TX_Q_STATE_ENTRY_EXP_LSB 6
1365 * htt_q_state - shared between host and firmware via DMA
1367 * This structure is used for the host to expose it's software queue state to
1368 * firmware so that its rate control can schedule fetch requests for optimized
1369 * performance. This is most notably used for MU-MIMO aggregation when multiple
1370 * MU clients are connected.
1372 * @count: Each element defines the host queue depth. When q depth type was
1373 * configured as HTT_Q_DEPTH_TYPE_BYTES then each entry is defined as:
1374 * FACTOR * 128 * 8^EXP (see HTT_TX_Q_STATE_ENTRY_FACTOR_MASK and
1375 * HTT_TX_Q_STATE_ENTRY_EXP_MASK). When q depth type was configured as
1376 * HTT_Q_DEPTH_TYPE_MSDUS the number of packets is scaled by 2 **
1377 * record_multiplier (see htt_q_state_conf).
1378 * @map: Used by firmware to quickly check which host queues are not empty. It
1379 * is a bitmap simply saying.
1380 * @seq: Used by firmware to quickly check if the host queues were updated
1381 * since it last checked.
1383 * FIXME: Is the q_state map[] size calculation really correct?
1385 struct htt_q_state
{
1386 u8 count
[HTT_TX_Q_STATE_NUM_TIDS
][HTT_TX_Q_STATE_NUM_PEERS
];
1387 u32 map
[HTT_TX_Q_STATE_NUM_TIDS
][(HTT_TX_Q_STATE_NUM_PEERS
+ 31) / 32];
1391 #define HTT_TX_FETCH_RECORD_INFO_PEER_ID_MASK 0x0fff
1392 #define HTT_TX_FETCH_RECORD_INFO_PEER_ID_LSB 0
1393 #define HTT_TX_FETCH_RECORD_INFO_TID_MASK 0xf000
1394 #define HTT_TX_FETCH_RECORD_INFO_TID_LSB 12
1396 struct htt_tx_fetch_record
{
1397 __le16 info
; /* HTT_TX_FETCH_IND_RECORD_INFO_ */
1402 struct htt_tx_fetch_ind
{
1404 __le16 fetch_seq_num
;
1406 __le16 num_resp_ids
;
1408 struct htt_tx_fetch_record records
[0];
1409 __le32 resp_ids
[0]; /* ath10k_htt_get_tx_fetch_ind_resp_ids() */
1412 static inline void *
1413 ath10k_htt_get_tx_fetch_ind_resp_ids(struct htt_tx_fetch_ind
*ind
)
1415 return (void *)&ind
->records
[le16_to_cpu(ind
->num_records
)];
1418 struct htt_tx_fetch_resp
{
1421 __le16 fetch_seq_num
;
1424 struct htt_tx_fetch_record records
[0];
1427 struct htt_tx_fetch_confirm
{
1429 __le16 num_resp_ids
;
1433 enum htt_tx_mode_switch_mode
{
1434 HTT_TX_MODE_SWITCH_PUSH
= 0,
1435 HTT_TX_MODE_SWITCH_PUSH_PULL
= 1,
1438 #define HTT_TX_MODE_SWITCH_IND_INFO0_ENABLE BIT(0)
1439 #define HTT_TX_MODE_SWITCH_IND_INFO0_NUM_RECORDS_MASK 0xfffe
1440 #define HTT_TX_MODE_SWITCH_IND_INFO0_NUM_RECORDS_LSB 1
1442 #define HTT_TX_MODE_SWITCH_IND_INFO1_MODE_MASK 0x0003
1443 #define HTT_TX_MODE_SWITCH_IND_INFO1_MODE_LSB 0
1444 #define HTT_TX_MODE_SWITCH_IND_INFO1_THRESHOLD_MASK 0xfffc
1445 #define HTT_TX_MODE_SWITCH_IND_INFO1_THRESHOLD_LSB 2
1447 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_PEER_ID_MASK 0x0fff
1448 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_PEER_ID_LSB 0
1449 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_TID_MASK 0xf000
1450 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_TID_LSB 12
1452 struct htt_tx_mode_switch_record
{
1453 __le16 info0
; /* HTT_TX_MODE_SWITCH_RECORD_INFO0_ */
1454 __le16 num_max_msdus
;
1457 struct htt_tx_mode_switch_ind
{
1459 __le16 info0
; /* HTT_TX_MODE_SWITCH_IND_INFO0_ */
1460 __le16 info1
; /* HTT_TX_MODE_SWITCH_IND_INFO1_ */
1462 struct htt_tx_mode_switch_record records
[0];
1465 struct htt_channel_change
{
1468 __le32 center_freq1
;
1469 __le32 center_freq2
;
1474 /* WEP: 24-bit PN */
1477 /* TKIP or CCMP: 48-bit PN */
1480 /* WAPI: 128-bit PN */
1485 struct htt_cmd_hdr hdr
;
1487 struct htt_ver_req ver_req
;
1488 struct htt_mgmt_tx_desc mgmt_tx
;
1489 struct htt_data_tx_desc data_tx
;
1490 struct htt_rx_ring_setup rx_setup
;
1491 struct htt_stats_req stats_req
;
1492 struct htt_oob_sync_req oob_sync_req
;
1493 struct htt_aggr_conf aggr_conf
;
1494 struct htt_frag_desc_bank_cfg frag_desc_bank_cfg
;
1495 struct htt_tx_fetch_resp tx_fetch_resp
;
1500 struct htt_resp_hdr hdr
;
1502 struct htt_ver_resp ver_resp
;
1503 struct htt_mgmt_tx_completion mgmt_tx_completion
;
1504 struct htt_data_tx_completion data_tx_completion
;
1505 struct htt_rx_indication rx_ind
;
1506 struct htt_rx_fragment_indication rx_frag_ind
;
1507 struct htt_rx_peer_map peer_map
;
1508 struct htt_rx_peer_unmap peer_unmap
;
1509 struct htt_rx_flush rx_flush
;
1510 struct htt_rx_addba rx_addba
;
1511 struct htt_rx_delba rx_delba
;
1512 struct htt_security_indication security_indication
;
1513 struct htt_rc_update rc_update
;
1514 struct htt_rx_test rx_test
;
1515 struct htt_pktlog_msg pktlog_msg
;
1516 struct htt_stats_conf stats_conf
;
1517 struct htt_rx_pn_ind rx_pn_ind
;
1518 struct htt_rx_offload_ind rx_offload_ind
;
1519 struct htt_rx_in_ord_ind rx_in_ord_ind
;
1520 struct htt_tx_fetch_ind tx_fetch_ind
;
1521 struct htt_tx_fetch_confirm tx_fetch_confirm
;
1522 struct htt_tx_mode_switch_ind tx_mode_switch_ind
;
1523 struct htt_channel_change chan_change
;
1527 /*** host side structures follow ***/
1529 struct htt_tx_done
{
1534 enum htt_tx_compl_state
{
1535 HTT_TX_COMPL_STATE_NONE
,
1536 HTT_TX_COMPL_STATE_ACK
,
1537 HTT_TX_COMPL_STATE_NOACK
,
1538 HTT_TX_COMPL_STATE_DISCARD
,
1541 struct htt_peer_map_event
{
1547 struct htt_peer_unmap_event
{
1551 struct ath10k_htt_txbuf
{
1552 struct htt_data_tx_desc_frag frags
[2];
1553 struct ath10k_htc_hdr htc_hdr
;
1554 struct htt_cmd_hdr cmd_hdr
;
1555 struct htt_data_tx_desc cmd_tx
;
1560 enum ath10k_htc_ep_id eid
;
1562 u8 target_version_major
;
1563 u8 target_version_minor
;
1564 struct completion target_version_received
;
1568 const enum htt_t2h_msg_type
*t2h_msg_types
;
1569 u32 t2h_msg_types_max
;
1573 * Ring of network buffer objects - This ring is
1574 * used exclusively by the host SW. This ring
1575 * mirrors the dev_addrs_ring that is shared
1576 * between the host SW and the MAC HW. The host SW
1577 * uses this netbufs ring to locate the network
1578 * buffer objects whose data buffers the HW has
1581 struct sk_buff
**netbufs_ring
;
1583 /* This is used only with firmware supporting IN_ORD_IND.
1585 * With Full Rx Reorder the HTT Rx Ring is more of a temporary
1586 * buffer ring from which buffer addresses are copied by the
1587 * firmware to MAC Rx ring. Firmware then delivers IN_ORD_IND
1588 * pointing to specific (re-ordered) buffers.
1590 * FIXME: With kernel generic hashing functions there's a lot
1591 * of hash collisions for sk_buffs.
1594 DECLARE_HASHTABLE(skb_table
, 4);
1597 * Ring of buffer addresses -
1598 * This ring holds the "physical" device address of the
1599 * rx buffers the host SW provides for the MAC HW to
1602 __le32
*paddrs_ring
;
1605 * Base address of ring, as a "physical" device address
1606 * rather than a CPU address.
1608 dma_addr_t base_paddr
;
1610 /* how many elems in the ring (power of 2) */
1616 /* how many rx buffers to keep in the ring */
1619 /* how many rx buffers (full+empty) are in the ring */
1623 * alloc_idx - where HTT SW has deposited empty buffers
1624 * This is allocated in consistent mem, so that the FW can
1625 * read this variable, and program the HW's FW_IDX reg with
1626 * the value of this shadow register.
1633 /* where HTT SW has processed bufs filled by rx MAC DMA */
1635 unsigned msdu_payld
;
1639 * refill_retry_timer - timer triggered when the ring is
1640 * not refilled to the level expected
1642 struct timer_list refill_retry_timer
;
1644 /* Protects access to all rx ring buffer state variables */
1648 unsigned int prefetch_len
;
1650 /* Protects access to pending_tx, num_pending_tx */
1652 int max_num_pending_tx
;
1654 int num_pending_mgmt_tx
;
1655 struct idr pending_tx
;
1656 wait_queue_head_t empty_tx_wq
;
1658 /* FIFO for storing tx done status {ack, no-ack, discard} and msdu id */
1659 DECLARE_KFIFO_PTR(txdone_fifo
, struct htt_tx_done
);
1661 /* set if host-fw communication goes haywire
1662 * used to avoid further failures */
1664 atomic_t num_mpdus_ready
;
1666 /* This is used to group tx/rx completions separately and process them
1667 * in batches to reduce cache stalls */
1668 struct tasklet_struct txrx_compl_task
;
1669 struct sk_buff_head rx_compl_q
;
1670 struct sk_buff_head rx_in_ord_compl_q
;
1671 struct sk_buff_head tx_fetch_ind_q
;
1673 /* rx_status template */
1674 struct ieee80211_rx_status rx_status
;
1678 struct htt_msdu_ext_desc
*vaddr
;
1683 struct ath10k_htt_txbuf
*vaddr
;
1688 struct htt_q_state
*vaddr
;
1690 u16 num_push_allowed
;
1693 enum htt_tx_mode_switch_mode mode
;
1694 enum htt_q_depth_type type
;
1698 #define RX_HTT_HDR_STATUS_LEN 64
1700 /* This structure layout is programmed via rx ring setup
1701 * so that FW knows how to transfer the rx descriptor to the host.
1702 * Buffers like this are placed on the rx ring. */
1703 struct htt_rx_desc
{
1705 /* This field is filled on the host using the msdu buffer
1706 * from htt_rx_indication */
1707 struct fw_rx_desc_base fw_desc
;
1711 struct rx_attention attention
;
1712 struct rx_frag_info frag_info
;
1713 struct rx_mpdu_start mpdu_start
;
1714 struct rx_msdu_start msdu_start
;
1715 struct rx_msdu_end msdu_end
;
1716 struct rx_mpdu_end mpdu_end
;
1717 struct rx_ppdu_start ppdu_start
;
1718 struct rx_ppdu_end ppdu_end
;
1720 u8 rx_hdr_status
[RX_HTT_HDR_STATUS_LEN
];
1724 #define HTT_RX_DESC_ALIGN 8
1726 #define HTT_MAC_ADDR_LEN 6
1730 * Should be: sizeof(struct htt_host_rx_desc) + max rx MSDU size,
1731 * rounded up to a cache line size.
1733 #define HTT_RX_BUF_SIZE 1920
1734 #define HTT_RX_MSDU_SIZE (HTT_RX_BUF_SIZE - (int)sizeof(struct htt_rx_desc))
1736 /* Refill a bunch of RX buffers for each refill round so that FW/HW can handle
1737 * aggregated traffic more nicely. */
1738 #define ATH10K_HTT_MAX_NUM_REFILL 100
1741 * DMA_MAP expects the buffer to be an integral number of cache lines.
1742 * Rather than checking the actual cache line size, this code makes a
1743 * conservative estimate of what the cache line size could be.
1745 #define HTT_LOG2_MAX_CACHE_LINE_SIZE 7 /* 2^7 = 128 */
1746 #define HTT_MAX_CACHE_LINE_SIZE_MASK ((1 << HTT_LOG2_MAX_CACHE_LINE_SIZE) - 1)
1748 /* These values are default in most firmware revisions and apparently are a
1749 * sweet spot performance wise.
1751 #define ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT 3
1752 #define ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT 64
1754 int ath10k_htt_connect(struct ath10k_htt
*htt
);
1755 int ath10k_htt_init(struct ath10k
*ar
);
1756 int ath10k_htt_setup(struct ath10k_htt
*htt
);
1758 int ath10k_htt_tx_alloc(struct ath10k_htt
*htt
);
1759 void ath10k_htt_tx_free(struct ath10k_htt
*htt
);
1761 int ath10k_htt_rx_alloc(struct ath10k_htt
*htt
);
1762 int ath10k_htt_rx_ring_refill(struct ath10k
*ar
);
1763 void ath10k_htt_rx_free(struct ath10k_htt
*htt
);
1765 void ath10k_htt_htc_tx_complete(struct ath10k
*ar
, struct sk_buff
*skb
);
1766 void ath10k_htt_htc_t2h_msg_handler(struct ath10k
*ar
, struct sk_buff
*skb
);
1767 bool ath10k_htt_t2h_msg_handler(struct ath10k
*ar
, struct sk_buff
*skb
);
1768 int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt
*htt
);
1769 int ath10k_htt_h2t_stats_req(struct ath10k_htt
*htt
, u8 mask
, u64 cookie
);
1770 int ath10k_htt_send_frag_desc_bank_cfg(struct ath10k_htt
*htt
);
1771 int ath10k_htt_send_rx_ring_cfg_ll(struct ath10k_htt
*htt
);
1772 int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt
*htt
,
1773 u8 max_subfrms_ampdu
,
1774 u8 max_subfrms_amsdu
);
1775 void ath10k_htt_hif_tx_complete(struct ath10k
*ar
, struct sk_buff
*skb
);
1776 int ath10k_htt_tx_fetch_resp(struct ath10k
*ar
,
1778 __le16 fetch_seq_num
,
1779 struct htt_tx_fetch_record
*records
,
1780 size_t num_records
);
1782 void ath10k_htt_tx_txq_update(struct ieee80211_hw
*hw
,
1783 struct ieee80211_txq
*txq
);
1784 void ath10k_htt_tx_txq_recalc(struct ieee80211_hw
*hw
,
1785 struct ieee80211_txq
*txq
);
1786 void ath10k_htt_tx_txq_sync(struct ath10k
*ar
);
1787 void ath10k_htt_tx_dec_pending(struct ath10k_htt
*htt
);
1788 int ath10k_htt_tx_inc_pending(struct ath10k_htt
*htt
);
1789 void ath10k_htt_tx_mgmt_dec_pending(struct ath10k_htt
*htt
);
1790 int ath10k_htt_tx_mgmt_inc_pending(struct ath10k_htt
*htt
, bool is_mgmt
,
1793 int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt
*htt
, struct sk_buff
*skb
);
1794 void ath10k_htt_tx_free_msdu_id(struct ath10k_htt
*htt
, u16 msdu_id
);
1795 int ath10k_htt_mgmt_tx(struct ath10k_htt
*htt
, struct sk_buff
*);
1796 int ath10k_htt_tx(struct ath10k_htt
*htt
,
1797 enum ath10k_hw_txrx_mode txmode
,
1798 struct sk_buff
*msdu
);
1799 void ath10k_htt_rx_pktlog_completion_handler(struct ath10k
*ar
,
1800 struct sk_buff
*skb
);