drivers/net/wireless/ath/ath10k/hw.h

   1 /*
   2  * Copyright (c) 2005-2011 Atheros Communications Inc.
   3  * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
   4  *
   5  * Permission to use, copy, modify, and/or distribute this software for any
   6  * purpose with or without fee is hereby granted, provided that the above
   7  * copyright notice and this permission notice appear in all copies.
   8  *
   9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16  */
  17
  18 #ifndef _HW_H_
  19 #define _HW_H_
  20
  21 #include "targaddrs.h"
  22
  23 #define ATH10K_FW_DIR                   "ath10k"
  24
  25 #define QCA988X_2_0_DEVICE_ID   (0x003c)
  26 #define QCA6164_2_1_DEVICE_ID   (0x0041)
  27 #define QCA6174_2_1_DEVICE_ID   (0x003e)
  28 #define QCA99X0_2_0_DEVICE_ID   (0x0040)
  29 #define QCA9377_1_0_DEVICE_ID   (0x0042)
  30
  31 /* QCA988X 1.0 definitions (unsupported) */
  32 #define QCA988X_HW_1_0_CHIP_ID_REV      0x0
  33
  34 /* QCA988X 2.0 definitions */
  35 #define QCA988X_HW_2_0_VERSION          0x4100016c
  36 #define QCA988X_HW_2_0_CHIP_ID_REV      0x2
  37 #define QCA988X_HW_2_0_FW_DIR           ATH10K_FW_DIR "/QCA988X/hw2.0"
  38 #define QCA988X_HW_2_0_FW_FILE          "firmware.bin"
  39 #define QCA988X_HW_2_0_OTP_FILE         "otp.bin"
  40 #define QCA988X_HW_2_0_BOARD_DATA_FILE  "board.bin"
  41 #define QCA988X_HW_2_0_PATCH_LOAD_ADDR  0x1234
  42
  43 /* QCA6174 target BMI version signatures */
  44 #define QCA6174_HW_1_0_VERSION          0x05000000
  45 #define QCA6174_HW_1_1_VERSION          0x05000001
  46 #define QCA6174_HW_1_3_VERSION          0x05000003
  47 #define QCA6174_HW_2_1_VERSION          0x05010000
  48 #define QCA6174_HW_3_0_VERSION          0x05020000
  49 #define QCA6174_HW_3_2_VERSION          0x05030000
  50
  51 /* QCA9377 target BMI version signatures */
  52 #define QCA9377_HW_1_0_DEV_VERSION      0x05020000
  53 #define QCA9377_HW_1_1_DEV_VERSION      0x05020001
  54
  55 enum qca6174_pci_rev {
  56         QCA6174_PCI_REV_1_1 = 0x11,
  57         QCA6174_PCI_REV_1_3 = 0x13,
  58         QCA6174_PCI_REV_2_0 = 0x20,
  59         QCA6174_PCI_REV_3_0 = 0x30,
  60 };
  61
  62 enum qca6174_chip_id_rev {
  63         QCA6174_HW_1_0_CHIP_ID_REV = 0,
  64         QCA6174_HW_1_1_CHIP_ID_REV = 1,
  65         QCA6174_HW_1_3_CHIP_ID_REV = 2,
  66         QCA6174_HW_2_1_CHIP_ID_REV = 4,
  67         QCA6174_HW_2_2_CHIP_ID_REV = 5,
  68         QCA6174_HW_3_0_CHIP_ID_REV = 8,
  69         QCA6174_HW_3_1_CHIP_ID_REV = 9,
  70         QCA6174_HW_3_2_CHIP_ID_REV = 10,
  71 };
  72
  73 enum qca9377_chip_id_rev {
  74         QCA9377_HW_1_0_CHIP_ID_REV = 0x0,
  75         QCA9377_HW_1_1_CHIP_ID_REV = 0x1,
  76 };
  77
  78 #define QCA6174_HW_2_1_FW_DIR           "ath10k/QCA6174/hw2.1"
  79 #define QCA6174_HW_2_1_FW_FILE          "firmware.bin"
  80 #define QCA6174_HW_2_1_OTP_FILE         "otp.bin"
  81 #define QCA6174_HW_2_1_BOARD_DATA_FILE  "board.bin"
  82 #define QCA6174_HW_2_1_PATCH_LOAD_ADDR  0x1234
  83
  84 #define QCA6174_HW_3_0_FW_DIR           "ath10k/QCA6174/hw3.0"
  85 #define QCA6174_HW_3_0_FW_FILE          "firmware.bin"
  86 #define QCA6174_HW_3_0_OTP_FILE         "otp.bin"
  87 #define QCA6174_HW_3_0_BOARD_DATA_FILE  "board.bin"
  88 #define QCA6174_HW_3_0_PATCH_LOAD_ADDR  0x1234
  89
  90 /* QCA99X0 1.0 definitions (unsupported) */
  91 #define QCA99X0_HW_1_0_CHIP_ID_REV     0x0
  92
  93 /* QCA99X0 2.0 definitions */
  94 #define QCA99X0_HW_2_0_DEV_VERSION     0x01000000
  95 #define QCA99X0_HW_2_0_CHIP_ID_REV     0x1
  96 #define QCA99X0_HW_2_0_FW_DIR          ATH10K_FW_DIR "/QCA99X0/hw2.0"
  97 #define QCA99X0_HW_2_0_FW_FILE         "firmware.bin"
  98 #define QCA99X0_HW_2_0_OTP_FILE        "otp.bin"
  99 #define QCA99X0_HW_2_0_BOARD_DATA_FILE "board.bin"
 100 #define QCA99X0_HW_2_0_PATCH_LOAD_ADDR  0x1234
 101
 102 /* QCA9377 1.0 definitions */
 103 #define QCA9377_HW_1_0_FW_DIR          ATH10K_FW_DIR "/QCA9377/hw1.0"
 104 #define QCA9377_HW_1_0_FW_FILE         "firmware.bin"
 105 #define QCA9377_HW_1_0_OTP_FILE        "otp.bin"
 106 #define QCA9377_HW_1_0_BOARD_DATA_FILE "board.bin"
 107 #define QCA9377_HW_1_0_PATCH_LOAD_ADDR  0x1234
 108
 109 /* QCA4019 1.0 definitions */
 110 #define QCA4019_HW_1_0_DEV_VERSION     0x01000000
 111 #define QCA4019_HW_1_0_FW_DIR          ATH10K_FW_DIR "/QCA4019/hw1.0"
 112 #define QCA4019_HW_1_0_FW_FILE         "firmware.bin"
 113 #define QCA4019_HW_1_0_OTP_FILE        "otp.bin"
 114 #define QCA4019_HW_1_0_BOARD_DATA_FILE "board.bin"
 115 #define QCA4019_HW_1_0_PATCH_LOAD_ADDR  0x1234
 116
 117 #define ATH10K_FW_API2_FILE             "firmware-2.bin"
 118 #define ATH10K_FW_API3_FILE             "firmware-3.bin"
 119
 120 /* added support for ATH10K_FW_IE_WMI_OP_VERSION */
 121 #define ATH10K_FW_API4_FILE             "firmware-4.bin"
 122
 123 /* HTT id conflict fix for management frames over HTT */
 124 #define ATH10K_FW_API5_FILE             "firmware-5.bin"
 125
 126 #define ATH10K_FW_UTF_FILE              "utf.bin"
 127 #define ATH10K_FW_UTF_API2_FILE         "utf-2.bin"
 128
 129 /* includes also the null byte */
 130 #define ATH10K_FIRMWARE_MAGIC               "QCA-ATH10K"
 131 #define ATH10K_BOARD_MAGIC                  "QCA-ATH10K-BOARD"
 132
 133 #define ATH10K_BOARD_API2_FILE         "board-2.bin"
 134
 135 #define REG_DUMP_COUNT_QCA988X 60
 136
 137 #define QCA988X_CAL_DATA_LEN            2116
 138
 139 struct ath10k_fw_ie {
 140         __le32 id;
 141         __le32 len;
 142         u8 data[0];
 143 };
 144
 145 enum ath10k_fw_ie_type {
 146         ATH10K_FW_IE_FW_VERSION = 0,
 147         ATH10K_FW_IE_TIMESTAMP = 1,
 148         ATH10K_FW_IE_FEATURES = 2,
 149         ATH10K_FW_IE_FW_IMAGE = 3,
 150         ATH10K_FW_IE_OTP_IMAGE = 4,
 151
 152         /* WMI "operations" interface version, 32 bit value. Supported from
 153          * FW API 4 and above.
 154          */
 155         ATH10K_FW_IE_WMI_OP_VERSION = 5,
 156
 157         /* HTT "operations" interface version, 32 bit value. Supported from
 158          * FW API 5 and above.
 159          */
 160         ATH10K_FW_IE_HTT_OP_VERSION = 6,
 161
 162         /* Code swap image for firmware binary */
 163         ATH10K_FW_IE_FW_CODE_SWAP_IMAGE = 7,
 164 };
 165
 166 enum ath10k_fw_wmi_op_version {
 167         ATH10K_FW_WMI_OP_VERSION_UNSET = 0,
 168
 169         ATH10K_FW_WMI_OP_VERSION_MAIN = 1,
 170         ATH10K_FW_WMI_OP_VERSION_10_1 = 2,
 171         ATH10K_FW_WMI_OP_VERSION_10_2 = 3,
 172         ATH10K_FW_WMI_OP_VERSION_TLV = 4,
 173         ATH10K_FW_WMI_OP_VERSION_10_2_4 = 5,
 174         ATH10K_FW_WMI_OP_VERSION_10_4 = 6,
 175
 176         /* keep last */
 177         ATH10K_FW_WMI_OP_VERSION_MAX,
 178 };
 179
 180 enum ath10k_fw_htt_op_version {
 181         ATH10K_FW_HTT_OP_VERSION_UNSET = 0,
 182
 183         ATH10K_FW_HTT_OP_VERSION_MAIN = 1,
 184
 185         /* also used in 10.2 and 10.2.4 branches */
 186         ATH10K_FW_HTT_OP_VERSION_10_1 = 2,
 187
 188         ATH10K_FW_HTT_OP_VERSION_TLV = 3,
 189
 190         ATH10K_FW_HTT_OP_VERSION_10_4 = 4,
 191
 192         /* keep last */
 193         ATH10K_FW_HTT_OP_VERSION_MAX,
 194 };
 195
 196 enum ath10k_bd_ie_type {
 197         /* contains sub IEs of enum ath10k_bd_ie_board_type */
 198         ATH10K_BD_IE_BOARD = 0,
 199 };
 200
 201 enum ath10k_bd_ie_board_type {
 202         ATH10K_BD_IE_BOARD_NAME = 0,
 203         ATH10K_BD_IE_BOARD_DATA = 1,
 204 };
 205
 206 enum ath10k_hw_rev {
 207         ATH10K_HW_QCA988X,
 208         ATH10K_HW_QCA6174,
 209         ATH10K_HW_QCA99X0,
 210         ATH10K_HW_QCA9377,
 211         ATH10K_HW_QCA4019,
 212 };
 213
 214 struct ath10k_hw_regs {
 215         u32 rtc_state_cold_reset_mask;
 216         u32 rtc_soc_base_address;
 217         u32 rtc_wmac_base_address;
 218         u32 soc_core_base_address;
 219         u32 ce_wrapper_base_address;
 220         u32 ce0_base_address;
 221         u32 ce1_base_address;
 222         u32 ce2_base_address;
 223         u32 ce3_base_address;
 224         u32 ce4_base_address;
 225         u32 ce5_base_address;
 226         u32 ce6_base_address;
 227         u32 ce7_base_address;
 228         u32 soc_reset_control_si0_rst_mask;
 229         u32 soc_reset_control_ce_rst_mask;
 230         u32 soc_chip_id_address;
 231         u32 scratch_3_address;
 232         u32 fw_indicator_address;
 233         u32 pcie_local_base_address;
 234         u32 ce_wrap_intr_sum_host_msi_lsb;
 235         u32 ce_wrap_intr_sum_host_msi_mask;
 236         u32 pcie_intr_fw_mask;
 237         u32 pcie_intr_ce_mask_all;
 238         u32 pcie_intr_clr_address;
 239 };
 240
 241 extern const struct ath10k_hw_regs qca988x_regs;
 242 extern const struct ath10k_hw_regs qca6174_regs;
 243 extern const struct ath10k_hw_regs qca99x0_regs;
 244 extern const struct ath10k_hw_regs qca4019_regs;
 245
 246 struct ath10k_hw_values {
 247         u32 rtc_state_val_on;
 248         u8 ce_count;
 249         u8 msi_assign_ce_max;
 250         u8 num_target_ce_config_wlan;
 251         u16 ce_desc_meta_data_mask;
 252         u8 ce_desc_meta_data_lsb;
 253 };
 254
 255 extern const struct ath10k_hw_values qca988x_values;
 256 extern const struct ath10k_hw_values qca6174_values;
 257 extern const struct ath10k_hw_values qca99x0_values;
 258 extern const struct ath10k_hw_values qca4019_values;
 259
 260 void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
 261                                 u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev);
 262
 263 #define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X)
 264 #define QCA_REV_6174(ar) ((ar)->hw_rev == ATH10K_HW_QCA6174)
 265 #define QCA_REV_99X0(ar) ((ar)->hw_rev == ATH10K_HW_QCA99X0)
 266 #define QCA_REV_9377(ar) ((ar)->hw_rev == ATH10K_HW_QCA9377)
 267 #define QCA_REV_40XX(ar) ((ar)->hw_rev == ATH10K_HW_QCA4019)
 268
 269 /* Known pecularities:
 270  *  - raw appears in nwifi decap, raw and nwifi appear in ethernet decap
 271  *  - raw have FCS, nwifi doesn't
 272  *  - ethernet frames have 802.11 header decapped and parts (base hdr, cipher
 273  *    param, llc/snap) are aligned to 4byte boundaries each */
 274 enum ath10k_hw_txrx_mode {
 275         ATH10K_HW_TXRX_RAW = 0,
 276
 277         /* Native Wifi decap mode is used to align IP frames to 4-byte
 278          * boundaries and avoid a very expensive re-alignment in mac80211.
 279          */
 280         ATH10K_HW_TXRX_NATIVE_WIFI = 1,
 281         ATH10K_HW_TXRX_ETHERNET = 2,
 282
 283         /* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */
 284         ATH10K_HW_TXRX_MGMT = 3,
 285 };
 286
 287 enum ath10k_mcast2ucast_mode {
 288         ATH10K_MCAST2UCAST_DISABLED = 0,
 289         ATH10K_MCAST2UCAST_ENABLED = 1,
 290 };
 291
 292 struct ath10k_pktlog_hdr {
 293         __le16 flags;
 294         __le16 missed_cnt;
 295         __le16 log_type;
 296         __le16 size;
 297         __le32 timestamp;
 298         u8 payload[0];
 299 } __packed;
 300
 301 struct ath10k_pktlog_10_4_hdr {
 302         __le16 flags;
 303         __le16 missed_cnt;
 304         __le16 log_type;
 305         __le16 size;
 306         __le32 timestamp;
 307         __le32 type_specific_data;
 308         u8 payload[0];
 309 } __packed;
 310
 311 enum ath10k_hw_rate_ofdm {
 312         ATH10K_HW_RATE_OFDM_48M = 0,
 313         ATH10K_HW_RATE_OFDM_24M,
 314         ATH10K_HW_RATE_OFDM_12M,
 315         ATH10K_HW_RATE_OFDM_6M,
 316         ATH10K_HW_RATE_OFDM_54M,
 317         ATH10K_HW_RATE_OFDM_36M,
 318         ATH10K_HW_RATE_OFDM_18M,
 319         ATH10K_HW_RATE_OFDM_9M,
 320 };
 321
 322 enum ath10k_hw_rate_cck {
 323         ATH10K_HW_RATE_CCK_LP_11M = 0,
 324         ATH10K_HW_RATE_CCK_LP_5_5M,
 325         ATH10K_HW_RATE_CCK_LP_2M,
 326         ATH10K_HW_RATE_CCK_LP_1M,
 327         ATH10K_HW_RATE_CCK_SP_11M,
 328         ATH10K_HW_RATE_CCK_SP_5_5M,
 329         ATH10K_HW_RATE_CCK_SP_2M,
 330 };
 331
 332 enum ath10k_hw_4addr_pad {
 333         ATH10K_HW_4ADDR_PAD_AFTER,
 334         ATH10K_HW_4ADDR_PAD_BEFORE,
 335 };
 336
 337 /* Target specific defines for MAIN firmware */
 338 #define TARGET_NUM_VDEVS                        8
 339 #define TARGET_NUM_PEER_AST                     2
 340 #define TARGET_NUM_WDS_ENTRIES                  32
 341 #define TARGET_DMA_BURST_SIZE                   0
 342 #define TARGET_MAC_AGGR_DELIM                   0
 343 #define TARGET_AST_SKID_LIMIT                   16
 344 #define TARGET_NUM_STATIONS                     16
 345 #define TARGET_NUM_PEERS                        ((TARGET_NUM_STATIONS) + \
 346                                                  (TARGET_NUM_VDEVS))
 347 #define TARGET_NUM_OFFLOAD_PEERS                0
 348 #define TARGET_NUM_OFFLOAD_REORDER_BUFS         0
 349 #define TARGET_NUM_PEER_KEYS                    2
 350 #define TARGET_NUM_TIDS                         ((TARGET_NUM_PEERS) * 2)
 351 #define TARGET_TX_CHAIN_MASK                    (BIT(0) | BIT(1) | BIT(2))
 352 #define TARGET_RX_CHAIN_MASK                    (BIT(0) | BIT(1) | BIT(2))
 353 #define TARGET_RX_TIMEOUT_LO_PRI                100
 354 #define TARGET_RX_TIMEOUT_HI_PRI                40
 355
 356 #define TARGET_SCAN_MAX_PENDING_REQS            4
 357 #define TARGET_BMISS_OFFLOAD_MAX_VDEV           3
 358 #define TARGET_ROAM_OFFLOAD_MAX_VDEV            3
 359 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES     8
 360 #define TARGET_GTK_OFFLOAD_MAX_VDEV             3
 361 #define TARGET_NUM_MCAST_GROUPS                 0
 362 #define TARGET_NUM_MCAST_TABLE_ELEMS            0
 363 #define TARGET_MCAST2UCAST_MODE                 ATH10K_MCAST2UCAST_DISABLED
 364 #define TARGET_TX_DBG_LOG_SIZE                  1024
 365 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0
 366 #define TARGET_VOW_CONFIG                       0
 367 #define TARGET_NUM_MSDU_DESC                    (1024 + 400)
 368 #define TARGET_MAX_FRAG_ENTRIES                 0
 369
 370 /* Target specific defines for 10.X firmware */
 371 #define TARGET_10X_NUM_VDEVS                    16
 372 #define TARGET_10X_NUM_PEER_AST                 2
 373 #define TARGET_10X_NUM_WDS_ENTRIES              32
 374 #define TARGET_10X_DMA_BURST_SIZE               0
 375 #define TARGET_10X_MAC_AGGR_DELIM               0
 376 #define TARGET_10X_AST_SKID_LIMIT               128
 377 #define TARGET_10X_NUM_STATIONS                 128
 378 #define TARGET_10X_TX_STATS_NUM_STATIONS        118
 379 #define TARGET_10X_NUM_PEERS                    ((TARGET_10X_NUM_STATIONS) + \
 380                                                  (TARGET_10X_NUM_VDEVS))
 381 #define TARGET_10X_TX_STATS_NUM_PEERS           ((TARGET_10X_TX_STATS_NUM_STATIONS) + \
 382                                                  (TARGET_10X_NUM_VDEVS))
 383 #define TARGET_10X_NUM_OFFLOAD_PEERS            0
 384 #define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS     0
 385 #define TARGET_10X_NUM_PEER_KEYS                2
 386 #define TARGET_10X_NUM_TIDS_MAX                 256
 387 #define TARGET_10X_NUM_TIDS                     min((TARGET_10X_NUM_TIDS_MAX), \
 388                                                     (TARGET_10X_NUM_PEERS) * 2)
 389 #define TARGET_10X_TX_STATS_NUM_TIDS            min((TARGET_10X_NUM_TIDS_MAX), \
 390                                                     (TARGET_10X_TX_STATS_NUM_PEERS) * 2)
 391 #define TARGET_10X_TX_CHAIN_MASK                (BIT(0) | BIT(1) | BIT(2))
 392 #define TARGET_10X_RX_CHAIN_MASK                (BIT(0) | BIT(1) | BIT(2))
 393 #define TARGET_10X_RX_TIMEOUT_LO_PRI            100
 394 #define TARGET_10X_RX_TIMEOUT_HI_PRI            40
 395 #define TARGET_10X_SCAN_MAX_PENDING_REQS        4
 396 #define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV       2
 397 #define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV        2
 398 #define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES 8
 399 #define TARGET_10X_GTK_OFFLOAD_MAX_VDEV         3
 400 #define TARGET_10X_NUM_MCAST_GROUPS             0
 401 #define TARGET_10X_NUM_MCAST_TABLE_ELEMS        0
 402 #define TARGET_10X_MCAST2UCAST_MODE             ATH10K_MCAST2UCAST_DISABLED
 403 #define TARGET_10X_TX_DBG_LOG_SIZE              1024
 404 #define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
 405 #define TARGET_10X_VOW_CONFIG                   0
 406 #define TARGET_10X_NUM_MSDU_DESC                (1024 + 400)
 407 #define TARGET_10X_MAX_FRAG_ENTRIES             0
 408
 409 /* 10.2 parameters */
 410 #define TARGET_10_2_DMA_BURST_SIZE              0
 411
 412 /* Target specific defines for WMI-TLV firmware */
 413 #define TARGET_TLV_NUM_VDEVS                    4
 414 #define TARGET_TLV_NUM_STATIONS                 32
 415 #define TARGET_TLV_NUM_PEERS                    35
 416 #define TARGET_TLV_NUM_TDLS_VDEVS               1
 417 #define TARGET_TLV_NUM_TIDS                     ((TARGET_TLV_NUM_PEERS) * 2)
 418 #define TARGET_TLV_NUM_MSDU_DESC                (1024 + 32)
 419 #define TARGET_TLV_NUM_WOW_PATTERNS             22
 420
 421 /* Diagnostic Window */
 422 #define CE_DIAG_PIPE    7
 423
 424 #define NUM_TARGET_CE_CONFIG_WLAN ar->hw_values->num_target_ce_config_wlan
 425
 426 /* Target specific defines for 10.4 firmware */
 427 #define TARGET_10_4_NUM_VDEVS                   16
 428 #define TARGET_10_4_NUM_STATIONS                32
 429 #define TARGET_10_4_NUM_PEERS                   ((TARGET_10_4_NUM_STATIONS) + \
 430                                                  (TARGET_10_4_NUM_VDEVS))
 431 #define TARGET_10_4_ACTIVE_PEERS                0
 432
 433 #define TARGET_10_4_NUM_QCACHE_PEERS_MAX        512
 434 #define TARGET_10_4_NUM_OFFLOAD_PEERS           0
 435 #define TARGET_10_4_NUM_OFFLOAD_REORDER_BUFFS   0
 436 #define TARGET_10_4_NUM_PEER_KEYS               2
 437 #define TARGET_10_4_TGT_NUM_TIDS                ((TARGET_10_4_NUM_PEERS) * 2)
 438 #define TARGET_10_4_AST_SKID_LIMIT              32
 439
 440 /* 100 ms for video, best-effort, and background */
 441 #define TARGET_10_4_RX_TIMEOUT_LO_PRI           100
 442
 443 /* 40 ms for voice */
 444 #define TARGET_10_4_RX_TIMEOUT_HI_PRI           40
 445
 446 #define TARGET_10_4_RX_DECAP_MODE               ATH10K_HW_TXRX_NATIVE_WIFI
 447 #define TARGET_10_4_SCAN_MAX_REQS               4
 448 #define TARGET_10_4_BMISS_OFFLOAD_MAX_VDEV      3
 449 #define TARGET_10_4_ROAM_OFFLOAD_MAX_VDEV       3
 450 #define TARGET_10_4_ROAM_OFFLOAD_MAX_PROFILES   8
 451
 452 /* Note: mcast to ucast is disabled by default */
 453 #define TARGET_10_4_NUM_MCAST_GROUPS            0
 454 #define TARGET_10_4_NUM_MCAST_TABLE_ELEMS       0
 455 #define TARGET_10_4_MCAST2UCAST_MODE            0
 456
 457 #define TARGET_10_4_TX_DBG_LOG_SIZE             1024
 458 #define TARGET_10_4_NUM_WDS_ENTRIES             32
 459 #define TARGET_10_4_DMA_BURST_SIZE              0
 460 #define TARGET_10_4_MAC_AGGR_DELIM              0
 461 #define TARGET_10_4_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
 462 #define TARGET_10_4_VOW_CONFIG                  0
 463 #define TARGET_10_4_GTK_OFFLOAD_MAX_VDEV        3
 464 #define TARGET_10_4_11AC_TX_MAX_FRAGS           2
 465 #define TARGET_10_4_MAX_PEER_EXT_STATS          16
 466 #define TARGET_10_4_SMART_ANT_CAP               0
 467 #define TARGET_10_4_BK_MIN_FREE                 0
 468 #define TARGET_10_4_BE_MIN_FREE                 0
 469 #define TARGET_10_4_VI_MIN_FREE                 0
 470 #define TARGET_10_4_VO_MIN_FREE                 0
 471 #define TARGET_10_4_RX_BATCH_MODE               1
 472 #define TARGET_10_4_THERMAL_THROTTLING_CONFIG   0
 473 #define TARGET_10_4_ATF_CONFIG                  0
 474 #define TARGET_10_4_IPHDR_PAD_CONFIG            1
 475 #define TARGET_10_4_QWRAP_CONFIG                0
 476
 477 /* Number of Copy Engines supported */
 478 #define CE_COUNT ar->hw_values->ce_count
 479
 480 /*
 481  * Granted MSIs are assigned as follows:
 482  * Firmware uses the first
 483  * Remaining MSIs, if any, are used by Copy Engines
 484  * This mapping is known to both Target firmware and Host software.
 485  * It may be changed as long as Host and Target are kept in sync.
 486  */
 487 /* MSI for firmware (errors, etc.) */
 488 #define MSI_ASSIGN_FW           0
 489
 490 /* MSIs for Copy Engines */
 491 #define MSI_ASSIGN_CE_INITIAL   1
 492 #define MSI_ASSIGN_CE_MAX       ar->hw_values->msi_assign_ce_max
 493
 494 /* as of IP3.7.1 */
 495 #define RTC_STATE_V_ON                          ar->hw_values->rtc_state_val_on
 496
 497 #define RTC_STATE_COLD_RESET_MASK               ar->regs->rtc_state_cold_reset_mask
 498 #define RTC_STATE_V_LSB                         0
 499 #define RTC_STATE_V_MASK                        0x00000007
 500 #define RTC_STATE_ADDRESS                       0x0000
 501 #define PCIE_SOC_WAKE_V_MASK                    0x00000001
 502 #define PCIE_SOC_WAKE_ADDRESS                   0x0004
 503 #define PCIE_SOC_WAKE_RESET                     0x00000000
 504 #define SOC_GLOBAL_RESET_ADDRESS                0x0008
 505
 506 #define RTC_SOC_BASE_ADDRESS                    ar->regs->rtc_soc_base_address
 507 #define RTC_WMAC_BASE_ADDRESS                   ar->regs->rtc_wmac_base_address
 508 #define MAC_COEX_BASE_ADDRESS                   0x00006000
 509 #define BT_COEX_BASE_ADDRESS                    0x00007000
 510 #define SOC_PCIE_BASE_ADDRESS                   0x00008000
 511 #define SOC_CORE_BASE_ADDRESS                   ar->regs->soc_core_base_address
 512 #define WLAN_UART_BASE_ADDRESS                  0x0000c000
 513 #define WLAN_SI_BASE_ADDRESS                    0x00010000
 514 #define WLAN_GPIO_BASE_ADDRESS                  0x00014000
 515 #define WLAN_ANALOG_INTF_BASE_ADDRESS           0x0001c000
 516 #define WLAN_MAC_BASE_ADDRESS                   0x00020000
 517 #define EFUSE_BASE_ADDRESS                      0x00030000
 518 #define FPGA_REG_BASE_ADDRESS                   0x00039000
 519 #define WLAN_UART2_BASE_ADDRESS                 0x00054c00
 520 #define CE_WRAPPER_BASE_ADDRESS                 ar->regs->ce_wrapper_base_address
 521 #define CE0_BASE_ADDRESS                        ar->regs->ce0_base_address
 522 #define CE1_BASE_ADDRESS                        ar->regs->ce1_base_address
 523 #define CE2_BASE_ADDRESS                        ar->regs->ce2_base_address
 524 #define CE3_BASE_ADDRESS                        ar->regs->ce3_base_address
 525 #define CE4_BASE_ADDRESS                        ar->regs->ce4_base_address
 526 #define CE5_BASE_ADDRESS                        ar->regs->ce5_base_address
 527 #define CE6_BASE_ADDRESS                        ar->regs->ce6_base_address
 528 #define CE7_BASE_ADDRESS                        ar->regs->ce7_base_address
 529 #define DBI_BASE_ADDRESS                        0x00060000
 530 #define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS      0x0006c000
 531 #define PCIE_LOCAL_BASE_ADDRESS         ar->regs->pcie_local_base_address
 532
 533 #define SOC_RESET_CONTROL_ADDRESS               0x00000000
 534 #define SOC_RESET_CONTROL_OFFSET                0x00000000
 535 #define SOC_RESET_CONTROL_SI0_RST_MASK          ar->regs->soc_reset_control_si0_rst_mask
 536 #define SOC_RESET_CONTROL_CE_RST_MASK           ar->regs->soc_reset_control_ce_rst_mask
 537 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK     0x00000040
 538 #define SOC_CPU_CLOCK_OFFSET                    0x00000020
 539 #define SOC_CPU_CLOCK_STANDARD_LSB              0
 540 #define SOC_CPU_CLOCK_STANDARD_MASK             0x00000003
 541 #define SOC_CLOCK_CONTROL_OFFSET                0x00000028
 542 #define SOC_CLOCK_CONTROL_SI0_CLK_MASK          0x00000001
 543 #define SOC_SYSTEM_SLEEP_OFFSET                 0x000000c4
 544 #define SOC_LPO_CAL_OFFSET                      0x000000e0
 545 #define SOC_LPO_CAL_ENABLE_LSB                  20
 546 #define SOC_LPO_CAL_ENABLE_MASK                 0x00100000
 547 #define SOC_LF_TIMER_CONTROL0_ADDRESS           0x00000050
 548 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK       0x00000004
 549
 550 #define SOC_CHIP_ID_ADDRESS                     ar->regs->soc_chip_id_address
 551 #define SOC_CHIP_ID_REV_LSB                     8
 552 #define SOC_CHIP_ID_REV_MASK                    0x00000f00
 553
 554 #define WLAN_RESET_CONTROL_COLD_RST_MASK        0x00000008
 555 #define WLAN_RESET_CONTROL_WARM_RST_MASK        0x00000004
 556 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB           0
 557 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK          0x00000001
 558
 559 #define WLAN_GPIO_PIN0_ADDRESS                  0x00000028
 560 #define WLAN_GPIO_PIN0_CONFIG_MASK              0x00007800
 561 #define WLAN_GPIO_PIN1_ADDRESS                  0x0000002c
 562 #define WLAN_GPIO_PIN1_CONFIG_MASK              0x00007800
 563 #define WLAN_GPIO_PIN10_ADDRESS                 0x00000050
 564 #define WLAN_GPIO_PIN11_ADDRESS                 0x00000054
 565 #define WLAN_GPIO_PIN12_ADDRESS                 0x00000058
 566 #define WLAN_GPIO_PIN13_ADDRESS                 0x0000005c
 567
 568 #define CLOCK_GPIO_OFFSET                       0xffffffff
 569 #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB            0
 570 #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK           0
 571
 572 #define SI_CONFIG_OFFSET                        0x00000000
 573 #define SI_CONFIG_BIDIR_OD_DATA_LSB             18
 574 #define SI_CONFIG_BIDIR_OD_DATA_MASK            0x00040000
 575 #define SI_CONFIG_I2C_LSB                       16
 576 #define SI_CONFIG_I2C_MASK                      0x00010000
 577 #define SI_CONFIG_POS_SAMPLE_LSB                7
 578 #define SI_CONFIG_POS_SAMPLE_MASK               0x00000080
 579 #define SI_CONFIG_INACTIVE_DATA_LSB             5
 580 #define SI_CONFIG_INACTIVE_DATA_MASK            0x00000020
 581 #define SI_CONFIG_INACTIVE_CLK_LSB              4
 582 #define SI_CONFIG_INACTIVE_CLK_MASK             0x00000010
 583 #define SI_CONFIG_DIVIDER_LSB                   0
 584 #define SI_CONFIG_DIVIDER_MASK                  0x0000000f
 585 #define SI_CS_OFFSET                            0x00000004
 586 #define SI_CS_DONE_ERR_MASK                     0x00000400
 587 #define SI_CS_DONE_INT_MASK                     0x00000200
 588 #define SI_CS_START_LSB                         8
 589 #define SI_CS_START_MASK                        0x00000100
 590 #define SI_CS_RX_CNT_LSB                        4
 591 #define SI_CS_RX_CNT_MASK                       0x000000f0
 592 #define SI_CS_TX_CNT_LSB                        0
 593 #define SI_CS_TX_CNT_MASK                       0x0000000f
 594
 595 #define SI_TX_DATA0_OFFSET                      0x00000008
 596 #define SI_TX_DATA1_OFFSET                      0x0000000c
 597 #define SI_RX_DATA0_OFFSET                      0x00000010
 598 #define SI_RX_DATA1_OFFSET                      0x00000014
 599
 600 #define CORE_CTRL_CPU_INTR_MASK                 0x00002000
 601 #define CORE_CTRL_PCIE_REG_31_MASK              0x00000800
 602 #define CORE_CTRL_ADDRESS                       0x0000
 603 #define PCIE_INTR_ENABLE_ADDRESS                0x0008
 604 #define PCIE_INTR_CAUSE_ADDRESS                 0x000c
 605 #define PCIE_INTR_CLR_ADDRESS                   ar->regs->pcie_intr_clr_address
 606 #define SCRATCH_3_ADDRESS                       ar->regs->scratch_3_address
 607 #define CPU_INTR_ADDRESS                        0x0010
 608
 609 #define CCNT_TO_MSEC(ar, x) ((x) / ar->hw_params.channel_counters_freq_hz)
 610
 611 /* Firmware indications to the Host via SCRATCH_3 register. */
 612 #define FW_INDICATOR_ADDRESS                    ar->regs->fw_indicator_address
 613 #define FW_IND_EVENT_PENDING                    1
 614 #define FW_IND_INITIALIZED                      2
 615 #define FW_IND_HOST_READY                       0x80000000
 616
 617 /* HOST_REG interrupt from firmware */
 618 #define PCIE_INTR_FIRMWARE_MASK                 ar->regs->pcie_intr_fw_mask
 619 #define PCIE_INTR_CE_MASK_ALL                   ar->regs->pcie_intr_ce_mask_all
 620
 621 #define DRAM_BASE_ADDRESS                       0x00400000
 622
 623 #define PCIE_BAR_REG_ADDRESS                    0x40030
 624
 625 #define MISSING 0
 626
 627 #define SYSTEM_SLEEP_OFFSET                     SOC_SYSTEM_SLEEP_OFFSET
 628 #define WLAN_SYSTEM_SLEEP_OFFSET                SOC_SYSTEM_SLEEP_OFFSET
 629 #define WLAN_RESET_CONTROL_OFFSET               SOC_RESET_CONTROL_OFFSET
 630 #define CLOCK_CONTROL_OFFSET                    SOC_CLOCK_CONTROL_OFFSET
 631 #define CLOCK_CONTROL_SI0_CLK_MASK              SOC_CLOCK_CONTROL_SI0_CLK_MASK
 632 #define RESET_CONTROL_MBOX_RST_MASK             MISSING
 633 #define RESET_CONTROL_SI0_RST_MASK              SOC_RESET_CONTROL_SI0_RST_MASK
 634 #define GPIO_BASE_ADDRESS                       WLAN_GPIO_BASE_ADDRESS
 635 #define GPIO_PIN0_OFFSET                        WLAN_GPIO_PIN0_ADDRESS
 636 #define GPIO_PIN1_OFFSET                        WLAN_GPIO_PIN1_ADDRESS
 637 #define GPIO_PIN0_CONFIG_MASK                   WLAN_GPIO_PIN0_CONFIG_MASK
 638 #define GPIO_PIN1_CONFIG_MASK                   WLAN_GPIO_PIN1_CONFIG_MASK
 639 #define SI_BASE_ADDRESS                         WLAN_SI_BASE_ADDRESS
 640 #define SCRATCH_BASE_ADDRESS                    SOC_CORE_BASE_ADDRESS
 641 #define LOCAL_SCRATCH_OFFSET                    0x18
 642 #define CPU_CLOCK_OFFSET                        SOC_CPU_CLOCK_OFFSET
 643 #define LPO_CAL_OFFSET                          SOC_LPO_CAL_OFFSET
 644 #define GPIO_PIN10_OFFSET                       WLAN_GPIO_PIN10_ADDRESS
 645 #define GPIO_PIN11_OFFSET                       WLAN_GPIO_PIN11_ADDRESS
 646 #define GPIO_PIN12_OFFSET                       WLAN_GPIO_PIN12_ADDRESS
 647 #define GPIO_PIN13_OFFSET                       WLAN_GPIO_PIN13_ADDRESS
 648 #define CPU_CLOCK_STANDARD_LSB                  SOC_CPU_CLOCK_STANDARD_LSB
 649 #define CPU_CLOCK_STANDARD_MASK                 SOC_CPU_CLOCK_STANDARD_MASK
 650 #define LPO_CAL_ENABLE_LSB                      SOC_LPO_CAL_ENABLE_LSB
 651 #define LPO_CAL_ENABLE_MASK                     SOC_LPO_CAL_ENABLE_MASK
 652 #define ANALOG_INTF_BASE_ADDRESS                WLAN_ANALOG_INTF_BASE_ADDRESS
 653 #define MBOX_BASE_ADDRESS                       MISSING
 654 #define INT_STATUS_ENABLE_ERROR_LSB             MISSING
 655 #define INT_STATUS_ENABLE_ERROR_MASK            MISSING
 656 #define INT_STATUS_ENABLE_CPU_LSB               MISSING
 657 #define INT_STATUS_ENABLE_CPU_MASK              MISSING
 658 #define INT_STATUS_ENABLE_COUNTER_LSB           MISSING
 659 #define INT_STATUS_ENABLE_COUNTER_MASK          MISSING
 660 #define INT_STATUS_ENABLE_MBOX_DATA_LSB         MISSING
 661 #define INT_STATUS_ENABLE_MBOX_DATA_MASK        MISSING
 662 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB    MISSING
 663 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK   MISSING
 664 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB     MISSING
 665 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK    MISSING
 666 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB       MISSING
 667 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK      MISSING
 668 #define INT_STATUS_ENABLE_ADDRESS               MISSING
 669 #define CPU_INT_STATUS_ENABLE_BIT_LSB           MISSING
 670 #define CPU_INT_STATUS_ENABLE_BIT_MASK          MISSING
 671 #define HOST_INT_STATUS_ADDRESS                 MISSING
 672 #define CPU_INT_STATUS_ADDRESS                  MISSING
 673 #define ERROR_INT_STATUS_ADDRESS                MISSING
 674 #define ERROR_INT_STATUS_WAKEUP_MASK            MISSING
 675 #define ERROR_INT_STATUS_WAKEUP_LSB             MISSING
 676 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK      MISSING
 677 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB       MISSING
 678 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK       MISSING
 679 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB        MISSING
 680 #define COUNT_DEC_ADDRESS                       MISSING
 681 #define HOST_INT_STATUS_CPU_MASK                MISSING
 682 #define HOST_INT_STATUS_CPU_LSB                 MISSING
 683 #define HOST_INT_STATUS_ERROR_MASK              MISSING
 684 #define HOST_INT_STATUS_ERROR_LSB               MISSING
 685 #define HOST_INT_STATUS_COUNTER_MASK            MISSING
 686 #define HOST_INT_STATUS_COUNTER_LSB             MISSING
 687 #define RX_LOOKAHEAD_VALID_ADDRESS              MISSING
 688 #define WINDOW_DATA_ADDRESS                     MISSING
 689 #define WINDOW_READ_ADDR_ADDRESS                MISSING
 690 #define WINDOW_WRITE_ADDR_ADDRESS               MISSING
 691
 692 #define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB)
 693
 694 #endif /* _HW_H_ */