drivers/net/wireless/ath/ath10k/pci.h

   1 /*
   2  * Copyright (c) 2005-2011 Atheros Communications Inc.
   3  * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
   4  *
   5  * Permission to use, copy, modify, and/or distribute this software for any
   6  * purpose with or without fee is hereby granted, provided that the above
   7  * copyright notice and this permission notice appear in all copies.
   8  *
   9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16  */
  17
  18 #ifndef _PCI_H_
  19 #define _PCI_H_
  20
  21 #include <linux/interrupt.h>
  22
  23 #include "hw.h"
  24 #include "ce.h"
  25
  26 /*
  27  * maximum number of bytes that can be handled atomically by DiagRead/DiagWrite
  28  */
  29 #define DIAG_TRANSFER_LIMIT 2048
  30
  31 /*
  32  * maximum number of bytes that can be
  33  * handled atomically by DiagRead/DiagWrite
  34  */
  35 #define DIAG_TRANSFER_LIMIT 2048
  36
  37 struct bmi_xfer {
  38         bool tx_done;
  39         bool rx_done;
  40         bool wait_for_resp;
  41         u32 resp_len;
  42 };
  43
  44 /*
  45  * PCI-specific Target state
  46  *
  47  * NOTE: Structure is shared between Host software and Target firmware!
  48  *
  49  * Much of this may be of interest to the Host so
  50  * HOST_INTEREST->hi_interconnect_state points here
  51  * (and all members are 32-bit quantities in order to
  52  * facilitate Host access). In particular, Host software is
  53  * required to initialize pipe_cfg_addr and svc_to_pipe_map.
  54  */
  55 struct pcie_state {
  56         /* Pipe configuration Target address */
  57         /* NB: ce_pipe_config[CE_COUNT] */
  58         u32 pipe_cfg_addr;
  59
  60         /* Service to pipe map Target address */
  61         /* NB: service_to_pipe[PIPE_TO_CE_MAP_CN] */
  62         u32 svc_to_pipe_map;
  63
  64         /* number of MSI interrupts requested */
  65         u32 msi_requested;
  66
  67         /* number of MSI interrupts granted */
  68         u32 msi_granted;
  69
  70         /* Message Signalled Interrupt address */
  71         u32 msi_addr;
  72
  73         /* Base data */
  74         u32 msi_data;
  75
  76         /*
  77          * Data for firmware interrupt;
  78          * MSI data for other interrupts are
  79          * in various SoC registers
  80          */
  81         u32 msi_fw_intr_data;
  82
  83         /* PCIE_PWR_METHOD_* */
  84         u32 power_mgmt_method;
  85
  86         /* PCIE_CONFIG_FLAG_* */
  87         u32 config_flags;
  88 };
  89
  90 /* PCIE_CONFIG_FLAG definitions */
  91 #define PCIE_CONFIG_FLAG_ENABLE_L1  0x0000001
  92
  93 /* Host software's Copy Engine configuration. */
  94 #define CE_ATTR_FLAGS 0
  95
  96 /*
  97  * Configuration information for a Copy Engine pipe.
  98  * Passed from Host to Target during startup (one per CE).
  99  *
 100  * NOTE: Structure is shared between Host software and Target firmware!
 101  */
 102 struct ce_pipe_config {
 103         __le32 pipenum;
 104         __le32 pipedir;
 105         __le32 nentries;
 106         __le32 nbytes_max;
 107         __le32 flags;
 108         __le32 reserved;
 109 };
 110
 111 /*
 112  * Directions for interconnect pipe configuration.
 113  * These definitions may be used during configuration and are shared
 114  * between Host and Target.
 115  *
 116  * Pipe Directions are relative to the Host, so PIPEDIR_IN means
 117  * "coming IN over air through Target to Host" as with a WiFi Rx operation.
 118  * Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air"
 119  * as with a WiFi Tx operation. This is somewhat awkward for the "middle-man"
 120  * Target since things that are "PIPEDIR_OUT" are coming IN to the Target
 121  * over the interconnect.
 122  */
 123 #define PIPEDIR_NONE    0
 124 #define PIPEDIR_IN      1  /* Target-->Host, WiFi Rx direction */
 125 #define PIPEDIR_OUT     2  /* Host->Target, WiFi Tx direction */
 126 #define PIPEDIR_INOUT   3  /* bidirectional */
 127
 128 /* Establish a mapping between a service/direction and a pipe. */
 129 struct service_to_pipe {
 130         __le32 service_id;
 131         __le32 pipedir;
 132         __le32 pipenum;
 133 };
 134
 135 /* Per-pipe state. */
 136 struct ath10k_pci_pipe {
 137         /* Handle of underlying Copy Engine */
 138         struct ath10k_ce_pipe *ce_hdl;
 139
 140         /* Our pipe number; facilitiates use of pipe_info ptrs. */
 141         u8 pipe_num;
 142
 143         /* Convenience back pointer to hif_ce_state. */
 144         struct ath10k *hif_ce_state;
 145
 146         size_t buf_sz;
 147
 148         /* protects compl_free and num_send_allowed */
 149         spinlock_t pipe_lock;
 150
 151         struct ath10k_pci *ar_pci;
 152         struct tasklet_struct intr;
 153 };
 154
 155 struct ath10k_pci {
 156         struct pci_dev *pdev;
 157         struct device *dev;
 158         struct ath10k *ar;
 159         void __iomem *mem;
 160
 161         /*
 162          * Number of MSI interrupts granted, 0 --> using legacy PCI line
 163          * interrupts.
 164          */
 165         int num_msi_intrs;
 166
 167         struct tasklet_struct intr_tq;
 168         struct tasklet_struct msi_fw_err;
 169
 170         struct ath10k_pci_pipe pipe_info[CE_COUNT_MAX];
 171
 172         struct ath10k_hif_cb msg_callbacks_current;
 173
 174         /* Copy Engine used for Diagnostic Accesses */
 175         struct ath10k_ce_pipe *ce_diag;
 176
 177         /* FIXME: document what this really protects */
 178         spinlock_t ce_lock;
 179
 180         /* Map CE id to ce_state */
 181         struct ath10k_ce_pipe ce_states[CE_COUNT_MAX];
 182         struct timer_list rx_post_retry;
 183 };
 184
 185 static inline struct ath10k_pci *ath10k_pci_priv(struct ath10k *ar)
 186 {
 187         return (struct ath10k_pci *)ar->drv_priv;
 188 }
 189
 190 #define ATH10K_PCI_RX_POST_RETRY_MS 50
 191 #define ATH_PCI_RESET_WAIT_MAX 10 /* ms */
 192 #define PCIE_WAKE_TIMEOUT 5000  /* 5ms */
 193
 194 #define BAR_NUM 0
 195
 196 #define CDC_WAR_MAGIC_STR   0xceef0000
 197 #define CDC_WAR_DATA_CE     4
 198
 199 /*
 200  * TODO: Should be a function call specific to each Target-type.
 201  * This convoluted macro converts from Target CPU Virtual Address Space to CE
 202  * Address Space. As part of this process, we conservatively fetch the current
 203  * PCIE_BAR. MOST of the time, this should match the upper bits of PCI space
 204  * for this device; but that's not guaranteed.
 205  */
 206 #define TARG_CPU_SPACE_TO_CE_SPACE(ar, pci_addr, addr)                  \
 207         (((ioread32((pci_addr)+(SOC_CORE_BASE_ADDRESS|                  \
 208           CORE_CTRL_ADDRESS)) & 0x7ff) << 21) |                         \
 209          0x100000 | ((addr) & 0xfffff))
 210
 211 /* Wait up to this many Ms for a Diagnostic Access CE operation to complete */
 212 #define DIAG_ACCESS_CE_TIMEOUT_MS 10
 213
 214 /* Target exposes its registers for direct access. However before host can
 215  * access them it needs to make sure the target is awake (ath10k_pci_wake,
 216  * ath10k_pci_wake_wait, ath10k_pci_is_awake). Once target is awake it won't go
 217  * to sleep unless host tells it to (ath10k_pci_sleep).
 218  *
 219  * If host tries to access target registers without waking it up it can
 220  * scribble over host memory.
 221  *
 222  * If target is asleep waking it up may take up to even 2ms.
 223  */
 224
 225 static inline void ath10k_pci_write32(struct ath10k *ar, u32 offset,
 226                                       u32 value)
 227 {
 228         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 229
 230         iowrite32(value, ar_pci->mem + offset);
 231 }
 232
 233 static inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset)
 234 {
 235         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 236
 237         return ioread32(ar_pci->mem + offset);
 238 }
 239
 240 static inline u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr)
 241 {
 242         return ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + addr);
 243 }
 244
 245 static inline void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val)
 246 {
 247         ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val);
 248 }
 249
 250 static inline u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr)
 251 {
 252         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 253
 254         return ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + addr);
 255 }
 256
 257 static inline void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val)
 258 {
 259         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 260
 261         iowrite32(val, ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + addr);
 262 }
 263
 264 #endif /* _PCI_H_ */