2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 /* TODO: Clean up channel debuging -doesn't work anyway- and start
22 * working on reg. control code using all available eeprom information
23 * -rev. engineering needed- */
27 #include <linux/types.h>
28 #include <net/mac80211.h>
32 /* RX/TX descriptor hw structs
33 * TODO: Driver part should only see sw structs */
36 /* EEPROM structs/offsets
37 * TODO: Make a more generic struct (eg. add more stuff to ath5k_capabilities)
38 * and clean up common bits, then introduce set/get functions in eeprom.c */
42 #define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */
43 #define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */
44 #define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */
45 #define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */
46 #define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */
47 #define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */
48 #define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */
49 #define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */
50 #define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */
51 #define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */
52 #define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */
53 #define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */
54 #define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */
55 #define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */
56 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
57 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
58 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */
59 #define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */
60 #define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */
61 #define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */
62 #define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */
63 #define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */
64 #define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */
65 #define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */
66 #define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */
67 #define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */
68 #define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */
69 #define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */
71 /****************************\
72 GENERIC DRIVER DEFINITIONS
73 \****************************/
75 #define ATH5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__)
77 #define ATH5K_PRINTK(_sc, _level, _fmt, ...) \
78 printk(_level "ath5k %s: " _fmt, \
79 ((_sc) && (_sc)->hw) ? wiphy_name((_sc)->hw->wiphy) : "", \
82 #define ATH5K_PRINTK_LIMIT(_sc, _level, _fmt, ...) do { \
83 if (net_ratelimit()) \
84 ATH5K_PRINTK(_sc, _level, _fmt, ##__VA_ARGS__); \
87 #define ATH5K_INFO(_sc, _fmt, ...) \
88 ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__)
90 #define ATH5K_WARN(_sc, _fmt, ...) \
91 ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__)
93 #define ATH5K_ERR(_sc, _fmt, ...) \
94 ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__)
97 * AR5K REGISTER ACCESS
100 /* Some macros to read/write fields */
102 /* First shift, then mask */
103 #define AR5K_REG_SM(_val, _flags) \
104 (((_val) << _flags##_S) & (_flags))
106 /* First mask, then shift */
107 #define AR5K_REG_MS(_val, _flags) \
108 (((_val) & (_flags)) >> _flags##_S)
110 /* Some registers can hold multiple values of interest. For this
111 * reason when we want to write to these registers we must first
112 * retrieve the values which we do not want to clear (lets call this
113 * old_data) and then set the register with this and our new_value:
114 * ( old_data | new_value) */
115 #define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \
116 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
117 (((_val) << _flags##_S) & (_flags)), _reg)
119 #define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \
120 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \
121 (_mask)) | (_flags), _reg)
123 #define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \
124 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)
126 #define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \
127 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)
129 /* Access to PHY registers */
130 #define AR5K_PHY_READ(ah, _reg) \
131 ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2))
133 #define AR5K_PHY_WRITE(ah, _reg, _val) \
134 ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2))
136 /* Access QCU registers per queue */
137 #define AR5K_REG_READ_Q(ah, _reg, _queue) \
138 (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \
140 #define AR5K_REG_WRITE_Q(ah, _reg, _queue) \
141 ath5k_hw_reg_write(ah, (1 << _queue), _reg)
143 #define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \
144 _reg |= 1 << _queue; \
147 #define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \
148 _reg &= ~(1 << _queue); \
151 /* Used while writing initvals */
152 #define AR5K_REG_WAIT(_i) do { \
157 /* Register dumps are done per operation mode */
158 #define AR5K_INI_RFGAIN_5GHZ 0
159 #define AR5K_INI_RFGAIN_2GHZ 1
161 /* TODO: Clean this up */
162 #define AR5K_INI_VAL_11A 0
163 #define AR5K_INI_VAL_11A_TURBO 1
164 #define AR5K_INI_VAL_11B 2
165 #define AR5K_INI_VAL_11G 3
166 #define AR5K_INI_VAL_11G_TURBO 4
167 #define AR5K_INI_VAL_XR 0
168 #define AR5K_INI_VAL_MAX 5
170 /* Used for BSSID etc manipulation */
171 #define AR5K_LOW_ID(_a)( \
172 (_a)[0] | (_a)[1] << 8 | (_a)[2] << 16 | (_a)[3] << 24 \
175 #define AR5K_HIGH_ID(_a) ((_a)[4] | (_a)[5] << 8)
178 * Some tuneable values (these should be changeable by the user)
179 * TODO: Make use of them and add more options OR use debug/configfs
181 #define AR5K_TUNE_DMA_BEACON_RESP 2
182 #define AR5K_TUNE_SW_BEACON_RESP 10
183 #define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0
184 #define AR5K_TUNE_RADAR_ALERT false
185 #define AR5K_TUNE_MIN_TX_FIFO_THRES 1
186 #define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_LEN / 64) + 1)
187 #define AR5K_TUNE_REGISTER_TIMEOUT 20000
188 /* Register for RSSI threshold has a mask of 0xff, so 255 seems to
189 * be the max value. */
190 #define AR5K_TUNE_RSSI_THRES 129
191 /* This must be set when setting the RSSI threshold otherwise it can
192 * prevent a reset. If AR5K_RSSI_THR is read after writing to it
193 * the BMISS_THRES will be seen as 0, seems harware doesn't keep
194 * track of it. Max value depends on harware. For AR5210 this is just 7.
195 * For AR5211+ this seems to be up to 255. */
196 #define AR5K_TUNE_BMISS_THRES 7
197 #define AR5K_TUNE_REGISTER_DWELL_TIME 20000
198 #define AR5K_TUNE_BEACON_INTERVAL 100
199 #define AR5K_TUNE_AIFS 2
200 #define AR5K_TUNE_AIFS_11B 2
201 #define AR5K_TUNE_AIFS_XR 0
202 #define AR5K_TUNE_CWMIN 15
203 #define AR5K_TUNE_CWMIN_11B 31
204 #define AR5K_TUNE_CWMIN_XR 3
205 #define AR5K_TUNE_CWMAX 1023
206 #define AR5K_TUNE_CWMAX_11B 1023
207 #define AR5K_TUNE_CWMAX_XR 7
208 #define AR5K_TUNE_NOISE_FLOOR -72
209 #define AR5K_TUNE_MAX_TXPOWER 63
210 #define AR5K_TUNE_DEFAULT_TXPOWER 25
211 #define AR5K_TUNE_TPC_TXPOWER false
212 #define AR5K_TUNE_HWTXTRIES 4
214 #define AR5K_INIT_CARR_SENSE_EN 1
216 /*Swap RX/TX Descriptor for big endian archs*/
217 #if defined(__BIG_ENDIAN)
218 #define AR5K_INIT_CFG ( \
219 AR5K_CFG_SWTD | AR5K_CFG_SWRD \
222 #define AR5K_INIT_CFG 0x00000000
226 #define AR5K_INIT_CYCRSSI_THR1 2
227 #define AR5K_INIT_TX_LATENCY 502
228 #define AR5K_INIT_USEC 39
229 #define AR5K_INIT_USEC_TURBO 79
230 #define AR5K_INIT_USEC_32 31
231 #define AR5K_INIT_SLOT_TIME 396
232 #define AR5K_INIT_SLOT_TIME_TURBO 480
233 #define AR5K_INIT_ACK_CTS_TIMEOUT 1024
234 #define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800
235 #define AR5K_INIT_PROG_IFS 920
236 #define AR5K_INIT_PROG_IFS_TURBO 960
237 #define AR5K_INIT_EIFS 3440
238 #define AR5K_INIT_EIFS_TURBO 6880
239 #define AR5K_INIT_SIFS 560
240 #define AR5K_INIT_SIFS_TURBO 480
241 #define AR5K_INIT_SH_RETRY 10
242 #define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY
243 #define AR5K_INIT_SSH_RETRY 32
244 #define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY
245 #define AR5K_INIT_TX_RETRY 10
247 #define AR5K_INIT_TRANSMIT_LATENCY ( \
248 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
251 #define AR5K_INIT_TRANSMIT_LATENCY_TURBO ( \
252 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
253 (AR5K_INIT_USEC_TURBO) \
255 #define AR5K_INIT_PROTO_TIME_CNTRL ( \
256 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) | \
257 (AR5K_INIT_PROG_IFS) \
259 #define AR5K_INIT_PROTO_TIME_CNTRL_TURBO ( \
260 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) | \
261 (AR5K_INIT_PROG_IFS_TURBO) \
264 /* token to use for aifs, cwmin, cwmax in MadWiFi */
265 #define AR5K_TXQ_USEDEFAULT ((u32) -1)
267 /* GENERIC CHIPSET DEFINITIONS */
289 * Common silicon revision/version values
292 enum ath5k_srev_type
{
297 struct ath5k_srev_name
{
299 enum ath5k_srev_type sr_type
;
303 #define AR5K_SREV_UNKNOWN 0xffff
305 #define AR5K_SREV_AR5210 0x00 /* Crete */
306 #define AR5K_SREV_AR5311 0x10 /* Maui 1 */
307 #define AR5K_SREV_AR5311A 0x20 /* Maui 2 */
308 #define AR5K_SREV_AR5311B 0x30 /* Spirit */
309 #define AR5K_SREV_AR5211 0x40 /* Oahu */
310 #define AR5K_SREV_AR5212 0x50 /* Venice */
311 #define AR5K_SREV_AR5213 0x55 /* ??? */
312 #define AR5K_SREV_AR5213A 0x59 /* Hainan */
313 #define AR5K_SREV_AR2413 0x78 /* Griffin lite */
314 #define AR5K_SREV_AR2414 0x70 /* Griffin */
315 #define AR5K_SREV_AR5424 0x90 /* Condor */
316 #define AR5K_SREV_AR5413 0xa4 /* Eagle lite */
317 #define AR5K_SREV_AR5414 0xa0 /* Eagle */
318 #define AR5K_SREV_AR2415 0xb0 /* Talon */
319 #define AR5K_SREV_AR5416 0xc0 /* PCI-E */
320 #define AR5K_SREV_AR5418 0xca /* PCI-E */
321 #define AR5K_SREV_AR2425 0xe0 /* Swan */
322 #define AR5K_SREV_AR2417 0xf0 /* Nala */
324 #define AR5K_SREV_RAD_5110 0x00
325 #define AR5K_SREV_RAD_5111 0x10
326 #define AR5K_SREV_RAD_5111A 0x15
327 #define AR5K_SREV_RAD_2111 0x20
328 #define AR5K_SREV_RAD_5112 0x30
329 #define AR5K_SREV_RAD_5112A 0x35
330 #define AR5K_SREV_RAD_5112B 0x36
331 #define AR5K_SREV_RAD_2112 0x40
332 #define AR5K_SREV_RAD_2112A 0x45
333 #define AR5K_SREV_RAD_2112B 0x46
334 #define AR5K_SREV_RAD_2413 0x50
335 #define AR5K_SREV_RAD_5413 0x60
336 #define AR5K_SREV_RAD_2316 0x70 /* Cobra SoC */
337 #define AR5K_SREV_RAD_2317 0x80
338 #define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */
339 #define AR5K_SREV_RAD_2425 0xa2
340 #define AR5K_SREV_RAD_5133 0xc0
342 #define AR5K_SREV_PHY_5211 0x30
343 #define AR5K_SREV_PHY_5212 0x41
344 #define AR5K_SREV_PHY_5212A 0x42
345 #define AR5K_SREV_PHY_5212B 0x43
346 #define AR5K_SREV_PHY_2413 0x45
347 #define AR5K_SREV_PHY_5413 0x61
348 #define AR5K_SREV_PHY_2425 0x70
351 #define IEEE80211_MAX_LEN 2500
353 /* TODO add support to mac80211 for vendor-specific rates and modes */
356 * Some of this information is based on Documentation from:
358 * http://madwifi.org/wiki/ChipsetFeatures/SuperAG
360 * Modulation for Atheros' eXtended Range - range enhancing extension that is
361 * supposed to double the distance an Atheros client device can keep a
362 * connection with an Atheros access point. This is achieved by increasing
363 * the receiver sensitivity up to, -105dBm, which is about 20dB above what
364 * the 802.11 specifications demand. In addition, new (proprietary) data rates
365 * are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s.
367 * Please note that can you either use XR or TURBO but you cannot use both,
368 * they are exclusive.
371 #define MODULATION_XR 0x00000200
373 * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a
374 * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s
375 * signaling rate achieved through the bonding of two 54Mbit/s 802.11g
376 * channels. To use this feature your Access Point must also suport it.
377 * There is also a distinction between "static" and "dynamic" turbo modes:
379 * - Static: is the dumb version: devices set to this mode stick to it until
380 * the mode is turned off.
381 * - Dynamic: is the intelligent version, the network decides itself if it
382 * is ok to use turbo. As soon as traffic is detected on adjacent channels
383 * (which would get used in turbo mode), or when a non-turbo station joins
384 * the network, turbo mode won't be used until the situation changes again.
385 * Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which
386 * monitors the used radio band in order to decide whether turbo mode may
389 * This article claims Super G sticks to bonding of channels 5 and 6 for
392 * http://www.pcworld.com/article/id,113428-page,1/article.html
394 * The channel bonding seems to be driver specific though. In addition to
395 * deciding what channels will be used, these "Turbo" modes are accomplished
396 * by also enabling the following features:
398 * - Bursting: allows multiple frames to be sent at once, rather than pausing
399 * after each frame. Bursting is a standards-compliant feature that can be
400 * used with any Access Point.
401 * - Fast frames: increases the amount of information that can be sent per
402 * frame, also resulting in a reduction of transmission overhead. It is a
403 * proprietary feature that needs to be supported by the Access Point.
404 * - Compression: data frames are compressed in real time using a Lempel Ziv
405 * algorithm. This is done transparently. Once this feature is enabled,
406 * compression and decompression takes place inside the chipset, without
407 * putting additional load on the host CPU.
410 #define MODULATION_TURBO 0x00000080
412 enum ath5k_driver_mode
{
414 AR5K_MODE_11A_TURBO
= 1,
417 AR5K_MODE_11G_TURBO
= 4,
422 enum ath5k_ant_mode
{
423 AR5K_ANTMODE_DEFAULT
= 0, /* default antenna setup */
424 AR5K_ANTMODE_FIXED_A
= 1, /* only antenna A is present */
425 AR5K_ANTMODE_FIXED_B
= 2, /* only antenna B is present */
426 AR5K_ANTMODE_SINGLE_AP
= 3, /* sta locked on a single ap */
427 AR5K_ANTMODE_SECTOR_AP
= 4, /* AP with tx antenna set on tx desc */
428 AR5K_ANTMODE_SECTOR_STA
= 5, /* STA with tx antenna set on tx desc */
429 AR5K_ANTMODE_DEBUG
= 6, /* Debug mode -A -> Rx, B-> Tx- */
439 * TX Status descriptor
441 struct ath5k_tx_status
{
455 #define AR5K_TXSTAT_ALTRATE 0x80
456 #define AR5K_TXERR_XRETRY 0x01
457 #define AR5K_TXERR_FILT 0x02
458 #define AR5K_TXERR_FIFO 0x04
461 * enum ath5k_tx_queue - Queue types used to classify tx queues.
462 * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue
463 * @AR5K_TX_QUEUE_DATA: A normal data queue
464 * @AR5K_TX_QUEUE_XR_DATA: An XR-data queue
465 * @AR5K_TX_QUEUE_BEACON: The beacon queue
466 * @AR5K_TX_QUEUE_CAB: The after-beacon queue
467 * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue
469 enum ath5k_tx_queue
{
470 AR5K_TX_QUEUE_INACTIVE
= 0,
472 AR5K_TX_QUEUE_XR_DATA
,
473 AR5K_TX_QUEUE_BEACON
,
478 #define AR5K_NUM_TX_QUEUES 10
479 #define AR5K_NUM_TX_QUEUES_NOQCU 2
482 * Queue syb-types to classify normal data queues.
483 * These are the 4 Access Categories as defined in
484 * WME spec. 0 is the lowest priority and 4 is the
485 * highest. Normal data that hasn't been classified
486 * goes to the Best Effort AC.
488 enum ath5k_tx_queue_subtype
{
489 AR5K_WME_AC_BK
= 0, /*Background traffic*/
490 AR5K_WME_AC_BE
, /*Best-effort (normal) traffic)*/
491 AR5K_WME_AC_VI
, /*Video traffic*/
492 AR5K_WME_AC_VO
, /*Voice traffic*/
496 * Queue ID numbers as returned by the hw functions, each number
497 * represents a hw queue. If hw does not support hw queues
498 * (eg 5210) all data goes in one queue. These match
499 * d80211 definitions (net80211/MadWiFi don't use them).
501 enum ath5k_tx_queue_id
{
502 AR5K_TX_QUEUE_ID_NOQCU_DATA
= 0,
503 AR5K_TX_QUEUE_ID_NOQCU_BEACON
= 1,
504 AR5K_TX_QUEUE_ID_DATA_MIN
= 0, /*IEEE80211_TX_QUEUE_DATA0*/
505 AR5K_TX_QUEUE_ID_DATA_MAX
= 4, /*IEEE80211_TX_QUEUE_DATA4*/
506 AR5K_TX_QUEUE_ID_DATA_SVP
= 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/
507 AR5K_TX_QUEUE_ID_CAB
= 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/
508 AR5K_TX_QUEUE_ID_BEACON
= 7, /*IEEE80211_TX_QUEUE_BEACON*/
509 AR5K_TX_QUEUE_ID_UAPSD
= 8,
510 AR5K_TX_QUEUE_ID_XR_DATA
= 9,
514 * Flags to set hw queue's parameters...
516 #define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */
517 #define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */
518 #define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */
519 #define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 /* Enable TXDESC interrupt -not used- */
520 #define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 /* Enable TXURN interrupt */
521 #define AR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020 /* Enable CBRORN interrupt */
522 #define AR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040 /* Enable CBRURN interrupt */
523 #define AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 /* Enable QTRIG interrupt */
524 #define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 /* Enable TXNOFRM interrupt */
525 #define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 /* Disable random post-backoff */
526 #define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300 /* Enable ready time expiry policy (?)*/
527 #define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800 /* Enable backoff while bursting */
528 #define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 /* Disable backoff while bursting */
529 #define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/
532 * A struct to hold tx queue's parameters
534 struct ath5k_txq_info
{
535 enum ath5k_tx_queue tqi_type
;
536 enum ath5k_tx_queue_subtype tqi_subtype
;
537 u16 tqi_flags
; /* Tx queue flags (see above) */
538 u32 tqi_aifs
; /* Arbitrated Interframe Space */
539 s32 tqi_cw_min
; /* Minimum Contention Window */
540 s32 tqi_cw_max
; /* Maximum Contention Window */
541 u32 tqi_cbr_period
; /* Constant bit rate period */
542 u32 tqi_cbr_overflow_limit
;
544 u32 tqi_ready_time
; /* Not used */
548 * Transmit packet types.
549 * used on tx control descriptor
550 * TODO: Use them inside base.c corectly
552 enum ath5k_pkt_type
{
553 AR5K_PKT_TYPE_NORMAL
= 0,
554 AR5K_PKT_TYPE_ATIM
= 1,
555 AR5K_PKT_TYPE_PSPOLL
= 2,
556 AR5K_PKT_TYPE_BEACON
= 3,
557 AR5K_PKT_TYPE_PROBE_RESP
= 4,
558 AR5K_PKT_TYPE_PIFS
= 5,
562 * TX power and TPC settings
564 #define AR5K_TXPOWER_OFDM(_r, _v) ( \
565 ((0 & 1) << ((_v) + 6)) | \
566 (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \
569 #define AR5K_TXPOWER_CCK(_r, _v) ( \
570 (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \
574 * DMA size definitions (2^n+2)
593 * RX Status descriptor
595 struct ath5k_rx_status
{
607 #define AR5K_RXERR_CRC 0x01
608 #define AR5K_RXERR_PHY 0x02
609 #define AR5K_RXERR_FIFO 0x04
610 #define AR5K_RXERR_DECRYPT 0x08
611 #define AR5K_RXERR_MIC 0x10
612 #define AR5K_RXKEYIX_INVALID ((u8) - 1)
613 #define AR5K_TXKEYIX_INVALID ((u32) - 1)
616 /**************************\
617 BEACON TIMERS DEFINITIONS
618 \**************************/
620 #define AR5K_BEACON_PERIOD 0x0000ffff
621 #define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/
622 #define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/
626 * struct ath5k_beacon_state - Per-station beacon timer state.
627 * @bs_interval: in TU's, can also include the above flags
628 * @bs_cfp_max_duration: if non-zero hw is setup to coexist with a
629 * Point Coordination Function capable AP
631 struct ath5k_beacon_state
{
637 u16 bs_cfp_max_duration
;
638 u16 bs_cfp_du_remain
;
640 u16 bs_sleep_duration
;
641 u16 bs_bmiss_threshold
;
648 * TSF to TU conversion:
650 * TSF is a 64bit value in usec (microseconds).
651 * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of
652 * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024).
654 #define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)
657 /*******************************\
658 GAIN OPTIMIZATION DEFINITIONS
659 \*******************************/
662 AR5K_RFGAIN_INACTIVE
= 0,
664 AR5K_RFGAIN_READ_REQUESTED
,
665 AR5K_RFGAIN_NEED_CHANGE
,
678 /********************\
680 \********************/
682 #define AR5K_SLOT_TIME_9 396
683 #define AR5K_SLOT_TIME_20 880
684 #define AR5K_SLOT_TIME_MAX 0xffff
687 #define CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */
688 #define CHANNEL_TURBO 0x0010 /* Turbo Channel */
689 #define CHANNEL_CCK 0x0020 /* CCK channel */
690 #define CHANNEL_OFDM 0x0040 /* OFDM channel */
691 #define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */
692 #define CHANNEL_5GHZ 0x0100 /* 5GHz channel */
693 #define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */
694 #define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */
695 #define CHANNEL_XR 0x0800 /* XR channel */
697 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
698 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
699 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
700 #define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
701 #define CHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
702 #define CHANNEL_108A CHANNEL_T
703 #define CHANNEL_108G CHANNEL_TG
704 #define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
706 #define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ| \
709 #define CHANNEL_ALL_NOTURBO (CHANNEL_ALL & ~CHANNEL_TURBO)
710 #define CHANNEL_MODES CHANNEL_ALL
713 * Used internaly for reset_tx_queue).
714 * Also see struct struct ieee80211_channel.
716 #define IS_CHAN_XR(_c) ((_c->hw_value & CHANNEL_XR) != 0)
717 #define IS_CHAN_B(_c) ((_c->hw_value & CHANNEL_B) != 0)
720 * The following structure is used to map 2GHz channels to
721 * 5GHz Atheros channels.
724 struct ath5k_athchan_2ghz
{
735 * Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32.
737 * The rate code is used to get the RX rate or set the TX rate on the
738 * hardware descriptors. It is also used for internal modulation control
741 * This is the hardware rate map we are aware of:
743 * rate_code 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08
744 * rate_kbps 3000 1000 ? ? ? 2000 500 48000
746 * rate_code 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10
747 * rate_kbps 24000 12000 6000 54000 36000 18000 9000 ?
749 * rate_code 17 18 19 20 21 22 23 24
750 * rate_kbps ? ? ? ? ? ? ? 11000
752 * rate_code 25 26 27 28 29 30 31 32
753 * rate_kbps 5500 2000 1000 11000S 5500S 2000S ? ?
755 * "S" indicates CCK rates with short preamble.
757 * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the
758 * lowest 4 bits, so they are the same as below with a 0xF mask.
759 * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M).
760 * We handle this in ath5k_setup_bands().
762 #define AR5K_MAX_RATES 32
765 #define ATH5K_RATE_CODE_1M 0x1B
766 #define ATH5K_RATE_CODE_2M 0x1A
767 #define ATH5K_RATE_CODE_5_5M 0x19
768 #define ATH5K_RATE_CODE_11M 0x18
770 #define ATH5K_RATE_CODE_6M 0x0B
771 #define ATH5K_RATE_CODE_9M 0x0F
772 #define ATH5K_RATE_CODE_12M 0x0A
773 #define ATH5K_RATE_CODE_18M 0x0E
774 #define ATH5K_RATE_CODE_24M 0x09
775 #define ATH5K_RATE_CODE_36M 0x0D
776 #define ATH5K_RATE_CODE_48M 0x08
777 #define ATH5K_RATE_CODE_54M 0x0C
779 #define ATH5K_RATE_CODE_XR_500K 0x07
780 #define ATH5K_RATE_CODE_XR_1M 0x02
781 #define ATH5K_RATE_CODE_XR_2M 0x06
782 #define ATH5K_RATE_CODE_XR_3M 0x01
784 /* adding this flag to rate_code enables short preamble */
785 #define AR5K_SET_SHORT_PREAMBLE 0x04
791 #define AR5K_KEYCACHE_SIZE 8
793 /***********************\
794 HW RELATED DEFINITIONS
795 \***********************/
800 #define AR5K_RSSI_EP_MULTIPLIER (1<<7)
802 #define AR5K_ASSERT_ENTRY(_e, _s) do { \
808 * Hardware interrupt abstraction
812 * enum ath5k_int - Hardware interrupt masks helpers
814 * @AR5K_INT_RX: mask to identify received frame interrupts, of type
815 * AR5K_ISR_RXOK or AR5K_ISR_RXERR
816 * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?)
817 * @AR5K_INT_RXNOFRM: No frame received (?)
818 * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The
819 * Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's
820 * LinkPtr is NULL. For more details, refer to:
821 * http://www.freepatentsonline.com/20030225739.html
822 * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors).
823 * Note that Rx overrun is not always fatal, on some chips we can continue
824 * operation without reseting the card, that's why int_fatal is not
825 * common for all chips.
826 * @AR5K_INT_TX: mask to identify received frame interrupts, of type
827 * AR5K_ISR_TXOK or AR5K_ISR_TXERR
828 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?)
829 * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold
830 * We currently do increments on interrupt by
831 * (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2
832 * @AR5K_INT_MIB: Indicates the Management Information Base counters should be
833 * checked. We should do this with ath5k_hw_update_mib_counters() but
834 * it seems we should also then do some noise immunity work.
835 * @AR5K_INT_RXPHY: RX PHY Error
836 * @AR5K_INT_RXKCM: RX Key cache miss
837 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a
838 * beacon that must be handled in software. The alternative is if you
839 * have VEOL support, in that case you let the hardware deal with things.
840 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing
841 * beacons from the AP have associated with, we should probably try to
842 * reassociate. When in IBSS mode this might mean we have not received
843 * any beacons from any local stations. Note that every station in an
844 * IBSS schedules to send beacons at the Target Beacon Transmission Time
845 * (TBTT) with a random backoff.
846 * @AR5K_INT_BNR: Beacon Not Ready interrupt - ??
847 * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now
848 * until properly handled
849 * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA
850 * errors. These types of errors we can enable seem to be of type
851 * AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR.
852 * @AR5K_INT_GLOBAL: Used to clear and set the IER
853 * @AR5K_INT_NOCARD: signals the card has been removed
854 * @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same
857 * These are mapped to take advantage of some common bits
858 * between the MACs, to be able to set intr properties
859 * easier. Some of them are not used yet inside hw.c. Most map
860 * to the respective hw interrupt value as they are common amogst different
864 AR5K_INT_RXOK
= 0x00000001,
865 AR5K_INT_RXDESC
= 0x00000002,
866 AR5K_INT_RXERR
= 0x00000004,
867 AR5K_INT_RXNOFRM
= 0x00000008,
868 AR5K_INT_RXEOL
= 0x00000010,
869 AR5K_INT_RXORN
= 0x00000020,
870 AR5K_INT_TXOK
= 0x00000040,
871 AR5K_INT_TXDESC
= 0x00000080,
872 AR5K_INT_TXERR
= 0x00000100,
873 AR5K_INT_TXNOFRM
= 0x00000200,
874 AR5K_INT_TXEOL
= 0x00000400,
875 AR5K_INT_TXURN
= 0x00000800,
876 AR5K_INT_MIB
= 0x00001000,
877 AR5K_INT_SWI
= 0x00002000,
878 AR5K_INT_RXPHY
= 0x00004000,
879 AR5K_INT_RXKCM
= 0x00008000,
880 AR5K_INT_SWBA
= 0x00010000,
881 AR5K_INT_BRSSI
= 0x00020000,
882 AR5K_INT_BMISS
= 0x00040000,
883 AR5K_INT_FATAL
= 0x00080000, /* Non common */
884 AR5K_INT_BNR
= 0x00100000, /* Non common */
885 AR5K_INT_TIM
= 0x00200000, /* Non common */
886 AR5K_INT_DTIM
= 0x00400000, /* Non common */
887 AR5K_INT_DTIM_SYNC
= 0x00800000, /* Non common */
888 AR5K_INT_GPIO
= 0x01000000,
889 AR5K_INT_BCN_TIMEOUT
= 0x02000000, /* Non common */
890 AR5K_INT_CAB_TIMEOUT
= 0x04000000, /* Non common */
891 AR5K_INT_RX_DOPPLER
= 0x08000000, /* Non common */
892 AR5K_INT_QCBRORN
= 0x10000000, /* Non common */
893 AR5K_INT_QCBRURN
= 0x20000000, /* Non common */
894 AR5K_INT_QTRIG
= 0x40000000, /* Non common */
895 AR5K_INT_GLOBAL
= 0x80000000,
897 AR5K_INT_COMMON
= AR5K_INT_RXOK
919 AR5K_INT_NOCARD
= 0xffffffff
925 enum ath5k_power_mode
{
926 AR5K_PM_UNDEFINED
= 0,
930 AR5K_PM_NETWORK_SLEEP
,
934 * These match net80211 definitions (not used in
936 * TODO: Clean this up
938 #define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/
939 #define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/
940 #define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/
941 #define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/
942 #define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/
944 /* GPIO-controlled software LED */
945 #define AR5K_SOFTLED_PIN 0
946 #define AR5K_SOFTLED_ON 0
947 #define AR5K_SOFTLED_OFF 1
950 * Chipset capabilities -see ath5k_hw_get_capability-
951 * get_capability function is not yet fully implemented
952 * in ath5k so most of these don't work yet...
953 * TODO: Implement these & merge with _TUNE_ stuff above
955 enum ath5k_capability_type
{
956 AR5K_CAP_REG_DMN
= 0, /* Used to get current reg. domain id */
957 AR5K_CAP_TKIP_MIC
= 2, /* Can handle TKIP MIC in hardware */
958 AR5K_CAP_TKIP_SPLIT
= 3, /* TKIP uses split keys */
959 AR5K_CAP_PHYCOUNTERS
= 4, /* PHY error counters */
960 AR5K_CAP_DIVERSITY
= 5, /* Supports fast diversity */
961 AR5K_CAP_NUM_TXQUEUES
= 6, /* Used to get max number of hw txqueues */
962 AR5K_CAP_VEOL
= 7, /* Supports virtual EOL */
963 AR5K_CAP_COMPRESSION
= 8, /* Supports compression */
964 AR5K_CAP_BURST
= 9, /* Supports packet bursting */
965 AR5K_CAP_FASTFRAME
= 10, /* Supports fast frames */
966 AR5K_CAP_TXPOW
= 11, /* Used to get global tx power limit */
967 AR5K_CAP_TPC
= 12, /* Can do per-packet tx power control (needed for 802.11a) */
968 AR5K_CAP_BSSIDMASK
= 13, /* Supports bssid mask */
969 AR5K_CAP_MCAST_KEYSRCH
= 14, /* Supports multicast key search */
970 AR5K_CAP_TSF_ADJUST
= 15, /* Supports beacon tsf adjust */
971 AR5K_CAP_XR
= 16, /* Supports XR mode */
972 AR5K_CAP_WME_TKIPMIC
= 17, /* Supports TKIP MIC when using WMM */
973 AR5K_CAP_CHAN_HALFRATE
= 18, /* Supports half rate channels */
974 AR5K_CAP_CHAN_QUARTERRATE
= 19, /* Supports quarter rate channels */
975 AR5K_CAP_RFSILENT
= 20, /* Supports RFsilent */
979 /* XXX: we *may* move cap_range stuff to struct wiphy */
980 struct ath5k_capabilities
{
982 * Supported PHY modes
983 * (ie. CHANNEL_A, CHANNEL_B, ...)
985 DECLARE_BITMAP(cap_mode
, AR5K_MODE_MAX
);
988 * Frequency range (without regulation restrictions)
998 * Values stored in the EEPROM (some of them...)
1000 struct ath5k_eeprom_info cap_eeprom
;
1011 /***************************************\
1012 HARDWARE ABSTRACTION LAYER STRUCTURE
1013 \***************************************/
1019 #define AR5K_MAX_GPIO 10
1020 #define AR5K_MAX_RF_BANKS 8
1022 /* TODO: Clean up and merge with ath5k_softc */
1026 struct ath5k_softc
*ah_sc
;
1027 void __iomem
*ah_iobase
;
1029 enum ath5k_int ah_imr
;
1031 enum nl80211_iftype ah_op_mode
;
1032 struct ieee80211_channel
*ah_current_channel
;
1034 bool ah_calibration
;
1035 bool ah_single_chip
;
1036 bool ah_combined_mic
;
1038 enum ath5k_version ah_version
;
1039 enum ath5k_radio ah_radio
;
1043 u16 ah_mac_revision
;
1044 u16 ah_phy_revision
;
1045 u16 ah_radio_5ghz_revision
;
1046 u16 ah_radio_2ghz_revision
;
1048 #define ah_modes ah_capabilities.cap_mode
1049 #define ah_ee_version ah_capabilities.cap_eeprom.ee_version
1055 u32 ah_limit_tx_retries
;
1057 /* Antenna Control */
1058 u32 ah_ant_ctl
[AR5K_EEPROM_N_MODES
][AR5K_ANT_MAX
];
1062 bool ah_software_retry
;
1064 u8 ah_sta_id
[ETH_ALEN
];
1066 /* Current BSSID we are trying to assoc to / create.
1067 * This is passed by mac80211 on config_interface() and cached here for
1069 u8 ah_bssid
[ETH_ALEN
];
1070 u8 ah_bssid_mask
[ETH_ALEN
];
1074 struct ath_regulatory ah_regulatory
;
1075 struct ath5k_capabilities ah_capabilities
;
1077 struct ath5k_txq_info ah_txq
[AR5K_NUM_TX_QUEUES
];
1079 u32 ah_txq_imr_txok
;
1080 u32 ah_txq_imr_txerr
;
1081 u32 ah_txq_imr_txurn
;
1082 u32 ah_txq_imr_txdesc
;
1083 u32 ah_txq_imr_txeol
;
1084 u32 ah_txq_imr_cbrorn
;
1085 u32 ah_txq_imr_cbrurn
;
1086 u32 ah_txq_imr_qtrig
;
1087 u32 ah_txq_imr_nofrm
;
1090 size_t ah_rf_banks_size
;
1091 size_t ah_rf_regs_count
;
1092 struct ath5k_gain ah_gain
;
1093 u8 ah_offset
[AR5K_MAX_RF_BANKS
];
1097 /* Temporary tables used for interpolation */
1098 u8 tmpL
[AR5K_EEPROM_N_PD_GAINS
]
1099 [AR5K_EEPROM_POWER_TABLE_SIZE
];
1100 u8 tmpR
[AR5K_EEPROM_N_PD_GAINS
]
1101 [AR5K_EEPROM_POWER_TABLE_SIZE
];
1102 u8 txp_pd_table
[AR5K_EEPROM_POWER_TABLE_SIZE
* 2];
1103 u16 txp_rates_power_table
[AR5K_MAX_RATES
];
1106 /* Values in 0.25dB units */
1109 /* Values in 0.5dB units */
1112 s16 txp_cck_ofdm_gainf_delta
;
1113 /* Value in dB units */
1114 s16 txp_cck_ofdm_pwr_delta
;
1120 struct ieee80211_channel r_last_channel
;
1123 /* noise floor from last periodic calibration */
1129 int (*ah_setup_rx_desc
)(struct ath5k_hw
*ah
, struct ath5k_desc
*desc
,
1130 u32 size
, unsigned int flags
);
1131 int (*ah_setup_tx_desc
)(struct ath5k_hw
*, struct ath5k_desc
*,
1132 unsigned int, unsigned int, enum ath5k_pkt_type
, unsigned int,
1133 unsigned int, unsigned int, unsigned int, unsigned int,
1134 unsigned int, unsigned int, unsigned int);
1135 int (*ah_setup_mrr_tx_desc
)(struct ath5k_hw
*, struct ath5k_desc
*,
1136 unsigned int, unsigned int, unsigned int, unsigned int,
1137 unsigned int, unsigned int);
1138 int (*ah_proc_tx_desc
)(struct ath5k_hw
*, struct ath5k_desc
*,
1139 struct ath5k_tx_status
*);
1140 int (*ah_proc_rx_desc
)(struct ath5k_hw
*, struct ath5k_desc
*,
1141 struct ath5k_rx_status
*);
1148 /* Attach/Detach Functions */
1149 extern struct ath5k_hw
*ath5k_hw_attach(struct ath5k_softc
*sc
, u8 mac_version
);
1150 extern void ath5k_hw_detach(struct ath5k_hw
*ah
);
1153 extern int ath5k_init_leds(struct ath5k_softc
*sc
);
1154 extern void ath5k_led_enable(struct ath5k_softc
*sc
);
1155 extern void ath5k_led_off(struct ath5k_softc
*sc
);
1156 extern void ath5k_unregister_leds(struct ath5k_softc
*sc
);
1158 /* Reset Functions */
1159 extern int ath5k_hw_nic_wakeup(struct ath5k_hw
*ah
, int flags
, bool initial
);
1160 extern int ath5k_hw_on_hold(struct ath5k_hw
*ah
);
1161 extern int ath5k_hw_reset(struct ath5k_hw
*ah
, enum nl80211_iftype op_mode
, struct ieee80211_channel
*channel
, bool change_channel
);
1162 /* Power management functions */
1163 extern int ath5k_hw_set_power(struct ath5k_hw
*ah
, enum ath5k_power_mode mode
, bool set_chip
, u16 sleep_duration
);
1165 /* DMA Related Functions */
1166 extern void ath5k_hw_start_rx_dma(struct ath5k_hw
*ah
);
1167 extern int ath5k_hw_stop_rx_dma(struct ath5k_hw
*ah
);
1168 extern u32
ath5k_hw_get_rxdp(struct ath5k_hw
*ah
);
1169 extern void ath5k_hw_set_rxdp(struct ath5k_hw
*ah
, u32 phys_addr
);
1170 extern int ath5k_hw_start_tx_dma(struct ath5k_hw
*ah
, unsigned int queue
);
1171 extern int ath5k_hw_stop_tx_dma(struct ath5k_hw
*ah
, unsigned int queue
);
1172 extern u32
ath5k_hw_get_txdp(struct ath5k_hw
*ah
, unsigned int queue
);
1173 extern int ath5k_hw_set_txdp(struct ath5k_hw
*ah
, unsigned int queue
,
1175 extern int ath5k_hw_update_tx_triglevel(struct ath5k_hw
*ah
, bool increase
);
1176 /* Interrupt handling */
1177 extern bool ath5k_hw_is_intr_pending(struct ath5k_hw
*ah
);
1178 extern int ath5k_hw_get_isr(struct ath5k_hw
*ah
, enum ath5k_int
*interrupt_mask
);
1179 extern enum ath5k_int
ath5k_hw_set_imr(struct ath5k_hw
*ah
, enum
1180 ath5k_int new_mask
);
1181 extern void ath5k_hw_update_mib_counters(struct ath5k_hw
*ah
, struct ieee80211_low_level_stats
*stats
);
1183 /* EEPROM access functions */
1184 extern int ath5k_eeprom_init(struct ath5k_hw
*ah
);
1185 extern void ath5k_eeprom_detach(struct ath5k_hw
*ah
);
1186 extern int ath5k_eeprom_read_mac(struct ath5k_hw
*ah
, u8
*mac
);
1187 extern bool ath5k_eeprom_is_hb63(struct ath5k_hw
*ah
);
1189 /* Protocol Control Unit Functions */
1190 extern int ath5k_hw_set_opmode(struct ath5k_hw
*ah
);
1191 /* BSSID Functions */
1192 extern void ath5k_hw_get_lladdr(struct ath5k_hw
*ah
, u8
*mac
);
1193 extern int ath5k_hw_set_lladdr(struct ath5k_hw
*ah
, const u8
*mac
);
1194 extern void ath5k_hw_set_associd(struct ath5k_hw
*ah
, const u8
*bssid
, u16 assoc_id
);
1195 extern int ath5k_hw_set_bssid_mask(struct ath5k_hw
*ah
, const u8
*mask
);
1196 /* Receive start/stop functions */
1197 extern void ath5k_hw_start_rx_pcu(struct ath5k_hw
*ah
);
1198 extern void ath5k_hw_stop_rx_pcu(struct ath5k_hw
*ah
);
1199 /* RX Filter functions */
1200 extern void ath5k_hw_set_mcast_filter(struct ath5k_hw
*ah
, u32 filter0
, u32 filter1
);
1201 extern int ath5k_hw_set_mcast_filter_idx(struct ath5k_hw
*ah
, u32 index
);
1202 extern int ath5k_hw_clear_mcast_filter_idx(struct ath5k_hw
*ah
, u32 index
);
1203 extern u32
ath5k_hw_get_rx_filter(struct ath5k_hw
*ah
);
1204 extern void ath5k_hw_set_rx_filter(struct ath5k_hw
*ah
, u32 filter
);
1205 /* Beacon control functions */
1206 extern u32
ath5k_hw_get_tsf32(struct ath5k_hw
*ah
);
1207 extern u64
ath5k_hw_get_tsf64(struct ath5k_hw
*ah
);
1208 extern void ath5k_hw_set_tsf64(struct ath5k_hw
*ah
, u64 tsf64
);
1209 extern void ath5k_hw_reset_tsf(struct ath5k_hw
*ah
);
1210 extern void ath5k_hw_init_beacon(struct ath5k_hw
*ah
, u32 next_beacon
, u32 interval
);
1212 extern int ath5k_hw_set_beacon_timers(struct ath5k_hw
*ah
, const struct ath5k_beacon_state
*state
);
1213 extern void ath5k_hw_reset_beacon(struct ath5k_hw
*ah
);
1214 extern int ath5k_hw_beaconq_finish(struct ath5k_hw
*ah
, unsigned long phys_addr
);
1217 void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw
*ah
, bool high
);
1218 /* ACK/CTS Timeouts */
1219 extern int ath5k_hw_set_ack_timeout(struct ath5k_hw
*ah
, unsigned int timeout
);
1220 extern unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw
*ah
);
1221 extern int ath5k_hw_set_cts_timeout(struct ath5k_hw
*ah
, unsigned int timeout
);
1222 extern unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw
*ah
);
1223 /* Key table (WEP) functions */
1224 extern int ath5k_hw_reset_key(struct ath5k_hw
*ah
, u16 entry
);
1225 extern int ath5k_hw_is_key_valid(struct ath5k_hw
*ah
, u16 entry
);
1226 extern int ath5k_hw_set_key(struct ath5k_hw
*ah
, u16 entry
, const struct ieee80211_key_conf
*key
, const u8
*mac
);
1227 extern int ath5k_hw_set_key_lladdr(struct ath5k_hw
*ah
, u16 entry
, const u8
*mac
);
1229 /* Queue Control Unit, DFS Control Unit Functions */
1230 extern int ath5k_hw_get_tx_queueprops(struct ath5k_hw
*ah
, int queue
, struct ath5k_txq_info
*queue_info
);
1231 extern int ath5k_hw_set_tx_queueprops(struct ath5k_hw
*ah
, int queue
,
1232 const struct ath5k_txq_info
*queue_info
);
1233 extern int ath5k_hw_setup_tx_queue(struct ath5k_hw
*ah
,
1234 enum ath5k_tx_queue queue_type
,
1235 struct ath5k_txq_info
*queue_info
);
1236 extern u32
ath5k_hw_num_tx_pending(struct ath5k_hw
*ah
, unsigned int queue
);
1237 extern void ath5k_hw_release_tx_queue(struct ath5k_hw
*ah
, unsigned int queue
);
1238 extern int ath5k_hw_reset_tx_queue(struct ath5k_hw
*ah
, unsigned int queue
);
1239 extern unsigned int ath5k_hw_get_slot_time(struct ath5k_hw
*ah
);
1240 extern int ath5k_hw_set_slot_time(struct ath5k_hw
*ah
, unsigned int slot_time
);
1242 /* Hardware Descriptor Functions */
1243 extern int ath5k_hw_init_desc_functions(struct ath5k_hw
*ah
);
1245 /* GPIO Functions */
1246 extern void ath5k_hw_set_ledstate(struct ath5k_hw
*ah
, unsigned int state
);
1247 extern int ath5k_hw_set_gpio_input(struct ath5k_hw
*ah
, u32 gpio
);
1248 extern int ath5k_hw_set_gpio_output(struct ath5k_hw
*ah
, u32 gpio
);
1249 extern u32
ath5k_hw_get_gpio(struct ath5k_hw
*ah
, u32 gpio
);
1250 extern int ath5k_hw_set_gpio(struct ath5k_hw
*ah
, u32 gpio
, u32 val
);
1251 extern void ath5k_hw_set_gpio_intr(struct ath5k_hw
*ah
, unsigned int gpio
, u32 interrupt_level
);
1253 /* rfkill Functions */
1254 extern void ath5k_rfkill_hw_start(struct ath5k_hw
*ah
);
1255 extern void ath5k_rfkill_hw_stop(struct ath5k_hw
*ah
);
1257 /* Misc functions */
1258 int ath5k_hw_set_capabilities(struct ath5k_hw
*ah
);
1259 extern int ath5k_hw_get_capability(struct ath5k_hw
*ah
, enum ath5k_capability_type cap_type
, u32 capability
, u32
*result
);
1260 extern int ath5k_hw_enable_pspoll(struct ath5k_hw
*ah
, u8
*bssid
, u16 assoc_id
);
1261 extern int ath5k_hw_disable_pspoll(struct ath5k_hw
*ah
);
1263 /* Initial register settings functions */
1264 extern int ath5k_hw_write_initvals(struct ath5k_hw
*ah
, u8 mode
, bool change_channel
);
1267 extern int ath5k_hw_rfregs_init(struct ath5k_hw
*ah
,
1268 struct ieee80211_channel
*channel
,
1270 extern int ath5k_hw_rfgain_init(struct ath5k_hw
*ah
, unsigned int freq
);
1271 extern enum ath5k_rfgain
ath5k_hw_gainf_calibrate(struct ath5k_hw
*ah
);
1272 extern int ath5k_hw_rfgain_opt_init(struct ath5k_hw
*ah
);
1273 /* PHY/RF channel functions */
1274 extern bool ath5k_channel_ok(struct ath5k_hw
*ah
, u16 freq
, unsigned int flags
);
1275 extern int ath5k_hw_channel(struct ath5k_hw
*ah
, struct ieee80211_channel
*channel
);
1276 /* PHY calibration */
1277 extern int ath5k_hw_phy_calibrate(struct ath5k_hw
*ah
, struct ieee80211_channel
*channel
);
1278 extern int ath5k_hw_noise_floor_calibration(struct ath5k_hw
*ah
, short freq
);
1279 /* Spur mitigation */
1280 bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw
*ah
,
1281 struct ieee80211_channel
*channel
);
1282 void ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw
*ah
,
1283 struct ieee80211_channel
*channel
);
1284 /* Misc PHY functions */
1285 extern u16
ath5k_hw_radio_revision(struct ath5k_hw
*ah
, unsigned int chan
);
1286 extern int ath5k_hw_phy_disable(struct ath5k_hw
*ah
);
1287 /* Antenna control */
1288 extern void ath5k_hw_set_antenna_mode(struct ath5k_hw
*ah
, u8 ant_mode
);
1289 extern void ath5k_hw_set_def_antenna(struct ath5k_hw
*ah
, u8 ant
);
1290 extern unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw
*ah
);
1291 /* TX power setup */
1292 extern int ath5k_hw_txpower(struct ath5k_hw
*ah
, struct ieee80211_channel
*channel
, u8 ee_mode
, u8 txpower
);
1293 extern int ath5k_hw_set_txpower_limit(struct ath5k_hw
*ah
, u8 txpower
);
1296 * Functions used internaly
1300 * Translate usec to hw clock units
1301 * TODO: Half/quarter rate
1303 static inline unsigned int ath5k_hw_htoclock(unsigned int usec
, bool turbo
)
1305 return turbo
? (usec
* 80) : (usec
* 40);
1309 * Translate hw clock units to usec
1310 * TODO: Half/quarter rate
1312 static inline unsigned int ath5k_hw_clocktoh(unsigned int clock
, bool turbo
)
1314 return turbo
? (clock
/ 80) : (clock
/ 40);
1318 * Read from a register
1320 static inline u32
ath5k_hw_reg_read(struct ath5k_hw
*ah
, u16 reg
)
1322 return ioread32(ah
->ah_iobase
+ reg
);
1326 * Write to a register
1328 static inline void ath5k_hw_reg_write(struct ath5k_hw
*ah
, u32 val
, u16 reg
)
1330 iowrite32(val
, ah
->ah_iobase
+ reg
);
1333 #if defined(_ATH5K_RESET) || defined(_ATH5K_PHY)
1335 * Check if a register write has been completed
1337 static int ath5k_hw_register_timeout(struct ath5k_hw
*ah
, u32 reg
, u32 flag
,
1338 u32 val
, bool is_set
)
1343 for (i
= AR5K_TUNE_REGISTER_TIMEOUT
; i
> 0; i
--) {
1344 data
= ath5k_hw_reg_read(ah
, reg
);
1345 if (is_set
&& (data
& flag
))
1347 else if ((data
& flag
) == val
)
1352 return (i
<= 0) ? -EAGAIN
: 0;
1356 static inline u32
ath5k_hw_bitswap(u32 val
, unsigned int bits
)
1358 u32 retval
= 0, bit
, i
;
1360 for (i
= 0; i
< bits
; i
++) {
1361 bit
= (val
>> i
) & 1;
1362 retval
= (retval
<< 1) | bit
;
1368 static inline int ath5k_pad_size(int hdrlen
)
1370 return (hdrlen
< 24) ? 0 : hdrlen
& 3;