drivers/net/wireless/ath/ath5k/dma.c

   1 /*
   2  * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
   3  * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
   4  *
   5  * Permission to use, copy, modify, and distribute this software for any
   6  * purpose with or without fee is hereby granted, provided that the above
   7  * copyright notice and this permission notice appear in all copies.
   8  *
   9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16  *
  17  */
  18
  19 /*************************************\
  20 * DMA and interrupt masking functions *
  21 \*************************************/
  22
  23 /*
  24  * dma.c - DMA and interrupt masking functions
  25  *
  26  * Here we setup descriptor pointers (rxdp/txdp) start/stop dma engine and
  27  * handle queue setup for 5210 chipset (rest are handled on qcu.c).
  28  * Also we setup interrupt mask register (IMR) and read the various iterrupt
  29  * status registers (ISR).
  30  *
  31  * TODO: Handle SISR on 5211+ and introduce a function to return the queue
  32  * number that resulted the interrupt.
  33  */
  34
  35 #include "ath5k.h"
  36 #include "reg.h"
  37 #include "debug.h"
  38 #include "base.h"
  39
  40
  41 /*********\
  42 * Receive *
  43 \*********/
  44
  45 /**
  46  * ath5k_hw_start_rx_dma - Start DMA receive
  47  *
  48  * @ah: The &struct ath5k_hw
  49  */
  50 void ath5k_hw_start_rx_dma(struct ath5k_hw *ah)
  51 {
  52         ath5k_hw_reg_write(ah, AR5K_CR_RXE, AR5K_CR);
  53         ath5k_hw_reg_read(ah, AR5K_CR);
  54 }
  55
  56 /**
  57  * ath5k_hw_stop_rx_dma - Stop DMA receive
  58  *
  59  * @ah: The &struct ath5k_hw
  60  */
  61 int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah)
  62 {
  63         unsigned int i;
  64
  65         ath5k_hw_reg_write(ah, AR5K_CR_RXD, AR5K_CR);
  66
  67         /*
  68          * It may take some time to disable the DMA receive unit
  69          */
  70         for (i = 1000; i > 0 &&
  71                         (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) != 0;
  72                         i--)
  73                 udelay(10);
  74
  75         return i ? 0 : -EBUSY;
  76 }
  77
  78 /**
  79  * ath5k_hw_get_rxdp - Get RX Descriptor's address
  80  *
  81  * @ah: The &struct ath5k_hw
  82  */
  83 u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah)
  84 {
  85         return ath5k_hw_reg_read(ah, AR5K_RXDP);
  86 }
  87
  88 /**
  89  * ath5k_hw_set_rxdp - Set RX Descriptor's address
  90  *
  91  * @ah: The &struct ath5k_hw
  92  * @phys_addr: RX descriptor address
  93  *
  94  * XXX: Should we check if rx is enabled before setting rxdp ?
  95  */
  96 void ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr)
  97 {
  98         ath5k_hw_reg_write(ah, phys_addr, AR5K_RXDP);
  99 }
 100
 101
 102 /**********\
 103 * Transmit *
 104 \**********/
 105
 106 /**
 107  * ath5k_hw_start_tx_dma - Start DMA transmit for a specific queue
 108  *
 109  * @ah: The &struct ath5k_hw
 110  * @queue: The hw queue number
 111  *
 112  * Start DMA transmit for a specific queue and since 5210 doesn't have
 113  * QCU/DCU, set up queue parameters for 5210 here based on queue type (one
 114  * queue for normal data and one queue for beacons). For queue setup
 115  * on newer chips check out qcu.c. Returns -EINVAL if queue number is out
 116  * of range or if queue is already disabled.
 117  *
 118  * NOTE: Must be called after setting up tx control descriptor for that
 119  * queue (see below).
 120  */
 121 int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue)
 122 {
 123         u32 tx_queue;
 124
 125         AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
 126
 127         /* Return if queue is declared inactive */
 128         if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
 129                 return -EINVAL;
 130
 131         if (ah->ah_version == AR5K_AR5210) {
 132                 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);
 133
 134                 /*
 135                  * Set the queue by type on 5210
 136                  */
 137                 switch (ah->ah_txq[queue].tqi_type) {
 138                 case AR5K_TX_QUEUE_DATA:
 139                         tx_queue |= AR5K_CR_TXE0 & ~AR5K_CR_TXD0;
 140                         break;
 141                 case AR5K_TX_QUEUE_BEACON:
 142                         tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1;
 143                         ath5k_hw_reg_write(ah, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE,
 144                                         AR5K_BSR);
 145                         break;
 146                 case AR5K_TX_QUEUE_CAB:
 147                         tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1;
 148                         ath5k_hw_reg_write(ah, AR5K_BCR_TQ1FV | AR5K_BCR_TQ1V |
 149                                 AR5K_BCR_BDMAE, AR5K_BSR);
 150                         break;
 151                 default:
 152                         return -EINVAL;
 153                 }
 154                 /* Start queue */
 155                 ath5k_hw_reg_write(ah, tx_queue, AR5K_CR);
 156                 ath5k_hw_reg_read(ah, AR5K_CR);
 157         } else {
 158                 /* Return if queue is disabled */
 159                 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXD, queue))
 160                         return -EIO;
 161
 162                 /* Start queue */
 163                 AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXE, queue);
 164         }
 165
 166         return 0;
 167 }
 168
 169 /**
 170  * ath5k_hw_stop_tx_dma - Stop DMA transmit on a specific queue
 171  *
 172  * @ah: The &struct ath5k_hw
 173  * @queue: The hw queue number
 174  *
 175  * Stop DMA transmit on a specific hw queue and drain queue so we don't
 176  * have any pending frames. Returns -EBUSY if we still have pending frames,
 177  * -EINVAL if queue number is out of range or inactive.
 178  *
 179  */
 180 int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
 181 {
 182         unsigned int i = 40;
 183         u32 tx_queue, pending;
 184
 185         AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
 186
 187         /* Return if queue is declared inactive */
 188         if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
 189                 return -EINVAL;
 190
 191         if (ah->ah_version == AR5K_AR5210) {
 192                 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);
 193
 194                 /*
 195                  * Set by queue type
 196                  */
 197                 switch (ah->ah_txq[queue].tqi_type) {
 198                 case AR5K_TX_QUEUE_DATA:
 199                         tx_queue |= AR5K_CR_TXD0 & ~AR5K_CR_TXE0;
 200                         break;
 201                 case AR5K_TX_QUEUE_BEACON:
 202                 case AR5K_TX_QUEUE_CAB:
 203                         /* XXX Fix me... */
 204                         tx_queue |= AR5K_CR_TXD1 & ~AR5K_CR_TXD1;
 205                         ath5k_hw_reg_write(ah, 0, AR5K_BSR);
 206                         break;
 207                 default:
 208                         return -EINVAL;
 209                 }
 210
 211                 /* Stop queue */
 212                 ath5k_hw_reg_write(ah, tx_queue, AR5K_CR);
 213                 ath5k_hw_reg_read(ah, AR5K_CR);
 214         } else {
 215                 /*
 216                  * Schedule TX disable and wait until queue is empty
 217                  */
 218                 AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXD, queue);
 219
 220                 /*Check for pending frames*/
 221                 do {
 222                         pending = ath5k_hw_reg_read(ah,
 223                                 AR5K_QUEUE_STATUS(queue)) &
 224                                 AR5K_QCU_STS_FRMPENDCNT;
 225                         udelay(100);
 226                 } while (--i && pending);
 227
 228                 /* For 2413+ order PCU to drop packets using
 229                  * QUIET mechanism */
 230                 if (ah->ah_mac_version >= (AR5K_SREV_AR2414 >> 4) &&
 231                 pending){
 232                         /* Set periodicity and duration */
 233                         ath5k_hw_reg_write(ah,
 234                                 AR5K_REG_SM(100, AR5K_QUIET_CTL2_QT_PER)|
 235                                 AR5K_REG_SM(10, AR5K_QUIET_CTL2_QT_DUR),
 236                                 AR5K_QUIET_CTL2);
 237
 238                         /* Enable quiet period for current TSF */
 239                         ath5k_hw_reg_write(ah,
 240                                 AR5K_QUIET_CTL1_QT_EN |
 241                                 AR5K_REG_SM(ath5k_hw_reg_read(ah,
 242                                                 AR5K_TSF_L32_5211) >> 10,
 243                                                 AR5K_QUIET_CTL1_NEXT_QT_TSF),
 244                                 AR5K_QUIET_CTL1);
 245
 246                         /* Force channel idle high */
 247                         AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211,
 248                                         AR5K_DIAG_SW_CHANNEL_IDLE_HIGH);
 249
 250                         /* Wait a while and disable mechanism */
 251                         udelay(200);
 252                         AR5K_REG_DISABLE_BITS(ah, AR5K_QUIET_CTL1,
 253                                                 AR5K_QUIET_CTL1_QT_EN);
 254
 255                         /* Re-check for pending frames */
 256                         i = 40;
 257                         do {
 258                                 pending = ath5k_hw_reg_read(ah,
 259                                         AR5K_QUEUE_STATUS(queue)) &
 260                                         AR5K_QCU_STS_FRMPENDCNT;
 261                                 udelay(100);
 262                         } while (--i && pending);
 263
 264                         AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5211,
 265                                         AR5K_DIAG_SW_CHANNEL_IDLE_HIGH);
 266                 }
 267
 268                 /* Clear register */
 269                 ath5k_hw_reg_write(ah, 0, AR5K_QCU_TXD);
 270                 if (pending)
 271                         return -EBUSY;
 272         }
 273
 274         /* TODO: Check for success on 5210 else return error */
 275         return 0;
 276 }
 277
 278 /**
 279  * ath5k_hw_get_txdp - Get TX Descriptor's address for a specific queue
 280  *
 281  * @ah: The &struct ath5k_hw
 282  * @queue: The hw queue number
 283  *
 284  * Get TX descriptor's address for a specific queue. For 5210 we ignore
 285  * the queue number and use tx queue type since we only have 2 queues.
 286  * We use TXDP0 for normal data queue and TXDP1 for beacon queue.
 287  * For newer chips with QCU/DCU we just read the corresponding TXDP register.
 288  *
 289  * XXX: Is TXDP read and clear ?
 290  */
 291 u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue)
 292 {
 293         u16 tx_reg;
 294
 295         AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
 296
 297         /*
 298          * Get the transmit queue descriptor pointer from the selected queue
 299          */
 300         /*5210 doesn't have QCU*/
 301         if (ah->ah_version == AR5K_AR5210) {
 302                 switch (ah->ah_txq[queue].tqi_type) {
 303                 case AR5K_TX_QUEUE_DATA:
 304                         tx_reg = AR5K_NOQCU_TXDP0;
 305                         break;
 306                 case AR5K_TX_QUEUE_BEACON:
 307                 case AR5K_TX_QUEUE_CAB:
 308                         tx_reg = AR5K_NOQCU_TXDP1;
 309                         break;
 310                 default:
 311                         return 0xffffffff;
 312                 }
 313         } else {
 314                 tx_reg = AR5K_QUEUE_TXDP(queue);
 315         }
 316
 317         return ath5k_hw_reg_read(ah, tx_reg);
 318 }
 319
 320 /**
 321  * ath5k_hw_set_txdp - Set TX Descriptor's address for a specific queue
 322  *
 323  * @ah: The &struct ath5k_hw
 324  * @queue: The hw queue number
 325  *
 326  * Set TX descriptor's address for a specific queue. For 5210 we ignore
 327  * the queue number and we use tx queue type since we only have 2 queues
 328  * so as above we use TXDP0 for normal data queue and TXDP1 for beacon queue.
 329  * For newer chips with QCU/DCU we just set the corresponding TXDP register.
 330  * Returns -EINVAL if queue type is invalid for 5210 and -EIO if queue is still
 331  * active.
 332  */
 333 int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr)
 334 {
 335         u16 tx_reg;
 336
 337         AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
 338
 339         /*
 340          * Set the transmit queue descriptor pointer register by type
 341          * on 5210
 342          */
 343         if (ah->ah_version == AR5K_AR5210) {
 344                 switch (ah->ah_txq[queue].tqi_type) {
 345                 case AR5K_TX_QUEUE_DATA:
 346                         tx_reg = AR5K_NOQCU_TXDP0;
 347                         break;
 348                 case AR5K_TX_QUEUE_BEACON:
 349                 case AR5K_TX_QUEUE_CAB:
 350                         tx_reg = AR5K_NOQCU_TXDP1;
 351                         break;
 352                 default:
 353                         return -EINVAL;
 354                 }
 355         } else {
 356                 /*
 357                  * Set the transmit queue descriptor pointer for
 358                  * the selected queue on QCU for 5211+
 359                  * (this won't work if the queue is still active)
 360                  */
 361                 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue))
 362                         return -EIO;
 363
 364                 tx_reg = AR5K_QUEUE_TXDP(queue);
 365         }
 366
 367         /* Set descriptor pointer */
 368         ath5k_hw_reg_write(ah, phys_addr, tx_reg);
 369
 370         return 0;
 371 }
 372
 373 /**
 374  * ath5k_hw_update_tx_triglevel - Update tx trigger level
 375  *
 376  * @ah: The &struct ath5k_hw
 377  * @increase: Flag to force increase of trigger level
 378  *
 379  * This function increases/decreases the tx trigger level for the tx fifo
 380  * buffer (aka FIFO threshold) that is used to indicate when PCU flushes
 381  * the buffer and transmits its data. Lowering this results sending small
 382  * frames more quickly but can lead to tx underruns, raising it a lot can
 383  * result other problems (i think bmiss is related). Right now we start with
 384  * the lowest possible (64Bytes) and if we get tx underrun we increase it using
 385  * the increase flag. Returns -EIO if we have reached maximum/minimum.
 386  *
 387  * XXX: Link this with tx DMA size ?
 388  * XXX: Use it to save interrupts ?
 389  * TODO: Needs testing, i think it's related to bmiss...
 390  */
 391 int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase)
 392 {
 393         u32 trigger_level, imr;
 394         int ret = -EIO;
 395
 396         /*
 397          * Disable interrupts by setting the mask
 398          */
 399         imr = ath5k_hw_set_imr(ah, ah->ah_imr & ~AR5K_INT_GLOBAL);
 400
 401         trigger_level = AR5K_REG_MS(ath5k_hw_reg_read(ah, AR5K_TXCFG),
 402                         AR5K_TXCFG_TXFULL);
 403
 404         if (!increase) {
 405                 if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES)
 406                         goto done;
 407         } else
 408                 trigger_level +=
 409                         ((AR5K_TUNE_MAX_TX_FIFO_THRES - trigger_level) / 2);
 410
 411         /*
 412          * Update trigger level on success
 413          */
 414         if (ah->ah_version == AR5K_AR5210)
 415                 ath5k_hw_reg_write(ah, trigger_level, AR5K_TRIG_LVL);
 416         else
 417                 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG,
 418                                 AR5K_TXCFG_TXFULL, trigger_level);
 419
 420         ret = 0;
 421
 422 done:
 423         /*
 424          * Restore interrupt mask
 425          */
 426         ath5k_hw_set_imr(ah, imr);
 427
 428         return ret;
 429 }
 430
 431
 432 /*******************\
 433 * Interrupt masking *
 434 \*******************/
 435
 436 /**
 437  * ath5k_hw_is_intr_pending - Check if we have pending interrupts
 438  *
 439  * @ah: The &struct ath5k_hw
 440  *
 441  * Check if we have pending interrupts to process. Returns 1 if we
 442  * have pending interrupts and 0 if we haven't.
 443  */
 444 bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah)
 445 {
 446         return ath5k_hw_reg_read(ah, AR5K_INTPEND) == 1 ? 1 : 0;
 447 }
 448
 449 /**
 450  * ath5k_hw_get_isr - Get interrupt status
 451  *
 452  * @ah: The @struct ath5k_hw
 453  * @interrupt_mask: Driver's interrupt mask used to filter out
 454  * interrupts in sw.
 455  *
 456  * This function is used inside our interrupt handler to determine the reason
 457  * for the interrupt by reading Primary Interrupt Status Register. Returns an
 458  * abstract interrupt status mask which is mostly ISR with some uncommon bits
 459  * being mapped on some standard non hw-specific positions
 460  * (check out &ath5k_int).
 461  *
 462  * NOTE: We use read-and-clear register, so after this function is called ISR
 463  * is zeroed.
 464  */
 465 int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask)
 466 {
 467         u32 data;
 468
 469         /*
 470          * Read interrupt status from the Interrupt Status register
 471          * on 5210
 472          */
 473         if (ah->ah_version == AR5K_AR5210) {
 474                 data = ath5k_hw_reg_read(ah, AR5K_ISR);
 475                 if (unlikely(data == AR5K_INT_NOCARD)) {
 476                         *interrupt_mask = data;
 477                         return -ENODEV;
 478                 }
 479         } else {
 480                 /*
 481                  * Read interrupt status from Interrupt
 482                  * Status Register shadow copy (Read And Clear)
 483                  *
 484                  * Note: PISR/SISR Not available on 5210
 485                  */
 486                 data = ath5k_hw_reg_read(ah, AR5K_RAC_PISR);
 487                 if (unlikely(data == AR5K_INT_NOCARD)) {
 488                         *interrupt_mask = data;
 489                         return -ENODEV;
 490                 }
 491         }
 492
 493         /*
 494          * Get abstract interrupt mask (driver-compatible)
 495          */
 496         *interrupt_mask = (data & AR5K_INT_COMMON) & ah->ah_imr;
 497
 498         if (ah->ah_version != AR5K_AR5210) {
 499                 u32 sisr2 = ath5k_hw_reg_read(ah, AR5K_RAC_SISR2);
 500
 501                 /*HIU = Host Interface Unit (PCI etc)*/
 502                 if (unlikely(data & (AR5K_ISR_HIUERR)))
 503                         *interrupt_mask |= AR5K_INT_FATAL;
 504
 505                 /*Beacon Not Ready*/
 506                 if (unlikely(data & (AR5K_ISR_BNR)))
 507                         *interrupt_mask |= AR5K_INT_BNR;
 508
 509                 if (unlikely(sisr2 & (AR5K_SISR2_SSERR |
 510                                         AR5K_SISR2_DPERR |
 511                                         AR5K_SISR2_MCABT)))
 512                         *interrupt_mask |= AR5K_INT_FATAL;
 513
 514                 if (data & AR5K_ISR_TIM)
 515                         *interrupt_mask |= AR5K_INT_TIM;
 516
 517                 if (data & AR5K_ISR_BCNMISC) {
 518                         if (sisr2 & AR5K_SISR2_TIM)
 519                                 *interrupt_mask |= AR5K_INT_TIM;
 520                         if (sisr2 & AR5K_SISR2_DTIM)
 521                                 *interrupt_mask |= AR5K_INT_DTIM;
 522                         if (sisr2 & AR5K_SISR2_DTIM_SYNC)
 523                                 *interrupt_mask |= AR5K_INT_DTIM_SYNC;
 524                         if (sisr2 & AR5K_SISR2_BCN_TIMEOUT)
 525                                 *interrupt_mask |= AR5K_INT_BCN_TIMEOUT;
 526                         if (sisr2 & AR5K_SISR2_CAB_TIMEOUT)
 527                                 *interrupt_mask |= AR5K_INT_CAB_TIMEOUT;
 528                 }
 529
 530                 if (data & AR5K_ISR_RXDOPPLER)
 531                         *interrupt_mask |= AR5K_INT_RX_DOPPLER;
 532                 if (data & AR5K_ISR_QCBRORN) {
 533                         *interrupt_mask |= AR5K_INT_QCBRORN;
 534                         ah->ah_txq_isr |= AR5K_REG_MS(
 535                                         ath5k_hw_reg_read(ah, AR5K_RAC_SISR3),
 536                                         AR5K_SISR3_QCBRORN);
 537                 }
 538                 if (data & AR5K_ISR_QCBRURN) {
 539                         *interrupt_mask |= AR5K_INT_QCBRURN;
 540                         ah->ah_txq_isr |= AR5K_REG_MS(
 541                                         ath5k_hw_reg_read(ah, AR5K_RAC_SISR3),
 542                                         AR5K_SISR3_QCBRURN);
 543                 }
 544                 if (data & AR5K_ISR_QTRIG) {
 545                         *interrupt_mask |= AR5K_INT_QTRIG;
 546                         ah->ah_txq_isr |= AR5K_REG_MS(
 547                                         ath5k_hw_reg_read(ah, AR5K_RAC_SISR4),
 548                                         AR5K_SISR4_QTRIG);
 549                 }
 550
 551                 if (data & AR5K_ISR_TXOK)
 552                         ah->ah_txq_isr |= AR5K_REG_MS(
 553                                         ath5k_hw_reg_read(ah, AR5K_RAC_SISR0),
 554                                         AR5K_SISR0_QCU_TXOK);
 555
 556                 if (data & AR5K_ISR_TXDESC)
 557                         ah->ah_txq_isr |= AR5K_REG_MS(
 558                                         ath5k_hw_reg_read(ah, AR5K_RAC_SISR0),
 559                                         AR5K_SISR0_QCU_TXDESC);
 560
 561                 if (data & AR5K_ISR_TXERR)
 562                         ah->ah_txq_isr |= AR5K_REG_MS(
 563                                         ath5k_hw_reg_read(ah, AR5K_RAC_SISR1),
 564                                         AR5K_SISR1_QCU_TXERR);
 565
 566                 if (data & AR5K_ISR_TXEOL)
 567                         ah->ah_txq_isr |= AR5K_REG_MS(
 568                                         ath5k_hw_reg_read(ah, AR5K_RAC_SISR1),
 569                                         AR5K_SISR1_QCU_TXEOL);
 570
 571                 if (data & AR5K_ISR_TXURN)
 572                         ah->ah_txq_isr |= AR5K_REG_MS(
 573                                         ath5k_hw_reg_read(ah, AR5K_RAC_SISR2),
 574                                         AR5K_SISR2_QCU_TXURN);
 575         } else {
 576                 if (unlikely(data & (AR5K_ISR_SSERR | AR5K_ISR_MCABT
 577                                 | AR5K_ISR_HIUERR | AR5K_ISR_DPERR)))
 578                         *interrupt_mask |= AR5K_INT_FATAL;
 579
 580                 /*
 581                  * XXX: BMISS interrupts may occur after association.
 582                  * I found this on 5210 code but it needs testing. If this is
 583                  * true we should disable them before assoc and re-enable them
 584                  * after a successful assoc + some jiffies.
 585                         interrupt_mask &= ~AR5K_INT_BMISS;
 586                  */
 587         }
 588
 589         /*
 590          * In case we didn't handle anything,
 591          * print the register value.
 592          */
 593         if (unlikely(*interrupt_mask == 0 && net_ratelimit()))
 594                 ATH5K_PRINTF("ISR: 0x%08x IMR: 0x%08x\n", data, ah->ah_imr);
 595
 596         return 0;
 597 }
 598
 599 /**
 600  * ath5k_hw_set_imr - Set interrupt mask
 601  *
 602  * @ah: The &struct ath5k_hw
 603  * @new_mask: The new interrupt mask to be set
 604  *
 605  * Set the interrupt mask in hw to save interrupts. We do that by mapping
 606  * ath5k_int bits to hw-specific bits to remove abstraction and writing
 607  * Interrupt Mask Register.
 608  */
 609 enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask)
 610 {
 611         enum ath5k_int old_mask, int_mask;
 612
 613         old_mask = ah->ah_imr;
 614
 615         /*
 616          * Disable card interrupts to prevent any race conditions
 617          * (they will be re-enabled afterwards if AR5K_INT GLOBAL
 618          * is set again on the new mask).
 619          */
 620         if (old_mask & AR5K_INT_GLOBAL) {
 621                 ath5k_hw_reg_write(ah, AR5K_IER_DISABLE, AR5K_IER);
 622                 ath5k_hw_reg_read(ah, AR5K_IER);
 623         }
 624
 625         /*
 626          * Add additional, chipset-dependent interrupt mask flags
 627          * and write them to the IMR (interrupt mask register).
 628          */
 629         int_mask = new_mask & AR5K_INT_COMMON;
 630
 631         if (ah->ah_version != AR5K_AR5210) {
 632                 /* Preserve per queue TXURN interrupt mask */
 633                 u32 simr2 = ath5k_hw_reg_read(ah, AR5K_SIMR2)
 634                                 & AR5K_SIMR2_QCU_TXURN;
 635
 636                 if (new_mask & AR5K_INT_FATAL) {
 637                         int_mask |= AR5K_IMR_HIUERR;
 638                         simr2 |= (AR5K_SIMR2_MCABT | AR5K_SIMR2_SSERR
 639                                 | AR5K_SIMR2_DPERR);
 640                 }
 641
 642                 /*Beacon Not Ready*/
 643                 if (new_mask & AR5K_INT_BNR)
 644                         int_mask |= AR5K_INT_BNR;
 645
 646                 if (new_mask & AR5K_INT_TIM)
 647                         int_mask |= AR5K_IMR_TIM;
 648
 649                 if (new_mask & AR5K_INT_TIM)
 650                         simr2 |= AR5K_SISR2_TIM;
 651                 if (new_mask & AR5K_INT_DTIM)
 652                         simr2 |= AR5K_SISR2_DTIM;
 653                 if (new_mask & AR5K_INT_DTIM_SYNC)
 654                         simr2 |= AR5K_SISR2_DTIM_SYNC;
 655                 if (new_mask & AR5K_INT_BCN_TIMEOUT)
 656                         simr2 |= AR5K_SISR2_BCN_TIMEOUT;
 657                 if (new_mask & AR5K_INT_CAB_TIMEOUT)
 658                         simr2 |= AR5K_SISR2_CAB_TIMEOUT;
 659
 660                 if (new_mask & AR5K_INT_RX_DOPPLER)
 661                         int_mask |= AR5K_IMR_RXDOPPLER;
 662
 663                 /* Note: Per queue interrupt masks
 664                  * are set via reset_tx_queue (qcu.c) */
 665                 ath5k_hw_reg_write(ah, int_mask, AR5K_PIMR);
 666                 ath5k_hw_reg_write(ah, simr2, AR5K_SIMR2);
 667
 668         } else {
 669                 if (new_mask & AR5K_INT_FATAL)
 670                         int_mask |= (AR5K_IMR_SSERR | AR5K_IMR_MCABT
 671                                 | AR5K_IMR_HIUERR | AR5K_IMR_DPERR);
 672
 673                 ath5k_hw_reg_write(ah, int_mask, AR5K_IMR);
 674         }
 675
 676         /* If RXNOFRM interrupt is masked disable it
 677          * by setting AR5K_RXNOFRM to zero */
 678         if (!(new_mask & AR5K_INT_RXNOFRM))
 679                 ath5k_hw_reg_write(ah, 0, AR5K_RXNOFRM);
 680
 681         /* Store new interrupt mask */
 682         ah->ah_imr = new_mask;
 683
 684         /* ..re-enable interrupts if AR5K_INT_GLOBAL is set */
 685         if (new_mask & AR5K_INT_GLOBAL) {
 686                 ath5k_hw_reg_write(ah, AR5K_IER_ENABLE, AR5K_IER);
 687                 ath5k_hw_reg_read(ah, AR5K_IER);
 688         }
 689
 690         return old_mask;
 691 }
 692
 693
 694 /********************\
 695  Init/Stop functions
 696 \********************/
 697
 698 /**
 699  * ath5k_hw_dma_init - Initialize DMA unit
 700  *
 701  * @ah: The &struct ath5k_hw
 702  *
 703  * Set DMA size and pre-enable interrupts
 704  * (driver handles tx/rx buffer setup and
 705  * dma start/stop)
 706  *
 707  * XXX: Save/restore RXDP/TXDP registers ?
 708  */
 709 void ath5k_hw_dma_init(struct ath5k_hw *ah)
 710 {
 711         /*
 712          * Set Rx/Tx DMA Configuration
 713          *
 714          * Set standard DMA size (128). Note that
 715          * a DMA size of 512 causes rx overruns and tx errors
 716          * on pci-e cards (tested on 5424 but since rx overruns
 717          * also occur on 5416/5418 with madwifi we set 128
 718          * for all PCI-E cards to be safe).
 719          *
 720          * XXX: need to check 5210 for this
 721          * TODO: Check out tx triger level, it's always 64 on dumps but I
 722          * guess we can tweak it and see how it goes ;-)
 723          */
 724         if (ah->ah_version != AR5K_AR5210) {
 725                 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG,
 726                         AR5K_TXCFG_SDMAMR, AR5K_DMASIZE_128B);
 727                 AR5K_REG_WRITE_BITS(ah, AR5K_RXCFG,
 728                         AR5K_RXCFG_SDMAMW, AR5K_DMASIZE_128B);
 729         }
 730
 731         /* Pre-enable interrupts on 5211/5212*/
 732         if (ah->ah_version != AR5K_AR5210)
 733                 ath5k_hw_set_imr(ah, ah->ah_imr);
 734
 735 }
 736
 737 /**
 738  * ath5k_hw_dma_stop - stop DMA unit
 739  *
 740  * @ah: The &struct ath5k_hw
 741  *
 742  * Stop tx/rx DMA and interrupts. Returns
 743  * -EBUSY if tx or rx dma failed to stop.
 744  *
 745  * XXX: Sometimes DMA unit hangs and we have
 746  * stuck frames on tx queues, only a reset
 747  * can fix that.
 748  */
 749 int ath5k_hw_dma_stop(struct ath5k_hw *ah)
 750 {
 751         int i, qmax, err;
 752         err = 0;
 753
 754         /* Disable interrupts */
 755         ath5k_hw_set_imr(ah, 0);
 756
 757         /* Stop rx dma */
 758         err = ath5k_hw_stop_rx_dma(ah);
 759         if (err)
 760                 return err;
 761
 762         /* Clear any pending interrupts
 763          * and disable tx dma */
 764         if (ah->ah_version != AR5K_AR5210) {
 765                 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR);
 766                 qmax = AR5K_NUM_TX_QUEUES;
 767         } else {
 768                 /* PISR/SISR Not available on 5210 */
 769                 ath5k_hw_reg_read(ah, AR5K_ISR);
 770                 qmax = AR5K_NUM_TX_QUEUES_NOQCU;
 771         }
 772
 773         for (i = 0; i < qmax; i++) {
 774                 err = ath5k_hw_stop_tx_dma(ah, i);
 775                 /* -EINVAL -> queue inactive */
 776                 if (err != -EINVAL)
 777                         return err;
 778         }
 779
 780         return err;
 781 }