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Merge commit 'v3.1-rc4' into next
[deliverable/linux.git] / drivers / net / wireless / ath / ath5k / phy.c
1 /*
2 * PHY functions
3 *
4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
7 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
8 *
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 *
21 */
22
23 #include <linux/delay.h>
24 #include <linux/slab.h>
25 #include <asm/unaligned.h>
26
27 #include "ath5k.h"
28 #include "reg.h"
29 #include "base.h"
30 #include "rfbuffer.h"
31 #include "rfgain.h"
32
33
34 /******************\
35 * Helper functions *
36 \******************/
37
38 /*
39 * Get the PHY Chip revision
40 */
41 u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
42 {
43 unsigned int i;
44 u32 srev;
45 u16 ret;
46
47 /*
48 * Set the radio chip access register
49 */
50 switch (chan) {
51 case CHANNEL_2GHZ:
52 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
53 break;
54 case CHANNEL_5GHZ:
55 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
56 break;
57 default:
58 return 0;
59 }
60
61 mdelay(2);
62
63 /* ...wait until PHY is ready and read the selected radio revision */
64 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
65
66 for (i = 0; i < 8; i++)
67 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20));
68
69 if (ah->ah_version == AR5K_AR5210) {
70 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf;
71 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
72 } else {
73 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
74 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
75 ((srev & 0x0f) << 4), 8);
76 }
77
78 /* Reset to the 5GHz mode */
79 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
80
81 return ret;
82 }
83
84 /*
85 * Check if a channel is supported
86 */
87 bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
88 {
89 /* Check if the channel is in our supported range */
90 if (flags & CHANNEL_2GHZ) {
91 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
92 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
93 return true;
94 } else if (flags & CHANNEL_5GHZ)
95 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
96 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
97 return true;
98
99 return false;
100 }
101
102 bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
103 struct ieee80211_channel *channel)
104 {
105 u8 refclk_freq;
106
107 if ((ah->ah_radio == AR5K_RF5112) ||
108 (ah->ah_radio == AR5K_RF5413) ||
109 (ah->ah_radio == AR5K_RF2413) ||
110 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
111 refclk_freq = 40;
112 else
113 refclk_freq = 32;
114
115 if ((channel->center_freq % refclk_freq != 0) &&
116 ((channel->center_freq % refclk_freq < 10) ||
117 (channel->center_freq % refclk_freq > 22)))
118 return true;
119 else
120 return false;
121 }
122
123 /*
124 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
125 */
126 static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah,
127 const struct ath5k_rf_reg *rf_regs,
128 u32 val, u8 reg_id, bool set)
129 {
130 const struct ath5k_rf_reg *rfreg = NULL;
131 u8 offset, bank, num_bits, col, position;
132 u16 entry;
133 u32 mask, data, last_bit, bits_shifted, first_bit;
134 u32 *rfb;
135 s32 bits_left;
136 int i;
137
138 data = 0;
139 rfb = ah->ah_rf_banks;
140
141 for (i = 0; i < ah->ah_rf_regs_count; i++) {
142 if (rf_regs[i].index == reg_id) {
143 rfreg = &rf_regs[i];
144 break;
145 }
146 }
147
148 if (rfb == NULL || rfreg == NULL) {
149 ATH5K_PRINTF("Rf register not found!\n");
150 /* should not happen */
151 return 0;
152 }
153
154 bank = rfreg->bank;
155 num_bits = rfreg->field.len;
156 first_bit = rfreg->field.pos;
157 col = rfreg->field.col;
158
159 /* first_bit is an offset from bank's
160 * start. Since we have all banks on
161 * the same array, we use this offset
162 * to mark each bank's start */
163 offset = ah->ah_offset[bank];
164
165 /* Boundary check */
166 if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) {
167 ATH5K_PRINTF("invalid values at offset %u\n", offset);
168 return 0;
169 }
170
171 entry = ((first_bit - 1) / 8) + offset;
172 position = (first_bit - 1) % 8;
173
174 if (set)
175 data = ath5k_hw_bitswap(val, num_bits);
176
177 for (bits_shifted = 0, bits_left = num_bits; bits_left > 0;
178 position = 0, entry++) {
179
180 last_bit = (position + bits_left > 8) ? 8 :
181 position + bits_left;
182
183 mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) <<
184 (col * 8);
185
186 if (set) {
187 rfb[entry] &= ~mask;
188 rfb[entry] |= ((data << position) << (col * 8)) & mask;
189 data >>= (8 - position);
190 } else {
191 data |= (((rfb[entry] & mask) >> (col * 8)) >> position)
192 << bits_shifted;
193 bits_shifted += last_bit - position;
194 }
195
196 bits_left -= 8 - position;
197 }
198
199 data = set ? 1 : ath5k_hw_bitswap(data, num_bits);
200
201 return data;
202 }
203
204 /**
205 * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212
206 *
207 * @ah: the &struct ath5k_hw
208 * @channel: the currently set channel upon reset
209 *
210 * Write the delta slope coefficient (used on pilot tracking ?) for OFDM
211 * operation on the AR5212 upon reset. This is a helper for ath5k_hw_phy_init.
212 *
213 * Since delta slope is floating point we split it on its exponent and
214 * mantissa and provide these values on hw.
215 *
216 * For more infos i think this patent is related
217 * http://www.freepatentsonline.com/7184495.html
218 */
219 static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
220 struct ieee80211_channel *channel)
221 {
222 /* Get exponent and mantissa and set it */
223 u32 coef_scaled, coef_exp, coef_man,
224 ds_coef_exp, ds_coef_man, clock;
225
226 BUG_ON(!(ah->ah_version == AR5K_AR5212) ||
227 !(channel->hw_value & CHANNEL_OFDM));
228
229 /* Get coefficient
230 * ALGO: coef = (5 * clock / carrier_freq) / 2
231 * we scale coef by shifting clock value by 24 for
232 * better precision since we use integers */
233 switch (ah->ah_bwmode) {
234 case AR5K_BWMODE_40MHZ:
235 clock = 40 * 2;
236 break;
237 case AR5K_BWMODE_10MHZ:
238 clock = 40 / 2;
239 break;
240 case AR5K_BWMODE_5MHZ:
241 clock = 40 / 4;
242 break;
243 default:
244 clock = 40;
245 break;
246 }
247 coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq;
248
249 /* Get exponent
250 * ALGO: coef_exp = 14 - highest set bit position */
251 coef_exp = ilog2(coef_scaled);
252
253 /* Doesn't make sense if it's zero*/
254 if (!coef_scaled || !coef_exp)
255 return -EINVAL;
256
257 /* Note: we've shifted coef_scaled by 24 */
258 coef_exp = 14 - (coef_exp - 24);
259
260
261 /* Get mantissa (significant digits)
262 * ALGO: coef_mant = floor(coef_scaled* 2^coef_exp+0.5) */
263 coef_man = coef_scaled +
264 (1 << (24 - coef_exp - 1));
265
266 /* Calculate delta slope coefficient exponent
267 * and mantissa (remove scaling) and set them on hw */
268 ds_coef_man = coef_man >> (24 - coef_exp);
269 ds_coef_exp = coef_exp - 16;
270
271 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
272 AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man);
273 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
274 AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp);
275
276 return 0;
277 }
278
279 int ath5k_hw_phy_disable(struct ath5k_hw *ah)
280 {
281 /*Just a try M.F.*/
282 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
283
284 return 0;
285 }
286
287 /*
288 * Wait for synth to settle
289 */
290 static void ath5k_hw_wait_for_synth(struct ath5k_hw *ah,
291 struct ieee80211_channel *channel)
292 {
293 /*
294 * On 5211+ read activation -> rx delay
295 * and use it (100ns steps).
296 */
297 if (ah->ah_version != AR5K_AR5210) {
298 u32 delay;
299 delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
300 AR5K_PHY_RX_DELAY_M;
301 delay = (channel->hw_value & CHANNEL_CCK) ?
302 ((delay << 2) / 22) : (delay / 10);
303 if (ah->ah_bwmode == AR5K_BWMODE_10MHZ)
304 delay = delay << 1;
305 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ)
306 delay = delay << 2;
307 /* XXX: /2 on turbo ? Let's be safe
308 * for now */
309 udelay(100 + delay);
310 } else {
311 mdelay(1);
312 }
313 }
314
315
316 /**********************\
317 * RF Gain optimization *
318 \**********************/
319
320 /*
321 * This code is used to optimize RF gain on different environments
322 * (temperature mostly) based on feedback from a power detector.
323 *
324 * It's only used on RF5111 and RF5112, later RF chips seem to have
325 * auto adjustment on hw -notice they have a much smaller BANK 7 and
326 * no gain optimization ladder-.
327 *
328 * For more infos check out this patent doc
329 * http://www.freepatentsonline.com/7400691.html
330 *
331 * This paper describes power drops as seen on the receiver due to
332 * probe packets
333 * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues
334 * %20of%20Power%20Control.pdf
335 *
336 * And this is the MadWiFi bug entry related to the above
337 * http://madwifi-project.org/ticket/1659
338 * with various measurements and diagrams
339 *
340 * TODO: Deal with power drops due to probes by setting an appropriate
341 * tx power on the probe packets ! Make this part of the calibration process.
342 */
343
344 /* Initialize ah_gain during attach */
345 int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah)
346 {
347 /* Initialize the gain optimization values */
348 switch (ah->ah_radio) {
349 case AR5K_RF5111:
350 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default;
351 ah->ah_gain.g_low = 20;
352 ah->ah_gain.g_high = 35;
353 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
354 break;
355 case AR5K_RF5112:
356 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default;
357 ah->ah_gain.g_low = 20;
358 ah->ah_gain.g_high = 85;
359 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
360 break;
361 default:
362 return -EINVAL;
363 }
364
365 return 0;
366 }
367
368 /* Schedule a gain probe check on the next transmitted packet.
369 * That means our next packet is going to be sent with lower
370 * tx power and a Peak to Average Power Detector (PAPD) will try
371 * to measure the gain.
372 *
373 * XXX: How about forcing a tx packet (bypassing PCU arbitrator etc)
374 * just after we enable the probe so that we don't mess with
375 * standard traffic ? Maybe it's time to use sw interrupts and
376 * a probe tasklet !!!
377 */
378 static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah)
379 {
380
381 /* Skip if gain calibration is inactive or
382 * we already handle a probe request */
383 if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE)
384 return;
385
386 /* Send the packet with 2dB below max power as
387 * patent doc suggest */
388 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4,
389 AR5K_PHY_PAPD_PROBE_TXPOWER) |
390 AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);
391
392 ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED;
393
394 }
395
396 /* Calculate gain_F measurement correction
397 * based on the current step for RF5112 rev. 2 */
398 static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah)
399 {
400 u32 mix, step;
401 u32 *rf;
402 const struct ath5k_gain_opt *go;
403 const struct ath5k_gain_opt_step *g_step;
404 const struct ath5k_rf_reg *rf_regs;
405
406 /* Only RF5112 Rev. 2 supports it */
407 if ((ah->ah_radio != AR5K_RF5112) ||
408 (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A))
409 return 0;
410
411 go = &rfgain_opt_5112;
412 rf_regs = rf_regs_5112a;
413 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
414
415 g_step = &go->go_step[ah->ah_gain.g_step_idx];
416
417 if (ah->ah_rf_banks == NULL)
418 return 0;
419
420 rf = ah->ah_rf_banks;
421 ah->ah_gain.g_f_corr = 0;
422
423 /* No VGA (Variable Gain Amplifier) override, skip */
424 if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1)
425 return 0;
426
427 /* Mix gain stepping */
428 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false);
429
430 /* Mix gain override */
431 mix = g_step->gos_param[0];
432
433 switch (mix) {
434 case 3:
435 ah->ah_gain.g_f_corr = step * 2;
436 break;
437 case 2:
438 ah->ah_gain.g_f_corr = (step - 5) * 2;
439 break;
440 case 1:
441 ah->ah_gain.g_f_corr = step;
442 break;
443 default:
444 ah->ah_gain.g_f_corr = 0;
445 break;
446 }
447
448 return ah->ah_gain.g_f_corr;
449 }
450
451 /* Check if current gain_F measurement is in the range of our
452 * power detector windows. If we get a measurement outside range
453 * we know it's not accurate (detectors can't measure anything outside
454 * their detection window) so we must ignore it */
455 static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah)
456 {
457 const struct ath5k_rf_reg *rf_regs;
458 u32 step, mix_ovr, level[4];
459 u32 *rf;
460
461 if (ah->ah_rf_banks == NULL)
462 return false;
463
464 rf = ah->ah_rf_banks;
465
466 if (ah->ah_radio == AR5K_RF5111) {
467
468 rf_regs = rf_regs_5111;
469 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
470
471 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP,
472 false);
473
474 level[0] = 0;
475 level[1] = (step == 63) ? 50 : step + 4;
476 level[2] = (step != 63) ? 64 : level[0];
477 level[3] = level[2] + 50;
478
479 ah->ah_gain.g_high = level[3] -
480 (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
481 ah->ah_gain.g_low = level[0] +
482 (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
483 } else {
484
485 rf_regs = rf_regs_5112;
486 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
487
488 mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR,
489 false);
490
491 level[0] = level[2] = 0;
492
493 if (mix_ovr == 1) {
494 level[1] = level[3] = 83;
495 } else {
496 level[1] = level[3] = 107;
497 ah->ah_gain.g_high = 55;
498 }
499 }
500
501 return (ah->ah_gain.g_current >= level[0] &&
502 ah->ah_gain.g_current <= level[1]) ||
503 (ah->ah_gain.g_current >= level[2] &&
504 ah->ah_gain.g_current <= level[3]);
505 }
506
507 /* Perform gain_F adjustment by choosing the right set
508 * of parameters from RF gain optimization ladder */
509 static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah)
510 {
511 const struct ath5k_gain_opt *go;
512 const struct ath5k_gain_opt_step *g_step;
513 int ret = 0;
514
515 switch (ah->ah_radio) {
516 case AR5K_RF5111:
517 go = &rfgain_opt_5111;
518 break;
519 case AR5K_RF5112:
520 go = &rfgain_opt_5112;
521 break;
522 default:
523 return 0;
524 }
525
526 g_step = &go->go_step[ah->ah_gain.g_step_idx];
527
528 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) {
529
530 /* Reached maximum */
531 if (ah->ah_gain.g_step_idx == 0)
532 return -1;
533
534 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
535 ah->ah_gain.g_target >= ah->ah_gain.g_high &&
536 ah->ah_gain.g_step_idx > 0;
537 g_step = &go->go_step[ah->ah_gain.g_step_idx])
538 ah->ah_gain.g_target -= 2 *
539 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain -
540 g_step->gos_gain);
541
542 ret = 1;
543 goto done;
544 }
545
546 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) {
547
548 /* Reached minimum */
549 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1))
550 return -2;
551
552 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
553 ah->ah_gain.g_target <= ah->ah_gain.g_low &&
554 ah->ah_gain.g_step_idx < go->go_steps_count - 1;
555 g_step = &go->go_step[ah->ah_gain.g_step_idx])
556 ah->ah_gain.g_target -= 2 *
557 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain -
558 g_step->gos_gain);
559
560 ret = 2;
561 goto done;
562 }
563
564 done:
565 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE,
566 "ret %d, gain step %u, current gain %u, target gain %u\n",
567 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current,
568 ah->ah_gain.g_target);
569
570 return ret;
571 }
572
573 /* Main callback for thermal RF gain calibration engine
574 * Check for a new gain reading and schedule an adjustment
575 * if needed.
576 *
577 * TODO: Use sw interrupt to schedule reset if gain_F needs
578 * adjustment */
579 enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah)
580 {
581 u32 data, type;
582 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
583
584 if (ah->ah_rf_banks == NULL ||
585 ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE)
586 return AR5K_RFGAIN_INACTIVE;
587
588 /* No check requested, either engine is inactive
589 * or an adjustment is already requested */
590 if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED)
591 goto done;
592
593 /* Read the PAPD (Peak to Average Power Detector)
594 * register */
595 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE);
596
597 /* No probe is scheduled, read gain_F measurement */
598 if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) {
599 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S;
600 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE);
601
602 /* If tx packet is CCK correct the gain_F measurement
603 * by cck ofdm gain delta */
604 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) {
605 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
606 ah->ah_gain.g_current +=
607 ee->ee_cck_ofdm_gain_delta;
608 else
609 ah->ah_gain.g_current +=
610 AR5K_GAIN_CCK_PROBE_CORR;
611 }
612
613 /* Further correct gain_F measurement for
614 * RF5112A radios */
615 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
616 ath5k_hw_rf_gainf_corr(ah);
617 ah->ah_gain.g_current =
618 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ?
619 (ah->ah_gain.g_current - ah->ah_gain.g_f_corr) :
620 0;
621 }
622
623 /* Check if measurement is ok and if we need
624 * to adjust gain, schedule a gain adjustment,
625 * else switch back to the active state */
626 if (ath5k_hw_rf_check_gainf_readback(ah) &&
627 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) &&
628 ath5k_hw_rf_gainf_adjust(ah)) {
629 ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE;
630 } else {
631 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
632 }
633 }
634
635 done:
636 return ah->ah_gain.g_state;
637 }
638
639 /* Write initial RF gain table to set the RF sensitivity
640 * this one works on all RF chips and has nothing to do
641 * with gain_F calibration */
642 static int ath5k_hw_rfgain_init(struct ath5k_hw *ah, enum ieee80211_band band)
643 {
644 const struct ath5k_ini_rfgain *ath5k_rfg;
645 unsigned int i, size, index;
646
647 switch (ah->ah_radio) {
648 case AR5K_RF5111:
649 ath5k_rfg = rfgain_5111;
650 size = ARRAY_SIZE(rfgain_5111);
651 break;
652 case AR5K_RF5112:
653 ath5k_rfg = rfgain_5112;
654 size = ARRAY_SIZE(rfgain_5112);
655 break;
656 case AR5K_RF2413:
657 ath5k_rfg = rfgain_2413;
658 size = ARRAY_SIZE(rfgain_2413);
659 break;
660 case AR5K_RF2316:
661 ath5k_rfg = rfgain_2316;
662 size = ARRAY_SIZE(rfgain_2316);
663 break;
664 case AR5K_RF5413:
665 ath5k_rfg = rfgain_5413;
666 size = ARRAY_SIZE(rfgain_5413);
667 break;
668 case AR5K_RF2317:
669 case AR5K_RF2425:
670 ath5k_rfg = rfgain_2425;
671 size = ARRAY_SIZE(rfgain_2425);
672 break;
673 default:
674 return -EINVAL;
675 }
676
677 index = (band == IEEE80211_BAND_2GHZ) ? 1 : 0;
678
679 for (i = 0; i < size; i++) {
680 AR5K_REG_WAIT(i);
681 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[index],
682 (u32)ath5k_rfg[i].rfg_register);
683 }
684
685 return 0;
686 }
687
688
689
690 /********************\
691 * RF Registers setup *
692 \********************/
693
694 /*
695 * Setup RF registers by writing RF buffer on hw
696 */
697 static int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
698 struct ieee80211_channel *channel, unsigned int mode)
699 {
700 const struct ath5k_rf_reg *rf_regs;
701 const struct ath5k_ini_rfbuffer *ini_rfb;
702 const struct ath5k_gain_opt *go = NULL;
703 const struct ath5k_gain_opt_step *g_step;
704 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
705 u8 ee_mode = 0;
706 u32 *rfb;
707 int i, obdb = -1, bank = -1;
708
709 switch (ah->ah_radio) {
710 case AR5K_RF5111:
711 rf_regs = rf_regs_5111;
712 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
713 ini_rfb = rfb_5111;
714 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111);
715 go = &rfgain_opt_5111;
716 break;
717 case AR5K_RF5112:
718 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
719 rf_regs = rf_regs_5112a;
720 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
721 ini_rfb = rfb_5112a;
722 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a);
723 } else {
724 rf_regs = rf_regs_5112;
725 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
726 ini_rfb = rfb_5112;
727 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112);
728 }
729 go = &rfgain_opt_5112;
730 break;
731 case AR5K_RF2413:
732 rf_regs = rf_regs_2413;
733 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413);
734 ini_rfb = rfb_2413;
735 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413);
736 break;
737 case AR5K_RF2316:
738 rf_regs = rf_regs_2316;
739 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316);
740 ini_rfb = rfb_2316;
741 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316);
742 break;
743 case AR5K_RF5413:
744 rf_regs = rf_regs_5413;
745 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413);
746 ini_rfb = rfb_5413;
747 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413);
748 break;
749 case AR5K_RF2317:
750 rf_regs = rf_regs_2425;
751 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
752 ini_rfb = rfb_2317;
753 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317);
754 break;
755 case AR5K_RF2425:
756 rf_regs = rf_regs_2425;
757 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
758 if (ah->ah_mac_srev < AR5K_SREV_AR2417) {
759 ini_rfb = rfb_2425;
760 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425);
761 } else {
762 ini_rfb = rfb_2417;
763 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417);
764 }
765 break;
766 default:
767 return -EINVAL;
768 }
769
770 /* If it's the first time we set RF buffer, allocate
771 * ah->ah_rf_banks based on ah->ah_rf_banks_size
772 * we set above */
773 if (ah->ah_rf_banks == NULL) {
774 ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size,
775 GFP_KERNEL);
776 if (ah->ah_rf_banks == NULL) {
777 ATH5K_ERR(ah, "out of memory\n");
778 return -ENOMEM;
779 }
780 }
781
782 /* Copy values to modify them */
783 rfb = ah->ah_rf_banks;
784
785 for (i = 0; i < ah->ah_rf_banks_size; i++) {
786 if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) {
787 ATH5K_ERR(ah, "invalid bank\n");
788 return -EINVAL;
789 }
790
791 /* Bank changed, write down the offset */
792 if (bank != ini_rfb[i].rfb_bank) {
793 bank = ini_rfb[i].rfb_bank;
794 ah->ah_offset[bank] = i;
795 }
796
797 rfb[i] = ini_rfb[i].rfb_mode_data[mode];
798 }
799
800 /* Set Output and Driver bias current (OB/DB) */
801 if (channel->hw_value & CHANNEL_2GHZ) {
802
803 if (channel->hw_value & CHANNEL_CCK)
804 ee_mode = AR5K_EEPROM_MODE_11B;
805 else
806 ee_mode = AR5K_EEPROM_MODE_11G;
807
808 /* For RF511X/RF211X combination we
809 * use b_OB and b_DB parameters stored
810 * in eeprom on ee->ee_ob[ee_mode][0]
811 *
812 * For all other chips we use OB/DB for 2GHz
813 * stored in the b/g modal section just like
814 * 802.11a on ee->ee_ob[ee_mode][1] */
815 if ((ah->ah_radio == AR5K_RF5111) ||
816 (ah->ah_radio == AR5K_RF5112))
817 obdb = 0;
818 else
819 obdb = 1;
820
821 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
822 AR5K_RF_OB_2GHZ, true);
823
824 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
825 AR5K_RF_DB_2GHZ, true);
826
827 /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */
828 } else if ((channel->hw_value & CHANNEL_5GHZ) ||
829 (ah->ah_radio == AR5K_RF5111)) {
830
831 /* For 11a, Turbo and XR we need to choose
832 * OB/DB based on frequency range */
833 ee_mode = AR5K_EEPROM_MODE_11A;
834 obdb = channel->center_freq >= 5725 ? 3 :
835 (channel->center_freq >= 5500 ? 2 :
836 (channel->center_freq >= 5260 ? 1 :
837 (channel->center_freq > 4000 ? 0 : -1)));
838
839 if (obdb < 0)
840 return -EINVAL;
841
842 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
843 AR5K_RF_OB_5GHZ, true);
844
845 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
846 AR5K_RF_DB_5GHZ, true);
847 }
848
849 g_step = &go->go_step[ah->ah_gain.g_step_idx];
850
851 /* Set turbo mode (N/A on RF5413) */
852 if ((ah->ah_bwmode == AR5K_BWMODE_40MHZ) &&
853 (ah->ah_radio != AR5K_RF5413))
854 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_TURBO, false);
855
856 /* Bank Modifications (chip-specific) */
857 if (ah->ah_radio == AR5K_RF5111) {
858
859 /* Set gain_F settings according to current step */
860 if (channel->hw_value & CHANNEL_OFDM) {
861
862 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL,
863 AR5K_PHY_FRAME_CTL_TX_CLIP,
864 g_step->gos_param[0]);
865
866 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
867 AR5K_RF_PWD_90, true);
868
869 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
870 AR5K_RF_PWD_84, true);
871
872 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
873 AR5K_RF_RFGAIN_SEL, true);
874
875 /* We programmed gain_F parameters, switch back
876 * to active state */
877 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
878
879 }
880
881 /* Bank 6/7 setup */
882
883 ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode],
884 AR5K_RF_PWD_XPD, true);
885
886 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode],
887 AR5K_RF_XPD_GAIN, true);
888
889 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
890 AR5K_RF_GAIN_I, true);
891
892 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
893 AR5K_RF_PLO_SEL, true);
894
895 /* Tweak power detectors for half/quarter rate support */
896 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ ||
897 ah->ah_bwmode == AR5K_BWMODE_10MHZ) {
898 u8 wait_i;
899
900 ath5k_hw_rfb_op(ah, rf_regs, 0x1f,
901 AR5K_RF_WAIT_S, true);
902
903 wait_i = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ?
904 0x1f : 0x10;
905
906 ath5k_hw_rfb_op(ah, rf_regs, wait_i,
907 AR5K_RF_WAIT_I, true);
908 ath5k_hw_rfb_op(ah, rf_regs, 3,
909 AR5K_RF_MAX_TIME, true);
910
911 }
912 }
913
914 if (ah->ah_radio == AR5K_RF5112) {
915
916 /* Set gain_F settings according to current step */
917 if (channel->hw_value & CHANNEL_OFDM) {
918
919 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0],
920 AR5K_RF_MIXGAIN_OVR, true);
921
922 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
923 AR5K_RF_PWD_138, true);
924
925 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
926 AR5K_RF_PWD_137, true);
927
928 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
929 AR5K_RF_PWD_136, true);
930
931 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4],
932 AR5K_RF_PWD_132, true);
933
934 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5],
935 AR5K_RF_PWD_131, true);
936
937 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6],
938 AR5K_RF_PWD_130, true);
939
940 /* We programmed gain_F parameters, switch back
941 * to active state */
942 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
943 }
944
945 /* Bank 6/7 setup */
946
947 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
948 AR5K_RF_XPD_SEL, true);
949
950 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) {
951 /* Rev. 1 supports only one xpd */
952 ath5k_hw_rfb_op(ah, rf_regs,
953 ee->ee_x_gain[ee_mode],
954 AR5K_RF_XPD_GAIN, true);
955
956 } else {
957 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
958 if (ee->ee_pd_gains[ee_mode] > 1) {
959 ath5k_hw_rfb_op(ah, rf_regs,
960 pdg_curve_to_idx[0],
961 AR5K_RF_PD_GAIN_LO, true);
962 ath5k_hw_rfb_op(ah, rf_regs,
963 pdg_curve_to_idx[1],
964 AR5K_RF_PD_GAIN_HI, true);
965 } else {
966 ath5k_hw_rfb_op(ah, rf_regs,
967 pdg_curve_to_idx[0],
968 AR5K_RF_PD_GAIN_LO, true);
969 ath5k_hw_rfb_op(ah, rf_regs,
970 pdg_curve_to_idx[0],
971 AR5K_RF_PD_GAIN_HI, true);
972 }
973
974 /* Lower synth voltage on Rev 2 */
975 if (ah->ah_radio == AR5K_RF5112 &&
976 (ah->ah_radio_5ghz_revision & AR5K_SREV_REV) > 0) {
977 ath5k_hw_rfb_op(ah, rf_regs, 2,
978 AR5K_RF_HIGH_VC_CP, true);
979
980 ath5k_hw_rfb_op(ah, rf_regs, 2,
981 AR5K_RF_MID_VC_CP, true);
982
983 ath5k_hw_rfb_op(ah, rf_regs, 2,
984 AR5K_RF_LOW_VC_CP, true);
985
986 ath5k_hw_rfb_op(ah, rf_regs, 2,
987 AR5K_RF_PUSH_UP, true);
988 }
989
990 /* Decrease power consumption on 5213+ BaseBand */
991 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
992 ath5k_hw_rfb_op(ah, rf_regs, 1,
993 AR5K_RF_PAD2GND, true);
994
995 ath5k_hw_rfb_op(ah, rf_regs, 1,
996 AR5K_RF_XB2_LVL, true);
997
998 ath5k_hw_rfb_op(ah, rf_regs, 1,
999 AR5K_RF_XB5_LVL, true);
1000
1001 ath5k_hw_rfb_op(ah, rf_regs, 1,
1002 AR5K_RF_PWD_167, true);
1003
1004 ath5k_hw_rfb_op(ah, rf_regs, 1,
1005 AR5K_RF_PWD_166, true);
1006 }
1007 }
1008
1009 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
1010 AR5K_RF_GAIN_I, true);
1011
1012 /* Tweak power detector for half/quarter rates */
1013 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ ||
1014 ah->ah_bwmode == AR5K_BWMODE_10MHZ) {
1015 u8 pd_delay;
1016
1017 pd_delay = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ?
1018 0xf : 0x8;
1019
1020 ath5k_hw_rfb_op(ah, rf_regs, pd_delay,
1021 AR5K_RF_PD_PERIOD_A, true);
1022 ath5k_hw_rfb_op(ah, rf_regs, 0xf,
1023 AR5K_RF_PD_DELAY_A, true);
1024
1025 }
1026 }
1027
1028 if (ah->ah_radio == AR5K_RF5413 &&
1029 channel->hw_value & CHANNEL_2GHZ) {
1030
1031 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE,
1032 true);
1033
1034 /* Set optimum value for early revisions (on pci-e chips) */
1035 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 &&
1036 ah->ah_mac_srev < AR5K_SREV_AR5413)
1037 ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3),
1038 AR5K_RF_PWD_ICLOBUF_2G, true);
1039
1040 }
1041
1042 /* Write RF banks on hw */
1043 for (i = 0; i < ah->ah_rf_banks_size; i++) {
1044 AR5K_REG_WAIT(i);
1045 ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register);
1046 }
1047
1048 return 0;
1049 }
1050
1051
1052 /**************************\
1053 PHY/RF channel functions
1054 \**************************/
1055
1056 /*
1057 * Conversion needed for RF5110
1058 */
1059 static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
1060 {
1061 u32 athchan;
1062
1063 /*
1064 * Convert IEEE channel/MHz to an internal channel value used
1065 * by the AR5210 chipset. This has not been verified with
1066 * newer chipsets like the AR5212A who have a completely
1067 * different RF/PHY part.
1068 */
1069 athchan = (ath5k_hw_bitswap(
1070 (ieee80211_frequency_to_channel(
1071 channel->center_freq) - 24) / 2, 5)
1072 << 1) | (1 << 6) | 0x1;
1073 return athchan;
1074 }
1075
1076 /*
1077 * Set channel on RF5110
1078 */
1079 static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah,
1080 struct ieee80211_channel *channel)
1081 {
1082 u32 data;
1083
1084 /*
1085 * Set the channel and wait
1086 */
1087 data = ath5k_hw_rf5110_chan2athchan(channel);
1088 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER);
1089 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0);
1090 mdelay(1);
1091
1092 return 0;
1093 }
1094
1095 /*
1096 * Conversion needed for 5111
1097 */
1098 static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
1099 struct ath5k_athchan_2ghz *athchan)
1100 {
1101 int channel;
1102
1103 /* Cast this value to catch negative channel numbers (>= -19) */
1104 channel = (int)ieee;
1105
1106 /*
1107 * Map 2GHz IEEE channel to 5GHz Atheros channel
1108 */
1109 if (channel <= 13) {
1110 athchan->a2_athchan = 115 + channel;
1111 athchan->a2_flags = 0x46;
1112 } else if (channel == 14) {
1113 athchan->a2_athchan = 124;
1114 athchan->a2_flags = 0x44;
1115 } else if (channel >= 15 && channel <= 26) {
1116 athchan->a2_athchan = ((channel - 14) * 4) + 132;
1117 athchan->a2_flags = 0x46;
1118 } else
1119 return -EINVAL;
1120
1121 return 0;
1122 }
1123
1124 /*
1125 * Set channel on 5111
1126 */
1127 static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
1128 struct ieee80211_channel *channel)
1129 {
1130 struct ath5k_athchan_2ghz ath5k_channel_2ghz;
1131 unsigned int ath5k_channel =
1132 ieee80211_frequency_to_channel(channel->center_freq);
1133 u32 data0, data1, clock;
1134 int ret;
1135
1136 /*
1137 * Set the channel on the RF5111 radio
1138 */
1139 data0 = data1 = 0;
1140
1141 if (channel->hw_value & CHANNEL_2GHZ) {
1142 /* Map 2GHz channel to 5GHz Atheros channel ID */
1143 ret = ath5k_hw_rf5111_chan2athchan(
1144 ieee80211_frequency_to_channel(channel->center_freq),
1145 &ath5k_channel_2ghz);
1146 if (ret)
1147 return ret;
1148
1149 ath5k_channel = ath5k_channel_2ghz.a2_athchan;
1150 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff)
1151 << 5) | (1 << 4);
1152 }
1153
1154 if (ath5k_channel < 145 || !(ath5k_channel & 1)) {
1155 clock = 1;
1156 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) |
1157 (clock << 1) | (1 << 10) | 1;
1158 } else {
1159 clock = 0;
1160 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff)
1161 << 2) | (clock << 1) | (1 << 10) | 1;
1162 }
1163
1164 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8),
1165 AR5K_RF_BUFFER);
1166 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00),
1167 AR5K_RF_BUFFER_CONTROL_3);
1168
1169 return 0;
1170 }
1171
1172 /*
1173 * Set channel on 5112 and newer
1174 */
1175 static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
1176 struct ieee80211_channel *channel)
1177 {
1178 u32 data, data0, data1, data2;
1179 u16 c;
1180
1181 data = data0 = data1 = data2 = 0;
1182 c = channel->center_freq;
1183
1184 if (c < 4800) {
1185 if (!((c - 2224) % 5)) {
1186 data0 = ((2 * (c - 704)) - 3040) / 10;
1187 data1 = 1;
1188 } else if (!((c - 2192) % 5)) {
1189 data0 = ((2 * (c - 672)) - 3040) / 10;
1190 data1 = 0;
1191 } else
1192 return -EINVAL;
1193
1194 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
1195 } else if ((c % 5) != 2 || c > 5435) {
1196 if (!(c % 20) && c >= 5120) {
1197 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1198 data2 = ath5k_hw_bitswap(3, 2);
1199 } else if (!(c % 10)) {
1200 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1201 data2 = ath5k_hw_bitswap(2, 2);
1202 } else if (!(c % 5)) {
1203 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1204 data2 = ath5k_hw_bitswap(1, 2);
1205 } else
1206 return -EINVAL;
1207 } else {
1208 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8);
1209 data2 = ath5k_hw_bitswap(0, 2);
1210 }
1211
1212 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
1213
1214 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1215 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1216
1217 return 0;
1218 }
1219
1220 /*
1221 * Set the channel on the RF2425
1222 */
1223 static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah,
1224 struct ieee80211_channel *channel)
1225 {
1226 u32 data, data0, data2;
1227 u16 c;
1228
1229 data = data0 = data2 = 0;
1230 c = channel->center_freq;
1231
1232 if (c < 4800) {
1233 data0 = ath5k_hw_bitswap((c - 2272), 8);
1234 data2 = 0;
1235 /* ? 5GHz ? */
1236 } else if ((c % 5) != 2 || c > 5435) {
1237 if (!(c % 20) && c < 5120)
1238 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1239 else if (!(c % 10))
1240 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1241 else if (!(c % 5))
1242 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1243 else
1244 return -EINVAL;
1245 data2 = ath5k_hw_bitswap(1, 2);
1246 } else {
1247 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8);
1248 data2 = ath5k_hw_bitswap(0, 2);
1249 }
1250
1251 data = (data0 << 4) | data2 << 2 | 0x1001;
1252
1253 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1254 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1255
1256 return 0;
1257 }
1258
1259 /*
1260 * Set a channel on the radio chip
1261 */
1262 static int ath5k_hw_channel(struct ath5k_hw *ah,
1263 struct ieee80211_channel *channel)
1264 {
1265 int ret;
1266 /*
1267 * Check bounds supported by the PHY (we don't care about regulatory
1268 * restrictions at this point). Note: hw_value already has the band
1269 * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok()
1270 * of the band by that */
1271 if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) {
1272 ATH5K_ERR(ah,
1273 "channel frequency (%u MHz) out of supported "
1274 "band range\n",
1275 channel->center_freq);
1276 return -EINVAL;
1277 }
1278
1279 /*
1280 * Set the channel and wait
1281 */
1282 switch (ah->ah_radio) {
1283 case AR5K_RF5110:
1284 ret = ath5k_hw_rf5110_channel(ah, channel);
1285 break;
1286 case AR5K_RF5111:
1287 ret = ath5k_hw_rf5111_channel(ah, channel);
1288 break;
1289 case AR5K_RF2317:
1290 case AR5K_RF2425:
1291 ret = ath5k_hw_rf2425_channel(ah, channel);
1292 break;
1293 default:
1294 ret = ath5k_hw_rf5112_channel(ah, channel);
1295 break;
1296 }
1297
1298 if (ret)
1299 return ret;
1300
1301 /* Set JAPAN setting for channel 14 */
1302 if (channel->center_freq == 2484) {
1303 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1304 AR5K_PHY_CCKTXCTL_JAPAN);
1305 } else {
1306 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1307 AR5K_PHY_CCKTXCTL_WORLD);
1308 }
1309
1310 ah->ah_current_channel = channel;
1311
1312 return 0;
1313 }
1314
1315 /*****************\
1316 PHY calibration
1317 \*****************/
1318
1319 static s32 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah)
1320 {
1321 s32 val;
1322
1323 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF);
1324 return sign_extend32(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 8);
1325 }
1326
1327 void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah)
1328 {
1329 int i;
1330
1331 ah->ah_nfcal_hist.index = 0;
1332 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++)
1333 ah->ah_nfcal_hist.nfval[i] = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
1334 }
1335
1336 static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor)
1337 {
1338 struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist;
1339 hist->index = (hist->index + 1) & (ATH5K_NF_CAL_HIST_MAX - 1);
1340 hist->nfval[hist->index] = noise_floor;
1341 }
1342
1343 static s16 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah)
1344 {
1345 s16 sort[ATH5K_NF_CAL_HIST_MAX];
1346 s16 tmp;
1347 int i, j;
1348
1349 memcpy(sort, ah->ah_nfcal_hist.nfval, sizeof(sort));
1350 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX - 1; i++) {
1351 for (j = 1; j < ATH5K_NF_CAL_HIST_MAX - i; j++) {
1352 if (sort[j] > sort[j - 1]) {
1353 tmp = sort[j];
1354 sort[j] = sort[j - 1];
1355 sort[j - 1] = tmp;
1356 }
1357 }
1358 }
1359 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) {
1360 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE,
1361 "cal %d:%d\n", i, sort[i]);
1362 }
1363 return sort[(ATH5K_NF_CAL_HIST_MAX - 1) / 2];
1364 }
1365
1366 /*
1367 * When we tell the hardware to perform a noise floor calibration
1368 * by setting the AR5K_PHY_AGCCTL_NF bit, it will periodically
1369 * sample-and-hold the minimum noise level seen at the antennas.
1370 * This value is then stored in a ring buffer of recently measured
1371 * noise floor values so we have a moving window of the last few
1372 * samples.
1373 *
1374 * The median of the values in the history is then loaded into the
1375 * hardware for its own use for RSSI and CCA measurements.
1376 */
1377 void ath5k_hw_update_noise_floor(struct ath5k_hw *ah)
1378 {
1379 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1380 u32 val;
1381 s16 nf, threshold;
1382 u8 ee_mode;
1383
1384 /* keep last value if calibration hasn't completed */
1385 if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) {
1386 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE,
1387 "NF did not complete in calibration window\n");
1388
1389 return;
1390 }
1391
1392 ee_mode = ath5k_eeprom_mode_from_channel(ah->ah_current_channel);
1393
1394 /* completed NF calibration, test threshold */
1395 nf = ath5k_hw_read_measured_noise_floor(ah);
1396 threshold = ee->ee_noise_floor_thr[ee_mode];
1397
1398 if (nf > threshold) {
1399 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE,
1400 "noise floor failure detected; "
1401 "read %d, threshold %d\n",
1402 nf, threshold);
1403
1404 nf = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
1405 }
1406
1407 ath5k_hw_update_nfcal_hist(ah, nf);
1408 nf = ath5k_hw_get_median_noise_floor(ah);
1409
1410 /* load noise floor (in .5 dBm) so the hardware will use it */
1411 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF) & ~AR5K_PHY_NF_M;
1412 val |= (nf * 2) & AR5K_PHY_NF_M;
1413 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF);
1414
1415 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
1416 ~(AR5K_PHY_AGCCTL_NF_EN | AR5K_PHY_AGCCTL_NF_NOUPDATE));
1417
1418 ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
1419 0, false);
1420
1421 /*
1422 * Load a high max CCA Power value (-50 dBm in .5 dBm units)
1423 * so that we're not capped by the median we just loaded.
1424 * This will be used as the initial value for the next noise
1425 * floor calibration.
1426 */
1427 val = (val & ~AR5K_PHY_NF_M) | ((-50 * 2) & AR5K_PHY_NF_M);
1428 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF);
1429 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1430 AR5K_PHY_AGCCTL_NF_EN |
1431 AR5K_PHY_AGCCTL_NF_NOUPDATE |
1432 AR5K_PHY_AGCCTL_NF);
1433
1434 ah->ah_noise_floor = nf;
1435
1436 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE,
1437 "noise floor calibrated: %d\n", nf);
1438 }
1439
1440 /*
1441 * Perform a PHY calibration on RF5110
1442 * -Fix BPSK/QAM Constellation (I/Q correction)
1443 */
1444 static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
1445 struct ieee80211_channel *channel)
1446 {
1447 u32 phy_sig, phy_agc, phy_sat, beacon;
1448 int ret;
1449
1450 /*
1451 * Disable beacons and RX/TX queues, wait
1452 */
1453 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210,
1454 AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210);
1455 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
1456 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
1457
1458 mdelay(2);
1459
1460 /*
1461 * Set the channel (with AGC turned off)
1462 */
1463 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1464 udelay(10);
1465 ret = ath5k_hw_channel(ah, channel);
1466
1467 /*
1468 * Activate PHY and wait
1469 */
1470 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
1471 mdelay(1);
1472
1473 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1474
1475 if (ret)
1476 return ret;
1477
1478 /*
1479 * Calibrate the radio chip
1480 */
1481
1482 /* Remember normal state */
1483 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG);
1484 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE);
1485 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT);
1486
1487 /* Update radio registers */
1488 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) |
1489 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG);
1490
1491 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI |
1492 AR5K_PHY_AGCCOARSE_LO)) |
1493 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) |
1494 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE);
1495
1496 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT |
1497 AR5K_PHY_ADCSAT_THR)) |
1498 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) |
1499 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT);
1500
1501 udelay(20);
1502
1503 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1504 udelay(10);
1505 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG);
1506 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1507
1508 mdelay(1);
1509
1510 /*
1511 * Enable calibration and wait until completion
1512 */
1513 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL);
1514
1515 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
1516 AR5K_PHY_AGCCTL_CAL, 0, false);
1517
1518 /* Reset to normal state */
1519 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG);
1520 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE);
1521 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT);
1522
1523 if (ret) {
1524 ATH5K_ERR(ah, "calibration timeout (%uMHz)\n",
1525 channel->center_freq);
1526 return ret;
1527 }
1528
1529 /*
1530 * Re-enable RX/TX and beacons
1531 */
1532 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210,
1533 AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210);
1534 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210);
1535
1536 return 0;
1537 }
1538
1539 /*
1540 * Perform I/Q calibration on RF5111/5112 and newer chips
1541 */
1542 static int
1543 ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah)
1544 {
1545 u32 i_pwr, q_pwr;
1546 s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
1547 int i;
1548
1549 if (!ah->ah_calibration ||
1550 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
1551 return 0;
1552
1553 /* Calibration has finished, get the results and re-run */
1554 /* work around empty results which can apparently happen on 5212 */
1555 for (i = 0; i <= 10; i++) {
1556 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR);
1557 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I);
1558 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q);
1559 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE,
1560 "iq_corr:%x i_pwr:%x q_pwr:%x", iq_corr, i_pwr, q_pwr);
1561 if (i_pwr && q_pwr)
1562 break;
1563 }
1564
1565 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
1566
1567 if (ah->ah_version == AR5K_AR5211)
1568 q_coffd = q_pwr >> 6;
1569 else
1570 q_coffd = q_pwr >> 7;
1571
1572 /* protect against divide by 0 and loss of sign bits */
1573 if (i_coffd == 0 || q_coffd < 2)
1574 return 0;
1575
1576 i_coff = (-iq_corr) / i_coffd;
1577 i_coff = clamp(i_coff, -32, 31); /* signed 6 bit */
1578
1579 if (ah->ah_version == AR5K_AR5211)
1580 q_coff = (i_pwr / q_coffd) - 64;
1581 else
1582 q_coff = (i_pwr / q_coffd) - 128;
1583 q_coff = clamp(q_coff, -16, 15); /* signed 5 bit */
1584
1585 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE,
1586 "new I:%d Q:%d (i_coffd:%x q_coffd:%x)",
1587 i_coff, q_coff, i_coffd, q_coffd);
1588
1589 /* Commit new I/Q values (set enable bit last to match HAL sources) */
1590 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, i_coff);
1591 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, q_coff);
1592 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE);
1593
1594 /* Re-enable calibration -if we don't we'll commit
1595 * the same values again and again */
1596 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
1597 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
1598 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN);
1599
1600 return 0;
1601 }
1602
1603 /*
1604 * Perform a PHY calibration
1605 */
1606 int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
1607 struct ieee80211_channel *channel)
1608 {
1609 int ret;
1610
1611 if (ah->ah_radio == AR5K_RF5110)
1612 return ath5k_hw_rf5110_calibrate(ah, channel);
1613
1614 ret = ath5k_hw_rf511x_iq_calibrate(ah);
1615
1616 if ((ah->ah_radio == AR5K_RF5111 || ah->ah_radio == AR5K_RF5112) &&
1617 (channel->hw_value & CHANNEL_OFDM))
1618 ath5k_hw_request_rfgain_probe(ah);
1619
1620 return ret;
1621 }
1622
1623
1624 /***************************\
1625 * Spur mitigation functions *
1626 \***************************/
1627
1628 static void
1629 ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
1630 struct ieee80211_channel *channel)
1631 {
1632 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1633 u32 mag_mask[4] = {0, 0, 0, 0};
1634 u32 pilot_mask[2] = {0, 0};
1635 /* Note: fbin values are scaled up by 2 */
1636 u16 spur_chan_fbin, chan_fbin, symbol_width, spur_detection_window;
1637 s32 spur_delta_phase, spur_freq_sigma_delta;
1638 s32 spur_offset, num_symbols_x16;
1639 u8 num_symbol_offsets, i, freq_band;
1640
1641 /* Convert current frequency to fbin value (the same way channels
1642 * are stored on EEPROM, check out ath5k_eeprom_bin2freq) and scale
1643 * up by 2 so we can compare it later */
1644 if (channel->hw_value & CHANNEL_2GHZ) {
1645 chan_fbin = (channel->center_freq - 2300) * 10;
1646 freq_band = AR5K_EEPROM_BAND_2GHZ;
1647 } else {
1648 chan_fbin = (channel->center_freq - 4900) * 10;
1649 freq_band = AR5K_EEPROM_BAND_5GHZ;
1650 }
1651
1652 /* Check if any spur_chan_fbin from EEPROM is
1653 * within our current channel's spur detection range */
1654 spur_chan_fbin = AR5K_EEPROM_NO_SPUR;
1655 spur_detection_window = AR5K_SPUR_CHAN_WIDTH;
1656 /* XXX: Half/Quarter channels ?*/
1657 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
1658 spur_detection_window *= 2;
1659
1660 for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) {
1661 spur_chan_fbin = ee->ee_spur_chans[i][freq_band];
1662
1663 /* Note: mask cleans AR5K_EEPROM_NO_SPUR flag
1664 * so it's zero if we got nothing from EEPROM */
1665 if (spur_chan_fbin == AR5K_EEPROM_NO_SPUR) {
1666 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
1667 break;
1668 }
1669
1670 if ((chan_fbin - spur_detection_window <=
1671 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK)) &&
1672 (chan_fbin + spur_detection_window >=
1673 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK))) {
1674 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
1675 break;
1676 }
1677 }
1678
1679 /* We need to enable spur filter for this channel */
1680 if (spur_chan_fbin) {
1681 spur_offset = spur_chan_fbin - chan_fbin;
1682 /*
1683 * Calculate deltas:
1684 * spur_freq_sigma_delta -> spur_offset / sample_freq << 21
1685 * spur_delta_phase -> spur_offset / chip_freq << 11
1686 * Note: Both values have 100Hz resolution
1687 */
1688 switch (ah->ah_bwmode) {
1689 case AR5K_BWMODE_40MHZ:
1690 /* Both sample_freq and chip_freq are 80MHz */
1691 spur_delta_phase = (spur_offset << 16) / 25;
1692 spur_freq_sigma_delta = (spur_delta_phase >> 10);
1693 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz * 2;
1694 break;
1695 case AR5K_BWMODE_10MHZ:
1696 /* Both sample_freq and chip_freq are 20MHz (?) */
1697 spur_delta_phase = (spur_offset << 18) / 25;
1698 spur_freq_sigma_delta = (spur_delta_phase >> 10);
1699 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 2;
1700 case AR5K_BWMODE_5MHZ:
1701 /* Both sample_freq and chip_freq are 10MHz (?) */
1702 spur_delta_phase = (spur_offset << 19) / 25;
1703 spur_freq_sigma_delta = (spur_delta_phase >> 10);
1704 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 4;
1705 default:
1706 if (channel->hw_value == CHANNEL_A) {
1707 /* Both sample_freq and chip_freq are 40MHz */
1708 spur_delta_phase = (spur_offset << 17) / 25;
1709 spur_freq_sigma_delta =
1710 (spur_delta_phase >> 10);
1711 symbol_width =
1712 AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
1713 } else {
1714 /* sample_freq -> 40MHz chip_freq -> 44MHz
1715 * (for b compatibility) */
1716 spur_delta_phase = (spur_offset << 17) / 25;
1717 spur_freq_sigma_delta =
1718 (spur_offset << 8) / 55;
1719 symbol_width =
1720 AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
1721 }
1722 break;
1723 }
1724
1725 /* Calculate pilot and magnitude masks */
1726
1727 /* Scale up spur_offset by 1000 to switch to 100HZ resolution
1728 * and divide by symbol_width to find how many symbols we have
1729 * Note: number of symbols is scaled up by 16 */
1730 num_symbols_x16 = ((spur_offset * 1000) << 4) / symbol_width;
1731
1732 /* Spur is on a symbol if num_symbols_x16 % 16 is zero */
1733 if (!(num_symbols_x16 & 0xF))
1734 /* _X_ */
1735 num_symbol_offsets = 3;
1736 else
1737 /* _xx_ */
1738 num_symbol_offsets = 4;
1739
1740 for (i = 0; i < num_symbol_offsets; i++) {
1741
1742 /* Calculate pilot mask */
1743 s32 curr_sym_off =
1744 (num_symbols_x16 / 16) + i + 25;
1745
1746 /* Pilot magnitude mask seems to be a way to
1747 * declare the boundaries for our detection
1748 * window or something, it's 2 for the middle
1749 * value(s) where the symbol is expected to be
1750 * and 1 on the boundary values */
1751 u8 plt_mag_map =
1752 (i == 0 || i == (num_symbol_offsets - 1))
1753 ? 1 : 2;
1754
1755 if (curr_sym_off >= 0 && curr_sym_off <= 32) {
1756 if (curr_sym_off <= 25)
1757 pilot_mask[0] |= 1 << curr_sym_off;
1758 else if (curr_sym_off >= 27)
1759 pilot_mask[0] |= 1 << (curr_sym_off - 1);
1760 } else if (curr_sym_off >= 33 && curr_sym_off <= 52)
1761 pilot_mask[1] |= 1 << (curr_sym_off - 33);
1762
1763 /* Calculate magnitude mask (for viterbi decoder) */
1764 if (curr_sym_off >= -1 && curr_sym_off <= 14)
1765 mag_mask[0] |=
1766 plt_mag_map << (curr_sym_off + 1) * 2;
1767 else if (curr_sym_off >= 15 && curr_sym_off <= 30)
1768 mag_mask[1] |=
1769 plt_mag_map << (curr_sym_off - 15) * 2;
1770 else if (curr_sym_off >= 31 && curr_sym_off <= 46)
1771 mag_mask[2] |=
1772 plt_mag_map << (curr_sym_off - 31) * 2;
1773 else if (curr_sym_off >= 47 && curr_sym_off <= 53)
1774 mag_mask[3] |=
1775 plt_mag_map << (curr_sym_off - 47) * 2;
1776
1777 }
1778
1779 /* Write settings on hw to enable spur filter */
1780 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1781 AR5K_PHY_BIN_MASK_CTL_RATE, 0xff);
1782 /* XXX: Self correlator also ? */
1783 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
1784 AR5K_PHY_IQ_PILOT_MASK_EN |
1785 AR5K_PHY_IQ_CHAN_MASK_EN |
1786 AR5K_PHY_IQ_SPUR_FILT_EN);
1787
1788 /* Set delta phase and freq sigma delta */
1789 ath5k_hw_reg_write(ah,
1790 AR5K_REG_SM(spur_delta_phase,
1791 AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE) |
1792 AR5K_REG_SM(spur_freq_sigma_delta,
1793 AR5K_PHY_TIMING_11_SPUR_FREQ_SD) |
1794 AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC,
1795 AR5K_PHY_TIMING_11);
1796
1797 /* Write pilot masks */
1798 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7);
1799 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
1800 AR5K_PHY_TIMING_8_PILOT_MASK_2,
1801 pilot_mask[1]);
1802
1803 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9);
1804 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
1805 AR5K_PHY_TIMING_10_PILOT_MASK_2,
1806 pilot_mask[1]);
1807
1808 /* Write magnitude masks */
1809 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1);
1810 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2);
1811 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3);
1812 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1813 AR5K_PHY_BIN_MASK_CTL_MASK_4,
1814 mag_mask[3]);
1815
1816 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1);
1817 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2);
1818 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3);
1819 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
1820 AR5K_PHY_BIN_MASK2_4_MASK_4,
1821 mag_mask[3]);
1822
1823 } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) &
1824 AR5K_PHY_IQ_SPUR_FILT_EN) {
1825 /* Clean up spur mitigation settings and disable filter */
1826 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1827 AR5K_PHY_BIN_MASK_CTL_RATE, 0);
1828 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ,
1829 AR5K_PHY_IQ_PILOT_MASK_EN |
1830 AR5K_PHY_IQ_CHAN_MASK_EN |
1831 AR5K_PHY_IQ_SPUR_FILT_EN);
1832 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11);
1833
1834 /* Clear pilot masks */
1835 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7);
1836 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
1837 AR5K_PHY_TIMING_8_PILOT_MASK_2,
1838 0);
1839
1840 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9);
1841 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
1842 AR5K_PHY_TIMING_10_PILOT_MASK_2,
1843 0);
1844
1845 /* Clear magnitude masks */
1846 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1);
1847 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2);
1848 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3);
1849 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1850 AR5K_PHY_BIN_MASK_CTL_MASK_4,
1851 0);
1852
1853 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1);
1854 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2);
1855 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3);
1856 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
1857 AR5K_PHY_BIN_MASK2_4_MASK_4,
1858 0);
1859 }
1860 }
1861
1862
1863 /*****************\
1864 * Antenna control *
1865 \*****************/
1866
1867 static void /*TODO:Boundary check*/
1868 ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant)
1869 {
1870 if (ah->ah_version != AR5K_AR5210)
1871 ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA);
1872 }
1873
1874 /*
1875 * Enable/disable fast rx antenna diversity
1876 */
1877 static void
1878 ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable)
1879 {
1880 switch (ee_mode) {
1881 case AR5K_EEPROM_MODE_11G:
1882 /* XXX: This is set to
1883 * disabled on initvals !!! */
1884 case AR5K_EEPROM_MODE_11A:
1885 if (enable)
1886 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL,
1887 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1888 else
1889 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1890 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1891 break;
1892 case AR5K_EEPROM_MODE_11B:
1893 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1894 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1895 break;
1896 default:
1897 return;
1898 }
1899
1900 if (enable) {
1901 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
1902 AR5K_PHY_RESTART_DIV_GC, 4);
1903
1904 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
1905 AR5K_PHY_FAST_ANT_DIV_EN);
1906 } else {
1907 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
1908 AR5K_PHY_RESTART_DIV_GC, 0);
1909
1910 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
1911 AR5K_PHY_FAST_ANT_DIV_EN);
1912 }
1913 }
1914
1915 void
1916 ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode)
1917 {
1918 u8 ant0, ant1;
1919
1920 /*
1921 * In case a fixed antenna was set as default
1922 * use the same switch table twice.
1923 */
1924 if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_A)
1925 ant0 = ant1 = AR5K_ANT_SWTABLE_A;
1926 else if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_B)
1927 ant0 = ant1 = AR5K_ANT_SWTABLE_B;
1928 else {
1929 ant0 = AR5K_ANT_SWTABLE_A;
1930 ant1 = AR5K_ANT_SWTABLE_B;
1931 }
1932
1933 /* Set antenna idle switch table */
1934 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_ANT_CTL,
1935 AR5K_PHY_ANT_CTL_SWTABLE_IDLE,
1936 (ah->ah_ant_ctl[ee_mode][AR5K_ANT_CTL] |
1937 AR5K_PHY_ANT_CTL_TXRX_EN));
1938
1939 /* Set antenna switch tables */
1940 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant0],
1941 AR5K_PHY_ANT_SWITCH_TABLE_0);
1942 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant1],
1943 AR5K_PHY_ANT_SWITCH_TABLE_1);
1944 }
1945
1946 /*
1947 * Set antenna operating mode
1948 */
1949 void
1950 ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode)
1951 {
1952 struct ieee80211_channel *channel = ah->ah_current_channel;
1953 bool use_def_for_tx, update_def_on_tx, use_def_for_rts, fast_div;
1954 bool use_def_for_sg;
1955 int ee_mode;
1956 u8 def_ant, tx_ant;
1957 u32 sta_id1 = 0;
1958
1959 /* if channel is not initialized yet we can't set the antennas
1960 * so just store the mode. it will be set on the next reset */
1961 if (channel == NULL) {
1962 ah->ah_ant_mode = ant_mode;
1963 return;
1964 }
1965
1966 def_ant = ah->ah_def_ant;
1967
1968 ee_mode = ath5k_eeprom_mode_from_channel(channel);
1969 if (ee_mode < 0) {
1970 ATH5K_ERR(ah,
1971 "invalid channel: %d\n", channel->center_freq);
1972 return;
1973 }
1974
1975 switch (ant_mode) {
1976 case AR5K_ANTMODE_DEFAULT:
1977 tx_ant = 0;
1978 use_def_for_tx = false;
1979 update_def_on_tx = false;
1980 use_def_for_rts = false;
1981 use_def_for_sg = false;
1982 fast_div = true;
1983 break;
1984 case AR5K_ANTMODE_FIXED_A:
1985 def_ant = 1;
1986 tx_ant = 1;
1987 use_def_for_tx = true;
1988 update_def_on_tx = false;
1989 use_def_for_rts = true;
1990 use_def_for_sg = true;
1991 fast_div = false;
1992 break;
1993 case AR5K_ANTMODE_FIXED_B:
1994 def_ant = 2;
1995 tx_ant = 2;
1996 use_def_for_tx = true;
1997 update_def_on_tx = false;
1998 use_def_for_rts = true;
1999 use_def_for_sg = true;
2000 fast_div = false;
2001 break;
2002 case AR5K_ANTMODE_SINGLE_AP:
2003 def_ant = 1; /* updated on tx */
2004 tx_ant = 0;
2005 use_def_for_tx = true;
2006 update_def_on_tx = true;
2007 use_def_for_rts = true;
2008 use_def_for_sg = true;
2009 fast_div = true;
2010 break;
2011 case AR5K_ANTMODE_SECTOR_AP:
2012 tx_ant = 1; /* variable */
2013 use_def_for_tx = false;
2014 update_def_on_tx = false;
2015 use_def_for_rts = true;
2016 use_def_for_sg = false;
2017 fast_div = false;
2018 break;
2019 case AR5K_ANTMODE_SECTOR_STA:
2020 tx_ant = 1; /* variable */
2021 use_def_for_tx = true;
2022 update_def_on_tx = false;
2023 use_def_for_rts = true;
2024 use_def_for_sg = false;
2025 fast_div = true;
2026 break;
2027 case AR5K_ANTMODE_DEBUG:
2028 def_ant = 1;
2029 tx_ant = 2;
2030 use_def_for_tx = false;
2031 update_def_on_tx = false;
2032 use_def_for_rts = false;
2033 use_def_for_sg = false;
2034 fast_div = false;
2035 break;
2036 default:
2037 return;
2038 }
2039
2040 ah->ah_tx_ant = tx_ant;
2041 ah->ah_ant_mode = ant_mode;
2042 ah->ah_def_ant = def_ant;
2043
2044 sta_id1 |= use_def_for_tx ? AR5K_STA_ID1_DEFAULT_ANTENNA : 0;
2045 sta_id1 |= update_def_on_tx ? AR5K_STA_ID1_DESC_ANTENNA : 0;
2046 sta_id1 |= use_def_for_rts ? AR5K_STA_ID1_RTS_DEF_ANTENNA : 0;
2047 sta_id1 |= use_def_for_sg ? AR5K_STA_ID1_SELFGEN_DEF_ANT : 0;
2048
2049 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS);
2050
2051 if (sta_id1)
2052 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1);
2053
2054 ath5k_hw_set_antenna_switch(ah, ee_mode);
2055 /* Note: set diversity before default antenna
2056 * because it won't work correctly */
2057 ath5k_hw_set_fast_div(ah, ee_mode, fast_div);
2058 ath5k_hw_set_def_antenna(ah, def_ant);
2059 }
2060
2061
2062 /****************\
2063 * TX power setup *
2064 \****************/
2065
2066 /*
2067 * Helper functions
2068 */
2069
2070 /*
2071 * Do linear interpolation between two given (x, y) points
2072 */
2073 static s16
2074 ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right,
2075 s16 y_left, s16 y_right)
2076 {
2077 s16 ratio, result;
2078
2079 /* Avoid divide by zero and skip interpolation
2080 * if we have the same point */
2081 if ((x_left == x_right) || (y_left == y_right))
2082 return y_left;
2083
2084 /*
2085 * Since we use ints and not fps, we need to scale up in
2086 * order to get a sane ratio value (or else we 'll eg. get
2087 * always 1 instead of 1.25, 1.75 etc). We scale up by 100
2088 * to have some accuracy both for 0.5 and 0.25 steps.
2089 */
2090 ratio = ((100 * y_right - 100 * y_left) / (x_right - x_left));
2091
2092 /* Now scale down to be in range */
2093 result = y_left + (ratio * (target - x_left) / 100);
2094
2095 return result;
2096 }
2097
2098 /*
2099 * Find vertical boundary (min pwr) for the linear PCDAC curve.
2100 *
2101 * Since we have the top of the curve and we draw the line below
2102 * until we reach 1 (1 pcdac step) we need to know which point
2103 * (x value) that is so that we don't go below y axis and have negative
2104 * pcdac values when creating the curve, or fill the table with zeroes.
2105 */
2106 static s16
2107 ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR,
2108 const s16 *pwrL, const s16 *pwrR)
2109 {
2110 s8 tmp;
2111 s16 min_pwrL, min_pwrR;
2112 s16 pwr_i;
2113
2114 /* Some vendors write the same pcdac value twice !!! */
2115 if (stepL[0] == stepL[1] || stepR[0] == stepR[1])
2116 return max(pwrL[0], pwrR[0]);
2117
2118 if (pwrL[0] == pwrL[1])
2119 min_pwrL = pwrL[0];
2120 else {
2121 pwr_i = pwrL[0];
2122 do {
2123 pwr_i--;
2124 tmp = (s8) ath5k_get_interpolated_value(pwr_i,
2125 pwrL[0], pwrL[1],
2126 stepL[0], stepL[1]);
2127 } while (tmp > 1);
2128
2129 min_pwrL = pwr_i;
2130 }
2131
2132 if (pwrR[0] == pwrR[1])
2133 min_pwrR = pwrR[0];
2134 else {
2135 pwr_i = pwrR[0];
2136 do {
2137 pwr_i--;
2138 tmp = (s8) ath5k_get_interpolated_value(pwr_i,
2139 pwrR[0], pwrR[1],
2140 stepR[0], stepR[1]);
2141 } while (tmp > 1);
2142
2143 min_pwrR = pwr_i;
2144 }
2145
2146 /* Keep the right boundary so that it works for both curves */
2147 return max(min_pwrL, min_pwrR);
2148 }
2149
2150 /*
2151 * Interpolate (pwr,vpd) points to create a Power to PDADC or a
2152 * Power to PCDAC curve.
2153 *
2154 * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC
2155 * steps (offsets) on y axis. Power can go up to 31.5dB and max
2156 * PCDAC/PDADC step for each curve is 64 but we can write more than
2157 * one curves on hw so we can go up to 128 (which is the max step we
2158 * can write on the final table).
2159 *
2160 * We write y values (PCDAC/PDADC steps) on hw.
2161 */
2162 static void
2163 ath5k_create_power_curve(s16 pmin, s16 pmax,
2164 const s16 *pwr, const u8 *vpd,
2165 u8 num_points,
2166 u8 *vpd_table, u8 type)
2167 {
2168 u8 idx[2] = { 0, 1 };
2169 s16 pwr_i = 2 * pmin;
2170 int i;
2171
2172 if (num_points < 2)
2173 return;
2174
2175 /* We want the whole line, so adjust boundaries
2176 * to cover the entire power range. Note that
2177 * power values are already 0.25dB so no need
2178 * to multiply pwr_i by 2 */
2179 if (type == AR5K_PWRTABLE_LINEAR_PCDAC) {
2180 pwr_i = pmin;
2181 pmin = 0;
2182 pmax = 63;
2183 }
2184
2185 /* Find surrounding turning points (TPs)
2186 * and interpolate between them */
2187 for (i = 0; (i <= (u16) (pmax - pmin)) &&
2188 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
2189
2190 /* We passed the right TP, move to the next set of TPs
2191 * if we pass the last TP, extrapolate above using the last
2192 * two TPs for ratio */
2193 if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) {
2194 idx[0]++;
2195 idx[1]++;
2196 }
2197
2198 vpd_table[i] = (u8) ath5k_get_interpolated_value(pwr_i,
2199 pwr[idx[0]], pwr[idx[1]],
2200 vpd[idx[0]], vpd[idx[1]]);
2201
2202 /* Increase by 0.5dB
2203 * (0.25 dB units) */
2204 pwr_i += 2;
2205 }
2206 }
2207
2208 /*
2209 * Get the surrounding per-channel power calibration piers
2210 * for a given frequency so that we can interpolate between
2211 * them and come up with an appropriate dataset for our current
2212 * channel.
2213 */
2214 static void
2215 ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah,
2216 struct ieee80211_channel *channel,
2217 struct ath5k_chan_pcal_info **pcinfo_l,
2218 struct ath5k_chan_pcal_info **pcinfo_r)
2219 {
2220 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2221 struct ath5k_chan_pcal_info *pcinfo;
2222 u8 idx_l, idx_r;
2223 u8 mode, max, i;
2224 u32 target = channel->center_freq;
2225
2226 idx_l = 0;
2227 idx_r = 0;
2228
2229 if (!(channel->hw_value & CHANNEL_OFDM)) {
2230 pcinfo = ee->ee_pwr_cal_b;
2231 mode = AR5K_EEPROM_MODE_11B;
2232 } else if (channel->hw_value & CHANNEL_2GHZ) {
2233 pcinfo = ee->ee_pwr_cal_g;
2234 mode = AR5K_EEPROM_MODE_11G;
2235 } else {
2236 pcinfo = ee->ee_pwr_cal_a;
2237 mode = AR5K_EEPROM_MODE_11A;
2238 }
2239 max = ee->ee_n_piers[mode] - 1;
2240
2241 /* Frequency is below our calibrated
2242 * range. Use the lowest power curve
2243 * we have */
2244 if (target < pcinfo[0].freq) {
2245 idx_l = idx_r = 0;
2246 goto done;
2247 }
2248
2249 /* Frequency is above our calibrated
2250 * range. Use the highest power curve
2251 * we have */
2252 if (target > pcinfo[max].freq) {
2253 idx_l = idx_r = max;
2254 goto done;
2255 }
2256
2257 /* Frequency is inside our calibrated
2258 * channel range. Pick the surrounding
2259 * calibration piers so that we can
2260 * interpolate */
2261 for (i = 0; i <= max; i++) {
2262
2263 /* Frequency matches one of our calibration
2264 * piers, no need to interpolate, just use
2265 * that calibration pier */
2266 if (pcinfo[i].freq == target) {
2267 idx_l = idx_r = i;
2268 goto done;
2269 }
2270
2271 /* We found a calibration pier that's above
2272 * frequency, use this pier and the previous
2273 * one to interpolate */
2274 if (target < pcinfo[i].freq) {
2275 idx_r = i;
2276 idx_l = idx_r - 1;
2277 goto done;
2278 }
2279 }
2280
2281 done:
2282 *pcinfo_l = &pcinfo[idx_l];
2283 *pcinfo_r = &pcinfo[idx_r];
2284 }
2285
2286 /*
2287 * Get the surrounding per-rate power calibration data
2288 * for a given frequency and interpolate between power
2289 * values to set max target power supported by hw for
2290 * each rate.
2291 */
2292 static void
2293 ath5k_get_rate_pcal_data(struct ath5k_hw *ah,
2294 struct ieee80211_channel *channel,
2295 struct ath5k_rate_pcal_info *rates)
2296 {
2297 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2298 struct ath5k_rate_pcal_info *rpinfo;
2299 u8 idx_l, idx_r;
2300 u8 mode, max, i;
2301 u32 target = channel->center_freq;
2302
2303 idx_l = 0;
2304 idx_r = 0;
2305
2306 if (!(channel->hw_value & CHANNEL_OFDM)) {
2307 rpinfo = ee->ee_rate_tpwr_b;
2308 mode = AR5K_EEPROM_MODE_11B;
2309 } else if (channel->hw_value & CHANNEL_2GHZ) {
2310 rpinfo = ee->ee_rate_tpwr_g;
2311 mode = AR5K_EEPROM_MODE_11G;
2312 } else {
2313 rpinfo = ee->ee_rate_tpwr_a;
2314 mode = AR5K_EEPROM_MODE_11A;
2315 }
2316 max = ee->ee_rate_target_pwr_num[mode] - 1;
2317
2318 /* Get the surrounding calibration
2319 * piers - same as above */
2320 if (target < rpinfo[0].freq) {
2321 idx_l = idx_r = 0;
2322 goto done;
2323 }
2324
2325 if (target > rpinfo[max].freq) {
2326 idx_l = idx_r = max;
2327 goto done;
2328 }
2329
2330 for (i = 0; i <= max; i++) {
2331
2332 if (rpinfo[i].freq == target) {
2333 idx_l = idx_r = i;
2334 goto done;
2335 }
2336
2337 if (target < rpinfo[i].freq) {
2338 idx_r = i;
2339 idx_l = idx_r - 1;
2340 goto done;
2341 }
2342 }
2343
2344 done:
2345 /* Now interpolate power value, based on the frequency */
2346 rates->freq = target;
2347
2348 rates->target_power_6to24 =
2349 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2350 rpinfo[idx_r].freq,
2351 rpinfo[idx_l].target_power_6to24,
2352 rpinfo[idx_r].target_power_6to24);
2353
2354 rates->target_power_36 =
2355 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2356 rpinfo[idx_r].freq,
2357 rpinfo[idx_l].target_power_36,
2358 rpinfo[idx_r].target_power_36);
2359
2360 rates->target_power_48 =
2361 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2362 rpinfo[idx_r].freq,
2363 rpinfo[idx_l].target_power_48,
2364 rpinfo[idx_r].target_power_48);
2365
2366 rates->target_power_54 =
2367 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2368 rpinfo[idx_r].freq,
2369 rpinfo[idx_l].target_power_54,
2370 rpinfo[idx_r].target_power_54);
2371 }
2372
2373 /*
2374 * Get the max edge power for this channel if
2375 * we have such data from EEPROM's Conformance Test
2376 * Limits (CTL), and limit max power if needed.
2377 */
2378 static void
2379 ath5k_get_max_ctl_power(struct ath5k_hw *ah,
2380 struct ieee80211_channel *channel)
2381 {
2382 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
2383 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2384 struct ath5k_edge_power *rep = ee->ee_ctl_pwr;
2385 u8 *ctl_val = ee->ee_ctl;
2386 s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4;
2387 s16 edge_pwr = 0;
2388 u8 rep_idx;
2389 u8 i, ctl_mode;
2390 u8 ctl_idx = 0xFF;
2391 u32 target = channel->center_freq;
2392
2393 ctl_mode = ath_regd_get_band_ctl(regulatory, channel->band);
2394
2395 switch (channel->hw_value & CHANNEL_MODES) {
2396 case CHANNEL_A:
2397 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
2398 ctl_mode |= AR5K_CTL_TURBO;
2399 else
2400 ctl_mode |= AR5K_CTL_11A;
2401 break;
2402 case CHANNEL_G:
2403 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
2404 ctl_mode |= AR5K_CTL_TURBOG;
2405 else
2406 ctl_mode |= AR5K_CTL_11G;
2407 break;
2408 case CHANNEL_B:
2409 ctl_mode |= AR5K_CTL_11B;
2410 break;
2411 case CHANNEL_XR:
2412 /* Fall through */
2413 default:
2414 return;
2415 }
2416
2417 for (i = 0; i < ee->ee_ctls; i++) {
2418 if (ctl_val[i] == ctl_mode) {
2419 ctl_idx = i;
2420 break;
2421 }
2422 }
2423
2424 /* If we have a CTL dataset available grab it and find the
2425 * edge power for our frequency */
2426 if (ctl_idx == 0xFF)
2427 return;
2428
2429 /* Edge powers are sorted by frequency from lower
2430 * to higher. Each CTL corresponds to 8 edge power
2431 * measurements. */
2432 rep_idx = ctl_idx * AR5K_EEPROM_N_EDGES;
2433
2434 /* Don't do boundaries check because we
2435 * might have more that one bands defined
2436 * for this mode */
2437
2438 /* Get the edge power that's closer to our
2439 * frequency */
2440 for (i = 0; i < AR5K_EEPROM_N_EDGES; i++) {
2441 rep_idx += i;
2442 if (target <= rep[rep_idx].freq)
2443 edge_pwr = (s16) rep[rep_idx].edge;
2444 }
2445
2446 if (edge_pwr)
2447 ah->ah_txpower.txp_max_pwr = 4 * min(edge_pwr, max_chan_pwr);
2448 }
2449
2450
2451 /*
2452 * Power to PCDAC table functions
2453 */
2454
2455 /*
2456 * Fill Power to PCDAC table on RF5111
2457 *
2458 * No further processing is needed for RF5111, the only thing we have to
2459 * do is fill the values below and above calibration range since eeprom data
2460 * may not cover the entire PCDAC table.
2461 */
2462 static void
2463 ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min,
2464 s16 *table_max)
2465 {
2466 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2467 u8 *pcdac_tmp = ah->ah_txpower.tmpL[0];
2468 u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i;
2469 s16 min_pwr, max_pwr;
2470
2471 /* Get table boundaries */
2472 min_pwr = table_min[0];
2473 pcdac_0 = pcdac_tmp[0];
2474
2475 max_pwr = table_max[0];
2476 pcdac_n = pcdac_tmp[table_max[0] - table_min[0]];
2477
2478 /* Extrapolate below minimum using pcdac_0 */
2479 pcdac_i = 0;
2480 for (i = 0; i < min_pwr; i++)
2481 pcdac_out[pcdac_i++] = pcdac_0;
2482
2483 /* Copy values from pcdac_tmp */
2484 pwr_idx = min_pwr;
2485 for (i = 0; pwr_idx <= max_pwr &&
2486 pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) {
2487 pcdac_out[pcdac_i++] = pcdac_tmp[i];
2488 pwr_idx++;
2489 }
2490
2491 /* Extrapolate above maximum */
2492 while (pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE)
2493 pcdac_out[pcdac_i++] = pcdac_n;
2494
2495 }
2496
2497 /*
2498 * Combine available XPD Curves and fill Linear Power to PCDAC table
2499 * on RF5112
2500 *
2501 * RFX112 can have up to 2 curves (one for low txpower range and one for
2502 * higher txpower range). We need to put them both on pcdac_out and place
2503 * them in the correct location. In case we only have one curve available
2504 * just fit it on pcdac_out (it's supposed to cover the entire range of
2505 * available pwr levels since it's always the higher power curve). Extrapolate
2506 * below and above final table if needed.
2507 */
2508 static void
2509 ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min,
2510 s16 *table_max, u8 pdcurves)
2511 {
2512 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2513 u8 *pcdac_low_pwr;
2514 u8 *pcdac_high_pwr;
2515 u8 *pcdac_tmp;
2516 u8 pwr;
2517 s16 max_pwr_idx;
2518 s16 min_pwr_idx;
2519 s16 mid_pwr_idx = 0;
2520 /* Edge flag turns on the 7nth bit on the PCDAC
2521 * to declare the higher power curve (force values
2522 * to be greater than 64). If we only have one curve
2523 * we don't need to set this, if we have 2 curves and
2524 * fill the table backwards this can also be used to
2525 * switch from higher power curve to lower power curve */
2526 u8 edge_flag;
2527 int i;
2528
2529 /* When we have only one curve available
2530 * that's the higher power curve. If we have
2531 * two curves the first is the high power curve
2532 * and the next is the low power curve. */
2533 if (pdcurves > 1) {
2534 pcdac_low_pwr = ah->ah_txpower.tmpL[1];
2535 pcdac_high_pwr = ah->ah_txpower.tmpL[0];
2536 mid_pwr_idx = table_max[1] - table_min[1] - 1;
2537 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
2538
2539 /* If table size goes beyond 31.5dB, keep the
2540 * upper 31.5dB range when setting tx power.
2541 * Note: 126 = 31.5 dB in quarter dB steps */
2542 if (table_max[0] - table_min[1] > 126)
2543 min_pwr_idx = table_max[0] - 126;
2544 else
2545 min_pwr_idx = table_min[1];
2546
2547 /* Since we fill table backwards
2548 * start from high power curve */
2549 pcdac_tmp = pcdac_high_pwr;
2550
2551 edge_flag = 0x40;
2552 } else {
2553 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */
2554 pcdac_high_pwr = ah->ah_txpower.tmpL[0];
2555 min_pwr_idx = table_min[0];
2556 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
2557 pcdac_tmp = pcdac_high_pwr;
2558 edge_flag = 0;
2559 }
2560
2561 /* This is used when setting tx power*/
2562 ah->ah_txpower.txp_min_idx = min_pwr_idx / 2;
2563
2564 /* Fill Power to PCDAC table backwards */
2565 pwr = max_pwr_idx;
2566 for (i = 63; i >= 0; i--) {
2567 /* Entering lower power range, reset
2568 * edge flag and set pcdac_tmp to lower
2569 * power curve.*/
2570 if (edge_flag == 0x40 &&
2571 (2 * pwr <= (table_max[1] - table_min[0]) || pwr == 0)) {
2572 edge_flag = 0x00;
2573 pcdac_tmp = pcdac_low_pwr;
2574 pwr = mid_pwr_idx / 2;
2575 }
2576
2577 /* Don't go below 1, extrapolate below if we have
2578 * already switched to the lower power curve -or
2579 * we only have one curve and edge_flag is zero
2580 * anyway */
2581 if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) {
2582 while (i >= 0) {
2583 pcdac_out[i] = pcdac_out[i + 1];
2584 i--;
2585 }
2586 break;
2587 }
2588
2589 pcdac_out[i] = pcdac_tmp[pwr] | edge_flag;
2590
2591 /* Extrapolate above if pcdac is greater than
2592 * 126 -this can happen because we OR pcdac_out
2593 * value with edge_flag on high power curve */
2594 if (pcdac_out[i] > 126)
2595 pcdac_out[i] = 126;
2596
2597 /* Decrease by a 0.5dB step */
2598 pwr--;
2599 }
2600 }
2601
2602 /* Write PCDAC values on hw */
2603 static void
2604 ath5k_write_pcdac_table(struct ath5k_hw *ah)
2605 {
2606 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2607 int i;
2608
2609 /*
2610 * Write TX power values
2611 */
2612 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2613 ath5k_hw_reg_write(ah,
2614 (((pcdac_out[2 * i + 0] << 8 | 0xff) & 0xffff) << 0) |
2615 (((pcdac_out[2 * i + 1] << 8 | 0xff) & 0xffff) << 16),
2616 AR5K_PHY_PCDAC_TXPOWER(i));
2617 }
2618 }
2619
2620
2621 /*
2622 * Power to PDADC table functions
2623 */
2624
2625 /*
2626 * Set the gain boundaries and create final Power to PDADC table
2627 *
2628 * We can have up to 4 pd curves, we need to do a similar process
2629 * as we do for RF5112. This time we don't have an edge_flag but we
2630 * set the gain boundaries on a separate register.
2631 */
2632 static void
2633 ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah,
2634 s16 *pwr_min, s16 *pwr_max, u8 pdcurves)
2635 {
2636 u8 gain_boundaries[AR5K_EEPROM_N_PD_GAINS];
2637 u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
2638 u8 *pdadc_tmp;
2639 s16 pdadc_0;
2640 u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size;
2641 u8 pd_gain_overlap;
2642
2643 /* Note: Register value is initialized on initvals
2644 * there is no feedback from hw.
2645 * XXX: What about pd_gain_overlap from EEPROM ? */
2646 pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) &
2647 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP;
2648
2649 /* Create final PDADC table */
2650 for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) {
2651 pdadc_tmp = ah->ah_txpower.tmpL[pdg];
2652
2653 if (pdg == pdcurves - 1)
2654 /* 2 dB boundary stretch for last
2655 * (higher power) curve */
2656 gain_boundaries[pdg] = pwr_max[pdg] + 4;
2657 else
2658 /* Set gain boundary in the middle
2659 * between this curve and the next one */
2660 gain_boundaries[pdg] =
2661 (pwr_max[pdg] + pwr_min[pdg + 1]) / 2;
2662
2663 /* Sanity check in case our 2 db stretch got out of
2664 * range. */
2665 if (gain_boundaries[pdg] > AR5K_TUNE_MAX_TXPOWER)
2666 gain_boundaries[pdg] = AR5K_TUNE_MAX_TXPOWER;
2667
2668 /* For the first curve (lower power)
2669 * start from 0 dB */
2670 if (pdg == 0)
2671 pdadc_0 = 0;
2672 else
2673 /* For the other curves use the gain overlap */
2674 pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) -
2675 pd_gain_overlap;
2676
2677 /* Force each power step to be at least 0.5 dB */
2678 if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1)
2679 pwr_step = pdadc_tmp[1] - pdadc_tmp[0];
2680 else
2681 pwr_step = 1;
2682
2683 /* If pdadc_0 is negative, we need to extrapolate
2684 * below this pdgain by a number of pwr_steps */
2685 while ((pdadc_0 < 0) && (pdadc_i < 128)) {
2686 s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step;
2687 pdadc_out[pdadc_i++] = (tmp < 0) ? 0 : (u8) tmp;
2688 pdadc_0++;
2689 }
2690
2691 /* Set last pwr level, using gain boundaries */
2692 pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg];
2693 /* Limit it to be inside pwr range */
2694 table_size = pwr_max[pdg] - pwr_min[pdg];
2695 max_idx = (pdadc_n < table_size) ? pdadc_n : table_size;
2696
2697 /* Fill pdadc_out table */
2698 while (pdadc_0 < max_idx && pdadc_i < 128)
2699 pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++];
2700
2701 /* Need to extrapolate above this pdgain? */
2702 if (pdadc_n <= max_idx)
2703 continue;
2704
2705 /* Force each power step to be at least 0.5 dB */
2706 if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1)
2707 pwr_step = pdadc_tmp[table_size - 1] -
2708 pdadc_tmp[table_size - 2];
2709 else
2710 pwr_step = 1;
2711
2712 /* Extrapolate above */
2713 while ((pdadc_0 < (s16) pdadc_n) &&
2714 (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2)) {
2715 s16 tmp = pdadc_tmp[table_size - 1] +
2716 (pdadc_0 - max_idx) * pwr_step;
2717 pdadc_out[pdadc_i++] = (tmp > 127) ? 127 : (u8) tmp;
2718 pdadc_0++;
2719 }
2720 }
2721
2722 while (pdg < AR5K_EEPROM_N_PD_GAINS) {
2723 gain_boundaries[pdg] = gain_boundaries[pdg - 1];
2724 pdg++;
2725 }
2726
2727 while (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2) {
2728 pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1];
2729 pdadc_i++;
2730 }
2731
2732 /* Set gain boundaries */
2733 ath5k_hw_reg_write(ah,
2734 AR5K_REG_SM(pd_gain_overlap,
2735 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP) |
2736 AR5K_REG_SM(gain_boundaries[0],
2737 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1) |
2738 AR5K_REG_SM(gain_boundaries[1],
2739 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2) |
2740 AR5K_REG_SM(gain_boundaries[2],
2741 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3) |
2742 AR5K_REG_SM(gain_boundaries[3],
2743 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4),
2744 AR5K_PHY_TPC_RG5);
2745
2746 /* Used for setting rate power table */
2747 ah->ah_txpower.txp_min_idx = pwr_min[0];
2748
2749 }
2750
2751 /* Write PDADC values on hw */
2752 static void
2753 ath5k_write_pwr_to_pdadc_table(struct ath5k_hw *ah, u8 ee_mode)
2754 {
2755 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2756 u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
2757 u8 *pdg_to_idx = ee->ee_pdc_to_idx[ee_mode];
2758 u8 pdcurves = ee->ee_pd_gains[ee_mode];
2759 u32 reg;
2760 u8 i;
2761
2762 /* Select the right pdgain curves */
2763
2764 /* Clear current settings */
2765 reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1);
2766 reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 |
2767 AR5K_PHY_TPC_RG1_PDGAIN_2 |
2768 AR5K_PHY_TPC_RG1_PDGAIN_3 |
2769 AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
2770
2771 /*
2772 * Use pd_gains curve from eeprom
2773 *
2774 * This overrides the default setting from initvals
2775 * in case some vendors (e.g. Zcomax) don't use the default
2776 * curves. If we don't honor their settings we 'll get a
2777 * 5dB (1 * gain overlap ?) drop.
2778 */
2779 reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
2780
2781 switch (pdcurves) {
2782 case 3:
2783 reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3);
2784 /* Fall through */
2785 case 2:
2786 reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2);
2787 /* Fall through */
2788 case 1:
2789 reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1);
2790 break;
2791 }
2792 ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1);
2793
2794 /*
2795 * Write TX power values
2796 */
2797 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2798 u32 val = get_unaligned_le32(&pdadc_out[4 * i]);
2799 ath5k_hw_reg_write(ah, val, AR5K_PHY_PDADC_TXPOWER(i));
2800 }
2801 }
2802
2803
2804 /*
2805 * Common code for PCDAC/PDADC tables
2806 */
2807
2808 /*
2809 * This is the main function that uses all of the above
2810 * to set PCDAC/PDADC table on hw for the current channel.
2811 * This table is used for tx power calibration on the baseband,
2812 * without it we get weird tx power levels and in some cases
2813 * distorted spectral mask
2814 */
2815 static int
2816 ath5k_setup_channel_powertable(struct ath5k_hw *ah,
2817 struct ieee80211_channel *channel,
2818 u8 ee_mode, u8 type)
2819 {
2820 struct ath5k_pdgain_info *pdg_L, *pdg_R;
2821 struct ath5k_chan_pcal_info *pcinfo_L;
2822 struct ath5k_chan_pcal_info *pcinfo_R;
2823 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2824 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
2825 s16 table_min[AR5K_EEPROM_N_PD_GAINS];
2826 s16 table_max[AR5K_EEPROM_N_PD_GAINS];
2827 u8 *tmpL;
2828 u8 *tmpR;
2829 u32 target = channel->center_freq;
2830 int pdg, i;
2831
2832 /* Get surrounding freq piers for this channel */
2833 ath5k_get_chan_pcal_surrounding_piers(ah, channel,
2834 &pcinfo_L,
2835 &pcinfo_R);
2836
2837 /* Loop over pd gain curves on
2838 * surrounding freq piers by index */
2839 for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) {
2840
2841 /* Fill curves in reverse order
2842 * from lower power (max gain)
2843 * to higher power. Use curve -> idx
2844 * backmapping we did on eeprom init */
2845 u8 idx = pdg_curve_to_idx[pdg];
2846
2847 /* Grab the needed curves by index */
2848 pdg_L = &pcinfo_L->pd_curves[idx];
2849 pdg_R = &pcinfo_R->pd_curves[idx];
2850
2851 /* Initialize the temp tables */
2852 tmpL = ah->ah_txpower.tmpL[pdg];
2853 tmpR = ah->ah_txpower.tmpR[pdg];
2854
2855 /* Set curve's x boundaries and create
2856 * curves so that they cover the same
2857 * range (if we don't do that one table
2858 * will have values on some range and the
2859 * other one won't have any so interpolation
2860 * will fail) */
2861 table_min[pdg] = min(pdg_L->pd_pwr[0],
2862 pdg_R->pd_pwr[0]) / 2;
2863
2864 table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
2865 pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2;
2866
2867 /* Now create the curves on surrounding channels
2868 * and interpolate if needed to get the final
2869 * curve for this gain on this channel */
2870 switch (type) {
2871 case AR5K_PWRTABLE_LINEAR_PCDAC:
2872 /* Override min/max so that we don't loose
2873 * accuracy (don't divide by 2) */
2874 table_min[pdg] = min(pdg_L->pd_pwr[0],
2875 pdg_R->pd_pwr[0]);
2876
2877 table_max[pdg] =
2878 max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
2879 pdg_R->pd_pwr[pdg_R->pd_points - 1]);
2880
2881 /* Override minimum so that we don't get
2882 * out of bounds while extrapolating
2883 * below. Don't do this when we have 2
2884 * curves and we are on the high power curve
2885 * because table_min is ok in this case */
2886 if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) {
2887
2888 table_min[pdg] =
2889 ath5k_get_linear_pcdac_min(pdg_L->pd_step,
2890 pdg_R->pd_step,
2891 pdg_L->pd_pwr,
2892 pdg_R->pd_pwr);
2893
2894 /* Don't go too low because we will
2895 * miss the upper part of the curve.
2896 * Note: 126 = 31.5dB (max power supported)
2897 * in 0.25dB units */
2898 if (table_max[pdg] - table_min[pdg] > 126)
2899 table_min[pdg] = table_max[pdg] - 126;
2900 }
2901
2902 /* Fall through */
2903 case AR5K_PWRTABLE_PWR_TO_PCDAC:
2904 case AR5K_PWRTABLE_PWR_TO_PDADC:
2905
2906 ath5k_create_power_curve(table_min[pdg],
2907 table_max[pdg],
2908 pdg_L->pd_pwr,
2909 pdg_L->pd_step,
2910 pdg_L->pd_points, tmpL, type);
2911
2912 /* We are in a calibration
2913 * pier, no need to interpolate
2914 * between freq piers */
2915 if (pcinfo_L == pcinfo_R)
2916 continue;
2917
2918 ath5k_create_power_curve(table_min[pdg],
2919 table_max[pdg],
2920 pdg_R->pd_pwr,
2921 pdg_R->pd_step,
2922 pdg_R->pd_points, tmpR, type);
2923 break;
2924 default:
2925 return -EINVAL;
2926 }
2927
2928 /* Interpolate between curves
2929 * of surrounding freq piers to
2930 * get the final curve for this
2931 * pd gain. Re-use tmpL for interpolation
2932 * output */
2933 for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) &&
2934 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
2935 tmpL[i] = (u8) ath5k_get_interpolated_value(target,
2936 (s16) pcinfo_L->freq,
2937 (s16) pcinfo_R->freq,
2938 (s16) tmpL[i],
2939 (s16) tmpR[i]);
2940 }
2941 }
2942
2943 /* Now we have a set of curves for this
2944 * channel on tmpL (x range is table_max - table_min
2945 * and y values are tmpL[pdg][]) sorted in the same
2946 * order as EEPROM (because we've used the backmapping).
2947 * So for RF5112 it's from higher power to lower power
2948 * and for RF2413 it's from lower power to higher power.
2949 * For RF5111 we only have one curve. */
2950
2951 /* Fill min and max power levels for this
2952 * channel by interpolating the values on
2953 * surrounding channels to complete the dataset */
2954 ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target,
2955 (s16) pcinfo_L->freq,
2956 (s16) pcinfo_R->freq,
2957 pcinfo_L->min_pwr, pcinfo_R->min_pwr);
2958
2959 ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target,
2960 (s16) pcinfo_L->freq,
2961 (s16) pcinfo_R->freq,
2962 pcinfo_L->max_pwr, pcinfo_R->max_pwr);
2963
2964 /* Fill PCDAC/PDADC table */
2965 switch (type) {
2966 case AR5K_PWRTABLE_LINEAR_PCDAC:
2967 /* For RF5112 we can have one or two curves
2968 * and each curve covers a certain power lvl
2969 * range so we need to do some more processing */
2970 ath5k_combine_linear_pcdac_curves(ah, table_min, table_max,
2971 ee->ee_pd_gains[ee_mode]);
2972
2973 /* Set txp.offset so that we can
2974 * match max power value with max
2975 * table index */
2976 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2);
2977 break;
2978 case AR5K_PWRTABLE_PWR_TO_PCDAC:
2979 /* We are done for RF5111 since it has only
2980 * one curve, just fit the curve on the table */
2981 ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max);
2982
2983 /* No rate powertable adjustment for RF5111 */
2984 ah->ah_txpower.txp_min_idx = 0;
2985 ah->ah_txpower.txp_offset = 0;
2986 break;
2987 case AR5K_PWRTABLE_PWR_TO_PDADC:
2988 /* Set PDADC boundaries and fill
2989 * final PDADC table */
2990 ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max,
2991 ee->ee_pd_gains[ee_mode]);
2992
2993 /* Set txp.offset, note that table_min
2994 * can be negative */
2995 ah->ah_txpower.txp_offset = table_min[0];
2996 break;
2997 default:
2998 return -EINVAL;
2999 }
3000
3001 ah->ah_txpower.txp_setup = true;
3002
3003 return 0;
3004 }
3005
3006 /* Write power table for current channel to hw */
3007 static void
3008 ath5k_write_channel_powertable(struct ath5k_hw *ah, u8 ee_mode, u8 type)
3009 {
3010 if (type == AR5K_PWRTABLE_PWR_TO_PDADC)
3011 ath5k_write_pwr_to_pdadc_table(ah, ee_mode);
3012 else
3013 ath5k_write_pcdac_table(ah);
3014 }
3015
3016 /*
3017 * Per-rate tx power setting
3018 *
3019 * This is the code that sets the desired tx power (below
3020 * maximum) on hw for each rate (we also have TPC that sets
3021 * power per packet). We do that by providing an index on the
3022 * PCDAC/PDADC table we set up.
3023 */
3024
3025 /*
3026 * Set rate power table
3027 *
3028 * For now we only limit txpower based on maximum tx power
3029 * supported by hw (what's inside rate_info). We need to limit
3030 * this even more, based on regulatory domain etc.
3031 *
3032 * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps)
3033 * and is indexed as follows:
3034 * rates[0] - rates[7] -> OFDM rates
3035 * rates[8] - rates[14] -> CCK rates
3036 * rates[15] -> XR rates (they all have the same power)
3037 */
3038 static void
3039 ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr,
3040 struct ath5k_rate_pcal_info *rate_info,
3041 u8 ee_mode)
3042 {
3043 unsigned int i;
3044 u16 *rates;
3045
3046 /* max_pwr is power level we got from driver/user in 0.5dB
3047 * units, switch to 0.25dB units so we can compare */
3048 max_pwr *= 2;
3049 max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2;
3050
3051 /* apply rate limits */
3052 rates = ah->ah_txpower.txp_rates_power_table;
3053
3054 /* OFDM rates 6 to 24Mb/s */
3055 for (i = 0; i < 5; i++)
3056 rates[i] = min(max_pwr, rate_info->target_power_6to24);
3057
3058 /* Rest OFDM rates */
3059 rates[5] = min(rates[0], rate_info->target_power_36);
3060 rates[6] = min(rates[0], rate_info->target_power_48);
3061 rates[7] = min(rates[0], rate_info->target_power_54);
3062
3063 /* CCK rates */
3064 /* 1L */
3065 rates[8] = min(rates[0], rate_info->target_power_6to24);
3066 /* 2L */
3067 rates[9] = min(rates[0], rate_info->target_power_36);
3068 /* 2S */
3069 rates[10] = min(rates[0], rate_info->target_power_36);
3070 /* 5L */
3071 rates[11] = min(rates[0], rate_info->target_power_48);
3072 /* 5S */
3073 rates[12] = min(rates[0], rate_info->target_power_48);
3074 /* 11L */
3075 rates[13] = min(rates[0], rate_info->target_power_54);
3076 /* 11S */
3077 rates[14] = min(rates[0], rate_info->target_power_54);
3078
3079 /* XR rates */
3080 rates[15] = min(rates[0], rate_info->target_power_6to24);
3081
3082 /* CCK rates have different peak to average ratio
3083 * so we have to tweak their power so that gainf
3084 * correction works ok. For this we use OFDM to
3085 * CCK delta from eeprom */
3086 if ((ee_mode == AR5K_EEPROM_MODE_11G) &&
3087 (ah->ah_phy_revision < AR5K_SREV_PHY_5212A))
3088 for (i = 8; i <= 15; i++)
3089 rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta;
3090
3091 /* Now that we have all rates setup use table offset to
3092 * match the power range set by user with the power indices
3093 * on PCDAC/PDADC table */
3094 for (i = 0; i < 16; i++) {
3095 rates[i] += ah->ah_txpower.txp_offset;
3096 /* Don't get out of bounds */
3097 if (rates[i] > 63)
3098 rates[i] = 63;
3099 }
3100
3101 /* Min/max in 0.25dB units */
3102 ah->ah_txpower.txp_min_pwr = 2 * rates[7];
3103 ah->ah_txpower.txp_cur_pwr = 2 * rates[0];
3104 ah->ah_txpower.txp_ofdm = rates[7];
3105 }
3106
3107
3108 /*
3109 * Set transmission power
3110 */
3111 static int
3112 ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
3113 u8 txpower)
3114 {
3115 struct ath5k_rate_pcal_info rate_info;
3116 struct ieee80211_channel *curr_channel = ah->ah_current_channel;
3117 int ee_mode;
3118 u8 type;
3119 int ret;
3120
3121 if (txpower > AR5K_TUNE_MAX_TXPOWER) {
3122 ATH5K_ERR(ah, "invalid tx power: %u\n", txpower);
3123 return -EINVAL;
3124 }
3125
3126 ee_mode = ath5k_eeprom_mode_from_channel(channel);
3127 if (ee_mode < 0) {
3128 ATH5K_ERR(ah,
3129 "invalid channel: %d\n", channel->center_freq);
3130 return -EINVAL;
3131 }
3132
3133 /* Initialize TX power table */
3134 switch (ah->ah_radio) {
3135 case AR5K_RF5110:
3136 /* TODO */
3137 return 0;
3138 case AR5K_RF5111:
3139 type = AR5K_PWRTABLE_PWR_TO_PCDAC;
3140 break;
3141 case AR5K_RF5112:
3142 type = AR5K_PWRTABLE_LINEAR_PCDAC;
3143 break;
3144 case AR5K_RF2413:
3145 case AR5K_RF5413:
3146 case AR5K_RF2316:
3147 case AR5K_RF2317:
3148 case AR5K_RF2425:
3149 type = AR5K_PWRTABLE_PWR_TO_PDADC;
3150 break;
3151 default:
3152 return -EINVAL;
3153 }
3154
3155 /*
3156 * If we don't change channel/mode skip tx powertable calculation
3157 * and use the cached one.
3158 */
3159 if (!ah->ah_txpower.txp_setup ||
3160 (channel->hw_value != curr_channel->hw_value) ||
3161 (channel->center_freq != curr_channel->center_freq)) {
3162 /* Reset TX power values */
3163 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
3164 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
3165
3166 /* Calculate the powertable */
3167 ret = ath5k_setup_channel_powertable(ah, channel,
3168 ee_mode, type);
3169 if (ret)
3170 return ret;
3171 }
3172
3173 /* Write table on hw */
3174 ath5k_write_channel_powertable(ah, ee_mode, type);
3175
3176 /* Limit max power if we have a CTL available */
3177 ath5k_get_max_ctl_power(ah, channel);
3178
3179 /* FIXME: Antenna reduction stuff */
3180
3181 /* FIXME: Limit power on turbo modes */
3182
3183 /* FIXME: TPC scale reduction */
3184
3185 /* Get surrounding channels for per-rate power table
3186 * calibration */
3187 ath5k_get_rate_pcal_data(ah, channel, &rate_info);
3188
3189 /* Setup rate power table */
3190 ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode);
3191
3192 /* Write rate power table on hw */
3193 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) |
3194 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) |
3195 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1);
3196
3197 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) |
3198 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) |
3199 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2);
3200
3201 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) |
3202 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) |
3203 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3);
3204
3205 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) |
3206 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
3207 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);
3208
3209 /* FIXME: TPC support */
3210 if (ah->ah_txpower.txp_tpc) {
3211 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
3212 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
3213
3214 ath5k_hw_reg_write(ah,
3215 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) |
3216 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) |
3217 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP),
3218 AR5K_TPC);
3219 } else {
3220 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX |
3221 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
3222 }
3223
3224 return 0;
3225 }
3226
3227 int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower)
3228 {
3229 ATH5K_DBG(ah, ATH5K_DEBUG_TXPOWER,
3230 "changing txpower to %d\n", txpower);
3231
3232 return ath5k_hw_txpower(ah, ah->ah_current_channel, txpower);
3233 }
3234
3235 /*************\
3236 Init function
3237 \*************/
3238
3239 int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
3240 u8 mode, bool fast)
3241 {
3242 struct ieee80211_channel *curr_channel;
3243 int ret, i;
3244 u32 phy_tst1;
3245 ret = 0;
3246
3247 /*
3248 * Sanity check for fast flag
3249 * Don't try fast channel change when changing modulation
3250 * mode/band. We check for chip compatibility on
3251 * ath5k_hw_reset.
3252 */
3253 curr_channel = ah->ah_current_channel;
3254 if (fast && (channel->hw_value != curr_channel->hw_value))
3255 return -EINVAL;
3256
3257 /*
3258 * On fast channel change we only set the synth parameters
3259 * while PHY is running, enable calibration and skip the rest.
3260 */
3261 if (fast) {
3262 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_RFBUS_REQ,
3263 AR5K_PHY_RFBUS_REQ_REQUEST);
3264 for (i = 0; i < 100; i++) {
3265 if (ath5k_hw_reg_read(ah, AR5K_PHY_RFBUS_GRANT))
3266 break;
3267 udelay(5);
3268 }
3269 /* Failed */
3270 if (i >= 100)
3271 return -EIO;
3272
3273 /* Set channel and wait for synth */
3274 ret = ath5k_hw_channel(ah, channel);
3275 if (ret)
3276 return ret;
3277
3278 ath5k_hw_wait_for_synth(ah, channel);
3279 }
3280
3281 /*
3282 * Set TX power
3283 *
3284 * Note: We need to do that before we set
3285 * RF buffer settings on 5211/5212+ so that we
3286 * properly set curve indices.
3287 */
3288 ret = ath5k_hw_txpower(ah, channel, ah->ah_txpower.txp_cur_pwr ?
3289 ah->ah_txpower.txp_cur_pwr / 2 : AR5K_TUNE_MAX_TXPOWER);
3290 if (ret)
3291 return ret;
3292
3293 /* Write OFDM timings on 5212*/
3294 if (ah->ah_version == AR5K_AR5212 &&
3295 channel->hw_value & CHANNEL_OFDM) {
3296
3297 ret = ath5k_hw_write_ofdm_timings(ah, channel);
3298 if (ret)
3299 return ret;
3300
3301 /* Spur info is available only from EEPROM versions
3302 * greater than 5.3, but the EEPROM routines will use
3303 * static values for older versions */
3304 if (ah->ah_mac_srev >= AR5K_SREV_AR5424)
3305 ath5k_hw_set_spur_mitigation_filter(ah,
3306 channel);
3307 }
3308
3309 /* If we used fast channel switching
3310 * we are done, release RF bus and
3311 * fire up NF calibration.
3312 *
3313 * Note: Only NF calibration due to
3314 * channel change, not AGC calibration
3315 * since AGC is still running !
3316 */
3317 if (fast) {
3318 /*
3319 * Release RF Bus grant
3320 */
3321 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_RFBUS_REQ,
3322 AR5K_PHY_RFBUS_REQ_REQUEST);
3323
3324 /*
3325 * Start NF calibration
3326 */
3327 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
3328 AR5K_PHY_AGCCTL_NF);
3329
3330 return ret;
3331 }
3332
3333 /*
3334 * For 5210 we do all initialization using
3335 * initvals, so we don't have to modify
3336 * any settings (5210 also only supports
3337 * a/aturbo modes)
3338 */
3339 if (ah->ah_version != AR5K_AR5210) {
3340
3341 /*
3342 * Write initial RF gain settings
3343 * This should work for both 5111/5112
3344 */
3345 ret = ath5k_hw_rfgain_init(ah, channel->band);
3346 if (ret)
3347 return ret;
3348
3349 mdelay(1);
3350
3351 /*
3352 * Write RF buffer
3353 */
3354 ret = ath5k_hw_rfregs_init(ah, channel, mode);
3355 if (ret)
3356 return ret;
3357
3358 /*Enable/disable 802.11b mode on 5111
3359 (enable 2111 frequency converter + CCK)*/
3360 if (ah->ah_radio == AR5K_RF5111) {
3361 if (mode == AR5K_MODE_11B)
3362 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG,
3363 AR5K_TXCFG_B_MODE);
3364 else
3365 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
3366 AR5K_TXCFG_B_MODE);
3367 }
3368
3369 } else if (ah->ah_version == AR5K_AR5210) {
3370 mdelay(1);
3371 /* Disable phy and wait */
3372 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
3373 mdelay(1);
3374 }
3375
3376 /* Set channel on PHY */
3377 ret = ath5k_hw_channel(ah, channel);
3378 if (ret)
3379 return ret;
3380
3381 /*
3382 * Enable the PHY and wait until completion
3383 * This includes BaseBand and Synthesizer
3384 * activation.
3385 */
3386 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
3387
3388 ath5k_hw_wait_for_synth(ah, channel);
3389
3390 /*
3391 * Perform ADC test to see if baseband is ready
3392 * Set tx hold and check adc test register
3393 */
3394 phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1);
3395 ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1);
3396 for (i = 0; i <= 20; i++) {
3397 if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10))
3398 break;
3399 udelay(200);
3400 }
3401 ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1);
3402
3403 /*
3404 * Start automatic gain control calibration
3405 *
3406 * During AGC calibration RX path is re-routed to
3407 * a power detector so we don't receive anything.
3408 *
3409 * This method is used to calibrate some static offsets
3410 * used together with on-the fly I/Q calibration (the
3411 * one performed via ath5k_hw_phy_calibrate), which doesn't
3412 * interrupt rx path.
3413 *
3414 * While rx path is re-routed to the power detector we also
3415 * start a noise floor calibration to measure the
3416 * card's noise floor (the noise we measure when we are not
3417 * transmitting or receiving anything).
3418 *
3419 * If we are in a noisy environment, AGC calibration may time
3420 * out and/or noise floor calibration might timeout.
3421 */
3422 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
3423 AR5K_PHY_AGCCTL_CAL | AR5K_PHY_AGCCTL_NF);
3424
3425 /* At the same time start I/Q calibration for QAM constellation
3426 * -no need for CCK- */
3427 ah->ah_calibration = false;
3428 if (!(mode == AR5K_MODE_11B)) {
3429 ah->ah_calibration = true;
3430 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
3431 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
3432 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
3433 AR5K_PHY_IQ_RUN);
3434 }
3435
3436 /* Wait for gain calibration to finish (we check for I/Q calibration
3437 * during ath5k_phy_calibrate) */
3438 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
3439 AR5K_PHY_AGCCTL_CAL, 0, false)) {
3440 ATH5K_ERR(ah, "gain calibration timeout (%uMHz)\n",
3441 channel->center_freq);
3442 }
3443
3444 /* Restore antenna mode */
3445 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
3446
3447 return ret;
3448 }
Linux kernel - Deliverables
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