drivers/net/wireless/ath/ath9k/ar9003_mac.c

   1 /*
   2  * Copyright (c) 2010 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16 #include "hw.h"
  17
  18 static void ar9003_hw_rx_enable(struct ath_hw *hw)
  19 {
  20         REG_WRITE(hw, AR_CR, 0);
  21 }
  22
  23 static void ar9003_hw_set_desc_link(void *ds, u32 ds_link)
  24 {
  25         ((struct ar9003_txc *) ds)->link = ds_link;
  26 }
  27
  28 static void ar9003_hw_get_desc_link(void *ds, u32 **ds_link)
  29 {
  30         *ds_link = &((struct ar9003_txc *) ds)->link;
  31 }
  32
  33 static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
  34 {
  35         u32 isr = 0;
  36         u32 mask2 = 0;
  37         struct ath9k_hw_capabilities *pCap = &ah->caps;
  38         u32 sync_cause = 0;
  39         struct ath_common *common = ath9k_hw_common(ah);
  40
  41         if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
  42                 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
  43                                 == AR_RTC_STATUS_ON)
  44                         isr = REG_READ(ah, AR_ISR);
  45         }
  46
  47         sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT;
  48
  49         *masked = 0;
  50
  51         if (!isr && !sync_cause)
  52                 return false;
  53
  54         if (isr) {
  55                 if (isr & AR_ISR_BCNMISC) {
  56                         u32 isr2;
  57                         isr2 = REG_READ(ah, AR_ISR_S2);
  58
  59                         mask2 |= ((isr2 & AR_ISR_S2_TIM) >>
  60                                   MAP_ISR_S2_TIM);
  61                         mask2 |= ((isr2 & AR_ISR_S2_DTIM) >>
  62                                   MAP_ISR_S2_DTIM);
  63                         mask2 |= ((isr2 & AR_ISR_S2_DTIMSYNC) >>
  64                                   MAP_ISR_S2_DTIMSYNC);
  65                         mask2 |= ((isr2 & AR_ISR_S2_CABEND) >>
  66                                   MAP_ISR_S2_CABEND);
  67                         mask2 |= ((isr2 & AR_ISR_S2_GTT) <<
  68                                   MAP_ISR_S2_GTT);
  69                         mask2 |= ((isr2 & AR_ISR_S2_CST) <<
  70                                   MAP_ISR_S2_CST);
  71                         mask2 |= ((isr2 & AR_ISR_S2_TSFOOR) >>
  72                                   MAP_ISR_S2_TSFOOR);
  73
  74                         if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
  75                                 REG_WRITE(ah, AR_ISR_S2, isr2);
  76                                 isr &= ~AR_ISR_BCNMISC;
  77                         }
  78                 }
  79
  80                 if ((pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED))
  81                         isr = REG_READ(ah, AR_ISR_RAC);
  82
  83                 if (isr == 0xffffffff) {
  84                         *masked = 0;
  85                         return false;
  86                 }
  87
  88                 *masked = isr & ATH9K_INT_COMMON;
  89
  90                 if (ah->config.rx_intr_mitigation)
  91                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
  92                                 *masked |= ATH9K_INT_RXLP;
  93
  94                 if (ah->config.tx_intr_mitigation)
  95                         if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM))
  96                                 *masked |= ATH9K_INT_TX;
  97
  98                 if (isr & (AR_ISR_LP_RXOK | AR_ISR_RXERR))
  99                         *masked |= ATH9K_INT_RXLP;
 100
 101                 if (isr & AR_ISR_HP_RXOK)
 102                         *masked |= ATH9K_INT_RXHP;
 103
 104                 if (isr & (AR_ISR_TXOK | AR_ISR_TXERR | AR_ISR_TXEOL)) {
 105                         *masked |= ATH9K_INT_TX;
 106
 107                         if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
 108                                 u32 s0, s1;
 109                                 s0 = REG_READ(ah, AR_ISR_S0);
 110                                 REG_WRITE(ah, AR_ISR_S0, s0);
 111                                 s1 = REG_READ(ah, AR_ISR_S1);
 112                                 REG_WRITE(ah, AR_ISR_S1, s1);
 113
 114                                 isr &= ~(AR_ISR_TXOK | AR_ISR_TXERR |
 115                                          AR_ISR_TXEOL);
 116                         }
 117                 }
 118
 119                 if (isr & AR_ISR_GENTMR) {
 120                         u32 s5;
 121
 122                         if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)
 123                                 s5 = REG_READ(ah, AR_ISR_S5_S);
 124                         else
 125                                 s5 = REG_READ(ah, AR_ISR_S5);
 126
 127                         ah->intr_gen_timer_trigger =
 128                                 MS(s5, AR_ISR_S5_GENTIMER_TRIG);
 129
 130                         ah->intr_gen_timer_thresh =
 131                                 MS(s5, AR_ISR_S5_GENTIMER_THRESH);
 132
 133                         if (ah->intr_gen_timer_trigger)
 134                                 *masked |= ATH9K_INT_GENTIMER;
 135
 136                         if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
 137                                 REG_WRITE(ah, AR_ISR_S5, s5);
 138                                 isr &= ~AR_ISR_GENTMR;
 139                         }
 140
 141                 }
 142
 143                 *masked |= mask2;
 144
 145                 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
 146                         REG_WRITE(ah, AR_ISR, isr);
 147
 148                         (void) REG_READ(ah, AR_ISR);
 149                 }
 150         }
 151
 152         if (sync_cause) {
 153                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
 154                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
 155                         REG_WRITE(ah, AR_RC, 0);
 156                         *masked |= ATH9K_INT_FATAL;
 157                 }
 158
 159                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
 160                         ath_print(common, ATH_DBG_INTERRUPT,
 161                                   "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
 162
 163                         REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
 164                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
 165
 166         }
 167         return true;
 168 }
 169
 170 static void ar9003_hw_fill_txdesc(struct ath_hw *ah, void *ds, u32 seglen,
 171                                   bool is_firstseg, bool is_lastseg,
 172                                   const void *ds0, dma_addr_t buf_addr,
 173                                   unsigned int qcu)
 174 {
 175 }
 176
 177 static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds,
 178                                  struct ath_tx_status *ts)
 179 {
 180         return 0;
 181 }
 182 static void ar9003_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
 183                             u32 pktLen, enum ath9k_pkt_type type, u32 txPower,
 184                             u32 keyIx, enum ath9k_key_type keyType, u32 flags)
 185 {
 186
 187 }
 188
 189 static void ar9003_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
 190                                           void *lastds,
 191                                           u32 durUpdateEn, u32 rtsctsRate,
 192                                           u32 rtsctsDuration,
 193                                           struct ath9k_11n_rate_series series[],
 194                                           u32 nseries, u32 flags)
 195 {
 196
 197 }
 198
 199 static void ar9003_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
 200                                         u32 aggrLen)
 201 {
 202
 203 }
 204
 205 static void ar9003_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
 206                                          u32 numDelims)
 207 {
 208
 209 }
 210
 211 static void ar9003_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
 212 {
 213
 214 }
 215
 216 static void ar9003_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
 217 {
 218
 219 }
 220
 221 static void ar9003_hw_set11n_burstduration(struct ath_hw *ah, void *ds,
 222                                            u32 burstDuration)
 223 {
 224
 225 }
 226
 227 static void ar9003_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds,
 228                                             u32 vmf)
 229 {
 230
 231 }
 232
 233 void ar9003_hw_attach_mac_ops(struct ath_hw *hw)
 234 {
 235         struct ath_hw_ops *ops = ath9k_hw_ops(hw);
 236
 237         ops->rx_enable = ar9003_hw_rx_enable;
 238         ops->set_desc_link = ar9003_hw_set_desc_link;
 239         ops->get_desc_link = ar9003_hw_get_desc_link;
 240         ops->get_isr = ar9003_hw_get_isr;
 241         ops->fill_txdesc = ar9003_hw_fill_txdesc;
 242         ops->proc_txdesc = ar9003_hw_proc_txdesc;
 243         ops->set11n_txdesc = ar9003_hw_set11n_txdesc;
 244         ops->set11n_ratescenario = ar9003_hw_set11n_ratescenario;
 245         ops->set11n_aggr_first = ar9003_hw_set11n_aggr_first;
 246         ops->set11n_aggr_middle = ar9003_hw_set11n_aggr_middle;
 247         ops->set11n_aggr_last = ar9003_hw_set11n_aggr_last;
 248         ops->clr11n_aggr = ar9003_hw_clr11n_aggr;
 249         ops->set11n_burstduration = ar9003_hw_set11n_burstduration;
 250         ops->set11n_virtualmorefrag = ar9003_hw_set11n_virtualmorefrag;
 251 }
 252
 253 void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size)
 254 {
 255         REG_WRITE(ah, AR_DATABUF_SIZE, buf_size & AR_DATABUF_SIZE_MASK);
 256 }
 257 EXPORT_SYMBOL(ath9k_hw_set_rx_bufsize);
 258
 259 void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp,
 260                             enum ath9k_rx_qtype qtype)
 261 {
 262         if (qtype == ATH9K_RX_QUEUE_HP)
 263                 REG_WRITE(ah, AR_HP_RXDP, rxdp);
 264         else
 265                 REG_WRITE(ah, AR_LP_RXDP, rxdp);
 266 }
 267 EXPORT_SYMBOL(ath9k_hw_addrxbuf_edma);
 268
 269 int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs,
 270                                  void *buf_addr)
 271 {
 272         struct ar9003_rxs *rxsp = (struct ar9003_rxs *) buf_addr;
 273         unsigned int phyerr;
 274
 275         /* TODO: byte swap on big endian for ar9300_10 */
 276
 277         if ((rxsp->status11 & AR_RxDone) == 0)
 278                 return -EINPROGRESS;
 279
 280         if (MS(rxsp->ds_info, AR_DescId) != 0x168c)
 281                 return -EINVAL;
 282
 283         if ((rxsp->ds_info & (AR_TxRxDesc | AR_CtrlStat)) != 0)
 284                 return -EINPROGRESS;
 285
 286         if (!rxs)
 287                 return 0;
 288
 289         rxs->rs_status = 0;
 290         rxs->rs_flags =  0;
 291
 292         rxs->rs_datalen = rxsp->status2 & AR_DataLen;
 293         rxs->rs_tstamp =  rxsp->status3;
 294
 295         /* XXX: Keycache */
 296         rxs->rs_rssi = MS(rxsp->status5, AR_RxRSSICombined);
 297         rxs->rs_rssi_ctl0 = MS(rxsp->status1, AR_RxRSSIAnt00);
 298         rxs->rs_rssi_ctl1 = MS(rxsp->status1, AR_RxRSSIAnt01);
 299         rxs->rs_rssi_ctl2 = MS(rxsp->status1, AR_RxRSSIAnt02);
 300         rxs->rs_rssi_ext0 = MS(rxsp->status5, AR_RxRSSIAnt10);
 301         rxs->rs_rssi_ext1 = MS(rxsp->status5, AR_RxRSSIAnt11);
 302         rxs->rs_rssi_ext2 = MS(rxsp->status5, AR_RxRSSIAnt12);
 303
 304         if (rxsp->status11 & AR_RxKeyIdxValid)
 305                 rxs->rs_keyix = MS(rxsp->status11, AR_KeyIdx);
 306         else
 307                 rxs->rs_keyix = ATH9K_RXKEYIX_INVALID;
 308
 309         rxs->rs_rate = MS(rxsp->status1, AR_RxRate);
 310         rxs->rs_more = (rxsp->status2 & AR_RxMore) ? 1 : 0;
 311
 312         rxs->rs_isaggr = (rxsp->status11 & AR_RxAggr) ? 1 : 0;
 313         rxs->rs_moreaggr = (rxsp->status11 & AR_RxMoreAggr) ? 1 : 0;
 314         rxs->rs_antenna = (MS(rxsp->status4, AR_RxAntenna) & 0x7);
 315         rxs->rs_flags  = (rxsp->status4 & AR_GI) ? ATH9K_RX_GI : 0;
 316         rxs->rs_flags  |= (rxsp->status4 & AR_2040) ? ATH9K_RX_2040 : 0;
 317
 318         rxs->evm0 = rxsp->status6;
 319         rxs->evm1 = rxsp->status7;
 320         rxs->evm2 = rxsp->status8;
 321         rxs->evm3 = rxsp->status9;
 322         rxs->evm4 = (rxsp->status10 & 0xffff);
 323
 324         if (rxsp->status11 & AR_PreDelimCRCErr)
 325                 rxs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
 326
 327         if (rxsp->status11 & AR_PostDelimCRCErr)
 328                 rxs->rs_flags |= ATH9K_RX_DELIM_CRC_POST;
 329
 330         if (rxsp->status11 & AR_DecryptBusyErr)
 331                 rxs->rs_flags |= ATH9K_RX_DECRYPT_BUSY;
 332
 333         if ((rxsp->status11 & AR_RxFrameOK) == 0) {
 334                 if (rxsp->status11 & AR_CRCErr) {
 335                         rxs->rs_status |= ATH9K_RXERR_CRC;
 336                 } else if (rxsp->status11 & AR_PHYErr) {
 337                         rxs->rs_status |= ATH9K_RXERR_PHY;
 338                         phyerr = MS(rxsp->status11, AR_PHYErrCode);
 339                         rxs->rs_phyerr = phyerr;
 340                 } else if (rxsp->status11 & AR_DecryptCRCErr) {
 341                         rxs->rs_status |= ATH9K_RXERR_DECRYPT;
 342                 } else if (rxsp->status11 & AR_MichaelErr) {
 343                         rxs->rs_status |= ATH9K_RXERR_MIC;
 344                 }
 345         }
 346
 347         return 0;
 348 }
 349 EXPORT_SYMBOL(ath9k_hw_process_rxdesc_edma);
 350
 351 void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah)
 352 {
 353         ah->ts_tail = 0;
 354
 355         memset((void *) ah->ts_ring, 0,
 356                 ah->ts_size * sizeof(struct ar9003_txs));
 357
 358         ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
 359                   "TS Start 0x%x End 0x%x Virt %p, Size %d\n",
 360                    ah->ts_paddr_start, ah->ts_paddr_end,
 361                    ah->ts_ring, ah->ts_size);
 362
 363         REG_WRITE(ah, AR_Q_STATUS_RING_START, ah->ts_paddr_start);
 364         REG_WRITE(ah, AR_Q_STATUS_RING_END, ah->ts_paddr_end);
 365 }
 366
 367 void ath9k_hw_setup_statusring(struct ath_hw *ah, void *ts_start,
 368                                u32 ts_paddr_start,
 369                                u8 size)
 370 {
 371
 372         ah->ts_paddr_start = ts_paddr_start;
 373         ah->ts_paddr_end = ts_paddr_start + (size * sizeof(struct ar9003_txs));
 374         ah->ts_size = size;
 375         ah->ts_ring = (struct ar9003_txs *) ts_start;
 376
 377         ath9k_hw_reset_txstatus_ring(ah);
 378 }
 379 EXPORT_SYMBOL(ath9k_hw_setup_statusring);