2 * Copyright (c) 2010 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 static void ar9003_hw_rx_enable(struct ath_hw
*hw
)
20 REG_WRITE(hw
, AR_CR
, 0);
23 static void ar9003_hw_set_desc_link(void *ds
, u32 ds_link
)
25 ((struct ar9003_txc
*) ds
)->link
= ds_link
;
28 static void ar9003_hw_get_desc_link(void *ds
, u32
**ds_link
)
30 *ds_link
= &((struct ar9003_txc
*) ds
)->link
;
33 static bool ar9003_hw_get_isr(struct ath_hw
*ah
, enum ath9k_int
*masked
)
37 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
39 struct ath_common
*common
= ath9k_hw_common(ah
);
41 if (REG_READ(ah
, AR_INTR_ASYNC_CAUSE
) & AR_INTR_MAC_IRQ
) {
42 if ((REG_READ(ah
, AR_RTC_STATUS
) & AR_RTC_STATUS_M
)
44 isr
= REG_READ(ah
, AR_ISR
);
47 sync_cause
= REG_READ(ah
, AR_INTR_SYNC_CAUSE
) & AR_INTR_SYNC_DEFAULT
;
51 if (!isr
&& !sync_cause
)
55 if (isr
& AR_ISR_BCNMISC
) {
57 isr2
= REG_READ(ah
, AR_ISR_S2
);
59 mask2
|= ((isr2
& AR_ISR_S2_TIM
) >>
61 mask2
|= ((isr2
& AR_ISR_S2_DTIM
) >>
63 mask2
|= ((isr2
& AR_ISR_S2_DTIMSYNC
) >>
65 mask2
|= ((isr2
& AR_ISR_S2_CABEND
) >>
67 mask2
|= ((isr2
& AR_ISR_S2_GTT
) <<
69 mask2
|= ((isr2
& AR_ISR_S2_CST
) <<
71 mask2
|= ((isr2
& AR_ISR_S2_TSFOOR
) >>
74 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_RAC_SUPPORTED
)) {
75 REG_WRITE(ah
, AR_ISR_S2
, isr2
);
76 isr
&= ~AR_ISR_BCNMISC
;
80 if ((pCap
->hw_caps
& ATH9K_HW_CAP_RAC_SUPPORTED
))
81 isr
= REG_READ(ah
, AR_ISR_RAC
);
83 if (isr
== 0xffffffff) {
88 *masked
= isr
& ATH9K_INT_COMMON
;
90 if (ah
->config
.rx_intr_mitigation
)
91 if (isr
& (AR_ISR_RXMINTR
| AR_ISR_RXINTM
))
92 *masked
|= ATH9K_INT_RXLP
;
94 if (ah
->config
.tx_intr_mitigation
)
95 if (isr
& (AR_ISR_TXMINTR
| AR_ISR_TXINTM
))
96 *masked
|= ATH9K_INT_TX
;
98 if (isr
& (AR_ISR_LP_RXOK
| AR_ISR_RXERR
))
99 *masked
|= ATH9K_INT_RXLP
;
101 if (isr
& AR_ISR_HP_RXOK
)
102 *masked
|= ATH9K_INT_RXHP
;
104 if (isr
& (AR_ISR_TXOK
| AR_ISR_TXERR
| AR_ISR_TXEOL
)) {
105 *masked
|= ATH9K_INT_TX
;
107 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_RAC_SUPPORTED
)) {
109 s0
= REG_READ(ah
, AR_ISR_S0
);
110 REG_WRITE(ah
, AR_ISR_S0
, s0
);
111 s1
= REG_READ(ah
, AR_ISR_S1
);
112 REG_WRITE(ah
, AR_ISR_S1
, s1
);
114 isr
&= ~(AR_ISR_TXOK
| AR_ISR_TXERR
|
119 if (isr
& AR_ISR_GENTMR
) {
122 if (pCap
->hw_caps
& ATH9K_HW_CAP_RAC_SUPPORTED
)
123 s5
= REG_READ(ah
, AR_ISR_S5_S
);
125 s5
= REG_READ(ah
, AR_ISR_S5
);
127 ah
->intr_gen_timer_trigger
=
128 MS(s5
, AR_ISR_S5_GENTIMER_TRIG
);
130 ah
->intr_gen_timer_thresh
=
131 MS(s5
, AR_ISR_S5_GENTIMER_THRESH
);
133 if (ah
->intr_gen_timer_trigger
)
134 *masked
|= ATH9K_INT_GENTIMER
;
136 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_RAC_SUPPORTED
)) {
137 REG_WRITE(ah
, AR_ISR_S5
, s5
);
138 isr
&= ~AR_ISR_GENTMR
;
145 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_RAC_SUPPORTED
)) {
146 REG_WRITE(ah
, AR_ISR
, isr
);
148 (void) REG_READ(ah
, AR_ISR
);
153 if (sync_cause
& AR_INTR_SYNC_RADM_CPL_TIMEOUT
) {
154 REG_WRITE(ah
, AR_RC
, AR_RC_HOSTIF
);
155 REG_WRITE(ah
, AR_RC
, 0);
156 *masked
|= ATH9K_INT_FATAL
;
159 if (sync_cause
& AR_INTR_SYNC_LOCAL_TIMEOUT
)
160 ath_print(common
, ATH_DBG_INTERRUPT
,
161 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
163 REG_WRITE(ah
, AR_INTR_SYNC_CAUSE_CLR
, sync_cause
);
164 (void) REG_READ(ah
, AR_INTR_SYNC_CAUSE_CLR
);
170 static void ar9003_hw_fill_txdesc(struct ath_hw
*ah
, void *ds
, u32 seglen
,
171 bool is_firstseg
, bool is_lastseg
,
172 const void *ds0
, dma_addr_t buf_addr
,
177 static int ar9003_hw_proc_txdesc(struct ath_hw
*ah
, void *ds
,
178 struct ath_tx_status
*ts
)
182 static void ar9003_hw_set11n_txdesc(struct ath_hw
*ah
, void *ds
,
183 u32 pktLen
, enum ath9k_pkt_type type
, u32 txPower
,
184 u32 keyIx
, enum ath9k_key_type keyType
, u32 flags
)
189 static void ar9003_hw_set11n_ratescenario(struct ath_hw
*ah
, void *ds
,
191 u32 durUpdateEn
, u32 rtsctsRate
,
193 struct ath9k_11n_rate_series series
[],
194 u32 nseries
, u32 flags
)
199 static void ar9003_hw_set11n_aggr_first(struct ath_hw
*ah
, void *ds
,
205 static void ar9003_hw_set11n_aggr_middle(struct ath_hw
*ah
, void *ds
,
211 static void ar9003_hw_set11n_aggr_last(struct ath_hw
*ah
, void *ds
)
216 static void ar9003_hw_clr11n_aggr(struct ath_hw
*ah
, void *ds
)
221 static void ar9003_hw_set11n_burstduration(struct ath_hw
*ah
, void *ds
,
227 static void ar9003_hw_set11n_virtualmorefrag(struct ath_hw
*ah
, void *ds
,
233 void ar9003_hw_attach_mac_ops(struct ath_hw
*hw
)
235 struct ath_hw_ops
*ops
= ath9k_hw_ops(hw
);
237 ops
->rx_enable
= ar9003_hw_rx_enable
;
238 ops
->set_desc_link
= ar9003_hw_set_desc_link
;
239 ops
->get_desc_link
= ar9003_hw_get_desc_link
;
240 ops
->get_isr
= ar9003_hw_get_isr
;
241 ops
->fill_txdesc
= ar9003_hw_fill_txdesc
;
242 ops
->proc_txdesc
= ar9003_hw_proc_txdesc
;
243 ops
->set11n_txdesc
= ar9003_hw_set11n_txdesc
;
244 ops
->set11n_ratescenario
= ar9003_hw_set11n_ratescenario
;
245 ops
->set11n_aggr_first
= ar9003_hw_set11n_aggr_first
;
246 ops
->set11n_aggr_middle
= ar9003_hw_set11n_aggr_middle
;
247 ops
->set11n_aggr_last
= ar9003_hw_set11n_aggr_last
;
248 ops
->clr11n_aggr
= ar9003_hw_clr11n_aggr
;
249 ops
->set11n_burstduration
= ar9003_hw_set11n_burstduration
;
250 ops
->set11n_virtualmorefrag
= ar9003_hw_set11n_virtualmorefrag
;
253 void ath9k_hw_set_rx_bufsize(struct ath_hw
*ah
, u16 buf_size
)
255 REG_WRITE(ah
, AR_DATABUF_SIZE
, buf_size
& AR_DATABUF_SIZE_MASK
);
257 EXPORT_SYMBOL(ath9k_hw_set_rx_bufsize
);
259 void ath9k_hw_addrxbuf_edma(struct ath_hw
*ah
, u32 rxdp
,
260 enum ath9k_rx_qtype qtype
)
262 if (qtype
== ATH9K_RX_QUEUE_HP
)
263 REG_WRITE(ah
, AR_HP_RXDP
, rxdp
);
265 REG_WRITE(ah
, AR_LP_RXDP
, rxdp
);
267 EXPORT_SYMBOL(ath9k_hw_addrxbuf_edma
);
269 int ath9k_hw_process_rxdesc_edma(struct ath_hw
*ah
, struct ath_rx_status
*rxs
,
272 struct ar9003_rxs
*rxsp
= (struct ar9003_rxs
*) buf_addr
;
275 /* TODO: byte swap on big endian for ar9300_10 */
277 if ((rxsp
->status11
& AR_RxDone
) == 0)
280 if (MS(rxsp
->ds_info
, AR_DescId
) != 0x168c)
283 if ((rxsp
->ds_info
& (AR_TxRxDesc
| AR_CtrlStat
)) != 0)
292 rxs
->rs_datalen
= rxsp
->status2
& AR_DataLen
;
293 rxs
->rs_tstamp
= rxsp
->status3
;
296 rxs
->rs_rssi
= MS(rxsp
->status5
, AR_RxRSSICombined
);
297 rxs
->rs_rssi_ctl0
= MS(rxsp
->status1
, AR_RxRSSIAnt00
);
298 rxs
->rs_rssi_ctl1
= MS(rxsp
->status1
, AR_RxRSSIAnt01
);
299 rxs
->rs_rssi_ctl2
= MS(rxsp
->status1
, AR_RxRSSIAnt02
);
300 rxs
->rs_rssi_ext0
= MS(rxsp
->status5
, AR_RxRSSIAnt10
);
301 rxs
->rs_rssi_ext1
= MS(rxsp
->status5
, AR_RxRSSIAnt11
);
302 rxs
->rs_rssi_ext2
= MS(rxsp
->status5
, AR_RxRSSIAnt12
);
304 if (rxsp
->status11
& AR_RxKeyIdxValid
)
305 rxs
->rs_keyix
= MS(rxsp
->status11
, AR_KeyIdx
);
307 rxs
->rs_keyix
= ATH9K_RXKEYIX_INVALID
;
309 rxs
->rs_rate
= MS(rxsp
->status1
, AR_RxRate
);
310 rxs
->rs_more
= (rxsp
->status2
& AR_RxMore
) ? 1 : 0;
312 rxs
->rs_isaggr
= (rxsp
->status11
& AR_RxAggr
) ? 1 : 0;
313 rxs
->rs_moreaggr
= (rxsp
->status11
& AR_RxMoreAggr
) ? 1 : 0;
314 rxs
->rs_antenna
= (MS(rxsp
->status4
, AR_RxAntenna
) & 0x7);
315 rxs
->rs_flags
= (rxsp
->status4
& AR_GI
) ? ATH9K_RX_GI
: 0;
316 rxs
->rs_flags
|= (rxsp
->status4
& AR_2040
) ? ATH9K_RX_2040
: 0;
318 rxs
->evm0
= rxsp
->status6
;
319 rxs
->evm1
= rxsp
->status7
;
320 rxs
->evm2
= rxsp
->status8
;
321 rxs
->evm3
= rxsp
->status9
;
322 rxs
->evm4
= (rxsp
->status10
& 0xffff);
324 if (rxsp
->status11
& AR_PreDelimCRCErr
)
325 rxs
->rs_flags
|= ATH9K_RX_DELIM_CRC_PRE
;
327 if (rxsp
->status11
& AR_PostDelimCRCErr
)
328 rxs
->rs_flags
|= ATH9K_RX_DELIM_CRC_POST
;
330 if (rxsp
->status11
& AR_DecryptBusyErr
)
331 rxs
->rs_flags
|= ATH9K_RX_DECRYPT_BUSY
;
333 if ((rxsp
->status11
& AR_RxFrameOK
) == 0) {
334 if (rxsp
->status11
& AR_CRCErr
) {
335 rxs
->rs_status
|= ATH9K_RXERR_CRC
;
336 } else if (rxsp
->status11
& AR_PHYErr
) {
337 rxs
->rs_status
|= ATH9K_RXERR_PHY
;
338 phyerr
= MS(rxsp
->status11
, AR_PHYErrCode
);
339 rxs
->rs_phyerr
= phyerr
;
340 } else if (rxsp
->status11
& AR_DecryptCRCErr
) {
341 rxs
->rs_status
|= ATH9K_RXERR_DECRYPT
;
342 } else if (rxsp
->status11
& AR_MichaelErr
) {
343 rxs
->rs_status
|= ATH9K_RXERR_MIC
;
349 EXPORT_SYMBOL(ath9k_hw_process_rxdesc_edma
);
351 void ath9k_hw_reset_txstatus_ring(struct ath_hw
*ah
)
355 memset((void *) ah
->ts_ring
, 0,
356 ah
->ts_size
* sizeof(struct ar9003_txs
));
358 ath_print(ath9k_hw_common(ah
), ATH_DBG_XMIT
,
359 "TS Start 0x%x End 0x%x Virt %p, Size %d\n",
360 ah
->ts_paddr_start
, ah
->ts_paddr_end
,
361 ah
->ts_ring
, ah
->ts_size
);
363 REG_WRITE(ah
, AR_Q_STATUS_RING_START
, ah
->ts_paddr_start
);
364 REG_WRITE(ah
, AR_Q_STATUS_RING_END
, ah
->ts_paddr_end
);
367 void ath9k_hw_setup_statusring(struct ath_hw
*ah
, void *ts_start
,
372 ah
->ts_paddr_start
= ts_paddr_start
;
373 ah
->ts_paddr_end
= ts_paddr_start
+ (size
* sizeof(struct ar9003_txs
));
375 ah
->ts_ring
= (struct ar9003_txs
*) ts_start
;
377 ath9k_hw_reset_txstatus_ring(ah
);
379 EXPORT_SYMBOL(ath9k_hw_setup_statusring
);