drivers/net/wireless/ath/ath9k/ar9003_phy.c

   1 /*
   2  * Copyright (c) 2010 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "hw.h"
  18 #include "ar9003_phy.h"
  19
  20 /**
  21  * ar9003_hw_set_channel - set channel on single-chip device
  22  * @ah: atheros hardware structure
  23  * @chan:
  24  *
  25  * This is the function to change channel on single-chip devices, that is
  26  * all devices after ar9280.
  27  *
  28  * This function takes the channel value in MHz and sets
  29  * hardware channel value. Assumes writes have been enabled to analog bus.
  30  *
  31  * Actual Expression,
  32  *
  33  * For 2GHz channel,
  34  * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
  35  * (freq_ref = 40MHz)
  36  *
  37  * For 5GHz channel,
  38  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
  39  * (freq_ref = 40MHz/(24>>amodeRefSel))
  40  *
  41  * For 5GHz channels which are 5MHz spaced,
  42  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
  43  * (freq_ref = 40MHz)
  44  */
  45 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
  46 {
  47         u16 bMode, fracMode = 0, aModeRefSel = 0;
  48         u32 freq, channelSel = 0, reg32 = 0;
  49         struct chan_centers centers;
  50         int loadSynthChannel;
  51
  52         ath9k_hw_get_channel_centers(ah, chan, &centers);
  53         freq = centers.synth_center;
  54
  55         if (freq < 4800) {     /* 2 GHz, fractional mode */
  56                 channelSel = CHANSEL_2G(freq);
  57                 /* Set to 2G mode */
  58                 bMode = 1;
  59         } else {
  60                 channelSel = CHANSEL_5G(freq);
  61                 /* Doubler is ON, so, divide channelSel by 2. */
  62                 channelSel >>= 1;
  63                 /* Set to 5G mode */
  64                 bMode = 0;
  65         }
  66
  67         /* Enable fractional mode for all channels */
  68         fracMode = 1;
  69         aModeRefSel = 0;
  70         loadSynthChannel = 0;
  71
  72         reg32 = (bMode << 29);
  73         REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
  74
  75         /* Enable Long shift Select for Synthesizer */
  76         REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
  77                       AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
  78
  79         /* Program Synth. setting */
  80         reg32 = (channelSel << 2) | (fracMode << 30) |
  81                 (aModeRefSel << 28) | (loadSynthChannel << 31);
  82         REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
  83
  84         /* Toggle Load Synth channel bit */
  85         loadSynthChannel = 1;
  86         reg32 = (channelSel << 2) | (fracMode << 30) |
  87                 (aModeRefSel << 28) | (loadSynthChannel << 31);
  88         REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
  89
  90         ah->curchan = chan;
  91         ah->curchan_rad_index = -1;
  92
  93         return 0;
  94 }
  95
  96 /**
  97  * ar9003_hw_spur_mitigate - convert baseband spur frequency
  98  * @ah: atheros hardware structure
  99  * @chan:
 100  *
 101  * For single-chip solutions. Converts to baseband spur frequency given the
 102  * input channel frequency and compute register settings below.
 103  *
 104  * Spur mitigation for MRC CCK
 105  */
 106 static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
 107                                     struct ath9k_channel *chan)
 108 {
 109         u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
 110         int cur_bb_spur, negative = 0, cck_spur_freq;
 111         int i;
 112
 113         /*
 114          * Need to verify range +/- 10 MHz in control channel, otherwise spur
 115          * is out-of-band and can be ignored.
 116          */
 117
 118         for (i = 0; i < 4; i++) {
 119                 negative = 0;
 120                 cur_bb_spur = spur_freq[i] - chan->channel;
 121
 122                 if (cur_bb_spur < 0) {
 123                         negative = 1;
 124                         cur_bb_spur = -cur_bb_spur;
 125                 }
 126                 if (cur_bb_spur < 10) {
 127                         cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
 128
 129                         if (negative == 1)
 130                                 cck_spur_freq = -cck_spur_freq;
 131
 132                         cck_spur_freq = cck_spur_freq & 0xfffff;
 133
 134                         REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
 135                                       AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
 136                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 137                                       AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
 138                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 139                                       AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
 140                                       0x2);
 141                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 142                                       AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
 143                                       0x1);
 144                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 145                                       AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
 146                                       cck_spur_freq);
 147
 148                         return;
 149                 }
 150         }
 151
 152         REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
 153                       AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
 154         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 155                       AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
 156         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 157                       AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
 158 }
 159
 160 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
 161                                          struct ath9k_channel *chan)
 162 {
 163         u32 pll;
 164
 165         pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
 166
 167         if (chan && IS_CHAN_HALF_RATE(chan))
 168                 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
 169         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 170                 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
 171
 172         if (chan && IS_CHAN_5GHZ(chan)) {
 173                 pll |= SM(0x28, AR_RTC_9300_PLL_DIV);
 174
 175                 /*
 176                  * When doing fast clock, set PLL to 0x142c
 177                  */
 178                 if (IS_CHAN_A_5MHZ_SPACED(chan))
 179                         pll = 0x142c;
 180         } else
 181                 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
 182
 183         return pll;
 184 }
 185
 186 static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
 187                                        struct ath9k_channel *chan)
 188 {
 189         u32 phymode;
 190         u32 enableDacFifo = 0;
 191
 192         enableDacFifo =
 193                 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
 194
 195         /* Enable 11n HT, 20 MHz */
 196         phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 | AR_PHY_GC_WALSH |
 197                   AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
 198
 199         /* Configure baseband for dynamic 20/40 operation */
 200         if (IS_CHAN_HT40(chan)) {
 201                 phymode |= AR_PHY_GC_DYN2040_EN;
 202                 /* Configure control (primary) channel at +-10MHz */
 203                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 204                     (chan->chanmode == CHANNEL_G_HT40PLUS))
 205                         phymode |= AR_PHY_GC_DYN2040_PRI_CH;
 206
 207         }
 208
 209         /* make sure we preserve INI settings */
 210         phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
 211         /* turn off Green Field detection for STA for now */
 212         phymode &= ~AR_PHY_GC_GF_DETECT_EN;
 213
 214         REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
 215
 216         /* Configure MAC for 20/40 operation */
 217         ath9k_hw_set11nmac2040(ah);
 218
 219         /* global transmit timeout (25 TUs default)*/
 220         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
 221         /* carrier sense timeout */
 222         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
 223 }
 224
 225 static void ar9003_hw_init_bb(struct ath_hw *ah,
 226                               struct ath9k_channel *chan)
 227 {
 228         u32 synthDelay;
 229
 230         /*
 231          * Wait for the frequency synth to settle (synth goes on
 232          * via AR_PHY_ACTIVE_EN).  Read the phy active delay register.
 233          * Value is in 100ns increments.
 234          */
 235         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 236         if (IS_CHAN_B(chan))
 237                 synthDelay = (4 * synthDelay) / 22;
 238         else
 239                 synthDelay /= 10;
 240
 241         /* Activate the PHY (includes baseband activate + synthesizer on) */
 242         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 243
 244         /*
 245          * There is an issue if the AP starts the calibration before
 246          * the base band timeout completes.  This could result in the
 247          * rx_clear false triggering.  As a workaround we add delay an
 248          * extra BASE_ACTIVATE_DELAY usecs to ensure this condition
 249          * does not happen.
 250          */
 251         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 252 }
 253
 254 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
 255 {
 256         switch (rx) {
 257         case 0x5:
 258                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
 259                             AR_PHY_SWAP_ALT_CHAIN);
 260         case 0x3:
 261         case 0x1:
 262         case 0x2:
 263         case 0x7:
 264                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
 265                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
 266                 break;
 267         default:
 268                 break;
 269         }
 270
 271         REG_WRITE(ah, AR_SELFGEN_MASK, tx);
 272         if (tx == 0x5) {
 273                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
 274                             AR_PHY_SWAP_ALT_CHAIN);
 275         }
 276 }
 277
 278 /*
 279  * Override INI values with chip specific configuration.
 280  */
 281 static void ar9003_hw_override_ini(struct ath_hw *ah)
 282 {
 283         u32 val;
 284
 285         /*
 286          * Set the RX_ABORT and RX_DIS and clear it only after
 287          * RXE is set for MAC. This prevents frames with
 288          * corrupted descriptor status.
 289          */
 290         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
 291
 292         /*
 293          * For AR9280 and above, there is a new feature that allows
 294          * Multicast search based on both MAC Address and Key ID. By default,
 295          * this feature is enabled. But since the driver is not using this
 296          * feature, we switch it off; otherwise multicast search based on
 297          * MAC addr only will fail.
 298          */
 299         val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
 300         REG_WRITE(ah, AR_PCU_MISC_MODE2,
 301                   val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE);
 302 }
 303
 304 static void ar9003_hw_prog_ini(struct ath_hw *ah,
 305                                struct ar5416IniArray *iniArr,
 306                                int column)
 307 {
 308         unsigned int i, regWrites = 0;
 309
 310         /* New INI format: Array may be undefined (pre, core, post arrays) */
 311         if (!iniArr->ia_array)
 312                 return;
 313
 314         /*
 315          * New INI format: Pre, core, and post arrays for a given subsystem
 316          * may be modal (> 2 columns) or non-modal (2 columns). Determine if
 317          * the array is non-modal and force the column to 1.
 318          */
 319         if (column >= iniArr->ia_columns)
 320                 column = 1;
 321
 322         for (i = 0; i < iniArr->ia_rows; i++) {
 323                 u32 reg = INI_RA(iniArr, i, 0);
 324                 u32 val = INI_RA(iniArr, i, column);
 325
 326                 REG_WRITE(ah, reg, val);
 327
 328                 /*
 329                  * Determine if this is a shift register value, and insert the
 330                  * configured delay if so.
 331                  */
 332                 if (reg >= 0x16000 && reg < 0x17000
 333                     && ah->config.analog_shiftreg)
 334                         udelay(100);
 335
 336                 DO_DELAY(regWrites);
 337         }
 338 }
 339
 340 static int ar9003_hw_process_ini(struct ath_hw *ah,
 341                                  struct ath9k_channel *chan)
 342 {
 343         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 344         unsigned int regWrites = 0, i;
 345         struct ieee80211_channel *channel = chan->chan;
 346         u32 modesIndex, freqIndex;
 347
 348         switch (chan->chanmode) {
 349         case CHANNEL_A:
 350         case CHANNEL_A_HT20:
 351                 modesIndex = 1;
 352                 freqIndex = 1;
 353                 break;
 354         case CHANNEL_A_HT40PLUS:
 355         case CHANNEL_A_HT40MINUS:
 356                 modesIndex = 2;
 357                 freqIndex = 1;
 358                 break;
 359         case CHANNEL_G:
 360         case CHANNEL_G_HT20:
 361         case CHANNEL_B:
 362                 modesIndex = 4;
 363                 freqIndex = 2;
 364                 break;
 365         case CHANNEL_G_HT40PLUS:
 366         case CHANNEL_G_HT40MINUS:
 367                 modesIndex = 3;
 368                 freqIndex = 2;
 369                 break;
 370
 371         default:
 372                 return -EINVAL;
 373         }
 374
 375         for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
 376                 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
 377                 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
 378                 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
 379                 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
 380         }
 381
 382         REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
 383         REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
 384
 385         /*
 386          * For 5GHz channels requiring Fast Clock, apply
 387          * different modal values.
 388          */
 389         if (IS_CHAN_A_5MHZ_SPACED(chan))
 390                 REG_WRITE_ARRAY(&ah->iniModesAdditional,
 391                                 modesIndex, regWrites);
 392
 393         ar9003_hw_override_ini(ah);
 394         ar9003_hw_set_channel_regs(ah, chan);
 395         ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
 396
 397         /* Set TX power */
 398         ah->eep_ops->set_txpower(ah, chan,
 399                                  ath9k_regd_get_ctl(regulatory, chan),
 400                                  channel->max_antenna_gain * 2,
 401                                  channel->max_power * 2,
 402                                  min((u32) MAX_RATE_POWER,
 403                                  (u32) regulatory->power_limit));
 404
 405         return 0;
 406 }
 407
 408 static void ar9003_hw_set_rfmode(struct ath_hw *ah,
 409                                  struct ath9k_channel *chan)
 410 {
 411         u32 rfMode = 0;
 412
 413         if (chan == NULL)
 414                 return;
 415
 416         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
 417                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
 418
 419         if (IS_CHAN_A_5MHZ_SPACED(chan))
 420                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
 421
 422         REG_WRITE(ah, AR_PHY_MODE, rfMode);
 423 }
 424
 425 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
 426 {
 427         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
 428 }
 429
 430 static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
 431                                       struct ath9k_channel *chan)
 432 {
 433         u32 coef_scaled, ds_coef_exp, ds_coef_man;
 434         u32 clockMhzScaled = 0x64000000;
 435         struct chan_centers centers;
 436
 437         /*
 438          * half and quarter rate can divide the scaled clock by 2 or 4
 439          * scale for selected channel bandwidth
 440          */
 441         if (IS_CHAN_HALF_RATE(chan))
 442                 clockMhzScaled = clockMhzScaled >> 1;
 443         else if (IS_CHAN_QUARTER_RATE(chan))
 444                 clockMhzScaled = clockMhzScaled >> 2;
 445
 446         /*
 447          * ALGO -> coef = 1e8/fcarrier*fclock/40;
 448          * scaled coef to provide precision for this floating calculation
 449          */
 450         ath9k_hw_get_channel_centers(ah, chan, &centers);
 451         coef_scaled = clockMhzScaled / centers.synth_center;
 452
 453         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
 454                                       &ds_coef_exp);
 455
 456         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
 457                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
 458         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
 459                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
 460
 461         /*
 462          * For Short GI,
 463          * scaled coeff is 9/10 that of normal coeff
 464          */
 465         coef_scaled = (9 * coef_scaled) / 10;
 466
 467         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
 468                                       &ds_coef_exp);
 469
 470         /* for short gi */
 471         REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
 472                       AR_PHY_SGI_DSC_MAN, ds_coef_man);
 473         REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
 474                       AR_PHY_SGI_DSC_EXP, ds_coef_exp);
 475 }
 476
 477 static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
 478 {
 479         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
 480         return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
 481                              AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
 482 }
 483
 484 /*
 485  * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
 486  * Read the phy active delay register. Value is in 100ns increments.
 487  */
 488 static void ar9003_hw_rfbus_done(struct ath_hw *ah)
 489 {
 490         u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 491         if (IS_CHAN_B(ah->curchan))
 492                 synthDelay = (4 * synthDelay) / 22;
 493         else
 494                 synthDelay /= 10;
 495
 496         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 497
 498         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
 499 }
 500
 501 /*
 502  * Set the interrupt and GPIO values so the ISR can disable RF
 503  * on a switch signal.  Assumes GPIO port and interrupt polarity
 504  * are set prior to call.
 505  */
 506 static void ar9003_hw_enable_rfkill(struct ath_hw *ah)
 507 {
 508         /* Connect rfsilent_bb_l to baseband */
 509         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
 510                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
 511         /* Set input mux for rfsilent_bb_l to GPIO #0 */
 512         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
 513                     AR_GPIO_INPUT_MUX2_RFSILENT);
 514
 515         /*
 516          * Configure the desired GPIO port for input and
 517          * enable baseband rf silence.
 518          */
 519         ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
 520         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
 521 }
 522
 523 static void ar9003_hw_set_diversity(struct ath_hw *ah, bool value)
 524 {
 525         u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
 526         if (value)
 527                 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
 528         else
 529                 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
 530         REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
 531 }
 532
 533 static bool ar9003_hw_ani_control(struct ath_hw *ah,
 534                                   enum ath9k_ani_cmd cmd, int param)
 535 {
 536         struct ar5416AniState *aniState = ah->curani;
 537         struct ath_common *common = ath9k_hw_common(ah);
 538
 539         switch (cmd & ah->ani_function) {
 540         case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
 541                 u32 level = param;
 542
 543                 if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
 544                         ath_print(common, ATH_DBG_ANI,
 545                                   "level out of range (%u > %u)\n",
 546                                   level,
 547                                   (unsigned)ARRAY_SIZE(ah->totalSizeDesired));
 548                         return false;
 549                 }
 550
 551                 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
 552                               AR_PHY_DESIRED_SZ_TOT_DES,
 553                               ah->totalSizeDesired[level]);
 554                 REG_RMW_FIELD(ah, AR_PHY_AGC,
 555                               AR_PHY_AGC_COARSE_LOW,
 556                               ah->coarse_low[level]);
 557                 REG_RMW_FIELD(ah, AR_PHY_AGC,
 558                               AR_PHY_AGC_COARSE_HIGH,
 559                               ah->coarse_high[level]);
 560                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
 561                               AR_PHY_FIND_SIG_FIRPWR, ah->firpwr[level]);
 562
 563                 if (level > aniState->noiseImmunityLevel)
 564                         ah->stats.ast_ani_niup++;
 565                 else if (level < aniState->noiseImmunityLevel)
 566                         ah->stats.ast_ani_nidown++;
 567                 aniState->noiseImmunityLevel = level;
 568                 break;
 569         }
 570         case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
 571                 const int m1ThreshLow[] = { 127, 50 };
 572                 const int m2ThreshLow[] = { 127, 40 };
 573                 const int m1Thresh[] = { 127, 0x4d };
 574                 const int m2Thresh[] = { 127, 0x40 };
 575                 const int m2CountThr[] = { 31, 16 };
 576                 const int m2CountThrLow[] = { 63, 48 };
 577                 u32 on = param ? 1 : 0;
 578
 579                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
 580                               AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
 581                               m1ThreshLow[on]);
 582                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
 583                               AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
 584                               m2ThreshLow[on]);
 585                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
 586                               AR_PHY_SFCORR_M1_THRESH, m1Thresh[on]);
 587                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
 588                               AR_PHY_SFCORR_M2_THRESH, m2Thresh[on]);
 589                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
 590                               AR_PHY_SFCORR_M2COUNT_THR, m2CountThr[on]);
 591                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
 592                               AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
 593                               m2CountThrLow[on]);
 594
 595                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 596                               AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLow[on]);
 597                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 598                               AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLow[on]);
 599                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 600                               AR_PHY_SFCORR_EXT_M1_THRESH, m1Thresh[on]);
 601                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 602                               AR_PHY_SFCORR_EXT_M2_THRESH, m2Thresh[on]);
 603
 604                 if (on)
 605                         REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
 606                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
 607                 else
 608                         REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
 609                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
 610
 611                 if (!on != aniState->ofdmWeakSigDetectOff) {
 612                         if (on)
 613                                 ah->stats.ast_ani_ofdmon++;
 614                         else
 615                                 ah->stats.ast_ani_ofdmoff++;
 616                         aniState->ofdmWeakSigDetectOff = !on;
 617                 }
 618                 break;
 619         }
 620         case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
 621                 const int weakSigThrCck[] = { 8, 6 };
 622                 u32 high = param ? 1 : 0;
 623
 624                 REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
 625                               AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
 626                               weakSigThrCck[high]);
 627                 if (high != aniState->cckWeakSigThreshold) {
 628                         if (high)
 629                                 ah->stats.ast_ani_cckhigh++;
 630                         else
 631                                 ah->stats.ast_ani_ccklow++;
 632                         aniState->cckWeakSigThreshold = high;
 633                 }
 634                 break;
 635         }
 636         case ATH9K_ANI_FIRSTEP_LEVEL:{
 637                 const int firstep[] = { 0, 4, 8 };
 638                 u32 level = param;
 639
 640                 if (level >= ARRAY_SIZE(firstep)) {
 641                         ath_print(common, ATH_DBG_ANI,
 642                                   "level out of range (%u > %u)\n",
 643                                   level,
 644                                   (unsigned) ARRAY_SIZE(firstep));
 645                         return false;
 646                 }
 647                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
 648                               AR_PHY_FIND_SIG_FIRSTEP,
 649                               firstep[level]);
 650                 if (level > aniState->firstepLevel)
 651                         ah->stats.ast_ani_stepup++;
 652                 else if (level < aniState->firstepLevel)
 653                         ah->stats.ast_ani_stepdown++;
 654                 aniState->firstepLevel = level;
 655                 break;
 656         }
 657         case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
 658                 const int cycpwrThr1[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
 659                 u32 level = param;
 660
 661                 if (level >= ARRAY_SIZE(cycpwrThr1)) {
 662                         ath_print(common, ATH_DBG_ANI,
 663                                   "level out of range (%u > %u)\n",
 664                                   level,
 665                                   (unsigned) ARRAY_SIZE(cycpwrThr1));
 666                         return false;
 667                 }
 668                 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
 669                               AR_PHY_TIMING5_CYCPWR_THR1,
 670                               cycpwrThr1[level]);
 671                 if (level > aniState->spurImmunityLevel)
 672                         ah->stats.ast_ani_spurup++;
 673                 else if (level < aniState->spurImmunityLevel)
 674                         ah->stats.ast_ani_spurdown++;
 675                 aniState->spurImmunityLevel = level;
 676                 break;
 677         }
 678         case ATH9K_ANI_PRESENT:
 679                 break;
 680         default:
 681                 ath_print(common, ATH_DBG_ANI,
 682                           "invalid cmd %u\n", cmd);
 683                 return false;
 684         }
 685
 686         ath_print(common, ATH_DBG_ANI, "ANI parameters:\n");
 687         ath_print(common, ATH_DBG_ANI,
 688                   "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
 689                   "ofdmWeakSigDetectOff=%d\n",
 690                   aniState->noiseImmunityLevel,
 691                   aniState->spurImmunityLevel,
 692                   !aniState->ofdmWeakSigDetectOff);
 693         ath_print(common, ATH_DBG_ANI,
 694                   "cckWeakSigThreshold=%d, "
 695                   "firstepLevel=%d, listenTime=%d\n",
 696                   aniState->cckWeakSigThreshold,
 697                   aniState->firstepLevel,
 698                   aniState->listenTime);
 699         ath_print(common, ATH_DBG_ANI,
 700                 "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
 701                 aniState->cycleCount,
 702                 aniState->ofdmPhyErrCount,
 703                 aniState->cckPhyErrCount);
 704
 705         return true;
 706 }
 707
 708 static void ar9003_hw_nf_sanitize_2g(struct ath_hw *ah, s16 *nf)
 709 {
 710         struct ath_common *common = ath9k_hw_common(ah);
 711
 712         if (*nf > ah->nf_2g_max) {
 713                 ath_print(common, ATH_DBG_CALIBRATE,
 714                           "2 GHz NF (%d) > MAX (%d), "
 715                           "correcting to MAX",
 716                           *nf, ah->nf_2g_max);
 717                 *nf = ah->nf_2g_max;
 718         } else if (*nf < ah->nf_2g_min) {
 719                 ath_print(common, ATH_DBG_CALIBRATE,
 720                           "2 GHz NF (%d) < MIN (%d), "
 721                           "correcting to MIN",
 722                           *nf, ah->nf_2g_min);
 723                 *nf = ah->nf_2g_min;
 724         }
 725 }
 726
 727 static void ar9003_hw_nf_sanitize_5g(struct ath_hw *ah, s16 *nf)
 728 {
 729         struct ath_common *common = ath9k_hw_common(ah);
 730
 731         if (*nf > ah->nf_5g_max) {
 732                 ath_print(common, ATH_DBG_CALIBRATE,
 733                           "5 GHz NF (%d) > MAX (%d), "
 734                           "correcting to MAX",
 735                           *nf, ah->nf_5g_max);
 736                 *nf = ah->nf_5g_max;
 737         } else if (*nf < ah->nf_5g_min) {
 738                 ath_print(common, ATH_DBG_CALIBRATE,
 739                           "5 GHz NF (%d) < MIN (%d), "
 740                           "correcting to MIN",
 741                           *nf, ah->nf_5g_min);
 742                 *nf = ah->nf_5g_min;
 743         }
 744 }
 745
 746 static void ar9003_hw_nf_sanitize(struct ath_hw *ah, s16 *nf)
 747 {
 748         if (IS_CHAN_2GHZ(ah->curchan))
 749                 ar9003_hw_nf_sanitize_2g(ah, nf);
 750         else
 751                 ar9003_hw_nf_sanitize_5g(ah, nf);
 752 }
 753
 754 static void ar9003_hw_do_getnf(struct ath_hw *ah,
 755                               int16_t nfarray[NUM_NF_READINGS])
 756 {
 757         struct ath_common *common = ath9k_hw_common(ah);
 758         int16_t nf;
 759
 760         nf = MS(REG_READ(ah, AR_PHY_CCA_0), AR_PHY_MINCCA_PWR);
 761         if (nf & 0x100)
 762                 nf = 0 - ((nf ^ 0x1ff) + 1);
 763         ar9003_hw_nf_sanitize(ah, &nf);
 764         ath_print(common, ATH_DBG_CALIBRATE,
 765                   "NF calibrated [ctl] [chain 0] is %d\n", nf);
 766         nfarray[0] = nf;
 767
 768         nf = MS(REG_READ(ah, AR_PHY_CCA_1), AR_PHY_CH1_MINCCA_PWR);
 769         if (nf & 0x100)
 770                 nf = 0 - ((nf ^ 0x1ff) + 1);
 771         ar9003_hw_nf_sanitize(ah, &nf);
 772         ath_print(common, ATH_DBG_CALIBRATE,
 773                   "NF calibrated [ctl] [chain 1] is %d\n", nf);
 774         nfarray[1] = nf;
 775
 776         nf = MS(REG_READ(ah, AR_PHY_CCA_2), AR_PHY_CH2_MINCCA_PWR);
 777         if (nf & 0x100)
 778                 nf = 0 - ((nf ^ 0x1ff) + 1);
 779         ar9003_hw_nf_sanitize(ah, &nf);
 780         ath_print(common, ATH_DBG_CALIBRATE,
 781                   "NF calibrated [ctl] [chain 2] is %d\n", nf);
 782         nfarray[2] = nf;
 783
 784         nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
 785         if (nf & 0x100)
 786                 nf = 0 - ((nf ^ 0x1ff) + 1);
 787         ar9003_hw_nf_sanitize(ah, &nf);
 788         ath_print(common, ATH_DBG_CALIBRATE,
 789                   "NF calibrated [ext] [chain 0] is %d\n", nf);
 790         nfarray[3] = nf;
 791
 792         nf = MS(REG_READ(ah, AR_PHY_EXT_CCA_1), AR_PHY_CH1_EXT_MINCCA_PWR);
 793         if (nf & 0x100)
 794                 nf = 0 - ((nf ^ 0x1ff) + 1);
 795         ar9003_hw_nf_sanitize(ah, &nf);
 796         ath_print(common, ATH_DBG_CALIBRATE,
 797                   "NF calibrated [ext] [chain 1] is %d\n", nf);
 798         nfarray[4] = nf;
 799
 800         nf = MS(REG_READ(ah, AR_PHY_EXT_CCA_2), AR_PHY_CH2_EXT_MINCCA_PWR);
 801         if (nf & 0x100)
 802                 nf = 0 - ((nf ^ 0x1ff) + 1);
 803         ar9003_hw_nf_sanitize(ah, &nf);
 804         ath_print(common, ATH_DBG_CALIBRATE,
 805                   "NF calibrated [ext] [chain 2] is %d\n", nf);
 806         nfarray[5] = nf;
 807 }
 808
 809 void ar9003_hw_set_nf_limits(struct ath_hw *ah)
 810 {
 811         ah->nf_2g_max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
 812         ah->nf_2g_min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
 813         ah->nf_5g_max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
 814         ah->nf_5g_min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
 815 }
 816
 817 void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
 818 {
 819         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
 820
 821         priv_ops->rf_set_freq = ar9003_hw_set_channel;
 822         priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
 823         priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
 824         priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
 825         priv_ops->init_bb = ar9003_hw_init_bb;
 826         priv_ops->process_ini = ar9003_hw_process_ini;
 827         priv_ops->set_rfmode = ar9003_hw_set_rfmode;
 828         priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
 829         priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
 830         priv_ops->rfbus_req = ar9003_hw_rfbus_req;
 831         priv_ops->rfbus_done = ar9003_hw_rfbus_done;
 832         priv_ops->enable_rfkill = ar9003_hw_enable_rfkill;
 833         priv_ops->set_diversity = ar9003_hw_set_diversity;
 834         priv_ops->ani_control = ar9003_hw_ani_control;
 835         priv_ops->do_getnf = ar9003_hw_do_getnf;
 836 }