Merge tag 'v3.8-rc4' into irq/core
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / calib.c
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "hw.h"
18 #include "hw-ops.h"
19 #include <linux/export.h>
20
21 /* Common calibration code */
22
23
24 static int16_t ath9k_hw_get_nf_hist_mid(int16_t *nfCalBuffer)
25 {
26 int16_t nfval;
27 int16_t sort[ATH9K_NF_CAL_HIST_MAX];
28 int i, j;
29
30 for (i = 0; i < ATH9K_NF_CAL_HIST_MAX; i++)
31 sort[i] = nfCalBuffer[i];
32
33 for (i = 0; i < ATH9K_NF_CAL_HIST_MAX - 1; i++) {
34 for (j = 1; j < ATH9K_NF_CAL_HIST_MAX - i; j++) {
35 if (sort[j] > sort[j - 1]) {
36 nfval = sort[j];
37 sort[j] = sort[j - 1];
38 sort[j - 1] = nfval;
39 }
40 }
41 }
42 nfval = sort[(ATH9K_NF_CAL_HIST_MAX - 1) >> 1];
43
44 return nfval;
45 }
46
47 static struct ath_nf_limits *ath9k_hw_get_nf_limits(struct ath_hw *ah,
48 struct ath9k_channel *chan)
49 {
50 struct ath_nf_limits *limit;
51
52 if (!chan || IS_CHAN_2GHZ(chan))
53 limit = &ah->nf_2g;
54 else
55 limit = &ah->nf_5g;
56
57 return limit;
58 }
59
60 static s16 ath9k_hw_get_default_nf(struct ath_hw *ah,
61 struct ath9k_channel *chan)
62 {
63 return ath9k_hw_get_nf_limits(ah, chan)->nominal;
64 }
65
66 s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan)
67 {
68 s8 noise = ATH_DEFAULT_NOISE_FLOOR;
69
70 if (chan && chan->noisefloor) {
71 s8 delta = chan->noisefloor -
72 ATH9K_NF_CAL_NOISE_THRESH -
73 ath9k_hw_get_default_nf(ah, chan);
74 if (delta > 0)
75 noise += delta;
76 }
77 return noise;
78 }
79 EXPORT_SYMBOL(ath9k_hw_getchan_noise);
80
81 static void ath9k_hw_update_nfcal_hist_buffer(struct ath_hw *ah,
82 struct ath9k_hw_cal_data *cal,
83 int16_t *nfarray)
84 {
85 struct ath_common *common = ath9k_hw_common(ah);
86 struct ath_nf_limits *limit;
87 struct ath9k_nfcal_hist *h;
88 bool high_nf_mid = false;
89 u8 chainmask = (ah->rxchainmask << 3) | ah->rxchainmask;
90 int i;
91
92 h = cal->nfCalHist;
93 limit = ath9k_hw_get_nf_limits(ah, ah->curchan);
94
95 for (i = 0; i < NUM_NF_READINGS; i++) {
96 if (!(chainmask & (1 << i)) ||
97 ((i >= AR5416_MAX_CHAINS) && !IS_CHAN_HT40(ah->curchan)))
98 continue;
99
100 h[i].nfCalBuffer[h[i].currIndex] = nfarray[i];
101
102 if (++h[i].currIndex >= ATH9K_NF_CAL_HIST_MAX)
103 h[i].currIndex = 0;
104
105 if (h[i].invalidNFcount > 0) {
106 h[i].invalidNFcount--;
107 h[i].privNF = nfarray[i];
108 } else {
109 h[i].privNF =
110 ath9k_hw_get_nf_hist_mid(h[i].nfCalBuffer);
111 }
112
113 if (!h[i].privNF)
114 continue;
115
116 if (h[i].privNF > limit->max) {
117 high_nf_mid = true;
118
119 ath_dbg(common, CALIBRATE,
120 "NFmid[%d] (%d) > MAX (%d), %s\n",
121 i, h[i].privNF, limit->max,
122 (cal->nfcal_interference ?
123 "not corrected (due to interference)" :
124 "correcting to MAX"));
125
126 /*
127 * Normally we limit the average noise floor by the
128 * hardware specific maximum here. However if we have
129 * encountered stuck beacons because of interference,
130 * we bypass this limit here in order to better deal
131 * with our environment.
132 */
133 if (!cal->nfcal_interference)
134 h[i].privNF = limit->max;
135 }
136 }
137
138 /*
139 * If the noise floor seems normal for all chains, assume that
140 * there is no significant interference in the environment anymore.
141 * Re-enable the enforcement of the NF maximum again.
142 */
143 if (!high_nf_mid)
144 cal->nfcal_interference = false;
145 }
146
147 static bool ath9k_hw_get_nf_thresh(struct ath_hw *ah,
148 enum ieee80211_band band,
149 int16_t *nft)
150 {
151 switch (band) {
152 case IEEE80211_BAND_5GHZ:
153 *nft = (int8_t)ah->eep_ops->get_eeprom(ah, EEP_NFTHRESH_5);
154 break;
155 case IEEE80211_BAND_2GHZ:
156 *nft = (int8_t)ah->eep_ops->get_eeprom(ah, EEP_NFTHRESH_2);
157 break;
158 default:
159 BUG_ON(1);
160 return false;
161 }
162
163 return true;
164 }
165
166 void ath9k_hw_reset_calibration(struct ath_hw *ah,
167 struct ath9k_cal_list *currCal)
168 {
169 int i;
170
171 ath9k_hw_setup_calibration(ah, currCal);
172
173 currCal->calState = CAL_RUNNING;
174
175 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
176 ah->meas0.sign[i] = 0;
177 ah->meas1.sign[i] = 0;
178 ah->meas2.sign[i] = 0;
179 ah->meas3.sign[i] = 0;
180 }
181
182 ah->cal_samples = 0;
183 }
184
185 /* This is done for the currently configured channel */
186 bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
187 {
188 struct ath_common *common = ath9k_hw_common(ah);
189 struct ieee80211_conf *conf = &common->hw->conf;
190 struct ath9k_cal_list *currCal = ah->cal_list_curr;
191
192 if (!ah->caldata)
193 return true;
194
195 if (!AR_SREV_9100(ah) && !AR_SREV_9160_10_OR_LATER(ah))
196 return true;
197
198 if (currCal == NULL)
199 return true;
200
201 if (currCal->calState != CAL_DONE) {
202 ath_dbg(common, CALIBRATE, "Calibration state incorrect, %d\n",
203 currCal->calState);
204 return true;
205 }
206
207 if (!(ah->supp_cals & currCal->calData->calType))
208 return true;
209
210 ath_dbg(common, CALIBRATE, "Resetting Cal %d state for channel %u\n",
211 currCal->calData->calType, conf->channel->center_freq);
212
213 ah->caldata->CalValid &= ~currCal->calData->calType;
214 currCal->calState = CAL_WAITING;
215
216 return false;
217 }
218 EXPORT_SYMBOL(ath9k_hw_reset_calvalid);
219
220 void ath9k_hw_start_nfcal(struct ath_hw *ah, bool update)
221 {
222 if (ah->caldata)
223 ah->caldata->nfcal_pending = true;
224
225 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
226 AR_PHY_AGC_CONTROL_ENABLE_NF);
227
228 if (update)
229 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
230 AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
231 else
232 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
233 AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
234
235 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
236 }
237
238 void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
239 {
240 struct ath9k_nfcal_hist *h = NULL;
241 unsigned i, j;
242 int32_t val;
243 u8 chainmask = (ah->rxchainmask << 3) | ah->rxchainmask;
244 struct ath_common *common = ath9k_hw_common(ah);
245 struct ieee80211_conf *conf = &common->hw->conf;
246 s16 default_nf = ath9k_hw_get_default_nf(ah, chan);
247
248 if (ah->caldata)
249 h = ah->caldata->nfCalHist;
250
251 for (i = 0; i < NUM_NF_READINGS; i++) {
252 if (chainmask & (1 << i)) {
253 s16 nfval;
254
255 if ((i >= AR5416_MAX_CHAINS) && !conf_is_ht40(conf))
256 continue;
257
258 if (h)
259 nfval = h[i].privNF;
260 else
261 nfval = default_nf;
262
263 val = REG_READ(ah, ah->nf_regs[i]);
264 val &= 0xFFFFFE00;
265 val |= (((u32) nfval << 1) & 0x1ff);
266 REG_WRITE(ah, ah->nf_regs[i], val);
267 }
268 }
269
270 /*
271 * Load software filtered NF value into baseband internal minCCApwr
272 * variable.
273 */
274 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
275 AR_PHY_AGC_CONTROL_ENABLE_NF);
276 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
277 AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
278 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
279
280 /*
281 * Wait for load to complete, should be fast, a few 10s of us.
282 * The max delay was changed from an original 250us to 10000us
283 * since 250us often results in NF load timeout and causes deaf
284 * condition during stress testing 12/12/2009
285 */
286 for (j = 0; j < 10000; j++) {
287 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
288 AR_PHY_AGC_CONTROL_NF) == 0)
289 break;
290 udelay(10);
291 }
292
293 /*
294 * We timed out waiting for the noisefloor to load, probably due to an
295 * in-progress rx. Simply return here and allow the load plenty of time
296 * to complete before the next calibration interval. We need to avoid
297 * trying to load -50 (which happens below) while the previous load is
298 * still in progress as this can cause rx deafness. Instead by returning
299 * here, the baseband nf cal will just be capped by our present
300 * noisefloor until the next calibration timer.
301 */
302 if (j == 10000) {
303 ath_dbg(common, ANY,
304 "Timeout while waiting for nf to load: AR_PHY_AGC_CONTROL=0x%x\n",
305 REG_READ(ah, AR_PHY_AGC_CONTROL));
306 return;
307 }
308
309 /*
310 * Restore maxCCAPower register parameter again so that we're not capped
311 * by the median we just loaded. This will be initial (and max) value
312 * of next noise floor calibration the baseband does.
313 */
314 ENABLE_REGWRITE_BUFFER(ah);
315 for (i = 0; i < NUM_NF_READINGS; i++) {
316 if (chainmask & (1 << i)) {
317 if ((i >= AR5416_MAX_CHAINS) && !conf_is_ht40(conf))
318 continue;
319
320 val = REG_READ(ah, ah->nf_regs[i]);
321 val &= 0xFFFFFE00;
322 val |= (((u32) (-50) << 1) & 0x1ff);
323 REG_WRITE(ah, ah->nf_regs[i], val);
324 }
325 }
326 REGWRITE_BUFFER_FLUSH(ah);
327 }
328
329
330 static void ath9k_hw_nf_sanitize(struct ath_hw *ah, s16 *nf)
331 {
332 struct ath_common *common = ath9k_hw_common(ah);
333 struct ath_nf_limits *limit;
334 int i;
335
336 if (IS_CHAN_2GHZ(ah->curchan))
337 limit = &ah->nf_2g;
338 else
339 limit = &ah->nf_5g;
340
341 for (i = 0; i < NUM_NF_READINGS; i++) {
342 if (!nf[i])
343 continue;
344
345 ath_dbg(common, CALIBRATE,
346 "NF calibrated [%s] [chain %d] is %d\n",
347 (i >= 3 ? "ext" : "ctl"), i % 3, nf[i]);
348
349 if (nf[i] > limit->max) {
350 ath_dbg(common, CALIBRATE,
351 "NF[%d] (%d) > MAX (%d), correcting to MAX\n",
352 i, nf[i], limit->max);
353 nf[i] = limit->max;
354 } else if (nf[i] < limit->min) {
355 ath_dbg(common, CALIBRATE,
356 "NF[%d] (%d) < MIN (%d), correcting to NOM\n",
357 i, nf[i], limit->min);
358 nf[i] = limit->nominal;
359 }
360 }
361 }
362
363 bool ath9k_hw_getnf(struct ath_hw *ah, struct ath9k_channel *chan)
364 {
365 struct ath_common *common = ath9k_hw_common(ah);
366 int16_t nf, nfThresh;
367 int16_t nfarray[NUM_NF_READINGS] = { 0 };
368 struct ath9k_nfcal_hist *h;
369 struct ieee80211_channel *c = chan->chan;
370 struct ath9k_hw_cal_data *caldata = ah->caldata;
371
372 chan->channelFlags &= (~CHANNEL_CW_INT);
373 if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
374 ath_dbg(common, CALIBRATE,
375 "NF did not complete in calibration window\n");
376 return false;
377 }
378
379 ath9k_hw_do_getnf(ah, nfarray);
380 ath9k_hw_nf_sanitize(ah, nfarray);
381 nf = nfarray[0];
382 if (ath9k_hw_get_nf_thresh(ah, c->band, &nfThresh)
383 && nf > nfThresh) {
384 ath_dbg(common, CALIBRATE,
385 "noise floor failed detected; detected %d, threshold %d\n",
386 nf, nfThresh);
387 chan->channelFlags |= CHANNEL_CW_INT;
388 }
389
390 if (!caldata) {
391 chan->noisefloor = nf;
392 ah->noise = ath9k_hw_getchan_noise(ah, chan);
393 return false;
394 }
395
396 h = caldata->nfCalHist;
397 caldata->nfcal_pending = false;
398 ath9k_hw_update_nfcal_hist_buffer(ah, caldata, nfarray);
399 chan->noisefloor = h[0].privNF;
400 ah->noise = ath9k_hw_getchan_noise(ah, chan);
401 return true;
402 }
403 EXPORT_SYMBOL(ath9k_hw_getnf);
404
405 void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah,
406 struct ath9k_channel *chan)
407 {
408 struct ath9k_nfcal_hist *h;
409 s16 default_nf;
410 int i, j;
411
412 ah->caldata->channel = chan->channel;
413 ah->caldata->channelFlags = chan->channelFlags & ~CHANNEL_CW_INT;
414 ah->caldata->chanmode = chan->chanmode;
415 h = ah->caldata->nfCalHist;
416 default_nf = ath9k_hw_get_default_nf(ah, chan);
417 for (i = 0; i < NUM_NF_READINGS; i++) {
418 h[i].currIndex = 0;
419 h[i].privNF = default_nf;
420 h[i].invalidNFcount = AR_PHY_CCA_FILTERWINDOW_LENGTH;
421 for (j = 0; j < ATH9K_NF_CAL_HIST_MAX; j++) {
422 h[i].nfCalBuffer[j] = default_nf;
423 }
424 }
425 }
426
427
428 void ath9k_hw_bstuck_nfcal(struct ath_hw *ah)
429 {
430 struct ath9k_hw_cal_data *caldata = ah->caldata;
431
432 if (unlikely(!caldata))
433 return;
434
435 /*
436 * If beacons are stuck, the most likely cause is interference.
437 * Triggering a noise floor calibration at this point helps the
438 * hardware adapt to a noisy environment much faster.
439 * To ensure that we recover from stuck beacons quickly, let
440 * the baseband update the internal NF value itself, similar to
441 * what is being done after a full reset.
442 */
443 if (!caldata->nfcal_pending)
444 ath9k_hw_start_nfcal(ah, true);
445 else if (!(REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF))
446 ath9k_hw_getnf(ah, ah->curchan);
447
448 caldata->nfcal_interference = true;
449 }
450 EXPORT_SYMBOL(ath9k_hw_bstuck_nfcal);
451
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