2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 static void ath9k_get_txgain_index(struct ath_hw
*ah
,
20 struct ath9k_channel
*chan
,
21 struct calDataPerFreqOpLoop
*rawDatasetOpLoop
,
22 u8
*calChans
, u16 availPiers
, u8
*pwr
, u8
*pcdacIdx
)
25 u16 idxL
= 0, idxR
= 0, numPiers
;
27 struct chan_centers centers
;
29 ath9k_hw_get_channel_centers(ah
, chan
, ¢ers
);
31 for (numPiers
= 0; numPiers
< availPiers
; numPiers
++)
32 if (calChans
[numPiers
] == AR5416_BCHAN_UNUSED
)
35 match
= ath9k_hw_get_lower_upper_index(
36 (u8
)FREQ2FBIN(centers
.synth_center
, IS_CHAN_2GHZ(chan
)),
37 calChans
, numPiers
, &idxL
, &idxR
);
39 pcdac
= rawDatasetOpLoop
[idxL
].pcdac
[0][0];
40 *pwr
= rawDatasetOpLoop
[idxL
].pwrPdg
[0][0];
42 pcdac
= rawDatasetOpLoop
[idxR
].pcdac
[0][0];
43 *pwr
= (rawDatasetOpLoop
[idxL
].pwrPdg
[0][0] +
44 rawDatasetOpLoop
[idxR
].pwrPdg
[0][0])/2;
47 while (pcdac
> ah
->originalGain
[i
] &&
48 i
< (AR9280_TX_GAIN_TABLE_SIZE
- 1))
55 static void ath9k_olc_get_pdadcs(struct ath_hw
*ah
,
63 REG_RMW_FIELD(ah
, AR_PHY_TX_PWRCTRL6_0
,
64 AR_PHY_TX_PWRCTRL_ERR_EST_MODE
, 3);
65 REG_RMW_FIELD(ah
, AR_PHY_TX_PWRCTRL6_1
,
66 AR_PHY_TX_PWRCTRL_ERR_EST_MODE
, 3);
68 REG_RMW_FIELD(ah
, AR_PHY_TX_PWRCTRL7
,
69 AR_PHY_TX_PWRCTRL_INIT_TX_GAIN
, initTxGain
);
72 for (i
= 0; i
< AR5416_NUM_PDADC_VALUES
; i
++)
74 pPDADCValues
[i
] = 0x0;
76 pPDADCValues
[i
] = 0xFF;
79 static int ath9k_hw_def_get_eeprom_ver(struct ath_hw
*ah
)
81 return ((ah
->eeprom
.def
.baseEepHeader
.version
>> 12) & 0xF);
84 static int ath9k_hw_def_get_eeprom_rev(struct ath_hw
*ah
)
86 return ((ah
->eeprom
.def
.baseEepHeader
.version
) & 0xFFF);
89 static bool ath9k_hw_def_fill_eeprom(struct ath_hw
*ah
)
91 #define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16))
92 struct ath_common
*common
= ath9k_hw_common(ah
);
93 u16
*eep_data
= (u16
*)&ah
->eeprom
.def
;
94 int addr
, ar5416_eep_start_loc
= 0x100;
96 for (addr
= 0; addr
< SIZE_EEPROM_DEF
; addr
++) {
97 if (!ath9k_hw_nvram_read(common
, addr
+ ar5416_eep_start_loc
,
99 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
100 "Unable to read eeprom region\n");
106 #undef SIZE_EEPROM_DEF
109 static int ath9k_hw_def_check_eeprom(struct ath_hw
*ah
)
111 struct ar5416_eeprom_def
*eep
=
112 (struct ar5416_eeprom_def
*) &ah
->eeprom
.def
;
113 struct ath_common
*common
= ath9k_hw_common(ah
);
114 u16
*eepdata
, temp
, magic
, magic2
;
116 bool need_swap
= false;
119 if (!ath9k_hw_nvram_read(common
, AR5416_EEPROM_MAGIC_OFFSET
, &magic
)) {
120 ath_print(common
, ATH_DBG_FATAL
, "Reading Magic # failed\n");
124 if (!ath9k_hw_use_flash(ah
)) {
125 ath_print(common
, ATH_DBG_EEPROM
,
126 "Read Magic = 0x%04X\n", magic
);
128 if (magic
!= AR5416_EEPROM_MAGIC
) {
129 magic2
= swab16(magic
);
131 if (magic2
== AR5416_EEPROM_MAGIC
) {
132 size
= sizeof(struct ar5416_eeprom_def
);
134 eepdata
= (u16
*) (&ah
->eeprom
);
136 for (addr
= 0; addr
< size
/ sizeof(u16
); addr
++) {
137 temp
= swab16(*eepdata
);
142 ath_print(common
, ATH_DBG_FATAL
,
143 "Invalid EEPROM Magic. "
144 "Endianness mismatch.\n");
150 ath_print(common
, ATH_DBG_EEPROM
, "need_swap = %s.\n",
151 need_swap
? "True" : "False");
154 el
= swab16(ah
->eeprom
.def
.baseEepHeader
.length
);
156 el
= ah
->eeprom
.def
.baseEepHeader
.length
;
158 if (el
> sizeof(struct ar5416_eeprom_def
))
159 el
= sizeof(struct ar5416_eeprom_def
) / sizeof(u16
);
161 el
= el
/ sizeof(u16
);
163 eepdata
= (u16
*)(&ah
->eeprom
);
165 for (i
= 0; i
< el
; i
++)
172 ath_print(common
, ATH_DBG_EEPROM
,
173 "EEPROM Endianness is not native.. Changing.\n");
175 word
= swab16(eep
->baseEepHeader
.length
);
176 eep
->baseEepHeader
.length
= word
;
178 word
= swab16(eep
->baseEepHeader
.checksum
);
179 eep
->baseEepHeader
.checksum
= word
;
181 word
= swab16(eep
->baseEepHeader
.version
);
182 eep
->baseEepHeader
.version
= word
;
184 word
= swab16(eep
->baseEepHeader
.regDmn
[0]);
185 eep
->baseEepHeader
.regDmn
[0] = word
;
187 word
= swab16(eep
->baseEepHeader
.regDmn
[1]);
188 eep
->baseEepHeader
.regDmn
[1] = word
;
190 word
= swab16(eep
->baseEepHeader
.rfSilent
);
191 eep
->baseEepHeader
.rfSilent
= word
;
193 word
= swab16(eep
->baseEepHeader
.blueToothOptions
);
194 eep
->baseEepHeader
.blueToothOptions
= word
;
196 word
= swab16(eep
->baseEepHeader
.deviceCap
);
197 eep
->baseEepHeader
.deviceCap
= word
;
199 for (j
= 0; j
< ARRAY_SIZE(eep
->modalHeader
); j
++) {
200 struct modal_eep_header
*pModal
=
201 &eep
->modalHeader
[j
];
202 integer
= swab32(pModal
->antCtrlCommon
);
203 pModal
->antCtrlCommon
= integer
;
205 for (i
= 0; i
< AR5416_MAX_CHAINS
; i
++) {
206 integer
= swab32(pModal
->antCtrlChain
[i
]);
207 pModal
->antCtrlChain
[i
] = integer
;
210 for (i
= 0; i
< AR5416_EEPROM_MODAL_SPURS
; i
++) {
211 word
= swab16(pModal
->spurChans
[i
].spurChan
);
212 pModal
->spurChans
[i
].spurChan
= word
;
217 if (sum
!= 0xffff || ah
->eep_ops
->get_eeprom_ver(ah
) != AR5416_EEP_VER
||
218 ah
->eep_ops
->get_eeprom_rev(ah
) < AR5416_EEP_NO_BACK_VER
) {
219 ath_print(common
, ATH_DBG_FATAL
,
220 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
221 sum
, ah
->eep_ops
->get_eeprom_ver(ah
));
228 static u32
ath9k_hw_def_get_eeprom(struct ath_hw
*ah
,
229 enum eeprom_param param
)
231 struct ar5416_eeprom_def
*eep
= &ah
->eeprom
.def
;
232 struct modal_eep_header
*pModal
= eep
->modalHeader
;
233 struct base_eep_header
*pBase
= &eep
->baseEepHeader
;
237 return pModal
[0].noiseFloorThreshCh
[0];
239 return pModal
[1].noiseFloorThreshCh
[0];
240 case AR_EEPROM_MAC(0):
241 return pBase
->macAddr
[0] << 8 | pBase
->macAddr
[1];
242 case AR_EEPROM_MAC(1):
243 return pBase
->macAddr
[2] << 8 | pBase
->macAddr
[3];
244 case AR_EEPROM_MAC(2):
245 return pBase
->macAddr
[4] << 8 | pBase
->macAddr
[5];
247 return pBase
->regDmn
[0];
249 return pBase
->regDmn
[1];
251 return pBase
->deviceCap
;
253 return pBase
->opCapFlags
;
255 return pBase
->rfSilent
;
265 return AR5416_VER_MASK
;
267 return pBase
->txMask
;
269 return pBase
->rxMask
;
270 case EEP_RXGAIN_TYPE
:
271 return pBase
->rxGainType
;
272 case EEP_TXGAIN_TYPE
:
273 return pBase
->txGainType
;
275 if (AR5416_VER_MASK
>= AR5416_EEP_MINOR_VER_19
)
276 return pBase
->openLoopPwrCntl
? true : false;
279 case EEP_RC_CHAIN_MASK
:
280 if (AR5416_VER_MASK
>= AR5416_EEP_MINOR_VER_19
)
281 return pBase
->rcChainMask
;
284 case EEP_DAC_HPWR_5G
:
285 if (AR5416_VER_MASK
>= AR5416_EEP_MINOR_VER_20
)
286 return pBase
->dacHiPwrMode_5G
;
290 if (AR5416_VER_MASK
>= AR5416_EEP_MINOR_VER_22
)
291 return pBase
->frac_n_5g
;
294 case EEP_PWR_TABLE_OFFSET
:
295 if (AR5416_VER_MASK
>= AR5416_EEP_MINOR_VER_21
)
296 return pBase
->pwr_table_offset
;
298 return AR5416_PWR_TABLE_OFFSET_DB
;
304 static void ath9k_hw_def_set_gain(struct ath_hw
*ah
,
305 struct modal_eep_header
*pModal
,
306 struct ar5416_eeprom_def
*eep
,
307 u8 txRxAttenLocal
, int regChainOffset
, int i
)
309 if (AR5416_VER_MASK
>= AR5416_EEP_MINOR_VER_3
) {
310 txRxAttenLocal
= pModal
->txRxAttenCh
[i
];
312 if (AR_SREV_9280_10_OR_LATER(ah
)) {
313 REG_RMW_FIELD(ah
, AR_PHY_GAIN_2GHZ
+ regChainOffset
,
314 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN
,
315 pModal
->bswMargin
[i
]);
316 REG_RMW_FIELD(ah
, AR_PHY_GAIN_2GHZ
+ regChainOffset
,
317 AR_PHY_GAIN_2GHZ_XATTEN1_DB
,
318 pModal
->bswAtten
[i
]);
319 REG_RMW_FIELD(ah
, AR_PHY_GAIN_2GHZ
+ regChainOffset
,
320 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN
,
321 pModal
->xatten2Margin
[i
]);
322 REG_RMW_FIELD(ah
, AR_PHY_GAIN_2GHZ
+ regChainOffset
,
323 AR_PHY_GAIN_2GHZ_XATTEN2_DB
,
324 pModal
->xatten2Db
[i
]);
326 REG_WRITE(ah
, AR_PHY_GAIN_2GHZ
+ regChainOffset
,
327 (REG_READ(ah
, AR_PHY_GAIN_2GHZ
+ regChainOffset
) &
328 ~AR_PHY_GAIN_2GHZ_BSW_MARGIN
)
329 | SM(pModal
-> bswMargin
[i
],
330 AR_PHY_GAIN_2GHZ_BSW_MARGIN
));
331 REG_WRITE(ah
, AR_PHY_GAIN_2GHZ
+ regChainOffset
,
332 (REG_READ(ah
, AR_PHY_GAIN_2GHZ
+ regChainOffset
) &
333 ~AR_PHY_GAIN_2GHZ_BSW_ATTEN
)
334 | SM(pModal
->bswAtten
[i
],
335 AR_PHY_GAIN_2GHZ_BSW_ATTEN
));
339 if (AR_SREV_9280_10_OR_LATER(ah
)) {
341 AR_PHY_RXGAIN
+ regChainOffset
,
342 AR9280_PHY_RXGAIN_TXRX_ATTEN
, txRxAttenLocal
);
344 AR_PHY_RXGAIN
+ regChainOffset
,
345 AR9280_PHY_RXGAIN_TXRX_MARGIN
, pModal
->rxTxMarginCh
[i
]);
348 AR_PHY_RXGAIN
+ regChainOffset
,
349 (REG_READ(ah
, AR_PHY_RXGAIN
+ regChainOffset
) &
350 ~AR_PHY_RXGAIN_TXRX_ATTEN
)
351 | SM(txRxAttenLocal
, AR_PHY_RXGAIN_TXRX_ATTEN
));
353 AR_PHY_GAIN_2GHZ
+ regChainOffset
,
354 (REG_READ(ah
, AR_PHY_GAIN_2GHZ
+ regChainOffset
) &
355 ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN
) |
356 SM(pModal
->rxTxMarginCh
[i
], AR_PHY_GAIN_2GHZ_RXTX_MARGIN
));
360 static void ath9k_hw_def_set_board_values(struct ath_hw
*ah
,
361 struct ath9k_channel
*chan
)
363 struct modal_eep_header
*pModal
;
364 struct ar5416_eeprom_def
*eep
= &ah
->eeprom
.def
;
365 int i
, regChainOffset
;
368 pModal
= &(eep
->modalHeader
[IS_CHAN_2GHZ(chan
)]);
369 txRxAttenLocal
= IS_CHAN_2GHZ(chan
) ? 23 : 44;
371 REG_WRITE(ah
, AR_PHY_SWITCH_COM
,
372 ah
->eep_ops
->get_eeprom_antenna_cfg(ah
, chan
));
374 for (i
= 0; i
< AR5416_MAX_CHAINS
; i
++) {
375 if (AR_SREV_9280(ah
)) {
380 if (AR_SREV_5416_20_OR_LATER(ah
) &&
381 (ah
->rxchainmask
== 5 || ah
->txchainmask
== 5) && (i
!= 0))
382 regChainOffset
= (i
== 1) ? 0x2000 : 0x1000;
384 regChainOffset
= i
* 0x1000;
386 REG_WRITE(ah
, AR_PHY_SWITCH_CHAIN_0
+ regChainOffset
,
387 pModal
->antCtrlChain
[i
]);
389 REG_WRITE(ah
, AR_PHY_TIMING_CTRL4(0) + regChainOffset
,
390 (REG_READ(ah
, AR_PHY_TIMING_CTRL4(0) + regChainOffset
) &
391 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF
|
392 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF
)) |
393 SM(pModal
->iqCalICh
[i
],
394 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF
) |
395 SM(pModal
->iqCalQCh
[i
],
396 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF
));
398 if ((i
== 0) || AR_SREV_5416_20_OR_LATER(ah
))
399 ath9k_hw_def_set_gain(ah
, pModal
, eep
, txRxAttenLocal
,
403 if (AR_SREV_9280_10_OR_LATER(ah
)) {
404 if (IS_CHAN_2GHZ(chan
)) {
405 ath9k_hw_analog_shift_rmw(ah
, AR_AN_RF2G1_CH0
,
407 AR_AN_RF2G1_CH0_OB_S
,
409 ath9k_hw_analog_shift_rmw(ah
, AR_AN_RF2G1_CH0
,
411 AR_AN_RF2G1_CH0_DB_S
,
413 ath9k_hw_analog_shift_rmw(ah
, AR_AN_RF2G1_CH1
,
415 AR_AN_RF2G1_CH1_OB_S
,
417 ath9k_hw_analog_shift_rmw(ah
, AR_AN_RF2G1_CH1
,
419 AR_AN_RF2G1_CH1_DB_S
,
422 ath9k_hw_analog_shift_rmw(ah
, AR_AN_RF5G1_CH0
,
424 AR_AN_RF5G1_CH0_OB5_S
,
426 ath9k_hw_analog_shift_rmw(ah
, AR_AN_RF5G1_CH0
,
428 AR_AN_RF5G1_CH0_DB5_S
,
430 ath9k_hw_analog_shift_rmw(ah
, AR_AN_RF5G1_CH1
,
432 AR_AN_RF5G1_CH1_OB5_S
,
434 ath9k_hw_analog_shift_rmw(ah
, AR_AN_RF5G1_CH1
,
436 AR_AN_RF5G1_CH1_DB5_S
,
439 ath9k_hw_analog_shift_rmw(ah
, AR_AN_TOP2
,
440 AR_AN_TOP2_XPABIAS_LVL
,
441 AR_AN_TOP2_XPABIAS_LVL_S
,
443 ath9k_hw_analog_shift_rmw(ah
, AR_AN_TOP2
,
444 AR_AN_TOP2_LOCALBIAS
,
445 AR_AN_TOP2_LOCALBIAS_S
,
447 REG_RMW_FIELD(ah
, AR_PHY_XPA_CFG
, AR_PHY_FORCE_XPA_CFG
,
448 pModal
->force_xpaon
);
451 REG_RMW_FIELD(ah
, AR_PHY_SETTLING
, AR_PHY_SETTLING_SWITCH
,
452 pModal
->switchSettling
);
453 REG_RMW_FIELD(ah
, AR_PHY_DESIRED_SZ
, AR_PHY_DESIRED_SZ_ADC
,
454 pModal
->adcDesiredSize
);
456 if (!AR_SREV_9280_10_OR_LATER(ah
))
457 REG_RMW_FIELD(ah
, AR_PHY_DESIRED_SZ
,
458 AR_PHY_DESIRED_SZ_PGA
,
459 pModal
->pgaDesiredSize
);
461 REG_WRITE(ah
, AR_PHY_RF_CTL4
,
462 SM(pModal
->txEndToXpaOff
, AR_PHY_RF_CTL4_TX_END_XPAA_OFF
)
463 | SM(pModal
->txEndToXpaOff
,
464 AR_PHY_RF_CTL4_TX_END_XPAB_OFF
)
465 | SM(pModal
->txFrameToXpaOn
,
466 AR_PHY_RF_CTL4_FRAME_XPAA_ON
)
467 | SM(pModal
->txFrameToXpaOn
,
468 AR_PHY_RF_CTL4_FRAME_XPAB_ON
));
470 REG_RMW_FIELD(ah
, AR_PHY_RF_CTL3
, AR_PHY_TX_END_TO_A2_RX_ON
,
471 pModal
->txEndToRxOn
);
473 if (AR_SREV_9280_10_OR_LATER(ah
)) {
474 REG_RMW_FIELD(ah
, AR_PHY_CCA
, AR9280_PHY_CCA_THRESH62
,
476 REG_RMW_FIELD(ah
, AR_PHY_EXT_CCA0
,
477 AR_PHY_EXT_CCA0_THRESH62
,
480 REG_RMW_FIELD(ah
, AR_PHY_CCA
, AR_PHY_CCA_THRESH62
,
482 REG_RMW_FIELD(ah
, AR_PHY_EXT_CCA
,
483 AR_PHY_EXT_CCA_THRESH62
,
487 if (AR5416_VER_MASK
>= AR5416_EEP_MINOR_VER_2
) {
488 REG_RMW_FIELD(ah
, AR_PHY_RF_CTL2
,
489 AR_PHY_TX_END_DATA_START
,
490 pModal
->txFrameToDataStart
);
491 REG_RMW_FIELD(ah
, AR_PHY_RF_CTL2
, AR_PHY_TX_END_PA_ON
,
492 pModal
->txFrameToPaOn
);
495 if (AR5416_VER_MASK
>= AR5416_EEP_MINOR_VER_3
) {
496 if (IS_CHAN_HT40(chan
))
497 REG_RMW_FIELD(ah
, AR_PHY_SETTLING
,
498 AR_PHY_SETTLING_SWITCH
,
499 pModal
->swSettleHt40
);
502 if (AR_SREV_9280_20_OR_LATER(ah
) &&
503 AR5416_VER_MASK
>= AR5416_EEP_MINOR_VER_19
)
504 REG_RMW_FIELD(ah
, AR_PHY_CCK_TX_CTRL
,
505 AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK
,
509 if (AR_SREV_9280_20(ah
) && AR5416_VER_MASK
>= AR5416_EEP_MINOR_VER_20
) {
510 if (IS_CHAN_2GHZ(chan
))
511 REG_RMW_FIELD(ah
, AR_AN_TOP1
, AR_AN_TOP1_DACIPMODE
,
512 eep
->baseEepHeader
.dacLpMode
);
513 else if (eep
->baseEepHeader
.dacHiPwrMode_5G
)
514 REG_RMW_FIELD(ah
, AR_AN_TOP1
, AR_AN_TOP1_DACIPMODE
, 0);
516 REG_RMW_FIELD(ah
, AR_AN_TOP1
, AR_AN_TOP1_DACIPMODE
,
517 eep
->baseEepHeader
.dacLpMode
);
521 REG_RMW_FIELD(ah
, AR_PHY_FRAME_CTL
, AR_PHY_FRAME_CTL_TX_CLIP
,
522 pModal
->miscBits
>> 2);
524 REG_RMW_FIELD(ah
, AR_PHY_TX_PWRCTRL9
,
525 AR_PHY_TX_DESIRED_SCALE_CCK
,
526 eep
->baseEepHeader
.desiredScaleCCK
);
530 static void ath9k_hw_def_set_addac(struct ath_hw
*ah
,
531 struct ath9k_channel
*chan
)
533 #define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt])
534 struct modal_eep_header
*pModal
;
535 struct ar5416_eeprom_def
*eep
= &ah
->eeprom
.def
;
538 if (ah
->hw_version
.macVersion
!= AR_SREV_VERSION_9160
)
541 if (ah
->eep_ops
->get_eeprom_rev(ah
) < AR5416_EEP_MINOR_VER_7
)
544 pModal
= &(eep
->modalHeader
[IS_CHAN_2GHZ(chan
)]);
546 if (pModal
->xpaBiasLvl
!= 0xff) {
547 biaslevel
= pModal
->xpaBiasLvl
;
549 u16 resetFreqBin
, freqBin
, freqCount
= 0;
550 struct chan_centers centers
;
552 ath9k_hw_get_channel_centers(ah
, chan
, ¢ers
);
554 resetFreqBin
= FREQ2FBIN(centers
.synth_center
,
556 freqBin
= XPA_LVL_FREQ(0) & 0xff;
557 biaslevel
= (u8
) (XPA_LVL_FREQ(0) >> 14);
561 while (freqCount
< 3) {
562 if (XPA_LVL_FREQ(freqCount
) == 0x0)
565 freqBin
= XPA_LVL_FREQ(freqCount
) & 0xff;
566 if (resetFreqBin
>= freqBin
)
567 biaslevel
= (u8
)(XPA_LVL_FREQ(freqCount
) >> 14);
574 if (IS_CHAN_2GHZ(chan
)) {
575 INI_RA(&ah
->iniAddac
, 7, 1) = (INI_RA(&ah
->iniAddac
,
576 7, 1) & (~0x18)) | biaslevel
<< 3;
578 INI_RA(&ah
->iniAddac
, 6, 1) = (INI_RA(&ah
->iniAddac
,
579 6, 1) & (~0xc0)) | biaslevel
<< 6;
584 static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw
*ah
,
585 struct ath9k_channel
*chan
,
586 struct cal_data_per_freq
*pRawDataSet
,
587 u8
*bChans
, u16 availPiers
,
588 u16 tPdGainOverlap
, int16_t *pMinCalPower
,
589 u16
*pPdGainBoundaries
, u8
*pPDADCValues
,
594 u16 idxL
= 0, idxR
= 0, numPiers
;
595 static u8 vpdTableL
[AR5416_NUM_PD_GAINS
]
596 [AR5416_MAX_PWR_RANGE_IN_HALF_DB
];
597 static u8 vpdTableR
[AR5416_NUM_PD_GAINS
]
598 [AR5416_MAX_PWR_RANGE_IN_HALF_DB
];
599 static u8 vpdTableI
[AR5416_NUM_PD_GAINS
]
600 [AR5416_MAX_PWR_RANGE_IN_HALF_DB
];
602 u8
*pVpdL
, *pVpdR
, *pPwrL
, *pPwrR
;
603 u8 minPwrT4
[AR5416_NUM_PD_GAINS
];
604 u8 maxPwrT4
[AR5416_NUM_PD_GAINS
];
607 u16 sizeCurrVpdTable
, maxIndex
, tgtIndex
;
609 int16_t minDelta
= 0;
610 struct chan_centers centers
;
612 ath9k_hw_get_channel_centers(ah
, chan
, ¢ers
);
614 for (numPiers
= 0; numPiers
< availPiers
; numPiers
++) {
615 if (bChans
[numPiers
] == AR5416_BCHAN_UNUSED
)
619 match
= ath9k_hw_get_lower_upper_index((u8
)FREQ2FBIN(centers
.synth_center
,
621 bChans
, numPiers
, &idxL
, &idxR
);
624 for (i
= 0; i
< numXpdGains
; i
++) {
625 minPwrT4
[i
] = pRawDataSet
[idxL
].pwrPdg
[i
][0];
626 maxPwrT4
[i
] = pRawDataSet
[idxL
].pwrPdg
[i
][4];
627 ath9k_hw_fill_vpd_table(minPwrT4
[i
], maxPwrT4
[i
],
628 pRawDataSet
[idxL
].pwrPdg
[i
],
629 pRawDataSet
[idxL
].vpdPdg
[i
],
630 AR5416_PD_GAIN_ICEPTS
,
634 for (i
= 0; i
< numXpdGains
; i
++) {
635 pVpdL
= pRawDataSet
[idxL
].vpdPdg
[i
];
636 pPwrL
= pRawDataSet
[idxL
].pwrPdg
[i
];
637 pVpdR
= pRawDataSet
[idxR
].vpdPdg
[i
];
638 pPwrR
= pRawDataSet
[idxR
].pwrPdg
[i
];
640 minPwrT4
[i
] = max(pPwrL
[0], pPwrR
[0]);
643 min(pPwrL
[AR5416_PD_GAIN_ICEPTS
- 1],
644 pPwrR
[AR5416_PD_GAIN_ICEPTS
- 1]);
647 ath9k_hw_fill_vpd_table(minPwrT4
[i
], maxPwrT4
[i
],
649 AR5416_PD_GAIN_ICEPTS
,
651 ath9k_hw_fill_vpd_table(minPwrT4
[i
], maxPwrT4
[i
],
653 AR5416_PD_GAIN_ICEPTS
,
656 for (j
= 0; j
<= (maxPwrT4
[i
] - minPwrT4
[i
]) / 2; j
++) {
658 (u8
)(ath9k_hw_interpolate((u16
)
663 bChans
[idxL
], bChans
[idxR
],
664 vpdTableL
[i
][j
], vpdTableR
[i
][j
]));
669 *pMinCalPower
= (int16_t)(minPwrT4
[0] / 2);
673 for (i
= 0; i
< numXpdGains
; i
++) {
674 if (i
== (numXpdGains
- 1))
675 pPdGainBoundaries
[i
] =
676 (u16
)(maxPwrT4
[i
] / 2);
678 pPdGainBoundaries
[i
] =
679 (u16
)((maxPwrT4
[i
] + minPwrT4
[i
+ 1]) / 4);
681 pPdGainBoundaries
[i
] =
682 min((u16
)AR5416_MAX_RATE_POWER
, pPdGainBoundaries
[i
]);
684 if ((i
== 0) && !AR_SREV_5416_20_OR_LATER(ah
)) {
685 minDelta
= pPdGainBoundaries
[0] - 23;
686 pPdGainBoundaries
[0] = 23;
692 if (AR_SREV_9280_10_OR_LATER(ah
))
693 ss
= (int16_t)(0 - (minPwrT4
[i
] / 2));
697 ss
= (int16_t)((pPdGainBoundaries
[i
- 1] -
699 tPdGainOverlap
+ 1 + minDelta
);
701 vpdStep
= (int16_t)(vpdTableI
[i
][1] - vpdTableI
[i
][0]);
702 vpdStep
= (int16_t)((vpdStep
< 1) ? 1 : vpdStep
);
704 while ((ss
< 0) && (k
< (AR5416_NUM_PDADC_VALUES
- 1))) {
705 tmpVal
= (int16_t)(vpdTableI
[i
][0] + ss
* vpdStep
);
706 pPDADCValues
[k
++] = (u8
)((tmpVal
< 0) ? 0 : tmpVal
);
710 sizeCurrVpdTable
= (u8
) ((maxPwrT4
[i
] - minPwrT4
[i
]) / 2 + 1);
711 tgtIndex
= (u8
)(pPdGainBoundaries
[i
] + tPdGainOverlap
-
713 maxIndex
= (tgtIndex
< sizeCurrVpdTable
) ?
714 tgtIndex
: sizeCurrVpdTable
;
716 while ((ss
< maxIndex
) && (k
< (AR5416_NUM_PDADC_VALUES
- 1))) {
717 pPDADCValues
[k
++] = vpdTableI
[i
][ss
++];
720 vpdStep
= (int16_t)(vpdTableI
[i
][sizeCurrVpdTable
- 1] -
721 vpdTableI
[i
][sizeCurrVpdTable
- 2]);
722 vpdStep
= (int16_t)((vpdStep
< 1) ? 1 : vpdStep
);
724 if (tgtIndex
> maxIndex
) {
725 while ((ss
<= tgtIndex
) &&
726 (k
< (AR5416_NUM_PDADC_VALUES
- 1))) {
727 tmpVal
= (int16_t)((vpdTableI
[i
][sizeCurrVpdTable
- 1] +
728 (ss
- maxIndex
+ 1) * vpdStep
));
729 pPDADCValues
[k
++] = (u8
)((tmpVal
> 255) ?
736 while (i
< AR5416_PD_GAINS_IN_MASK
) {
737 pPdGainBoundaries
[i
] = pPdGainBoundaries
[i
- 1];
741 while (k
< AR5416_NUM_PDADC_VALUES
) {
742 pPDADCValues
[k
] = pPDADCValues
[k
- 1];
749 static int16_t ath9k_change_gain_boundary_setting(struct ath_hw
*ah
,
752 u16 pdGainOverlap_t2
,
753 int8_t pwr_table_offset
,
759 /* Prior to writing the boundaries or the pdadc vs. power table
760 * into the chip registers the default starting point on the pdadc
761 * vs. power table needs to be checked and the curve boundaries
762 * adjusted accordingly
764 if (AR_SREV_9280_20_OR_LATER(ah
)) {
767 if (AR5416_PWR_TABLE_OFFSET_DB
!= pwr_table_offset
) {
768 /* get the difference in dB */
769 *diff
= (u16
)(pwr_table_offset
- AR5416_PWR_TABLE_OFFSET_DB
);
770 /* get the number of half dB steps */
772 /* change the original gain boundary settings
773 * by the number of half dB steps
775 for (k
= 0; k
< numXpdGain
; k
++)
776 gb
[k
] = (u16
)(gb
[k
] - *diff
);
778 /* Because of a hardware limitation, ensure the gain boundary
779 * is not larger than (63 - overlap)
781 gb_limit
= (u16
)(AR5416_MAX_RATE_POWER
- pdGainOverlap_t2
);
783 for (k
= 0; k
< numXpdGain
; k
++)
784 gb
[k
] = (u16
)min(gb_limit
, gb
[k
]);
790 static void ath9k_adjust_pdadc_values(struct ath_hw
*ah
,
791 int8_t pwr_table_offset
,
795 #define NUM_PDADC(diff) (AR5416_NUM_PDADC_VALUES - diff)
798 /* If this is a board that has a pwrTableOffset that differs from
799 * the default AR5416_PWR_TABLE_OFFSET_DB then the start of the
800 * pdadc vs pwr table needs to be adjusted prior to writing to the
803 if (AR_SREV_9280_20_OR_LATER(ah
)) {
804 if (AR5416_PWR_TABLE_OFFSET_DB
!= pwr_table_offset
) {
805 /* shift the table to start at the new offset */
806 for (k
= 0; k
< (u16
)NUM_PDADC(diff
); k
++ ) {
807 pdadcValues
[k
] = pdadcValues
[k
+ diff
];
810 /* fill the back of the table */
811 for (k
= (u16
)NUM_PDADC(diff
); k
< NUM_PDADC(0); k
++) {
812 pdadcValues
[k
] = pdadcValues
[NUM_PDADC(diff
)];
819 static void ath9k_hw_set_def_power_cal_table(struct ath_hw
*ah
,
820 struct ath9k_channel
*chan
,
821 int16_t *pTxPowerIndexOffset
)
823 #define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x)
824 #define SM_PDGAIN_B(x, y) \
825 SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y)
826 struct ath_common
*common
= ath9k_hw_common(ah
);
827 struct ar5416_eeprom_def
*pEepData
= &ah
->eeprom
.def
;
828 struct cal_data_per_freq
*pRawDataset
;
829 u8
*pCalBChans
= NULL
;
830 u16 pdGainOverlap_t2
;
831 static u8 pdadcValues
[AR5416_NUM_PDADC_VALUES
];
832 u16 gainBoundaries
[AR5416_PD_GAINS_IN_MASK
];
834 int16_t tMinCalPower
, diff
= 0;
835 u16 numXpdGain
, xpdMask
;
836 u16 xpdGainValues
[AR5416_NUM_PD_GAINS
] = { 0, 0, 0, 0 };
837 u32 reg32
, regOffset
, regChainOffset
;
839 int8_t pwr_table_offset
;
841 modalIdx
= IS_CHAN_2GHZ(chan
) ? 1 : 0;
842 xpdMask
= pEepData
->modalHeader
[modalIdx
].xpdGain
;
844 pwr_table_offset
= ah
->eep_ops
->get_eeprom(ah
, EEP_PWR_TABLE_OFFSET
);
846 if ((pEepData
->baseEepHeader
.version
& AR5416_EEP_VER_MINOR_MASK
) >=
847 AR5416_EEP_MINOR_VER_2
) {
849 pEepData
->modalHeader
[modalIdx
].pdGainOverlap
;
851 pdGainOverlap_t2
= (u16
)(MS(REG_READ(ah
, AR_PHY_TPCRG5
),
852 AR_PHY_TPCRG5_PD_GAIN_OVERLAP
));
855 if (IS_CHAN_2GHZ(chan
)) {
856 pCalBChans
= pEepData
->calFreqPier2G
;
857 numPiers
= AR5416_NUM_2G_CAL_PIERS
;
859 pCalBChans
= pEepData
->calFreqPier5G
;
860 numPiers
= AR5416_NUM_5G_CAL_PIERS
;
863 if (OLC_FOR_AR9280_20_LATER
&& IS_CHAN_2GHZ(chan
)) {
864 pRawDataset
= pEepData
->calPierData2G
[0];
865 ah
->initPDADC
= ((struct calDataPerFreqOpLoop
*)
866 pRawDataset
)->vpdPdg
[0][0];
871 for (i
= 1; i
<= AR5416_PD_GAINS_IN_MASK
; i
++) {
872 if ((xpdMask
>> (AR5416_PD_GAINS_IN_MASK
- i
)) & 1) {
873 if (numXpdGain
>= AR5416_NUM_PD_GAINS
)
875 xpdGainValues
[numXpdGain
] =
876 (u16
)(AR5416_PD_GAINS_IN_MASK
- i
);
881 REG_RMW_FIELD(ah
, AR_PHY_TPCRG1
, AR_PHY_TPCRG1_NUM_PD_GAIN
,
882 (numXpdGain
- 1) & 0x3);
883 REG_RMW_FIELD(ah
, AR_PHY_TPCRG1
, AR_PHY_TPCRG1_PD_GAIN_1
,
885 REG_RMW_FIELD(ah
, AR_PHY_TPCRG1
, AR_PHY_TPCRG1_PD_GAIN_2
,
887 REG_RMW_FIELD(ah
, AR_PHY_TPCRG1
, AR_PHY_TPCRG1_PD_GAIN_3
,
890 for (i
= 0; i
< AR5416_MAX_CHAINS
; i
++) {
891 if (AR_SREV_5416_20_OR_LATER(ah
) &&
892 (ah
->rxchainmask
== 5 || ah
->txchainmask
== 5) &&
894 regChainOffset
= (i
== 1) ? 0x2000 : 0x1000;
896 regChainOffset
= i
* 0x1000;
898 if (pEepData
->baseEepHeader
.txMask
& (1 << i
)) {
899 if (IS_CHAN_2GHZ(chan
))
900 pRawDataset
= pEepData
->calPierData2G
[i
];
902 pRawDataset
= pEepData
->calPierData5G
[i
];
905 if (OLC_FOR_AR9280_20_LATER
) {
909 ath9k_get_txgain_index(ah
, chan
,
910 (struct calDataPerFreqOpLoop
*)pRawDataset
,
911 pCalBChans
, numPiers
, &txPower
, &pcdacIdx
);
912 ath9k_olc_get_pdadcs(ah
, pcdacIdx
,
913 txPower
/2, pdadcValues
);
915 ath9k_hw_get_def_gain_boundaries_pdadcs(ah
,
917 pCalBChans
, numPiers
,
925 diff
= ath9k_change_gain_boundary_setting(ah
,
932 if ((i
== 0) || AR_SREV_5416_20_OR_LATER(ah
)) {
933 if (OLC_FOR_AR9280_20_LATER
) {
935 AR_PHY_TPCRG5
+ regChainOffset
,
937 AR_PHY_TPCRG5_PD_GAIN_OVERLAP
) |
938 SM_PD_GAIN(1) | SM_PD_GAIN(2) |
939 SM_PD_GAIN(3) | SM_PD_GAIN(4));
942 AR_PHY_TPCRG5
+ regChainOffset
,
944 AR_PHY_TPCRG5_PD_GAIN_OVERLAP
)|
953 ath9k_adjust_pdadc_values(ah
, pwr_table_offset
,
956 regOffset
= AR_PHY_BASE
+ (672 << 2) + regChainOffset
;
957 for (j
= 0; j
< 32; j
++) {
958 reg32
= ((pdadcValues
[4 * j
+ 0] & 0xFF) << 0) |
959 ((pdadcValues
[4 * j
+ 1] & 0xFF) << 8) |
960 ((pdadcValues
[4 * j
+ 2] & 0xFF) << 16)|
961 ((pdadcValues
[4 * j
+ 3] & 0xFF) << 24);
962 REG_WRITE(ah
, regOffset
, reg32
);
964 ath_print(common
, ATH_DBG_EEPROM
,
965 "PDADC (%d,%4x): %4.4x %8.8x\n",
966 i
, regChainOffset
, regOffset
,
968 ath_print(common
, ATH_DBG_EEPROM
,
969 "PDADC: Chain %d | PDADC %3d "
970 "Value %3d | PDADC %3d Value %3d | "
971 "PDADC %3d Value %3d | PDADC %3d "
973 i
, 4 * j
, pdadcValues
[4 * j
],
974 4 * j
+ 1, pdadcValues
[4 * j
+ 1],
975 4 * j
+ 2, pdadcValues
[4 * j
+ 2],
977 pdadcValues
[4 * j
+ 3]);
984 *pTxPowerIndexOffset
= 0;
989 static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw
*ah
,
990 struct ath9k_channel
*chan
,
993 u16 AntennaReduction
,
994 u16 twiceMaxRegulatoryPower
,
997 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
998 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 9 /* 10*log10(3)*2 */
1000 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
1001 struct ar5416_eeprom_def
*pEepData
= &ah
->eeprom
.def
;
1002 u16 twiceMaxEdgePower
= AR5416_MAX_RATE_POWER
;
1003 static const u16 tpScaleReductionTable
[5] =
1004 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER
};
1007 int16_t twiceLargestAntenna
;
1008 struct cal_ctl_data
*rep
;
1009 struct cal_target_power_leg targetPowerOfdm
, targetPowerCck
= {
1012 struct cal_target_power_leg targetPowerOfdmExt
= {
1013 0, { 0, 0, 0, 0} }, targetPowerCckExt
= {
1016 struct cal_target_power_ht targetPowerHt20
, targetPowerHt40
= {
1019 u16 scaledPower
= 0, minCtlPower
, maxRegAllowedPower
;
1020 u16 ctlModesFor11a
[] =
1021 { CTL_11A
, CTL_5GHT20
, CTL_11A_EXT
, CTL_5GHT40
};
1022 u16 ctlModesFor11g
[] =
1023 { CTL_11B
, CTL_11G
, CTL_2GHT20
, CTL_11B_EXT
, CTL_11G_EXT
,
1026 u16 numCtlModes
, *pCtlMode
, ctlMode
, freq
;
1027 struct chan_centers centers
;
1029 u16 twiceMinEdgePower
;
1031 tx_chainmask
= ah
->txchainmask
;
1033 ath9k_hw_get_channel_centers(ah
, chan
, ¢ers
);
1035 twiceLargestAntenna
= max(
1036 pEepData
->modalHeader
1037 [IS_CHAN_2GHZ(chan
)].antennaGainCh
[0],
1038 pEepData
->modalHeader
1039 [IS_CHAN_2GHZ(chan
)].antennaGainCh
[1]);
1041 twiceLargestAntenna
= max((u8
)twiceLargestAntenna
,
1042 pEepData
->modalHeader
1043 [IS_CHAN_2GHZ(chan
)].antennaGainCh
[2]);
1045 twiceLargestAntenna
= (int16_t)min(AntennaReduction
-
1046 twiceLargestAntenna
, 0);
1048 maxRegAllowedPower
= twiceMaxRegulatoryPower
+ twiceLargestAntenna
;
1050 if (regulatory
->tp_scale
!= ATH9K_TP_SCALE_MAX
) {
1051 maxRegAllowedPower
-=
1052 (tpScaleReductionTable
[(regulatory
->tp_scale
)] * 2);
1055 scaledPower
= min(powerLimit
, maxRegAllowedPower
);
1057 switch (ar5416_get_ntxchains(tx_chainmask
)) {
1061 scaledPower
-= REDUCE_SCALED_POWER_BY_TWO_CHAIN
;
1064 scaledPower
-= REDUCE_SCALED_POWER_BY_THREE_CHAIN
;
1068 scaledPower
= max((u16
)0, scaledPower
);
1070 if (IS_CHAN_2GHZ(chan
)) {
1071 numCtlModes
= ARRAY_SIZE(ctlModesFor11g
) -
1072 SUB_NUM_CTL_MODES_AT_2G_40
;
1073 pCtlMode
= ctlModesFor11g
;
1075 ath9k_hw_get_legacy_target_powers(ah
, chan
,
1076 pEepData
->calTargetPowerCck
,
1077 AR5416_NUM_2G_CCK_TARGET_POWERS
,
1078 &targetPowerCck
, 4, false);
1079 ath9k_hw_get_legacy_target_powers(ah
, chan
,
1080 pEepData
->calTargetPower2G
,
1081 AR5416_NUM_2G_20_TARGET_POWERS
,
1082 &targetPowerOfdm
, 4, false);
1083 ath9k_hw_get_target_powers(ah
, chan
,
1084 pEepData
->calTargetPower2GHT20
,
1085 AR5416_NUM_2G_20_TARGET_POWERS
,
1086 &targetPowerHt20
, 8, false);
1088 if (IS_CHAN_HT40(chan
)) {
1089 numCtlModes
= ARRAY_SIZE(ctlModesFor11g
);
1090 ath9k_hw_get_target_powers(ah
, chan
,
1091 pEepData
->calTargetPower2GHT40
,
1092 AR5416_NUM_2G_40_TARGET_POWERS
,
1093 &targetPowerHt40
, 8, true);
1094 ath9k_hw_get_legacy_target_powers(ah
, chan
,
1095 pEepData
->calTargetPowerCck
,
1096 AR5416_NUM_2G_CCK_TARGET_POWERS
,
1097 &targetPowerCckExt
, 4, true);
1098 ath9k_hw_get_legacy_target_powers(ah
, chan
,
1099 pEepData
->calTargetPower2G
,
1100 AR5416_NUM_2G_20_TARGET_POWERS
,
1101 &targetPowerOfdmExt
, 4, true);
1104 numCtlModes
= ARRAY_SIZE(ctlModesFor11a
) -
1105 SUB_NUM_CTL_MODES_AT_5G_40
;
1106 pCtlMode
= ctlModesFor11a
;
1108 ath9k_hw_get_legacy_target_powers(ah
, chan
,
1109 pEepData
->calTargetPower5G
,
1110 AR5416_NUM_5G_20_TARGET_POWERS
,
1111 &targetPowerOfdm
, 4, false);
1112 ath9k_hw_get_target_powers(ah
, chan
,
1113 pEepData
->calTargetPower5GHT20
,
1114 AR5416_NUM_5G_20_TARGET_POWERS
,
1115 &targetPowerHt20
, 8, false);
1117 if (IS_CHAN_HT40(chan
)) {
1118 numCtlModes
= ARRAY_SIZE(ctlModesFor11a
);
1119 ath9k_hw_get_target_powers(ah
, chan
,
1120 pEepData
->calTargetPower5GHT40
,
1121 AR5416_NUM_5G_40_TARGET_POWERS
,
1122 &targetPowerHt40
, 8, true);
1123 ath9k_hw_get_legacy_target_powers(ah
, chan
,
1124 pEepData
->calTargetPower5G
,
1125 AR5416_NUM_5G_20_TARGET_POWERS
,
1126 &targetPowerOfdmExt
, 4, true);
1130 for (ctlMode
= 0; ctlMode
< numCtlModes
; ctlMode
++) {
1131 bool isHt40CtlMode
= (pCtlMode
[ctlMode
] == CTL_5GHT40
) ||
1132 (pCtlMode
[ctlMode
] == CTL_2GHT40
);
1134 freq
= centers
.synth_center
;
1135 else if (pCtlMode
[ctlMode
] & EXT_ADDITIVE
)
1136 freq
= centers
.ext_center
;
1138 freq
= centers
.ctl_center
;
1140 if (ah
->eep_ops
->get_eeprom_ver(ah
) == 14 &&
1141 ah
->eep_ops
->get_eeprom_rev(ah
) <= 2)
1142 twiceMaxEdgePower
= AR5416_MAX_RATE_POWER
;
1144 for (i
= 0; (i
< AR5416_NUM_CTLS
) && pEepData
->ctlIndex
[i
]; i
++) {
1145 if ((((cfgCtl
& ~CTL_MODE_M
) |
1146 (pCtlMode
[ctlMode
] & CTL_MODE_M
)) ==
1147 pEepData
->ctlIndex
[i
]) ||
1148 (((cfgCtl
& ~CTL_MODE_M
) |
1149 (pCtlMode
[ctlMode
] & CTL_MODE_M
)) ==
1150 ((pEepData
->ctlIndex
[i
] & CTL_MODE_M
) | SD_NO_CTL
))) {
1151 rep
= &(pEepData
->ctlData
[i
]);
1153 twiceMinEdgePower
= ath9k_hw_get_max_edge_power(freq
,
1154 rep
->ctlEdges
[ar5416_get_ntxchains(tx_chainmask
) - 1],
1155 IS_CHAN_2GHZ(chan
), AR5416_NUM_BAND_EDGES
);
1157 if ((cfgCtl
& ~CTL_MODE_M
) == SD_NO_CTL
) {
1158 twiceMaxEdgePower
= min(twiceMaxEdgePower
,
1161 twiceMaxEdgePower
= twiceMinEdgePower
;
1167 minCtlPower
= min(twiceMaxEdgePower
, scaledPower
);
1169 switch (pCtlMode
[ctlMode
]) {
1171 for (i
= 0; i
< ARRAY_SIZE(targetPowerCck
.tPow2x
); i
++) {
1172 targetPowerCck
.tPow2x
[i
] =
1173 min((u16
)targetPowerCck
.tPow2x
[i
],
1179 for (i
= 0; i
< ARRAY_SIZE(targetPowerOfdm
.tPow2x
); i
++) {
1180 targetPowerOfdm
.tPow2x
[i
] =
1181 min((u16
)targetPowerOfdm
.tPow2x
[i
],
1187 for (i
= 0; i
< ARRAY_SIZE(targetPowerHt20
.tPow2x
); i
++) {
1188 targetPowerHt20
.tPow2x
[i
] =
1189 min((u16
)targetPowerHt20
.tPow2x
[i
],
1194 targetPowerCckExt
.tPow2x
[0] = min((u16
)
1195 targetPowerCckExt
.tPow2x
[0],
1200 targetPowerOfdmExt
.tPow2x
[0] = min((u16
)
1201 targetPowerOfdmExt
.tPow2x
[0],
1206 for (i
= 0; i
< ARRAY_SIZE(targetPowerHt40
.tPow2x
); i
++) {
1207 targetPowerHt40
.tPow2x
[i
] =
1208 min((u16
)targetPowerHt40
.tPow2x
[i
],
1217 ratesArray
[rate6mb
] = ratesArray
[rate9mb
] = ratesArray
[rate12mb
] =
1218 ratesArray
[rate18mb
] = ratesArray
[rate24mb
] =
1219 targetPowerOfdm
.tPow2x
[0];
1220 ratesArray
[rate36mb
] = targetPowerOfdm
.tPow2x
[1];
1221 ratesArray
[rate48mb
] = targetPowerOfdm
.tPow2x
[2];
1222 ratesArray
[rate54mb
] = targetPowerOfdm
.tPow2x
[3];
1223 ratesArray
[rateXr
] = targetPowerOfdm
.tPow2x
[0];
1225 for (i
= 0; i
< ARRAY_SIZE(targetPowerHt20
.tPow2x
); i
++)
1226 ratesArray
[rateHt20_0
+ i
] = targetPowerHt20
.tPow2x
[i
];
1228 if (IS_CHAN_2GHZ(chan
)) {
1229 ratesArray
[rate1l
] = targetPowerCck
.tPow2x
[0];
1230 ratesArray
[rate2s
] = ratesArray
[rate2l
] =
1231 targetPowerCck
.tPow2x
[1];
1232 ratesArray
[rate5_5s
] = ratesArray
[rate5_5l
] =
1233 targetPowerCck
.tPow2x
[2];
1234 ratesArray
[rate11s
] = ratesArray
[rate11l
] =
1235 targetPowerCck
.tPow2x
[3];
1237 if (IS_CHAN_HT40(chan
)) {
1238 for (i
= 0; i
< ARRAY_SIZE(targetPowerHt40
.tPow2x
); i
++) {
1239 ratesArray
[rateHt40_0
+ i
] =
1240 targetPowerHt40
.tPow2x
[i
];
1242 ratesArray
[rateDupOfdm
] = targetPowerHt40
.tPow2x
[0];
1243 ratesArray
[rateDupCck
] = targetPowerHt40
.tPow2x
[0];
1244 ratesArray
[rateExtOfdm
] = targetPowerOfdmExt
.tPow2x
[0];
1245 if (IS_CHAN_2GHZ(chan
)) {
1246 ratesArray
[rateExtCck
] =
1247 targetPowerCckExt
.tPow2x
[0];
1252 static void ath9k_hw_def_set_txpower(struct ath_hw
*ah
,
1253 struct ath9k_channel
*chan
,
1255 u8 twiceAntennaReduction
,
1256 u8 twiceMaxRegulatoryPower
,
1259 #define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta)
1260 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
1261 struct ar5416_eeprom_def
*pEepData
= &ah
->eeprom
.def
;
1262 struct modal_eep_header
*pModal
=
1263 &(pEepData
->modalHeader
[IS_CHAN_2GHZ(chan
)]);
1264 int16_t ratesArray
[Ar5416RateSize
];
1265 int16_t txPowerIndexOffset
= 0;
1266 u8 ht40PowerIncForPdadc
= 2;
1267 int i
, cck_ofdm_delta
= 0;
1269 memset(ratesArray
, 0, sizeof(ratesArray
));
1271 if ((pEepData
->baseEepHeader
.version
& AR5416_EEP_VER_MINOR_MASK
) >=
1272 AR5416_EEP_MINOR_VER_2
) {
1273 ht40PowerIncForPdadc
= pModal
->ht40PowerIncForPdadc
;
1276 ath9k_hw_set_def_power_per_rate_table(ah
, chan
,
1277 &ratesArray
[0], cfgCtl
,
1278 twiceAntennaReduction
,
1279 twiceMaxRegulatoryPower
,
1282 ath9k_hw_set_def_power_cal_table(ah
, chan
, &txPowerIndexOffset
);
1284 for (i
= 0; i
< ARRAY_SIZE(ratesArray
); i
++) {
1285 ratesArray
[i
] = (int16_t)(txPowerIndexOffset
+ ratesArray
[i
]);
1286 if (ratesArray
[i
] > AR5416_MAX_RATE_POWER
)
1287 ratesArray
[i
] = AR5416_MAX_RATE_POWER
;
1290 if (AR_SREV_9280_10_OR_LATER(ah
)) {
1291 for (i
= 0; i
< Ar5416RateSize
; i
++) {
1292 int8_t pwr_table_offset
;
1294 pwr_table_offset
= ah
->eep_ops
->get_eeprom(ah
,
1295 EEP_PWR_TABLE_OFFSET
);
1296 ratesArray
[i
] -= pwr_table_offset
* 2;
1300 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE1
,
1301 ATH9K_POW_SM(ratesArray
[rate18mb
], 24)
1302 | ATH9K_POW_SM(ratesArray
[rate12mb
], 16)
1303 | ATH9K_POW_SM(ratesArray
[rate9mb
], 8)
1304 | ATH9K_POW_SM(ratesArray
[rate6mb
], 0));
1305 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE2
,
1306 ATH9K_POW_SM(ratesArray
[rate54mb
], 24)
1307 | ATH9K_POW_SM(ratesArray
[rate48mb
], 16)
1308 | ATH9K_POW_SM(ratesArray
[rate36mb
], 8)
1309 | ATH9K_POW_SM(ratesArray
[rate24mb
], 0));
1311 if (IS_CHAN_2GHZ(chan
)) {
1312 if (OLC_FOR_AR9280_20_LATER
) {
1314 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE3
,
1315 ATH9K_POW_SM(RT_AR_DELTA(rate2s
), 24)
1316 | ATH9K_POW_SM(RT_AR_DELTA(rate2l
), 16)
1317 | ATH9K_POW_SM(ratesArray
[rateXr
], 8)
1318 | ATH9K_POW_SM(RT_AR_DELTA(rate1l
), 0));
1319 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE4
,
1320 ATH9K_POW_SM(RT_AR_DELTA(rate11s
), 24)
1321 | ATH9K_POW_SM(RT_AR_DELTA(rate11l
), 16)
1322 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5s
), 8)
1323 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5l
), 0));
1325 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE3
,
1326 ATH9K_POW_SM(ratesArray
[rate2s
], 24)
1327 | ATH9K_POW_SM(ratesArray
[rate2l
], 16)
1328 | ATH9K_POW_SM(ratesArray
[rateXr
], 8)
1329 | ATH9K_POW_SM(ratesArray
[rate1l
], 0));
1330 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE4
,
1331 ATH9K_POW_SM(ratesArray
[rate11s
], 24)
1332 | ATH9K_POW_SM(ratesArray
[rate11l
], 16)
1333 | ATH9K_POW_SM(ratesArray
[rate5_5s
], 8)
1334 | ATH9K_POW_SM(ratesArray
[rate5_5l
], 0));
1338 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE5
,
1339 ATH9K_POW_SM(ratesArray
[rateHt20_3
], 24)
1340 | ATH9K_POW_SM(ratesArray
[rateHt20_2
], 16)
1341 | ATH9K_POW_SM(ratesArray
[rateHt20_1
], 8)
1342 | ATH9K_POW_SM(ratesArray
[rateHt20_0
], 0));
1343 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE6
,
1344 ATH9K_POW_SM(ratesArray
[rateHt20_7
], 24)
1345 | ATH9K_POW_SM(ratesArray
[rateHt20_6
], 16)
1346 | ATH9K_POW_SM(ratesArray
[rateHt20_5
], 8)
1347 | ATH9K_POW_SM(ratesArray
[rateHt20_4
], 0));
1349 if (IS_CHAN_HT40(chan
)) {
1350 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE7
,
1351 ATH9K_POW_SM(ratesArray
[rateHt40_3
] +
1352 ht40PowerIncForPdadc
, 24)
1353 | ATH9K_POW_SM(ratesArray
[rateHt40_2
] +
1354 ht40PowerIncForPdadc
, 16)
1355 | ATH9K_POW_SM(ratesArray
[rateHt40_1
] +
1356 ht40PowerIncForPdadc
, 8)
1357 | ATH9K_POW_SM(ratesArray
[rateHt40_0
] +
1358 ht40PowerIncForPdadc
, 0));
1359 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE8
,
1360 ATH9K_POW_SM(ratesArray
[rateHt40_7
] +
1361 ht40PowerIncForPdadc
, 24)
1362 | ATH9K_POW_SM(ratesArray
[rateHt40_6
] +
1363 ht40PowerIncForPdadc
, 16)
1364 | ATH9K_POW_SM(ratesArray
[rateHt40_5
] +
1365 ht40PowerIncForPdadc
, 8)
1366 | ATH9K_POW_SM(ratesArray
[rateHt40_4
] +
1367 ht40PowerIncForPdadc
, 0));
1368 if (OLC_FOR_AR9280_20_LATER
) {
1369 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE9
,
1370 ATH9K_POW_SM(ratesArray
[rateExtOfdm
], 24)
1371 | ATH9K_POW_SM(RT_AR_DELTA(rateExtCck
), 16)
1372 | ATH9K_POW_SM(ratesArray
[rateDupOfdm
], 8)
1373 | ATH9K_POW_SM(RT_AR_DELTA(rateDupCck
), 0));
1375 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE9
,
1376 ATH9K_POW_SM(ratesArray
[rateExtOfdm
], 24)
1377 | ATH9K_POW_SM(ratesArray
[rateExtCck
], 16)
1378 | ATH9K_POW_SM(ratesArray
[rateDupOfdm
], 8)
1379 | ATH9K_POW_SM(ratesArray
[rateDupCck
], 0));
1383 REG_WRITE(ah
, AR_PHY_POWER_TX_SUB
,
1384 ATH9K_POW_SM(pModal
->pwrDecreaseFor3Chain
, 6)
1385 | ATH9K_POW_SM(pModal
->pwrDecreaseFor2Chain
, 0));
1389 if (IS_CHAN_HT40(chan
))
1391 else if (IS_CHAN_HT20(chan
))
1394 if (AR_SREV_9280_10_OR_LATER(ah
))
1395 regulatory
->max_power_level
=
1396 ratesArray
[i
] + AR5416_PWR_TABLE_OFFSET_DB
* 2;
1398 regulatory
->max_power_level
= ratesArray
[i
];
1400 switch(ar5416_get_ntxchains(ah
->txchainmask
)) {
1404 regulatory
->max_power_level
+= INCREASE_MAXPOW_BY_TWO_CHAIN
;
1407 regulatory
->max_power_level
+= INCREASE_MAXPOW_BY_THREE_CHAIN
;
1410 ath_print(ath9k_hw_common(ah
), ATH_DBG_EEPROM
,
1411 "Invalid chainmask configuration\n");
1416 static u8
ath9k_hw_def_get_num_ant_config(struct ath_hw
*ah
,
1417 enum ieee80211_band freq_band
)
1419 struct ar5416_eeprom_def
*eep
= &ah
->eeprom
.def
;
1420 struct modal_eep_header
*pModal
=
1421 &(eep
->modalHeader
[ATH9K_HAL_FREQ_BAND_2GHZ
== freq_band
]);
1422 struct base_eep_header
*pBase
= &eep
->baseEepHeader
;
1427 if (pBase
->version
>= 0x0E0D)
1428 if (pModal
->useAnt1
)
1429 num_ant_config
+= 1;
1431 return num_ant_config
;
1434 static u16
ath9k_hw_def_get_eeprom_antenna_cfg(struct ath_hw
*ah
,
1435 struct ath9k_channel
*chan
)
1437 struct ar5416_eeprom_def
*eep
= &ah
->eeprom
.def
;
1438 struct modal_eep_header
*pModal
=
1439 &(eep
->modalHeader
[IS_CHAN_2GHZ(chan
)]);
1441 return pModal
->antCtrlCommon
& 0xFFFF;
1444 static u16
ath9k_hw_def_get_spur_channel(struct ath_hw
*ah
, u16 i
, bool is2GHz
)
1446 #define EEP_DEF_SPURCHAN \
1447 (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan)
1448 struct ath_common
*common
= ath9k_hw_common(ah
);
1450 u16 spur_val
= AR_NO_SPUR
;
1452 ath_print(common
, ATH_DBG_ANI
,
1453 "Getting spur idx %d is2Ghz. %d val %x\n",
1454 i
, is2GHz
, ah
->config
.spurchans
[i
][is2GHz
]);
1456 switch (ah
->config
.spurmode
) {
1459 case SPUR_ENABLE_IOCTL
:
1460 spur_val
= ah
->config
.spurchans
[i
][is2GHz
];
1461 ath_print(common
, ATH_DBG_ANI
,
1462 "Getting spur val from new loc. %d\n", spur_val
);
1464 case SPUR_ENABLE_EEPROM
:
1465 spur_val
= EEP_DEF_SPURCHAN
;
1471 #undef EEP_DEF_SPURCHAN
1474 const struct eeprom_ops eep_def_ops
= {
1475 .check_eeprom
= ath9k_hw_def_check_eeprom
,
1476 .get_eeprom
= ath9k_hw_def_get_eeprom
,
1477 .fill_eeprom
= ath9k_hw_def_fill_eeprom
,
1478 .get_eeprom_ver
= ath9k_hw_def_get_eeprom_ver
,
1479 .get_eeprom_rev
= ath9k_hw_def_get_eeprom_rev
,
1480 .get_num_ant_config
= ath9k_hw_def_get_num_ant_config
,
1481 .get_eeprom_antenna_cfg
= ath9k_hw_def_get_eeprom_antenna_cfg
,
1482 .set_board_values
= ath9k_hw_def_set_board_values
,
1483 .set_addac
= ath9k_hw_def_set_addac
,
1484 .set_txpower
= ath9k_hw_def_set_txpower
,
1485 .get_spur_channel
= ath9k_hw_def_get_spur_channel